intel_dp.c revision f769cd247d2be5af377adf82882eddd1dce183c4
1/* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28#include <linux/i2c.h> 29#include <linux/slab.h> 30#include <linux/export.h> 31#include <linux/notifier.h> 32#include <linux/reboot.h> 33#include <drm/drmP.h> 34#include <drm/drm_crtc.h> 35#include <drm/drm_crtc_helper.h> 36#include <drm/drm_edid.h> 37#include "intel_drv.h" 38#include <drm/i915_drm.h> 39#include "i915_drv.h" 40 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000) 42 43struct dp_link_dpll { 44 int link_bw; 45 struct dpll dpll; 46}; 47 48static const struct dp_link_dpll gen4_dpll[] = { 49 { DP_LINK_BW_1_62, 50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, 51 { DP_LINK_BW_2_7, 52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } 53}; 54 55static const struct dp_link_dpll pch_dpll[] = { 56 { DP_LINK_BW_1_62, 57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, 58 { DP_LINK_BW_2_7, 59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } 60}; 61 62static const struct dp_link_dpll vlv_dpll[] = { 63 { DP_LINK_BW_1_62, 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, 65 { DP_LINK_BW_2_7, 66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } 67}; 68 69/* 70 * CHV supports eDP 1.4 that have more link rates. 71 * Below only provides the fixed rate but exclude variable rate. 72 */ 73static const struct dp_link_dpll chv_dpll[] = { 74 /* 75 * CHV requires to program fractional division for m2. 76 * m2 is stored in fixed point format using formula below 77 * (m2_int << 22) | m2_fraction 78 */ 79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */ 80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, 81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */ 82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, 83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */ 84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } 85}; 86 87/** 88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 89 * @intel_dp: DP struct 90 * 91 * If a CPU or PCH DP output is attached to an eDP panel, this function 92 * will return true, and false otherwise. 93 */ 94static bool is_edp(struct intel_dp *intel_dp) 95{ 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 97 98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP; 99} 100 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) 102{ 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 104 105 return intel_dig_port->base.base.dev; 106} 107 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector) 109{ 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base); 111} 112 113static void intel_dp_link_down(struct intel_dp *intel_dp); 114static bool _edp_panel_vdd_on(struct intel_dp *intel_dp); 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); 116 117int 118intel_dp_max_link_bw(struct intel_dp *intel_dp) 119{ 120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; 121 struct drm_device *dev = intel_dp->attached_connector->base.dev; 122 123 switch (max_link_bw) { 124 case DP_LINK_BW_1_62: 125 case DP_LINK_BW_2_7: 126 break; 127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ 128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || 129 INTEL_INFO(dev)->gen >= 8) && 130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12) 131 max_link_bw = DP_LINK_BW_5_4; 132 else 133 max_link_bw = DP_LINK_BW_2_7; 134 break; 135 default: 136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", 137 max_link_bw); 138 max_link_bw = DP_LINK_BW_1_62; 139 break; 140 } 141 return max_link_bw; 142} 143 144static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) 145{ 146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 147 struct drm_device *dev = intel_dig_port->base.base.dev; 148 u8 source_max, sink_max; 149 150 source_max = 4; 151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A && 152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0) 153 source_max = 2; 154 155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd); 156 157 return min(source_max, sink_max); 158} 159 160/* 161 * The units on the numbers in the next two are... bizarre. Examples will 162 * make it clearer; this one parallels an example in the eDP spec. 163 * 164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: 165 * 166 * 270000 * 1 * 8 / 10 == 216000 167 * 168 * The actual data capacity of that configuration is 2.16Gbit/s, so the 169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - 170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be 171 * 119000. At 18bpp that's 2142000 kilobits per second. 172 * 173 * Thus the strange-looking division by 10 in intel_dp_link_required, to 174 * get the result in decakilobits instead of kilobits. 175 */ 176 177static int 178intel_dp_link_required(int pixel_clock, int bpp) 179{ 180 return (pixel_clock * bpp + 9) / 10; 181} 182 183static int 184intel_dp_max_data_rate(int max_link_clock, int max_lanes) 185{ 186 return (max_link_clock * max_lanes * 8) / 10; 187} 188 189static enum drm_mode_status 190intel_dp_mode_valid(struct drm_connector *connector, 191 struct drm_display_mode *mode) 192{ 193 struct intel_dp *intel_dp = intel_attached_dp(connector); 194 struct intel_connector *intel_connector = to_intel_connector(connector); 195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 196 int target_clock = mode->clock; 197 int max_rate, mode_rate, max_lanes, max_link_clock; 198 199 if (is_edp(intel_dp) && fixed_mode) { 200 if (mode->hdisplay > fixed_mode->hdisplay) 201 return MODE_PANEL; 202 203 if (mode->vdisplay > fixed_mode->vdisplay) 204 return MODE_PANEL; 205 206 target_clock = fixed_mode->clock; 207 } 208 209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); 210 max_lanes = intel_dp_max_lane_count(intel_dp); 211 212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 213 mode_rate = intel_dp_link_required(target_clock, 18); 214 215 if (mode_rate > max_rate) 216 return MODE_CLOCK_HIGH; 217 218 if (mode->clock < 10000) 219 return MODE_CLOCK_LOW; 220 221 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 222 return MODE_H_ILLEGAL; 223 224 return MODE_OK; 225} 226 227static uint32_t 228pack_aux(uint8_t *src, int src_bytes) 229{ 230 int i; 231 uint32_t v = 0; 232 233 if (src_bytes > 4) 234 src_bytes = 4; 235 for (i = 0; i < src_bytes; i++) 236 v |= ((uint32_t) src[i]) << ((3-i) * 8); 237 return v; 238} 239 240static void 241unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) 242{ 243 int i; 244 if (dst_bytes > 4) 245 dst_bytes = 4; 246 for (i = 0; i < dst_bytes; i++) 247 dst[i] = src >> ((3-i) * 8); 248} 249 250/* hrawclock is 1/4 the FSB frequency */ 251static int 252intel_hrawclk(struct drm_device *dev) 253{ 254 struct drm_i915_private *dev_priv = dev->dev_private; 255 uint32_t clkcfg; 256 257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ 258 if (IS_VALLEYVIEW(dev)) 259 return 200; 260 261 clkcfg = I915_READ(CLKCFG); 262 switch (clkcfg & CLKCFG_FSB_MASK) { 263 case CLKCFG_FSB_400: 264 return 100; 265 case CLKCFG_FSB_533: 266 return 133; 267 case CLKCFG_FSB_667: 268 return 166; 269 case CLKCFG_FSB_800: 270 return 200; 271 case CLKCFG_FSB_1067: 272 return 266; 273 case CLKCFG_FSB_1333: 274 return 333; 275 /* these two are just a guess; one of them might be right */ 276 case CLKCFG_FSB_1600: 277 case CLKCFG_FSB_1600_ALT: 278 return 400; 279 default: 280 return 133; 281 } 282} 283 284static void 285intel_dp_init_panel_power_sequencer(struct drm_device *dev, 286 struct intel_dp *intel_dp, 287 struct edp_power_seq *out); 288static void 289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 290 struct intel_dp *intel_dp, 291 struct edp_power_seq *out); 292 293static enum pipe 294vlv_power_sequencer_pipe(struct intel_dp *intel_dp) 295{ 296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 297 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 298 struct drm_device *dev = intel_dig_port->base.base.dev; 299 struct drm_i915_private *dev_priv = dev->dev_private; 300 enum port port = intel_dig_port->port; 301 enum pipe pipe; 302 303 /* modeset should have pipe */ 304 if (crtc) 305 return to_intel_crtc(crtc)->pipe; 306 307 /* init time, try to find a pipe with this port selected */ 308 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { 309 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & 310 PANEL_PORT_SELECT_MASK; 311 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B) 312 return pipe; 313 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C) 314 return pipe; 315 } 316 317 /* shrug */ 318 return PIPE_A; 319} 320 321static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) 322{ 323 struct drm_device *dev = intel_dp_to_dev(intel_dp); 324 325 if (HAS_PCH_SPLIT(dev)) 326 return PCH_PP_CONTROL; 327 else 328 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); 329} 330 331static u32 _pp_stat_reg(struct intel_dp *intel_dp) 332{ 333 struct drm_device *dev = intel_dp_to_dev(intel_dp); 334 335 if (HAS_PCH_SPLIT(dev)) 336 return PCH_PP_STATUS; 337 else 338 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); 339} 340 341/* Reboot notifier handler to shutdown panel power to guarantee T12 timing 342 This function only applicable when panel PM state is not to be tracked */ 343static int edp_notify_handler(struct notifier_block *this, unsigned long code, 344 void *unused) 345{ 346 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), 347 edp_notifier); 348 struct drm_device *dev = intel_dp_to_dev(intel_dp); 349 struct drm_i915_private *dev_priv = dev->dev_private; 350 u32 pp_div; 351 u32 pp_ctrl_reg, pp_div_reg; 352 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); 353 354 if (!is_edp(intel_dp) || code != SYS_RESTART) 355 return 0; 356 357 if (IS_VALLEYVIEW(dev)) { 358 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); 359 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 360 pp_div = I915_READ(pp_div_reg); 361 pp_div &= PP_REFERENCE_DIVIDER_MASK; 362 363 /* 0x1F write to PP_DIV_REG sets max cycle delay */ 364 I915_WRITE(pp_div_reg, pp_div | 0x1F); 365 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); 366 msleep(intel_dp->panel_power_cycle_delay); 367 } 368 369 return 0; 370} 371 372static bool edp_have_panel_power(struct intel_dp *intel_dp) 373{ 374 struct drm_device *dev = intel_dp_to_dev(intel_dp); 375 struct drm_i915_private *dev_priv = dev->dev_private; 376 377 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; 378} 379 380static bool edp_have_panel_vdd(struct intel_dp *intel_dp) 381{ 382 struct drm_device *dev = intel_dp_to_dev(intel_dp); 383 struct drm_i915_private *dev_priv = dev->dev_private; 384 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 385 struct intel_encoder *intel_encoder = &intel_dig_port->base; 386 enum intel_display_power_domain power_domain; 387 388 power_domain = intel_display_port_power_domain(intel_encoder); 389 return intel_display_power_enabled(dev_priv, power_domain) && 390 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0; 391} 392 393static void 394intel_dp_check_edp(struct intel_dp *intel_dp) 395{ 396 struct drm_device *dev = intel_dp_to_dev(intel_dp); 397 struct drm_i915_private *dev_priv = dev->dev_private; 398 399 if (!is_edp(intel_dp)) 400 return; 401 402 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { 403 WARN(1, "eDP powered off while attempting aux channel communication.\n"); 404 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", 405 I915_READ(_pp_stat_reg(intel_dp)), 406 I915_READ(_pp_ctrl_reg(intel_dp))); 407 } 408} 409 410static uint32_t 411intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) 412{ 413 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 414 struct drm_device *dev = intel_dig_port->base.base.dev; 415 struct drm_i915_private *dev_priv = dev->dev_private; 416 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; 417 uint32_t status; 418 bool done; 419 420#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) 421 if (has_aux_irq) 422 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 423 msecs_to_jiffies_timeout(10)); 424 else 425 done = wait_for_atomic(C, 10) == 0; 426 if (!done) 427 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", 428 has_aux_irq); 429#undef C 430 431 return status; 432} 433 434static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 435{ 436 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 437 struct drm_device *dev = intel_dig_port->base.base.dev; 438 439 /* 440 * The clock divider is based off the hrawclk, and would like to run at 441 * 2MHz. So, take the hrawclk value and divide by 2 and use that 442 */ 443 return index ? 0 : intel_hrawclk(dev) / 2; 444} 445 446static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 447{ 448 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 449 struct drm_device *dev = intel_dig_port->base.base.dev; 450 451 if (index) 452 return 0; 453 454 if (intel_dig_port->port == PORT_A) { 455 if (IS_GEN6(dev) || IS_GEN7(dev)) 456 return 200; /* SNB & IVB eDP input clock at 400Mhz */ 457 else 458 return 225; /* eDP input clock at 450Mhz */ 459 } else { 460 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); 461 } 462} 463 464static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 465{ 466 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 467 struct drm_device *dev = intel_dig_port->base.base.dev; 468 struct drm_i915_private *dev_priv = dev->dev_private; 469 470 if (intel_dig_port->port == PORT_A) { 471 if (index) 472 return 0; 473 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000); 474 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { 475 /* Workaround for non-ULT HSW */ 476 switch (index) { 477 case 0: return 63; 478 case 1: return 72; 479 default: return 0; 480 } 481 } else { 482 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); 483 } 484} 485 486static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 487{ 488 return index ? 0 : 100; 489} 490 491static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, 492 bool has_aux_irq, 493 int send_bytes, 494 uint32_t aux_clock_divider) 495{ 496 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 497 struct drm_device *dev = intel_dig_port->base.base.dev; 498 uint32_t precharge, timeout; 499 500 if (IS_GEN6(dev)) 501 precharge = 3; 502 else 503 precharge = 5; 504 505 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL) 506 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 507 else 508 timeout = DP_AUX_CH_CTL_TIME_OUT_400us; 509 510 return DP_AUX_CH_CTL_SEND_BUSY | 511 DP_AUX_CH_CTL_DONE | 512 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | 513 DP_AUX_CH_CTL_TIME_OUT_ERROR | 514 timeout | 515 DP_AUX_CH_CTL_RECEIVE_ERROR | 516 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 517 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 518 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); 519} 520 521static int 522intel_dp_aux_ch(struct intel_dp *intel_dp, 523 uint8_t *send, int send_bytes, 524 uint8_t *recv, int recv_size) 525{ 526 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 527 struct drm_device *dev = intel_dig_port->base.base.dev; 528 struct drm_i915_private *dev_priv = dev->dev_private; 529 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; 530 uint32_t ch_data = ch_ctl + 4; 531 uint32_t aux_clock_divider; 532 int i, ret, recv_bytes; 533 uint32_t status; 534 int try, clock = 0; 535 bool has_aux_irq = HAS_AUX_IRQ(dev); 536 bool vdd; 537 538 vdd = _edp_panel_vdd_on(intel_dp); 539 540 /* dp aux is extremely sensitive to irq latency, hence request the 541 * lowest possible wakeup latency and so prevent the cpu from going into 542 * deep sleep states. 543 */ 544 pm_qos_update_request(&dev_priv->pm_qos, 0); 545 546 intel_dp_check_edp(intel_dp); 547 548 intel_aux_display_runtime_get(dev_priv); 549 550 /* Try to wait for any previous AUX channel activity */ 551 for (try = 0; try < 3; try++) { 552 status = I915_READ_NOTRACE(ch_ctl); 553 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 554 break; 555 msleep(1); 556 } 557 558 if (try == 3) { 559 WARN(1, "dp_aux_ch not started status 0x%08x\n", 560 I915_READ(ch_ctl)); 561 ret = -EBUSY; 562 goto out; 563 } 564 565 /* Only 5 data registers! */ 566 if (WARN_ON(send_bytes > 20 || recv_size > 20)) { 567 ret = -E2BIG; 568 goto out; 569 } 570 571 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { 572 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, 573 has_aux_irq, 574 send_bytes, 575 aux_clock_divider); 576 577 /* Must try at least 3 times according to DP spec */ 578 for (try = 0; try < 5; try++) { 579 /* Load the send data into the aux channel data registers */ 580 for (i = 0; i < send_bytes; i += 4) 581 I915_WRITE(ch_data + i, 582 pack_aux(send + i, send_bytes - i)); 583 584 /* Send the command and wait for it to complete */ 585 I915_WRITE(ch_ctl, send_ctl); 586 587 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); 588 589 /* Clear done status and any errors */ 590 I915_WRITE(ch_ctl, 591 status | 592 DP_AUX_CH_CTL_DONE | 593 DP_AUX_CH_CTL_TIME_OUT_ERROR | 594 DP_AUX_CH_CTL_RECEIVE_ERROR); 595 596 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | 597 DP_AUX_CH_CTL_RECEIVE_ERROR)) 598 continue; 599 if (status & DP_AUX_CH_CTL_DONE) 600 break; 601 } 602 if (status & DP_AUX_CH_CTL_DONE) 603 break; 604 } 605 606 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 607 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 608 ret = -EBUSY; 609 goto out; 610 } 611 612 /* Check for timeout or receive error. 613 * Timeouts occur when the sink is not connected 614 */ 615 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 616 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 617 ret = -EIO; 618 goto out; 619 } 620 621 /* Timeouts occur when the device isn't connected, so they're 622 * "normal" -- don't fill the kernel log with these */ 623 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 624 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 625 ret = -ETIMEDOUT; 626 goto out; 627 } 628 629 /* Unload any bytes sent back from the other side */ 630 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 631 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 632 if (recv_bytes > recv_size) 633 recv_bytes = recv_size; 634 635 for (i = 0; i < recv_bytes; i += 4) 636 unpack_aux(I915_READ(ch_data + i), 637 recv + i, recv_bytes - i); 638 639 ret = recv_bytes; 640out: 641 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); 642 intel_aux_display_runtime_put(dev_priv); 643 644 if (vdd) 645 edp_panel_vdd_off(intel_dp, false); 646 647 return ret; 648} 649 650#define BARE_ADDRESS_SIZE 3 651#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 652static ssize_t 653intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 654{ 655 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); 656 uint8_t txbuf[20], rxbuf[20]; 657 size_t txsize, rxsize; 658 int ret; 659 660 txbuf[0] = msg->request << 4; 661 txbuf[1] = msg->address >> 8; 662 txbuf[2] = msg->address & 0xff; 663 txbuf[3] = msg->size - 1; 664 665 switch (msg->request & ~DP_AUX_I2C_MOT) { 666 case DP_AUX_NATIVE_WRITE: 667 case DP_AUX_I2C_WRITE: 668 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; 669 rxsize = 1; 670 671 if (WARN_ON(txsize > 20)) 672 return -E2BIG; 673 674 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); 675 676 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); 677 if (ret > 0) { 678 msg->reply = rxbuf[0] >> 4; 679 680 /* Return payload size. */ 681 ret = msg->size; 682 } 683 break; 684 685 case DP_AUX_NATIVE_READ: 686 case DP_AUX_I2C_READ: 687 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; 688 rxsize = msg->size + 1; 689 690 if (WARN_ON(rxsize > 20)) 691 return -E2BIG; 692 693 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); 694 if (ret > 0) { 695 msg->reply = rxbuf[0] >> 4; 696 /* 697 * Assume happy day, and copy the data. The caller is 698 * expected to check msg->reply before touching it. 699 * 700 * Return payload size. 701 */ 702 ret--; 703 memcpy(msg->buffer, rxbuf + 1, ret); 704 } 705 break; 706 707 default: 708 ret = -EINVAL; 709 break; 710 } 711 712 return ret; 713} 714 715static void 716intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) 717{ 718 struct drm_device *dev = intel_dp_to_dev(intel_dp); 719 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 720 enum port port = intel_dig_port->port; 721 const char *name = NULL; 722 int ret; 723 724 switch (port) { 725 case PORT_A: 726 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; 727 name = "DPDDC-A"; 728 break; 729 case PORT_B: 730 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; 731 name = "DPDDC-B"; 732 break; 733 case PORT_C: 734 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; 735 name = "DPDDC-C"; 736 break; 737 case PORT_D: 738 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; 739 name = "DPDDC-D"; 740 break; 741 default: 742 BUG(); 743 } 744 745 if (!HAS_DDI(dev)) 746 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; 747 748 intel_dp->aux.name = name; 749 intel_dp->aux.dev = dev->dev; 750 intel_dp->aux.transfer = intel_dp_aux_transfer; 751 752 DRM_DEBUG_KMS("registering %s bus for %s\n", name, 753 connector->base.kdev->kobj.name); 754 755 ret = drm_dp_aux_register(&intel_dp->aux); 756 if (ret < 0) { 757 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n", 758 name, ret); 759 return; 760 } 761 762 ret = sysfs_create_link(&connector->base.kdev->kobj, 763 &intel_dp->aux.ddc.dev.kobj, 764 intel_dp->aux.ddc.dev.kobj.name); 765 if (ret < 0) { 766 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret); 767 drm_dp_aux_unregister(&intel_dp->aux); 768 } 769} 770 771static void 772intel_dp_connector_unregister(struct intel_connector *intel_connector) 773{ 774 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); 775 776 if (!intel_connector->mst_port) 777 sysfs_remove_link(&intel_connector->base.kdev->kobj, 778 intel_dp->aux.ddc.dev.kobj.name); 779 intel_connector_unregister(intel_connector); 780} 781 782static void 783hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw) 784{ 785 switch (link_bw) { 786 case DP_LINK_BW_1_62: 787 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; 788 break; 789 case DP_LINK_BW_2_7: 790 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; 791 break; 792 case DP_LINK_BW_5_4: 793 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; 794 break; 795 } 796} 797 798static void 799intel_dp_set_clock(struct intel_encoder *encoder, 800 struct intel_crtc_config *pipe_config, int link_bw) 801{ 802 struct drm_device *dev = encoder->base.dev; 803 const struct dp_link_dpll *divisor = NULL; 804 int i, count = 0; 805 806 if (IS_G4X(dev)) { 807 divisor = gen4_dpll; 808 count = ARRAY_SIZE(gen4_dpll); 809 } else if (HAS_PCH_SPLIT(dev)) { 810 divisor = pch_dpll; 811 count = ARRAY_SIZE(pch_dpll); 812 } else if (IS_CHERRYVIEW(dev)) { 813 divisor = chv_dpll; 814 count = ARRAY_SIZE(chv_dpll); 815 } else if (IS_VALLEYVIEW(dev)) { 816 divisor = vlv_dpll; 817 count = ARRAY_SIZE(vlv_dpll); 818 } 819 820 if (divisor && count) { 821 for (i = 0; i < count; i++) { 822 if (link_bw == divisor[i].link_bw) { 823 pipe_config->dpll = divisor[i].dpll; 824 pipe_config->clock_set = true; 825 break; 826 } 827 } 828 } 829} 830 831bool 832intel_dp_compute_config(struct intel_encoder *encoder, 833 struct intel_crtc_config *pipe_config) 834{ 835 struct drm_device *dev = encoder->base.dev; 836 struct drm_i915_private *dev_priv = dev->dev_private; 837 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 838 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 839 enum port port = dp_to_dig_port(intel_dp)->port; 840 struct intel_crtc *intel_crtc = encoder->new_crtc; 841 struct intel_connector *intel_connector = intel_dp->attached_connector; 842 int lane_count, clock; 843 int min_lane_count = 1; 844 int max_lane_count = intel_dp_max_lane_count(intel_dp); 845 /* Conveniently, the link BW constants become indices with a shift...*/ 846 int min_clock = 0; 847 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; 848 int bpp, mode_rate; 849 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; 850 int link_avail, link_clock; 851 852 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) 853 pipe_config->has_pch_encoder = true; 854 855 pipe_config->has_dp_encoder = true; 856 pipe_config->has_drrs = false; 857 pipe_config->has_audio = intel_dp->has_audio; 858 859 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 860 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 861 adjusted_mode); 862 if (!HAS_PCH_SPLIT(dev)) 863 intel_gmch_panel_fitting(intel_crtc, pipe_config, 864 intel_connector->panel.fitting_mode); 865 else 866 intel_pch_panel_fitting(intel_crtc, pipe_config, 867 intel_connector->panel.fitting_mode); 868 } 869 870 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 871 return false; 872 873 DRM_DEBUG_KMS("DP link computation with max lane count %i " 874 "max bw %02x pixel clock %iKHz\n", 875 max_lane_count, bws[max_clock], 876 adjusted_mode->crtc_clock); 877 878 /* Walk through all bpp values. Luckily they're all nicely spaced with 2 879 * bpc in between. */ 880 bpp = pipe_config->pipe_bpp; 881 if (is_edp(intel_dp)) { 882 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) { 883 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", 884 dev_priv->vbt.edp_bpp); 885 bpp = dev_priv->vbt.edp_bpp; 886 } 887 888 if (IS_BROADWELL(dev)) { 889 /* Yes, it's an ugly hack. */ 890 min_lane_count = max_lane_count; 891 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n", 892 min_lane_count); 893 } else if (dev_priv->vbt.edp_lanes) { 894 min_lane_count = min(dev_priv->vbt.edp_lanes, 895 max_lane_count); 896 DRM_DEBUG_KMS("using min %u lanes per VBT\n", 897 min_lane_count); 898 } 899 900 if (dev_priv->vbt.edp_rate) { 901 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock); 902 DRM_DEBUG_KMS("using min %02x link bw per VBT\n", 903 bws[min_clock]); 904 } 905 } 906 907 for (; bpp >= 6*3; bpp -= 2*3) { 908 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, 909 bpp); 910 911 for (clock = min_clock; clock <= max_clock; clock++) { 912 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) { 913 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); 914 link_avail = intel_dp_max_data_rate(link_clock, 915 lane_count); 916 917 if (mode_rate <= link_avail) { 918 goto found; 919 } 920 } 921 } 922 } 923 924 return false; 925 926found: 927 if (intel_dp->color_range_auto) { 928 /* 929 * See: 930 * CEA-861-E - 5.1 Default Encoding Parameters 931 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 932 */ 933 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) 934 intel_dp->color_range = DP_COLOR_RANGE_16_235; 935 else 936 intel_dp->color_range = 0; 937 } 938 939 if (intel_dp->color_range) 940 pipe_config->limited_color_range = true; 941 942 intel_dp->link_bw = bws[clock]; 943 intel_dp->lane_count = lane_count; 944 pipe_config->pipe_bpp = bpp; 945 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); 946 947 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", 948 intel_dp->link_bw, intel_dp->lane_count, 949 pipe_config->port_clock, bpp); 950 DRM_DEBUG_KMS("DP link bw required %i available %i\n", 951 mode_rate, link_avail); 952 953 intel_link_compute_m_n(bpp, lane_count, 954 adjusted_mode->crtc_clock, 955 pipe_config->port_clock, 956 &pipe_config->dp_m_n); 957 958 if (intel_connector->panel.downclock_mode != NULL && 959 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) { 960 pipe_config->has_drrs = true; 961 intel_link_compute_m_n(bpp, lane_count, 962 intel_connector->panel.downclock_mode->clock, 963 pipe_config->port_clock, 964 &pipe_config->dp_m2_n2); 965 } 966 967 if (HAS_DDI(dev)) 968 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw); 969 else 970 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); 971 972 return true; 973} 974 975static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) 976{ 977 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 978 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 979 struct drm_device *dev = crtc->base.dev; 980 struct drm_i915_private *dev_priv = dev->dev_private; 981 u32 dpa_ctl; 982 983 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock); 984 dpa_ctl = I915_READ(DP_A); 985 dpa_ctl &= ~DP_PLL_FREQ_MASK; 986 987 if (crtc->config.port_clock == 162000) { 988 /* For a long time we've carried around a ILK-DevA w/a for the 989 * 160MHz clock. If we're really unlucky, it's still required. 990 */ 991 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); 992 dpa_ctl |= DP_PLL_FREQ_160MHZ; 993 intel_dp->DP |= DP_PLL_FREQ_160MHZ; 994 } else { 995 dpa_ctl |= DP_PLL_FREQ_270MHZ; 996 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 997 } 998 999 I915_WRITE(DP_A, dpa_ctl); 1000 1001 POSTING_READ(DP_A); 1002 udelay(500); 1003} 1004 1005static void intel_dp_prepare(struct intel_encoder *encoder) 1006{ 1007 struct drm_device *dev = encoder->base.dev; 1008 struct drm_i915_private *dev_priv = dev->dev_private; 1009 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1010 enum port port = dp_to_dig_port(intel_dp)->port; 1011 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1012 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; 1013 1014 /* 1015 * There are four kinds of DP registers: 1016 * 1017 * IBX PCH 1018 * SNB CPU 1019 * IVB CPU 1020 * CPT PCH 1021 * 1022 * IBX PCH and CPU are the same for almost everything, 1023 * except that the CPU DP PLL is configured in this 1024 * register 1025 * 1026 * CPT PCH is quite different, having many bits moved 1027 * to the TRANS_DP_CTL register instead. That 1028 * configuration happens (oddly) in ironlake_pch_enable 1029 */ 1030 1031 /* Preserve the BIOS-computed detected bit. This is 1032 * supposed to be read-only. 1033 */ 1034 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; 1035 1036 /* Handle DP bits in common between all three register formats */ 1037 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 1038 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); 1039 1040 if (crtc->config.has_audio) { 1041 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", 1042 pipe_name(crtc->pipe)); 1043 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 1044 intel_write_eld(&encoder->base, adjusted_mode); 1045 } 1046 1047 /* Split out the IBX/CPU vs CPT settings */ 1048 1049 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { 1050 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1051 intel_dp->DP |= DP_SYNC_HS_HIGH; 1052 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 1053 intel_dp->DP |= DP_SYNC_VS_HIGH; 1054 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 1055 1056 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 1057 intel_dp->DP |= DP_ENHANCED_FRAMING; 1058 1059 intel_dp->DP |= crtc->pipe << 29; 1060 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { 1061 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) 1062 intel_dp->DP |= intel_dp->color_range; 1063 1064 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1065 intel_dp->DP |= DP_SYNC_HS_HIGH; 1066 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 1067 intel_dp->DP |= DP_SYNC_VS_HIGH; 1068 intel_dp->DP |= DP_LINK_TRAIN_OFF; 1069 1070 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 1071 intel_dp->DP |= DP_ENHANCED_FRAMING; 1072 1073 if (!IS_CHERRYVIEW(dev)) { 1074 if (crtc->pipe == 1) 1075 intel_dp->DP |= DP_PIPEB_SELECT; 1076 } else { 1077 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); 1078 } 1079 } else { 1080 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 1081 } 1082} 1083 1084#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 1085#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) 1086 1087#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) 1088#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) 1089 1090#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) 1091#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 1092 1093static void wait_panel_status(struct intel_dp *intel_dp, 1094 u32 mask, 1095 u32 value) 1096{ 1097 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1098 struct drm_i915_private *dev_priv = dev->dev_private; 1099 u32 pp_stat_reg, pp_ctrl_reg; 1100 1101 pp_stat_reg = _pp_stat_reg(intel_dp); 1102 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1103 1104 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", 1105 mask, value, 1106 I915_READ(pp_stat_reg), 1107 I915_READ(pp_ctrl_reg)); 1108 1109 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { 1110 DRM_ERROR("Panel status timeout: status %08x control %08x\n", 1111 I915_READ(pp_stat_reg), 1112 I915_READ(pp_ctrl_reg)); 1113 } 1114 1115 DRM_DEBUG_KMS("Wait complete\n"); 1116} 1117 1118static void wait_panel_on(struct intel_dp *intel_dp) 1119{ 1120 DRM_DEBUG_KMS("Wait for panel power on\n"); 1121 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); 1122} 1123 1124static void wait_panel_off(struct intel_dp *intel_dp) 1125{ 1126 DRM_DEBUG_KMS("Wait for panel power off time\n"); 1127 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); 1128} 1129 1130static void wait_panel_power_cycle(struct intel_dp *intel_dp) 1131{ 1132 DRM_DEBUG_KMS("Wait for panel power cycle\n"); 1133 1134 /* When we disable the VDD override bit last we have to do the manual 1135 * wait. */ 1136 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle, 1137 intel_dp->panel_power_cycle_delay); 1138 1139 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); 1140} 1141 1142static void wait_backlight_on(struct intel_dp *intel_dp) 1143{ 1144 wait_remaining_ms_from_jiffies(intel_dp->last_power_on, 1145 intel_dp->backlight_on_delay); 1146} 1147 1148static void edp_wait_backlight_off(struct intel_dp *intel_dp) 1149{ 1150 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, 1151 intel_dp->backlight_off_delay); 1152} 1153 1154/* Read the current pp_control value, unlocking the register if it 1155 * is locked 1156 */ 1157 1158static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) 1159{ 1160 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1161 struct drm_i915_private *dev_priv = dev->dev_private; 1162 u32 control; 1163 1164 control = I915_READ(_pp_ctrl_reg(intel_dp)); 1165 control &= ~PANEL_UNLOCK_MASK; 1166 control |= PANEL_UNLOCK_REGS; 1167 return control; 1168} 1169 1170static bool _edp_panel_vdd_on(struct intel_dp *intel_dp) 1171{ 1172 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1173 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1174 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1175 struct drm_i915_private *dev_priv = dev->dev_private; 1176 enum intel_display_power_domain power_domain; 1177 u32 pp; 1178 u32 pp_stat_reg, pp_ctrl_reg; 1179 bool need_to_disable = !intel_dp->want_panel_vdd; 1180 1181 if (!is_edp(intel_dp)) 1182 return false; 1183 1184 intel_dp->want_panel_vdd = true; 1185 1186 if (edp_have_panel_vdd(intel_dp)) 1187 return need_to_disable; 1188 1189 power_domain = intel_display_port_power_domain(intel_encoder); 1190 intel_display_power_get(dev_priv, power_domain); 1191 1192 DRM_DEBUG_KMS("Turning eDP VDD on\n"); 1193 1194 if (!edp_have_panel_power(intel_dp)) 1195 wait_panel_power_cycle(intel_dp); 1196 1197 pp = ironlake_get_pp_control(intel_dp); 1198 pp |= EDP_FORCE_VDD; 1199 1200 pp_stat_reg = _pp_stat_reg(intel_dp); 1201 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1202 1203 I915_WRITE(pp_ctrl_reg, pp); 1204 POSTING_READ(pp_ctrl_reg); 1205 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1206 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1207 /* 1208 * If the panel wasn't on, delay before accessing aux channel 1209 */ 1210 if (!edp_have_panel_power(intel_dp)) { 1211 DRM_DEBUG_KMS("eDP was not running\n"); 1212 msleep(intel_dp->panel_power_up_delay); 1213 } 1214 1215 return need_to_disable; 1216} 1217 1218void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) 1219{ 1220 if (is_edp(intel_dp)) { 1221 bool vdd = _edp_panel_vdd_on(intel_dp); 1222 1223 WARN(!vdd, "eDP VDD already requested on\n"); 1224 } 1225} 1226 1227static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) 1228{ 1229 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1230 struct drm_i915_private *dev_priv = dev->dev_private; 1231 u32 pp; 1232 u32 pp_stat_reg, pp_ctrl_reg; 1233 1234 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 1235 1236 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) { 1237 struct intel_digital_port *intel_dig_port = 1238 dp_to_dig_port(intel_dp); 1239 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1240 enum intel_display_power_domain power_domain; 1241 1242 DRM_DEBUG_KMS("Turning eDP VDD off\n"); 1243 1244 pp = ironlake_get_pp_control(intel_dp); 1245 pp &= ~EDP_FORCE_VDD; 1246 1247 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1248 pp_stat_reg = _pp_stat_reg(intel_dp); 1249 1250 I915_WRITE(pp_ctrl_reg, pp); 1251 POSTING_READ(pp_ctrl_reg); 1252 1253 /* Make sure sequencer is idle before allowing subsequent activity */ 1254 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1255 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1256 1257 if ((pp & POWER_TARGET_ON) == 0) 1258 intel_dp->last_power_cycle = jiffies; 1259 1260 power_domain = intel_display_port_power_domain(intel_encoder); 1261 intel_display_power_put(dev_priv, power_domain); 1262 } 1263} 1264 1265static void edp_panel_vdd_work(struct work_struct *__work) 1266{ 1267 struct intel_dp *intel_dp = container_of(to_delayed_work(__work), 1268 struct intel_dp, panel_vdd_work); 1269 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1270 1271 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1272 edp_panel_vdd_off_sync(intel_dp); 1273 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1274} 1275 1276static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) 1277{ 1278 unsigned long delay; 1279 1280 /* 1281 * Queue the timer to fire a long time from now (relative to the power 1282 * down delay) to keep the panel power up across a sequence of 1283 * operations. 1284 */ 1285 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); 1286 schedule_delayed_work(&intel_dp->panel_vdd_work, delay); 1287} 1288 1289static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) 1290{ 1291 if (!is_edp(intel_dp)) 1292 return; 1293 1294 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); 1295 1296 intel_dp->want_panel_vdd = false; 1297 1298 if (sync) 1299 edp_panel_vdd_off_sync(intel_dp); 1300 else 1301 edp_panel_vdd_schedule_off(intel_dp); 1302} 1303 1304void intel_edp_panel_on(struct intel_dp *intel_dp) 1305{ 1306 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1307 struct drm_i915_private *dev_priv = dev->dev_private; 1308 u32 pp; 1309 u32 pp_ctrl_reg; 1310 1311 if (!is_edp(intel_dp)) 1312 return; 1313 1314 DRM_DEBUG_KMS("Turn eDP power on\n"); 1315 1316 if (edp_have_panel_power(intel_dp)) { 1317 DRM_DEBUG_KMS("eDP power already on\n"); 1318 return; 1319 } 1320 1321 wait_panel_power_cycle(intel_dp); 1322 1323 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1324 pp = ironlake_get_pp_control(intel_dp); 1325 if (IS_GEN5(dev)) { 1326 /* ILK workaround: disable reset around power sequence */ 1327 pp &= ~PANEL_POWER_RESET; 1328 I915_WRITE(pp_ctrl_reg, pp); 1329 POSTING_READ(pp_ctrl_reg); 1330 } 1331 1332 pp |= POWER_TARGET_ON; 1333 if (!IS_GEN5(dev)) 1334 pp |= PANEL_POWER_RESET; 1335 1336 I915_WRITE(pp_ctrl_reg, pp); 1337 POSTING_READ(pp_ctrl_reg); 1338 1339 wait_panel_on(intel_dp); 1340 intel_dp->last_power_on = jiffies; 1341 1342 if (IS_GEN5(dev)) { 1343 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 1344 I915_WRITE(pp_ctrl_reg, pp); 1345 POSTING_READ(pp_ctrl_reg); 1346 } 1347} 1348 1349void intel_edp_panel_off(struct intel_dp *intel_dp) 1350{ 1351 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1352 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1353 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1354 struct drm_i915_private *dev_priv = dev->dev_private; 1355 enum intel_display_power_domain power_domain; 1356 u32 pp; 1357 u32 pp_ctrl_reg; 1358 1359 if (!is_edp(intel_dp)) 1360 return; 1361 1362 DRM_DEBUG_KMS("Turn eDP power off\n"); 1363 1364 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); 1365 1366 pp = ironlake_get_pp_control(intel_dp); 1367 /* We need to switch off panel power _and_ force vdd, for otherwise some 1368 * panels get very unhappy and cease to work. */ 1369 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | 1370 EDP_BLC_ENABLE); 1371 1372 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1373 1374 intel_dp->want_panel_vdd = false; 1375 1376 I915_WRITE(pp_ctrl_reg, pp); 1377 POSTING_READ(pp_ctrl_reg); 1378 1379 intel_dp->last_power_cycle = jiffies; 1380 wait_panel_off(intel_dp); 1381 1382 /* We got a reference when we enabled the VDD. */ 1383 power_domain = intel_display_port_power_domain(intel_encoder); 1384 intel_display_power_put(dev_priv, power_domain); 1385} 1386 1387void intel_edp_backlight_on(struct intel_dp *intel_dp) 1388{ 1389 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1390 struct drm_device *dev = intel_dig_port->base.base.dev; 1391 struct drm_i915_private *dev_priv = dev->dev_private; 1392 u32 pp; 1393 u32 pp_ctrl_reg; 1394 1395 if (!is_edp(intel_dp)) 1396 return; 1397 1398 DRM_DEBUG_KMS("\n"); 1399 1400 intel_panel_enable_backlight(intel_dp->attached_connector); 1401 1402 /* 1403 * If we enable the backlight right away following a panel power 1404 * on, we may see slight flicker as the panel syncs with the eDP 1405 * link. So delay a bit to make sure the image is solid before 1406 * allowing it to appear. 1407 */ 1408 wait_backlight_on(intel_dp); 1409 pp = ironlake_get_pp_control(intel_dp); 1410 pp |= EDP_BLC_ENABLE; 1411 1412 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1413 1414 I915_WRITE(pp_ctrl_reg, pp); 1415 POSTING_READ(pp_ctrl_reg); 1416} 1417 1418void intel_edp_backlight_off(struct intel_dp *intel_dp) 1419{ 1420 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1421 struct drm_i915_private *dev_priv = dev->dev_private; 1422 u32 pp; 1423 u32 pp_ctrl_reg; 1424 1425 if (!is_edp(intel_dp)) 1426 return; 1427 1428 DRM_DEBUG_KMS("\n"); 1429 pp = ironlake_get_pp_control(intel_dp); 1430 pp &= ~EDP_BLC_ENABLE; 1431 1432 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1433 1434 I915_WRITE(pp_ctrl_reg, pp); 1435 POSTING_READ(pp_ctrl_reg); 1436 intel_dp->last_backlight_off = jiffies; 1437 1438 edp_wait_backlight_off(intel_dp); 1439 1440 intel_panel_disable_backlight(intel_dp->attached_connector); 1441} 1442 1443static void ironlake_edp_pll_on(struct intel_dp *intel_dp) 1444{ 1445 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1446 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 1447 struct drm_device *dev = crtc->dev; 1448 struct drm_i915_private *dev_priv = dev->dev_private; 1449 u32 dpa_ctl; 1450 1451 assert_pipe_disabled(dev_priv, 1452 to_intel_crtc(crtc)->pipe); 1453 1454 DRM_DEBUG_KMS("\n"); 1455 dpa_ctl = I915_READ(DP_A); 1456 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); 1457 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1458 1459 /* We don't adjust intel_dp->DP while tearing down the link, to 1460 * facilitate link retraining (e.g. after hotplug). Hence clear all 1461 * enable bits here to ensure that we don't enable too much. */ 1462 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); 1463 intel_dp->DP |= DP_PLL_ENABLE; 1464 I915_WRITE(DP_A, intel_dp->DP); 1465 POSTING_READ(DP_A); 1466 udelay(200); 1467} 1468 1469static void ironlake_edp_pll_off(struct intel_dp *intel_dp) 1470{ 1471 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1472 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 1473 struct drm_device *dev = crtc->dev; 1474 struct drm_i915_private *dev_priv = dev->dev_private; 1475 u32 dpa_ctl; 1476 1477 assert_pipe_disabled(dev_priv, 1478 to_intel_crtc(crtc)->pipe); 1479 1480 dpa_ctl = I915_READ(DP_A); 1481 WARN((dpa_ctl & DP_PLL_ENABLE) == 0, 1482 "dp pll off, should be on\n"); 1483 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1484 1485 /* We can't rely on the value tracked for the DP register in 1486 * intel_dp->DP because link_down must not change that (otherwise link 1487 * re-training will fail. */ 1488 dpa_ctl &= ~DP_PLL_ENABLE; 1489 I915_WRITE(DP_A, dpa_ctl); 1490 POSTING_READ(DP_A); 1491 udelay(200); 1492} 1493 1494/* If the sink supports it, try to set the power state appropriately */ 1495void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) 1496{ 1497 int ret, i; 1498 1499 /* Should have a valid DPCD by this point */ 1500 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 1501 return; 1502 1503 if (mode != DRM_MODE_DPMS_ON) { 1504 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 1505 DP_SET_POWER_D3); 1506 if (ret != 1) 1507 DRM_DEBUG_DRIVER("failed to write sink power state\n"); 1508 } else { 1509 /* 1510 * When turning on, we need to retry for 1ms to give the sink 1511 * time to wake up. 1512 */ 1513 for (i = 0; i < 3; i++) { 1514 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 1515 DP_SET_POWER_D0); 1516 if (ret == 1) 1517 break; 1518 msleep(1); 1519 } 1520 } 1521} 1522 1523static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 1524 enum pipe *pipe) 1525{ 1526 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1527 enum port port = dp_to_dig_port(intel_dp)->port; 1528 struct drm_device *dev = encoder->base.dev; 1529 struct drm_i915_private *dev_priv = dev->dev_private; 1530 enum intel_display_power_domain power_domain; 1531 u32 tmp; 1532 1533 power_domain = intel_display_port_power_domain(encoder); 1534 if (!intel_display_power_enabled(dev_priv, power_domain)) 1535 return false; 1536 1537 tmp = I915_READ(intel_dp->output_reg); 1538 1539 if (!(tmp & DP_PORT_EN)) 1540 return false; 1541 1542 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { 1543 *pipe = PORT_TO_PIPE_CPT(tmp); 1544 } else if (IS_CHERRYVIEW(dev)) { 1545 *pipe = DP_PORT_TO_PIPE_CHV(tmp); 1546 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { 1547 *pipe = PORT_TO_PIPE(tmp); 1548 } else { 1549 u32 trans_sel; 1550 u32 trans_dp; 1551 int i; 1552 1553 switch (intel_dp->output_reg) { 1554 case PCH_DP_B: 1555 trans_sel = TRANS_DP_PORT_SEL_B; 1556 break; 1557 case PCH_DP_C: 1558 trans_sel = TRANS_DP_PORT_SEL_C; 1559 break; 1560 case PCH_DP_D: 1561 trans_sel = TRANS_DP_PORT_SEL_D; 1562 break; 1563 default: 1564 return true; 1565 } 1566 1567 for_each_pipe(i) { 1568 trans_dp = I915_READ(TRANS_DP_CTL(i)); 1569 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { 1570 *pipe = i; 1571 return true; 1572 } 1573 } 1574 1575 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", 1576 intel_dp->output_reg); 1577 } 1578 1579 return true; 1580} 1581 1582static void intel_dp_get_config(struct intel_encoder *encoder, 1583 struct intel_crtc_config *pipe_config) 1584{ 1585 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1586 u32 tmp, flags = 0; 1587 struct drm_device *dev = encoder->base.dev; 1588 struct drm_i915_private *dev_priv = dev->dev_private; 1589 enum port port = dp_to_dig_port(intel_dp)->port; 1590 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1591 int dotclock; 1592 1593 tmp = I915_READ(intel_dp->output_reg); 1594 if (tmp & DP_AUDIO_OUTPUT_ENABLE) 1595 pipe_config->has_audio = true; 1596 1597 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { 1598 if (tmp & DP_SYNC_HS_HIGH) 1599 flags |= DRM_MODE_FLAG_PHSYNC; 1600 else 1601 flags |= DRM_MODE_FLAG_NHSYNC; 1602 1603 if (tmp & DP_SYNC_VS_HIGH) 1604 flags |= DRM_MODE_FLAG_PVSYNC; 1605 else 1606 flags |= DRM_MODE_FLAG_NVSYNC; 1607 } else { 1608 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); 1609 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) 1610 flags |= DRM_MODE_FLAG_PHSYNC; 1611 else 1612 flags |= DRM_MODE_FLAG_NHSYNC; 1613 1614 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) 1615 flags |= DRM_MODE_FLAG_PVSYNC; 1616 else 1617 flags |= DRM_MODE_FLAG_NVSYNC; 1618 } 1619 1620 pipe_config->adjusted_mode.flags |= flags; 1621 1622 pipe_config->has_dp_encoder = true; 1623 1624 intel_dp_get_m_n(crtc, pipe_config); 1625 1626 if (port == PORT_A) { 1627 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) 1628 pipe_config->port_clock = 162000; 1629 else 1630 pipe_config->port_clock = 270000; 1631 } 1632 1633 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1634 &pipe_config->dp_m_n); 1635 1636 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) 1637 ironlake_check_encoder_dotclock(pipe_config, dotclock); 1638 1639 pipe_config->adjusted_mode.crtc_clock = dotclock; 1640 1641 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && 1642 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { 1643 /* 1644 * This is a big fat ugly hack. 1645 * 1646 * Some machines in UEFI boot mode provide us a VBT that has 18 1647 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 1648 * unknown we fail to light up. Yet the same BIOS boots up with 1649 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 1650 * max, not what it tells us to use. 1651 * 1652 * Note: This will still be broken if the eDP panel is not lit 1653 * up by the BIOS, and thus we can't get the mode at module 1654 * load. 1655 */ 1656 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 1657 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); 1658 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; 1659 } 1660} 1661 1662static bool is_edp_psr(struct intel_dp *intel_dp) 1663{ 1664 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED; 1665} 1666 1667static bool intel_edp_is_psr_enabled(struct drm_device *dev) 1668{ 1669 struct drm_i915_private *dev_priv = dev->dev_private; 1670 1671 if (!HAS_PSR(dev)) 1672 return false; 1673 1674 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; 1675} 1676 1677static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp, 1678 struct edp_vsc_psr *vsc_psr) 1679{ 1680 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1681 struct drm_device *dev = dig_port->base.base.dev; 1682 struct drm_i915_private *dev_priv = dev->dev_private; 1683 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 1684 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); 1685 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); 1686 uint32_t *data = (uint32_t *) vsc_psr; 1687 unsigned int i; 1688 1689 /* As per BSPec (Pipe Video Data Island Packet), we need to disable 1690 the video DIP being updated before program video DIP data buffer 1691 registers for DIP being updated. */ 1692 I915_WRITE(ctl_reg, 0); 1693 POSTING_READ(ctl_reg); 1694 1695 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { 1696 if (i < sizeof(struct edp_vsc_psr)) 1697 I915_WRITE(data_reg + i, *data++); 1698 else 1699 I915_WRITE(data_reg + i, 0); 1700 } 1701 1702 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); 1703 POSTING_READ(ctl_reg); 1704} 1705 1706static void intel_edp_psr_setup(struct intel_dp *intel_dp) 1707{ 1708 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1709 struct drm_i915_private *dev_priv = dev->dev_private; 1710 struct edp_vsc_psr psr_vsc; 1711 1712 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ 1713 memset(&psr_vsc, 0, sizeof(psr_vsc)); 1714 psr_vsc.sdp_header.HB0 = 0; 1715 psr_vsc.sdp_header.HB1 = 0x7; 1716 psr_vsc.sdp_header.HB2 = 0x2; 1717 psr_vsc.sdp_header.HB3 = 0x8; 1718 intel_edp_psr_write_vsc(intel_dp, &psr_vsc); 1719 1720 /* Avoid continuous PSR exit by masking memup and hpd */ 1721 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | 1722 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); 1723} 1724 1725static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) 1726{ 1727 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1728 struct drm_device *dev = dig_port->base.base.dev; 1729 struct drm_i915_private *dev_priv = dev->dev_private; 1730 uint32_t aux_clock_divider; 1731 int precharge = 0x3; 1732 int msg_size = 5; /* Header(4) + Message(1) */ 1733 bool only_standby = false; 1734 1735 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); 1736 1737 if (IS_BROADWELL(dev) && dig_port->port != PORT_A) 1738 only_standby = true; 1739 1740 /* Enable PSR in sink */ 1741 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) 1742 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 1743 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE); 1744 else 1745 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 1746 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); 1747 1748 /* Setup AUX registers */ 1749 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND); 1750 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION); 1751 I915_WRITE(EDP_PSR_AUX_CTL(dev), 1752 DP_AUX_CH_CTL_TIME_OUT_400us | 1753 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 1754 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 1755 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); 1756} 1757 1758static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) 1759{ 1760 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1761 struct drm_device *dev = dig_port->base.base.dev; 1762 struct drm_i915_private *dev_priv = dev->dev_private; 1763 uint32_t max_sleep_time = 0x1f; 1764 uint32_t idle_frames = 1; 1765 uint32_t val = 0x0; 1766 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 1767 bool only_standby = false; 1768 1769 if (IS_BROADWELL(dev) && dig_port->port != PORT_A) 1770 only_standby = true; 1771 1772 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) { 1773 val |= EDP_PSR_LINK_STANDBY; 1774 val |= EDP_PSR_TP2_TP3_TIME_0us; 1775 val |= EDP_PSR_TP1_TIME_0us; 1776 val |= EDP_PSR_SKIP_AUX_EXIT; 1777 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0; 1778 } else 1779 val |= EDP_PSR_LINK_DISABLE; 1780 1781 I915_WRITE(EDP_PSR_CTL(dev), val | 1782 (IS_BROADWELL(dev) ? 0 : link_entry_time) | 1783 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | 1784 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | 1785 EDP_PSR_ENABLE); 1786} 1787 1788static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp) 1789{ 1790 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1791 struct drm_device *dev = dig_port->base.base.dev; 1792 struct drm_i915_private *dev_priv = dev->dev_private; 1793 struct drm_crtc *crtc = dig_port->base.base.crtc; 1794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1795 1796 lockdep_assert_held(&dev_priv->psr.lock); 1797 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 1798 WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); 1799 1800 dev_priv->psr.source_ok = false; 1801 1802 if (IS_HASWELL(dev) && dig_port->port != PORT_A) { 1803 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); 1804 return false; 1805 } 1806 1807 if (!i915.enable_psr) { 1808 DRM_DEBUG_KMS("PSR disable by flag\n"); 1809 return false; 1810 } 1811 1812 /* Below limitations aren't valid for Broadwell */ 1813 if (IS_BROADWELL(dev)) 1814 goto out; 1815 1816 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & 1817 S3D_ENABLE) { 1818 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); 1819 return false; 1820 } 1821 1822 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 1823 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); 1824 return false; 1825 } 1826 1827 out: 1828 dev_priv->psr.source_ok = true; 1829 return true; 1830} 1831 1832static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) 1833{ 1834 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1835 struct drm_device *dev = intel_dig_port->base.base.dev; 1836 struct drm_i915_private *dev_priv = dev->dev_private; 1837 1838 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE); 1839 WARN_ON(dev_priv->psr.active); 1840 lockdep_assert_held(&dev_priv->psr.lock); 1841 1842 /* Enable PSR on the panel */ 1843 intel_edp_psr_enable_sink(intel_dp); 1844 1845 /* Enable PSR on the host */ 1846 intel_edp_psr_enable_source(intel_dp); 1847 1848 dev_priv->psr.active = true; 1849} 1850 1851void intel_edp_psr_enable(struct intel_dp *intel_dp) 1852{ 1853 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1854 struct drm_i915_private *dev_priv = dev->dev_private; 1855 1856 if (!HAS_PSR(dev)) { 1857 DRM_DEBUG_KMS("PSR not supported on this platform\n"); 1858 return; 1859 } 1860 1861 if (!is_edp_psr(intel_dp)) { 1862 DRM_DEBUG_KMS("PSR not supported by this panel\n"); 1863 return; 1864 } 1865 1866 mutex_lock(&dev_priv->psr.lock); 1867 if (dev_priv->psr.enabled) { 1868 DRM_DEBUG_KMS("PSR already in use\n"); 1869 mutex_unlock(&dev_priv->psr.lock); 1870 return; 1871 } 1872 1873 dev_priv->psr.busy_frontbuffer_bits = 0; 1874 1875 /* Setup PSR once */ 1876 intel_edp_psr_setup(intel_dp); 1877 1878 if (intel_edp_psr_match_conditions(intel_dp)) 1879 dev_priv->psr.enabled = intel_dp; 1880 mutex_unlock(&dev_priv->psr.lock); 1881} 1882 1883void intel_edp_psr_disable(struct intel_dp *intel_dp) 1884{ 1885 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1886 struct drm_i915_private *dev_priv = dev->dev_private; 1887 1888 mutex_lock(&dev_priv->psr.lock); 1889 if (!dev_priv->psr.enabled) { 1890 mutex_unlock(&dev_priv->psr.lock); 1891 return; 1892 } 1893 1894 if (dev_priv->psr.active) { 1895 I915_WRITE(EDP_PSR_CTL(dev), 1896 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); 1897 1898 /* Wait till PSR is idle */ 1899 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & 1900 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) 1901 DRM_ERROR("Timed out waiting for PSR Idle State\n"); 1902 1903 dev_priv->psr.active = false; 1904 } else { 1905 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE); 1906 } 1907 1908 dev_priv->psr.enabled = NULL; 1909 mutex_unlock(&dev_priv->psr.lock); 1910 1911 cancel_delayed_work_sync(&dev_priv->psr.work); 1912} 1913 1914static void intel_edp_psr_work(struct work_struct *work) 1915{ 1916 struct drm_i915_private *dev_priv = 1917 container_of(work, typeof(*dev_priv), psr.work.work); 1918 struct intel_dp *intel_dp = dev_priv->psr.enabled; 1919 1920 mutex_lock(&dev_priv->psr.lock); 1921 intel_dp = dev_priv->psr.enabled; 1922 1923 if (!intel_dp) 1924 goto unlock; 1925 1926 /* 1927 * The delayed work can race with an invalidate hence we need to 1928 * recheck. Since psr_flush first clears this and then reschedules we 1929 * won't ever miss a flush when bailing out here. 1930 */ 1931 if (dev_priv->psr.busy_frontbuffer_bits) 1932 goto unlock; 1933 1934 intel_edp_psr_do_enable(intel_dp); 1935unlock: 1936 mutex_unlock(&dev_priv->psr.lock); 1937} 1938 1939static void intel_edp_psr_do_exit(struct drm_device *dev) 1940{ 1941 struct drm_i915_private *dev_priv = dev->dev_private; 1942 1943 if (dev_priv->psr.active) { 1944 u32 val = I915_READ(EDP_PSR_CTL(dev)); 1945 1946 WARN_ON(!(val & EDP_PSR_ENABLE)); 1947 1948 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE); 1949 1950 dev_priv->psr.active = false; 1951 } 1952 1953} 1954 1955void intel_edp_psr_invalidate(struct drm_device *dev, 1956 unsigned frontbuffer_bits) 1957{ 1958 struct drm_i915_private *dev_priv = dev->dev_private; 1959 struct drm_crtc *crtc; 1960 enum pipe pipe; 1961 1962 mutex_lock(&dev_priv->psr.lock); 1963 if (!dev_priv->psr.enabled) { 1964 mutex_unlock(&dev_priv->psr.lock); 1965 return; 1966 } 1967 1968 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; 1969 pipe = to_intel_crtc(crtc)->pipe; 1970 1971 intel_edp_psr_do_exit(dev); 1972 1973 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); 1974 1975 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; 1976 mutex_unlock(&dev_priv->psr.lock); 1977} 1978 1979void intel_edp_psr_flush(struct drm_device *dev, 1980 unsigned frontbuffer_bits) 1981{ 1982 struct drm_i915_private *dev_priv = dev->dev_private; 1983 struct drm_crtc *crtc; 1984 enum pipe pipe; 1985 1986 mutex_lock(&dev_priv->psr.lock); 1987 if (!dev_priv->psr.enabled) { 1988 mutex_unlock(&dev_priv->psr.lock); 1989 return; 1990 } 1991 1992 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; 1993 pipe = to_intel_crtc(crtc)->pipe; 1994 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; 1995 1996 /* 1997 * On Haswell sprite plane updates don't result in a psr invalidating 1998 * signal in the hardware. Which means we need to manually fake this in 1999 * software for all flushes, not just when we've seen a preceding 2000 * invalidation through frontbuffer rendering. 2001 */ 2002 if (IS_HASWELL(dev) && 2003 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe))) 2004 intel_edp_psr_do_exit(dev); 2005 2006 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) 2007 schedule_delayed_work(&dev_priv->psr.work, 2008 msecs_to_jiffies(100)); 2009 mutex_unlock(&dev_priv->psr.lock); 2010} 2011 2012void intel_edp_psr_init(struct drm_device *dev) 2013{ 2014 struct drm_i915_private *dev_priv = dev->dev_private; 2015 2016 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work); 2017 mutex_init(&dev_priv->psr.lock); 2018} 2019 2020static void intel_disable_dp(struct intel_encoder *encoder) 2021{ 2022 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2023 enum port port = dp_to_dig_port(intel_dp)->port; 2024 struct drm_device *dev = encoder->base.dev; 2025 2026 /* Make sure the panel is off before trying to change the mode. But also 2027 * ensure that we have vdd while we switch off the panel. */ 2028 intel_edp_panel_vdd_on(intel_dp); 2029 intel_edp_backlight_off(intel_dp); 2030 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 2031 intel_edp_panel_off(intel_dp); 2032 2033 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ 2034 if (!(port == PORT_A || IS_VALLEYVIEW(dev))) 2035 intel_dp_link_down(intel_dp); 2036} 2037 2038static void g4x_post_disable_dp(struct intel_encoder *encoder) 2039{ 2040 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2041 enum port port = dp_to_dig_port(intel_dp)->port; 2042 2043 if (port != PORT_A) 2044 return; 2045 2046 intel_dp_link_down(intel_dp); 2047 ironlake_edp_pll_off(intel_dp); 2048} 2049 2050static void vlv_post_disable_dp(struct intel_encoder *encoder) 2051{ 2052 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2053 2054 intel_dp_link_down(intel_dp); 2055} 2056 2057static void chv_post_disable_dp(struct intel_encoder *encoder) 2058{ 2059 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2060 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2061 struct drm_device *dev = encoder->base.dev; 2062 struct drm_i915_private *dev_priv = dev->dev_private; 2063 struct intel_crtc *intel_crtc = 2064 to_intel_crtc(encoder->base.crtc); 2065 enum dpio_channel ch = vlv_dport_to_channel(dport); 2066 enum pipe pipe = intel_crtc->pipe; 2067 u32 val; 2068 2069 intel_dp_link_down(intel_dp); 2070 2071 mutex_lock(&dev_priv->dpio_lock); 2072 2073 /* Propagate soft reset to data lane reset */ 2074 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); 2075 val |= CHV_PCS_REQ_SOFTRESET_EN; 2076 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); 2077 2078 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); 2079 val |= CHV_PCS_REQ_SOFTRESET_EN; 2080 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); 2081 2082 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); 2083 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 2084 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); 2085 2086 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); 2087 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 2088 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); 2089 2090 mutex_unlock(&dev_priv->dpio_lock); 2091} 2092 2093static void intel_enable_dp(struct intel_encoder *encoder) 2094{ 2095 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2096 struct drm_device *dev = encoder->base.dev; 2097 struct drm_i915_private *dev_priv = dev->dev_private; 2098 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 2099 2100 if (WARN_ON(dp_reg & DP_PORT_EN)) 2101 return; 2102 2103 intel_edp_panel_vdd_on(intel_dp); 2104 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 2105 intel_dp_start_link_train(intel_dp); 2106 intel_edp_panel_on(intel_dp); 2107 edp_panel_vdd_off(intel_dp, true); 2108 intel_dp_complete_link_train(intel_dp); 2109 intel_dp_stop_link_train(intel_dp); 2110} 2111 2112static void g4x_enable_dp(struct intel_encoder *encoder) 2113{ 2114 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2115 2116 intel_enable_dp(encoder); 2117 intel_edp_backlight_on(intel_dp); 2118} 2119 2120static void vlv_enable_dp(struct intel_encoder *encoder) 2121{ 2122 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2123 2124 intel_edp_backlight_on(intel_dp); 2125} 2126 2127static void g4x_pre_enable_dp(struct intel_encoder *encoder) 2128{ 2129 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2130 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2131 2132 intel_dp_prepare(encoder); 2133 2134 /* Only ilk+ has port A */ 2135 if (dport->port == PORT_A) { 2136 ironlake_set_pll_cpu_edp(intel_dp); 2137 ironlake_edp_pll_on(intel_dp); 2138 } 2139} 2140 2141static void vlv_pre_enable_dp(struct intel_encoder *encoder) 2142{ 2143 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2144 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2145 struct drm_device *dev = encoder->base.dev; 2146 struct drm_i915_private *dev_priv = dev->dev_private; 2147 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 2148 enum dpio_channel port = vlv_dport_to_channel(dport); 2149 int pipe = intel_crtc->pipe; 2150 struct edp_power_seq power_seq; 2151 u32 val; 2152 2153 mutex_lock(&dev_priv->dpio_lock); 2154 2155 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); 2156 val = 0; 2157 if (pipe) 2158 val |= (1<<21); 2159 else 2160 val &= ~(1<<21); 2161 val |= 0x001000c4; 2162 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); 2163 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); 2164 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); 2165 2166 mutex_unlock(&dev_priv->dpio_lock); 2167 2168 if (is_edp(intel_dp)) { 2169 /* init power sequencer on this pipe and port */ 2170 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 2171 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, 2172 &power_seq); 2173 } 2174 2175 intel_enable_dp(encoder); 2176 2177 vlv_wait_port_ready(dev_priv, dport); 2178} 2179 2180static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) 2181{ 2182 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 2183 struct drm_device *dev = encoder->base.dev; 2184 struct drm_i915_private *dev_priv = dev->dev_private; 2185 struct intel_crtc *intel_crtc = 2186 to_intel_crtc(encoder->base.crtc); 2187 enum dpio_channel port = vlv_dport_to_channel(dport); 2188 int pipe = intel_crtc->pipe; 2189 2190 intel_dp_prepare(encoder); 2191 2192 /* Program Tx lane resets to default */ 2193 mutex_lock(&dev_priv->dpio_lock); 2194 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 2195 DPIO_PCS_TX_LANE2_RESET | 2196 DPIO_PCS_TX_LANE1_RESET); 2197 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 2198 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | 2199 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | 2200 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | 2201 DPIO_PCS_CLK_SOFT_RESET); 2202 2203 /* Fix up inter-pair skew failure */ 2204 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); 2205 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); 2206 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); 2207 mutex_unlock(&dev_priv->dpio_lock); 2208} 2209 2210static void chv_pre_enable_dp(struct intel_encoder *encoder) 2211{ 2212 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2213 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2214 struct drm_device *dev = encoder->base.dev; 2215 struct drm_i915_private *dev_priv = dev->dev_private; 2216 struct edp_power_seq power_seq; 2217 struct intel_crtc *intel_crtc = 2218 to_intel_crtc(encoder->base.crtc); 2219 enum dpio_channel ch = vlv_dport_to_channel(dport); 2220 int pipe = intel_crtc->pipe; 2221 int data, i; 2222 u32 val; 2223 2224 mutex_lock(&dev_priv->dpio_lock); 2225 2226 /* Deassert soft data lane reset*/ 2227 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); 2228 val |= CHV_PCS_REQ_SOFTRESET_EN; 2229 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); 2230 2231 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); 2232 val |= CHV_PCS_REQ_SOFTRESET_EN; 2233 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); 2234 2235 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); 2236 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 2237 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); 2238 2239 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); 2240 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 2241 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); 2242 2243 /* Program Tx lane latency optimal setting*/ 2244 for (i = 0; i < 4; i++) { 2245 /* Set the latency optimal bit */ 2246 data = (i == 1) ? 0x0 : 0x6; 2247 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i), 2248 data << DPIO_FRC_LATENCY_SHFIT); 2249 2250 /* Set the upar bit */ 2251 data = (i == 1) ? 0x0 : 0x1; 2252 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), 2253 data << DPIO_UPAR_SHIFT); 2254 } 2255 2256 /* Data lane stagger programming */ 2257 /* FIXME: Fix up value only after power analysis */ 2258 2259 mutex_unlock(&dev_priv->dpio_lock); 2260 2261 if (is_edp(intel_dp)) { 2262 /* init power sequencer on this pipe and port */ 2263 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 2264 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, 2265 &power_seq); 2266 } 2267 2268 intel_enable_dp(encoder); 2269 2270 vlv_wait_port_ready(dev_priv, dport); 2271} 2272 2273static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) 2274{ 2275 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 2276 struct drm_device *dev = encoder->base.dev; 2277 struct drm_i915_private *dev_priv = dev->dev_private; 2278 struct intel_crtc *intel_crtc = 2279 to_intel_crtc(encoder->base.crtc); 2280 enum dpio_channel ch = vlv_dport_to_channel(dport); 2281 enum pipe pipe = intel_crtc->pipe; 2282 u32 val; 2283 2284 mutex_lock(&dev_priv->dpio_lock); 2285 2286 /* program left/right clock distribution */ 2287 if (pipe != PIPE_B) { 2288 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); 2289 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); 2290 if (ch == DPIO_CH0) 2291 val |= CHV_BUFLEFTENA1_FORCE; 2292 if (ch == DPIO_CH1) 2293 val |= CHV_BUFRIGHTENA1_FORCE; 2294 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); 2295 } else { 2296 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); 2297 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); 2298 if (ch == DPIO_CH0) 2299 val |= CHV_BUFLEFTENA2_FORCE; 2300 if (ch == DPIO_CH1) 2301 val |= CHV_BUFRIGHTENA2_FORCE; 2302 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); 2303 } 2304 2305 /* program clock channel usage */ 2306 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); 2307 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 2308 if (pipe != PIPE_B) 2309 val &= ~CHV_PCS_USEDCLKCHANNEL; 2310 else 2311 val |= CHV_PCS_USEDCLKCHANNEL; 2312 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); 2313 2314 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); 2315 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 2316 if (pipe != PIPE_B) 2317 val &= ~CHV_PCS_USEDCLKCHANNEL; 2318 else 2319 val |= CHV_PCS_USEDCLKCHANNEL; 2320 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); 2321 2322 /* 2323 * This a a bit weird since generally CL 2324 * matches the pipe, but here we need to 2325 * pick the CL based on the port. 2326 */ 2327 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); 2328 if (pipe != PIPE_B) 2329 val &= ~CHV_CMN_USEDCLKCHANNEL; 2330 else 2331 val |= CHV_CMN_USEDCLKCHANNEL; 2332 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); 2333 2334 mutex_unlock(&dev_priv->dpio_lock); 2335} 2336 2337/* 2338 * Native read with retry for link status and receiver capability reads for 2339 * cases where the sink may still be asleep. 2340 * 2341 * Sinks are *supposed* to come up within 1ms from an off state, but we're also 2342 * supposed to retry 3 times per the spec. 2343 */ 2344static ssize_t 2345intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, 2346 void *buffer, size_t size) 2347{ 2348 ssize_t ret; 2349 int i; 2350 2351 for (i = 0; i < 3; i++) { 2352 ret = drm_dp_dpcd_read(aux, offset, buffer, size); 2353 if (ret == size) 2354 return ret; 2355 msleep(1); 2356 } 2357 2358 return ret; 2359} 2360 2361/* 2362 * Fetch AUX CH registers 0x202 - 0x207 which contain 2363 * link status information 2364 */ 2365static bool 2366intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 2367{ 2368 return intel_dp_dpcd_read_wake(&intel_dp->aux, 2369 DP_LANE0_1_STATUS, 2370 link_status, 2371 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; 2372} 2373 2374/* These are source-specific values. */ 2375static uint8_t 2376intel_dp_voltage_max(struct intel_dp *intel_dp) 2377{ 2378 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2379 enum port port = dp_to_dig_port(intel_dp)->port; 2380 2381 if (IS_VALLEYVIEW(dev)) 2382 return DP_TRAIN_VOLTAGE_SWING_1200; 2383 else if (IS_GEN7(dev) && port == PORT_A) 2384 return DP_TRAIN_VOLTAGE_SWING_800; 2385 else if (HAS_PCH_CPT(dev) && port != PORT_A) 2386 return DP_TRAIN_VOLTAGE_SWING_1200; 2387 else 2388 return DP_TRAIN_VOLTAGE_SWING_800; 2389} 2390 2391static uint8_t 2392intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) 2393{ 2394 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2395 enum port port = dp_to_dig_port(intel_dp)->port; 2396 2397 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 2398 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2399 case DP_TRAIN_VOLTAGE_SWING_400: 2400 return DP_TRAIN_PRE_EMPHASIS_9_5; 2401 case DP_TRAIN_VOLTAGE_SWING_600: 2402 return DP_TRAIN_PRE_EMPHASIS_6; 2403 case DP_TRAIN_VOLTAGE_SWING_800: 2404 return DP_TRAIN_PRE_EMPHASIS_3_5; 2405 case DP_TRAIN_VOLTAGE_SWING_1200: 2406 default: 2407 return DP_TRAIN_PRE_EMPHASIS_0; 2408 } 2409 } else if (IS_VALLEYVIEW(dev)) { 2410 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2411 case DP_TRAIN_VOLTAGE_SWING_400: 2412 return DP_TRAIN_PRE_EMPHASIS_9_5; 2413 case DP_TRAIN_VOLTAGE_SWING_600: 2414 return DP_TRAIN_PRE_EMPHASIS_6; 2415 case DP_TRAIN_VOLTAGE_SWING_800: 2416 return DP_TRAIN_PRE_EMPHASIS_3_5; 2417 case DP_TRAIN_VOLTAGE_SWING_1200: 2418 default: 2419 return DP_TRAIN_PRE_EMPHASIS_0; 2420 } 2421 } else if (IS_GEN7(dev) && port == PORT_A) { 2422 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2423 case DP_TRAIN_VOLTAGE_SWING_400: 2424 return DP_TRAIN_PRE_EMPHASIS_6; 2425 case DP_TRAIN_VOLTAGE_SWING_600: 2426 case DP_TRAIN_VOLTAGE_SWING_800: 2427 return DP_TRAIN_PRE_EMPHASIS_3_5; 2428 default: 2429 return DP_TRAIN_PRE_EMPHASIS_0; 2430 } 2431 } else { 2432 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2433 case DP_TRAIN_VOLTAGE_SWING_400: 2434 return DP_TRAIN_PRE_EMPHASIS_6; 2435 case DP_TRAIN_VOLTAGE_SWING_600: 2436 return DP_TRAIN_PRE_EMPHASIS_6; 2437 case DP_TRAIN_VOLTAGE_SWING_800: 2438 return DP_TRAIN_PRE_EMPHASIS_3_5; 2439 case DP_TRAIN_VOLTAGE_SWING_1200: 2440 default: 2441 return DP_TRAIN_PRE_EMPHASIS_0; 2442 } 2443 } 2444} 2445 2446static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) 2447{ 2448 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2449 struct drm_i915_private *dev_priv = dev->dev_private; 2450 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2451 struct intel_crtc *intel_crtc = 2452 to_intel_crtc(dport->base.base.crtc); 2453 unsigned long demph_reg_value, preemph_reg_value, 2454 uniqtranscale_reg_value; 2455 uint8_t train_set = intel_dp->train_set[0]; 2456 enum dpio_channel port = vlv_dport_to_channel(dport); 2457 int pipe = intel_crtc->pipe; 2458 2459 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2460 case DP_TRAIN_PRE_EMPHASIS_0: 2461 preemph_reg_value = 0x0004000; 2462 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2463 case DP_TRAIN_VOLTAGE_SWING_400: 2464 demph_reg_value = 0x2B405555; 2465 uniqtranscale_reg_value = 0x552AB83A; 2466 break; 2467 case DP_TRAIN_VOLTAGE_SWING_600: 2468 demph_reg_value = 0x2B404040; 2469 uniqtranscale_reg_value = 0x5548B83A; 2470 break; 2471 case DP_TRAIN_VOLTAGE_SWING_800: 2472 demph_reg_value = 0x2B245555; 2473 uniqtranscale_reg_value = 0x5560B83A; 2474 break; 2475 case DP_TRAIN_VOLTAGE_SWING_1200: 2476 demph_reg_value = 0x2B405555; 2477 uniqtranscale_reg_value = 0x5598DA3A; 2478 break; 2479 default: 2480 return 0; 2481 } 2482 break; 2483 case DP_TRAIN_PRE_EMPHASIS_3_5: 2484 preemph_reg_value = 0x0002000; 2485 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2486 case DP_TRAIN_VOLTAGE_SWING_400: 2487 demph_reg_value = 0x2B404040; 2488 uniqtranscale_reg_value = 0x5552B83A; 2489 break; 2490 case DP_TRAIN_VOLTAGE_SWING_600: 2491 demph_reg_value = 0x2B404848; 2492 uniqtranscale_reg_value = 0x5580B83A; 2493 break; 2494 case DP_TRAIN_VOLTAGE_SWING_800: 2495 demph_reg_value = 0x2B404040; 2496 uniqtranscale_reg_value = 0x55ADDA3A; 2497 break; 2498 default: 2499 return 0; 2500 } 2501 break; 2502 case DP_TRAIN_PRE_EMPHASIS_6: 2503 preemph_reg_value = 0x0000000; 2504 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2505 case DP_TRAIN_VOLTAGE_SWING_400: 2506 demph_reg_value = 0x2B305555; 2507 uniqtranscale_reg_value = 0x5570B83A; 2508 break; 2509 case DP_TRAIN_VOLTAGE_SWING_600: 2510 demph_reg_value = 0x2B2B4040; 2511 uniqtranscale_reg_value = 0x55ADDA3A; 2512 break; 2513 default: 2514 return 0; 2515 } 2516 break; 2517 case DP_TRAIN_PRE_EMPHASIS_9_5: 2518 preemph_reg_value = 0x0006000; 2519 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2520 case DP_TRAIN_VOLTAGE_SWING_400: 2521 demph_reg_value = 0x1B405555; 2522 uniqtranscale_reg_value = 0x55ADDA3A; 2523 break; 2524 default: 2525 return 0; 2526 } 2527 break; 2528 default: 2529 return 0; 2530 } 2531 2532 mutex_lock(&dev_priv->dpio_lock); 2533 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); 2534 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); 2535 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 2536 uniqtranscale_reg_value); 2537 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); 2538 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); 2539 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); 2540 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); 2541 mutex_unlock(&dev_priv->dpio_lock); 2542 2543 return 0; 2544} 2545 2546static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp) 2547{ 2548 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2549 struct drm_i915_private *dev_priv = dev->dev_private; 2550 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2551 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc); 2552 u32 deemph_reg_value, margin_reg_value, val; 2553 uint8_t train_set = intel_dp->train_set[0]; 2554 enum dpio_channel ch = vlv_dport_to_channel(dport); 2555 enum pipe pipe = intel_crtc->pipe; 2556 int i; 2557 2558 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2559 case DP_TRAIN_PRE_EMPHASIS_0: 2560 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2561 case DP_TRAIN_VOLTAGE_SWING_400: 2562 deemph_reg_value = 128; 2563 margin_reg_value = 52; 2564 break; 2565 case DP_TRAIN_VOLTAGE_SWING_600: 2566 deemph_reg_value = 128; 2567 margin_reg_value = 77; 2568 break; 2569 case DP_TRAIN_VOLTAGE_SWING_800: 2570 deemph_reg_value = 128; 2571 margin_reg_value = 102; 2572 break; 2573 case DP_TRAIN_VOLTAGE_SWING_1200: 2574 deemph_reg_value = 128; 2575 margin_reg_value = 154; 2576 /* FIXME extra to set for 1200 */ 2577 break; 2578 default: 2579 return 0; 2580 } 2581 break; 2582 case DP_TRAIN_PRE_EMPHASIS_3_5: 2583 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2584 case DP_TRAIN_VOLTAGE_SWING_400: 2585 deemph_reg_value = 85; 2586 margin_reg_value = 78; 2587 break; 2588 case DP_TRAIN_VOLTAGE_SWING_600: 2589 deemph_reg_value = 85; 2590 margin_reg_value = 116; 2591 break; 2592 case DP_TRAIN_VOLTAGE_SWING_800: 2593 deemph_reg_value = 85; 2594 margin_reg_value = 154; 2595 break; 2596 default: 2597 return 0; 2598 } 2599 break; 2600 case DP_TRAIN_PRE_EMPHASIS_6: 2601 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2602 case DP_TRAIN_VOLTAGE_SWING_400: 2603 deemph_reg_value = 64; 2604 margin_reg_value = 104; 2605 break; 2606 case DP_TRAIN_VOLTAGE_SWING_600: 2607 deemph_reg_value = 64; 2608 margin_reg_value = 154; 2609 break; 2610 default: 2611 return 0; 2612 } 2613 break; 2614 case DP_TRAIN_PRE_EMPHASIS_9_5: 2615 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2616 case DP_TRAIN_VOLTAGE_SWING_400: 2617 deemph_reg_value = 43; 2618 margin_reg_value = 154; 2619 break; 2620 default: 2621 return 0; 2622 } 2623 break; 2624 default: 2625 return 0; 2626 } 2627 2628 mutex_lock(&dev_priv->dpio_lock); 2629 2630 /* Clear calc init */ 2631 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 2632 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 2633 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 2634 2635 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 2636 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 2637 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 2638 2639 /* Program swing deemph */ 2640 for (i = 0; i < 4; i++) { 2641 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); 2642 val &= ~DPIO_SWING_DEEMPH9P5_MASK; 2643 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; 2644 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); 2645 } 2646 2647 /* Program swing margin */ 2648 for (i = 0; i < 4; i++) { 2649 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); 2650 val &= ~DPIO_SWING_MARGIN_MASK; 2651 val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT; 2652 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); 2653 } 2654 2655 /* Disable unique transition scale */ 2656 for (i = 0; i < 4; i++) { 2657 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); 2658 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; 2659 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); 2660 } 2661 2662 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK) 2663 == DP_TRAIN_PRE_EMPHASIS_0) && 2664 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK) 2665 == DP_TRAIN_VOLTAGE_SWING_1200)) { 2666 2667 /* 2668 * The document said it needs to set bit 27 for ch0 and bit 26 2669 * for ch1. Might be a typo in the doc. 2670 * For now, for this unique transition scale selection, set bit 2671 * 27 for ch0 and ch1. 2672 */ 2673 for (i = 0; i < 4; i++) { 2674 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); 2675 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; 2676 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); 2677 } 2678 2679 for (i = 0; i < 4; i++) { 2680 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); 2681 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); 2682 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT); 2683 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); 2684 } 2685 } 2686 2687 /* Start swing calculation */ 2688 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 2689 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 2690 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 2691 2692 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 2693 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 2694 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 2695 2696 /* LRC Bypass */ 2697 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); 2698 val |= DPIO_LRC_BYPASS; 2699 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); 2700 2701 mutex_unlock(&dev_priv->dpio_lock); 2702 2703 return 0; 2704} 2705 2706static void 2707intel_get_adjust_train(struct intel_dp *intel_dp, 2708 const uint8_t link_status[DP_LINK_STATUS_SIZE]) 2709{ 2710 uint8_t v = 0; 2711 uint8_t p = 0; 2712 int lane; 2713 uint8_t voltage_max; 2714 uint8_t preemph_max; 2715 2716 for (lane = 0; lane < intel_dp->lane_count; lane++) { 2717 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 2718 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 2719 2720 if (this_v > v) 2721 v = this_v; 2722 if (this_p > p) 2723 p = this_p; 2724 } 2725 2726 voltage_max = intel_dp_voltage_max(intel_dp); 2727 if (v >= voltage_max) 2728 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 2729 2730 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); 2731 if (p >= preemph_max) 2732 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 2733 2734 for (lane = 0; lane < 4; lane++) 2735 intel_dp->train_set[lane] = v | p; 2736} 2737 2738static uint32_t 2739intel_gen4_signal_levels(uint8_t train_set) 2740{ 2741 uint32_t signal_levels = 0; 2742 2743 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2744 case DP_TRAIN_VOLTAGE_SWING_400: 2745 default: 2746 signal_levels |= DP_VOLTAGE_0_4; 2747 break; 2748 case DP_TRAIN_VOLTAGE_SWING_600: 2749 signal_levels |= DP_VOLTAGE_0_6; 2750 break; 2751 case DP_TRAIN_VOLTAGE_SWING_800: 2752 signal_levels |= DP_VOLTAGE_0_8; 2753 break; 2754 case DP_TRAIN_VOLTAGE_SWING_1200: 2755 signal_levels |= DP_VOLTAGE_1_2; 2756 break; 2757 } 2758 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2759 case DP_TRAIN_PRE_EMPHASIS_0: 2760 default: 2761 signal_levels |= DP_PRE_EMPHASIS_0; 2762 break; 2763 case DP_TRAIN_PRE_EMPHASIS_3_5: 2764 signal_levels |= DP_PRE_EMPHASIS_3_5; 2765 break; 2766 case DP_TRAIN_PRE_EMPHASIS_6: 2767 signal_levels |= DP_PRE_EMPHASIS_6; 2768 break; 2769 case DP_TRAIN_PRE_EMPHASIS_9_5: 2770 signal_levels |= DP_PRE_EMPHASIS_9_5; 2771 break; 2772 } 2773 return signal_levels; 2774} 2775 2776/* Gen6's DP voltage swing and pre-emphasis control */ 2777static uint32_t 2778intel_gen6_edp_signal_levels(uint8_t train_set) 2779{ 2780 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2781 DP_TRAIN_PRE_EMPHASIS_MASK); 2782 switch (signal_levels) { 2783 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2784 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2785 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 2786 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2787 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 2788 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2789 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2790 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 2791 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2792 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2793 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 2794 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2795 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 2796 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 2797 default: 2798 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2799 "0x%x\n", signal_levels); 2800 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 2801 } 2802} 2803 2804/* Gen7's DP voltage swing and pre-emphasis control */ 2805static uint32_t 2806intel_gen7_edp_signal_levels(uint8_t train_set) 2807{ 2808 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2809 DP_TRAIN_PRE_EMPHASIS_MASK); 2810 switch (signal_levels) { 2811 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2812 return EDP_LINK_TRAIN_400MV_0DB_IVB; 2813 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2814 return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 2815 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2816 return EDP_LINK_TRAIN_400MV_6DB_IVB; 2817 2818 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2819 return EDP_LINK_TRAIN_600MV_0DB_IVB; 2820 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2821 return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 2822 2823 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2824 return EDP_LINK_TRAIN_800MV_0DB_IVB; 2825 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2826 return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 2827 2828 default: 2829 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2830 "0x%x\n", signal_levels); 2831 return EDP_LINK_TRAIN_500MV_0DB_IVB; 2832 } 2833} 2834 2835/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ 2836static uint32_t 2837intel_hsw_signal_levels(uint8_t train_set) 2838{ 2839 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2840 DP_TRAIN_PRE_EMPHASIS_MASK); 2841 switch (signal_levels) { 2842 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2843 return DDI_BUF_EMP_400MV_0DB_HSW; 2844 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2845 return DDI_BUF_EMP_400MV_3_5DB_HSW; 2846 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2847 return DDI_BUF_EMP_400MV_6DB_HSW; 2848 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: 2849 return DDI_BUF_EMP_400MV_9_5DB_HSW; 2850 2851 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2852 return DDI_BUF_EMP_600MV_0DB_HSW; 2853 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2854 return DDI_BUF_EMP_600MV_3_5DB_HSW; 2855 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2856 return DDI_BUF_EMP_600MV_6DB_HSW; 2857 2858 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2859 return DDI_BUF_EMP_800MV_0DB_HSW; 2860 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2861 return DDI_BUF_EMP_800MV_3_5DB_HSW; 2862 default: 2863 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2864 "0x%x\n", signal_levels); 2865 return DDI_BUF_EMP_400MV_0DB_HSW; 2866 } 2867} 2868 2869/* Properly updates "DP" with the correct signal levels. */ 2870static void 2871intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) 2872{ 2873 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2874 enum port port = intel_dig_port->port; 2875 struct drm_device *dev = intel_dig_port->base.base.dev; 2876 uint32_t signal_levels, mask; 2877 uint8_t train_set = intel_dp->train_set[0]; 2878 2879 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 2880 signal_levels = intel_hsw_signal_levels(train_set); 2881 mask = DDI_BUF_EMP_MASK; 2882 } else if (IS_CHERRYVIEW(dev)) { 2883 signal_levels = intel_chv_signal_levels(intel_dp); 2884 mask = 0; 2885 } else if (IS_VALLEYVIEW(dev)) { 2886 signal_levels = intel_vlv_signal_levels(intel_dp); 2887 mask = 0; 2888 } else if (IS_GEN7(dev) && port == PORT_A) { 2889 signal_levels = intel_gen7_edp_signal_levels(train_set); 2890 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; 2891 } else if (IS_GEN6(dev) && port == PORT_A) { 2892 signal_levels = intel_gen6_edp_signal_levels(train_set); 2893 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; 2894 } else { 2895 signal_levels = intel_gen4_signal_levels(train_set); 2896 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; 2897 } 2898 2899 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); 2900 2901 *DP = (*DP & ~mask) | signal_levels; 2902} 2903 2904static bool 2905intel_dp_set_link_train(struct intel_dp *intel_dp, 2906 uint32_t *DP, 2907 uint8_t dp_train_pat) 2908{ 2909 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2910 struct drm_device *dev = intel_dig_port->base.base.dev; 2911 struct drm_i915_private *dev_priv = dev->dev_private; 2912 enum port port = intel_dig_port->port; 2913 uint8_t buf[sizeof(intel_dp->train_set) + 1]; 2914 int ret, len; 2915 2916 if (HAS_DDI(dev)) { 2917 uint32_t temp = I915_READ(DP_TP_CTL(port)); 2918 2919 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) 2920 temp |= DP_TP_CTL_SCRAMBLE_DISABLE; 2921 else 2922 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; 2923 2924 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 2925 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2926 case DP_TRAINING_PATTERN_DISABLE: 2927 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 2928 2929 break; 2930 case DP_TRAINING_PATTERN_1: 2931 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 2932 break; 2933 case DP_TRAINING_PATTERN_2: 2934 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 2935 break; 2936 case DP_TRAINING_PATTERN_3: 2937 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 2938 break; 2939 } 2940 I915_WRITE(DP_TP_CTL(port), temp); 2941 2942 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { 2943 *DP &= ~DP_LINK_TRAIN_MASK_CPT; 2944 2945 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2946 case DP_TRAINING_PATTERN_DISABLE: 2947 *DP |= DP_LINK_TRAIN_OFF_CPT; 2948 break; 2949 case DP_TRAINING_PATTERN_1: 2950 *DP |= DP_LINK_TRAIN_PAT_1_CPT; 2951 break; 2952 case DP_TRAINING_PATTERN_2: 2953 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 2954 break; 2955 case DP_TRAINING_PATTERN_3: 2956 DRM_ERROR("DP training pattern 3 not supported\n"); 2957 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 2958 break; 2959 } 2960 2961 } else { 2962 *DP &= ~DP_LINK_TRAIN_MASK; 2963 2964 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2965 case DP_TRAINING_PATTERN_DISABLE: 2966 *DP |= DP_LINK_TRAIN_OFF; 2967 break; 2968 case DP_TRAINING_PATTERN_1: 2969 *DP |= DP_LINK_TRAIN_PAT_1; 2970 break; 2971 case DP_TRAINING_PATTERN_2: 2972 *DP |= DP_LINK_TRAIN_PAT_2; 2973 break; 2974 case DP_TRAINING_PATTERN_3: 2975 DRM_ERROR("DP training pattern 3 not supported\n"); 2976 *DP |= DP_LINK_TRAIN_PAT_2; 2977 break; 2978 } 2979 } 2980 2981 I915_WRITE(intel_dp->output_reg, *DP); 2982 POSTING_READ(intel_dp->output_reg); 2983 2984 buf[0] = dp_train_pat; 2985 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == 2986 DP_TRAINING_PATTERN_DISABLE) { 2987 /* don't write DP_TRAINING_LANEx_SET on disable */ 2988 len = 1; 2989 } else { 2990 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ 2991 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); 2992 len = intel_dp->lane_count + 1; 2993 } 2994 2995 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, 2996 buf, len); 2997 2998 return ret == len; 2999} 3000 3001static bool 3002intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, 3003 uint8_t dp_train_pat) 3004{ 3005 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 3006 intel_dp_set_signal_levels(intel_dp, DP); 3007 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); 3008} 3009 3010static bool 3011intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, 3012 const uint8_t link_status[DP_LINK_STATUS_SIZE]) 3013{ 3014 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3015 struct drm_device *dev = intel_dig_port->base.base.dev; 3016 struct drm_i915_private *dev_priv = dev->dev_private; 3017 int ret; 3018 3019 intel_get_adjust_train(intel_dp, link_status); 3020 intel_dp_set_signal_levels(intel_dp, DP); 3021 3022 I915_WRITE(intel_dp->output_reg, *DP); 3023 POSTING_READ(intel_dp->output_reg); 3024 3025 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, 3026 intel_dp->train_set, intel_dp->lane_count); 3027 3028 return ret == intel_dp->lane_count; 3029} 3030 3031static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) 3032{ 3033 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3034 struct drm_device *dev = intel_dig_port->base.base.dev; 3035 struct drm_i915_private *dev_priv = dev->dev_private; 3036 enum port port = intel_dig_port->port; 3037 uint32_t val; 3038 3039 if (!HAS_DDI(dev)) 3040 return; 3041 3042 val = I915_READ(DP_TP_CTL(port)); 3043 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3044 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 3045 I915_WRITE(DP_TP_CTL(port), val); 3046 3047 /* 3048 * On PORT_A we can have only eDP in SST mode. There the only reason 3049 * we need to set idle transmission mode is to work around a HW issue 3050 * where we enable the pipe while not in idle link-training mode. 3051 * In this case there is requirement to wait for a minimum number of 3052 * idle patterns to be sent. 3053 */ 3054 if (port == PORT_A) 3055 return; 3056 3057 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), 3058 1)) 3059 DRM_ERROR("Timed out waiting for DP idle patterns\n"); 3060} 3061 3062/* Enable corresponding port and start training pattern 1 */ 3063void 3064intel_dp_start_link_train(struct intel_dp *intel_dp) 3065{ 3066 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; 3067 struct drm_device *dev = encoder->dev; 3068 int i; 3069 uint8_t voltage; 3070 int voltage_tries, loop_tries; 3071 uint32_t DP = intel_dp->DP; 3072 uint8_t link_config[2]; 3073 3074 if (HAS_DDI(dev)) 3075 intel_ddi_prepare_link_retrain(encoder); 3076 3077 /* Write the link configuration data */ 3078 link_config[0] = intel_dp->link_bw; 3079 link_config[1] = intel_dp->lane_count; 3080 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 3081 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 3082 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); 3083 3084 link_config[0] = 0; 3085 link_config[1] = DP_SET_ANSI_8B10B; 3086 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); 3087 3088 DP |= DP_PORT_EN; 3089 3090 /* clock recovery */ 3091 if (!intel_dp_reset_link_train(intel_dp, &DP, 3092 DP_TRAINING_PATTERN_1 | 3093 DP_LINK_SCRAMBLING_DISABLE)) { 3094 DRM_ERROR("failed to enable link training\n"); 3095 return; 3096 } 3097 3098 voltage = 0xff; 3099 voltage_tries = 0; 3100 loop_tries = 0; 3101 for (;;) { 3102 uint8_t link_status[DP_LINK_STATUS_SIZE]; 3103 3104 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); 3105 if (!intel_dp_get_link_status(intel_dp, link_status)) { 3106 DRM_ERROR("failed to get link status\n"); 3107 break; 3108 } 3109 3110 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 3111 DRM_DEBUG_KMS("clock recovery OK\n"); 3112 break; 3113 } 3114 3115 /* Check to see if we've tried the max voltage */ 3116 for (i = 0; i < intel_dp->lane_count; i++) 3117 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 3118 break; 3119 if (i == intel_dp->lane_count) { 3120 ++loop_tries; 3121 if (loop_tries == 5) { 3122 DRM_ERROR("too many full retries, give up\n"); 3123 break; 3124 } 3125 intel_dp_reset_link_train(intel_dp, &DP, 3126 DP_TRAINING_PATTERN_1 | 3127 DP_LINK_SCRAMBLING_DISABLE); 3128 voltage_tries = 0; 3129 continue; 3130 } 3131 3132 /* Check to see if we've tried the same voltage 5 times */ 3133 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 3134 ++voltage_tries; 3135 if (voltage_tries == 5) { 3136 DRM_ERROR("too many voltage retries, give up\n"); 3137 break; 3138 } 3139 } else 3140 voltage_tries = 0; 3141 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 3142 3143 /* Update training set as requested by target */ 3144 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { 3145 DRM_ERROR("failed to update link training\n"); 3146 break; 3147 } 3148 } 3149 3150 intel_dp->DP = DP; 3151} 3152 3153void 3154intel_dp_complete_link_train(struct intel_dp *intel_dp) 3155{ 3156 bool channel_eq = false; 3157 int tries, cr_tries; 3158 uint32_t DP = intel_dp->DP; 3159 uint32_t training_pattern = DP_TRAINING_PATTERN_2; 3160 3161 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ 3162 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) 3163 training_pattern = DP_TRAINING_PATTERN_3; 3164 3165 /* channel equalization */ 3166 if (!intel_dp_set_link_train(intel_dp, &DP, 3167 training_pattern | 3168 DP_LINK_SCRAMBLING_DISABLE)) { 3169 DRM_ERROR("failed to start channel equalization\n"); 3170 return; 3171 } 3172 3173 tries = 0; 3174 cr_tries = 0; 3175 channel_eq = false; 3176 for (;;) { 3177 uint8_t link_status[DP_LINK_STATUS_SIZE]; 3178 3179 if (cr_tries > 5) { 3180 DRM_ERROR("failed to train DP, aborting\n"); 3181 break; 3182 } 3183 3184 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); 3185 if (!intel_dp_get_link_status(intel_dp, link_status)) { 3186 DRM_ERROR("failed to get link status\n"); 3187 break; 3188 } 3189 3190 /* Make sure clock is still ok */ 3191 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 3192 intel_dp_start_link_train(intel_dp); 3193 intel_dp_set_link_train(intel_dp, &DP, 3194 training_pattern | 3195 DP_LINK_SCRAMBLING_DISABLE); 3196 cr_tries++; 3197 continue; 3198 } 3199 3200 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { 3201 channel_eq = true; 3202 break; 3203 } 3204 3205 /* Try 5 times, then try clock recovery if that fails */ 3206 if (tries > 5) { 3207 intel_dp_link_down(intel_dp); 3208 intel_dp_start_link_train(intel_dp); 3209 intel_dp_set_link_train(intel_dp, &DP, 3210 training_pattern | 3211 DP_LINK_SCRAMBLING_DISABLE); 3212 tries = 0; 3213 cr_tries++; 3214 continue; 3215 } 3216 3217 /* Update training set as requested by target */ 3218 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { 3219 DRM_ERROR("failed to update link training\n"); 3220 break; 3221 } 3222 ++tries; 3223 } 3224 3225 intel_dp_set_idle_link_train(intel_dp); 3226 3227 intel_dp->DP = DP; 3228 3229 if (channel_eq) 3230 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); 3231 3232} 3233 3234void intel_dp_stop_link_train(struct intel_dp *intel_dp) 3235{ 3236 intel_dp_set_link_train(intel_dp, &intel_dp->DP, 3237 DP_TRAINING_PATTERN_DISABLE); 3238} 3239 3240static void 3241intel_dp_link_down(struct intel_dp *intel_dp) 3242{ 3243 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3244 enum port port = intel_dig_port->port; 3245 struct drm_device *dev = intel_dig_port->base.base.dev; 3246 struct drm_i915_private *dev_priv = dev->dev_private; 3247 struct intel_crtc *intel_crtc = 3248 to_intel_crtc(intel_dig_port->base.base.crtc); 3249 uint32_t DP = intel_dp->DP; 3250 3251 if (WARN_ON(HAS_DDI(dev))) 3252 return; 3253 3254 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) 3255 return; 3256 3257 DRM_DEBUG_KMS("\n"); 3258 3259 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { 3260 DP &= ~DP_LINK_TRAIN_MASK_CPT; 3261 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 3262 } else { 3263 DP &= ~DP_LINK_TRAIN_MASK; 3264 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 3265 } 3266 POSTING_READ(intel_dp->output_reg); 3267 3268 if (HAS_PCH_IBX(dev) && 3269 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { 3270 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 3271 3272 /* Hardware workaround: leaving our transcoder select 3273 * set to transcoder B while it's off will prevent the 3274 * corresponding HDMI output on transcoder A. 3275 * 3276 * Combine this with another hardware workaround: 3277 * transcoder select bit can only be cleared while the 3278 * port is enabled. 3279 */ 3280 DP &= ~DP_PIPEB_SELECT; 3281 I915_WRITE(intel_dp->output_reg, DP); 3282 3283 /* Changes to enable or select take place the vblank 3284 * after being written. 3285 */ 3286 if (WARN_ON(crtc == NULL)) { 3287 /* We should never try to disable a port without a crtc 3288 * attached. For paranoia keep the code around for a 3289 * bit. */ 3290 POSTING_READ(intel_dp->output_reg); 3291 msleep(50); 3292 } else 3293 intel_wait_for_vblank(dev, intel_crtc->pipe); 3294 } 3295 3296 DP &= ~DP_AUDIO_OUTPUT_ENABLE; 3297 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 3298 POSTING_READ(intel_dp->output_reg); 3299 msleep(intel_dp->panel_power_down_delay); 3300} 3301 3302static bool 3303intel_dp_get_dpcd(struct intel_dp *intel_dp) 3304{ 3305 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3306 struct drm_device *dev = dig_port->base.base.dev; 3307 struct drm_i915_private *dev_priv = dev->dev_private; 3308 3309 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; 3310 3311 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, 3312 sizeof(intel_dp->dpcd)) < 0) 3313 return false; /* aux transfer failed */ 3314 3315 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), 3316 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); 3317 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); 3318 3319 if (intel_dp->dpcd[DP_DPCD_REV] == 0) 3320 return false; /* DPCD not present */ 3321 3322 /* Check if the panel supports PSR */ 3323 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); 3324 if (is_edp(intel_dp)) { 3325 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, 3326 intel_dp->psr_dpcd, 3327 sizeof(intel_dp->psr_dpcd)); 3328 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { 3329 dev_priv->psr.sink_support = true; 3330 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); 3331 } 3332 } 3333 3334 /* Training Pattern 3 support */ 3335 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && 3336 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) { 3337 intel_dp->use_tps3 = true; 3338 DRM_DEBUG_KMS("Displayport TPS3 supported"); 3339 } else 3340 intel_dp->use_tps3 = false; 3341 3342 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 3343 DP_DWN_STRM_PORT_PRESENT)) 3344 return true; /* native DP sink */ 3345 3346 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) 3347 return true; /* no per-port downstream info */ 3348 3349 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, 3350 intel_dp->downstream_ports, 3351 DP_MAX_DOWNSTREAM_PORTS) < 0) 3352 return false; /* downstream port status fetch failed */ 3353 3354 return true; 3355} 3356 3357static void 3358intel_dp_probe_oui(struct intel_dp *intel_dp) 3359{ 3360 u8 buf[3]; 3361 3362 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 3363 return; 3364 3365 intel_edp_panel_vdd_on(intel_dp); 3366 3367 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) 3368 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 3369 buf[0], buf[1], buf[2]); 3370 3371 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) 3372 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 3373 buf[0], buf[1], buf[2]); 3374 3375 edp_panel_vdd_off(intel_dp, false); 3376} 3377 3378static bool 3379intel_dp_probe_mst(struct intel_dp *intel_dp) 3380{ 3381 u8 buf[1]; 3382 3383 if (!intel_dp->can_mst) 3384 return false; 3385 3386 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) 3387 return false; 3388 3389 _edp_panel_vdd_on(intel_dp); 3390 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) { 3391 if (buf[0] & DP_MST_CAP) { 3392 DRM_DEBUG_KMS("Sink is MST capable\n"); 3393 intel_dp->is_mst = true; 3394 } else { 3395 DRM_DEBUG_KMS("Sink is not MST capable\n"); 3396 intel_dp->is_mst = false; 3397 } 3398 } 3399 edp_panel_vdd_off(intel_dp, false); 3400 3401 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); 3402 return intel_dp->is_mst; 3403} 3404 3405int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) 3406{ 3407 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3408 struct drm_device *dev = intel_dig_port->base.base.dev; 3409 struct intel_crtc *intel_crtc = 3410 to_intel_crtc(intel_dig_port->base.base.crtc); 3411 u8 buf[1]; 3412 3413 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0) 3414 return -EAGAIN; 3415 3416 if (!(buf[0] & DP_TEST_CRC_SUPPORTED)) 3417 return -ENOTTY; 3418 3419 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 3420 DP_TEST_SINK_START) < 0) 3421 return -EAGAIN; 3422 3423 /* Wait 2 vblanks to be sure we will have the correct CRC value */ 3424 intel_wait_for_vblank(dev, intel_crtc->pipe); 3425 intel_wait_for_vblank(dev, intel_crtc->pipe); 3426 3427 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) 3428 return -EAGAIN; 3429 3430 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0); 3431 return 0; 3432} 3433 3434static bool 3435intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) 3436{ 3437 return intel_dp_dpcd_read_wake(&intel_dp->aux, 3438 DP_DEVICE_SERVICE_IRQ_VECTOR, 3439 sink_irq_vector, 1) == 1; 3440} 3441 3442static bool 3443intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) 3444{ 3445 int ret; 3446 3447 ret = intel_dp_dpcd_read_wake(&intel_dp->aux, 3448 DP_SINK_COUNT_ESI, 3449 sink_irq_vector, 14); 3450 if (ret != 14) 3451 return false; 3452 3453 return true; 3454} 3455 3456static void 3457intel_dp_handle_test_request(struct intel_dp *intel_dp) 3458{ 3459 /* NAK by default */ 3460 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK); 3461} 3462 3463static int 3464intel_dp_check_mst_status(struct intel_dp *intel_dp) 3465{ 3466 bool bret; 3467 3468 if (intel_dp->is_mst) { 3469 u8 esi[16] = { 0 }; 3470 int ret = 0; 3471 int retry; 3472 bool handled; 3473 bret = intel_dp_get_sink_irq_esi(intel_dp, esi); 3474go_again: 3475 if (bret == true) { 3476 3477 /* check link status - esi[10] = 0x200c */ 3478 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { 3479 DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); 3480 intel_dp_start_link_train(intel_dp); 3481 intel_dp_complete_link_train(intel_dp); 3482 intel_dp_stop_link_train(intel_dp); 3483 } 3484 3485 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]); 3486 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); 3487 3488 if (handled) { 3489 for (retry = 0; retry < 3; retry++) { 3490 int wret; 3491 wret = drm_dp_dpcd_write(&intel_dp->aux, 3492 DP_SINK_COUNT_ESI+1, 3493 &esi[1], 3); 3494 if (wret == 3) { 3495 break; 3496 } 3497 } 3498 3499 bret = intel_dp_get_sink_irq_esi(intel_dp, esi); 3500 if (bret == true) { 3501 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]); 3502 goto go_again; 3503 } 3504 } else 3505 ret = 0; 3506 3507 return ret; 3508 } else { 3509 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3510 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); 3511 intel_dp->is_mst = false; 3512 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); 3513 /* send a hotplug event */ 3514 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); 3515 } 3516 } 3517 return -EINVAL; 3518} 3519 3520/* 3521 * According to DP spec 3522 * 5.1.2: 3523 * 1. Read DPCD 3524 * 2. Configure link according to Receiver Capabilities 3525 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 3526 * 4. Check link status on receipt of hot-plug interrupt 3527 */ 3528void 3529intel_dp_check_link_status(struct intel_dp *intel_dp) 3530{ 3531 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 3532 u8 sink_irq_vector; 3533 u8 link_status[DP_LINK_STATUS_SIZE]; 3534 3535 /* FIXME: This access isn't protected by any locks. */ 3536 if (!intel_encoder->connectors_active) 3537 return; 3538 3539 if (WARN_ON(!intel_encoder->base.crtc)) 3540 return; 3541 3542 /* Try to read receiver status if the link appears to be up */ 3543 if (!intel_dp_get_link_status(intel_dp, link_status)) { 3544 return; 3545 } 3546 3547 /* Now read the DPCD to see if it's actually running */ 3548 if (!intel_dp_get_dpcd(intel_dp)) { 3549 return; 3550 } 3551 3552 /* Try to read the source of the interrupt */ 3553 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 3554 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { 3555 /* Clear interrupt source */ 3556 drm_dp_dpcd_writeb(&intel_dp->aux, 3557 DP_DEVICE_SERVICE_IRQ_VECTOR, 3558 sink_irq_vector); 3559 3560 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) 3561 intel_dp_handle_test_request(intel_dp); 3562 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) 3563 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); 3564 } 3565 3566 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { 3567 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", 3568 intel_encoder->base.name); 3569 intel_dp_start_link_train(intel_dp); 3570 intel_dp_complete_link_train(intel_dp); 3571 intel_dp_stop_link_train(intel_dp); 3572 } 3573} 3574 3575/* XXX this is probably wrong for multiple downstream ports */ 3576static enum drm_connector_status 3577intel_dp_detect_dpcd(struct intel_dp *intel_dp) 3578{ 3579 uint8_t *dpcd = intel_dp->dpcd; 3580 uint8_t type; 3581 3582 if (!intel_dp_get_dpcd(intel_dp)) 3583 return connector_status_disconnected; 3584 3585 /* if there's no downstream port, we're done */ 3586 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) 3587 return connector_status_connected; 3588 3589 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 3590 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 3591 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { 3592 uint8_t reg; 3593 3594 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, 3595 ®, 1) < 0) 3596 return connector_status_unknown; 3597 3598 return DP_GET_SINK_COUNT(reg) ? connector_status_connected 3599 : connector_status_disconnected; 3600 } 3601 3602 /* If no HPD, poke DDC gently */ 3603 if (drm_probe_ddc(&intel_dp->aux.ddc)) 3604 return connector_status_connected; 3605 3606 /* Well we tried, say unknown for unreliable port types */ 3607 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 3608 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 3609 if (type == DP_DS_PORT_TYPE_VGA || 3610 type == DP_DS_PORT_TYPE_NON_EDID) 3611 return connector_status_unknown; 3612 } else { 3613 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 3614 DP_DWN_STRM_PORT_TYPE_MASK; 3615 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || 3616 type == DP_DWN_STRM_PORT_TYPE_OTHER) 3617 return connector_status_unknown; 3618 } 3619 3620 /* Anything else is out of spec, warn and ignore */ 3621 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); 3622 return connector_status_disconnected; 3623} 3624 3625static enum drm_connector_status 3626ironlake_dp_detect(struct intel_dp *intel_dp) 3627{ 3628 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3629 struct drm_i915_private *dev_priv = dev->dev_private; 3630 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3631 enum drm_connector_status status; 3632 3633 /* Can't disconnect eDP, but you can close the lid... */ 3634 if (is_edp(intel_dp)) { 3635 status = intel_panel_detect(dev); 3636 if (status == connector_status_unknown) 3637 status = connector_status_connected; 3638 return status; 3639 } 3640 3641 if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) 3642 return connector_status_disconnected; 3643 3644 return intel_dp_detect_dpcd(intel_dp); 3645} 3646 3647static enum drm_connector_status 3648g4x_dp_detect(struct intel_dp *intel_dp) 3649{ 3650 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3651 struct drm_i915_private *dev_priv = dev->dev_private; 3652 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3653 uint32_t bit; 3654 3655 /* Can't disconnect eDP, but you can close the lid... */ 3656 if (is_edp(intel_dp)) { 3657 enum drm_connector_status status; 3658 3659 status = intel_panel_detect(dev); 3660 if (status == connector_status_unknown) 3661 status = connector_status_connected; 3662 return status; 3663 } 3664 3665 if (IS_VALLEYVIEW(dev)) { 3666 switch (intel_dig_port->port) { 3667 case PORT_B: 3668 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV; 3669 break; 3670 case PORT_C: 3671 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV; 3672 break; 3673 case PORT_D: 3674 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; 3675 break; 3676 default: 3677 return connector_status_unknown; 3678 } 3679 } else { 3680 switch (intel_dig_port->port) { 3681 case PORT_B: 3682 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; 3683 break; 3684 case PORT_C: 3685 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; 3686 break; 3687 case PORT_D: 3688 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; 3689 break; 3690 default: 3691 return connector_status_unknown; 3692 } 3693 } 3694 3695 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) 3696 return connector_status_disconnected; 3697 3698 return intel_dp_detect_dpcd(intel_dp); 3699} 3700 3701static struct edid * 3702intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) 3703{ 3704 struct intel_connector *intel_connector = to_intel_connector(connector); 3705 3706 /* use cached edid if we have one */ 3707 if (intel_connector->edid) { 3708 /* invalid edid */ 3709 if (IS_ERR(intel_connector->edid)) 3710 return NULL; 3711 3712 return drm_edid_duplicate(intel_connector->edid); 3713 } 3714 3715 return drm_get_edid(connector, adapter); 3716} 3717 3718static int 3719intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) 3720{ 3721 struct intel_connector *intel_connector = to_intel_connector(connector); 3722 3723 /* use cached edid if we have one */ 3724 if (intel_connector->edid) { 3725 /* invalid edid */ 3726 if (IS_ERR(intel_connector->edid)) 3727 return 0; 3728 3729 return intel_connector_update_modes(connector, 3730 intel_connector->edid); 3731 } 3732 3733 return intel_ddc_get_modes(connector, adapter); 3734} 3735 3736static enum drm_connector_status 3737intel_dp_detect(struct drm_connector *connector, bool force) 3738{ 3739 struct intel_dp *intel_dp = intel_attached_dp(connector); 3740 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3741 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3742 struct drm_device *dev = connector->dev; 3743 struct drm_i915_private *dev_priv = dev->dev_private; 3744 enum drm_connector_status status; 3745 enum intel_display_power_domain power_domain; 3746 struct edid *edid = NULL; 3747 bool ret; 3748 3749 power_domain = intel_display_port_power_domain(intel_encoder); 3750 intel_display_power_get(dev_priv, power_domain); 3751 3752 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 3753 connector->base.id, connector->name); 3754 3755 if (intel_dp->is_mst) { 3756 /* MST devices are disconnected from a monitor POV */ 3757 if (intel_encoder->type != INTEL_OUTPUT_EDP) 3758 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 3759 status = connector_status_disconnected; 3760 goto out; 3761 } 3762 3763 intel_dp->has_audio = false; 3764 3765 if (HAS_PCH_SPLIT(dev)) 3766 status = ironlake_dp_detect(intel_dp); 3767 else 3768 status = g4x_dp_detect(intel_dp); 3769 3770 if (status != connector_status_connected) 3771 goto out; 3772 3773 intel_dp_probe_oui(intel_dp); 3774 3775 ret = intel_dp_probe_mst(intel_dp); 3776 if (ret) { 3777 /* if we are in MST mode then this connector 3778 won't appear connected or have anything with EDID on it */ 3779 if (intel_encoder->type != INTEL_OUTPUT_EDP) 3780 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 3781 status = connector_status_disconnected; 3782 goto out; 3783 } 3784 3785 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { 3786 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); 3787 } else { 3788 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc); 3789 if (edid) { 3790 intel_dp->has_audio = drm_detect_monitor_audio(edid); 3791 kfree(edid); 3792 } 3793 } 3794 3795 if (intel_encoder->type != INTEL_OUTPUT_EDP) 3796 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 3797 status = connector_status_connected; 3798 3799out: 3800 intel_display_power_put(dev_priv, power_domain); 3801 return status; 3802} 3803 3804static int intel_dp_get_modes(struct drm_connector *connector) 3805{ 3806 struct intel_dp *intel_dp = intel_attached_dp(connector); 3807 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3808 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3809 struct intel_connector *intel_connector = to_intel_connector(connector); 3810 struct drm_device *dev = connector->dev; 3811 struct drm_i915_private *dev_priv = dev->dev_private; 3812 enum intel_display_power_domain power_domain; 3813 int ret; 3814 3815 /* We should parse the EDID data and find out if it has an audio sink 3816 */ 3817 3818 power_domain = intel_display_port_power_domain(intel_encoder); 3819 intel_display_power_get(dev_priv, power_domain); 3820 3821 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc); 3822 intel_display_power_put(dev_priv, power_domain); 3823 if (ret) 3824 return ret; 3825 3826 /* if eDP has no EDID, fall back to fixed mode */ 3827 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 3828 struct drm_display_mode *mode; 3829 mode = drm_mode_duplicate(dev, 3830 intel_connector->panel.fixed_mode); 3831 if (mode) { 3832 drm_mode_probed_add(connector, mode); 3833 return 1; 3834 } 3835 } 3836 return 0; 3837} 3838 3839static bool 3840intel_dp_detect_audio(struct drm_connector *connector) 3841{ 3842 struct intel_dp *intel_dp = intel_attached_dp(connector); 3843 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3844 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3845 struct drm_device *dev = connector->dev; 3846 struct drm_i915_private *dev_priv = dev->dev_private; 3847 enum intel_display_power_domain power_domain; 3848 struct edid *edid; 3849 bool has_audio = false; 3850 3851 power_domain = intel_display_port_power_domain(intel_encoder); 3852 intel_display_power_get(dev_priv, power_domain); 3853 3854 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc); 3855 if (edid) { 3856 has_audio = drm_detect_monitor_audio(edid); 3857 kfree(edid); 3858 } 3859 3860 intel_display_power_put(dev_priv, power_domain); 3861 3862 return has_audio; 3863} 3864 3865static int 3866intel_dp_set_property(struct drm_connector *connector, 3867 struct drm_property *property, 3868 uint64_t val) 3869{ 3870 struct drm_i915_private *dev_priv = connector->dev->dev_private; 3871 struct intel_connector *intel_connector = to_intel_connector(connector); 3872 struct intel_encoder *intel_encoder = intel_attached_encoder(connector); 3873 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 3874 int ret; 3875 3876 ret = drm_object_property_set_value(&connector->base, property, val); 3877 if (ret) 3878 return ret; 3879 3880 if (property == dev_priv->force_audio_property) { 3881 int i = val; 3882 bool has_audio; 3883 3884 if (i == intel_dp->force_audio) 3885 return 0; 3886 3887 intel_dp->force_audio = i; 3888 3889 if (i == HDMI_AUDIO_AUTO) 3890 has_audio = intel_dp_detect_audio(connector); 3891 else 3892 has_audio = (i == HDMI_AUDIO_ON); 3893 3894 if (has_audio == intel_dp->has_audio) 3895 return 0; 3896 3897 intel_dp->has_audio = has_audio; 3898 goto done; 3899 } 3900 3901 if (property == dev_priv->broadcast_rgb_property) { 3902 bool old_auto = intel_dp->color_range_auto; 3903 uint32_t old_range = intel_dp->color_range; 3904 3905 switch (val) { 3906 case INTEL_BROADCAST_RGB_AUTO: 3907 intel_dp->color_range_auto = true; 3908 break; 3909 case INTEL_BROADCAST_RGB_FULL: 3910 intel_dp->color_range_auto = false; 3911 intel_dp->color_range = 0; 3912 break; 3913 case INTEL_BROADCAST_RGB_LIMITED: 3914 intel_dp->color_range_auto = false; 3915 intel_dp->color_range = DP_COLOR_RANGE_16_235; 3916 break; 3917 default: 3918 return -EINVAL; 3919 } 3920 3921 if (old_auto == intel_dp->color_range_auto && 3922 old_range == intel_dp->color_range) 3923 return 0; 3924 3925 goto done; 3926 } 3927 3928 if (is_edp(intel_dp) && 3929 property == connector->dev->mode_config.scaling_mode_property) { 3930 if (val == DRM_MODE_SCALE_NONE) { 3931 DRM_DEBUG_KMS("no scaling not supported\n"); 3932 return -EINVAL; 3933 } 3934 3935 if (intel_connector->panel.fitting_mode == val) { 3936 /* the eDP scaling property is not changed */ 3937 return 0; 3938 } 3939 intel_connector->panel.fitting_mode = val; 3940 3941 goto done; 3942 } 3943 3944 return -EINVAL; 3945 3946done: 3947 if (intel_encoder->base.crtc) 3948 intel_crtc_restore_mode(intel_encoder->base.crtc); 3949 3950 return 0; 3951} 3952 3953static void 3954intel_dp_connector_destroy(struct drm_connector *connector) 3955{ 3956 struct intel_connector *intel_connector = to_intel_connector(connector); 3957 3958 if (!IS_ERR_OR_NULL(intel_connector->edid)) 3959 kfree(intel_connector->edid); 3960 3961 /* Can't call is_edp() since the encoder may have been destroyed 3962 * already. */ 3963 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3964 intel_panel_fini(&intel_connector->panel); 3965 3966 drm_connector_cleanup(connector); 3967 kfree(connector); 3968} 3969 3970void intel_dp_encoder_destroy(struct drm_encoder *encoder) 3971{ 3972 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 3973 struct intel_dp *intel_dp = &intel_dig_port->dp; 3974 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3975 3976 drm_dp_aux_unregister(&intel_dp->aux); 3977 intel_dp_mst_encoder_cleanup(intel_dig_port); 3978 drm_encoder_cleanup(encoder); 3979 if (is_edp(intel_dp)) { 3980 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 3981 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 3982 edp_panel_vdd_off_sync(intel_dp); 3983 drm_modeset_unlock(&dev->mode_config.connection_mutex); 3984 if (intel_dp->edp_notifier.notifier_call) { 3985 unregister_reboot_notifier(&intel_dp->edp_notifier); 3986 intel_dp->edp_notifier.notifier_call = NULL; 3987 } 3988 } 3989 kfree(intel_dig_port); 3990} 3991 3992static void intel_dp_encoder_reset(struct drm_encoder *encoder) 3993{ 3994 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder)); 3995} 3996 3997static const struct drm_connector_funcs intel_dp_connector_funcs = { 3998 .dpms = intel_connector_dpms, 3999 .detect = intel_dp_detect, 4000 .fill_modes = drm_helper_probe_single_connector_modes, 4001 .set_property = intel_dp_set_property, 4002 .destroy = intel_dp_connector_destroy, 4003}; 4004 4005static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 4006 .get_modes = intel_dp_get_modes, 4007 .mode_valid = intel_dp_mode_valid, 4008 .best_encoder = intel_best_encoder, 4009}; 4010 4011static const struct drm_encoder_funcs intel_dp_enc_funcs = { 4012 .reset = intel_dp_encoder_reset, 4013 .destroy = intel_dp_encoder_destroy, 4014}; 4015 4016void 4017intel_dp_hot_plug(struct intel_encoder *intel_encoder) 4018{ 4019 return; 4020} 4021 4022bool 4023intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) 4024{ 4025 struct intel_dp *intel_dp = &intel_dig_port->dp; 4026 struct drm_device *dev = intel_dig_port->base.base.dev; 4027 struct drm_i915_private *dev_priv = dev->dev_private; 4028 int ret; 4029 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP) 4030 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; 4031 4032 DRM_DEBUG_KMS("got hpd irq on port %d - %s\n", intel_dig_port->port, 4033 long_hpd ? "long" : "short"); 4034 4035 if (long_hpd) { 4036 if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) 4037 goto mst_fail; 4038 4039 if (!intel_dp_get_dpcd(intel_dp)) { 4040 goto mst_fail; 4041 } 4042 4043 intel_dp_probe_oui(intel_dp); 4044 4045 if (!intel_dp_probe_mst(intel_dp)) 4046 goto mst_fail; 4047 4048 } else { 4049 if (intel_dp->is_mst) { 4050 ret = intel_dp_check_mst_status(intel_dp); 4051 if (ret == -EINVAL) 4052 goto mst_fail; 4053 } 4054 4055 if (!intel_dp->is_mst) { 4056 /* 4057 * we'll check the link status via the normal hot plug path later - 4058 * but for short hpds we should check it now 4059 */ 4060 intel_dp_check_link_status(intel_dp); 4061 } 4062 } 4063 return false; 4064mst_fail: 4065 /* if we were in MST mode, and device is not there get out of MST mode */ 4066 if (intel_dp->is_mst) { 4067 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state); 4068 intel_dp->is_mst = false; 4069 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); 4070 } 4071 return true; 4072} 4073 4074/* Return which DP Port should be selected for Transcoder DP control */ 4075int 4076intel_trans_dp_port_sel(struct drm_crtc *crtc) 4077{ 4078 struct drm_device *dev = crtc->dev; 4079 struct intel_encoder *intel_encoder; 4080 struct intel_dp *intel_dp; 4081 4082 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 4083 intel_dp = enc_to_intel_dp(&intel_encoder->base); 4084 4085 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || 4086 intel_encoder->type == INTEL_OUTPUT_EDP) 4087 return intel_dp->output_reg; 4088 } 4089 4090 return -1; 4091} 4092 4093/* check the VBT to see whether the eDP is on DP-D port */ 4094bool intel_dp_is_edp(struct drm_device *dev, enum port port) 4095{ 4096 struct drm_i915_private *dev_priv = dev->dev_private; 4097 union child_device_config *p_child; 4098 int i; 4099 static const short port_mapping[] = { 4100 [PORT_B] = PORT_IDPB, 4101 [PORT_C] = PORT_IDPC, 4102 [PORT_D] = PORT_IDPD, 4103 }; 4104 4105 if (port == PORT_A) 4106 return true; 4107 4108 if (!dev_priv->vbt.child_dev_num) 4109 return false; 4110 4111 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { 4112 p_child = dev_priv->vbt.child_dev + i; 4113 4114 if (p_child->common.dvo_port == port_mapping[port] && 4115 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == 4116 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) 4117 return true; 4118 } 4119 return false; 4120} 4121 4122void 4123intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 4124{ 4125 struct intel_connector *intel_connector = to_intel_connector(connector); 4126 4127 intel_attach_force_audio_property(connector); 4128 intel_attach_broadcast_rgb_property(connector); 4129 intel_dp->color_range_auto = true; 4130 4131 if (is_edp(intel_dp)) { 4132 drm_mode_create_scaling_mode_property(connector->dev); 4133 drm_object_attach_property( 4134 &connector->base, 4135 connector->dev->mode_config.scaling_mode_property, 4136 DRM_MODE_SCALE_ASPECT); 4137 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; 4138 } 4139} 4140 4141static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) 4142{ 4143 intel_dp->last_power_cycle = jiffies; 4144 intel_dp->last_power_on = jiffies; 4145 intel_dp->last_backlight_off = jiffies; 4146} 4147 4148static void 4149intel_dp_init_panel_power_sequencer(struct drm_device *dev, 4150 struct intel_dp *intel_dp, 4151 struct edp_power_seq *out) 4152{ 4153 struct drm_i915_private *dev_priv = dev->dev_private; 4154 struct edp_power_seq cur, vbt, spec, final; 4155 u32 pp_on, pp_off, pp_div, pp; 4156 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; 4157 4158 if (HAS_PCH_SPLIT(dev)) { 4159 pp_ctrl_reg = PCH_PP_CONTROL; 4160 pp_on_reg = PCH_PP_ON_DELAYS; 4161 pp_off_reg = PCH_PP_OFF_DELAYS; 4162 pp_div_reg = PCH_PP_DIVISOR; 4163 } else { 4164 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); 4165 4166 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); 4167 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); 4168 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); 4169 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 4170 } 4171 4172 /* Workaround: Need to write PP_CONTROL with the unlock key as 4173 * the very first thing. */ 4174 pp = ironlake_get_pp_control(intel_dp); 4175 I915_WRITE(pp_ctrl_reg, pp); 4176 4177 pp_on = I915_READ(pp_on_reg); 4178 pp_off = I915_READ(pp_off_reg); 4179 pp_div = I915_READ(pp_div_reg); 4180 4181 /* Pull timing values out of registers */ 4182 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> 4183 PANEL_POWER_UP_DELAY_SHIFT; 4184 4185 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> 4186 PANEL_LIGHT_ON_DELAY_SHIFT; 4187 4188 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> 4189 PANEL_LIGHT_OFF_DELAY_SHIFT; 4190 4191 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> 4192 PANEL_POWER_DOWN_DELAY_SHIFT; 4193 4194 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> 4195 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; 4196 4197 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 4198 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); 4199 4200 vbt = dev_priv->vbt.edp_pps; 4201 4202 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of 4203 * our hw here, which are all in 100usec. */ 4204 spec.t1_t3 = 210 * 10; 4205 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ 4206 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ 4207 spec.t10 = 500 * 10; 4208 /* This one is special and actually in units of 100ms, but zero 4209 * based in the hw (so we need to add 100 ms). But the sw vbt 4210 * table multiplies it with 1000 to make it in units of 100usec, 4211 * too. */ 4212 spec.t11_t12 = (510 + 100) * 10; 4213 4214 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 4215 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); 4216 4217 /* Use the max of the register settings and vbt. If both are 4218 * unset, fall back to the spec limits. */ 4219#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ 4220 spec.field : \ 4221 max(cur.field, vbt.field)) 4222 assign_final(t1_t3); 4223 assign_final(t8); 4224 assign_final(t9); 4225 assign_final(t10); 4226 assign_final(t11_t12); 4227#undef assign_final 4228 4229#define get_delay(field) (DIV_ROUND_UP(final.field, 10)) 4230 intel_dp->panel_power_up_delay = get_delay(t1_t3); 4231 intel_dp->backlight_on_delay = get_delay(t8); 4232 intel_dp->backlight_off_delay = get_delay(t9); 4233 intel_dp->panel_power_down_delay = get_delay(t10); 4234 intel_dp->panel_power_cycle_delay = get_delay(t11_t12); 4235#undef get_delay 4236 4237 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", 4238 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, 4239 intel_dp->panel_power_cycle_delay); 4240 4241 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", 4242 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); 4243 4244 if (out) 4245 *out = final; 4246} 4247 4248static void 4249intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 4250 struct intel_dp *intel_dp, 4251 struct edp_power_seq *seq) 4252{ 4253 struct drm_i915_private *dev_priv = dev->dev_private; 4254 u32 pp_on, pp_off, pp_div, port_sel = 0; 4255 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); 4256 int pp_on_reg, pp_off_reg, pp_div_reg; 4257 4258 if (HAS_PCH_SPLIT(dev)) { 4259 pp_on_reg = PCH_PP_ON_DELAYS; 4260 pp_off_reg = PCH_PP_OFF_DELAYS; 4261 pp_div_reg = PCH_PP_DIVISOR; 4262 } else { 4263 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); 4264 4265 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); 4266 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); 4267 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 4268 } 4269 4270 /* 4271 * And finally store the new values in the power sequencer. The 4272 * backlight delays are set to 1 because we do manual waits on them. For 4273 * T8, even BSpec recommends doing it. For T9, if we don't do this, 4274 * we'll end up waiting for the backlight off delay twice: once when we 4275 * do the manual sleep, and once when we disable the panel and wait for 4276 * the PP_STATUS bit to become zero. 4277 */ 4278 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | 4279 (1 << PANEL_LIGHT_ON_DELAY_SHIFT); 4280 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | 4281 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); 4282 /* Compute the divisor for the pp clock, simply match the Bspec 4283 * formula. */ 4284 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; 4285 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) 4286 << PANEL_POWER_CYCLE_DELAY_SHIFT); 4287 4288 /* Haswell doesn't have any port selection bits for the panel 4289 * power sequencer any more. */ 4290 if (IS_VALLEYVIEW(dev)) { 4291 if (dp_to_dig_port(intel_dp)->port == PORT_B) 4292 port_sel = PANEL_PORT_SELECT_DPB_VLV; 4293 else 4294 port_sel = PANEL_PORT_SELECT_DPC_VLV; 4295 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { 4296 if (dp_to_dig_port(intel_dp)->port == PORT_A) 4297 port_sel = PANEL_PORT_SELECT_DPA; 4298 else 4299 port_sel = PANEL_PORT_SELECT_DPD; 4300 } 4301 4302 pp_on |= port_sel; 4303 4304 I915_WRITE(pp_on_reg, pp_on); 4305 I915_WRITE(pp_off_reg, pp_off); 4306 I915_WRITE(pp_div_reg, pp_div); 4307 4308 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", 4309 I915_READ(pp_on_reg), 4310 I915_READ(pp_off_reg), 4311 I915_READ(pp_div_reg)); 4312} 4313 4314void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) 4315{ 4316 struct drm_i915_private *dev_priv = dev->dev_private; 4317 struct intel_encoder *encoder; 4318 struct intel_dp *intel_dp = NULL; 4319 struct intel_crtc_config *config = NULL; 4320 struct intel_crtc *intel_crtc = NULL; 4321 struct intel_connector *intel_connector = dev_priv->drrs.connector; 4322 u32 reg, val; 4323 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR; 4324 4325 if (refresh_rate <= 0) { 4326 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); 4327 return; 4328 } 4329 4330 if (intel_connector == NULL) { 4331 DRM_DEBUG_KMS("DRRS supported for eDP only.\n"); 4332 return; 4333 } 4334 4335 /* 4336 * FIXME: This needs proper synchronization with psr state. But really 4337 * hard to tell without seeing the user of this function of this code. 4338 * Check locking and ordering once that lands. 4339 */ 4340 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) { 4341 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n"); 4342 return; 4343 } 4344 4345 encoder = intel_attached_encoder(&intel_connector->base); 4346 intel_dp = enc_to_intel_dp(&encoder->base); 4347 intel_crtc = encoder->new_crtc; 4348 4349 if (!intel_crtc) { 4350 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); 4351 return; 4352 } 4353 4354 config = &intel_crtc->config; 4355 4356 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) { 4357 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); 4358 return; 4359 } 4360 4361 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate) 4362 index = DRRS_LOW_RR; 4363 4364 if (index == intel_dp->drrs_state.refresh_rate_type) { 4365 DRM_DEBUG_KMS( 4366 "DRRS requested for previously set RR...ignoring\n"); 4367 return; 4368 } 4369 4370 if (!intel_crtc->active) { 4371 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); 4372 return; 4373 } 4374 4375 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) { 4376 reg = PIPECONF(intel_crtc->config.cpu_transcoder); 4377 val = I915_READ(reg); 4378 if (index > DRRS_HIGH_RR) { 4379 val |= PIPECONF_EDP_RR_MODE_SWITCH; 4380 intel_dp_set_m_n(intel_crtc); 4381 } else { 4382 val &= ~PIPECONF_EDP_RR_MODE_SWITCH; 4383 } 4384 I915_WRITE(reg, val); 4385 } 4386 4387 /* 4388 * mutex taken to ensure that there is no race between differnt 4389 * drrs calls trying to update refresh rate. This scenario may occur 4390 * in future when idleness detection based DRRS in kernel and 4391 * possible calls from user space to set differnt RR are made. 4392 */ 4393 4394 mutex_lock(&intel_dp->drrs_state.mutex); 4395 4396 intel_dp->drrs_state.refresh_rate_type = index; 4397 4398 mutex_unlock(&intel_dp->drrs_state.mutex); 4399 4400 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); 4401} 4402 4403static struct drm_display_mode * 4404intel_dp_drrs_init(struct intel_digital_port *intel_dig_port, 4405 struct intel_connector *intel_connector, 4406 struct drm_display_mode *fixed_mode) 4407{ 4408 struct drm_connector *connector = &intel_connector->base; 4409 struct intel_dp *intel_dp = &intel_dig_port->dp; 4410 struct drm_device *dev = intel_dig_port->base.base.dev; 4411 struct drm_i915_private *dev_priv = dev->dev_private; 4412 struct drm_display_mode *downclock_mode = NULL; 4413 4414 if (INTEL_INFO(dev)->gen <= 6) { 4415 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); 4416 return NULL; 4417 } 4418 4419 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { 4420 DRM_INFO("VBT doesn't support DRRS\n"); 4421 return NULL; 4422 } 4423 4424 downclock_mode = intel_find_panel_downclock 4425 (dev, fixed_mode, connector); 4426 4427 if (!downclock_mode) { 4428 DRM_INFO("DRRS not supported\n"); 4429 return NULL; 4430 } 4431 4432 dev_priv->drrs.connector = intel_connector; 4433 4434 mutex_init(&intel_dp->drrs_state.mutex); 4435 4436 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type; 4437 4438 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR; 4439 DRM_INFO("seamless DRRS supported for eDP panel.\n"); 4440 return downclock_mode; 4441} 4442 4443void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder) 4444{ 4445 struct drm_device *dev = intel_encoder->base.dev; 4446 struct drm_i915_private *dev_priv = dev->dev_private; 4447 struct intel_dp *intel_dp; 4448 enum intel_display_power_domain power_domain; 4449 4450 if (intel_encoder->type != INTEL_OUTPUT_EDP) 4451 return; 4452 4453 intel_dp = enc_to_intel_dp(&intel_encoder->base); 4454 if (!edp_have_panel_vdd(intel_dp)) 4455 return; 4456 /* 4457 * The VDD bit needs a power domain reference, so if the bit is 4458 * already enabled when we boot or resume, grab this reference and 4459 * schedule a vdd off, so we don't hold on to the reference 4460 * indefinitely. 4461 */ 4462 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); 4463 power_domain = intel_display_port_power_domain(intel_encoder); 4464 intel_display_power_get(dev_priv, power_domain); 4465 4466 edp_panel_vdd_schedule_off(intel_dp); 4467} 4468 4469static bool intel_edp_init_connector(struct intel_dp *intel_dp, 4470 struct intel_connector *intel_connector, 4471 struct edp_power_seq *power_seq) 4472{ 4473 struct drm_connector *connector = &intel_connector->base; 4474 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 4475 struct intel_encoder *intel_encoder = &intel_dig_port->base; 4476 struct drm_device *dev = intel_encoder->base.dev; 4477 struct drm_i915_private *dev_priv = dev->dev_private; 4478 struct drm_display_mode *fixed_mode = NULL; 4479 struct drm_display_mode *downclock_mode = NULL; 4480 bool has_dpcd; 4481 struct drm_display_mode *scan; 4482 struct edid *edid; 4483 4484 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED; 4485 4486 if (!is_edp(intel_dp)) 4487 return true; 4488 4489 intel_edp_panel_vdd_sanitize(intel_encoder); 4490 4491 /* Cache DPCD and EDID for edp. */ 4492 intel_edp_panel_vdd_on(intel_dp); 4493 has_dpcd = intel_dp_get_dpcd(intel_dp); 4494 edp_panel_vdd_off(intel_dp, false); 4495 4496 if (has_dpcd) { 4497 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) 4498 dev_priv->no_aux_handshake = 4499 intel_dp->dpcd[DP_MAX_DOWNSPREAD] & 4500 DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 4501 } else { 4502 /* if this fails, presume the device is a ghost */ 4503 DRM_INFO("failed to retrieve link info, disabling eDP\n"); 4504 return false; 4505 } 4506 4507 /* We now know it's not a ghost, init power sequence regs. */ 4508 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq); 4509 4510 mutex_lock(&dev->mode_config.mutex); 4511 edid = drm_get_edid(connector, &intel_dp->aux.ddc); 4512 if (edid) { 4513 if (drm_add_edid_modes(connector, edid)) { 4514 drm_mode_connector_update_edid_property(connector, 4515 edid); 4516 drm_edid_to_eld(connector, edid); 4517 } else { 4518 kfree(edid); 4519 edid = ERR_PTR(-EINVAL); 4520 } 4521 } else { 4522 edid = ERR_PTR(-ENOENT); 4523 } 4524 intel_connector->edid = edid; 4525 4526 /* prefer fixed mode from EDID if available */ 4527 list_for_each_entry(scan, &connector->probed_modes, head) { 4528 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { 4529 fixed_mode = drm_mode_duplicate(dev, scan); 4530 downclock_mode = intel_dp_drrs_init( 4531 intel_dig_port, 4532 intel_connector, fixed_mode); 4533 break; 4534 } 4535 } 4536 4537 /* fallback to VBT if available for eDP */ 4538 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { 4539 fixed_mode = drm_mode_duplicate(dev, 4540 dev_priv->vbt.lfp_lvds_vbt_mode); 4541 if (fixed_mode) 4542 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 4543 } 4544 mutex_unlock(&dev->mode_config.mutex); 4545 4546 if (IS_VALLEYVIEW(dev)) { 4547 intel_dp->edp_notifier.notifier_call = edp_notify_handler; 4548 register_reboot_notifier(&intel_dp->edp_notifier); 4549 } 4550 4551 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); 4552 intel_panel_setup_backlight(connector); 4553 4554 return true; 4555} 4556 4557bool 4558intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 4559 struct intel_connector *intel_connector) 4560{ 4561 struct drm_connector *connector = &intel_connector->base; 4562 struct intel_dp *intel_dp = &intel_dig_port->dp; 4563 struct intel_encoder *intel_encoder = &intel_dig_port->base; 4564 struct drm_device *dev = intel_encoder->base.dev; 4565 struct drm_i915_private *dev_priv = dev->dev_private; 4566 enum port port = intel_dig_port->port; 4567 struct edp_power_seq power_seq = { 0 }; 4568 int type; 4569 4570 /* intel_dp vfuncs */ 4571 if (IS_VALLEYVIEW(dev)) 4572 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; 4573 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 4574 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; 4575 else if (HAS_PCH_SPLIT(dev)) 4576 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; 4577 else 4578 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; 4579 4580 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; 4581 4582 /* Preserve the current hw state. */ 4583 intel_dp->DP = I915_READ(intel_dp->output_reg); 4584 intel_dp->attached_connector = intel_connector; 4585 4586 if (intel_dp_is_edp(dev, port)) 4587 type = DRM_MODE_CONNECTOR_eDP; 4588 else 4589 type = DRM_MODE_CONNECTOR_DisplayPort; 4590 4591 /* 4592 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but 4593 * for DP the encoder type can be set by the caller to 4594 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. 4595 */ 4596 if (type == DRM_MODE_CONNECTOR_eDP) 4597 intel_encoder->type = INTEL_OUTPUT_EDP; 4598 4599 DRM_DEBUG_KMS("Adding %s connector on port %c\n", 4600 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", 4601 port_name(port)); 4602 4603 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 4604 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 4605 4606 connector->interlace_allowed = true; 4607 connector->doublescan_allowed = 0; 4608 4609 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, 4610 edp_panel_vdd_work); 4611 4612 intel_connector_attach_encoder(intel_connector, intel_encoder); 4613 drm_connector_register(connector); 4614 4615 if (HAS_DDI(dev)) 4616 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 4617 else 4618 intel_connector->get_hw_state = intel_connector_get_hw_state; 4619 intel_connector->unregister = intel_dp_connector_unregister; 4620 4621 /* Set up the hotplug pin. */ 4622 switch (port) { 4623 case PORT_A: 4624 intel_encoder->hpd_pin = HPD_PORT_A; 4625 break; 4626 case PORT_B: 4627 intel_encoder->hpd_pin = HPD_PORT_B; 4628 break; 4629 case PORT_C: 4630 intel_encoder->hpd_pin = HPD_PORT_C; 4631 break; 4632 case PORT_D: 4633 intel_encoder->hpd_pin = HPD_PORT_D; 4634 break; 4635 default: 4636 BUG(); 4637 } 4638 4639 if (is_edp(intel_dp)) { 4640 intel_dp_init_panel_power_timestamps(intel_dp); 4641 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 4642 } 4643 4644 intel_dp_aux_init(intel_dp, intel_connector); 4645 4646 /* init MST on ports that can support it */ 4647 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 4648 if (port == PORT_B || port == PORT_C || port == PORT_D) { 4649 intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id); 4650 } 4651 } 4652 4653 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) { 4654 drm_dp_aux_unregister(&intel_dp->aux); 4655 if (is_edp(intel_dp)) { 4656 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 4657 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 4658 edp_panel_vdd_off_sync(intel_dp); 4659 drm_modeset_unlock(&dev->mode_config.connection_mutex); 4660 } 4661 drm_connector_unregister(connector); 4662 drm_connector_cleanup(connector); 4663 return false; 4664 } 4665 4666 intel_dp_add_properties(intel_dp, connector); 4667 4668 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 4669 * 0xd. Failure to do so will result in spurious interrupts being 4670 * generated on the port when a cable is not attached. 4671 */ 4672 if (IS_G4X(dev) && !IS_GM45(dev)) { 4673 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 4674 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 4675 } 4676 4677 return true; 4678} 4679 4680void 4681intel_dp_init(struct drm_device *dev, int output_reg, enum port port) 4682{ 4683 struct drm_i915_private *dev_priv = dev->dev_private; 4684 struct intel_digital_port *intel_dig_port; 4685 struct intel_encoder *intel_encoder; 4686 struct drm_encoder *encoder; 4687 struct intel_connector *intel_connector; 4688 4689 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 4690 if (!intel_dig_port) 4691 return; 4692 4693 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); 4694 if (!intel_connector) { 4695 kfree(intel_dig_port); 4696 return; 4697 } 4698 4699 intel_encoder = &intel_dig_port->base; 4700 encoder = &intel_encoder->base; 4701 4702 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, 4703 DRM_MODE_ENCODER_TMDS); 4704 4705 intel_encoder->compute_config = intel_dp_compute_config; 4706 intel_encoder->disable = intel_disable_dp; 4707 intel_encoder->get_hw_state = intel_dp_get_hw_state; 4708 intel_encoder->get_config = intel_dp_get_config; 4709 if (IS_CHERRYVIEW(dev)) { 4710 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; 4711 intel_encoder->pre_enable = chv_pre_enable_dp; 4712 intel_encoder->enable = vlv_enable_dp; 4713 intel_encoder->post_disable = chv_post_disable_dp; 4714 } else if (IS_VALLEYVIEW(dev)) { 4715 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; 4716 intel_encoder->pre_enable = vlv_pre_enable_dp; 4717 intel_encoder->enable = vlv_enable_dp; 4718 intel_encoder->post_disable = vlv_post_disable_dp; 4719 } else { 4720 intel_encoder->pre_enable = g4x_pre_enable_dp; 4721 intel_encoder->enable = g4x_enable_dp; 4722 intel_encoder->post_disable = g4x_post_disable_dp; 4723 } 4724 4725 intel_dig_port->port = port; 4726 intel_dig_port->dp.output_reg = output_reg; 4727 4728 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 4729 if (IS_CHERRYVIEW(dev)) { 4730 if (port == PORT_D) 4731 intel_encoder->crtc_mask = 1 << 2; 4732 else 4733 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 4734 } else { 4735 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 4736 } 4737 intel_encoder->cloneable = 0; 4738 intel_encoder->hot_plug = intel_dp_hot_plug; 4739 4740 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 4741 dev_priv->hpd_irq_port[port] = intel_dig_port; 4742 4743 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { 4744 drm_encoder_cleanup(encoder); 4745 kfree(intel_dig_port); 4746 kfree(intel_connector); 4747 } 4748} 4749 4750void intel_dp_mst_suspend(struct drm_device *dev) 4751{ 4752 struct drm_i915_private *dev_priv = dev->dev_private; 4753 int i; 4754 4755 /* disable MST */ 4756 for (i = 0; i < I915_MAX_PORTS; i++) { 4757 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i]; 4758 if (!intel_dig_port) 4759 continue; 4760 4761 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { 4762 if (!intel_dig_port->dp.can_mst) 4763 continue; 4764 if (intel_dig_port->dp.is_mst) 4765 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); 4766 } 4767 } 4768} 4769 4770void intel_dp_mst_resume(struct drm_device *dev) 4771{ 4772 struct drm_i915_private *dev_priv = dev->dev_private; 4773 int i; 4774 4775 for (i = 0; i < I915_MAX_PORTS; i++) { 4776 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i]; 4777 if (!intel_dig_port) 4778 continue; 4779 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { 4780 int ret; 4781 4782 if (!intel_dig_port->dp.can_mst) 4783 continue; 4784 4785 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); 4786 if (ret != 0) { 4787 intel_dp_check_mst_status(&intel_dig_port->dp); 4788 } 4789 } 4790 } 4791} 4792