1/* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2007 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 */ 28#include <linux/i2c.h> 29#include <linux/slab.h> 30#include <linux/delay.h> 31#include <linux/export.h> 32#include <drm/drmP.h> 33#include <drm/drm_crtc.h> 34#include <drm/drm_edid.h> 35#include "intel_drv.h" 36#include <drm/i915_drm.h> 37#include "i915_drv.h" 38#include "intel_sdvo_regs.h" 39 40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) 41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) 42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) 43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) 44 45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ 46 SDVO_TV_MASK) 47 48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK) 49#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) 50#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) 51#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) 52#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) 53 54 55static const char *tv_format_names[] = { 56 "NTSC_M" , "NTSC_J" , "NTSC_443", 57 "PAL_B" , "PAL_D" , "PAL_G" , 58 "PAL_H" , "PAL_I" , "PAL_M" , 59 "PAL_N" , "PAL_NC" , "PAL_60" , 60 "SECAM_B" , "SECAM_D" , "SECAM_G" , 61 "SECAM_K" , "SECAM_K1", "SECAM_L" , 62 "SECAM_60" 63}; 64 65#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) 66 67struct intel_sdvo { 68 struct intel_encoder base; 69 70 struct i2c_adapter *i2c; 71 u8 slave_addr; 72 73 struct i2c_adapter ddc; 74 75 /* Register for the SDVO device: SDVOB or SDVOC */ 76 uint32_t sdvo_reg; 77 78 /* Active outputs controlled by this SDVO output */ 79 uint16_t controlled_output; 80 81 /* 82 * Capabilities of the SDVO device returned by 83 * intel_sdvo_get_capabilities() 84 */ 85 struct intel_sdvo_caps caps; 86 87 /* Pixel clock limitations reported by the SDVO device, in kHz */ 88 int pixel_clock_min, pixel_clock_max; 89 90 /* 91 * For multiple function SDVO device, 92 * this is for current attached outputs. 93 */ 94 uint16_t attached_output; 95 96 /* 97 * Hotplug activation bits for this device 98 */ 99 uint16_t hotplug_active; 100 101 /** 102 * This is used to select the color range of RBG outputs in HDMI mode. 103 * It is only valid when using TMDS encoding and 8 bit per color mode. 104 */ 105 uint32_t color_range; 106 bool color_range_auto; 107 108 /** 109 * This is set if we're going to treat the device as TV-out. 110 * 111 * While we have these nice friendly flags for output types that ought 112 * to decide this for us, the S-Video output on our HDMI+S-Video card 113 * shows up as RGB1 (VGA). 114 */ 115 bool is_tv; 116 117 /* On different gens SDVOB is at different places. */ 118 bool is_sdvob; 119 120 /* This is for current tv format name */ 121 int tv_format_index; 122 123 /** 124 * This is set if we treat the device as HDMI, instead of DVI. 125 */ 126 bool is_hdmi; 127 bool has_hdmi_monitor; 128 bool has_hdmi_audio; 129 bool rgb_quant_range_selectable; 130 131 /** 132 * This is set if we detect output of sdvo device as LVDS and 133 * have a valid fixed mode to use with the panel. 134 */ 135 bool is_lvds; 136 137 /** 138 * This is sdvo fixed pannel mode pointer 139 */ 140 struct drm_display_mode *sdvo_lvds_fixed_mode; 141 142 /* DDC bus used by this SDVO encoder */ 143 uint8_t ddc_bus; 144 145 /* 146 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd 147 */ 148 uint8_t dtd_sdvo_flags; 149}; 150 151struct intel_sdvo_connector { 152 struct intel_connector base; 153 154 /* Mark the type of connector */ 155 uint16_t output_flag; 156 157 enum hdmi_force_audio force_audio; 158 159 /* This contains all current supported TV format */ 160 u8 tv_format_supported[TV_FORMAT_NUM]; 161 int format_supported_num; 162 struct drm_property *tv_format; 163 164 /* add the property for the SDVO-TV */ 165 struct drm_property *left; 166 struct drm_property *right; 167 struct drm_property *top; 168 struct drm_property *bottom; 169 struct drm_property *hpos; 170 struct drm_property *vpos; 171 struct drm_property *contrast; 172 struct drm_property *saturation; 173 struct drm_property *hue; 174 struct drm_property *sharpness; 175 struct drm_property *flicker_filter; 176 struct drm_property *flicker_filter_adaptive; 177 struct drm_property *flicker_filter_2d; 178 struct drm_property *tv_chroma_filter; 179 struct drm_property *tv_luma_filter; 180 struct drm_property *dot_crawl; 181 182 /* add the property for the SDVO-TV/LVDS */ 183 struct drm_property *brightness; 184 185 /* Add variable to record current setting for the above property */ 186 u32 left_margin, right_margin, top_margin, bottom_margin; 187 188 /* this is to get the range of margin.*/ 189 u32 max_hscan, max_vscan; 190 u32 max_hpos, cur_hpos; 191 u32 max_vpos, cur_vpos; 192 u32 cur_brightness, max_brightness; 193 u32 cur_contrast, max_contrast; 194 u32 cur_saturation, max_saturation; 195 u32 cur_hue, max_hue; 196 u32 cur_sharpness, max_sharpness; 197 u32 cur_flicker_filter, max_flicker_filter; 198 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; 199 u32 cur_flicker_filter_2d, max_flicker_filter_2d; 200 u32 cur_tv_chroma_filter, max_tv_chroma_filter; 201 u32 cur_tv_luma_filter, max_tv_luma_filter; 202 u32 cur_dot_crawl, max_dot_crawl; 203}; 204 205static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder) 206{ 207 return container_of(encoder, struct intel_sdvo, base); 208} 209 210static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) 211{ 212 return to_sdvo(intel_attached_encoder(connector)); 213} 214 215static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector) 216{ 217 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base); 218} 219 220static bool 221intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); 222static bool 223intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 224 struct intel_sdvo_connector *intel_sdvo_connector, 225 int type); 226static bool 227intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 228 struct intel_sdvo_connector *intel_sdvo_connector); 229 230/** 231 * Writes the SDVOB or SDVOC with the given value, but always writes both 232 * SDVOB and SDVOC to work around apparent hardware issues (according to 233 * comments in the BIOS). 234 */ 235static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) 236{ 237 struct drm_device *dev = intel_sdvo->base.base.dev; 238 struct drm_i915_private *dev_priv = dev->dev_private; 239 u32 bval = val, cval = val; 240 int i; 241 242 if (intel_sdvo->sdvo_reg == PCH_SDVOB) { 243 I915_WRITE(intel_sdvo->sdvo_reg, val); 244 I915_READ(intel_sdvo->sdvo_reg); 245 return; 246 } 247 248 if (intel_sdvo->sdvo_reg == GEN3_SDVOB) 249 cval = I915_READ(GEN3_SDVOC); 250 else 251 bval = I915_READ(GEN3_SDVOB); 252 253 /* 254 * Write the registers twice for luck. Sometimes, 255 * writing them only once doesn't appear to 'stick'. 256 * The BIOS does this too. Yay, magic 257 */ 258 for (i = 0; i < 2; i++) 259 { 260 I915_WRITE(GEN3_SDVOB, bval); 261 I915_READ(GEN3_SDVOB); 262 I915_WRITE(GEN3_SDVOC, cval); 263 I915_READ(GEN3_SDVOC); 264 } 265} 266 267static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) 268{ 269 struct i2c_msg msgs[] = { 270 { 271 .addr = intel_sdvo->slave_addr, 272 .flags = 0, 273 .len = 1, 274 .buf = &addr, 275 }, 276 { 277 .addr = intel_sdvo->slave_addr, 278 .flags = I2C_M_RD, 279 .len = 1, 280 .buf = ch, 281 } 282 }; 283 int ret; 284 285 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) 286 return true; 287 288 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); 289 return false; 290} 291 292#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} 293/** Mapping of command numbers to names, for debug output */ 294static const struct _sdvo_cmd_name { 295 u8 cmd; 296 const char *name; 297} sdvo_cmd_names[] = { 298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), 299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), 300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), 301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), 302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), 303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), 304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), 305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), 306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), 307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), 308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), 309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), 310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), 311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), 312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), 313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), 314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), 315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), 316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), 317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), 318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), 319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), 320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), 321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), 322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), 323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), 324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), 325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), 326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), 327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), 328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), 329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), 330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), 331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), 332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), 333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), 334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), 335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), 336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), 337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), 338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), 339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), 340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), 341 342 /* Add the op code for SDVO enhancements */ 343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), 344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), 345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), 346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), 347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), 348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), 349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), 350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), 351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), 352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), 353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), 354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), 355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), 356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), 357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), 358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), 359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), 360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), 361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), 362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), 363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), 364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), 365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), 366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), 367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), 368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), 369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), 370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), 371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), 372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), 373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), 374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), 375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), 376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), 377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), 378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), 379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), 380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), 381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), 382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), 383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), 384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), 385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), 386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), 387 388 /* HDMI op code */ 389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), 390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), 391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), 392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), 393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), 394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), 395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), 396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), 397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), 398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), 399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), 400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), 401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), 402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), 403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), 404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), 405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), 406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), 407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), 408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), 409}; 410 411#define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC") 412 413static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, 414 const void *args, int args_len) 415{ 416 int i, pos = 0; 417#define BUF_LEN 256 418 char buffer[BUF_LEN]; 419 420#define BUF_PRINT(args...) \ 421 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) 422 423 424 for (i = 0; i < args_len; i++) { 425 BUF_PRINT("%02X ", ((u8 *)args)[i]); 426 } 427 for (; i < 8; i++) { 428 BUF_PRINT(" "); 429 } 430 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { 431 if (cmd == sdvo_cmd_names[i].cmd) { 432 BUF_PRINT("(%s)", sdvo_cmd_names[i].name); 433 break; 434 } 435 } 436 if (i == ARRAY_SIZE(sdvo_cmd_names)) { 437 BUF_PRINT("(%02X)", cmd); 438 } 439 BUG_ON(pos >= BUF_LEN - 1); 440#undef BUF_PRINT 441#undef BUF_LEN 442 443 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer); 444} 445 446static const char *cmd_status_names[] = { 447 "Power on", 448 "Success", 449 "Not supported", 450 "Invalid arg", 451 "Pending", 452 "Target not specified", 453 "Scaling not supported" 454}; 455 456static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 457 const void *args, int args_len) 458{ 459 u8 *buf, status; 460 struct i2c_msg *msgs; 461 int i, ret = true; 462 463 /* Would be simpler to allocate both in one go ? */ 464 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); 465 if (!buf) 466 return false; 467 468 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); 469 if (!msgs) { 470 kfree(buf); 471 return false; 472 } 473 474 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); 475 476 for (i = 0; i < args_len; i++) { 477 msgs[i].addr = intel_sdvo->slave_addr; 478 msgs[i].flags = 0; 479 msgs[i].len = 2; 480 msgs[i].buf = buf + 2 *i; 481 buf[2*i + 0] = SDVO_I2C_ARG_0 - i; 482 buf[2*i + 1] = ((u8*)args)[i]; 483 } 484 msgs[i].addr = intel_sdvo->slave_addr; 485 msgs[i].flags = 0; 486 msgs[i].len = 2; 487 msgs[i].buf = buf + 2*i; 488 buf[2*i + 0] = SDVO_I2C_OPCODE; 489 buf[2*i + 1] = cmd; 490 491 /* the following two are to read the response */ 492 status = SDVO_I2C_CMD_STATUS; 493 msgs[i+1].addr = intel_sdvo->slave_addr; 494 msgs[i+1].flags = 0; 495 msgs[i+1].len = 1; 496 msgs[i+1].buf = &status; 497 498 msgs[i+2].addr = intel_sdvo->slave_addr; 499 msgs[i+2].flags = I2C_M_RD; 500 msgs[i+2].len = 1; 501 msgs[i+2].buf = &status; 502 503 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); 504 if (ret < 0) { 505 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); 506 ret = false; 507 goto out; 508 } 509 if (ret != i+3) { 510 /* failure in I2C transfer */ 511 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); 512 ret = false; 513 } 514 515out: 516 kfree(msgs); 517 kfree(buf); 518 return ret; 519} 520 521static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, 522 void *response, int response_len) 523{ 524 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ 525 u8 status; 526 int i, pos = 0; 527#define BUF_LEN 256 528 char buffer[BUF_LEN]; 529 530 531 /* 532 * The documentation states that all commands will be 533 * processed within 15µs, and that we need only poll 534 * the status byte a maximum of 3 times in order for the 535 * command to be complete. 536 * 537 * Check 5 times in case the hardware failed to read the docs. 538 * 539 * Also beware that the first response by many devices is to 540 * reply PENDING and stall for time. TVs are notorious for 541 * requiring longer than specified to complete their replies. 542 * Originally (in the DDX long ago), the delay was only ever 15ms 543 * with an additional delay of 30ms applied for TVs added later after 544 * many experiments. To accommodate both sets of delays, we do a 545 * sequence of slow checks if the device is falling behind and fails 546 * to reply within 5*15µs. 547 */ 548 if (!intel_sdvo_read_byte(intel_sdvo, 549 SDVO_I2C_CMD_STATUS, 550 &status)) 551 goto log_fail; 552 553 while ((status == SDVO_CMD_STATUS_PENDING || 554 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) { 555 if (retry < 10) 556 msleep(15); 557 else 558 udelay(15); 559 560 if (!intel_sdvo_read_byte(intel_sdvo, 561 SDVO_I2C_CMD_STATUS, 562 &status)) 563 goto log_fail; 564 } 565 566#define BUF_PRINT(args...) \ 567 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) 568 569 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) 570 BUF_PRINT("(%s)", cmd_status_names[status]); 571 else 572 BUF_PRINT("(??? %d)", status); 573 574 if (status != SDVO_CMD_STATUS_SUCCESS) 575 goto log_fail; 576 577 /* Read the command response */ 578 for (i = 0; i < response_len; i++) { 579 if (!intel_sdvo_read_byte(intel_sdvo, 580 SDVO_I2C_RETURN_0 + i, 581 &((u8 *)response)[i])) 582 goto log_fail; 583 BUF_PRINT(" %02X", ((u8 *)response)[i]); 584 } 585 BUG_ON(pos >= BUF_LEN - 1); 586#undef BUF_PRINT 587#undef BUF_LEN 588 589 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer); 590 return true; 591 592log_fail: 593 DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo)); 594 return false; 595} 596 597static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) 598{ 599 if (mode->clock >= 100000) 600 return 1; 601 else if (mode->clock >= 50000) 602 return 2; 603 else 604 return 4; 605} 606 607static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, 608 u8 ddc_bus) 609{ 610 /* This must be the immediately preceding write before the i2c xfer */ 611 return intel_sdvo_write_cmd(intel_sdvo, 612 SDVO_CMD_SET_CONTROL_BUS_SWITCH, 613 &ddc_bus, 1); 614} 615 616static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) 617{ 618 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) 619 return false; 620 621 return intel_sdvo_read_response(intel_sdvo, NULL, 0); 622} 623 624static bool 625intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) 626{ 627 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) 628 return false; 629 630 return intel_sdvo_read_response(intel_sdvo, value, len); 631} 632 633static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) 634{ 635 struct intel_sdvo_set_target_input_args targets = {0}; 636 return intel_sdvo_set_value(intel_sdvo, 637 SDVO_CMD_SET_TARGET_INPUT, 638 &targets, sizeof(targets)); 639} 640 641/** 642 * Return whether each input is trained. 643 * 644 * This function is making an assumption about the layout of the response, 645 * which should be checked against the docs. 646 */ 647static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) 648{ 649 struct intel_sdvo_get_trained_inputs_response response; 650 651 BUILD_BUG_ON(sizeof(response) != 1); 652 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, 653 &response, sizeof(response))) 654 return false; 655 656 *input_1 = response.input0_trained; 657 *input_2 = response.input1_trained; 658 return true; 659} 660 661static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, 662 u16 outputs) 663{ 664 return intel_sdvo_set_value(intel_sdvo, 665 SDVO_CMD_SET_ACTIVE_OUTPUTS, 666 &outputs, sizeof(outputs)); 667} 668 669static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, 670 u16 *outputs) 671{ 672 return intel_sdvo_get_value(intel_sdvo, 673 SDVO_CMD_GET_ACTIVE_OUTPUTS, 674 outputs, sizeof(*outputs)); 675} 676 677static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, 678 int mode) 679{ 680 u8 state = SDVO_ENCODER_STATE_ON; 681 682 switch (mode) { 683 case DRM_MODE_DPMS_ON: 684 state = SDVO_ENCODER_STATE_ON; 685 break; 686 case DRM_MODE_DPMS_STANDBY: 687 state = SDVO_ENCODER_STATE_STANDBY; 688 break; 689 case DRM_MODE_DPMS_SUSPEND: 690 state = SDVO_ENCODER_STATE_SUSPEND; 691 break; 692 case DRM_MODE_DPMS_OFF: 693 state = SDVO_ENCODER_STATE_OFF; 694 break; 695 } 696 697 return intel_sdvo_set_value(intel_sdvo, 698 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); 699} 700 701static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, 702 int *clock_min, 703 int *clock_max) 704{ 705 struct intel_sdvo_pixel_clock_range clocks; 706 707 BUILD_BUG_ON(sizeof(clocks) != 4); 708 if (!intel_sdvo_get_value(intel_sdvo, 709 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, 710 &clocks, sizeof(clocks))) 711 return false; 712 713 /* Convert the values from units of 10 kHz to kHz. */ 714 *clock_min = clocks.min * 10; 715 *clock_max = clocks.max * 10; 716 return true; 717} 718 719static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, 720 u16 outputs) 721{ 722 return intel_sdvo_set_value(intel_sdvo, 723 SDVO_CMD_SET_TARGET_OUTPUT, 724 &outputs, sizeof(outputs)); 725} 726 727static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 728 struct intel_sdvo_dtd *dtd) 729{ 730 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 731 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 732} 733 734static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 735 struct intel_sdvo_dtd *dtd) 736{ 737 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 738 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 739} 740 741static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, 742 struct intel_sdvo_dtd *dtd) 743{ 744 return intel_sdvo_set_timing(intel_sdvo, 745 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); 746} 747 748static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, 749 struct intel_sdvo_dtd *dtd) 750{ 751 return intel_sdvo_set_timing(intel_sdvo, 752 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); 753} 754 755static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo, 756 struct intel_sdvo_dtd *dtd) 757{ 758 return intel_sdvo_get_timing(intel_sdvo, 759 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); 760} 761 762static bool 763intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, 764 uint16_t clock, 765 uint16_t width, 766 uint16_t height) 767{ 768 struct intel_sdvo_preferred_input_timing_args args; 769 770 memset(&args, 0, sizeof(args)); 771 args.clock = clock; 772 args.width = width; 773 args.height = height; 774 args.interlace = 0; 775 776 if (intel_sdvo->is_lvds && 777 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || 778 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) 779 args.scaled = 1; 780 781 return intel_sdvo_set_value(intel_sdvo, 782 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, 783 &args, sizeof(args)); 784} 785 786static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, 787 struct intel_sdvo_dtd *dtd) 788{ 789 BUILD_BUG_ON(sizeof(dtd->part1) != 8); 790 BUILD_BUG_ON(sizeof(dtd->part2) != 8); 791 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 792 &dtd->part1, sizeof(dtd->part1)) && 793 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, 794 &dtd->part2, sizeof(dtd->part2)); 795} 796 797static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) 798{ 799 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); 800} 801 802static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, 803 const struct drm_display_mode *mode) 804{ 805 uint16_t width, height; 806 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; 807 uint16_t h_sync_offset, v_sync_offset; 808 int mode_clock; 809 810 memset(dtd, 0, sizeof(*dtd)); 811 812 width = mode->hdisplay; 813 height = mode->vdisplay; 814 815 /* do some mode translations */ 816 h_blank_len = mode->htotal - mode->hdisplay; 817 h_sync_len = mode->hsync_end - mode->hsync_start; 818 819 v_blank_len = mode->vtotal - mode->vdisplay; 820 v_sync_len = mode->vsync_end - mode->vsync_start; 821 822 h_sync_offset = mode->hsync_start - mode->hdisplay; 823 v_sync_offset = mode->vsync_start - mode->vdisplay; 824 825 mode_clock = mode->clock; 826 mode_clock /= 10; 827 dtd->part1.clock = mode_clock; 828 829 dtd->part1.h_active = width & 0xff; 830 dtd->part1.h_blank = h_blank_len & 0xff; 831 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | 832 ((h_blank_len >> 8) & 0xf); 833 dtd->part1.v_active = height & 0xff; 834 dtd->part1.v_blank = v_blank_len & 0xff; 835 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | 836 ((v_blank_len >> 8) & 0xf); 837 838 dtd->part2.h_sync_off = h_sync_offset & 0xff; 839 dtd->part2.h_sync_width = h_sync_len & 0xff; 840 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | 841 (v_sync_len & 0xf); 842 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | 843 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | 844 ((v_sync_len & 0x30) >> 4); 845 846 dtd->part2.dtd_flags = 0x18; 847 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 848 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; 849 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 850 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; 851 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 852 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; 853 854 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; 855} 856 857static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode, 858 const struct intel_sdvo_dtd *dtd) 859{ 860 struct drm_display_mode mode = {}; 861 862 mode.hdisplay = dtd->part1.h_active; 863 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; 864 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off; 865 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; 866 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width; 867 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; 868 mode.htotal = mode.hdisplay + dtd->part1.h_blank; 869 mode.htotal += (dtd->part1.h_high & 0xf) << 8; 870 871 mode.vdisplay = dtd->part1.v_active; 872 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; 873 mode.vsync_start = mode.vdisplay; 874 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; 875 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; 876 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0; 877 mode.vsync_end = mode.vsync_start + 878 (dtd->part2.v_sync_off_width & 0xf); 879 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; 880 mode.vtotal = mode.vdisplay + dtd->part1.v_blank; 881 mode.vtotal += (dtd->part1.v_high & 0xf) << 8; 882 883 mode.clock = dtd->part1.clock * 10; 884 885 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) 886 mode.flags |= DRM_MODE_FLAG_INTERLACE; 887 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 888 mode.flags |= DRM_MODE_FLAG_PHSYNC; 889 else 890 mode.flags |= DRM_MODE_FLAG_NHSYNC; 891 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 892 mode.flags |= DRM_MODE_FLAG_PVSYNC; 893 else 894 mode.flags |= DRM_MODE_FLAG_NVSYNC; 895 896 drm_mode_set_crtcinfo(&mode, 0); 897 898 drm_mode_copy(pmode, &mode); 899} 900 901static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) 902{ 903 struct intel_sdvo_encode encode; 904 905 BUILD_BUG_ON(sizeof(encode) != 2); 906 return intel_sdvo_get_value(intel_sdvo, 907 SDVO_CMD_GET_SUPP_ENCODE, 908 &encode, sizeof(encode)); 909} 910 911static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, 912 uint8_t mode) 913{ 914 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); 915} 916 917static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, 918 uint8_t mode) 919{ 920 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); 921} 922 923#if 0 924static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) 925{ 926 int i, j; 927 uint8_t set_buf_index[2]; 928 uint8_t av_split; 929 uint8_t buf_size; 930 uint8_t buf[48]; 931 uint8_t *pos; 932 933 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); 934 935 for (i = 0; i <= av_split; i++) { 936 set_buf_index[0] = i; set_buf_index[1] = 0; 937 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, 938 set_buf_index, 2); 939 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); 940 intel_sdvo_read_response(encoder, &buf_size, 1); 941 942 pos = buf; 943 for (j = 0; j <= buf_size; j += 8) { 944 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, 945 NULL, 0); 946 intel_sdvo_read_response(encoder, pos, 8); 947 pos += 8; 948 } 949 } 950} 951#endif 952 953static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, 954 unsigned if_index, uint8_t tx_rate, 955 const uint8_t *data, unsigned length) 956{ 957 uint8_t set_buf_index[2] = { if_index, 0 }; 958 uint8_t hbuf_size, tmp[8]; 959 int i; 960 961 if (!intel_sdvo_set_value(intel_sdvo, 962 SDVO_CMD_SET_HBUF_INDEX, 963 set_buf_index, 2)) 964 return false; 965 966 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO, 967 &hbuf_size, 1)) 968 return false; 969 970 /* Buffer size is 0 based, hooray! */ 971 hbuf_size++; 972 973 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n", 974 if_index, length, hbuf_size); 975 976 for (i = 0; i < hbuf_size; i += 8) { 977 memset(tmp, 0, 8); 978 if (i < length) 979 memcpy(tmp, data + i, min_t(unsigned, 8, length - i)); 980 981 if (!intel_sdvo_set_value(intel_sdvo, 982 SDVO_CMD_SET_HBUF_DATA, 983 tmp, 8)) 984 return false; 985 } 986 987 return intel_sdvo_set_value(intel_sdvo, 988 SDVO_CMD_SET_HBUF_TXRATE, 989 &tx_rate, 1); 990} 991 992static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, 993 const struct drm_display_mode *adjusted_mode) 994{ 995 uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 996 struct drm_crtc *crtc = intel_sdvo->base.base.crtc; 997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 998 union hdmi_infoframe frame; 999 int ret; 1000 ssize_t len; 1001 1002 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 1003 adjusted_mode); 1004 if (ret < 0) { 1005 DRM_ERROR("couldn't fill AVI infoframe\n"); 1006 return false; 1007 } 1008 1009 if (intel_sdvo->rgb_quant_range_selectable) { 1010 if (intel_crtc->config.limited_color_range) 1011 frame.avi.quantization_range = 1012 HDMI_QUANTIZATION_RANGE_LIMITED; 1013 else 1014 frame.avi.quantization_range = 1015 HDMI_QUANTIZATION_RANGE_FULL; 1016 } 1017 1018 len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data)); 1019 if (len < 0) 1020 return false; 1021 1022 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 1023 SDVO_HBUF_TX_VSYNC, 1024 sdvo_data, sizeof(sdvo_data)); 1025} 1026 1027static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) 1028{ 1029 struct intel_sdvo_tv_format format; 1030 uint32_t format_map; 1031 1032 format_map = 1 << intel_sdvo->tv_format_index; 1033 memset(&format, 0, sizeof(format)); 1034 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); 1035 1036 BUILD_BUG_ON(sizeof(format) != 6); 1037 return intel_sdvo_set_value(intel_sdvo, 1038 SDVO_CMD_SET_TV_FORMAT, 1039 &format, sizeof(format)); 1040} 1041 1042static bool 1043intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, 1044 const struct drm_display_mode *mode) 1045{ 1046 struct intel_sdvo_dtd output_dtd; 1047 1048 if (!intel_sdvo_set_target_output(intel_sdvo, 1049 intel_sdvo->attached_output)) 1050 return false; 1051 1052 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1053 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1054 return false; 1055 1056 return true; 1057} 1058 1059/* Asks the sdvo controller for the preferred input mode given the output mode. 1060 * Unfortunately we have to set up the full output mode to do that. */ 1061static bool 1062intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, 1063 const struct drm_display_mode *mode, 1064 struct drm_display_mode *adjusted_mode) 1065{ 1066 struct intel_sdvo_dtd input_dtd; 1067 1068 /* Reset the input timing to the screen. Assume always input 0. */ 1069 if (!intel_sdvo_set_target_input(intel_sdvo)) 1070 return false; 1071 1072 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, 1073 mode->clock / 10, 1074 mode->hdisplay, 1075 mode->vdisplay)) 1076 return false; 1077 1078 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, 1079 &input_dtd)) 1080 return false; 1081 1082 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1083 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; 1084 1085 return true; 1086} 1087 1088static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_config *pipe_config) 1089{ 1090 unsigned dotclock = pipe_config->port_clock; 1091 struct dpll *clock = &pipe_config->dpll; 1092 1093 /* SDVO TV has fixed PLL values depend on its clock range, 1094 this mirrors vbios setting. */ 1095 if (dotclock >= 100000 && dotclock < 140500) { 1096 clock->p1 = 2; 1097 clock->p2 = 10; 1098 clock->n = 3; 1099 clock->m1 = 16; 1100 clock->m2 = 8; 1101 } else if (dotclock >= 140500 && dotclock <= 200000) { 1102 clock->p1 = 1; 1103 clock->p2 = 10; 1104 clock->n = 6; 1105 clock->m1 = 12; 1106 clock->m2 = 8; 1107 } else { 1108 WARN(1, "SDVO TV clock out of range: %i\n", dotclock); 1109 } 1110 1111 pipe_config->clock_set = true; 1112} 1113 1114static bool intel_sdvo_compute_config(struct intel_encoder *encoder, 1115 struct intel_crtc_config *pipe_config) 1116{ 1117 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1118 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 1119 struct drm_display_mode *mode = &pipe_config->requested_mode; 1120 1121 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n"); 1122 pipe_config->pipe_bpp = 8*3; 1123 1124 if (HAS_PCH_SPLIT(encoder->base.dev)) 1125 pipe_config->has_pch_encoder = true; 1126 1127 /* We need to construct preferred input timings based on our 1128 * output timings. To do that, we have to set the output 1129 * timings, even though this isn't really the right place in 1130 * the sequence to do it. Oh well. 1131 */ 1132 if (intel_sdvo->is_tv) { 1133 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) 1134 return false; 1135 1136 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1137 mode, 1138 adjusted_mode); 1139 pipe_config->sdvo_tv_clock = true; 1140 } else if (intel_sdvo->is_lvds) { 1141 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, 1142 intel_sdvo->sdvo_lvds_fixed_mode)) 1143 return false; 1144 1145 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1146 mode, 1147 adjusted_mode); 1148 } 1149 1150 /* Make the CRTC code factor in the SDVO pixel multiplier. The 1151 * SDVO device will factor out the multiplier during mode_set. 1152 */ 1153 pipe_config->pixel_multiplier = 1154 intel_sdvo_get_pixel_multiplier(adjusted_mode); 1155 1156 pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor; 1157 1158 if (intel_sdvo->color_range_auto) { 1159 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 1160 /* FIXME: This bit is only valid when using TMDS encoding and 8 1161 * bit per color mode. */ 1162 if (pipe_config->has_hdmi_sink && 1163 drm_match_cea_mode(adjusted_mode) > 1) 1164 pipe_config->limited_color_range = true; 1165 } else { 1166 if (pipe_config->has_hdmi_sink && 1167 intel_sdvo->color_range == HDMI_COLOR_RANGE_16_235) 1168 pipe_config->limited_color_range = true; 1169 } 1170 1171 /* Clock computation needs to happen after pixel multiplier. */ 1172 if (intel_sdvo->is_tv) 1173 i9xx_adjust_sdvo_tv_clock(pipe_config); 1174 1175 return true; 1176} 1177 1178static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) 1179{ 1180 struct drm_device *dev = intel_encoder->base.dev; 1181 struct drm_i915_private *dev_priv = dev->dev_private; 1182 struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc); 1183 struct drm_display_mode *adjusted_mode = 1184 &crtc->config.adjusted_mode; 1185 struct drm_display_mode *mode = &crtc->config.requested_mode; 1186 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); 1187 u32 sdvox; 1188 struct intel_sdvo_in_out_map in_out; 1189 struct intel_sdvo_dtd input_dtd, output_dtd; 1190 int rate; 1191 1192 if (!mode) 1193 return; 1194 1195 /* First, set the input mapping for the first input to our controlled 1196 * output. This is only correct if we're a single-input device, in 1197 * which case the first input is the output from the appropriate SDVO 1198 * channel on the motherboard. In a two-input device, the first input 1199 * will be SDVOB and the second SDVOC. 1200 */ 1201 in_out.in0 = intel_sdvo->attached_output; 1202 in_out.in1 = 0; 1203 1204 intel_sdvo_set_value(intel_sdvo, 1205 SDVO_CMD_SET_IN_OUT_MAP, 1206 &in_out, sizeof(in_out)); 1207 1208 /* Set the output timings to the screen */ 1209 if (!intel_sdvo_set_target_output(intel_sdvo, 1210 intel_sdvo->attached_output)) 1211 return; 1212 1213 /* lvds has a special fixed output timing. */ 1214 if (intel_sdvo->is_lvds) 1215 intel_sdvo_get_dtd_from_mode(&output_dtd, 1216 intel_sdvo->sdvo_lvds_fixed_mode); 1217 else 1218 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1219 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1220 DRM_INFO("Setting output timings on %s failed\n", 1221 SDVO_NAME(intel_sdvo)); 1222 1223 /* Set the input timing to the screen. Assume always input 0. */ 1224 if (!intel_sdvo_set_target_input(intel_sdvo)) 1225 return; 1226 1227 if (crtc->config.has_hdmi_sink) { 1228 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); 1229 intel_sdvo_set_colorimetry(intel_sdvo, 1230 SDVO_COLORIMETRY_RGB256); 1231 intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode); 1232 } else 1233 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); 1234 1235 if (intel_sdvo->is_tv && 1236 !intel_sdvo_set_tv_format(intel_sdvo)) 1237 return; 1238 1239 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); 1240 1241 if (intel_sdvo->is_tv || intel_sdvo->is_lvds) 1242 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; 1243 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) 1244 DRM_INFO("Setting input timings on %s failed\n", 1245 SDVO_NAME(intel_sdvo)); 1246 1247 switch (crtc->config.pixel_multiplier) { 1248 default: 1249 WARN(1, "unknown pixel mutlipler specified\n"); 1250 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; 1251 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; 1252 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; 1253 } 1254 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) 1255 return; 1256 1257 /* Set the SDVO control regs. */ 1258 if (INTEL_INFO(dev)->gen >= 4) { 1259 /* The real mode polarity is set by the SDVO commands, using 1260 * struct intel_sdvo_dtd. */ 1261 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; 1262 if (!HAS_PCH_SPLIT(dev) && crtc->config.limited_color_range) 1263 sdvox |= HDMI_COLOR_RANGE_16_235; 1264 if (INTEL_INFO(dev)->gen < 5) 1265 sdvox |= SDVO_BORDER_ENABLE; 1266 } else { 1267 sdvox = I915_READ(intel_sdvo->sdvo_reg); 1268 switch (intel_sdvo->sdvo_reg) { 1269 case GEN3_SDVOB: 1270 sdvox &= SDVOB_PRESERVE_MASK; 1271 break; 1272 case GEN3_SDVOC: 1273 sdvox &= SDVOC_PRESERVE_MASK; 1274 break; 1275 } 1276 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; 1277 } 1278 1279 if (INTEL_PCH_TYPE(dev) >= PCH_CPT) 1280 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe); 1281 else 1282 sdvox |= SDVO_PIPE_SEL(crtc->pipe); 1283 1284 if (intel_sdvo->has_hdmi_audio) 1285 sdvox |= SDVO_AUDIO_ENABLE; 1286 1287 if (INTEL_INFO(dev)->gen >= 4) { 1288 /* done in crtc_mode_set as the dpll_md reg must be written early */ 1289 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { 1290 /* done in crtc_mode_set as it lives inside the dpll register */ 1291 } else { 1292 sdvox |= (crtc->config.pixel_multiplier - 1) 1293 << SDVO_PORT_MULTIPLY_SHIFT; 1294 } 1295 1296 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && 1297 INTEL_INFO(dev)->gen < 5) 1298 sdvox |= SDVO_STALL_SELECT; 1299 intel_sdvo_write_sdvox(intel_sdvo, sdvox); 1300} 1301 1302static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) 1303{ 1304 struct intel_sdvo_connector *intel_sdvo_connector = 1305 to_intel_sdvo_connector(&connector->base); 1306 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base); 1307 u16 active_outputs = 0; 1308 1309 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1310 1311 if (active_outputs & intel_sdvo_connector->output_flag) 1312 return true; 1313 else 1314 return false; 1315} 1316 1317static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, 1318 enum pipe *pipe) 1319{ 1320 struct drm_device *dev = encoder->base.dev; 1321 struct drm_i915_private *dev_priv = dev->dev_private; 1322 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1323 u16 active_outputs = 0; 1324 u32 tmp; 1325 1326 tmp = I915_READ(intel_sdvo->sdvo_reg); 1327 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1328 1329 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0)) 1330 return false; 1331 1332 if (HAS_PCH_CPT(dev)) 1333 *pipe = PORT_TO_PIPE_CPT(tmp); 1334 else 1335 *pipe = PORT_TO_PIPE(tmp); 1336 1337 return true; 1338} 1339 1340static void intel_sdvo_get_config(struct intel_encoder *encoder, 1341 struct intel_crtc_config *pipe_config) 1342{ 1343 struct drm_device *dev = encoder->base.dev; 1344 struct drm_i915_private *dev_priv = dev->dev_private; 1345 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1346 struct intel_sdvo_dtd dtd; 1347 int encoder_pixel_multiplier = 0; 1348 int dotclock; 1349 u32 flags = 0, sdvox; 1350 u8 val; 1351 bool ret; 1352 1353 sdvox = I915_READ(intel_sdvo->sdvo_reg); 1354 1355 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); 1356 if (!ret) { 1357 /* Some sdvo encoders are not spec compliant and don't 1358 * implement the mandatory get_timings function. */ 1359 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n"); 1360 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS; 1361 } else { 1362 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 1363 flags |= DRM_MODE_FLAG_PHSYNC; 1364 else 1365 flags |= DRM_MODE_FLAG_NHSYNC; 1366 1367 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 1368 flags |= DRM_MODE_FLAG_PVSYNC; 1369 else 1370 flags |= DRM_MODE_FLAG_NVSYNC; 1371 } 1372 1373 pipe_config->adjusted_mode.flags |= flags; 1374 1375 /* 1376 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in 1377 * the sdvo port register, on all other platforms it is part of the dpll 1378 * state. Since the general pipe state readout happens before the 1379 * encoder->get_config we so already have a valid pixel multplier on all 1380 * other platfroms. 1381 */ 1382 if (IS_I915G(dev) || IS_I915GM(dev)) { 1383 pipe_config->pixel_multiplier = 1384 ((sdvox & SDVO_PORT_MULTIPLY_MASK) 1385 >> SDVO_PORT_MULTIPLY_SHIFT) + 1; 1386 } 1387 1388 dotclock = pipe_config->port_clock; 1389 if (pipe_config->pixel_multiplier) 1390 dotclock /= pipe_config->pixel_multiplier; 1391 1392 if (HAS_PCH_SPLIT(dev)) 1393 ironlake_check_encoder_dotclock(pipe_config, dotclock); 1394 1395 pipe_config->adjusted_mode.crtc_clock = dotclock; 1396 1397 /* Cross check the port pixel multiplier with the sdvo encoder state. */ 1398 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, 1399 &val, 1)) { 1400 switch (val) { 1401 case SDVO_CLOCK_RATE_MULT_1X: 1402 encoder_pixel_multiplier = 1; 1403 break; 1404 case SDVO_CLOCK_RATE_MULT_2X: 1405 encoder_pixel_multiplier = 2; 1406 break; 1407 case SDVO_CLOCK_RATE_MULT_4X: 1408 encoder_pixel_multiplier = 4; 1409 break; 1410 } 1411 } 1412 1413 if (sdvox & HDMI_COLOR_RANGE_16_235) 1414 pipe_config->limited_color_range = true; 1415 1416 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, 1417 &val, 1)) { 1418 if (val == SDVO_ENCODE_HDMI) 1419 pipe_config->has_hdmi_sink = true; 1420 } 1421 1422 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier, 1423 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n", 1424 pipe_config->pixel_multiplier, encoder_pixel_multiplier); 1425} 1426 1427static void intel_disable_sdvo(struct intel_encoder *encoder) 1428{ 1429 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1430 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1431 u32 temp; 1432 1433 intel_sdvo_set_active_outputs(intel_sdvo, 0); 1434 if (0) 1435 intel_sdvo_set_encoder_power_state(intel_sdvo, 1436 DRM_MODE_DPMS_OFF); 1437 1438 temp = I915_READ(intel_sdvo->sdvo_reg); 1439 if ((temp & SDVO_ENABLE) != 0) { 1440 /* HW workaround for IBX, we need to move the port to 1441 * transcoder A before disabling it. */ 1442 if (HAS_PCH_IBX(encoder->base.dev)) { 1443 struct drm_crtc *crtc = encoder->base.crtc; 1444 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; 1445 1446 if (temp & SDVO_PIPE_B_SELECT) { 1447 temp &= ~SDVO_PIPE_B_SELECT; 1448 I915_WRITE(intel_sdvo->sdvo_reg, temp); 1449 POSTING_READ(intel_sdvo->sdvo_reg); 1450 1451 /* Again we need to write this twice. */ 1452 I915_WRITE(intel_sdvo->sdvo_reg, temp); 1453 POSTING_READ(intel_sdvo->sdvo_reg); 1454 1455 /* Transcoder selection bits only update 1456 * effectively on vblank. */ 1457 if (crtc) 1458 intel_wait_for_vblank(encoder->base.dev, pipe); 1459 else 1460 msleep(50); 1461 } 1462 } 1463 1464 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE); 1465 } 1466} 1467 1468static void intel_enable_sdvo(struct intel_encoder *encoder) 1469{ 1470 struct drm_device *dev = encoder->base.dev; 1471 struct drm_i915_private *dev_priv = dev->dev_private; 1472 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1473 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1474 u32 temp; 1475 bool input1, input2; 1476 int i; 1477 bool success; 1478 1479 temp = I915_READ(intel_sdvo->sdvo_reg); 1480 if ((temp & SDVO_ENABLE) == 0) { 1481 /* HW workaround for IBX, we need to move the port 1482 * to transcoder A before disabling it, so restore it here. */ 1483 if (HAS_PCH_IBX(dev)) 1484 temp |= SDVO_PIPE_SEL(intel_crtc->pipe); 1485 1486 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE); 1487 } 1488 for (i = 0; i < 2; i++) 1489 intel_wait_for_vblank(dev, intel_crtc->pipe); 1490 1491 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); 1492 /* Warn if the device reported failure to sync. 1493 * A lot of SDVO devices fail to notify of sync, but it's 1494 * a given it the status is a success, we succeeded. 1495 */ 1496 if (success && !input1) { 1497 DRM_DEBUG_KMS("First %s output reported failure to " 1498 "sync\n", SDVO_NAME(intel_sdvo)); 1499 } 1500 1501 if (0) 1502 intel_sdvo_set_encoder_power_state(intel_sdvo, 1503 DRM_MODE_DPMS_ON); 1504 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); 1505} 1506 1507/* Special dpms function to support cloning between dvo/sdvo/crt. */ 1508static void intel_sdvo_dpms(struct drm_connector *connector, int mode) 1509{ 1510 struct drm_crtc *crtc; 1511 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1512 1513 /* dvo supports only 2 dpms states. */ 1514 if (mode != DRM_MODE_DPMS_ON) 1515 mode = DRM_MODE_DPMS_OFF; 1516 1517 if (mode == connector->dpms) 1518 return; 1519 1520 connector->dpms = mode; 1521 1522 /* Only need to change hw state when actually enabled */ 1523 crtc = intel_sdvo->base.base.crtc; 1524 if (!crtc) { 1525 intel_sdvo->base.connectors_active = false; 1526 return; 1527 } 1528 1529 /* We set active outputs manually below in case pipe dpms doesn't change 1530 * due to cloning. */ 1531 if (mode != DRM_MODE_DPMS_ON) { 1532 intel_sdvo_set_active_outputs(intel_sdvo, 0); 1533 if (0) 1534 intel_sdvo_set_encoder_power_state(intel_sdvo, mode); 1535 1536 intel_sdvo->base.connectors_active = false; 1537 1538 intel_crtc_update_dpms(crtc); 1539 } else { 1540 intel_sdvo->base.connectors_active = true; 1541 1542 intel_crtc_update_dpms(crtc); 1543 1544 if (0) 1545 intel_sdvo_set_encoder_power_state(intel_sdvo, mode); 1546 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); 1547 } 1548 1549 intel_modeset_check_state(connector->dev); 1550} 1551 1552static enum drm_mode_status 1553intel_sdvo_mode_valid(struct drm_connector *connector, 1554 struct drm_display_mode *mode) 1555{ 1556 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1557 1558 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1559 return MODE_NO_DBLESCAN; 1560 1561 if (intel_sdvo->pixel_clock_min > mode->clock) 1562 return MODE_CLOCK_LOW; 1563 1564 if (intel_sdvo->pixel_clock_max < mode->clock) 1565 return MODE_CLOCK_HIGH; 1566 1567 if (intel_sdvo->is_lvds) { 1568 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) 1569 return MODE_PANEL; 1570 1571 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) 1572 return MODE_PANEL; 1573 } 1574 1575 return MODE_OK; 1576} 1577 1578static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) 1579{ 1580 BUILD_BUG_ON(sizeof(*caps) != 8); 1581 if (!intel_sdvo_get_value(intel_sdvo, 1582 SDVO_CMD_GET_DEVICE_CAPS, 1583 caps, sizeof(*caps))) 1584 return false; 1585 1586 DRM_DEBUG_KMS("SDVO capabilities:\n" 1587 " vendor_id: %d\n" 1588 " device_id: %d\n" 1589 " device_rev_id: %d\n" 1590 " sdvo_version_major: %d\n" 1591 " sdvo_version_minor: %d\n" 1592 " sdvo_inputs_mask: %d\n" 1593 " smooth_scaling: %d\n" 1594 " sharp_scaling: %d\n" 1595 " up_scaling: %d\n" 1596 " down_scaling: %d\n" 1597 " stall_support: %d\n" 1598 " output_flags: %d\n", 1599 caps->vendor_id, 1600 caps->device_id, 1601 caps->device_rev_id, 1602 caps->sdvo_version_major, 1603 caps->sdvo_version_minor, 1604 caps->sdvo_inputs_mask, 1605 caps->smooth_scaling, 1606 caps->sharp_scaling, 1607 caps->up_scaling, 1608 caps->down_scaling, 1609 caps->stall_support, 1610 caps->output_flags); 1611 1612 return true; 1613} 1614 1615static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) 1616{ 1617 struct drm_device *dev = intel_sdvo->base.base.dev; 1618 uint16_t hotplug; 1619 1620 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise 1621 * on the line. */ 1622 if (IS_I945G(dev) || IS_I945GM(dev)) 1623 return 0; 1624 1625 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, 1626 &hotplug, sizeof(hotplug))) 1627 return 0; 1628 1629 return hotplug; 1630} 1631 1632static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) 1633{ 1634 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1635 1636 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, 1637 &intel_sdvo->hotplug_active, 2); 1638} 1639 1640static bool 1641intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) 1642{ 1643 /* Is there more than one type of output? */ 1644 return hweight16(intel_sdvo->caps.output_flags) > 1; 1645} 1646 1647static struct edid * 1648intel_sdvo_get_edid(struct drm_connector *connector) 1649{ 1650 struct intel_sdvo *sdvo = intel_attached_sdvo(connector); 1651 return drm_get_edid(connector, &sdvo->ddc); 1652} 1653 1654/* Mac mini hack -- use the same DDC as the analog connector */ 1655static struct edid * 1656intel_sdvo_get_analog_edid(struct drm_connector *connector) 1657{ 1658 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1659 1660 return drm_get_edid(connector, 1661 intel_gmbus_get_adapter(dev_priv, 1662 dev_priv->vbt.crt_ddc_pin)); 1663} 1664 1665static enum drm_connector_status 1666intel_sdvo_tmds_sink_detect(struct drm_connector *connector) 1667{ 1668 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1669 enum drm_connector_status status; 1670 struct edid *edid; 1671 1672 edid = intel_sdvo_get_edid(connector); 1673 1674 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { 1675 u8 ddc, saved_ddc = intel_sdvo->ddc_bus; 1676 1677 /* 1678 * Don't use the 1 as the argument of DDC bus switch to get 1679 * the EDID. It is used for SDVO SPD ROM. 1680 */ 1681 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { 1682 intel_sdvo->ddc_bus = ddc; 1683 edid = intel_sdvo_get_edid(connector); 1684 if (edid) 1685 break; 1686 } 1687 /* 1688 * If we found the EDID on the other bus, 1689 * assume that is the correct DDC bus. 1690 */ 1691 if (edid == NULL) 1692 intel_sdvo->ddc_bus = saved_ddc; 1693 } 1694 1695 /* 1696 * When there is no edid and no monitor is connected with VGA 1697 * port, try to use the CRT ddc to read the EDID for DVI-connector. 1698 */ 1699 if (edid == NULL) 1700 edid = intel_sdvo_get_analog_edid(connector); 1701 1702 status = connector_status_unknown; 1703 if (edid != NULL) { 1704 /* DDC bus is shared, match EDID to connector type */ 1705 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 1706 status = connector_status_connected; 1707 if (intel_sdvo->is_hdmi) { 1708 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); 1709 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); 1710 intel_sdvo->rgb_quant_range_selectable = 1711 drm_rgb_quant_range_selectable(edid); 1712 } 1713 } else 1714 status = connector_status_disconnected; 1715 kfree(edid); 1716 } 1717 1718 if (status == connector_status_connected) { 1719 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1720 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO) 1721 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON); 1722 } 1723 1724 return status; 1725} 1726 1727static bool 1728intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, 1729 struct edid *edid) 1730{ 1731 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); 1732 bool connector_is_digital = !!IS_DIGITAL(sdvo); 1733 1734 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n", 1735 connector_is_digital, monitor_is_digital); 1736 return connector_is_digital == monitor_is_digital; 1737} 1738 1739static enum drm_connector_status 1740intel_sdvo_detect(struct drm_connector *connector, bool force) 1741{ 1742 uint16_t response; 1743 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1744 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1745 enum drm_connector_status ret; 1746 1747 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1748 connector->base.id, connector->name); 1749 1750 if (!intel_sdvo_get_value(intel_sdvo, 1751 SDVO_CMD_GET_ATTACHED_DISPLAYS, 1752 &response, 2)) 1753 return connector_status_unknown; 1754 1755 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", 1756 response & 0xff, response >> 8, 1757 intel_sdvo_connector->output_flag); 1758 1759 if (response == 0) 1760 return connector_status_disconnected; 1761 1762 intel_sdvo->attached_output = response; 1763 1764 intel_sdvo->has_hdmi_monitor = false; 1765 intel_sdvo->has_hdmi_audio = false; 1766 intel_sdvo->rgb_quant_range_selectable = false; 1767 1768 if ((intel_sdvo_connector->output_flag & response) == 0) 1769 ret = connector_status_disconnected; 1770 else if (IS_TMDS(intel_sdvo_connector)) 1771 ret = intel_sdvo_tmds_sink_detect(connector); 1772 else { 1773 struct edid *edid; 1774 1775 /* if we have an edid check it matches the connection */ 1776 edid = intel_sdvo_get_edid(connector); 1777 if (edid == NULL) 1778 edid = intel_sdvo_get_analog_edid(connector); 1779 if (edid != NULL) { 1780 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, 1781 edid)) 1782 ret = connector_status_connected; 1783 else 1784 ret = connector_status_disconnected; 1785 1786 kfree(edid); 1787 } else 1788 ret = connector_status_connected; 1789 } 1790 1791 /* May update encoder flag for like clock for SDVO TV, etc.*/ 1792 if (ret == connector_status_connected) { 1793 intel_sdvo->is_tv = false; 1794 intel_sdvo->is_lvds = false; 1795 1796 if (response & SDVO_TV_MASK) 1797 intel_sdvo->is_tv = true; 1798 if (response & SDVO_LVDS_MASK) 1799 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL; 1800 } 1801 1802 return ret; 1803} 1804 1805static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) 1806{ 1807 struct edid *edid; 1808 1809 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1810 connector->base.id, connector->name); 1811 1812 /* set the bus switch and get the modes */ 1813 edid = intel_sdvo_get_edid(connector); 1814 1815 /* 1816 * Mac mini hack. On this device, the DVI-I connector shares one DDC 1817 * link between analog and digital outputs. So, if the regular SDVO 1818 * DDC fails, check to see if the analog output is disconnected, in 1819 * which case we'll look there for the digital DDC data. 1820 */ 1821 if (edid == NULL) 1822 edid = intel_sdvo_get_analog_edid(connector); 1823 1824 if (edid != NULL) { 1825 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), 1826 edid)) { 1827 drm_mode_connector_update_edid_property(connector, edid); 1828 drm_add_edid_modes(connector, edid); 1829 } 1830 1831 kfree(edid); 1832 } 1833} 1834 1835/* 1836 * Set of SDVO TV modes. 1837 * Note! This is in reply order (see loop in get_tv_modes). 1838 * XXX: all 60Hz refresh? 1839 */ 1840static const struct drm_display_mode sdvo_tv_modes[] = { 1841 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, 1842 416, 0, 200, 201, 232, 233, 0, 1843 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1844 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, 1845 416, 0, 240, 241, 272, 273, 0, 1846 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1847 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, 1848 496, 0, 300, 301, 332, 333, 0, 1849 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1850 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, 1851 736, 0, 350, 351, 382, 383, 0, 1852 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1853 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, 1854 736, 0, 400, 401, 432, 433, 0, 1855 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1856 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, 1857 736, 0, 480, 481, 512, 513, 0, 1858 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1859 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, 1860 800, 0, 480, 481, 512, 513, 0, 1861 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1862 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, 1863 800, 0, 576, 577, 608, 609, 0, 1864 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1865 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, 1866 816, 0, 350, 351, 382, 383, 0, 1867 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1868 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, 1869 816, 0, 400, 401, 432, 433, 0, 1870 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1871 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, 1872 816, 0, 480, 481, 512, 513, 0, 1873 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1874 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, 1875 816, 0, 540, 541, 572, 573, 0, 1876 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1877 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, 1878 816, 0, 576, 577, 608, 609, 0, 1879 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1880 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, 1881 864, 0, 576, 577, 608, 609, 0, 1882 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1883 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, 1884 896, 0, 600, 601, 632, 633, 0, 1885 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1886 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, 1887 928, 0, 624, 625, 656, 657, 0, 1888 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1889 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, 1890 1016, 0, 766, 767, 798, 799, 0, 1891 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1892 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, 1893 1120, 0, 768, 769, 800, 801, 0, 1894 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1895 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, 1896 1376, 0, 1024, 1025, 1056, 1057, 0, 1897 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1898}; 1899 1900static void intel_sdvo_get_tv_modes(struct drm_connector *connector) 1901{ 1902 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1903 struct intel_sdvo_sdtv_resolution_request tv_res; 1904 uint32_t reply = 0, format_map = 0; 1905 int i; 1906 1907 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1908 connector->base.id, connector->name); 1909 1910 /* Read the list of supported input resolutions for the selected TV 1911 * format. 1912 */ 1913 format_map = 1 << intel_sdvo->tv_format_index; 1914 memcpy(&tv_res, &format_map, 1915 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); 1916 1917 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) 1918 return; 1919 1920 BUILD_BUG_ON(sizeof(tv_res) != 3); 1921 if (!intel_sdvo_write_cmd(intel_sdvo, 1922 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, 1923 &tv_res, sizeof(tv_res))) 1924 return; 1925 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) 1926 return; 1927 1928 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) 1929 if (reply & (1 << i)) { 1930 struct drm_display_mode *nmode; 1931 nmode = drm_mode_duplicate(connector->dev, 1932 &sdvo_tv_modes[i]); 1933 if (nmode) 1934 drm_mode_probed_add(connector, nmode); 1935 } 1936} 1937 1938static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) 1939{ 1940 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1941 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1942 struct drm_display_mode *newmode; 1943 1944 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1945 connector->base.id, connector->name); 1946 1947 /* 1948 * Fetch modes from VBT. For SDVO prefer the VBT mode since some 1949 * SDVO->LVDS transcoders can't cope with the EDID mode. 1950 */ 1951 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) { 1952 newmode = drm_mode_duplicate(connector->dev, 1953 dev_priv->vbt.sdvo_lvds_vbt_mode); 1954 if (newmode != NULL) { 1955 /* Guarantee the mode is preferred */ 1956 newmode->type = (DRM_MODE_TYPE_PREFERRED | 1957 DRM_MODE_TYPE_DRIVER); 1958 drm_mode_probed_add(connector, newmode); 1959 } 1960 } 1961 1962 /* 1963 * Attempt to get the mode list from DDC. 1964 * Assume that the preferred modes are 1965 * arranged in priority order. 1966 */ 1967 intel_ddc_get_modes(connector, &intel_sdvo->ddc); 1968 1969 list_for_each_entry(newmode, &connector->probed_modes, head) { 1970 if (newmode->type & DRM_MODE_TYPE_PREFERRED) { 1971 intel_sdvo->sdvo_lvds_fixed_mode = 1972 drm_mode_duplicate(connector->dev, newmode); 1973 1974 intel_sdvo->is_lvds = true; 1975 break; 1976 } 1977 } 1978} 1979 1980static int intel_sdvo_get_modes(struct drm_connector *connector) 1981{ 1982 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1983 1984 if (IS_TV(intel_sdvo_connector)) 1985 intel_sdvo_get_tv_modes(connector); 1986 else if (IS_LVDS(intel_sdvo_connector)) 1987 intel_sdvo_get_lvds_modes(connector); 1988 else 1989 intel_sdvo_get_ddc_modes(connector); 1990 1991 return !list_empty(&connector->probed_modes); 1992} 1993 1994static void 1995intel_sdvo_destroy_enhance_property(struct drm_connector *connector) 1996{ 1997 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1998 struct drm_device *dev = connector->dev; 1999 2000 if (intel_sdvo_connector->left) 2001 drm_property_destroy(dev, intel_sdvo_connector->left); 2002 if (intel_sdvo_connector->right) 2003 drm_property_destroy(dev, intel_sdvo_connector->right); 2004 if (intel_sdvo_connector->top) 2005 drm_property_destroy(dev, intel_sdvo_connector->top); 2006 if (intel_sdvo_connector->bottom) 2007 drm_property_destroy(dev, intel_sdvo_connector->bottom); 2008 if (intel_sdvo_connector->hpos) 2009 drm_property_destroy(dev, intel_sdvo_connector->hpos); 2010 if (intel_sdvo_connector->vpos) 2011 drm_property_destroy(dev, intel_sdvo_connector->vpos); 2012 if (intel_sdvo_connector->saturation) 2013 drm_property_destroy(dev, intel_sdvo_connector->saturation); 2014 if (intel_sdvo_connector->contrast) 2015 drm_property_destroy(dev, intel_sdvo_connector->contrast); 2016 if (intel_sdvo_connector->hue) 2017 drm_property_destroy(dev, intel_sdvo_connector->hue); 2018 if (intel_sdvo_connector->sharpness) 2019 drm_property_destroy(dev, intel_sdvo_connector->sharpness); 2020 if (intel_sdvo_connector->flicker_filter) 2021 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter); 2022 if (intel_sdvo_connector->flicker_filter_2d) 2023 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d); 2024 if (intel_sdvo_connector->flicker_filter_adaptive) 2025 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive); 2026 if (intel_sdvo_connector->tv_luma_filter) 2027 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter); 2028 if (intel_sdvo_connector->tv_chroma_filter) 2029 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter); 2030 if (intel_sdvo_connector->dot_crawl) 2031 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl); 2032 if (intel_sdvo_connector->brightness) 2033 drm_property_destroy(dev, intel_sdvo_connector->brightness); 2034} 2035 2036static void intel_sdvo_destroy(struct drm_connector *connector) 2037{ 2038 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2039 2040 if (intel_sdvo_connector->tv_format) 2041 drm_property_destroy(connector->dev, 2042 intel_sdvo_connector->tv_format); 2043 2044 intel_sdvo_destroy_enhance_property(connector); 2045 drm_connector_cleanup(connector); 2046 kfree(intel_sdvo_connector); 2047} 2048 2049static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector) 2050{ 2051 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 2052 struct edid *edid; 2053 bool has_audio = false; 2054 2055 if (!intel_sdvo->is_hdmi) 2056 return false; 2057 2058 edid = intel_sdvo_get_edid(connector); 2059 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL) 2060 has_audio = drm_detect_monitor_audio(edid); 2061 kfree(edid); 2062 2063 return has_audio; 2064} 2065 2066static int 2067intel_sdvo_set_property(struct drm_connector *connector, 2068 struct drm_property *property, 2069 uint64_t val) 2070{ 2071 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 2072 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2073 struct drm_i915_private *dev_priv = connector->dev->dev_private; 2074 uint16_t temp_value; 2075 uint8_t cmd; 2076 int ret; 2077 2078 ret = drm_object_property_set_value(&connector->base, property, val); 2079 if (ret) 2080 return ret; 2081 2082 if (property == dev_priv->force_audio_property) { 2083 int i = val; 2084 bool has_audio; 2085 2086 if (i == intel_sdvo_connector->force_audio) 2087 return 0; 2088 2089 intel_sdvo_connector->force_audio = i; 2090 2091 if (i == HDMI_AUDIO_AUTO) 2092 has_audio = intel_sdvo_detect_hdmi_audio(connector); 2093 else 2094 has_audio = (i == HDMI_AUDIO_ON); 2095 2096 if (has_audio == intel_sdvo->has_hdmi_audio) 2097 return 0; 2098 2099 intel_sdvo->has_hdmi_audio = has_audio; 2100 goto done; 2101 } 2102 2103 if (property == dev_priv->broadcast_rgb_property) { 2104 bool old_auto = intel_sdvo->color_range_auto; 2105 uint32_t old_range = intel_sdvo->color_range; 2106 2107 switch (val) { 2108 case INTEL_BROADCAST_RGB_AUTO: 2109 intel_sdvo->color_range_auto = true; 2110 break; 2111 case INTEL_BROADCAST_RGB_FULL: 2112 intel_sdvo->color_range_auto = false; 2113 intel_sdvo->color_range = 0; 2114 break; 2115 case INTEL_BROADCAST_RGB_LIMITED: 2116 intel_sdvo->color_range_auto = false; 2117 /* FIXME: this bit is only valid when using TMDS 2118 * encoding and 8 bit per color mode. */ 2119 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235; 2120 break; 2121 default: 2122 return -EINVAL; 2123 } 2124 2125 if (old_auto == intel_sdvo->color_range_auto && 2126 old_range == intel_sdvo->color_range) 2127 return 0; 2128 2129 goto done; 2130 } 2131 2132#define CHECK_PROPERTY(name, NAME) \ 2133 if (intel_sdvo_connector->name == property) { \ 2134 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \ 2135 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ 2136 cmd = SDVO_CMD_SET_##NAME; \ 2137 intel_sdvo_connector->cur_##name = temp_value; \ 2138 goto set_value; \ 2139 } 2140 2141 if (property == intel_sdvo_connector->tv_format) { 2142 if (val >= TV_FORMAT_NUM) 2143 return -EINVAL; 2144 2145 if (intel_sdvo->tv_format_index == 2146 intel_sdvo_connector->tv_format_supported[val]) 2147 return 0; 2148 2149 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val]; 2150 goto done; 2151 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) { 2152 temp_value = val; 2153 if (intel_sdvo_connector->left == property) { 2154 drm_object_property_set_value(&connector->base, 2155 intel_sdvo_connector->right, val); 2156 if (intel_sdvo_connector->left_margin == temp_value) 2157 return 0; 2158 2159 intel_sdvo_connector->left_margin = temp_value; 2160 intel_sdvo_connector->right_margin = temp_value; 2161 temp_value = intel_sdvo_connector->max_hscan - 2162 intel_sdvo_connector->left_margin; 2163 cmd = SDVO_CMD_SET_OVERSCAN_H; 2164 goto set_value; 2165 } else if (intel_sdvo_connector->right == property) { 2166 drm_object_property_set_value(&connector->base, 2167 intel_sdvo_connector->left, val); 2168 if (intel_sdvo_connector->right_margin == temp_value) 2169 return 0; 2170 2171 intel_sdvo_connector->left_margin = temp_value; 2172 intel_sdvo_connector->right_margin = temp_value; 2173 temp_value = intel_sdvo_connector->max_hscan - 2174 intel_sdvo_connector->left_margin; 2175 cmd = SDVO_CMD_SET_OVERSCAN_H; 2176 goto set_value; 2177 } else if (intel_sdvo_connector->top == property) { 2178 drm_object_property_set_value(&connector->base, 2179 intel_sdvo_connector->bottom, val); 2180 if (intel_sdvo_connector->top_margin == temp_value) 2181 return 0; 2182 2183 intel_sdvo_connector->top_margin = temp_value; 2184 intel_sdvo_connector->bottom_margin = temp_value; 2185 temp_value = intel_sdvo_connector->max_vscan - 2186 intel_sdvo_connector->top_margin; 2187 cmd = SDVO_CMD_SET_OVERSCAN_V; 2188 goto set_value; 2189 } else if (intel_sdvo_connector->bottom == property) { 2190 drm_object_property_set_value(&connector->base, 2191 intel_sdvo_connector->top, val); 2192 if (intel_sdvo_connector->bottom_margin == temp_value) 2193 return 0; 2194 2195 intel_sdvo_connector->top_margin = temp_value; 2196 intel_sdvo_connector->bottom_margin = temp_value; 2197 temp_value = intel_sdvo_connector->max_vscan - 2198 intel_sdvo_connector->top_margin; 2199 cmd = SDVO_CMD_SET_OVERSCAN_V; 2200 goto set_value; 2201 } 2202 CHECK_PROPERTY(hpos, HPOS) 2203 CHECK_PROPERTY(vpos, VPOS) 2204 CHECK_PROPERTY(saturation, SATURATION) 2205 CHECK_PROPERTY(contrast, CONTRAST) 2206 CHECK_PROPERTY(hue, HUE) 2207 CHECK_PROPERTY(brightness, BRIGHTNESS) 2208 CHECK_PROPERTY(sharpness, SHARPNESS) 2209 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) 2210 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) 2211 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) 2212 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) 2213 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) 2214 CHECK_PROPERTY(dot_crawl, DOT_CRAWL) 2215 } 2216 2217 return -EINVAL; /* unknown property */ 2218 2219set_value: 2220 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2)) 2221 return -EIO; 2222 2223 2224done: 2225 if (intel_sdvo->base.base.crtc) 2226 intel_crtc_restore_mode(intel_sdvo->base.base.crtc); 2227 2228 return 0; 2229#undef CHECK_PROPERTY 2230} 2231 2232static const struct drm_connector_funcs intel_sdvo_connector_funcs = { 2233 .dpms = intel_sdvo_dpms, 2234 .detect = intel_sdvo_detect, 2235 .fill_modes = drm_helper_probe_single_connector_modes, 2236 .set_property = intel_sdvo_set_property, 2237 .destroy = intel_sdvo_destroy, 2238}; 2239 2240static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { 2241 .get_modes = intel_sdvo_get_modes, 2242 .mode_valid = intel_sdvo_mode_valid, 2243 .best_encoder = intel_best_encoder, 2244}; 2245 2246static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) 2247{ 2248 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder)); 2249 2250 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL) 2251 drm_mode_destroy(encoder->dev, 2252 intel_sdvo->sdvo_lvds_fixed_mode); 2253 2254 i2c_del_adapter(&intel_sdvo->ddc); 2255 intel_encoder_destroy(encoder); 2256} 2257 2258static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { 2259 .destroy = intel_sdvo_enc_destroy, 2260}; 2261 2262static void 2263intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) 2264{ 2265 uint16_t mask = 0; 2266 unsigned int num_bits; 2267 2268 /* Make a mask of outputs less than or equal to our own priority in the 2269 * list. 2270 */ 2271 switch (sdvo->controlled_output) { 2272 case SDVO_OUTPUT_LVDS1: 2273 mask |= SDVO_OUTPUT_LVDS1; 2274 case SDVO_OUTPUT_LVDS0: 2275 mask |= SDVO_OUTPUT_LVDS0; 2276 case SDVO_OUTPUT_TMDS1: 2277 mask |= SDVO_OUTPUT_TMDS1; 2278 case SDVO_OUTPUT_TMDS0: 2279 mask |= SDVO_OUTPUT_TMDS0; 2280 case SDVO_OUTPUT_RGB1: 2281 mask |= SDVO_OUTPUT_RGB1; 2282 case SDVO_OUTPUT_RGB0: 2283 mask |= SDVO_OUTPUT_RGB0; 2284 break; 2285 } 2286 2287 /* Count bits to find what number we are in the priority list. */ 2288 mask &= sdvo->caps.output_flags; 2289 num_bits = hweight16(mask); 2290 /* If more than 3 outputs, default to DDC bus 3 for now. */ 2291 if (num_bits > 3) 2292 num_bits = 3; 2293 2294 /* Corresponds to SDVO_CONTROL_BUS_DDCx */ 2295 sdvo->ddc_bus = 1 << num_bits; 2296} 2297 2298/** 2299 * Choose the appropriate DDC bus for control bus switch command for this 2300 * SDVO output based on the controlled output. 2301 * 2302 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS 2303 * outputs, then LVDS outputs. 2304 */ 2305static void 2306intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, 2307 struct intel_sdvo *sdvo, u32 reg) 2308{ 2309 struct sdvo_device_mapping *mapping; 2310 2311 if (sdvo->is_sdvob) 2312 mapping = &(dev_priv->sdvo_mappings[0]); 2313 else 2314 mapping = &(dev_priv->sdvo_mappings[1]); 2315 2316 if (mapping->initialized) 2317 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); 2318 else 2319 intel_sdvo_guess_ddc_bus(sdvo); 2320} 2321 2322static void 2323intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, 2324 struct intel_sdvo *sdvo, u32 reg) 2325{ 2326 struct sdvo_device_mapping *mapping; 2327 u8 pin; 2328 2329 if (sdvo->is_sdvob) 2330 mapping = &dev_priv->sdvo_mappings[0]; 2331 else 2332 mapping = &dev_priv->sdvo_mappings[1]; 2333 2334 if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin)) 2335 pin = mapping->i2c_pin; 2336 else 2337 pin = GMBUS_PORT_DPB; 2338 2339 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); 2340 2341 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow 2342 * our code totally fails once we start using gmbus. Hence fall back to 2343 * bit banging for now. */ 2344 intel_gmbus_force_bit(sdvo->i2c, true); 2345} 2346 2347/* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ 2348static void 2349intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) 2350{ 2351 intel_gmbus_force_bit(sdvo->i2c, false); 2352} 2353 2354static bool 2355intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device) 2356{ 2357 return intel_sdvo_check_supp_encode(intel_sdvo); 2358} 2359 2360static u8 2361intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo) 2362{ 2363 struct drm_i915_private *dev_priv = dev->dev_private; 2364 struct sdvo_device_mapping *my_mapping, *other_mapping; 2365 2366 if (sdvo->is_sdvob) { 2367 my_mapping = &dev_priv->sdvo_mappings[0]; 2368 other_mapping = &dev_priv->sdvo_mappings[1]; 2369 } else { 2370 my_mapping = &dev_priv->sdvo_mappings[1]; 2371 other_mapping = &dev_priv->sdvo_mappings[0]; 2372 } 2373 2374 /* If the BIOS described our SDVO device, take advantage of it. */ 2375 if (my_mapping->slave_addr) 2376 return my_mapping->slave_addr; 2377 2378 /* If the BIOS only described a different SDVO device, use the 2379 * address that it isn't using. 2380 */ 2381 if (other_mapping->slave_addr) { 2382 if (other_mapping->slave_addr == 0x70) 2383 return 0x72; 2384 else 2385 return 0x70; 2386 } 2387 2388 /* No SDVO device info is found for another DVO port, 2389 * so use mapping assumption we had before BIOS parsing. 2390 */ 2391 if (sdvo->is_sdvob) 2392 return 0x70; 2393 else 2394 return 0x72; 2395} 2396 2397static void 2398intel_sdvo_connector_unregister(struct intel_connector *intel_connector) 2399{ 2400 struct drm_connector *drm_connector; 2401 struct intel_sdvo *sdvo_encoder; 2402 2403 drm_connector = &intel_connector->base; 2404 sdvo_encoder = intel_attached_sdvo(&intel_connector->base); 2405 2406 sysfs_remove_link(&drm_connector->kdev->kobj, 2407 sdvo_encoder->ddc.dev.kobj.name); 2408 intel_connector_unregister(intel_connector); 2409} 2410 2411static int 2412intel_sdvo_connector_init(struct intel_sdvo_connector *connector, 2413 struct intel_sdvo *encoder) 2414{ 2415 struct drm_connector *drm_connector; 2416 int ret; 2417 2418 drm_connector = &connector->base.base; 2419 ret = drm_connector_init(encoder->base.base.dev, 2420 drm_connector, 2421 &intel_sdvo_connector_funcs, 2422 connector->base.base.connector_type); 2423 if (ret < 0) 2424 return ret; 2425 2426 drm_connector_helper_add(drm_connector, 2427 &intel_sdvo_connector_helper_funcs); 2428 2429 connector->base.base.interlace_allowed = 1; 2430 connector->base.base.doublescan_allowed = 0; 2431 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; 2432 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; 2433 connector->base.unregister = intel_sdvo_connector_unregister; 2434 2435 intel_connector_attach_encoder(&connector->base, &encoder->base); 2436 ret = drm_connector_register(drm_connector); 2437 if (ret < 0) 2438 goto err1; 2439 2440 ret = sysfs_create_link(&drm_connector->kdev->kobj, 2441 &encoder->ddc.dev.kobj, 2442 encoder->ddc.dev.kobj.name); 2443 if (ret < 0) 2444 goto err2; 2445 2446 return 0; 2447 2448err2: 2449 drm_connector_unregister(drm_connector); 2450err1: 2451 drm_connector_cleanup(drm_connector); 2452 2453 return ret; 2454} 2455 2456static void 2457intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, 2458 struct intel_sdvo_connector *connector) 2459{ 2460 struct drm_device *dev = connector->base.base.dev; 2461 2462 intel_attach_force_audio_property(&connector->base.base); 2463 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) { 2464 intel_attach_broadcast_rgb_property(&connector->base.base); 2465 intel_sdvo->color_range_auto = true; 2466 } 2467} 2468 2469static bool 2470intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) 2471{ 2472 struct drm_encoder *encoder = &intel_sdvo->base.base; 2473 struct drm_connector *connector; 2474 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2475 struct intel_connector *intel_connector; 2476 struct intel_sdvo_connector *intel_sdvo_connector; 2477 2478 DRM_DEBUG_KMS("initialising DVI device %d\n", device); 2479 2480 intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL); 2481 if (!intel_sdvo_connector) 2482 return false; 2483 2484 if (device == 0) { 2485 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; 2486 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; 2487 } else if (device == 1) { 2488 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; 2489 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; 2490 } 2491 2492 intel_connector = &intel_sdvo_connector->base; 2493 connector = &intel_connector->base; 2494 if (intel_sdvo_get_hotplug_support(intel_sdvo) & 2495 intel_sdvo_connector->output_flag) { 2496 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; 2497 /* Some SDVO devices have one-shot hotplug interrupts. 2498 * Ensure that they get re-enabled when an interrupt happens. 2499 */ 2500 intel_encoder->hot_plug = intel_sdvo_enable_hotplug; 2501 intel_sdvo_enable_hotplug(intel_encoder); 2502 } else { 2503 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 2504 } 2505 encoder->encoder_type = DRM_MODE_ENCODER_TMDS; 2506 connector->connector_type = DRM_MODE_CONNECTOR_DVID; 2507 2508 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { 2509 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 2510 intel_sdvo->is_hdmi = true; 2511 } 2512 2513 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2514 kfree(intel_sdvo_connector); 2515 return false; 2516 } 2517 2518 if (intel_sdvo->is_hdmi) 2519 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); 2520 2521 return true; 2522} 2523 2524static bool 2525intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) 2526{ 2527 struct drm_encoder *encoder = &intel_sdvo->base.base; 2528 struct drm_connector *connector; 2529 struct intel_connector *intel_connector; 2530 struct intel_sdvo_connector *intel_sdvo_connector; 2531 2532 DRM_DEBUG_KMS("initialising TV type %d\n", type); 2533 2534 intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL); 2535 if (!intel_sdvo_connector) 2536 return false; 2537 2538 intel_connector = &intel_sdvo_connector->base; 2539 connector = &intel_connector->base; 2540 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; 2541 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; 2542 2543 intel_sdvo->controlled_output |= type; 2544 intel_sdvo_connector->output_flag = type; 2545 2546 intel_sdvo->is_tv = true; 2547 2548 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2549 kfree(intel_sdvo_connector); 2550 return false; 2551 } 2552 2553 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) 2554 goto err; 2555 2556 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2557 goto err; 2558 2559 return true; 2560 2561err: 2562 drm_connector_unregister(connector); 2563 intel_sdvo_destroy(connector); 2564 return false; 2565} 2566 2567static bool 2568intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) 2569{ 2570 struct drm_encoder *encoder = &intel_sdvo->base.base; 2571 struct drm_connector *connector; 2572 struct intel_connector *intel_connector; 2573 struct intel_sdvo_connector *intel_sdvo_connector; 2574 2575 DRM_DEBUG_KMS("initialising analog device %d\n", device); 2576 2577 intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL); 2578 if (!intel_sdvo_connector) 2579 return false; 2580 2581 intel_connector = &intel_sdvo_connector->base; 2582 connector = &intel_connector->base; 2583 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 2584 encoder->encoder_type = DRM_MODE_ENCODER_DAC; 2585 connector->connector_type = DRM_MODE_CONNECTOR_VGA; 2586 2587 if (device == 0) { 2588 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; 2589 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; 2590 } else if (device == 1) { 2591 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; 2592 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; 2593 } 2594 2595 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2596 kfree(intel_sdvo_connector); 2597 return false; 2598 } 2599 2600 return true; 2601} 2602 2603static bool 2604intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) 2605{ 2606 struct drm_encoder *encoder = &intel_sdvo->base.base; 2607 struct drm_connector *connector; 2608 struct intel_connector *intel_connector; 2609 struct intel_sdvo_connector *intel_sdvo_connector; 2610 2611 DRM_DEBUG_KMS("initialising LVDS device %d\n", device); 2612 2613 intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL); 2614 if (!intel_sdvo_connector) 2615 return false; 2616 2617 intel_connector = &intel_sdvo_connector->base; 2618 connector = &intel_connector->base; 2619 encoder->encoder_type = DRM_MODE_ENCODER_LVDS; 2620 connector->connector_type = DRM_MODE_CONNECTOR_LVDS; 2621 2622 if (device == 0) { 2623 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; 2624 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; 2625 } else if (device == 1) { 2626 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; 2627 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; 2628 } 2629 2630 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2631 kfree(intel_sdvo_connector); 2632 return false; 2633 } 2634 2635 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2636 goto err; 2637 2638 return true; 2639 2640err: 2641 drm_connector_unregister(connector); 2642 intel_sdvo_destroy(connector); 2643 return false; 2644} 2645 2646static bool 2647intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) 2648{ 2649 intel_sdvo->is_tv = false; 2650 intel_sdvo->is_lvds = false; 2651 2652 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ 2653 2654 if (flags & SDVO_OUTPUT_TMDS0) 2655 if (!intel_sdvo_dvi_init(intel_sdvo, 0)) 2656 return false; 2657 2658 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) 2659 if (!intel_sdvo_dvi_init(intel_sdvo, 1)) 2660 return false; 2661 2662 /* TV has no XXX1 function block */ 2663 if (flags & SDVO_OUTPUT_SVID0) 2664 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) 2665 return false; 2666 2667 if (flags & SDVO_OUTPUT_CVBS0) 2668 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) 2669 return false; 2670 2671 if (flags & SDVO_OUTPUT_YPRPB0) 2672 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0)) 2673 return false; 2674 2675 if (flags & SDVO_OUTPUT_RGB0) 2676 if (!intel_sdvo_analog_init(intel_sdvo, 0)) 2677 return false; 2678 2679 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) 2680 if (!intel_sdvo_analog_init(intel_sdvo, 1)) 2681 return false; 2682 2683 if (flags & SDVO_OUTPUT_LVDS0) 2684 if (!intel_sdvo_lvds_init(intel_sdvo, 0)) 2685 return false; 2686 2687 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) 2688 if (!intel_sdvo_lvds_init(intel_sdvo, 1)) 2689 return false; 2690 2691 if ((flags & SDVO_OUTPUT_MASK) == 0) { 2692 unsigned char bytes[2]; 2693 2694 intel_sdvo->controlled_output = 0; 2695 memcpy(bytes, &intel_sdvo->caps.output_flags, 2); 2696 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", 2697 SDVO_NAME(intel_sdvo), 2698 bytes[0], bytes[1]); 2699 return false; 2700 } 2701 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 2702 2703 return true; 2704} 2705 2706static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) 2707{ 2708 struct drm_device *dev = intel_sdvo->base.base.dev; 2709 struct drm_connector *connector, *tmp; 2710 2711 list_for_each_entry_safe(connector, tmp, 2712 &dev->mode_config.connector_list, head) { 2713 if (intel_attached_encoder(connector) == &intel_sdvo->base) { 2714 drm_connector_unregister(connector); 2715 intel_sdvo_destroy(connector); 2716 } 2717 } 2718} 2719 2720static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 2721 struct intel_sdvo_connector *intel_sdvo_connector, 2722 int type) 2723{ 2724 struct drm_device *dev = intel_sdvo->base.base.dev; 2725 struct intel_sdvo_tv_format format; 2726 uint32_t format_map, i; 2727 2728 if (!intel_sdvo_set_target_output(intel_sdvo, type)) 2729 return false; 2730 2731 BUILD_BUG_ON(sizeof(format) != 6); 2732 if (!intel_sdvo_get_value(intel_sdvo, 2733 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, 2734 &format, sizeof(format))) 2735 return false; 2736 2737 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); 2738 2739 if (format_map == 0) 2740 return false; 2741 2742 intel_sdvo_connector->format_supported_num = 0; 2743 for (i = 0 ; i < TV_FORMAT_NUM; i++) 2744 if (format_map & (1 << i)) 2745 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; 2746 2747 2748 intel_sdvo_connector->tv_format = 2749 drm_property_create(dev, DRM_MODE_PROP_ENUM, 2750 "mode", intel_sdvo_connector->format_supported_num); 2751 if (!intel_sdvo_connector->tv_format) 2752 return false; 2753 2754 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 2755 drm_property_add_enum( 2756 intel_sdvo_connector->tv_format, i, 2757 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); 2758 2759 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0]; 2760 drm_object_attach_property(&intel_sdvo_connector->base.base.base, 2761 intel_sdvo_connector->tv_format, 0); 2762 return true; 2763 2764} 2765 2766#define ENHANCEMENT(name, NAME) do { \ 2767 if (enhancements.name) { \ 2768 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ 2769 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ 2770 return false; \ 2771 intel_sdvo_connector->max_##name = data_value[0]; \ 2772 intel_sdvo_connector->cur_##name = response; \ 2773 intel_sdvo_connector->name = \ 2774 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ 2775 if (!intel_sdvo_connector->name) return false; \ 2776 drm_object_attach_property(&connector->base, \ 2777 intel_sdvo_connector->name, \ 2778 intel_sdvo_connector->cur_##name); \ 2779 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ 2780 data_value[0], data_value[1], response); \ 2781 } \ 2782} while (0) 2783 2784static bool 2785intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, 2786 struct intel_sdvo_connector *intel_sdvo_connector, 2787 struct intel_sdvo_enhancements_reply enhancements) 2788{ 2789 struct drm_device *dev = intel_sdvo->base.base.dev; 2790 struct drm_connector *connector = &intel_sdvo_connector->base.base; 2791 uint16_t response, data_value[2]; 2792 2793 /* when horizontal overscan is supported, Add the left/right property */ 2794 if (enhancements.overscan_h) { 2795 if (!intel_sdvo_get_value(intel_sdvo, 2796 SDVO_CMD_GET_MAX_OVERSCAN_H, 2797 &data_value, 4)) 2798 return false; 2799 2800 if (!intel_sdvo_get_value(intel_sdvo, 2801 SDVO_CMD_GET_OVERSCAN_H, 2802 &response, 2)) 2803 return false; 2804 2805 intel_sdvo_connector->max_hscan = data_value[0]; 2806 intel_sdvo_connector->left_margin = data_value[0] - response; 2807 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; 2808 intel_sdvo_connector->left = 2809 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); 2810 if (!intel_sdvo_connector->left) 2811 return false; 2812 2813 drm_object_attach_property(&connector->base, 2814 intel_sdvo_connector->left, 2815 intel_sdvo_connector->left_margin); 2816 2817 intel_sdvo_connector->right = 2818 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); 2819 if (!intel_sdvo_connector->right) 2820 return false; 2821 2822 drm_object_attach_property(&connector->base, 2823 intel_sdvo_connector->right, 2824 intel_sdvo_connector->right_margin); 2825 DRM_DEBUG_KMS("h_overscan: max %d, " 2826 "default %d, current %d\n", 2827 data_value[0], data_value[1], response); 2828 } 2829 2830 if (enhancements.overscan_v) { 2831 if (!intel_sdvo_get_value(intel_sdvo, 2832 SDVO_CMD_GET_MAX_OVERSCAN_V, 2833 &data_value, 4)) 2834 return false; 2835 2836 if (!intel_sdvo_get_value(intel_sdvo, 2837 SDVO_CMD_GET_OVERSCAN_V, 2838 &response, 2)) 2839 return false; 2840 2841 intel_sdvo_connector->max_vscan = data_value[0]; 2842 intel_sdvo_connector->top_margin = data_value[0] - response; 2843 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; 2844 intel_sdvo_connector->top = 2845 drm_property_create_range(dev, 0, 2846 "top_margin", 0, data_value[0]); 2847 if (!intel_sdvo_connector->top) 2848 return false; 2849 2850 drm_object_attach_property(&connector->base, 2851 intel_sdvo_connector->top, 2852 intel_sdvo_connector->top_margin); 2853 2854 intel_sdvo_connector->bottom = 2855 drm_property_create_range(dev, 0, 2856 "bottom_margin", 0, data_value[0]); 2857 if (!intel_sdvo_connector->bottom) 2858 return false; 2859 2860 drm_object_attach_property(&connector->base, 2861 intel_sdvo_connector->bottom, 2862 intel_sdvo_connector->bottom_margin); 2863 DRM_DEBUG_KMS("v_overscan: max %d, " 2864 "default %d, current %d\n", 2865 data_value[0], data_value[1], response); 2866 } 2867 2868 ENHANCEMENT(hpos, HPOS); 2869 ENHANCEMENT(vpos, VPOS); 2870 ENHANCEMENT(saturation, SATURATION); 2871 ENHANCEMENT(contrast, CONTRAST); 2872 ENHANCEMENT(hue, HUE); 2873 ENHANCEMENT(sharpness, SHARPNESS); 2874 ENHANCEMENT(brightness, BRIGHTNESS); 2875 ENHANCEMENT(flicker_filter, FLICKER_FILTER); 2876 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 2877 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); 2878 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); 2879 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); 2880 2881 if (enhancements.dot_crawl) { 2882 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) 2883 return false; 2884 2885 intel_sdvo_connector->max_dot_crawl = 1; 2886 intel_sdvo_connector->cur_dot_crawl = response & 0x1; 2887 intel_sdvo_connector->dot_crawl = 2888 drm_property_create_range(dev, 0, "dot_crawl", 0, 1); 2889 if (!intel_sdvo_connector->dot_crawl) 2890 return false; 2891 2892 drm_object_attach_property(&connector->base, 2893 intel_sdvo_connector->dot_crawl, 2894 intel_sdvo_connector->cur_dot_crawl); 2895 DRM_DEBUG_KMS("dot crawl: current %d\n", response); 2896 } 2897 2898 return true; 2899} 2900 2901static bool 2902intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, 2903 struct intel_sdvo_connector *intel_sdvo_connector, 2904 struct intel_sdvo_enhancements_reply enhancements) 2905{ 2906 struct drm_device *dev = intel_sdvo->base.base.dev; 2907 struct drm_connector *connector = &intel_sdvo_connector->base.base; 2908 uint16_t response, data_value[2]; 2909 2910 ENHANCEMENT(brightness, BRIGHTNESS); 2911 2912 return true; 2913} 2914#undef ENHANCEMENT 2915 2916static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 2917 struct intel_sdvo_connector *intel_sdvo_connector) 2918{ 2919 union { 2920 struct intel_sdvo_enhancements_reply reply; 2921 uint16_t response; 2922 } enhancements; 2923 2924 BUILD_BUG_ON(sizeof(enhancements) != 2); 2925 2926 enhancements.response = 0; 2927 intel_sdvo_get_value(intel_sdvo, 2928 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, 2929 &enhancements, sizeof(enhancements)); 2930 if (enhancements.response == 0) { 2931 DRM_DEBUG_KMS("No enhancement is supported\n"); 2932 return true; 2933 } 2934 2935 if (IS_TV(intel_sdvo_connector)) 2936 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); 2937 else if (IS_LVDS(intel_sdvo_connector)) 2938 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); 2939 else 2940 return true; 2941} 2942 2943static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, 2944 struct i2c_msg *msgs, 2945 int num) 2946{ 2947 struct intel_sdvo *sdvo = adapter->algo_data; 2948 2949 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) 2950 return -EIO; 2951 2952 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); 2953} 2954 2955static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) 2956{ 2957 struct intel_sdvo *sdvo = adapter->algo_data; 2958 return sdvo->i2c->algo->functionality(sdvo->i2c); 2959} 2960 2961static const struct i2c_algorithm intel_sdvo_ddc_proxy = { 2962 .master_xfer = intel_sdvo_ddc_proxy_xfer, 2963 .functionality = intel_sdvo_ddc_proxy_func 2964}; 2965 2966static bool 2967intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, 2968 struct drm_device *dev) 2969{ 2970 sdvo->ddc.owner = THIS_MODULE; 2971 sdvo->ddc.class = I2C_CLASS_DDC; 2972 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy"); 2973 sdvo->ddc.dev.parent = &dev->pdev->dev; 2974 sdvo->ddc.algo_data = sdvo; 2975 sdvo->ddc.algo = &intel_sdvo_ddc_proxy; 2976 2977 return i2c_add_adapter(&sdvo->ddc) == 0; 2978} 2979 2980bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob) 2981{ 2982 struct drm_i915_private *dev_priv = dev->dev_private; 2983 struct intel_encoder *intel_encoder; 2984 struct intel_sdvo *intel_sdvo; 2985 int i; 2986 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL); 2987 if (!intel_sdvo) 2988 return false; 2989 2990 intel_sdvo->sdvo_reg = sdvo_reg; 2991 intel_sdvo->is_sdvob = is_sdvob; 2992 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1; 2993 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg); 2994 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) 2995 goto err_i2c_bus; 2996 2997 /* encoder type will be decided later */ 2998 intel_encoder = &intel_sdvo->base; 2999 intel_encoder->type = INTEL_OUTPUT_SDVO; 3000 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0); 3001 3002 /* Read the regs to test if we can talk to the device */ 3003 for (i = 0; i < 0x40; i++) { 3004 u8 byte; 3005 3006 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { 3007 DRM_DEBUG_KMS("No SDVO device found on %s\n", 3008 SDVO_NAME(intel_sdvo)); 3009 goto err; 3010 } 3011 } 3012 3013 intel_encoder->compute_config = intel_sdvo_compute_config; 3014 intel_encoder->disable = intel_disable_sdvo; 3015 intel_encoder->pre_enable = intel_sdvo_pre_enable; 3016 intel_encoder->enable = intel_enable_sdvo; 3017 intel_encoder->get_hw_state = intel_sdvo_get_hw_state; 3018 intel_encoder->get_config = intel_sdvo_get_config; 3019 3020 /* In default case sdvo lvds is false */ 3021 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) 3022 goto err; 3023 3024 if (intel_sdvo_output_setup(intel_sdvo, 3025 intel_sdvo->caps.output_flags) != true) { 3026 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n", 3027 SDVO_NAME(intel_sdvo)); 3028 /* Output_setup can leave behind connectors! */ 3029 goto err_output; 3030 } 3031 3032 /* Only enable the hotplug irq if we need it, to work around noisy 3033 * hotplug lines. 3034 */ 3035 if (intel_sdvo->hotplug_active) { 3036 intel_encoder->hpd_pin = 3037 intel_sdvo->is_sdvob ? HPD_SDVO_B : HPD_SDVO_C; 3038 } 3039 3040 /* 3041 * Cloning SDVO with anything is often impossible, since the SDVO 3042 * encoder can request a special input timing mode. And even if that's 3043 * not the case we have evidence that cloning a plain unscaled mode with 3044 * VGA doesn't really work. Furthermore the cloning flags are way too 3045 * simplistic anyway to express such constraints, so just give up on 3046 * cloning for SDVO encoders. 3047 */ 3048 intel_sdvo->base.cloneable = 0; 3049 3050 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg); 3051 3052 /* Set the input timing to the screen. Assume always input 0. */ 3053 if (!intel_sdvo_set_target_input(intel_sdvo)) 3054 goto err_output; 3055 3056 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, 3057 &intel_sdvo->pixel_clock_min, 3058 &intel_sdvo->pixel_clock_max)) 3059 goto err_output; 3060 3061 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " 3062 "clock range %dMHz - %dMHz, " 3063 "input 1: %c, input 2: %c, " 3064 "output 1: %c, output 2: %c\n", 3065 SDVO_NAME(intel_sdvo), 3066 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, 3067 intel_sdvo->caps.device_rev_id, 3068 intel_sdvo->pixel_clock_min / 1000, 3069 intel_sdvo->pixel_clock_max / 1000, 3070 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', 3071 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', 3072 /* check currently supported outputs */ 3073 intel_sdvo->caps.output_flags & 3074 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', 3075 intel_sdvo->caps.output_flags & 3076 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); 3077 return true; 3078 3079err_output: 3080 intel_sdvo_output_cleanup(intel_sdvo); 3081 3082err: 3083 drm_encoder_cleanup(&intel_encoder->base); 3084 i2c_del_adapter(&intel_sdvo->ddc); 3085err_i2c_bus: 3086 intel_sdvo_unselect_i2c_bus(intel_sdvo); 3087 kfree(intel_sdvo); 3088 3089 return false; 3090} 3091