mdp4.xml.h revision facb4f4e7fae93ddfcfc2a5f2d0417185a7029ed
1#ifndef MDP4_XML 2#define MDP4_XML 3 4/* Autogenerated file, DO NOT EDIT manually! 5 6This file was generated by the rules-ng-ng headergen tool in this git repository: 7http://github.com/freedreno/envytools/ 8git clone https://github.com/freedreno/envytools.git 9 10The rules-ng-ng source files this header was generated from are: 11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 647 bytes, from 2013-11-30 14:45:35) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31) 14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52) 15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05) 19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) 20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04) 21 22Copyright (C) 2013 by the following authors: 23- Rob Clark <robdclark@gmail.com> (robclark) 24 25Permission is hereby granted, free of charge, to any person obtaining 26a copy of this software and associated documentation files (the 27"Software"), to deal in the Software without restriction, including 28without limitation the rights to use, copy, modify, merge, publish, 29distribute, sublicense, and/or sell copies of the Software, and to 30permit persons to whom the Software is furnished to do so, subject to 31the following conditions: 32 33The above copyright notice and this permission notice (including the 34next paragraph) shall be included in all copies or substantial 35portions of the Software. 36 37THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 38EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 39MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 40IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 41LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 42OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 43WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 44*/ 45 46 47enum mdp4_pipe { 48 VG1 = 0, 49 VG2 = 1, 50 RGB1 = 2, 51 RGB2 = 3, 52 RGB3 = 4, 53 VG3 = 5, 54 VG4 = 6, 55}; 56 57enum mdp4_mixer { 58 MIXER0 = 0, 59 MIXER1 = 1, 60 MIXER2 = 2, 61}; 62 63enum mdp4_intf { 64 INTF_LCDC_DTV = 0, 65 INTF_DSI_VIDEO = 1, 66 INTF_DSI_CMD = 2, 67 INTF_EBI2_TV = 3, 68}; 69 70enum mdp4_cursor_format { 71 CURSOR_ARGB = 1, 72 CURSOR_XRGB = 2, 73}; 74 75enum mdp4_dma { 76 DMA_P = 0, 77 DMA_S = 1, 78 DMA_E = 2, 79}; 80 81#define MDP4_IRQ_OVERLAY0_DONE 0x00000001 82#define MDP4_IRQ_OVERLAY1_DONE 0x00000002 83#define MDP4_IRQ_DMA_S_DONE 0x00000004 84#define MDP4_IRQ_DMA_E_DONE 0x00000008 85#define MDP4_IRQ_DMA_P_DONE 0x00000010 86#define MDP4_IRQ_VG1_HISTOGRAM 0x00000020 87#define MDP4_IRQ_VG2_HISTOGRAM 0x00000040 88#define MDP4_IRQ_PRIMARY_VSYNC 0x00000080 89#define MDP4_IRQ_PRIMARY_INTF_UDERRUN 0x00000100 90#define MDP4_IRQ_EXTERNAL_VSYNC 0x00000200 91#define MDP4_IRQ_EXTERNAL_INTF_UDERRUN 0x00000400 92#define MDP4_IRQ_PRIMARY_RDPTR 0x00000800 93#define MDP4_IRQ_DMA_P_HISTOGRAM 0x00020000 94#define MDP4_IRQ_DMA_S_HISTOGRAM 0x04000000 95#define MDP4_IRQ_OVERLAY2_DONE 0x40000000 96#define REG_MDP4_VERSION 0x00000000 97#define MDP4_VERSION_MINOR__MASK 0x00ff0000 98#define MDP4_VERSION_MINOR__SHIFT 16 99static inline uint32_t MDP4_VERSION_MINOR(uint32_t val) 100{ 101 return ((val) << MDP4_VERSION_MINOR__SHIFT) & MDP4_VERSION_MINOR__MASK; 102} 103#define MDP4_VERSION_MAJOR__MASK 0xff000000 104#define MDP4_VERSION_MAJOR__SHIFT 24 105static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val) 106{ 107 return ((val) << MDP4_VERSION_MAJOR__SHIFT) & MDP4_VERSION_MAJOR__MASK; 108} 109 110#define REG_MDP4_OVLP0_KICK 0x00000004 111 112#define REG_MDP4_OVLP1_KICK 0x00000008 113 114#define REG_MDP4_OVLP2_KICK 0x000000d0 115 116#define REG_MDP4_DMA_P_KICK 0x0000000c 117 118#define REG_MDP4_DMA_S_KICK 0x00000010 119 120#define REG_MDP4_DMA_E_KICK 0x00000014 121 122#define REG_MDP4_DISP_STATUS 0x00000018 123 124#define REG_MDP4_DISP_INTF_SEL 0x00000038 125#define MDP4_DISP_INTF_SEL_PRIM__MASK 0x00000003 126#define MDP4_DISP_INTF_SEL_PRIM__SHIFT 0 127static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val) 128{ 129 return ((val) << MDP4_DISP_INTF_SEL_PRIM__SHIFT) & MDP4_DISP_INTF_SEL_PRIM__MASK; 130} 131#define MDP4_DISP_INTF_SEL_SEC__MASK 0x0000000c 132#define MDP4_DISP_INTF_SEL_SEC__SHIFT 2 133static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val) 134{ 135 return ((val) << MDP4_DISP_INTF_SEL_SEC__SHIFT) & MDP4_DISP_INTF_SEL_SEC__MASK; 136} 137#define MDP4_DISP_INTF_SEL_EXT__MASK 0x00000030 138#define MDP4_DISP_INTF_SEL_EXT__SHIFT 4 139static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val) 140{ 141 return ((val) << MDP4_DISP_INTF_SEL_EXT__SHIFT) & MDP4_DISP_INTF_SEL_EXT__MASK; 142} 143#define MDP4_DISP_INTF_SEL_DSI_VIDEO 0x00000040 144#define MDP4_DISP_INTF_SEL_DSI_CMD 0x00000080 145 146#define REG_MDP4_RESET_STATUS 0x0000003c 147 148#define REG_MDP4_READ_CNFG 0x0000004c 149 150#define REG_MDP4_INTR_ENABLE 0x00000050 151 152#define REG_MDP4_INTR_STATUS 0x00000054 153 154#define REG_MDP4_INTR_CLEAR 0x00000058 155 156#define REG_MDP4_EBI2_LCD0 0x00000060 157 158#define REG_MDP4_EBI2_LCD1 0x00000064 159 160#define REG_MDP4_PORTMAP_MODE 0x00000070 161 162#define REG_MDP4_CS_CONTROLLER0 0x000000c0 163 164#define REG_MDP4_CS_CONTROLLER1 0x000000c4 165 166#define REG_MDP4_LAYERMIXER2_IN_CFG 0x000100f0 167#define MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK 0x00000007 168#define MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT 0 169static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) 170{ 171 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK; 172} 173#define MDP4_LAYERMIXER2_IN_CFG_PIPE0_MIXER1 0x00000008 174#define MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK 0x00000070 175#define MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT 4 176static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) 177{ 178 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK; 179} 180#define MDP4_LAYERMIXER2_IN_CFG_PIPE1_MIXER1 0x00000080 181#define MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK 0x00000700 182#define MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT 8 183static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) 184{ 185 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK; 186} 187#define MDP4_LAYERMIXER2_IN_CFG_PIPE2_MIXER1 0x00000800 188#define MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK 0x00007000 189#define MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT 12 190static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) 191{ 192 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK; 193} 194#define MDP4_LAYERMIXER2_IN_CFG_PIPE3_MIXER1 0x00008000 195#define MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK 0x00070000 196#define MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT 16 197static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) 198{ 199 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK; 200} 201#define MDP4_LAYERMIXER2_IN_CFG_PIPE4_MIXER1 0x00080000 202#define MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK 0x00700000 203#define MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT 20 204static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val) 205{ 206 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK; 207} 208#define MDP4_LAYERMIXER2_IN_CFG_PIPE5_MIXER1 0x00800000 209#define MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK 0x07000000 210#define MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT 24 211static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val) 212{ 213 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK; 214} 215#define MDP4_LAYERMIXER2_IN_CFG_PIPE6_MIXER1 0x08000000 216#define MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK 0x70000000 217#define MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT 28 218static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val) 219{ 220 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK; 221} 222#define MDP4_LAYERMIXER2_IN_CFG_PIPE7_MIXER1 0x80000000 223 224#define REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD 0x000100fc 225 226#define REG_MDP4_LAYERMIXER_IN_CFG 0x00010100 227#define MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK 0x00000007 228#define MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT 0 229static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) 230{ 231 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK; 232} 233#define MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1 0x00000008 234#define MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK 0x00000070 235#define MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT 4 236static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) 237{ 238 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK; 239} 240#define MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1 0x00000080 241#define MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK 0x00000700 242#define MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT 8 243static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) 244{ 245 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK; 246} 247#define MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1 0x00000800 248#define MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK 0x00007000 249#define MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT 12 250static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) 251{ 252 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK; 253} 254#define MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1 0x00008000 255#define MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK 0x00070000 256#define MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT 16 257static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) 258{ 259 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK; 260} 261#define MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1 0x00080000 262#define MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK 0x00700000 263#define MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT 20 264static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val) 265{ 266 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK; 267} 268#define MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1 0x00800000 269#define MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK 0x07000000 270#define MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT 24 271static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val) 272{ 273 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK; 274} 275#define MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1 0x08000000 276#define MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK 0x70000000 277#define MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT 28 278static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val) 279{ 280 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK; 281} 282#define MDP4_LAYERMIXER_IN_CFG_PIPE7_MIXER1 0x80000000 283 284#define REG_MDP4_VG2_SRC_FORMAT 0x00030050 285 286#define REG_MDP4_VG2_CONST_COLOR 0x00031008 287 288#define REG_MDP4_OVERLAY_FLUSH 0x00018000 289#define MDP4_OVERLAY_FLUSH_OVLP0 0x00000001 290#define MDP4_OVERLAY_FLUSH_OVLP1 0x00000002 291#define MDP4_OVERLAY_FLUSH_VG1 0x00000004 292#define MDP4_OVERLAY_FLUSH_VG2 0x00000008 293#define MDP4_OVERLAY_FLUSH_RGB1 0x00000010 294#define MDP4_OVERLAY_FLUSH_RGB2 0x00000020 295 296static inline uint32_t __offset_OVLP(uint32_t idx) 297{ 298 switch (idx) { 299 case 0: return 0x00010000; 300 case 1: return 0x00018000; 301 case 2: return 0x00088000; 302 default: return INVALID_IDX(idx); 303 } 304} 305static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); } 306 307static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); } 308 309static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); } 310#define MDP4_OVLP_SIZE_HEIGHT__MASK 0xffff0000 311#define MDP4_OVLP_SIZE_HEIGHT__SHIFT 16 312static inline uint32_t MDP4_OVLP_SIZE_HEIGHT(uint32_t val) 313{ 314 return ((val) << MDP4_OVLP_SIZE_HEIGHT__SHIFT) & MDP4_OVLP_SIZE_HEIGHT__MASK; 315} 316#define MDP4_OVLP_SIZE_WIDTH__MASK 0x0000ffff 317#define MDP4_OVLP_SIZE_WIDTH__SHIFT 0 318static inline uint32_t MDP4_OVLP_SIZE_WIDTH(uint32_t val) 319{ 320 return ((val) << MDP4_OVLP_SIZE_WIDTH__SHIFT) & MDP4_OVLP_SIZE_WIDTH__MASK; 321} 322 323static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); } 324 325static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); } 326 327static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); } 328 329static inline uint32_t __offset_STAGE(uint32_t idx) 330{ 331 switch (idx) { 332 case 0: return 0x00000104; 333 case 1: return 0x00000124; 334 case 2: return 0x00000144; 335 case 3: return 0x00000160; 336 default: return INVALID_IDX(idx); 337 } 338} 339static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } 340 341static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } 342#define MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK 0x00000003 343#define MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT 0 344static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val) 345{ 346 return ((val) << MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK; 347} 348#define MDP4_OVLP_STAGE_OP_FG_INV_ALPHA 0x00000004 349#define MDP4_OVLP_STAGE_OP_FG_MOD_ALPHA 0x00000008 350#define MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK 0x00000030 351#define MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT 4 352static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val) 353{ 354 return ((val) << MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK; 355} 356#define MDP4_OVLP_STAGE_OP_BG_INV_ALPHA 0x00000040 357#define MDP4_OVLP_STAGE_OP_BG_MOD_ALPHA 0x00000080 358#define MDP4_OVLP_STAGE_OP_FG_TRANSP 0x00000100 359#define MDP4_OVLP_STAGE_OP_BG_TRANSP 0x00000200 360 361static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_OVLP(i0) + __offset_STAGE(i1); } 362 363static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_OVLP(i0) + __offset_STAGE(i1); } 364 365static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_OVLP(i0) + __offset_STAGE(i1); } 366 367static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_OVLP(i0) + __offset_STAGE(i1); } 368 369static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_OVLP(i0) + __offset_STAGE(i1); } 370 371static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_OVLP(i0) + __offset_STAGE(i1); } 372 373static inline uint32_t __offset_STAGE_CO3(uint32_t idx) 374{ 375 switch (idx) { 376 case 0: return 0x00001004; 377 case 1: return 0x00001404; 378 case 2: return 0x00001804; 379 case 3: return 0x00001b84; 380 default: return INVALID_IDX(idx); 381 } 382} 383static inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); } 384 385static inline uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); } 386#define MDP4_OVLP_STAGE_CO3_SEL_FG_ALPHA 0x00000001 387 388static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) { return 0x00000180 + __offset_OVLP(i0); } 389 390static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) { return 0x00000184 + __offset_OVLP(i0); } 391 392static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) { return 0x00000188 + __offset_OVLP(i0); } 393 394static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) { return 0x0000018c + __offset_OVLP(i0); } 395 396static inline uint32_t REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) { return 0x00000200 + __offset_OVLP(i0); } 397 398static inline uint32_t REG_MDP4_OVLP_CSC(uint32_t i0) { return 0x00002000 + __offset_OVLP(i0); } 399 400 401static inline uint32_t REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; } 402 403static inline uint32_t REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; } 404 405static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; } 406 407static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; } 408 409static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; } 410 411static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; } 412 413static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; } 414 415static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; } 416 417static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; } 418 419static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; } 420 421#define REG_MDP4_DMA_P_OP_MODE 0x00090070 422 423static inline uint32_t REG_MDP4_LUTN(uint32_t i0) { return 0x00094800 + 0x400*i0; } 424 425static inline uint32_t REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; } 426 427static inline uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; } 428 429#define REG_MDP4_DMA_S_OP_MODE 0x000a0028 430 431static inline uint32_t REG_MDP4_DMA_E_QUANT(uint32_t i0) { return 0x000b0070 + 0x4*i0; } 432 433static inline uint32_t __offset_DMA(enum mdp4_dma idx) 434{ 435 switch (idx) { 436 case DMA_P: return 0x00090000; 437 case DMA_S: return 0x000a0000; 438 case DMA_E: return 0x000b0000; 439 default: return INVALID_IDX(idx); 440 } 441} 442static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); } 443 444static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); } 445#define MDP4_DMA_CONFIG_G_BPC__MASK 0x00000003 446#define MDP4_DMA_CONFIG_G_BPC__SHIFT 0 447static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val) 448{ 449 return ((val) << MDP4_DMA_CONFIG_G_BPC__SHIFT) & MDP4_DMA_CONFIG_G_BPC__MASK; 450} 451#define MDP4_DMA_CONFIG_B_BPC__MASK 0x0000000c 452#define MDP4_DMA_CONFIG_B_BPC__SHIFT 2 453static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val) 454{ 455 return ((val) << MDP4_DMA_CONFIG_B_BPC__SHIFT) & MDP4_DMA_CONFIG_B_BPC__MASK; 456} 457#define MDP4_DMA_CONFIG_R_BPC__MASK 0x00000030 458#define MDP4_DMA_CONFIG_R_BPC__SHIFT 4 459static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val) 460{ 461 return ((val) << MDP4_DMA_CONFIG_R_BPC__SHIFT) & MDP4_DMA_CONFIG_R_BPC__MASK; 462} 463#define MDP4_DMA_CONFIG_PACK_ALIGN_MSB 0x00000080 464#define MDP4_DMA_CONFIG_PACK__MASK 0x0000ff00 465#define MDP4_DMA_CONFIG_PACK__SHIFT 8 466static inline uint32_t MDP4_DMA_CONFIG_PACK(uint32_t val) 467{ 468 return ((val) << MDP4_DMA_CONFIG_PACK__SHIFT) & MDP4_DMA_CONFIG_PACK__MASK; 469} 470#define MDP4_DMA_CONFIG_DEFLKR_EN 0x01000000 471#define MDP4_DMA_CONFIG_DITHER_EN 0x01000000 472 473static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i0); } 474#define MDP4_DMA_SRC_SIZE_HEIGHT__MASK 0xffff0000 475#define MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT 16 476static inline uint32_t MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val) 477{ 478 return ((val) << MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT) & MDP4_DMA_SRC_SIZE_HEIGHT__MASK; 479} 480#define MDP4_DMA_SRC_SIZE_WIDTH__MASK 0x0000ffff 481#define MDP4_DMA_SRC_SIZE_WIDTH__SHIFT 0 482static inline uint32_t MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val) 483{ 484 return ((val) << MDP4_DMA_SRC_SIZE_WIDTH__SHIFT) & MDP4_DMA_SRC_SIZE_WIDTH__MASK; 485} 486 487static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i0); } 488 489static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA(i0); } 490 491static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i0); } 492#define MDP4_DMA_DST_SIZE_HEIGHT__MASK 0xffff0000 493#define MDP4_DMA_DST_SIZE_HEIGHT__SHIFT 16 494static inline uint32_t MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val) 495{ 496 return ((val) << MDP4_DMA_DST_SIZE_HEIGHT__SHIFT) & MDP4_DMA_DST_SIZE_HEIGHT__MASK; 497} 498#define MDP4_DMA_DST_SIZE_WIDTH__MASK 0x0000ffff 499#define MDP4_DMA_DST_SIZE_WIDTH__SHIFT 0 500static inline uint32_t MDP4_DMA_DST_SIZE_WIDTH(uint32_t val) 501{ 502 return ((val) << MDP4_DMA_DST_SIZE_WIDTH__SHIFT) & MDP4_DMA_DST_SIZE_WIDTH__MASK; 503} 504 505static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DMA(i0); } 506#define MDP4_DMA_CURSOR_SIZE_WIDTH__MASK 0x0000007f 507#define MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT 0 508static inline uint32_t MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val) 509{ 510 return ((val) << MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT) & MDP4_DMA_CURSOR_SIZE_WIDTH__MASK; 511} 512#define MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK 0x007f0000 513#define MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT 16 514static inline uint32_t MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val) 515{ 516 return ((val) << MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT) & MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK; 517} 518 519static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) { return 0x00000048 + __offset_DMA(i0); } 520 521static inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) { return 0x0000004c + __offset_DMA(i0); } 522#define MDP4_DMA_CURSOR_POS_X__MASK 0x0000ffff 523#define MDP4_DMA_CURSOR_POS_X__SHIFT 0 524static inline uint32_t MDP4_DMA_CURSOR_POS_X(uint32_t val) 525{ 526 return ((val) << MDP4_DMA_CURSOR_POS_X__SHIFT) & MDP4_DMA_CURSOR_POS_X__MASK; 527} 528#define MDP4_DMA_CURSOR_POS_Y__MASK 0xffff0000 529#define MDP4_DMA_CURSOR_POS_Y__SHIFT 16 530static inline uint32_t MDP4_DMA_CURSOR_POS_Y(uint32_t val) 531{ 532 return ((val) << MDP4_DMA_CURSOR_POS_Y__SHIFT) & MDP4_DMA_CURSOR_POS_Y__MASK; 533} 534 535static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) { return 0x00000060 + __offset_DMA(i0); } 536#define MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN 0x00000001 537#define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK 0x00000006 538#define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT 1 539static inline uint32_t MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val) 540{ 541 return ((val) << MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT) & MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK; 542} 543#define MDP4_DMA_CURSOR_BLEND_CONFIG_TRANSP_EN 0x00000008 544 545static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) { return 0x00000064 + __offset_DMA(i0); } 546 547static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) { return 0x00000068 + __offset_DMA(i0); } 548 549static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) { return 0x0000006c + __offset_DMA(i0); } 550 551static inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) { return 0x00001004 + __offset_DMA(i0); } 552 553static inline uint32_t REG_MDP4_DMA_CSC(enum mdp4_dma i0) { return 0x00003000 + __offset_DMA(i0); } 554 555 556static inline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; } 557 558static inline uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; } 559 560static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; } 561 562static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; } 563 564static inline uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; } 565 566static inline uint32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; } 567 568static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; } 569 570static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; } 571 572static inline uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; } 573 574static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; } 575 576static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; } 577 578static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; } 579#define MDP4_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000 580#define MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT 16 581static inline uint32_t MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val) 582{ 583 return ((val) << MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SRC_SIZE_HEIGHT__MASK; 584} 585#define MDP4_PIPE_SRC_SIZE_WIDTH__MASK 0x0000ffff 586#define MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT 0 587static inline uint32_t MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val) 588{ 589 return ((val) << MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SRC_SIZE_WIDTH__MASK; 590} 591 592static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) { return 0x00020004 + 0x10000*i0; } 593#define MDP4_PIPE_SRC_XY_Y__MASK 0xffff0000 594#define MDP4_PIPE_SRC_XY_Y__SHIFT 16 595static inline uint32_t MDP4_PIPE_SRC_XY_Y(uint32_t val) 596{ 597 return ((val) << MDP4_PIPE_SRC_XY_Y__SHIFT) & MDP4_PIPE_SRC_XY_Y__MASK; 598} 599#define MDP4_PIPE_SRC_XY_X__MASK 0x0000ffff 600#define MDP4_PIPE_SRC_XY_X__SHIFT 0 601static inline uint32_t MDP4_PIPE_SRC_XY_X(uint32_t val) 602{ 603 return ((val) << MDP4_PIPE_SRC_XY_X__SHIFT) & MDP4_PIPE_SRC_XY_X__MASK; 604} 605 606static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) { return 0x00020008 + 0x10000*i0; } 607#define MDP4_PIPE_DST_SIZE_HEIGHT__MASK 0xffff0000 608#define MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT 16 609static inline uint32_t MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val) 610{ 611 return ((val) << MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_DST_SIZE_HEIGHT__MASK; 612} 613#define MDP4_PIPE_DST_SIZE_WIDTH__MASK 0x0000ffff 614#define MDP4_PIPE_DST_SIZE_WIDTH__SHIFT 0 615static inline uint32_t MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val) 616{ 617 return ((val) << MDP4_PIPE_DST_SIZE_WIDTH__SHIFT) & MDP4_PIPE_DST_SIZE_WIDTH__MASK; 618} 619 620static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) { return 0x0002000c + 0x10000*i0; } 621#define MDP4_PIPE_DST_XY_Y__MASK 0xffff0000 622#define MDP4_PIPE_DST_XY_Y__SHIFT 16 623static inline uint32_t MDP4_PIPE_DST_XY_Y(uint32_t val) 624{ 625 return ((val) << MDP4_PIPE_DST_XY_Y__SHIFT) & MDP4_PIPE_DST_XY_Y__MASK; 626} 627#define MDP4_PIPE_DST_XY_X__MASK 0x0000ffff 628#define MDP4_PIPE_DST_XY_X__SHIFT 0 629static inline uint32_t MDP4_PIPE_DST_XY_X(uint32_t val) 630{ 631 return ((val) << MDP4_PIPE_DST_XY_X__SHIFT) & MDP4_PIPE_DST_XY_X__MASK; 632} 633 634static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) { return 0x00020010 + 0x10000*i0; } 635 636static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { return 0x00020014 + 0x10000*i0; } 637 638static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 0x00020018 + 0x10000*i0; } 639 640static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 0x00020040 + 0x10000*i0; } 641#define MDP4_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff 642#define MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT 0 643static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val) 644{ 645 return ((val) << MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P0__MASK; 646} 647#define MDP4_PIPE_SRC_STRIDE_A_P1__MASK 0xffff0000 648#define MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT 16 649static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val) 650{ 651 return ((val) << MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P1__MASK; 652} 653 654static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) { return 0x00020044 + 0x10000*i0; } 655#define MDP4_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff 656#define MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT 0 657static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val) 658{ 659 return ((val) << MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P2__MASK; 660} 661#define MDP4_PIPE_SRC_STRIDE_B_P3__MASK 0xffff0000 662#define MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT 16 663static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val) 664{ 665 return ((val) << MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P3__MASK; 666} 667 668static inline uint32_t REG_MDP4_PIPE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x10000*i0; } 669#define MDP4_PIPE_FRAME_SIZE_HEIGHT__MASK 0xffff0000 670#define MDP4_PIPE_FRAME_SIZE_HEIGHT__SHIFT 16 671static inline uint32_t MDP4_PIPE_FRAME_SIZE_HEIGHT(uint32_t val) 672{ 673 return ((val) << MDP4_PIPE_FRAME_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_FRAME_SIZE_HEIGHT__MASK; 674} 675#define MDP4_PIPE_FRAME_SIZE_WIDTH__MASK 0x0000ffff 676#define MDP4_PIPE_FRAME_SIZE_WIDTH__SHIFT 0 677static inline uint32_t MDP4_PIPE_FRAME_SIZE_WIDTH(uint32_t val) 678{ 679 return ((val) << MDP4_PIPE_FRAME_SIZE_WIDTH__SHIFT) & MDP4_PIPE_FRAME_SIZE_WIDTH__MASK; 680} 681 682static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0; } 683#define MDP4_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003 684#define MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT 0 685static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val) 686{ 687 return ((val) << MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_G_BPC__MASK; 688} 689#define MDP4_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c 690#define MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT 2 691static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val) 692{ 693 return ((val) << MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_B_BPC__MASK; 694} 695#define MDP4_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030 696#define MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT 4 697static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val) 698{ 699 return ((val) << MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_R_BPC__MASK; 700} 701#define MDP4_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0 702#define MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT 6 703static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val) 704{ 705 return ((val) << MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_A_BPC__MASK; 706} 707#define MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE 0x00000100 708#define MDP4_PIPE_SRC_FORMAT_CPP__MASK 0x00000600 709#define MDP4_PIPE_SRC_FORMAT_CPP__SHIFT 9 710static inline uint32_t MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val) 711{ 712 return ((val) << MDP4_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CPP__MASK; 713} 714#define MDP4_PIPE_SRC_FORMAT_ROTATED_90 0x00001000 715#define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK 0x00006000 716#define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT 13 717static inline uint32_t MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val) 718{ 719 return ((val) << MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK; 720} 721#define MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000 722#define MDP4_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000 723#define MDP4_PIPE_SRC_FORMAT_SOLID_FILL 0x00400000 724 725static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 0x00020054 + 0x10000*i0; } 726#define MDP4_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff 727#define MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT 0 728static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val) 729{ 730 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM0__MASK; 731} 732#define MDP4_PIPE_SRC_UNPACK_ELEM1__MASK 0x0000ff00 733#define MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT 8 734static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val) 735{ 736 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM1__MASK; 737} 738#define MDP4_PIPE_SRC_UNPACK_ELEM2__MASK 0x00ff0000 739#define MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT 16 740static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val) 741{ 742 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM2__MASK; 743} 744#define MDP4_PIPE_SRC_UNPACK_ELEM3__MASK 0xff000000 745#define MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT 24 746static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val) 747{ 748 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM3__MASK; 749} 750 751static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 0x00020058 + 0x10000*i0; } 752#define MDP4_PIPE_OP_MODE_SCALEX_EN 0x00000001 753#define MDP4_PIPE_OP_MODE_SCALEY_EN 0x00000002 754#define MDP4_PIPE_OP_MODE_SRC_YCBCR 0x00000200 755#define MDP4_PIPE_OP_MODE_DST_YCBCR 0x00000400 756#define MDP4_PIPE_OP_MODE_CSC_EN 0x00000800 757#define MDP4_PIPE_OP_MODE_FLIP_LR 0x00002000 758#define MDP4_PIPE_OP_MODE_FLIP_UD 0x00004000 759#define MDP4_PIPE_OP_MODE_DITHER_EN 0x00008000 760#define MDP4_PIPE_OP_MODE_IGC_LUT_EN 0x00010000 761#define MDP4_PIPE_OP_MODE_DEINT_EN 0x00040000 762#define MDP4_PIPE_OP_MODE_DEINT_ODD_REF 0x00080000 763 764static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) { return 0x0002005c + 0x10000*i0; } 765 766static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) { return 0x00020060 + 0x10000*i0; } 767 768static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) { return 0x00021004 + 0x10000*i0; } 769 770static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) { return 0x00021008 + 0x10000*i0; } 771 772static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) { return 0x00024000 + 0x10000*i0; } 773 774 775static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; } 776 777static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; } 778 779static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; } 780 781static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; } 782 783static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; } 784 785static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; } 786 787static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; } 788 789static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; } 790 791static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; } 792 793static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; } 794 795#define REG_MDP4_LCDC 0x000c0000 796 797#define REG_MDP4_LCDC_ENABLE 0x000c0000 798 799#define REG_MDP4_LCDC_HSYNC_CTRL 0x000c0004 800#define MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK 0x0000ffff 801#define MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT 0 802static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val) 803{ 804 return ((val) << MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK; 805} 806#define MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK 0xffff0000 807#define MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT 16 808static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val) 809{ 810 return ((val) << MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK; 811} 812 813#define REG_MDP4_LCDC_VSYNC_PERIOD 0x000c0008 814 815#define REG_MDP4_LCDC_VSYNC_LEN 0x000c000c 816 817#define REG_MDP4_LCDC_DISPLAY_HCTRL 0x000c0010 818#define MDP4_LCDC_DISPLAY_HCTRL_START__MASK 0x0000ffff 819#define MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT 0 820static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val) 821{ 822 return ((val) << MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_START__MASK; 823} 824#define MDP4_LCDC_DISPLAY_HCTRL_END__MASK 0xffff0000 825#define MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT 16 826static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val) 827{ 828 return ((val) << MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_END__MASK; 829} 830 831#define REG_MDP4_LCDC_DISPLAY_VSTART 0x000c0014 832 833#define REG_MDP4_LCDC_DISPLAY_VEND 0x000c0018 834 835#define REG_MDP4_LCDC_ACTIVE_HCTL 0x000c001c 836#define MDP4_LCDC_ACTIVE_HCTL_START__MASK 0x00007fff 837#define MDP4_LCDC_ACTIVE_HCTL_START__SHIFT 0 838static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val) 839{ 840 return ((val) << MDP4_LCDC_ACTIVE_HCTL_START__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_START__MASK; 841} 842#define MDP4_LCDC_ACTIVE_HCTL_END__MASK 0x7fff0000 843#define MDP4_LCDC_ACTIVE_HCTL_END__SHIFT 16 844static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val) 845{ 846 return ((val) << MDP4_LCDC_ACTIVE_HCTL_END__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_END__MASK; 847} 848#define MDP4_LCDC_ACTIVE_HCTL_ACTIVE_START_X 0x80000000 849 850#define REG_MDP4_LCDC_ACTIVE_VSTART 0x000c0020 851 852#define REG_MDP4_LCDC_ACTIVE_VEND 0x000c0024 853 854#define REG_MDP4_LCDC_BORDER_CLR 0x000c0028 855 856#define REG_MDP4_LCDC_UNDERFLOW_CLR 0x000c002c 857#define MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff 858#define MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT 0 859static inline uint32_t MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val) 860{ 861 return ((val) << MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK; 862} 863#define MDP4_LCDC_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000 864 865#define REG_MDP4_LCDC_HSYNC_SKEW 0x000c0030 866 867#define REG_MDP4_LCDC_TEST_CNTL 0x000c0034 868 869#define REG_MDP4_LCDC_CTRL_POLARITY 0x000c0038 870#define MDP4_LCDC_CTRL_POLARITY_HSYNC_LOW 0x00000001 871#define MDP4_LCDC_CTRL_POLARITY_VSYNC_LOW 0x00000002 872#define MDP4_LCDC_CTRL_POLARITY_DATA_EN_LOW 0x00000004 873 874#define REG_MDP4_DTV 0x000d0000 875 876#define REG_MDP4_DTV_ENABLE 0x000d0000 877 878#define REG_MDP4_DTV_HSYNC_CTRL 0x000d0004 879#define MDP4_DTV_HSYNC_CTRL_PULSEW__MASK 0x0000ffff 880#define MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT 0 881static inline uint32_t MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val) 882{ 883 return ((val) << MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DTV_HSYNC_CTRL_PULSEW__MASK; 884} 885#define MDP4_DTV_HSYNC_CTRL_PERIOD__MASK 0xffff0000 886#define MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT 16 887static inline uint32_t MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val) 888{ 889 return ((val) << MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DTV_HSYNC_CTRL_PERIOD__MASK; 890} 891 892#define REG_MDP4_DTV_VSYNC_PERIOD 0x000d0008 893 894#define REG_MDP4_DTV_VSYNC_LEN 0x000d000c 895 896#define REG_MDP4_DTV_DISPLAY_HCTRL 0x000d0018 897#define MDP4_DTV_DISPLAY_HCTRL_START__MASK 0x0000ffff 898#define MDP4_DTV_DISPLAY_HCTRL_START__SHIFT 0 899static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val) 900{ 901 return ((val) << MDP4_DTV_DISPLAY_HCTRL_START__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_START__MASK; 902} 903#define MDP4_DTV_DISPLAY_HCTRL_END__MASK 0xffff0000 904#define MDP4_DTV_DISPLAY_HCTRL_END__SHIFT 16 905static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val) 906{ 907 return ((val) << MDP4_DTV_DISPLAY_HCTRL_END__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_END__MASK; 908} 909 910#define REG_MDP4_DTV_DISPLAY_VSTART 0x000d001c 911 912#define REG_MDP4_DTV_DISPLAY_VEND 0x000d0020 913 914#define REG_MDP4_DTV_ACTIVE_HCTL 0x000d002c 915#define MDP4_DTV_ACTIVE_HCTL_START__MASK 0x00007fff 916#define MDP4_DTV_ACTIVE_HCTL_START__SHIFT 0 917static inline uint32_t MDP4_DTV_ACTIVE_HCTL_START(uint32_t val) 918{ 919 return ((val) << MDP4_DTV_ACTIVE_HCTL_START__SHIFT) & MDP4_DTV_ACTIVE_HCTL_START__MASK; 920} 921#define MDP4_DTV_ACTIVE_HCTL_END__MASK 0x7fff0000 922#define MDP4_DTV_ACTIVE_HCTL_END__SHIFT 16 923static inline uint32_t MDP4_DTV_ACTIVE_HCTL_END(uint32_t val) 924{ 925 return ((val) << MDP4_DTV_ACTIVE_HCTL_END__SHIFT) & MDP4_DTV_ACTIVE_HCTL_END__MASK; 926} 927#define MDP4_DTV_ACTIVE_HCTL_ACTIVE_START_X 0x80000000 928 929#define REG_MDP4_DTV_ACTIVE_VSTART 0x000d0030 930 931#define REG_MDP4_DTV_ACTIVE_VEND 0x000d0038 932 933#define REG_MDP4_DTV_BORDER_CLR 0x000d0040 934 935#define REG_MDP4_DTV_UNDERFLOW_CLR 0x000d0044 936#define MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff 937#define MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT 0 938static inline uint32_t MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val) 939{ 940 return ((val) << MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK; 941} 942#define MDP4_DTV_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000 943 944#define REG_MDP4_DTV_HSYNC_SKEW 0x000d0048 945 946#define REG_MDP4_DTV_TEST_CNTL 0x000d004c 947 948#define REG_MDP4_DTV_CTRL_POLARITY 0x000d0050 949#define MDP4_DTV_CTRL_POLARITY_HSYNC_LOW 0x00000001 950#define MDP4_DTV_CTRL_POLARITY_VSYNC_LOW 0x00000002 951#define MDP4_DTV_CTRL_POLARITY_DATA_EN_LOW 0x00000004 952 953#define REG_MDP4_DSI 0x000e0000 954 955#define REG_MDP4_DSI_ENABLE 0x000e0000 956 957#define REG_MDP4_DSI_HSYNC_CTRL 0x000e0004 958#define MDP4_DSI_HSYNC_CTRL_PULSEW__MASK 0x0000ffff 959#define MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT 0 960static inline uint32_t MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val) 961{ 962 return ((val) << MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DSI_HSYNC_CTRL_PULSEW__MASK; 963} 964#define MDP4_DSI_HSYNC_CTRL_PERIOD__MASK 0xffff0000 965#define MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT 16 966static inline uint32_t MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val) 967{ 968 return ((val) << MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DSI_HSYNC_CTRL_PERIOD__MASK; 969} 970 971#define REG_MDP4_DSI_VSYNC_PERIOD 0x000e0008 972 973#define REG_MDP4_DSI_VSYNC_LEN 0x000e000c 974 975#define REG_MDP4_DSI_DISPLAY_HCTRL 0x000e0010 976#define MDP4_DSI_DISPLAY_HCTRL_START__MASK 0x0000ffff 977#define MDP4_DSI_DISPLAY_HCTRL_START__SHIFT 0 978static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val) 979{ 980 return ((val) << MDP4_DSI_DISPLAY_HCTRL_START__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_START__MASK; 981} 982#define MDP4_DSI_DISPLAY_HCTRL_END__MASK 0xffff0000 983#define MDP4_DSI_DISPLAY_HCTRL_END__SHIFT 16 984static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val) 985{ 986 return ((val) << MDP4_DSI_DISPLAY_HCTRL_END__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_END__MASK; 987} 988 989#define REG_MDP4_DSI_DISPLAY_VSTART 0x000e0014 990 991#define REG_MDP4_DSI_DISPLAY_VEND 0x000e0018 992 993#define REG_MDP4_DSI_ACTIVE_HCTL 0x000e001c 994#define MDP4_DSI_ACTIVE_HCTL_START__MASK 0x00007fff 995#define MDP4_DSI_ACTIVE_HCTL_START__SHIFT 0 996static inline uint32_t MDP4_DSI_ACTIVE_HCTL_START(uint32_t val) 997{ 998 return ((val) << MDP4_DSI_ACTIVE_HCTL_START__SHIFT) & MDP4_DSI_ACTIVE_HCTL_START__MASK; 999} 1000#define MDP4_DSI_ACTIVE_HCTL_END__MASK 0x7fff0000 1001#define MDP4_DSI_ACTIVE_HCTL_END__SHIFT 16 1002static inline uint32_t MDP4_DSI_ACTIVE_HCTL_END(uint32_t val) 1003{ 1004 return ((val) << MDP4_DSI_ACTIVE_HCTL_END__SHIFT) & MDP4_DSI_ACTIVE_HCTL_END__MASK; 1005} 1006#define MDP4_DSI_ACTIVE_HCTL_ACTIVE_START_X 0x80000000 1007 1008#define REG_MDP4_DSI_ACTIVE_VSTART 0x000e0020 1009 1010#define REG_MDP4_DSI_ACTIVE_VEND 0x000e0024 1011 1012#define REG_MDP4_DSI_BORDER_CLR 0x000e0028 1013 1014#define REG_MDP4_DSI_UNDERFLOW_CLR 0x000e002c 1015#define MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff 1016#define MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT 0 1017static inline uint32_t MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val) 1018{ 1019 return ((val) << MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK; 1020} 1021#define MDP4_DSI_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000 1022 1023#define REG_MDP4_DSI_HSYNC_SKEW 0x000e0030 1024 1025#define REG_MDP4_DSI_TEST_CNTL 0x000e0034 1026 1027#define REG_MDP4_DSI_CTRL_POLARITY 0x000e0038 1028#define MDP4_DSI_CTRL_POLARITY_HSYNC_LOW 0x00000001 1029#define MDP4_DSI_CTRL_POLARITY_VSYNC_LOW 0x00000002 1030#define MDP4_DSI_CTRL_POLARITY_DATA_EN_LOW 0x00000004 1031 1032 1033#endif /* MDP4_XML */ 1034