mdp4_kms.c revision d65bd0e431156f156f43946b6efb524694afb685
1/* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 19#include "msm_drv.h" 20#include "msm_mmu.h" 21#include "mdp4_kms.h" 22 23static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev); 24 25static int mdp4_hw_init(struct msm_kms *kms) 26{ 27 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); 28 struct drm_device *dev = mdp4_kms->dev; 29 uint32_t version, major, minor, dmap_cfg, vg_cfg; 30 unsigned long clk; 31 int ret = 0; 32 33 pm_runtime_get_sync(dev->dev); 34 35 mdp4_enable(mdp4_kms); 36 version = mdp4_read(mdp4_kms, REG_MDP4_VERSION); 37 mdp4_disable(mdp4_kms); 38 39 major = FIELD(version, MDP4_VERSION_MAJOR); 40 minor = FIELD(version, MDP4_VERSION_MINOR); 41 42 DBG("found MDP4 version v%d.%d", major, minor); 43 44 if (major != 4) { 45 dev_err(dev->dev, "unexpected MDP version: v%d.%d\n", 46 major, minor); 47 ret = -ENXIO; 48 goto out; 49 } 50 51 mdp4_kms->rev = minor; 52 53 if (mdp4_kms->dsi_pll_vdda) { 54 if ((mdp4_kms->rev == 2) || (mdp4_kms->rev == 4)) { 55 ret = regulator_set_voltage(mdp4_kms->dsi_pll_vdda, 56 1200000, 1200000); 57 if (ret) { 58 dev_err(dev->dev, 59 "failed to set dsi_pll_vdda voltage: %d\n", ret); 60 goto out; 61 } 62 } 63 } 64 65 if (mdp4_kms->dsi_pll_vddio) { 66 if (mdp4_kms->rev == 2) { 67 ret = regulator_set_voltage(mdp4_kms->dsi_pll_vddio, 68 1800000, 1800000); 69 if (ret) { 70 dev_err(dev->dev, 71 "failed to set dsi_pll_vddio voltage: %d\n", ret); 72 goto out; 73 } 74 } 75 } 76 77 if (mdp4_kms->rev > 1) { 78 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff); 79 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f); 80 } 81 82 mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3); 83 84 /* max read pending cmd config, 3 pending requests: */ 85 mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222); 86 87 clk = clk_get_rate(mdp4_kms->clk); 88 89 if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) { 90 dmap_cfg = 0x47; /* 16 bytes-burst x 8 req */ 91 vg_cfg = 0x47; /* 16 bytes-burs x 8 req */ 92 } else { 93 dmap_cfg = 0x27; /* 8 bytes-burst x 8 req */ 94 vg_cfg = 0x43; /* 16 bytes-burst x 4 req */ 95 } 96 97 DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg); 98 99 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg); 100 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg); 101 102 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg); 103 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg); 104 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg); 105 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg); 106 107 if (mdp4_kms->rev >= 2) 108 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1); 109 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0); 110 111 /* disable CSC matrix / YUV by default: */ 112 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0); 113 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0); 114 mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0); 115 mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0); 116 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0); 117 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0); 118 119 if (mdp4_kms->rev > 1) 120 mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1); 121 122out: 123 pm_runtime_put_sync(dev->dev); 124 125 return ret; 126} 127 128static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate, 129 struct drm_encoder *encoder) 130{ 131 /* if we had >1 encoder, we'd need something more clever: */ 132 return mdp4_dtv_round_pixclk(encoder, rate); 133} 134 135static void mdp4_preclose(struct msm_kms *kms, struct drm_file *file) 136{ 137 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); 138 struct msm_drm_private *priv = mdp4_kms->dev->dev_private; 139 unsigned i; 140 141 for (i = 0; i < priv->num_crtcs; i++) 142 mdp4_crtc_cancel_pending_flip(priv->crtcs[i], file); 143} 144 145static void mdp4_destroy(struct msm_kms *kms) 146{ 147 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); 148 if (mdp4_kms->blank_cursor_iova) 149 msm_gem_put_iova(mdp4_kms->blank_cursor_bo, mdp4_kms->id); 150 if (mdp4_kms->blank_cursor_bo) 151 drm_gem_object_unreference_unlocked(mdp4_kms->blank_cursor_bo); 152 kfree(mdp4_kms); 153} 154 155static const struct mdp_kms_funcs kms_funcs = { 156 .base = { 157 .hw_init = mdp4_hw_init, 158 .irq_preinstall = mdp4_irq_preinstall, 159 .irq_postinstall = mdp4_irq_postinstall, 160 .irq_uninstall = mdp4_irq_uninstall, 161 .irq = mdp4_irq, 162 .enable_vblank = mdp4_enable_vblank, 163 .disable_vblank = mdp4_disable_vblank, 164 .get_format = mdp_get_format, 165 .round_pixclk = mdp4_round_pixclk, 166 .preclose = mdp4_preclose, 167 .destroy = mdp4_destroy, 168 }, 169 .set_irqmask = mdp4_set_irqmask, 170}; 171 172int mdp4_disable(struct mdp4_kms *mdp4_kms) 173{ 174 DBG(""); 175 176 clk_disable_unprepare(mdp4_kms->clk); 177 if (mdp4_kms->pclk) 178 clk_disable_unprepare(mdp4_kms->pclk); 179 clk_disable_unprepare(mdp4_kms->lut_clk); 180 if (mdp4_kms->axi_clk) 181 clk_disable_unprepare(mdp4_kms->axi_clk); 182 183 return 0; 184} 185 186int mdp4_enable(struct mdp4_kms *mdp4_kms) 187{ 188 DBG(""); 189 190 clk_prepare_enable(mdp4_kms->clk); 191 if (mdp4_kms->pclk) 192 clk_prepare_enable(mdp4_kms->pclk); 193 clk_prepare_enable(mdp4_kms->lut_clk); 194 if (mdp4_kms->axi_clk) 195 clk_prepare_enable(mdp4_kms->axi_clk); 196 197 return 0; 198} 199 200static int modeset_init(struct mdp4_kms *mdp4_kms) 201{ 202 struct drm_device *dev = mdp4_kms->dev; 203 struct msm_drm_private *priv = dev->dev_private; 204 struct drm_plane *plane; 205 struct drm_crtc *crtc; 206 struct drm_encoder *encoder; 207 struct hdmi *hdmi; 208 int ret; 209 210 /* 211 * NOTE: this is a bit simplistic until we add support 212 * for more than just RGB1->DMA_E->DTV->HDMI 213 */ 214 215 /* construct non-private planes: */ 216 plane = mdp4_plane_init(dev, VG1, false); 217 if (IS_ERR(plane)) { 218 dev_err(dev->dev, "failed to construct plane for VG1\n"); 219 ret = PTR_ERR(plane); 220 goto fail; 221 } 222 priv->planes[priv->num_planes++] = plane; 223 224 plane = mdp4_plane_init(dev, VG2, false); 225 if (IS_ERR(plane)) { 226 dev_err(dev->dev, "failed to construct plane for VG2\n"); 227 ret = PTR_ERR(plane); 228 goto fail; 229 } 230 priv->planes[priv->num_planes++] = plane; 231 232 /* the CRTCs get constructed with a private plane: */ 233 plane = mdp4_plane_init(dev, RGB1, true); 234 if (IS_ERR(plane)) { 235 dev_err(dev->dev, "failed to construct plane for RGB1\n"); 236 ret = PTR_ERR(plane); 237 goto fail; 238 } 239 240 crtc = mdp4_crtc_init(dev, plane, priv->num_crtcs, 1, DMA_E); 241 if (IS_ERR(crtc)) { 242 dev_err(dev->dev, "failed to construct crtc for DMA_E\n"); 243 ret = PTR_ERR(crtc); 244 goto fail; 245 } 246 priv->crtcs[priv->num_crtcs++] = crtc; 247 248 encoder = mdp4_dtv_encoder_init(dev); 249 if (IS_ERR(encoder)) { 250 dev_err(dev->dev, "failed to construct DTV encoder\n"); 251 ret = PTR_ERR(encoder); 252 goto fail; 253 } 254 encoder->possible_crtcs = 0x1; /* DTV can be hooked to DMA_E */ 255 priv->encoders[priv->num_encoders++] = encoder; 256 257 hdmi = hdmi_init(dev, encoder); 258 if (IS_ERR(hdmi)) { 259 ret = PTR_ERR(hdmi); 260 dev_err(dev->dev, "failed to initialize HDMI: %d\n", ret); 261 goto fail; 262 } 263 264 return 0; 265 266fail: 267 return ret; 268} 269 270static const char *iommu_ports[] = { 271 "mdp_port0_cb0", "mdp_port1_cb0", 272}; 273 274struct msm_kms *mdp4_kms_init(struct drm_device *dev) 275{ 276 struct platform_device *pdev = dev->platformdev; 277 struct mdp4_platform_config *config = mdp4_get_config(pdev); 278 struct mdp4_kms *mdp4_kms; 279 struct msm_kms *kms = NULL; 280 struct msm_mmu *mmu; 281 int ret; 282 283 mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL); 284 if (!mdp4_kms) { 285 dev_err(dev->dev, "failed to allocate kms\n"); 286 ret = -ENOMEM; 287 goto fail; 288 } 289 290 mdp_kms_init(&mdp4_kms->base, &kms_funcs); 291 292 kms = &mdp4_kms->base.base; 293 294 mdp4_kms->dev = dev; 295 296 mdp4_kms->mmio = msm_ioremap(pdev, NULL, "MDP4"); 297 if (IS_ERR(mdp4_kms->mmio)) { 298 ret = PTR_ERR(mdp4_kms->mmio); 299 goto fail; 300 } 301 302 mdp4_kms->dsi_pll_vdda = 303 devm_regulator_get_optional(&pdev->dev, "dsi_pll_vdda"); 304 if (IS_ERR(mdp4_kms->dsi_pll_vdda)) 305 mdp4_kms->dsi_pll_vdda = NULL; 306 307 mdp4_kms->dsi_pll_vddio = 308 devm_regulator_get_optional(&pdev->dev, "dsi_pll_vddio"); 309 if (IS_ERR(mdp4_kms->dsi_pll_vddio)) 310 mdp4_kms->dsi_pll_vddio = NULL; 311 312 mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd"); 313 if (IS_ERR(mdp4_kms->vdd)) 314 mdp4_kms->vdd = NULL; 315 316 if (mdp4_kms->vdd) { 317 ret = regulator_enable(mdp4_kms->vdd); 318 if (ret) { 319 dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret); 320 goto fail; 321 } 322 } 323 324 mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk"); 325 if (IS_ERR(mdp4_kms->clk)) { 326 dev_err(dev->dev, "failed to get core_clk\n"); 327 ret = PTR_ERR(mdp4_kms->clk); 328 goto fail; 329 } 330 331 mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk"); 332 if (IS_ERR(mdp4_kms->pclk)) 333 mdp4_kms->pclk = NULL; 334 335 // XXX if (rev >= MDP_REV_42) { ??? 336 mdp4_kms->lut_clk = devm_clk_get(&pdev->dev, "lut_clk"); 337 if (IS_ERR(mdp4_kms->lut_clk)) { 338 dev_err(dev->dev, "failed to get lut_clk\n"); 339 ret = PTR_ERR(mdp4_kms->lut_clk); 340 goto fail; 341 } 342 343 mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "mdp_axi_clk"); 344 if (IS_ERR(mdp4_kms->axi_clk)) { 345 dev_err(dev->dev, "failed to get axi_clk\n"); 346 ret = PTR_ERR(mdp4_kms->axi_clk); 347 goto fail; 348 } 349 350 clk_set_rate(mdp4_kms->clk, config->max_clk); 351 clk_set_rate(mdp4_kms->lut_clk, config->max_clk); 352 353 /* make sure things are off before attaching iommu (bootloader could 354 * have left things on, in which case we'll start getting faults if 355 * we don't disable): 356 */ 357 mdp4_enable(mdp4_kms); 358 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0); 359 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0); 360 mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0); 361 mdp4_disable(mdp4_kms); 362 mdelay(16); 363 364 if (config->iommu) { 365 mmu = msm_iommu_new(&pdev->dev, config->iommu); 366 if (IS_ERR(mmu)) { 367 ret = PTR_ERR(mmu); 368 goto fail; 369 } 370 ret = mmu->funcs->attach(mmu, iommu_ports, 371 ARRAY_SIZE(iommu_ports)); 372 if (ret) 373 goto fail; 374 } else { 375 dev_info(dev->dev, "no iommu, fallback to phys " 376 "contig buffers for scanout\n"); 377 mmu = NULL; 378 } 379 380 mdp4_kms->id = msm_register_mmu(dev, mmu); 381 if (mdp4_kms->id < 0) { 382 ret = mdp4_kms->id; 383 dev_err(dev->dev, "failed to register mdp4 iommu: %d\n", ret); 384 goto fail; 385 } 386 387 ret = modeset_init(mdp4_kms); 388 if (ret) { 389 dev_err(dev->dev, "modeset_init failed: %d\n", ret); 390 goto fail; 391 } 392 393 mutex_lock(&dev->struct_mutex); 394 mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC); 395 mutex_unlock(&dev->struct_mutex); 396 if (IS_ERR(mdp4_kms->blank_cursor_bo)) { 397 ret = PTR_ERR(mdp4_kms->blank_cursor_bo); 398 dev_err(dev->dev, "could not allocate blank-cursor bo: %d\n", ret); 399 mdp4_kms->blank_cursor_bo = NULL; 400 goto fail; 401 } 402 403 ret = msm_gem_get_iova(mdp4_kms->blank_cursor_bo, mdp4_kms->id, 404 &mdp4_kms->blank_cursor_iova); 405 if (ret) { 406 dev_err(dev->dev, "could not pin blank-cursor bo: %d\n", ret); 407 goto fail; 408 } 409 410 return kms; 411 412fail: 413 if (kms) 414 mdp4_destroy(kms); 415 return ERR_PTR(ret); 416} 417 418static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev) 419{ 420 static struct mdp4_platform_config config = {}; 421#ifdef CONFIG_OF 422 /* TODO */ 423 config.max_clk = 266667000; 424 config.iommu = iommu_domain_alloc(&platform_bus_type); 425#else 426 if (cpu_is_apq8064()) 427 config.max_clk = 266667000; 428 else 429 config.max_clk = 200000000; 430 431 config.iommu = msm_get_iommu_domain(DISPLAY_READ_DOMAIN); 432#endif 433 return &config; 434} 435