nv04.c revision cb75d97e9c77743ecfcc43375be135a55a4d9b25
1/* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 25#include <subdev/device.h> 26#include <subdev/bios.h> 27#include <subdev/i2c.h> 28#include <subdev/clock.h> 29#include <subdev/devinit.h> 30 31int 32nv04_identify(struct nouveau_device *device) 33{ 34 switch (device->chipset) { 35 case 0x04: 36 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 37 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 38 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 39 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv04_devinit_oclass; 40 break; 41 case 0x05: 42 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 43 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 44 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 45 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv05_devinit_oclass; 46 break; 47 default: 48 nv_fatal(device, "unknown RIVA chipset\n"); 49 return -EINVAL; 50 } 51 52 return 0; 53} 54