nve0.c revision f49e7259a4ea3a9ac42fc1c70c86d5e50e800731 
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <subdev/bios.h>
26#include <subdev/bus.h>
27#include <subdev/gpio.h>
28#include <subdev/i2c.h>
29#include <subdev/clock.h>
30#include <subdev/therm.h>
31#include <subdev/mxm.h>
32#include <subdev/devinit.h>
33#include <subdev/mc.h>
34#include <subdev/timer.h>
35#include <subdev/fb.h>
36#include <subdev/ltcg.h>
37#include <subdev/ibus.h>
38#include <subdev/instmem.h>
39#include <subdev/vm.h>
40#include <subdev/bar.h>
41
42#include <engine/device.h>
43#include <engine/dmaobj.h>
44#include <engine/fifo.h>
45#include <engine/software.h>
46#include <engine/graph.h>
47#include <engine/disp.h>
48#include <engine/copy.h>
49#include <engine/bsp.h>
50#include <engine/vp.h>
51#include <engine/ppp.h>
52
53int
54nve0_identify(struct nouveau_device *device)
55{
56	switch (device->chipset) {
57	case 0xe4:
58		device->cname = "GK104";
59		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
60		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nve0_gpio_oclass;
61		device->oclass[NVDEV_SUBDEV_I2C    ] = &nvd0_i2c_oclass;
62		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
63		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
64		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
65		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
66		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
67		device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
68		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
69		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
70		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
71		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
72		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
73		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
74		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
75		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
76		device->oclass[NVDEV_ENGINE_FIFO   ] = &nve0_fifo_oclass;
77		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
78		device->oclass[NVDEV_ENGINE_GR     ] = &nve0_graph_oclass;
79		device->oclass[NVDEV_ENGINE_DISP   ] = &nve0_disp_oclass;
80		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
81		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
82		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
83		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
84		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
85		break;
86	case 0xe7:
87		device->cname = "GK107";
88		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
89		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nve0_gpio_oclass;
90		device->oclass[NVDEV_SUBDEV_I2C    ] = &nvd0_i2c_oclass;
91		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
92		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
93		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
94		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
95		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
96		device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
97		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
98		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
99		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
100		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
101		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
102		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
103		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
104		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
105		device->oclass[NVDEV_ENGINE_FIFO   ] = &nve0_fifo_oclass;
106		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
107		device->oclass[NVDEV_ENGINE_GR     ] = &nve0_graph_oclass;
108		device->oclass[NVDEV_ENGINE_DISP   ] = &nve0_disp_oclass;
109		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
110		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
111		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
112		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
113		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
114		break;
115	case 0xe6:
116		device->cname = "GK106";
117		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
118		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nve0_gpio_oclass;
119		device->oclass[NVDEV_SUBDEV_I2C    ] = &nvd0_i2c_oclass;
120		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
121		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
122		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
123		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
124		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
125		device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
126		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
127		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
128		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
129		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
130		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
131		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
132		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
133		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
134		device->oclass[NVDEV_ENGINE_FIFO   ] = &nve0_fifo_oclass;
135		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
136		device->oclass[NVDEV_ENGINE_GR     ] = &nve0_graph_oclass;
137		device->oclass[NVDEV_ENGINE_DISP   ] = &nve0_disp_oclass;
138		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
139		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
140		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
141		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
142		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
143		break;
144	case 0xf0:
145		device->cname = "GK110";
146		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
147		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nve0_gpio_oclass;
148		device->oclass[NVDEV_SUBDEV_I2C    ] = &nvd0_i2c_oclass;
149		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
150		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
151		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
152		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
153		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
154		device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
155		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
156		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
157		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
158		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
159		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
160		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
161		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
162		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
163#if 0
164		device->oclass[NVDEV_ENGINE_FIFO   ] = &nve0_fifo_oclass;
165		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
166		device->oclass[NVDEV_ENGINE_GR     ] = &nve0_graph_oclass;
167#endif
168		device->oclass[NVDEV_ENGINE_DISP   ] = &nvf0_disp_oclass;
169#if 0
170		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
171		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
172		device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
173		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
174		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
175		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
176#endif
177		break;
178	default:
179		nv_fatal(device, "unknown Kepler chipset\n");
180		return -EINVAL;
181	}
182
183	return 0;
184}
185