nv94.c revision a3761fa2483f48d158234760d5e25e5071e41537 
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <engine/software.h>
26#include <engine/disp.h>
27
28#include <core/class.h>
29
30#include "nv50.h"
31
32/*******************************************************************************
33 * EVO master channel object
34 ******************************************************************************/
35
36const struct nv50_disp_mthd_list
37nv94_disp_mast_mthd_sor = {
38	.mthd = 0x0040,
39	.addr = 0x000008,
40	.data = {
41		{ 0x0600, 0x610794 },
42		{}
43	}
44};
45
46const struct nv50_disp_mthd_chan
47nv94_disp_mast_mthd_chan = {
48	.name = "Core",
49	.addr = 0x000000,
50	.data = {
51		{ "Global", 1, &nv50_disp_mast_mthd_base },
52		{    "DAC", 3, &nv84_disp_mast_mthd_dac  },
53		{    "SOR", 4, &nv94_disp_mast_mthd_sor  },
54		{   "PIOR", 3, &nv50_disp_mast_mthd_pior },
55		{   "HEAD", 2, &nv84_disp_mast_mthd_head },
56		{}
57	}
58};
59
60/*******************************************************************************
61 * Base display object
62 ******************************************************************************/
63
64static struct nouveau_oclass
65nv94_disp_sclass[] = {
66	{ NV94_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs.base },
67	{ NV94_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs.base },
68	{ NV94_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs.base },
69	{ NV94_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs.base },
70	{ NV94_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs.base },
71	{}
72};
73
74static struct nouveau_omthds
75nv94_disp_base_omthds[] = {
76	{ HEAD_MTHD(NV50_DISP_SCANOUTPOS)     , nv50_disp_base_scanoutpos },
77	{ SOR_MTHD(NV94_DISP_SOR_DP_PWR)      , nv50_sor_mthd },
78	{ PIOR_MTHD(NV50_DISP_PIOR_PWR)       , nv50_pior_mthd },
79	{ PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR)  , nv50_pior_mthd },
80	{ PIOR_MTHD(NV50_DISP_PIOR_DP_PWR)    , nv50_pior_mthd },
81	{},
82};
83
84static struct nouveau_oclass
85nv94_disp_base_oclass[] = {
86	{ NV94_DISP_CLASS, &nv50_disp_base_ofuncs, nv94_disp_base_omthds },
87	{}
88};
89
90/*******************************************************************************
91 * Display engine implementation
92 ******************************************************************************/
93
94static int
95nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
96	       struct nouveau_oclass *oclass, void *data, u32 size,
97	       struct nouveau_object **pobject)
98{
99	struct nv50_disp_priv *priv;
100	int ret;
101
102	ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
103				  "display", &priv);
104	*pobject = nv_object(priv);
105	if (ret)
106		return ret;
107
108	nv_engine(priv)->sclass = nv94_disp_base_oclass;
109	nv_engine(priv)->cclass = &nv50_disp_cclass;
110	nv_subdev(priv)->intr = nv50_disp_intr;
111	INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
112	priv->sclass = nv94_disp_sclass;
113	priv->head.nr = 2;
114	priv->dac.nr = 3;
115	priv->sor.nr = 4;
116	priv->pior.nr = 3;
117	priv->dac.power = nv50_dac_power;
118	priv->dac.sense = nv50_dac_sense;
119	priv->sor.power = nv50_sor_power;
120	priv->sor.hdmi = nv84_hdmi_ctrl;
121	priv->pior.power = nv50_pior_power;
122	return 0;
123}
124
125struct nouveau_oclass *
126nv94_disp_outp_sclass[] = {
127	&nv50_pior_dp_impl.base.base,
128	&nv94_sor_dp_impl.base.base,
129	NULL
130};
131
132struct nouveau_oclass *
133nv94_disp_oclass = &(struct nv50_disp_impl) {
134	.base.base.handle = NV_ENGINE(DISP, 0x88),
135	.base.base.ofuncs = &(struct nouveau_ofuncs) {
136		.ctor = nv94_disp_ctor,
137		.dtor = _nouveau_disp_dtor,
138		.init = _nouveau_disp_init,
139		.fini = _nouveau_disp_fini,
140	},
141	.base.vblank = &nv50_disp_vblank_func,
142	.base.outp =  nv94_disp_outp_sclass,
143	.mthd.core = &nv94_disp_mast_mthd_chan,
144	.mthd.base = &nv84_disp_sync_mthd_chan,
145	.mthd.ovly = &nv84_disp_ovly_mthd_chan,
146	.mthd.prev = 0x000004,
147}.base.base;
148