nv94.c revision ef22c8bb7b3fac45919b7fde412d36d1a8367d51 
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <engine/software.h>
26#include <engine/disp.h>
27
28#include <core/class.h>
29
30#include "nv50.h"
31
32static struct nouveau_oclass
33nv94_disp_sclass[] = {
34	{ NV94_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs },
35	{ NV94_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs },
36	{ NV94_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs },
37	{ NV94_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs },
38	{ NV94_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs },
39	{}
40};
41
42static struct nouveau_omthds
43nv94_disp_base_omthds[] = {
44	{ SOR_MTHD(NV50_DISP_SOR_PWR)         , nv50_sor_mthd },
45	{ SOR_MTHD(NV84_DISP_SOR_HDMI_PWR)    , nv50_sor_mthd },
46	{ SOR_MTHD(NV94_DISP_SOR_DP_TRAIN)    , nv50_sor_mthd },
47	{ SOR_MTHD(NV94_DISP_SOR_DP_LNKCTL)   , nv50_sor_mthd },
48	{ SOR_MTHD(NV94_DISP_SOR_DP_DRVCTL(0)), nv50_sor_mthd },
49	{ SOR_MTHD(NV94_DISP_SOR_DP_DRVCTL(1)), nv50_sor_mthd },
50	{ SOR_MTHD(NV94_DISP_SOR_DP_DRVCTL(2)), nv50_sor_mthd },
51	{ SOR_MTHD(NV94_DISP_SOR_DP_DRVCTL(3)), nv50_sor_mthd },
52	{ DAC_MTHD(NV50_DISP_DAC_PWR)         , nv50_dac_mthd },
53	{ DAC_MTHD(NV50_DISP_DAC_LOAD)        , nv50_dac_mthd },
54	{},
55};
56
57static struct nouveau_oclass
58nv94_disp_base_oclass[] = {
59	{ NV94_DISP_CLASS, &nv50_disp_base_ofuncs, nv94_disp_base_omthds },
60	{}
61};
62
63static int
64nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
65	       struct nouveau_oclass *oclass, void *data, u32 size,
66	       struct nouveau_object **pobject)
67{
68	struct nv50_disp_priv *priv;
69	int ret;
70
71	ret = nouveau_disp_create(parent, engine, oclass, "PDISP",
72				  "display", &priv);
73	*pobject = nv_object(priv);
74	if (ret)
75		return ret;
76
77	nv_engine(priv)->sclass = nv94_disp_base_oclass;
78	nv_engine(priv)->cclass = &nv50_disp_cclass;
79	nv_subdev(priv)->intr = nv50_disp_intr;
80	priv->sclass = nv94_disp_sclass;
81	priv->head.nr = 2;
82	priv->dac.nr = 3;
83	priv->sor.nr = 4;
84	priv->dac.power = nv50_dac_power;
85	priv->sor.power = nv50_sor_power;
86
87	INIT_LIST_HEAD(&priv->base.vblank.list);
88	spin_lock_init(&priv->base.vblank.lock);
89	return 0;
90}
91
92struct nouveau_oclass
93nv94_disp_oclass = {
94	.handle = NV_ENGINE(DISP, 0x88),
95	.ofuncs = &(struct nouveau_ofuncs) {
96		.ctor = nv94_disp_ctor,
97		.dtor = _nouveau_disp_dtor,
98		.init = _nouveau_disp_init,
99		.fini = _nouveau_disp_fini,
100	},
101};
102