ctxnvf0.c revision 0085a60524aeb743c15bbdf7354f4e4f6623243e
1/* 2 * Copyright 2013 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs <bskeggs@redhat.com> 23 */ 24 25#include "nvc0.h" 26 27static struct nvc0_graph_init 28nvf0_grctx_init_unk40xx[] = { 29 { 0x404004, 8, 0x04, 0x00000000 }, 30 { 0x404024, 1, 0x04, 0x0000e000 }, 31 { 0x404028, 8, 0x04, 0x00000000 }, 32 { 0x4040a8, 8, 0x04, 0x00000000 }, 33 { 0x4040c8, 1, 0x04, 0xf800008f }, 34 { 0x4040d0, 6, 0x04, 0x00000000 }, 35 { 0x4040e8, 1, 0x04, 0x00001000 }, 36 { 0x4040f8, 1, 0x04, 0x00000000 }, 37 { 0x404100, 10, 0x04, 0x00000000 }, 38 { 0x404130, 2, 0x04, 0x00000000 }, 39 { 0x404138, 1, 0x04, 0x20000040 }, 40 { 0x404150, 1, 0x04, 0x0000002e }, 41 { 0x404154, 1, 0x04, 0x00000400 }, 42 { 0x404158, 1, 0x04, 0x00000200 }, 43 { 0x404164, 1, 0x04, 0x00000055 }, 44 { 0x40417c, 2, 0x04, 0x00000000 }, 45 { 0x4041a0, 4, 0x04, 0x00000000 }, 46 { 0x404200, 1, 0x04, 0x0000a197 }, 47 { 0x404204, 1, 0x04, 0x0000a1c0 }, 48 { 0x404208, 1, 0x04, 0x0000a140 }, 49 { 0x40420c, 1, 0x04, 0x0000902d }, 50 {} 51}; 52 53static struct nvc0_graph_init 54nvf0_grctx_init_unk44xx[] = { 55 { 0x404404, 12, 0x04, 0x00000000 }, 56 { 0x404438, 1, 0x04, 0x00000000 }, 57 { 0x404460, 2, 0x04, 0x00000000 }, 58 { 0x404468, 1, 0x04, 0x00ffffff }, 59 { 0x40446c, 1, 0x04, 0x00000000 }, 60 { 0x404480, 1, 0x04, 0x00000001 }, 61 { 0x404498, 1, 0x04, 0x00000001 }, 62 {} 63}; 64 65static struct nvc0_graph_init 66nvf0_grctx_init_unk5bxx[] = { 67 { 0x405b00, 1, 0x04, 0x00000000 }, 68 { 0x405b10, 1, 0x04, 0x00001000 }, 69 { 0x405b20, 1, 0x04, 0x04000000 }, 70 {} 71}; 72 73static struct nvc0_graph_init 74nvf0_grctx_init_unk60xx[] = { 75 { 0x406020, 1, 0x04, 0x034103c1 }, 76 { 0x406028, 4, 0x04, 0x00000001 }, 77 {} 78}; 79 80static struct nvc0_graph_init 81nvf0_grctx_init_unk64xx[] = { 82 { 0x4064a8, 1, 0x04, 0x00000000 }, 83 { 0x4064ac, 1, 0x04, 0x00003fff }, 84 { 0x4064b0, 3, 0x04, 0x00000000 }, 85 { 0x4064c0, 1, 0x04, 0x802000f0 }, 86 { 0x4064c4, 1, 0x04, 0x0192ffff }, 87 { 0x4064c8, 1, 0x04, 0x018007c0 }, 88 { 0x4064cc, 9, 0x04, 0x00000000 }, 89 { 0x4064fc, 1, 0x04, 0x0000022a }, 90 {} 91}; 92 93static struct nvc0_graph_init 94nvf0_grctx_init_unk88xx[] = { 95 { 0x408800, 1, 0x04, 0x12802a3c }, 96 { 0x408804, 1, 0x04, 0x00000040 }, 97 { 0x408808, 1, 0x04, 0x1003e005 }, 98 { 0x408840, 1, 0x04, 0x0000000b }, 99 { 0x408900, 1, 0x04, 0x3080b801 }, 100 { 0x408904, 1, 0x04, 0x62000001 }, 101 { 0x408908, 1, 0x04, 0x00c8102f }, 102 { 0x408980, 1, 0x04, 0x0000011d }, 103 {} 104}; 105 106static struct nvc0_graph_init 107nvf0_grctx_init_gpc_0[] = { 108 { 0x418380, 1, 0x04, 0x00000016 }, 109 { 0x418400, 1, 0x04, 0x38004e00 }, 110 { 0x418404, 1, 0x04, 0x71e0ffff }, 111 { 0x41840c, 1, 0x04, 0x00001008 }, 112 { 0x418410, 1, 0x04, 0x0fff0fff }, 113 { 0x418414, 1, 0x04, 0x02200fff }, 114 { 0x418450, 6, 0x04, 0x00000000 }, 115 { 0x418468, 1, 0x04, 0x00000001 }, 116 { 0x41846c, 2, 0x04, 0x00000000 }, 117 { 0x418600, 1, 0x04, 0x0000001f }, 118 { 0x418684, 1, 0x04, 0x0000000f }, 119 { 0x418700, 1, 0x04, 0x00000002 }, 120 { 0x418704, 1, 0x04, 0x00000080 }, 121 { 0x418708, 3, 0x04, 0x00000000 }, 122 { 0x418800, 1, 0x04, 0x7006860a }, 123 { 0x418808, 1, 0x04, 0x00000000 }, 124 { 0x41880c, 1, 0x04, 0x00000030 }, 125 { 0x418810, 1, 0x04, 0x00000000 }, 126 { 0x418828, 1, 0x04, 0x00000044 }, 127 { 0x418830, 1, 0x04, 0x10000001 }, 128 { 0x4188d8, 1, 0x04, 0x00000008 }, 129 { 0x4188e0, 1, 0x04, 0x01000000 }, 130 { 0x4188e8, 5, 0x04, 0x00000000 }, 131 { 0x4188fc, 1, 0x04, 0x20100018 }, 132 { 0x41891c, 1, 0x04, 0x00ff00ff }, 133 { 0x418924, 1, 0x04, 0x00000000 }, 134 { 0x418928, 1, 0x04, 0x00ffff00 }, 135 { 0x41892c, 1, 0x04, 0x0000ff00 }, 136 { 0x418b00, 1, 0x04, 0x00000006 }, 137 { 0x418b08, 1, 0x04, 0x0a418820 }, 138 { 0x418b0c, 1, 0x04, 0x062080e6 }, 139 { 0x418b10, 1, 0x04, 0x020398a4 }, 140 { 0x418b14, 1, 0x04, 0x0e629062 }, 141 { 0x418b18, 1, 0x04, 0x0a418820 }, 142 { 0x418b1c, 1, 0x04, 0x000000e6 }, 143 { 0x418bb8, 1, 0x04, 0x00000103 }, 144 { 0x418c08, 1, 0x04, 0x00000001 }, 145 { 0x418c10, 8, 0x04, 0x00000000 }, 146 { 0x418c40, 1, 0x04, 0xffffffff }, 147 { 0x418c6c, 1, 0x04, 0x00000001 }, 148 { 0x418c80, 1, 0x04, 0x20200004 }, 149 { 0x418c8c, 1, 0x04, 0x00000001 }, 150 { 0x418d24, 1, 0x04, 0x00000000 }, 151 { 0x419000, 1, 0x04, 0x00000780 }, 152 { 0x419004, 2, 0x04, 0x00000000 }, 153 { 0x419014, 1, 0x04, 0x00000004 }, 154 {} 155}; 156 157static struct nvc0_graph_init 158nvf0_grctx_init_tpc[] = { 159 { 0x419848, 1, 0x04, 0x00000000 }, 160 { 0x419864, 1, 0x04, 0x00000129 }, 161 { 0x419888, 1, 0x04, 0x00000000 }, 162 { 0x419a00, 1, 0x04, 0x000000f0 }, 163 { 0x419a04, 1, 0x04, 0x00000001 }, 164 { 0x419a08, 1, 0x04, 0x00000021 }, 165 { 0x419a0c, 1, 0x04, 0x00020000 }, 166 { 0x419a10, 1, 0x04, 0x00000000 }, 167 { 0x419a14, 1, 0x04, 0x00000200 }, 168 { 0x419a1c, 1, 0x04, 0x0000c000 }, 169 { 0x419a20, 1, 0x04, 0x00020800 }, 170 { 0x419a30, 1, 0x04, 0x00000001 }, 171 { 0x419ac4, 1, 0x04, 0x0037f440 }, 172 { 0x419c00, 1, 0x04, 0x0000001a }, 173 { 0x419c04, 1, 0x04, 0x80000006 }, 174 { 0x419c08, 1, 0x04, 0x00000002 }, 175 { 0x419c20, 1, 0x04, 0x00000000 }, 176 { 0x419c24, 1, 0x04, 0x00084210 }, 177 { 0x419c28, 1, 0x04, 0x3efbefbe }, 178 { 0x419ce8, 1, 0x04, 0x00000000 }, 179 { 0x419cf4, 1, 0x04, 0x00000203 }, 180 { 0x419e04, 1, 0x04, 0x00000000 }, 181 { 0x419e08, 1, 0x04, 0x0000001d }, 182 { 0x419e0c, 1, 0x04, 0x00000000 }, 183 { 0x419e10, 1, 0x04, 0x00001c02 }, 184 { 0x419e44, 1, 0x04, 0x0013eff2 }, 185 { 0x419e48, 1, 0x04, 0x00000000 }, 186 { 0x419e4c, 1, 0x04, 0x0000007f }, 187 { 0x419e50, 2, 0x04, 0x00000000 }, 188 { 0x419e58, 1, 0x04, 0x00000001 }, 189 { 0x419e5c, 3, 0x04, 0x00000000 }, 190 { 0x419e68, 1, 0x04, 0x00000002 }, 191 { 0x419e6c, 12, 0x04, 0x00000000 }, 192 { 0x419eac, 1, 0x04, 0x00001fcf }, 193 { 0x419eb0, 1, 0x04, 0x0db00da0 }, 194 { 0x419eb8, 1, 0x04, 0x00000000 }, 195 { 0x419ec8, 1, 0x04, 0x0001304f }, 196 { 0x419f30, 4, 0x04, 0x00000000 }, 197 { 0x419f40, 1, 0x04, 0x00000018 }, 198 { 0x419f44, 3, 0x04, 0x00000000 }, 199 { 0x419f58, 1, 0x04, 0x00000000 }, 200 { 0x419f70, 1, 0x04, 0x00007300 }, 201 { 0x419f78, 1, 0x04, 0x000000eb }, 202 { 0x419f7c, 1, 0x04, 0x00000404 }, 203 {} 204}; 205 206static struct nvc0_graph_init 207nvf0_grctx_init_unk[] = { 208 { 0x41be24, 1, 0x04, 0x00000006 }, 209 { 0x41bec0, 1, 0x04, 0x10000000 }, 210 { 0x41bec4, 1, 0x04, 0x00037f7f }, 211 { 0x41bee4, 1, 0x04, 0x00000000 }, 212 { 0x41bf00, 1, 0x04, 0x0a418820 }, 213 { 0x41bf04, 1, 0x04, 0x062080e6 }, 214 { 0x41bf08, 1, 0x04, 0x020398a4 }, 215 { 0x41bf0c, 1, 0x04, 0x0e629062 }, 216 { 0x41bf10, 1, 0x04, 0x0a418820 }, 217 { 0x41bf14, 1, 0x04, 0x000000e6 }, 218 { 0x41bfd0, 1, 0x04, 0x00900103 }, 219 { 0x41bfe0, 1, 0x04, 0x00400001 }, 220 { 0x41bfe4, 1, 0x04, 0x00000000 }, 221 {} 222}; 223 224static void 225nvf0_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) 226{ 227 u32 magic[GPC_MAX][4]; 228 u32 offset; 229 int gpc; 230 231 mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); 232 mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); 233 mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW); 234 mmio_list(0x40800c, 0x00000000, 8, 1); 235 mmio_list(0x408010, 0x80000000, 0, 0); 236 mmio_list(0x419004, 0x00000000, 8, 1); 237 mmio_list(0x419008, 0x00000000, 0, 0); 238 mmio_list(0x4064cc, 0x80000000, 0, 0); 239 mmio_list(0x408004, 0x00000000, 8, 0); 240 mmio_list(0x408008, 0x80000030, 0, 0); 241 mmio_list(0x418808, 0x00000000, 8, 0); 242 mmio_list(0x41880c, 0x80000030, 0, 0); 243 mmio_list(0x4064c8, 0x01800600, 0, 0); 244 mmio_list(0x418810, 0x80000000, 12, 2); 245 mmio_list(0x419848, 0x10000000, 12, 2); 246 247 mmio_list(0x405830, 0x02180648, 0, 0); 248 mmio_list(0x4064c4, 0x0192ffff, 0, 0); 249 250 for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) { 251 u16 magic0 = 0x0218 * (priv->tpc_nr[gpc] - 1); 252 u16 magic1 = 0x0648 * (priv->tpc_nr[gpc] - 1); 253 u16 magic2 = 0x0218; 254 u16 magic3 = 0x0648; 255 magic[gpc][0] = 0x10000000 | (magic0 << 16) | offset; 256 magic[gpc][1] = 0x00000000 | (magic1 << 16); 257 offset += 0x0324 * (priv->tpc_nr[gpc] - 1);; 258 magic[gpc][2] = 0x10000000 | (magic2 << 16) | offset; 259 magic[gpc][3] = 0x00000000 | (magic3 << 16); 260 offset += 0x0324; 261 } 262 263 for (gpc = 0; gpc < priv->gpc_nr; gpc++) { 264 mmio_list(GPC_UNIT(gpc, 0x30c0), magic[gpc][0], 0, 0); 265 mmio_list(GPC_UNIT(gpc, 0x30e4), magic[gpc][1] | offset, 0, 0); 266 offset += 0x07ff * (priv->tpc_nr[gpc] - 1); 267 mmio_list(GPC_UNIT(gpc, 0x32c0), magic[gpc][2], 0, 0); 268 mmio_list(GPC_UNIT(gpc, 0x32e4), magic[gpc][3] | offset, 0, 0); 269 offset += 0x07ff; 270 } 271 272 mmio_list(0x17e91c, 0x06060609, 0, 0); 273 mmio_list(0x17e920, 0x00090a05, 0, 0); 274} 275 276static struct nvc0_graph_init * 277nvf0_grctx_init_hub[] = { 278 nvc0_grctx_init_base, 279 nvf0_grctx_init_unk40xx, 280 nvf0_grctx_init_unk44xx, 281 nve4_grctx_init_unk46xx, 282 nve4_grctx_init_unk47xx, 283 nve4_grctx_init_unk58xx, 284 nvf0_grctx_init_unk5bxx, 285 nvf0_grctx_init_unk60xx, 286 nvf0_grctx_init_unk64xx, 287 nve4_grctx_init_unk80xx, 288 nvf0_grctx_init_unk88xx, 289 nvd9_grctx_init_rop, 290 NULL 291}; 292 293struct nvc0_graph_init * 294nvf0_grctx_init_gpc[] = { 295 nvf0_grctx_init_gpc_0, 296 nvc0_grctx_init_gpc_1, 297 nvf0_grctx_init_tpc, 298 nvf0_grctx_init_unk, 299 NULL 300}; 301 302static struct nvc0_graph_mthd 303nvf0_grctx_init_mthd[] = { 304 { 0xa197, nvc1_grctx_init_9097, }, 305 { 0x902d, nvc0_grctx_init_902d, }, 306 { 0x902d, nvc0_grctx_init_mthd_magic, }, 307 {} 308}; 309 310struct nouveau_oclass * 311nvf0_grctx_oclass = &(struct nvc0_grctx_oclass) { 312 .base.handle = NV_ENGCTX(GR, 0xf0), 313 .base.ofuncs = &(struct nouveau_ofuncs) { 314 .ctor = nvc0_graph_context_ctor, 315 .dtor = nvc0_graph_context_dtor, 316 .init = _nouveau_graph_context_init, 317 .fini = _nouveau_graph_context_fini, 318 .rd32 = _nouveau_graph_context_rd32, 319 .wr32 = _nouveau_graph_context_wr32, 320 }, 321 .main = nve4_grctx_generate_main, 322 .mods = nvf0_grctx_generate_mods, 323 .hub = nvf0_grctx_init_hub, 324 .gpc = nvf0_grctx_init_gpc, 325 .icmd = nvc0_grctx_init_icmd, 326 .mthd = nvf0_grctx_init_mthd, 327}.base; 328