1#ifndef __NVIF_CLASS_H__ 2#define __NVIF_CLASS_H__ 3 4/******************************************************************************* 5 * class identifiers 6 ******************************************************************************/ 7 8/* the below match nvidia-assigned (either in hw, or sw) class numbers */ 9#define NV_DEVICE 0x00000080 10 11#define NV_DMA_FROM_MEMORY 0x00000002 12#define NV_DMA_TO_MEMORY 0x00000003 13#define NV_DMA_IN_MEMORY 0x0000003d 14 15#define NV04_DISP 0x00000046 16 17#define NV03_CHANNEL_DMA 0x0000006b 18#define NV10_CHANNEL_DMA 0x0000006e 19#define NV17_CHANNEL_DMA 0x0000176e 20#define NV40_CHANNEL_DMA 0x0000406e 21#define NV50_CHANNEL_DMA 0x0000506e 22#define G82_CHANNEL_DMA 0x0000826e 23 24#define NV50_CHANNEL_GPFIFO 0x0000506f 25#define G82_CHANNEL_GPFIFO 0x0000826f 26#define FERMI_CHANNEL_GPFIFO 0x0000906f 27#define KEPLER_CHANNEL_GPFIFO_A 0x0000a06f 28 29#define NV50_DISP 0x00005070 30#define G82_DISP 0x00008270 31#define GT200_DISP 0x00008370 32#define GT214_DISP 0x00008570 33#define GT206_DISP 0x00008870 34#define GF110_DISP 0x00009070 35#define GK104_DISP 0x00009170 36#define GK110_DISP 0x00009270 37#define GM107_DISP 0x00009470 38 39#define NV50_DISP_CURSOR 0x0000507a 40#define G82_DISP_CURSOR 0x0000827a 41#define GT214_DISP_CURSOR 0x0000857a 42#define GF110_DISP_CURSOR 0x0000907a 43#define GK104_DISP_CURSOR 0x0000917a 44 45#define NV50_DISP_OVERLAY 0x0000507b 46#define G82_DISP_OVERLAY 0x0000827b 47#define GT214_DISP_OVERLAY 0x0000857b 48#define GF110_DISP_OVERLAY 0x0000907b 49#define GK104_DISP_OVERLAY 0x0000917b 50 51#define NV50_DISP_BASE_CHANNEL_DMA 0x0000507c 52#define G82_DISP_BASE_CHANNEL_DMA 0x0000827c 53#define GT200_DISP_BASE_CHANNEL_DMA 0x0000837c 54#define GT214_DISP_BASE_CHANNEL_DMA 0x0000857c 55#define GF110_DISP_BASE_CHANNEL_DMA 0x0000907c 56#define GK104_DISP_BASE_CHANNEL_DMA 0x0000917c 57#define GK110_DISP_BASE_CHANNEL_DMA 0x0000927c 58 59#define NV50_DISP_CORE_CHANNEL_DMA 0x0000507d 60#define G82_DISP_CORE_CHANNEL_DMA 0x0000827d 61#define GT200_DISP_CORE_CHANNEL_DMA 0x0000837d 62#define GT214_DISP_CORE_CHANNEL_DMA 0x0000857d 63#define GT206_DISP_CORE_CHANNEL_DMA 0x0000887d 64#define GF110_DISP_CORE_CHANNEL_DMA 0x0000907d 65#define GK104_DISP_CORE_CHANNEL_DMA 0x0000917d 66#define GK110_DISP_CORE_CHANNEL_DMA 0x0000927d 67#define GM107_DISP_CORE_CHANNEL_DMA 0x0000947d 68 69#define NV50_DISP_OVERLAY_CHANNEL_DMA 0x0000507e 70#define G82_DISP_OVERLAY_CHANNEL_DMA 0x0000827e 71#define GT200_DISP_OVERLAY_CHANNEL_DMA 0x0000837e 72#define GT214_DISP_OVERLAY_CHANNEL_DMA 0x0000857e 73#define GF110_DISP_OVERLAY_CONTROL_DMA 0x0000907e 74#define GK104_DISP_OVERLAY_CONTROL_DMA 0x0000917e 75 76#define FERMI_A 0x00009097 77#define FERMI_B 0x00009197 78#define FERMI_C 0x00009297 79 80#define KEPLER_A 0x0000a097 81#define KEPLER_B 0x0000a197 82#define KEPLER_C 0x0000a297 83 84#define MAXWELL_A 0x0000b097 85 86#define FERMI_COMPUTE_A 0x000090c0 87#define FERMI_COMPUTE_B 0x000091c0 88 89#define KEPLER_COMPUTE_A 0x0000a0c0 90#define KEPLER_COMPUTE_B 0x0000a1c0 91 92#define MAXWELL_COMPUTE_A 0x0000b0c0 93 94 95/******************************************************************************* 96 * client 97 ******************************************************************************/ 98 99#define NV_CLIENT_DEVLIST 0x00 100 101struct nv_client_devlist_v0 { 102 __u8 version; 103 __u8 count; 104 __u8 pad02[6]; 105 __u64 device[]; 106}; 107 108 109/******************************************************************************* 110 * device 111 ******************************************************************************/ 112 113struct nv_device_v0 { 114 __u8 version; 115 __u8 pad01[7]; 116 __u64 device; /* device identifier, ~0 for client default */ 117#define NV_DEVICE_V0_DISABLE_IDENTIFY 0x0000000000000001ULL 118#define NV_DEVICE_V0_DISABLE_MMIO 0x0000000000000002ULL 119#define NV_DEVICE_V0_DISABLE_VBIOS 0x0000000000000004ULL 120#define NV_DEVICE_V0_DISABLE_CORE 0x0000000000000008ULL 121#define NV_DEVICE_V0_DISABLE_DISP 0x0000000000010000ULL 122#define NV_DEVICE_V0_DISABLE_FIFO 0x0000000000020000ULL 123#define NV_DEVICE_V0_DISABLE_GRAPH 0x0000000100000000ULL 124#define NV_DEVICE_V0_DISABLE_MPEG 0x0000000200000000ULL 125#define NV_DEVICE_V0_DISABLE_ME 0x0000000400000000ULL 126#define NV_DEVICE_V0_DISABLE_VP 0x0000000800000000ULL 127#define NV_DEVICE_V0_DISABLE_CRYPT 0x0000001000000000ULL 128#define NV_DEVICE_V0_DISABLE_BSP 0x0000002000000000ULL 129#define NV_DEVICE_V0_DISABLE_PPP 0x0000004000000000ULL 130#define NV_DEVICE_V0_DISABLE_COPY0 0x0000008000000000ULL 131#define NV_DEVICE_V0_DISABLE_COPY1 0x0000010000000000ULL 132#define NV_DEVICE_V0_DISABLE_VIC 0x0000020000000000ULL 133#define NV_DEVICE_V0_DISABLE_VENC 0x0000040000000000ULL 134 __u64 disable; /* disable particular subsystems */ 135 __u64 debug0; /* as above, but *internal* ids, and *NOT* ABI */ 136}; 137 138#define NV_DEVICE_V0_INFO 0x00 139 140struct nv_device_info_v0 { 141 __u8 version; 142#define NV_DEVICE_INFO_V0_IGP 0x00 143#define NV_DEVICE_INFO_V0_PCI 0x01 144#define NV_DEVICE_INFO_V0_AGP 0x02 145#define NV_DEVICE_INFO_V0_PCIE 0x03 146#define NV_DEVICE_INFO_V0_SOC 0x04 147 __u8 platform; 148 __u16 chipset; /* from NV_PMC_BOOT_0 */ 149 __u8 revision; /* from NV_PMC_BOOT_0 */ 150#define NV_DEVICE_INFO_V0_TNT 0x01 151#define NV_DEVICE_INFO_V0_CELSIUS 0x02 152#define NV_DEVICE_INFO_V0_KELVIN 0x03 153#define NV_DEVICE_INFO_V0_RANKINE 0x04 154#define NV_DEVICE_INFO_V0_CURIE 0x05 155#define NV_DEVICE_INFO_V0_TESLA 0x06 156#define NV_DEVICE_INFO_V0_FERMI 0x07 157#define NV_DEVICE_INFO_V0_KEPLER 0x08 158#define NV_DEVICE_INFO_V0_MAXWELL 0x09 159 __u8 family; 160 __u8 pad06[2]; 161 __u64 ram_size; 162 __u64 ram_user; 163}; 164 165 166/******************************************************************************* 167 * context dma 168 ******************************************************************************/ 169 170struct nv_dma_v0 { 171 __u8 version; 172#define NV_DMA_V0_TARGET_VM 0x00 173#define NV_DMA_V0_TARGET_VRAM 0x01 174#define NV_DMA_V0_TARGET_PCI 0x02 175#define NV_DMA_V0_TARGET_PCI_US 0x03 176#define NV_DMA_V0_TARGET_AGP 0x04 177 __u8 target; 178#define NV_DMA_V0_ACCESS_VM 0x00 179#define NV_DMA_V0_ACCESS_RD 0x01 180#define NV_DMA_V0_ACCESS_WR 0x02 181#define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR) 182 __u8 access; 183 __u8 pad03[5]; 184 __u64 start; 185 __u64 limit; 186 /* ... chipset-specific class data */ 187}; 188 189struct nv50_dma_v0 { 190 __u8 version; 191#define NV50_DMA_V0_PRIV_VM 0x00 192#define NV50_DMA_V0_PRIV_US 0x01 193#define NV50_DMA_V0_PRIV__S 0x02 194 __u8 priv; 195#define NV50_DMA_V0_PART_VM 0x00 196#define NV50_DMA_V0_PART_256 0x01 197#define NV50_DMA_V0_PART_1KB 0x02 198 __u8 part; 199#define NV50_DMA_V0_COMP_NONE 0x00 200#define NV50_DMA_V0_COMP_1 0x01 201#define NV50_DMA_V0_COMP_2 0x02 202#define NV50_DMA_V0_COMP_VM 0x03 203 __u8 comp; 204#define NV50_DMA_V0_KIND_PITCH 0x00 205#define NV50_DMA_V0_KIND_VM 0x7f 206 __u8 kind; 207 __u8 pad05[3]; 208}; 209 210struct gf100_dma_v0 { 211 __u8 version; 212#define GF100_DMA_V0_PRIV_VM 0x00 213#define GF100_DMA_V0_PRIV_US 0x01 214#define GF100_DMA_V0_PRIV__S 0x02 215 __u8 priv; 216#define GF100_DMA_V0_KIND_PITCH 0x00 217#define GF100_DMA_V0_KIND_VM 0xff 218 __u8 kind; 219 __u8 pad03[5]; 220}; 221 222struct gf110_dma_v0 { 223 __u8 version; 224#define GF110_DMA_V0_PAGE_LP 0x00 225#define GF110_DMA_V0_PAGE_SP 0x01 226 __u8 page; 227#define GF110_DMA_V0_KIND_PITCH 0x00 228#define GF110_DMA_V0_KIND_VM 0xff 229 __u8 kind; 230 __u8 pad03[5]; 231}; 232 233 234/******************************************************************************* 235 * perfmon 236 ******************************************************************************/ 237 238struct nvif_perfctr_v0 { 239 __u8 version; 240 __u8 pad01[1]; 241 __u16 logic_op; 242 __u8 pad04[4]; 243 char name[4][64]; 244}; 245 246#define NVIF_PERFCTR_V0_QUERY 0x00 247#define NVIF_PERFCTR_V0_SAMPLE 0x01 248#define NVIF_PERFCTR_V0_READ 0x02 249 250struct nvif_perfctr_query_v0 { 251 __u8 version; 252 __u8 pad01[3]; 253 __u32 iter; 254 char name[64]; 255}; 256 257struct nvif_perfctr_sample { 258}; 259 260struct nvif_perfctr_read_v0 { 261 __u8 version; 262 __u8 pad01[7]; 263 __u32 ctr; 264 __u32 clk; 265}; 266 267 268/******************************************************************************* 269 * device control 270 ******************************************************************************/ 271 272#define NVIF_CONTROL_PSTATE_INFO 0x00 273#define NVIF_CONTROL_PSTATE_ATTR 0x01 274#define NVIF_CONTROL_PSTATE_USER 0x02 275 276struct nvif_control_pstate_info_v0 { 277 __u8 version; 278 __u8 count; /* out: number of power states */ 279#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE (-1) 280#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON (-2) 281 __s8 ustate_ac; /* out: target pstate index */ 282 __s8 ustate_dc; /* out: target pstate index */ 283 __s8 pwrsrc; /* out: current power source */ 284#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN (-1) 285#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON (-2) 286 __s8 pstate; /* out: current pstate index */ 287 __u8 pad06[2]; 288}; 289 290struct nvif_control_pstate_attr_v0 { 291 __u8 version; 292#define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT (-1) 293 __s8 state; /* in: index of pstate to query 294 * out: pstate identifier 295 */ 296 __u8 index; /* in: index of attribute to query 297 * out: index of next attribute, or 0 if no more 298 */ 299 __u8 pad03[5]; 300 __u32 min; 301 __u32 max; 302 char name[32]; 303 char unit[16]; 304}; 305 306struct nvif_control_pstate_user_v0 { 307 __u8 version; 308#define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN (-1) 309#define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON (-2) 310 __s8 ustate; /* in: pstate identifier */ 311 __s8 pwrsrc; /* in: target power source */ 312 __u8 pad03[5]; 313}; 314 315 316/******************************************************************************* 317 * DMA FIFO channels 318 ******************************************************************************/ 319 320struct nv03_channel_dma_v0 { 321 __u8 version; 322 __u8 chid; 323 __u8 pad02[2]; 324 __u32 pushbuf; 325 __u64 offset; 326}; 327 328#define G82_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 329 330/******************************************************************************* 331 * GPFIFO channels 332 ******************************************************************************/ 333 334struct nv50_channel_gpfifo_v0 { 335 __u8 version; 336 __u8 chid; 337 __u8 pad01[6]; 338 __u32 pushbuf; 339 __u32 ilength; 340 __u64 ioffset; 341}; 342 343struct kepler_channel_gpfifo_a_v0 { 344 __u8 version; 345#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01 346#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_VP 0x02 347#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_PPP 0x04 348#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_BSP 0x08 349#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10 350#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1 0x20 351#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC 0x40 352 __u8 engine; 353 __u16 chid; 354 __u8 pad04[4]; 355 __u32 pushbuf; 356 __u32 ilength; 357 __u64 ioffset; 358}; 359 360/******************************************************************************* 361 * legacy display 362 ******************************************************************************/ 363 364#define NV04_DISP_NTFY_VBLANK 0x00 365#define NV04_DISP_NTFY_CONN 0x01 366 367struct nv04_disp_mthd_v0 { 368 __u8 version; 369#define NV04_DISP_SCANOUTPOS 0x00 370 __u8 method; 371 __u8 head; 372 __u8 pad03[5]; 373}; 374 375struct nv04_disp_scanoutpos_v0 { 376 __u8 version; 377 __u8 pad01[7]; 378 __s64 time[2]; 379 __u16 vblanks; 380 __u16 vblanke; 381 __u16 vtotal; 382 __u16 vline; 383 __u16 hblanks; 384 __u16 hblanke; 385 __u16 htotal; 386 __u16 hline; 387}; 388 389/******************************************************************************* 390 * display 391 ******************************************************************************/ 392 393#define NV50_DISP_MTHD 0x00 394 395struct nv50_disp_mthd_v0 { 396 __u8 version; 397#define NV50_DISP_SCANOUTPOS 0x00 398 __u8 method; 399 __u8 head; 400 __u8 pad03[5]; 401}; 402 403struct nv50_disp_mthd_v1 { 404 __u8 version; 405#define NV50_DISP_MTHD_V1_DAC_PWR 0x10 406#define NV50_DISP_MTHD_V1_DAC_LOAD 0x11 407#define NV50_DISP_MTHD_V1_SOR_PWR 0x20 408#define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21 409#define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22 410#define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23 411#define NV50_DISP_MTHD_V1_SOR_DP_PWR 0x24 412#define NV50_DISP_MTHD_V1_PIOR_PWR 0x30 413 __u8 method; 414 __u16 hasht; 415 __u16 hashm; 416 __u8 pad06[2]; 417}; 418 419struct nv50_disp_dac_pwr_v0 { 420 __u8 version; 421 __u8 state; 422 __u8 data; 423 __u8 vsync; 424 __u8 hsync; 425 __u8 pad05[3]; 426}; 427 428struct nv50_disp_dac_load_v0 { 429 __u8 version; 430 __u8 load; 431 __u8 pad02[2]; 432 __u32 data; 433}; 434 435struct nv50_disp_sor_pwr_v0 { 436 __u8 version; 437 __u8 state; 438 __u8 pad02[6]; 439}; 440 441struct nv50_disp_sor_hda_eld_v0 { 442 __u8 version; 443 __u8 pad01[7]; 444 __u8 data[]; 445}; 446 447struct nv50_disp_sor_hdmi_pwr_v0 { 448 __u8 version; 449 __u8 state; 450 __u8 max_ac_packet; 451 __u8 rekey; 452 __u8 pad04[4]; 453}; 454 455struct nv50_disp_sor_lvds_script_v0 { 456 __u8 version; 457 __u8 pad01[1]; 458 __u16 script; 459 __u8 pad04[4]; 460}; 461 462struct nv50_disp_sor_dp_pwr_v0 { 463 __u8 version; 464 __u8 state; 465 __u8 pad02[6]; 466}; 467 468struct nv50_disp_pior_pwr_v0 { 469 __u8 version; 470 __u8 state; 471 __u8 type; 472 __u8 pad03[5]; 473}; 474 475/* core */ 476struct nv50_disp_core_channel_dma_v0 { 477 __u8 version; 478 __u8 pad01[3]; 479 __u32 pushbuf; 480}; 481 482#define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 483 484/* cursor immediate */ 485struct nv50_disp_cursor_v0 { 486 __u8 version; 487 __u8 head; 488 __u8 pad02[6]; 489}; 490 491#define NV50_DISP_CURSOR_V0_NTFY_UEVENT 0x00 492 493/* base */ 494struct nv50_disp_base_channel_dma_v0 { 495 __u8 version; 496 __u8 pad01[2]; 497 __u8 head; 498 __u32 pushbuf; 499}; 500 501#define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 502 503/* overlay */ 504struct nv50_disp_overlay_channel_dma_v0 { 505 __u8 version; 506 __u8 pad01[2]; 507 __u8 head; 508 __u32 pushbuf; 509}; 510 511#define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 512 513/* overlay immediate */ 514struct nv50_disp_overlay_v0 { 515 __u8 version; 516 __u8 head; 517 __u8 pad02[6]; 518}; 519 520#define NV50_DISP_OVERLAY_V0_NTFY_UEVENT 0x00 521 522/******************************************************************************* 523 * fermi 524 ******************************************************************************/ 525 526#define FERMI_A_ZBC_COLOR 0x00 527#define FERMI_A_ZBC_DEPTH 0x01 528 529struct fermi_a_zbc_color_v0 { 530 __u8 version; 531#define FERMI_A_ZBC_COLOR_V0_FMT_ZERO 0x01 532#define FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE 0x02 533#define FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32 0x04 534#define FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16 0x08 535#define FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16 0x0c 536#define FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16 0x10 537#define FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16 0x14 538#define FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16 0x16 539#define FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8 0x18 540#define FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8 0x1c 541#define FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10 0x20 542#define FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10 0x24 543#define FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8 0x28 544#define FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8 0x2c 545#define FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8 0x30 546#define FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8 0x34 547#define FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8 0x38 548#define FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10 0x3c 549#define FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11 0x40 550 __u8 format; 551 __u8 index; 552 __u8 pad03[5]; 553 __u32 ds[4]; 554 __u32 l2[4]; 555}; 556 557struct fermi_a_zbc_depth_v0 { 558 __u8 version; 559#define FERMI_A_ZBC_DEPTH_V0_FMT_FP32 0x01 560 __u8 format; 561 __u8 index; 562 __u8 pad03[5]; 563 __u32 ds; 564 __u32 l2; 565}; 566 567#endif 568