1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "nv04.h"
26
27const struct nouveau_mc_intr
28nv50_mc_intr[] = {
29	{ 0x04000000, NVDEV_ENGINE_DISP },  /* DISP before FIFO, so pageflip-timestamping works! */
30	{ 0x00000001, NVDEV_ENGINE_MPEG },
31	{ 0x00000100, NVDEV_ENGINE_FIFO },
32	{ 0x00001000, NVDEV_ENGINE_GR },
33	{ 0x00004000, NVDEV_ENGINE_CRYPT },	/* NV84- */
34	{ 0x00008000, NVDEV_ENGINE_BSP },	/* NV84- */
35	{ 0x00020000, NVDEV_ENGINE_VP },	/* NV84- */
36	{ 0x00100000, NVDEV_SUBDEV_TIMER },
37	{ 0x00200000, NVDEV_SUBDEV_GPIO },	/* PMGR->GPIO */
38	{ 0x00200000, NVDEV_SUBDEV_I2C }, 	/* PMGR->I2C/AUX */
39	{ 0x10000000, NVDEV_SUBDEV_BUS },
40	{ 0x80000000, NVDEV_ENGINE_SW },
41	{ 0x0002d101, NVDEV_SUBDEV_FB },
42	{},
43};
44
45static void
46nv50_mc_msi_rearm(struct nouveau_mc *pmc)
47{
48	struct nouveau_device *device = nv_device(pmc);
49	pci_write_config_byte(device->pdev, 0x68, 0xff);
50}
51
52int
53nv50_mc_init(struct nouveau_object *object)
54{
55	struct nv04_mc_priv *priv = (void *)object;
56	nv_wr32(priv, 0x000200, 0xffffffff); /* everything on */
57	return nouveau_mc_init(&priv->base);
58}
59
60struct nouveau_oclass *
61nv50_mc_oclass = &(struct nouveau_mc_oclass) {
62	.base.handle = NV_SUBDEV(MC, 0x50),
63	.base.ofuncs = &(struct nouveau_ofuncs) {
64		.ctor = nv04_mc_ctor,
65		.dtor = _nouveau_mc_dtor,
66		.init = nv50_mc_init,
67		.fini = _nouveau_mc_fini,
68	},
69	.intr = nv50_mc_intr,
70	.msi_rearm = nv50_mc_msi_rearm,
71}.base;
72