nouveau_bios.c revision 05a7c15d48ff53b054bc36fc8a2be8bc9b60d9e7
1/* 2 * Copyright 2005-2006 Erik Waling 3 * Copyright 2006 Stephane Marchesin 4 * Copyright 2007-2009 Stuart Bennett 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 25#include "drmP.h" 26#define NV_DEBUG_NOTRACE 27#include "nouveau_drv.h" 28#include "nouveau_hw.h" 29#include "nouveau_encoder.h" 30#include "nouveau_gpio.h" 31 32#include <linux/io-mapping.h> 33 34/* these defines are made up */ 35#define NV_CIO_CRE_44_HEADA 0x0 36#define NV_CIO_CRE_44_HEADB 0x3 37#define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */ 38 39#define EDID1_LEN 128 40 41#define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg) 42#define LOG_OLD_VALUE(x) 43 44struct init_exec { 45 bool execute; 46 bool repeat; 47}; 48 49static bool nv_cksum(const uint8_t *data, unsigned int length) 50{ 51 /* 52 * There's a few checksums in the BIOS, so here's a generic checking 53 * function. 54 */ 55 int i; 56 uint8_t sum = 0; 57 58 for (i = 0; i < length; i++) 59 sum += data[i]; 60 61 if (sum) 62 return true; 63 64 return false; 65} 66 67static int 68score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable) 69{ 70 if (!(data[0] == 0x55 && data[1] == 0xAA)) { 71 NV_TRACEWARN(dev, "... BIOS signature not found\n"); 72 return 0; 73 } 74 75 if (nv_cksum(data, data[2] * 512)) { 76 NV_TRACEWARN(dev, "... BIOS checksum invalid\n"); 77 /* if a ro image is somewhat bad, it's probably all rubbish */ 78 return writeable ? 2 : 1; 79 } else 80 NV_TRACE(dev, "... appears to be valid\n"); 81 82 return 3; 83} 84 85static void load_vbios_prom(struct drm_device *dev, uint8_t *data) 86{ 87 struct drm_nouveau_private *dev_priv = dev->dev_private; 88 uint32_t pci_nv_20, save_pci_nv_20; 89 int pcir_ptr; 90 int i; 91 92 if (dev_priv->card_type >= NV_50) 93 pci_nv_20 = 0x88050; 94 else 95 pci_nv_20 = NV_PBUS_PCI_NV_20; 96 97 /* enable ROM access */ 98 save_pci_nv_20 = nvReadMC(dev, pci_nv_20); 99 nvWriteMC(dev, pci_nv_20, 100 save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED); 101 102 /* bail if no rom signature */ 103 if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 || 104 nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa) 105 goto out; 106 107 /* additional check (see note below) - read PCI record header */ 108 pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) | 109 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8; 110 if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' || 111 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' || 112 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' || 113 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R') 114 goto out; 115 116 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a 117 * a good read may be obtained by waiting or re-reading (cargocult: 5x) 118 * each byte. we'll hope pramin has something usable instead 119 */ 120 for (i = 0; i < NV_PROM_SIZE; i++) 121 data[i] = nv_rd08(dev, NV_PROM_OFFSET + i); 122 123out: 124 /* disable ROM access */ 125 nvWriteMC(dev, pci_nv_20, 126 save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED); 127} 128 129static void load_vbios_pramin(struct drm_device *dev, uint8_t *data) 130{ 131 struct drm_nouveau_private *dev_priv = dev->dev_private; 132 uint32_t old_bar0_pramin = 0; 133 int i; 134 135 if (dev_priv->card_type >= NV_50) { 136 u64 addr = (u64)(nv_rd32(dev, 0x619f04) & 0xffffff00) << 8; 137 if (!addr) { 138 addr = (u64)nv_rd32(dev, 0x1700) << 16; 139 addr += 0xf0000; 140 } 141 142 old_bar0_pramin = nv_rd32(dev, 0x1700); 143 nv_wr32(dev, 0x1700, addr >> 16); 144 } 145 146 /* bail if no rom signature */ 147 if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 || 148 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa) 149 goto out; 150 151 for (i = 0; i < NV_PROM_SIZE; i++) 152 data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i); 153 154out: 155 if (dev_priv->card_type >= NV_50) 156 nv_wr32(dev, 0x1700, old_bar0_pramin); 157} 158 159static void load_vbios_pci(struct drm_device *dev, uint8_t *data) 160{ 161 void __iomem *rom = NULL; 162 size_t rom_len; 163 int ret; 164 165 ret = pci_enable_rom(dev->pdev); 166 if (ret) 167 return; 168 169 rom = pci_map_rom(dev->pdev, &rom_len); 170 if (!rom) 171 goto out; 172 memcpy_fromio(data, rom, rom_len); 173 pci_unmap_rom(dev->pdev, rom); 174 175out: 176 pci_disable_rom(dev->pdev); 177} 178 179static void load_vbios_acpi(struct drm_device *dev, uint8_t *data) 180{ 181 int i; 182 int ret; 183 int size = 64 * 1024; 184 185 if (!nouveau_acpi_rom_supported(dev->pdev)) 186 return; 187 188 for (i = 0; i < (size / ROM_BIOS_PAGE); i++) { 189 ret = nouveau_acpi_get_bios_chunk(data, 190 (i * ROM_BIOS_PAGE), 191 ROM_BIOS_PAGE); 192 if (ret <= 0) 193 break; 194 } 195 return; 196} 197 198struct methods { 199 const char desc[8]; 200 void (*loadbios)(struct drm_device *, uint8_t *); 201 const bool rw; 202}; 203 204static struct methods shadow_methods[] = { 205 { "PRAMIN", load_vbios_pramin, true }, 206 { "PROM", load_vbios_prom, false }, 207 { "ACPI", load_vbios_acpi, true }, 208 { "PCIROM", load_vbios_pci, true }, 209}; 210#define NUM_SHADOW_METHODS ARRAY_SIZE(shadow_methods) 211 212static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data) 213{ 214 struct methods *methods = shadow_methods; 215 int testscore = 3; 216 int scores[NUM_SHADOW_METHODS], i; 217 218 if (nouveau_vbios) { 219 for (i = 0; i < NUM_SHADOW_METHODS; i++) 220 if (!strcasecmp(nouveau_vbios, methods[i].desc)) 221 break; 222 223 if (i < NUM_SHADOW_METHODS) { 224 NV_INFO(dev, "Attempting to use BIOS image from %s\n", 225 methods[i].desc); 226 227 methods[i].loadbios(dev, data); 228 if (score_vbios(dev, data, methods[i].rw)) 229 return true; 230 } 231 232 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios); 233 } 234 235 for (i = 0; i < NUM_SHADOW_METHODS; i++) { 236 NV_TRACE(dev, "Attempting to load BIOS image from %s\n", 237 methods[i].desc); 238 data[0] = data[1] = 0; /* avoid reuse of previous image */ 239 methods[i].loadbios(dev, data); 240 scores[i] = score_vbios(dev, data, methods[i].rw); 241 if (scores[i] == testscore) 242 return true; 243 } 244 245 while (--testscore > 0) { 246 for (i = 0; i < NUM_SHADOW_METHODS; i++) { 247 if (scores[i] == testscore) { 248 NV_TRACE(dev, "Using BIOS image from %s\n", 249 methods[i].desc); 250 methods[i].loadbios(dev, data); 251 return true; 252 } 253 } 254 } 255 256 NV_ERROR(dev, "No valid BIOS image found\n"); 257 return false; 258} 259 260struct init_tbl_entry { 261 char *name; 262 uint8_t id; 263 /* Return: 264 * > 0: success, length of opcode 265 * 0: success, but abort further parsing of table (INIT_DONE etc) 266 * < 0: failure, table parsing will be aborted 267 */ 268 int (*handler)(struct nvbios *, uint16_t, struct init_exec *); 269}; 270 271static int parse_init_table(struct nvbios *, uint16_t, struct init_exec *); 272 273#define MACRO_INDEX_SIZE 2 274#define MACRO_SIZE 8 275#define CONDITION_SIZE 12 276#define IO_FLAG_CONDITION_SIZE 9 277#define IO_CONDITION_SIZE 5 278#define MEM_INIT_SIZE 66 279 280static void still_alive(void) 281{ 282#if 0 283 sync(); 284 mdelay(2); 285#endif 286} 287 288static uint32_t 289munge_reg(struct nvbios *bios, uint32_t reg) 290{ 291 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 292 struct dcb_entry *dcbent = bios->display.output; 293 294 if (dev_priv->card_type < NV_50) 295 return reg; 296 297 if (reg & 0x80000000) { 298 BUG_ON(bios->display.crtc < 0); 299 reg += bios->display.crtc * 0x800; 300 } 301 302 if (reg & 0x40000000) { 303 BUG_ON(!dcbent); 304 305 reg += (ffs(dcbent->or) - 1) * 0x800; 306 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1)) 307 reg += 0x00000080; 308 } 309 310 reg &= ~0xe0000000; 311 return reg; 312} 313 314static int 315valid_reg(struct nvbios *bios, uint32_t reg) 316{ 317 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 318 struct drm_device *dev = bios->dev; 319 320 /* C51 has misaligned regs on purpose. Marvellous */ 321 if (reg & 0x2 || 322 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51)) 323 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg); 324 325 /* warn on C51 regs that haven't been verified accessible in tracing */ 326 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 && 327 reg != 0x130d && reg != 0x1311 && reg != 0x60081d) 328 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n", 329 reg); 330 331 if (reg >= (8*1024*1024)) { 332 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg); 333 return 0; 334 } 335 336 return 1; 337} 338 339static bool 340valid_idx_port(struct nvbios *bios, uint16_t port) 341{ 342 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 343 struct drm_device *dev = bios->dev; 344 345 /* 346 * If adding more ports here, the read/write functions below will need 347 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is 348 * used for the port in question 349 */ 350 if (dev_priv->card_type < NV_50) { 351 if (port == NV_CIO_CRX__COLOR) 352 return true; 353 if (port == NV_VIO_SRX) 354 return true; 355 } else { 356 if (port == NV_CIO_CRX__COLOR) 357 return true; 358 } 359 360 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n", 361 port); 362 363 return false; 364} 365 366static bool 367valid_port(struct nvbios *bios, uint16_t port) 368{ 369 struct drm_device *dev = bios->dev; 370 371 /* 372 * If adding more ports here, the read/write functions below will need 373 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is 374 * used for the port in question 375 */ 376 if (port == NV_VIO_VSE2) 377 return true; 378 379 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port); 380 381 return false; 382} 383 384static uint32_t 385bios_rd32(struct nvbios *bios, uint32_t reg) 386{ 387 uint32_t data; 388 389 reg = munge_reg(bios, reg); 390 if (!valid_reg(bios, reg)) 391 return 0; 392 393 /* 394 * C51 sometimes uses regs with bit0 set in the address. For these 395 * cases there should exist a translation in a BIOS table to an IO 396 * port address which the BIOS uses for accessing the reg 397 * 398 * These only seem to appear for the power control regs to a flat panel, 399 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs 400 * for 0x1308 and 0x1310 are used - hence the mask below. An S3 401 * suspend-resume mmio trace from a C51 will be required to see if this 402 * is true for the power microcode in 0x14.., or whether the direct IO 403 * port access method is needed 404 */ 405 if (reg & 0x1) 406 reg &= ~0x1; 407 408 data = nv_rd32(bios->dev, reg); 409 410 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data); 411 412 return data; 413} 414 415static void 416bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data) 417{ 418 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 419 420 reg = munge_reg(bios, reg); 421 if (!valid_reg(bios, reg)) 422 return; 423 424 /* see note in bios_rd32 */ 425 if (reg & 0x1) 426 reg &= 0xfffffffe; 427 428 LOG_OLD_VALUE(bios_rd32(bios, reg)); 429 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data); 430 431 if (dev_priv->vbios.execute) { 432 still_alive(); 433 nv_wr32(bios->dev, reg, data); 434 } 435} 436 437static uint8_t 438bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index) 439{ 440 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 441 struct drm_device *dev = bios->dev; 442 uint8_t data; 443 444 if (!valid_idx_port(bios, port)) 445 return 0; 446 447 if (dev_priv->card_type < NV_50) { 448 if (port == NV_VIO_SRX) 449 data = NVReadVgaSeq(dev, bios->state.crtchead, index); 450 else /* assume NV_CIO_CRX__COLOR */ 451 data = NVReadVgaCrtc(dev, bios->state.crtchead, index); 452 } else { 453 uint32_t data32; 454 455 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3)); 456 data = (data32 >> ((index & 3) << 3)) & 0xff; 457 } 458 459 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, " 460 "Head: 0x%02X, Data: 0x%02X\n", 461 port, index, bios->state.crtchead, data); 462 return data; 463} 464 465static void 466bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data) 467{ 468 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 469 struct drm_device *dev = bios->dev; 470 471 if (!valid_idx_port(bios, port)) 472 return; 473 474 /* 475 * The current head is maintained in the nvbios member state.crtchead. 476 * We trap changes to CR44 and update the head variable and hence the 477 * register set written. 478 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance 479 * of the write, and to head1 after the write 480 */ 481 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 && 482 data != NV_CIO_CRE_44_HEADB) 483 bios->state.crtchead = 0; 484 485 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index)); 486 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, " 487 "Head: 0x%02X, Data: 0x%02X\n", 488 port, index, bios->state.crtchead, data); 489 490 if (bios->execute && dev_priv->card_type < NV_50) { 491 still_alive(); 492 if (port == NV_VIO_SRX) 493 NVWriteVgaSeq(dev, bios->state.crtchead, index, data); 494 else /* assume NV_CIO_CRX__COLOR */ 495 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data); 496 } else 497 if (bios->execute) { 498 uint32_t data32, shift = (index & 3) << 3; 499 500 still_alive(); 501 502 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3)); 503 data32 &= ~(0xff << shift); 504 data32 |= (data << shift); 505 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32); 506 } 507 508 if (port == NV_CIO_CRX__COLOR && 509 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB) 510 bios->state.crtchead = 1; 511} 512 513static uint8_t 514bios_port_rd(struct nvbios *bios, uint16_t port) 515{ 516 uint8_t data, head = bios->state.crtchead; 517 518 if (!valid_port(bios, port)) 519 return 0; 520 521 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port); 522 523 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n", 524 port, head, data); 525 526 return data; 527} 528 529static void 530bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data) 531{ 532 int head = bios->state.crtchead; 533 534 if (!valid_port(bios, port)) 535 return; 536 537 LOG_OLD_VALUE(bios_port_rd(bios, port)); 538 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n", 539 port, head, data); 540 541 if (!bios->execute) 542 return; 543 544 still_alive(); 545 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data); 546} 547 548static bool 549io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 550{ 551 /* 552 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte 553 * for the CRTC index; 1 byte for the mask to apply to the value 554 * retrieved from the CRTC; 1 byte for the shift right to apply to the 555 * masked CRTC value; 2 bytes for the offset to the flag array, to 556 * which the shifted value is added; 1 byte for the mask applied to the 557 * value read from the flag array; and 1 byte for the value to compare 558 * against the masked byte from the flag table. 559 */ 560 561 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE; 562 uint16_t crtcport = ROM16(bios->data[condptr]); 563 uint8_t crtcindex = bios->data[condptr + 2]; 564 uint8_t mask = bios->data[condptr + 3]; 565 uint8_t shift = bios->data[condptr + 4]; 566 uint16_t flagarray = ROM16(bios->data[condptr + 5]); 567 uint8_t flagarraymask = bios->data[condptr + 7]; 568 uint8_t cmpval = bios->data[condptr + 8]; 569 uint8_t data; 570 571 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 572 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, " 573 "Cmpval: 0x%02X\n", 574 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval); 575 576 data = bios_idxprt_rd(bios, crtcport, crtcindex); 577 578 data = bios->data[flagarray + ((data & mask) >> shift)]; 579 data &= flagarraymask; 580 581 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n", 582 offset, data, cmpval); 583 584 return (data == cmpval); 585} 586 587static bool 588bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 589{ 590 /* 591 * The condition table entry has 4 bytes for the address of the 592 * register to check, 4 bytes for a mask to apply to the register and 593 * 4 for a test comparison value 594 */ 595 596 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE; 597 uint32_t reg = ROM32(bios->data[condptr]); 598 uint32_t mask = ROM32(bios->data[condptr + 4]); 599 uint32_t cmpval = ROM32(bios->data[condptr + 8]); 600 uint32_t data; 601 602 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n", 603 offset, cond, reg, mask); 604 605 data = bios_rd32(bios, reg) & mask; 606 607 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n", 608 offset, data, cmpval); 609 610 return (data == cmpval); 611} 612 613static bool 614io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 615{ 616 /* 617 * The IO condition entry has 2 bytes for the IO port address; 1 byte 618 * for the index to write to io_port; 1 byte for the mask to apply to 619 * the byte read from io_port+1; and 1 byte for the value to compare 620 * against the masked byte. 621 */ 622 623 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE; 624 uint16_t io_port = ROM16(bios->data[condptr]); 625 uint8_t port_index = bios->data[condptr + 2]; 626 uint8_t mask = bios->data[condptr + 3]; 627 uint8_t cmpval = bios->data[condptr + 4]; 628 629 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask; 630 631 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n", 632 offset, data, cmpval); 633 634 return (data == cmpval); 635} 636 637static int 638nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk) 639{ 640 struct drm_nouveau_private *dev_priv = dev->dev_private; 641 struct nouveau_pll_vals pll; 642 struct pll_lims pll_limits; 643 u32 ctrl, mask, coef; 644 int ret; 645 646 ret = get_pll_limits(dev, reg, &pll_limits); 647 if (ret) 648 return ret; 649 650 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll); 651 if (!clk) 652 return -ERANGE; 653 654 coef = pll.N1 << 8 | pll.M1; 655 ctrl = pll.log2P << 16; 656 mask = 0x00070000; 657 if (reg == 0x004008) { 658 mask |= 0x01f80000; 659 ctrl |= (pll_limits.log2p_bias << 19); 660 ctrl |= (pll.log2P << 22); 661 } 662 663 if (!dev_priv->vbios.execute) 664 return 0; 665 666 nv_mask(dev, reg + 0, mask, ctrl); 667 nv_wr32(dev, reg + 4, coef); 668 return 0; 669} 670 671static int 672setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk) 673{ 674 struct drm_device *dev = bios->dev; 675 struct drm_nouveau_private *dev_priv = dev->dev_private; 676 /* clk in kHz */ 677 struct pll_lims pll_lim; 678 struct nouveau_pll_vals pllvals; 679 int ret; 680 681 if (dev_priv->card_type >= NV_50) 682 return nv50_pll_set(dev, reg, clk); 683 684 /* high regs (such as in the mac g5 table) are not -= 4 */ 685 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim); 686 if (ret) 687 return ret; 688 689 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals); 690 if (!clk) 691 return -ERANGE; 692 693 if (bios->execute) { 694 still_alive(); 695 nouveau_hw_setpll(dev, reg, &pllvals); 696 } 697 698 return 0; 699} 700 701static int dcb_entry_idx_from_crtchead(struct drm_device *dev) 702{ 703 struct drm_nouveau_private *dev_priv = dev->dev_private; 704 struct nvbios *bios = &dev_priv->vbios; 705 706 /* 707 * For the results of this function to be correct, CR44 must have been 708 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0, 709 * and the DCB table parsed, before the script calling the function is 710 * run. run_digital_op_script is example of how to do such setup 711 */ 712 713 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0); 714 715 if (dcb_entry > bios->dcb.entries) { 716 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently " 717 "(%02X)\n", dcb_entry); 718 dcb_entry = 0x7f; /* unused / invalid marker */ 719 } 720 721 return dcb_entry; 722} 723 724static struct nouveau_i2c_chan * 725init_i2c_device_find(struct drm_device *dev, int i2c_index) 726{ 727 if (i2c_index == 0xff) { 728 struct drm_nouveau_private *dev_priv = dev->dev_private; 729 struct dcb_table *dcb = &dev_priv->vbios.dcb; 730 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */ 731 int idx = dcb_entry_idx_from_crtchead(dev); 732 733 i2c_index = NV_I2C_DEFAULT(0); 734 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default) 735 i2c_index = NV_I2C_DEFAULT(1); 736 } 737 738 return nouveau_i2c_find(dev, i2c_index); 739} 740 741static uint32_t 742get_tmds_index_reg(struct drm_device *dev, uint8_t mlv) 743{ 744 /* 745 * For mlv < 0x80, it is an index into a table of TMDS base addresses. 746 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by 747 * CR58 for CR57 = 0 to index a table of offsets to the basic 748 * 0x6808b0 address. 749 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by 750 * CR58 for CR57 = 0 to index a table of offsets to the basic 751 * 0x6808b0 address, and then flip the offset by 8. 752 */ 753 754 struct drm_nouveau_private *dev_priv = dev->dev_private; 755 struct nvbios *bios = &dev_priv->vbios; 756 const int pramdac_offset[13] = { 757 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 }; 758 const uint32_t pramdac_table[4] = { 759 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 }; 760 761 if (mlv >= 0x80) { 762 int dcb_entry, dacoffset; 763 764 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */ 765 dcb_entry = dcb_entry_idx_from_crtchead(dev); 766 if (dcb_entry == 0x7f) 767 return 0; 768 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or]; 769 if (mlv == 0x81) 770 dacoffset ^= 8; 771 return 0x6808b0 + dacoffset; 772 } else { 773 if (mlv >= ARRAY_SIZE(pramdac_table)) { 774 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n", 775 mlv); 776 return 0; 777 } 778 return pramdac_table[mlv]; 779 } 780} 781 782static int 783init_io_restrict_prog(struct nvbios *bios, uint16_t offset, 784 struct init_exec *iexec) 785{ 786 /* 787 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2') 788 * 789 * offset (8 bit): opcode 790 * offset + 1 (16 bit): CRTC port 791 * offset + 3 (8 bit): CRTC index 792 * offset + 4 (8 bit): mask 793 * offset + 5 (8 bit): shift 794 * offset + 6 (8 bit): count 795 * offset + 7 (32 bit): register 796 * offset + 11 (32 bit): configuration 1 797 * ... 798 * 799 * Starting at offset + 11 there are "count" 32 bit values. 800 * To find out which value to use read index "CRTC index" on "CRTC 801 * port", AND this value with "mask" and then bit shift right "shift" 802 * bits. Read the appropriate value using this index and write to 803 * "register" 804 */ 805 806 uint16_t crtcport = ROM16(bios->data[offset + 1]); 807 uint8_t crtcindex = bios->data[offset + 3]; 808 uint8_t mask = bios->data[offset + 4]; 809 uint8_t shift = bios->data[offset + 5]; 810 uint8_t count = bios->data[offset + 6]; 811 uint32_t reg = ROM32(bios->data[offset + 7]); 812 uint8_t config; 813 uint32_t configval; 814 int len = 11 + count * 4; 815 816 if (!iexec->execute) 817 return len; 818 819 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 820 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n", 821 offset, crtcport, crtcindex, mask, shift, count, reg); 822 823 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 824 if (config > count) { 825 NV_ERROR(bios->dev, 826 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 827 offset, config, count); 828 return len; 829 } 830 831 configval = ROM32(bios->data[offset + 11 + config * 4]); 832 833 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config); 834 835 bios_wr32(bios, reg, configval); 836 837 return len; 838} 839 840static int 841init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 842{ 843 /* 844 * INIT_REPEAT opcode: 0x33 ('3') 845 * 846 * offset (8 bit): opcode 847 * offset + 1 (8 bit): count 848 * 849 * Execute script following this opcode up to INIT_REPEAT_END 850 * "count" times 851 */ 852 853 uint8_t count = bios->data[offset + 1]; 854 uint8_t i; 855 856 /* no iexec->execute check by design */ 857 858 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n", 859 offset, count); 860 861 iexec->repeat = true; 862 863 /* 864 * count - 1, as the script block will execute once when we leave this 865 * opcode -- this is compatible with bios behaviour as: 866 * a) the block is always executed at least once, even if count == 0 867 * b) the bios interpreter skips to the op following INIT_END_REPEAT, 868 * while we don't 869 */ 870 for (i = 0; i < count - 1; i++) 871 parse_init_table(bios, offset + 2, iexec); 872 873 iexec->repeat = false; 874 875 return 2; 876} 877 878static int 879init_io_restrict_pll(struct nvbios *bios, uint16_t offset, 880 struct init_exec *iexec) 881{ 882 /* 883 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4') 884 * 885 * offset (8 bit): opcode 886 * offset + 1 (16 bit): CRTC port 887 * offset + 3 (8 bit): CRTC index 888 * offset + 4 (8 bit): mask 889 * offset + 5 (8 bit): shift 890 * offset + 6 (8 bit): IO flag condition index 891 * offset + 7 (8 bit): count 892 * offset + 8 (32 bit): register 893 * offset + 12 (16 bit): frequency 1 894 * ... 895 * 896 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz). 897 * Set PLL register "register" to coefficients for frequency n, 898 * selected by reading index "CRTC index" of "CRTC port" ANDed with 899 * "mask" and shifted right by "shift". 900 * 901 * If "IO flag condition index" > 0, and condition met, double 902 * frequency before setting it. 903 */ 904 905 uint16_t crtcport = ROM16(bios->data[offset + 1]); 906 uint8_t crtcindex = bios->data[offset + 3]; 907 uint8_t mask = bios->data[offset + 4]; 908 uint8_t shift = bios->data[offset + 5]; 909 int8_t io_flag_condition_idx = bios->data[offset + 6]; 910 uint8_t count = bios->data[offset + 7]; 911 uint32_t reg = ROM32(bios->data[offset + 8]); 912 uint8_t config; 913 uint16_t freq; 914 int len = 12 + count * 2; 915 916 if (!iexec->execute) 917 return len; 918 919 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 920 "Shift: 0x%02X, IO Flag Condition: 0x%02X, " 921 "Count: 0x%02X, Reg: 0x%08X\n", 922 offset, crtcport, crtcindex, mask, shift, 923 io_flag_condition_idx, count, reg); 924 925 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 926 if (config > count) { 927 NV_ERROR(bios->dev, 928 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 929 offset, config, count); 930 return len; 931 } 932 933 freq = ROM16(bios->data[offset + 12 + config * 2]); 934 935 if (io_flag_condition_idx > 0) { 936 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) { 937 BIOSLOG(bios, "0x%04X: Condition fulfilled -- " 938 "frequency doubled\n", offset); 939 freq *= 2; 940 } else 941 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- " 942 "frequency unchanged\n", offset); 943 } 944 945 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n", 946 offset, reg, config, freq); 947 948 setPLL(bios, reg, freq * 10); 949 950 return len; 951} 952 953static int 954init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 955{ 956 /* 957 * INIT_END_REPEAT opcode: 0x36 ('6') 958 * 959 * offset (8 bit): opcode 960 * 961 * Marks the end of the block for INIT_REPEAT to repeat 962 */ 963 964 /* no iexec->execute check by design */ 965 966 /* 967 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when 968 * we're not in repeat mode 969 */ 970 if (iexec->repeat) 971 return 0; 972 973 return 1; 974} 975 976static int 977init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 978{ 979 /* 980 * INIT_COPY opcode: 0x37 ('7') 981 * 982 * offset (8 bit): opcode 983 * offset + 1 (32 bit): register 984 * offset + 5 (8 bit): shift 985 * offset + 6 (8 bit): srcmask 986 * offset + 7 (16 bit): CRTC port 987 * offset + 9 (8 bit): CRTC index 988 * offset + 10 (8 bit): mask 989 * 990 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with 991 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC 992 * port 993 */ 994 995 uint32_t reg = ROM32(bios->data[offset + 1]); 996 uint8_t shift = bios->data[offset + 5]; 997 uint8_t srcmask = bios->data[offset + 6]; 998 uint16_t crtcport = ROM16(bios->data[offset + 7]); 999 uint8_t crtcindex = bios->data[offset + 9]; 1000 uint8_t mask = bios->data[offset + 10]; 1001 uint32_t data; 1002 uint8_t crtcdata; 1003 1004 if (!iexec->execute) 1005 return 11; 1006 1007 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, " 1008 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n", 1009 offset, reg, shift, srcmask, crtcport, crtcindex, mask); 1010 1011 data = bios_rd32(bios, reg); 1012 1013 if (shift < 0x80) 1014 data >>= shift; 1015 else 1016 data <<= (0x100 - shift); 1017 1018 data &= srcmask; 1019 1020 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask; 1021 crtcdata |= (uint8_t)data; 1022 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata); 1023 1024 return 11; 1025} 1026 1027static int 1028init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1029{ 1030 /* 1031 * INIT_NOT opcode: 0x38 ('8') 1032 * 1033 * offset (8 bit): opcode 1034 * 1035 * Invert the current execute / no-execute condition (i.e. "else") 1036 */ 1037 if (iexec->execute) 1038 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset); 1039 else 1040 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset); 1041 1042 iexec->execute = !iexec->execute; 1043 return 1; 1044} 1045 1046static int 1047init_io_flag_condition(struct nvbios *bios, uint16_t offset, 1048 struct init_exec *iexec) 1049{ 1050 /* 1051 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9') 1052 * 1053 * offset (8 bit): opcode 1054 * offset + 1 (8 bit): condition number 1055 * 1056 * Check condition "condition number" in the IO flag condition table. 1057 * If condition not met skip subsequent opcodes until condition is 1058 * inverted (INIT_NOT), or we hit INIT_RESUME 1059 */ 1060 1061 uint8_t cond = bios->data[offset + 1]; 1062 1063 if (!iexec->execute) 1064 return 2; 1065 1066 if (io_flag_condition_met(bios, offset, cond)) 1067 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 1068 else { 1069 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 1070 iexec->execute = false; 1071 } 1072 1073 return 2; 1074} 1075 1076static int 1077init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1078{ 1079 /* 1080 * INIT_DP_CONDITION opcode: 0x3A ('') 1081 * 1082 * offset (8 bit): opcode 1083 * offset + 1 (8 bit): "sub" opcode 1084 * offset + 2 (8 bit): unknown 1085 * 1086 */ 1087 1088 struct dcb_entry *dcb = bios->display.output; 1089 struct drm_device *dev = bios->dev; 1090 uint8_t cond = bios->data[offset + 1]; 1091 uint8_t *table, *entry; 1092 1093 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond); 1094 1095 if (!iexec->execute) 1096 return 3; 1097 1098 table = nouveau_dp_bios_data(dev, dcb, &entry); 1099 if (!table) 1100 return 3; 1101 1102 switch (cond) { 1103 case 0: 1104 entry = dcb_conn(dev, dcb->connector); 1105 if (!entry || entry[0] != DCB_CONNECTOR_eDP) 1106 iexec->execute = false; 1107 break; 1108 case 1: 1109 case 2: 1110 if (!(entry[5] & cond)) 1111 iexec->execute = false; 1112 break; 1113 case 5: 1114 { 1115 struct nouveau_i2c_chan *auxch; 1116 int ret; 1117 1118 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index); 1119 if (!auxch) { 1120 NV_ERROR(dev, "0x%04X: couldn't get auxch\n", offset); 1121 return 3; 1122 } 1123 1124 ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1); 1125 if (ret) { 1126 NV_ERROR(dev, "0x%04X: auxch rd fail: %d\n", offset, ret); 1127 return 3; 1128 } 1129 1130 if (!(cond & 1)) 1131 iexec->execute = false; 1132 } 1133 break; 1134 default: 1135 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond); 1136 break; 1137 } 1138 1139 if (iexec->execute) 1140 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset); 1141 else 1142 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset); 1143 1144 return 3; 1145} 1146 1147static int 1148init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1149{ 1150 /* 1151 * INIT_3B opcode: 0x3B ('') 1152 * 1153 * offset (8 bit): opcode 1154 * offset + 1 (8 bit): crtc index 1155 * 1156 */ 1157 1158 uint8_t or = ffs(bios->display.output->or) - 1; 1159 uint8_t index = bios->data[offset + 1]; 1160 uint8_t data; 1161 1162 if (!iexec->execute) 1163 return 2; 1164 1165 data = bios_idxprt_rd(bios, 0x3d4, index); 1166 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or)); 1167 return 2; 1168} 1169 1170static int 1171init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1172{ 1173 /* 1174 * INIT_3C opcode: 0x3C ('') 1175 * 1176 * offset (8 bit): opcode 1177 * offset + 1 (8 bit): crtc index 1178 * 1179 */ 1180 1181 uint8_t or = ffs(bios->display.output->or) - 1; 1182 uint8_t index = bios->data[offset + 1]; 1183 uint8_t data; 1184 1185 if (!iexec->execute) 1186 return 2; 1187 1188 data = bios_idxprt_rd(bios, 0x3d4, index); 1189 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or)); 1190 return 2; 1191} 1192 1193static int 1194init_idx_addr_latched(struct nvbios *bios, uint16_t offset, 1195 struct init_exec *iexec) 1196{ 1197 /* 1198 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I') 1199 * 1200 * offset (8 bit): opcode 1201 * offset + 1 (32 bit): control register 1202 * offset + 5 (32 bit): data register 1203 * offset + 9 (32 bit): mask 1204 * offset + 13 (32 bit): data 1205 * offset + 17 (8 bit): count 1206 * offset + 18 (8 bit): address 1 1207 * offset + 19 (8 bit): data 1 1208 * ... 1209 * 1210 * For each of "count" address and data pairs, write "data n" to 1211 * "data register", read the current value of "control register", 1212 * and write it back once ANDed with "mask", ORed with "data", 1213 * and ORed with "address n" 1214 */ 1215 1216 uint32_t controlreg = ROM32(bios->data[offset + 1]); 1217 uint32_t datareg = ROM32(bios->data[offset + 5]); 1218 uint32_t mask = ROM32(bios->data[offset + 9]); 1219 uint32_t data = ROM32(bios->data[offset + 13]); 1220 uint8_t count = bios->data[offset + 17]; 1221 int len = 18 + count * 2; 1222 uint32_t value; 1223 int i; 1224 1225 if (!iexec->execute) 1226 return len; 1227 1228 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, " 1229 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n", 1230 offset, controlreg, datareg, mask, data, count); 1231 1232 for (i = 0; i < count; i++) { 1233 uint8_t instaddress = bios->data[offset + 18 + i * 2]; 1234 uint8_t instdata = bios->data[offset + 19 + i * 2]; 1235 1236 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n", 1237 offset, instaddress, instdata); 1238 1239 bios_wr32(bios, datareg, instdata); 1240 value = bios_rd32(bios, controlreg) & mask; 1241 value |= data; 1242 value |= instaddress; 1243 bios_wr32(bios, controlreg, value); 1244 } 1245 1246 return len; 1247} 1248 1249static int 1250init_io_restrict_pll2(struct nvbios *bios, uint16_t offset, 1251 struct init_exec *iexec) 1252{ 1253 /* 1254 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J') 1255 * 1256 * offset (8 bit): opcode 1257 * offset + 1 (16 bit): CRTC port 1258 * offset + 3 (8 bit): CRTC index 1259 * offset + 4 (8 bit): mask 1260 * offset + 5 (8 bit): shift 1261 * offset + 6 (8 bit): count 1262 * offset + 7 (32 bit): register 1263 * offset + 11 (32 bit): frequency 1 1264 * ... 1265 * 1266 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz). 1267 * Set PLL register "register" to coefficients for frequency n, 1268 * selected by reading index "CRTC index" of "CRTC port" ANDed with 1269 * "mask" and shifted right by "shift". 1270 */ 1271 1272 uint16_t crtcport = ROM16(bios->data[offset + 1]); 1273 uint8_t crtcindex = bios->data[offset + 3]; 1274 uint8_t mask = bios->data[offset + 4]; 1275 uint8_t shift = bios->data[offset + 5]; 1276 uint8_t count = bios->data[offset + 6]; 1277 uint32_t reg = ROM32(bios->data[offset + 7]); 1278 int len = 11 + count * 4; 1279 uint8_t config; 1280 uint32_t freq; 1281 1282 if (!iexec->execute) 1283 return len; 1284 1285 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 1286 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n", 1287 offset, crtcport, crtcindex, mask, shift, count, reg); 1288 1289 if (!reg) 1290 return len; 1291 1292 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 1293 if (config > count) { 1294 NV_ERROR(bios->dev, 1295 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 1296 offset, config, count); 1297 return len; 1298 } 1299 1300 freq = ROM32(bios->data[offset + 11 + config * 4]); 1301 1302 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n", 1303 offset, reg, config, freq); 1304 1305 setPLL(bios, reg, freq); 1306 1307 return len; 1308} 1309 1310static int 1311init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1312{ 1313 /* 1314 * INIT_PLL2 opcode: 0x4B ('K') 1315 * 1316 * offset (8 bit): opcode 1317 * offset + 1 (32 bit): register 1318 * offset + 5 (32 bit): freq 1319 * 1320 * Set PLL register "register" to coefficients for frequency "freq" 1321 */ 1322 1323 uint32_t reg = ROM32(bios->data[offset + 1]); 1324 uint32_t freq = ROM32(bios->data[offset + 5]); 1325 1326 if (!iexec->execute) 1327 return 9; 1328 1329 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n", 1330 offset, reg, freq); 1331 1332 setPLL(bios, reg, freq); 1333 return 9; 1334} 1335 1336static int 1337init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1338{ 1339 /* 1340 * INIT_I2C_BYTE opcode: 0x4C ('L') 1341 * 1342 * offset (8 bit): opcode 1343 * offset + 1 (8 bit): DCB I2C table entry index 1344 * offset + 2 (8 bit): I2C slave address 1345 * offset + 3 (8 bit): count 1346 * offset + 4 (8 bit): I2C register 1 1347 * offset + 5 (8 bit): mask 1 1348 * offset + 6 (8 bit): data 1 1349 * ... 1350 * 1351 * For each of "count" registers given by "I2C register n" on the device 1352 * addressed by "I2C slave address" on the I2C bus given by 1353 * "DCB I2C table entry index", read the register, AND the result with 1354 * "mask n" and OR it with "data n" before writing it back to the device 1355 */ 1356 1357 struct drm_device *dev = bios->dev; 1358 uint8_t i2c_index = bios->data[offset + 1]; 1359 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1360 uint8_t count = bios->data[offset + 3]; 1361 struct nouveau_i2c_chan *chan; 1362 int len = 4 + count * 3; 1363 int ret, i; 1364 1365 if (!iexec->execute) 1366 return len; 1367 1368 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1369 "Count: 0x%02X\n", 1370 offset, i2c_index, i2c_address, count); 1371 1372 chan = init_i2c_device_find(dev, i2c_index); 1373 if (!chan) { 1374 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset); 1375 return len; 1376 } 1377 1378 for (i = 0; i < count; i++) { 1379 uint8_t reg = bios->data[offset + 4 + i * 3]; 1380 uint8_t mask = bios->data[offset + 5 + i * 3]; 1381 uint8_t data = bios->data[offset + 6 + i * 3]; 1382 union i2c_smbus_data val; 1383 1384 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 1385 I2C_SMBUS_READ, reg, 1386 I2C_SMBUS_BYTE_DATA, &val); 1387 if (ret < 0) { 1388 NV_ERROR(dev, "0x%04X: i2c rd fail: %d\n", offset, ret); 1389 return len; 1390 } 1391 1392 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, " 1393 "Mask: 0x%02X, Data: 0x%02X\n", 1394 offset, reg, val.byte, mask, data); 1395 1396 if (!bios->execute) 1397 continue; 1398 1399 val.byte &= mask; 1400 val.byte |= data; 1401 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 1402 I2C_SMBUS_WRITE, reg, 1403 I2C_SMBUS_BYTE_DATA, &val); 1404 if (ret < 0) { 1405 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret); 1406 return len; 1407 } 1408 } 1409 1410 return len; 1411} 1412 1413static int 1414init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1415{ 1416 /* 1417 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M') 1418 * 1419 * offset (8 bit): opcode 1420 * offset + 1 (8 bit): DCB I2C table entry index 1421 * offset + 2 (8 bit): I2C slave address 1422 * offset + 3 (8 bit): count 1423 * offset + 4 (8 bit): I2C register 1 1424 * offset + 5 (8 bit): data 1 1425 * ... 1426 * 1427 * For each of "count" registers given by "I2C register n" on the device 1428 * addressed by "I2C slave address" on the I2C bus given by 1429 * "DCB I2C table entry index", set the register to "data n" 1430 */ 1431 1432 struct drm_device *dev = bios->dev; 1433 uint8_t i2c_index = bios->data[offset + 1]; 1434 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1435 uint8_t count = bios->data[offset + 3]; 1436 struct nouveau_i2c_chan *chan; 1437 int len = 4 + count * 2; 1438 int ret, i; 1439 1440 if (!iexec->execute) 1441 return len; 1442 1443 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1444 "Count: 0x%02X\n", 1445 offset, i2c_index, i2c_address, count); 1446 1447 chan = init_i2c_device_find(dev, i2c_index); 1448 if (!chan) { 1449 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset); 1450 return len; 1451 } 1452 1453 for (i = 0; i < count; i++) { 1454 uint8_t reg = bios->data[offset + 4 + i * 2]; 1455 union i2c_smbus_data val; 1456 1457 val.byte = bios->data[offset + 5 + i * 2]; 1458 1459 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n", 1460 offset, reg, val.byte); 1461 1462 if (!bios->execute) 1463 continue; 1464 1465 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 1466 I2C_SMBUS_WRITE, reg, 1467 I2C_SMBUS_BYTE_DATA, &val); 1468 if (ret < 0) { 1469 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret); 1470 return len; 1471 } 1472 } 1473 1474 return len; 1475} 1476 1477static int 1478init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1479{ 1480 /* 1481 * INIT_ZM_I2C opcode: 0x4E ('N') 1482 * 1483 * offset (8 bit): opcode 1484 * offset + 1 (8 bit): DCB I2C table entry index 1485 * offset + 2 (8 bit): I2C slave address 1486 * offset + 3 (8 bit): count 1487 * offset + 4 (8 bit): data 1 1488 * ... 1489 * 1490 * Send "count" bytes ("data n") to the device addressed by "I2C slave 1491 * address" on the I2C bus given by "DCB I2C table entry index" 1492 */ 1493 1494 struct drm_device *dev = bios->dev; 1495 uint8_t i2c_index = bios->data[offset + 1]; 1496 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1497 uint8_t count = bios->data[offset + 3]; 1498 int len = 4 + count; 1499 struct nouveau_i2c_chan *chan; 1500 struct i2c_msg msg; 1501 uint8_t data[256]; 1502 int ret, i; 1503 1504 if (!iexec->execute) 1505 return len; 1506 1507 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1508 "Count: 0x%02X\n", 1509 offset, i2c_index, i2c_address, count); 1510 1511 chan = init_i2c_device_find(dev, i2c_index); 1512 if (!chan) { 1513 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset); 1514 return len; 1515 } 1516 1517 for (i = 0; i < count; i++) { 1518 data[i] = bios->data[offset + 4 + i]; 1519 1520 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]); 1521 } 1522 1523 if (bios->execute) { 1524 msg.addr = i2c_address; 1525 msg.flags = 0; 1526 msg.len = count; 1527 msg.buf = data; 1528 ret = i2c_transfer(&chan->adapter, &msg, 1); 1529 if (ret != 1) { 1530 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret); 1531 return len; 1532 } 1533 } 1534 1535 return len; 1536} 1537 1538static int 1539init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1540{ 1541 /* 1542 * INIT_TMDS opcode: 0x4F ('O') (non-canon name) 1543 * 1544 * offset (8 bit): opcode 1545 * offset + 1 (8 bit): magic lookup value 1546 * offset + 2 (8 bit): TMDS address 1547 * offset + 3 (8 bit): mask 1548 * offset + 4 (8 bit): data 1549 * 1550 * Read the data reg for TMDS address "TMDS address", AND it with mask 1551 * and OR it with data, then write it back 1552 * "magic lookup value" determines which TMDS base address register is 1553 * used -- see get_tmds_index_reg() 1554 */ 1555 1556 struct drm_device *dev = bios->dev; 1557 uint8_t mlv = bios->data[offset + 1]; 1558 uint32_t tmdsaddr = bios->data[offset + 2]; 1559 uint8_t mask = bios->data[offset + 3]; 1560 uint8_t data = bios->data[offset + 4]; 1561 uint32_t reg, value; 1562 1563 if (!iexec->execute) 1564 return 5; 1565 1566 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, " 1567 "Mask: 0x%02X, Data: 0x%02X\n", 1568 offset, mlv, tmdsaddr, mask, data); 1569 1570 reg = get_tmds_index_reg(bios->dev, mlv); 1571 if (!reg) { 1572 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset); 1573 return 5; 1574 } 1575 1576 bios_wr32(bios, reg, 1577 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE); 1578 value = (bios_rd32(bios, reg + 4) & mask) | data; 1579 bios_wr32(bios, reg + 4, value); 1580 bios_wr32(bios, reg, tmdsaddr); 1581 1582 return 5; 1583} 1584 1585static int 1586init_zm_tmds_group(struct nvbios *bios, uint16_t offset, 1587 struct init_exec *iexec) 1588{ 1589 /* 1590 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name) 1591 * 1592 * offset (8 bit): opcode 1593 * offset + 1 (8 bit): magic lookup value 1594 * offset + 2 (8 bit): count 1595 * offset + 3 (8 bit): addr 1 1596 * offset + 4 (8 bit): data 1 1597 * ... 1598 * 1599 * For each of "count" TMDS address and data pairs write "data n" to 1600 * "addr n". "magic lookup value" determines which TMDS base address 1601 * register is used -- see get_tmds_index_reg() 1602 */ 1603 1604 struct drm_device *dev = bios->dev; 1605 uint8_t mlv = bios->data[offset + 1]; 1606 uint8_t count = bios->data[offset + 2]; 1607 int len = 3 + count * 2; 1608 uint32_t reg; 1609 int i; 1610 1611 if (!iexec->execute) 1612 return len; 1613 1614 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n", 1615 offset, mlv, count); 1616 1617 reg = get_tmds_index_reg(bios->dev, mlv); 1618 if (!reg) { 1619 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset); 1620 return len; 1621 } 1622 1623 for (i = 0; i < count; i++) { 1624 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2]; 1625 uint8_t tmdsdata = bios->data[offset + 4 + i * 2]; 1626 1627 bios_wr32(bios, reg + 4, tmdsdata); 1628 bios_wr32(bios, reg, tmdsaddr); 1629 } 1630 1631 return len; 1632} 1633 1634static int 1635init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset, 1636 struct init_exec *iexec) 1637{ 1638 /* 1639 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q') 1640 * 1641 * offset (8 bit): opcode 1642 * offset + 1 (8 bit): CRTC index1 1643 * offset + 2 (8 bit): CRTC index2 1644 * offset + 3 (8 bit): baseaddr 1645 * offset + 4 (8 bit): count 1646 * offset + 5 (8 bit): data 1 1647 * ... 1648 * 1649 * For each of "count" address and data pairs, write "baseaddr + n" to 1650 * "CRTC index1" and "data n" to "CRTC index2" 1651 * Once complete, restore initial value read from "CRTC index1" 1652 */ 1653 uint8_t crtcindex1 = bios->data[offset + 1]; 1654 uint8_t crtcindex2 = bios->data[offset + 2]; 1655 uint8_t baseaddr = bios->data[offset + 3]; 1656 uint8_t count = bios->data[offset + 4]; 1657 int len = 5 + count; 1658 uint8_t oldaddr, data; 1659 int i; 1660 1661 if (!iexec->execute) 1662 return len; 1663 1664 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, " 1665 "BaseAddr: 0x%02X, Count: 0x%02X\n", 1666 offset, crtcindex1, crtcindex2, baseaddr, count); 1667 1668 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1); 1669 1670 for (i = 0; i < count; i++) { 1671 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, 1672 baseaddr + i); 1673 data = bios->data[offset + 5 + i]; 1674 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data); 1675 } 1676 1677 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr); 1678 1679 return len; 1680} 1681 1682static int 1683init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1684{ 1685 /* 1686 * INIT_CR opcode: 0x52 ('R') 1687 * 1688 * offset (8 bit): opcode 1689 * offset + 1 (8 bit): CRTC index 1690 * offset + 2 (8 bit): mask 1691 * offset + 3 (8 bit): data 1692 * 1693 * Assign the value of at "CRTC index" ANDed with mask and ORed with 1694 * data back to "CRTC index" 1695 */ 1696 1697 uint8_t crtcindex = bios->data[offset + 1]; 1698 uint8_t mask = bios->data[offset + 2]; 1699 uint8_t data = bios->data[offset + 3]; 1700 uint8_t value; 1701 1702 if (!iexec->execute) 1703 return 4; 1704 1705 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n", 1706 offset, crtcindex, mask, data); 1707 1708 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask; 1709 value |= data; 1710 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value); 1711 1712 return 4; 1713} 1714 1715static int 1716init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1717{ 1718 /* 1719 * INIT_ZM_CR opcode: 0x53 ('S') 1720 * 1721 * offset (8 bit): opcode 1722 * offset + 1 (8 bit): CRTC index 1723 * offset + 2 (8 bit): value 1724 * 1725 * Assign "value" to CRTC register with index "CRTC index". 1726 */ 1727 1728 uint8_t crtcindex = ROM32(bios->data[offset + 1]); 1729 uint8_t data = bios->data[offset + 2]; 1730 1731 if (!iexec->execute) 1732 return 3; 1733 1734 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data); 1735 1736 return 3; 1737} 1738 1739static int 1740init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1741{ 1742 /* 1743 * INIT_ZM_CR_GROUP opcode: 0x54 ('T') 1744 * 1745 * offset (8 bit): opcode 1746 * offset + 1 (8 bit): count 1747 * offset + 2 (8 bit): CRTC index 1 1748 * offset + 3 (8 bit): value 1 1749 * ... 1750 * 1751 * For "count", assign "value n" to CRTC register with index 1752 * "CRTC index n". 1753 */ 1754 1755 uint8_t count = bios->data[offset + 1]; 1756 int len = 2 + count * 2; 1757 int i; 1758 1759 if (!iexec->execute) 1760 return len; 1761 1762 for (i = 0; i < count; i++) 1763 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec); 1764 1765 return len; 1766} 1767 1768static int 1769init_condition_time(struct nvbios *bios, uint16_t offset, 1770 struct init_exec *iexec) 1771{ 1772 /* 1773 * INIT_CONDITION_TIME opcode: 0x56 ('V') 1774 * 1775 * offset (8 bit): opcode 1776 * offset + 1 (8 bit): condition number 1777 * offset + 2 (8 bit): retries / 50 1778 * 1779 * Check condition "condition number" in the condition table. 1780 * Bios code then sleeps for 2ms if the condition is not met, and 1781 * repeats up to "retries" times, but on one C51 this has proved 1782 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do 1783 * this, and bail after "retries" times, or 2s, whichever is less. 1784 * If still not met after retries, clear execution flag for this table. 1785 */ 1786 1787 uint8_t cond = bios->data[offset + 1]; 1788 uint16_t retries = bios->data[offset + 2] * 50; 1789 unsigned cnt; 1790 1791 if (!iexec->execute) 1792 return 3; 1793 1794 if (retries > 100) 1795 retries = 100; 1796 1797 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n", 1798 offset, cond, retries); 1799 1800 if (!bios->execute) /* avoid 2s delays when "faking" execution */ 1801 retries = 1; 1802 1803 for (cnt = 0; cnt < retries; cnt++) { 1804 if (bios_condition_met(bios, offset, cond)) { 1805 BIOSLOG(bios, "0x%04X: Condition met, continuing\n", 1806 offset); 1807 break; 1808 } else { 1809 BIOSLOG(bios, "0x%04X: " 1810 "Condition not met, sleeping for 20ms\n", 1811 offset); 1812 mdelay(20); 1813 } 1814 } 1815 1816 if (!bios_condition_met(bios, offset, cond)) { 1817 NV_WARN(bios->dev, 1818 "0x%04X: Condition still not met after %dms, " 1819 "skipping following opcodes\n", offset, 20 * retries); 1820 iexec->execute = false; 1821 } 1822 1823 return 3; 1824} 1825 1826static int 1827init_ltime(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1828{ 1829 /* 1830 * INIT_LTIME opcode: 0x57 ('V') 1831 * 1832 * offset (8 bit): opcode 1833 * offset + 1 (16 bit): time 1834 * 1835 * Sleep for "time" milliseconds. 1836 */ 1837 1838 unsigned time = ROM16(bios->data[offset + 1]); 1839 1840 if (!iexec->execute) 1841 return 3; 1842 1843 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X milliseconds\n", 1844 offset, time); 1845 1846 mdelay(time); 1847 1848 return 3; 1849} 1850 1851static int 1852init_zm_reg_sequence(struct nvbios *bios, uint16_t offset, 1853 struct init_exec *iexec) 1854{ 1855 /* 1856 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X') 1857 * 1858 * offset (8 bit): opcode 1859 * offset + 1 (32 bit): base register 1860 * offset + 5 (8 bit): count 1861 * offset + 6 (32 bit): value 1 1862 * ... 1863 * 1864 * Starting at offset + 6 there are "count" 32 bit values. 1865 * For "count" iterations set "base register" + 4 * current_iteration 1866 * to "value current_iteration" 1867 */ 1868 1869 uint32_t basereg = ROM32(bios->data[offset + 1]); 1870 uint32_t count = bios->data[offset + 5]; 1871 int len = 6 + count * 4; 1872 int i; 1873 1874 if (!iexec->execute) 1875 return len; 1876 1877 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n", 1878 offset, basereg, count); 1879 1880 for (i = 0; i < count; i++) { 1881 uint32_t reg = basereg + i * 4; 1882 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]); 1883 1884 bios_wr32(bios, reg, data); 1885 } 1886 1887 return len; 1888} 1889 1890static int 1891init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1892{ 1893 /* 1894 * INIT_SUB_DIRECT opcode: 0x5B ('[') 1895 * 1896 * offset (8 bit): opcode 1897 * offset + 1 (16 bit): subroutine offset (in bios) 1898 * 1899 * Calls a subroutine that will execute commands until INIT_DONE 1900 * is found. 1901 */ 1902 1903 uint16_t sub_offset = ROM16(bios->data[offset + 1]); 1904 1905 if (!iexec->execute) 1906 return 3; 1907 1908 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n", 1909 offset, sub_offset); 1910 1911 parse_init_table(bios, sub_offset, iexec); 1912 1913 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset); 1914 1915 return 3; 1916} 1917 1918static int 1919init_jump(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1920{ 1921 /* 1922 * INIT_JUMP opcode: 0x5C ('\') 1923 * 1924 * offset (8 bit): opcode 1925 * offset + 1 (16 bit): offset (in bios) 1926 * 1927 * Continue execution of init table from 'offset' 1928 */ 1929 1930 uint16_t jmp_offset = ROM16(bios->data[offset + 1]); 1931 1932 if (!iexec->execute) 1933 return 3; 1934 1935 BIOSLOG(bios, "0x%04X: Jump to 0x%04X\n", offset, jmp_offset); 1936 return jmp_offset - offset; 1937} 1938 1939static int 1940init_i2c_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1941{ 1942 /* 1943 * INIT_I2C_IF opcode: 0x5E ('^') 1944 * 1945 * offset (8 bit): opcode 1946 * offset + 1 (8 bit): DCB I2C table entry index 1947 * offset + 2 (8 bit): I2C slave address 1948 * offset + 3 (8 bit): I2C register 1949 * offset + 4 (8 bit): mask 1950 * offset + 5 (8 bit): data 1951 * 1952 * Read the register given by "I2C register" on the device addressed 1953 * by "I2C slave address" on the I2C bus given by "DCB I2C table 1954 * entry index". Compare the result AND "mask" to "data". 1955 * If they're not equal, skip subsequent opcodes until condition is 1956 * inverted (INIT_NOT), or we hit INIT_RESUME 1957 */ 1958 1959 uint8_t i2c_index = bios->data[offset + 1]; 1960 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1961 uint8_t reg = bios->data[offset + 3]; 1962 uint8_t mask = bios->data[offset + 4]; 1963 uint8_t data = bios->data[offset + 5]; 1964 struct nouveau_i2c_chan *chan; 1965 union i2c_smbus_data val; 1966 int ret; 1967 1968 /* no execute check by design */ 1969 1970 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n", 1971 offset, i2c_index, i2c_address); 1972 1973 chan = init_i2c_device_find(bios->dev, i2c_index); 1974 if (!chan) 1975 return -ENODEV; 1976 1977 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 1978 I2C_SMBUS_READ, reg, 1979 I2C_SMBUS_BYTE_DATA, &val); 1980 if (ret < 0) { 1981 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: [no device], " 1982 "Mask: 0x%02X, Data: 0x%02X\n", 1983 offset, reg, mask, data); 1984 iexec->execute = 0; 1985 return 6; 1986 } 1987 1988 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, " 1989 "Mask: 0x%02X, Data: 0x%02X\n", 1990 offset, reg, val.byte, mask, data); 1991 1992 iexec->execute = ((val.byte & mask) == data); 1993 1994 return 6; 1995} 1996 1997static int 1998init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1999{ 2000 /* 2001 * INIT_COPY_NV_REG opcode: 0x5F ('_') 2002 * 2003 * offset (8 bit): opcode 2004 * offset + 1 (32 bit): src reg 2005 * offset + 5 (8 bit): shift 2006 * offset + 6 (32 bit): src mask 2007 * offset + 10 (32 bit): xor 2008 * offset + 14 (32 bit): dst reg 2009 * offset + 18 (32 bit): dst mask 2010 * 2011 * Shift REGVAL("src reg") right by (signed) "shift", AND result with 2012 * "src mask", then XOR with "xor". Write this OR'd with 2013 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg" 2014 */ 2015 2016 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1])); 2017 uint8_t shift = bios->data[offset + 5]; 2018 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6])); 2019 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10])); 2020 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14])); 2021 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18])); 2022 uint32_t srcvalue, dstvalue; 2023 2024 if (!iexec->execute) 2025 return 22; 2026 2027 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, " 2028 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n", 2029 offset, srcreg, shift, srcmask, xor, dstreg, dstmask); 2030 2031 srcvalue = bios_rd32(bios, srcreg); 2032 2033 if (shift < 0x80) 2034 srcvalue >>= shift; 2035 else 2036 srcvalue <<= (0x100 - shift); 2037 2038 srcvalue = (srcvalue & srcmask) ^ xor; 2039 2040 dstvalue = bios_rd32(bios, dstreg) & dstmask; 2041 2042 bios_wr32(bios, dstreg, dstvalue | srcvalue); 2043 2044 return 22; 2045} 2046 2047static int 2048init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2049{ 2050 /* 2051 * INIT_ZM_INDEX_IO opcode: 0x62 ('b') 2052 * 2053 * offset (8 bit): opcode 2054 * offset + 1 (16 bit): CRTC port 2055 * offset + 3 (8 bit): CRTC index 2056 * offset + 4 (8 bit): data 2057 * 2058 * Write "data" to index "CRTC index" of "CRTC port" 2059 */ 2060 uint16_t crtcport = ROM16(bios->data[offset + 1]); 2061 uint8_t crtcindex = bios->data[offset + 3]; 2062 uint8_t data = bios->data[offset + 4]; 2063 2064 if (!iexec->execute) 2065 return 5; 2066 2067 bios_idxprt_wr(bios, crtcport, crtcindex, data); 2068 2069 return 5; 2070} 2071 2072static inline void 2073bios_md32(struct nvbios *bios, uint32_t reg, 2074 uint32_t mask, uint32_t val) 2075{ 2076 bios_wr32(bios, reg, (bios_rd32(bios, reg) & ~mask) | val); 2077} 2078 2079static uint32_t 2080peek_fb(struct drm_device *dev, struct io_mapping *fb, 2081 uint32_t off) 2082{ 2083 uint32_t val = 0; 2084 2085 if (off < pci_resource_len(dev->pdev, 1)) { 2086 uint8_t __iomem *p = 2087 io_mapping_map_atomic_wc(fb, off & PAGE_MASK); 2088 2089 val = ioread32(p + (off & ~PAGE_MASK)); 2090 2091 io_mapping_unmap_atomic(p); 2092 } 2093 2094 return val; 2095} 2096 2097static void 2098poke_fb(struct drm_device *dev, struct io_mapping *fb, 2099 uint32_t off, uint32_t val) 2100{ 2101 if (off < pci_resource_len(dev->pdev, 1)) { 2102 uint8_t __iomem *p = 2103 io_mapping_map_atomic_wc(fb, off & PAGE_MASK); 2104 2105 iowrite32(val, p + (off & ~PAGE_MASK)); 2106 wmb(); 2107 2108 io_mapping_unmap_atomic(p); 2109 } 2110} 2111 2112static inline bool 2113read_back_fb(struct drm_device *dev, struct io_mapping *fb, 2114 uint32_t off, uint32_t val) 2115{ 2116 poke_fb(dev, fb, off, val); 2117 return val == peek_fb(dev, fb, off); 2118} 2119 2120static int 2121nv04_init_compute_mem(struct nvbios *bios) 2122{ 2123 struct drm_device *dev = bios->dev; 2124 uint32_t patt = 0xdeadbeef; 2125 struct io_mapping *fb; 2126 int i; 2127 2128 /* Map the framebuffer aperture */ 2129 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1), 2130 pci_resource_len(dev->pdev, 1)); 2131 if (!fb) 2132 return -ENOMEM; 2133 2134 /* Sequencer and refresh off */ 2135 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20); 2136 bios_md32(bios, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF); 2137 2138 bios_md32(bios, NV04_PFB_BOOT_0, ~0, 2139 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB | 2140 NV04_PFB_BOOT_0_RAM_WIDTH_128 | 2141 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT); 2142 2143 for (i = 0; i < 4; i++) 2144 poke_fb(dev, fb, 4 * i, patt); 2145 2146 poke_fb(dev, fb, 0x400000, patt + 1); 2147 2148 if (peek_fb(dev, fb, 0) == patt + 1) { 2149 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE, 2150 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT); 2151 bios_md32(bios, NV04_PFB_DEBUG_0, 2152 NV04_PFB_DEBUG_0_REFRESH_OFF, 0); 2153 2154 for (i = 0; i < 4; i++) 2155 poke_fb(dev, fb, 4 * i, patt); 2156 2157 if ((peek_fb(dev, fb, 0xc) & 0xffff) != (patt & 0xffff)) 2158 bios_md32(bios, NV04_PFB_BOOT_0, 2159 NV04_PFB_BOOT_0_RAM_WIDTH_128 | 2160 NV04_PFB_BOOT_0_RAM_AMOUNT, 2161 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 2162 2163 } else if ((peek_fb(dev, fb, 0xc) & 0xffff0000) != 2164 (patt & 0xffff0000)) { 2165 bios_md32(bios, NV04_PFB_BOOT_0, 2166 NV04_PFB_BOOT_0_RAM_WIDTH_128 | 2167 NV04_PFB_BOOT_0_RAM_AMOUNT, 2168 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); 2169 2170 } else if (peek_fb(dev, fb, 0) != patt) { 2171 if (read_back_fb(dev, fb, 0x800000, patt)) 2172 bios_md32(bios, NV04_PFB_BOOT_0, 2173 NV04_PFB_BOOT_0_RAM_AMOUNT, 2174 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 2175 else 2176 bios_md32(bios, NV04_PFB_BOOT_0, 2177 NV04_PFB_BOOT_0_RAM_AMOUNT, 2178 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); 2179 2180 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE, 2181 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT); 2182 2183 } else if (!read_back_fb(dev, fb, 0x800000, patt)) { 2184 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, 2185 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 2186 2187 } 2188 2189 /* Refresh on, sequencer on */ 2190 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0); 2191 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20); 2192 2193 io_mapping_free(fb); 2194 return 0; 2195} 2196 2197static const uint8_t * 2198nv05_memory_config(struct nvbios *bios) 2199{ 2200 /* Defaults for BIOSes lacking a memory config table */ 2201 static const uint8_t default_config_tab[][2] = { 2202 { 0x24, 0x00 }, 2203 { 0x28, 0x00 }, 2204 { 0x24, 0x01 }, 2205 { 0x1f, 0x00 }, 2206 { 0x0f, 0x00 }, 2207 { 0x17, 0x00 }, 2208 { 0x06, 0x00 }, 2209 { 0x00, 0x00 } 2210 }; 2211 int i = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 2212 NV_PEXTDEV_BOOT_0_RAMCFG) >> 2; 2213 2214 if (bios->legacy.mem_init_tbl_ptr) 2215 return &bios->data[bios->legacy.mem_init_tbl_ptr + 2 * i]; 2216 else 2217 return default_config_tab[i]; 2218} 2219 2220static int 2221nv05_init_compute_mem(struct nvbios *bios) 2222{ 2223 struct drm_device *dev = bios->dev; 2224 const uint8_t *ramcfg = nv05_memory_config(bios); 2225 uint32_t patt = 0xdeadbeef; 2226 struct io_mapping *fb; 2227 int i, v; 2228 2229 /* Map the framebuffer aperture */ 2230 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1), 2231 pci_resource_len(dev->pdev, 1)); 2232 if (!fb) 2233 return -ENOMEM; 2234 2235 /* Sequencer off */ 2236 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20); 2237 2238 if (bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE) 2239 goto out; 2240 2241 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0); 2242 2243 /* If present load the hardcoded scrambling table */ 2244 if (bios->legacy.mem_init_tbl_ptr) { 2245 uint32_t *scramble_tab = (uint32_t *)&bios->data[ 2246 bios->legacy.mem_init_tbl_ptr + 0x10]; 2247 2248 for (i = 0; i < 8; i++) 2249 bios_wr32(bios, NV04_PFB_SCRAMBLE(i), 2250 ROM32(scramble_tab[i])); 2251 } 2252 2253 /* Set memory type/width/length defaults depending on the straps */ 2254 bios_md32(bios, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]); 2255 2256 if (ramcfg[1] & 0x80) 2257 bios_md32(bios, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE); 2258 2259 bios_md32(bios, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20); 2260 bios_md32(bios, NV04_PFB_CFG1, 0, 1); 2261 2262 /* Probe memory bus width */ 2263 for (i = 0; i < 4; i++) 2264 poke_fb(dev, fb, 4 * i, patt); 2265 2266 if (peek_fb(dev, fb, 0xc) != patt) 2267 bios_md32(bios, NV04_PFB_BOOT_0, 2268 NV04_PFB_BOOT_0_RAM_WIDTH_128, 0); 2269 2270 /* Probe memory length */ 2271 v = bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT; 2272 2273 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB && 2274 (!read_back_fb(dev, fb, 0x1000000, ++patt) || 2275 !read_back_fb(dev, fb, 0, ++patt))) 2276 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, 2277 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB); 2278 2279 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB && 2280 !read_back_fb(dev, fb, 0x800000, ++patt)) 2281 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, 2282 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 2283 2284 if (!read_back_fb(dev, fb, 0x400000, ++patt)) 2285 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, 2286 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); 2287 2288out: 2289 /* Sequencer on */ 2290 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20); 2291 2292 io_mapping_free(fb); 2293 return 0; 2294} 2295 2296static int 2297nv10_init_compute_mem(struct nvbios *bios) 2298{ 2299 struct drm_device *dev = bios->dev; 2300 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2301 const int mem_width[] = { 0x10, 0x00, 0x20 }; 2302 const int mem_width_count = (dev_priv->chipset >= 0x17 ? 3 : 2); 2303 uint32_t patt = 0xdeadbeef; 2304 struct io_mapping *fb; 2305 int i, j, k; 2306 2307 /* Map the framebuffer aperture */ 2308 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1), 2309 pci_resource_len(dev->pdev, 1)); 2310 if (!fb) 2311 return -ENOMEM; 2312 2313 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1); 2314 2315 /* Probe memory bus width */ 2316 for (i = 0; i < mem_width_count; i++) { 2317 bios_md32(bios, NV04_PFB_CFG0, 0x30, mem_width[i]); 2318 2319 for (j = 0; j < 4; j++) { 2320 for (k = 0; k < 4; k++) 2321 poke_fb(dev, fb, 0x1c, 0); 2322 2323 poke_fb(dev, fb, 0x1c, patt); 2324 poke_fb(dev, fb, 0x3c, 0); 2325 2326 if (peek_fb(dev, fb, 0x1c) == patt) 2327 goto mem_width_found; 2328 } 2329 } 2330 2331mem_width_found: 2332 patt <<= 1; 2333 2334 /* Probe amount of installed memory */ 2335 for (i = 0; i < 4; i++) { 2336 int off = bios_rd32(bios, NV04_PFB_FIFO_DATA) - 0x100000; 2337 2338 poke_fb(dev, fb, off, patt); 2339 poke_fb(dev, fb, 0, 0); 2340 2341 peek_fb(dev, fb, 0); 2342 peek_fb(dev, fb, 0); 2343 peek_fb(dev, fb, 0); 2344 peek_fb(dev, fb, 0); 2345 2346 if (peek_fb(dev, fb, off) == patt) 2347 goto amount_found; 2348 } 2349 2350 /* IC missing - disable the upper half memory space. */ 2351 bios_md32(bios, NV04_PFB_CFG0, 0x1000, 0); 2352 2353amount_found: 2354 io_mapping_free(fb); 2355 return 0; 2356} 2357 2358static int 2359nv20_init_compute_mem(struct nvbios *bios) 2360{ 2361 struct drm_device *dev = bios->dev; 2362 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2363 uint32_t mask = (dev_priv->chipset >= 0x25 ? 0x300 : 0x900); 2364 uint32_t amount, off; 2365 struct io_mapping *fb; 2366 2367 /* Map the framebuffer aperture */ 2368 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1), 2369 pci_resource_len(dev->pdev, 1)); 2370 if (!fb) 2371 return -ENOMEM; 2372 2373 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1); 2374 2375 /* Allow full addressing */ 2376 bios_md32(bios, NV04_PFB_CFG0, 0, mask); 2377 2378 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA); 2379 for (off = amount; off > 0x2000000; off -= 0x2000000) 2380 poke_fb(dev, fb, off - 4, off); 2381 2382 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA); 2383 if (amount != peek_fb(dev, fb, amount - 4)) 2384 /* IC missing - disable the upper half memory space. */ 2385 bios_md32(bios, NV04_PFB_CFG0, mask, 0); 2386 2387 io_mapping_free(fb); 2388 return 0; 2389} 2390 2391static int 2392init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2393{ 2394 /* 2395 * INIT_COMPUTE_MEM opcode: 0x63 ('c') 2396 * 2397 * offset (8 bit): opcode 2398 * 2399 * This opcode is meant to set the PFB memory config registers 2400 * appropriately so that we can correctly calculate how much VRAM it 2401 * has (on nv10 and better chipsets the amount of installed VRAM is 2402 * subsequently reported in NV_PFB_CSTATUS (0x10020C)). 2403 * 2404 * The implementation of this opcode in general consists of several 2405 * parts: 2406 * 2407 * 1) Determination of memory type and density. Only necessary for 2408 * really old chipsets, the memory type reported by the strap bits 2409 * (0x101000) is assumed to be accurate on nv05 and newer. 2410 * 2411 * 2) Determination of the memory bus width. Usually done by a cunning 2412 * combination of writes to offsets 0x1c and 0x3c in the fb, and 2413 * seeing whether the written values are read back correctly. 2414 * 2415 * Only necessary on nv0x-nv1x and nv34, on the other cards we can 2416 * trust the straps. 2417 * 2418 * 3) Determination of how many of the card's RAM pads have ICs 2419 * attached, usually done by a cunning combination of writes to an 2420 * offset slightly less than the maximum memory reported by 2421 * NV_PFB_CSTATUS, then seeing if the test pattern can be read back. 2422 * 2423 * This appears to be a NOP on IGPs and NV4x or newer chipsets, both io 2424 * logs of the VBIOS and kmmio traces of the binary driver POSTing the 2425 * card show nothing being done for this opcode. Why is it still listed 2426 * in the table?! 2427 */ 2428 2429 /* no iexec->execute check by design */ 2430 2431 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2432 int ret; 2433 2434 if (dev_priv->chipset >= 0x40 || 2435 dev_priv->chipset == 0x1a || 2436 dev_priv->chipset == 0x1f) 2437 ret = 0; 2438 else if (dev_priv->chipset >= 0x20 && 2439 dev_priv->chipset != 0x34) 2440 ret = nv20_init_compute_mem(bios); 2441 else if (dev_priv->chipset >= 0x10) 2442 ret = nv10_init_compute_mem(bios); 2443 else if (dev_priv->chipset >= 0x5) 2444 ret = nv05_init_compute_mem(bios); 2445 else 2446 ret = nv04_init_compute_mem(bios); 2447 2448 if (ret) 2449 return ret; 2450 2451 return 1; 2452} 2453 2454static int 2455init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2456{ 2457 /* 2458 * INIT_RESET opcode: 0x65 ('e') 2459 * 2460 * offset (8 bit): opcode 2461 * offset + 1 (32 bit): register 2462 * offset + 5 (32 bit): value1 2463 * offset + 9 (32 bit): value2 2464 * 2465 * Assign "value1" to "register", then assign "value2" to "register" 2466 */ 2467 2468 uint32_t reg = ROM32(bios->data[offset + 1]); 2469 uint32_t value1 = ROM32(bios->data[offset + 5]); 2470 uint32_t value2 = ROM32(bios->data[offset + 9]); 2471 uint32_t pci_nv_19, pci_nv_20; 2472 2473 /* no iexec->execute check by design */ 2474 2475 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19); 2476 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19 & ~0xf00); 2477 2478 bios_wr32(bios, reg, value1); 2479 2480 udelay(10); 2481 2482 bios_wr32(bios, reg, value2); 2483 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19); 2484 2485 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20); 2486 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */ 2487 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20); 2488 2489 return 13; 2490} 2491 2492static int 2493init_configure_mem(struct nvbios *bios, uint16_t offset, 2494 struct init_exec *iexec) 2495{ 2496 /* 2497 * INIT_CONFIGURE_MEM opcode: 0x66 ('f') 2498 * 2499 * offset (8 bit): opcode 2500 * 2501 * Equivalent to INIT_DONE on bios version 3 or greater. 2502 * For early bios versions, sets up the memory registers, using values 2503 * taken from the memory init table 2504 */ 2505 2506 /* no iexec->execute check by design */ 2507 2508 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4); 2509 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6; 2510 uint32_t reg, data; 2511 2512 if (bios->major_version > 2) 2513 return 0; 2514 2515 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd( 2516 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20); 2517 2518 if (bios->data[meminitoffs] & 1) 2519 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr; 2520 2521 for (reg = ROM32(bios->data[seqtbloffs]); 2522 reg != 0xffffffff; 2523 reg = ROM32(bios->data[seqtbloffs += 4])) { 2524 2525 switch (reg) { 2526 case NV04_PFB_PRE: 2527 data = NV04_PFB_PRE_CMD_PRECHARGE; 2528 break; 2529 case NV04_PFB_PAD: 2530 data = NV04_PFB_PAD_CKE_NORMAL; 2531 break; 2532 case NV04_PFB_REF: 2533 data = NV04_PFB_REF_CMD_REFRESH; 2534 break; 2535 default: 2536 data = ROM32(bios->data[meminitdata]); 2537 meminitdata += 4; 2538 if (data == 0xffffffff) 2539 continue; 2540 } 2541 2542 bios_wr32(bios, reg, data); 2543 } 2544 2545 return 1; 2546} 2547 2548static int 2549init_configure_clk(struct nvbios *bios, uint16_t offset, 2550 struct init_exec *iexec) 2551{ 2552 /* 2553 * INIT_CONFIGURE_CLK opcode: 0x67 ('g') 2554 * 2555 * offset (8 bit): opcode 2556 * 2557 * Equivalent to INIT_DONE on bios version 3 or greater. 2558 * For early bios versions, sets up the NVClk and MClk PLLs, using 2559 * values taken from the memory init table 2560 */ 2561 2562 /* no iexec->execute check by design */ 2563 2564 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4); 2565 int clock; 2566 2567 if (bios->major_version > 2) 2568 return 0; 2569 2570 clock = ROM16(bios->data[meminitoffs + 4]) * 10; 2571 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock); 2572 2573 clock = ROM16(bios->data[meminitoffs + 2]) * 10; 2574 if (bios->data[meminitoffs] & 1) /* DDR */ 2575 clock *= 2; 2576 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock); 2577 2578 return 1; 2579} 2580 2581static int 2582init_configure_preinit(struct nvbios *bios, uint16_t offset, 2583 struct init_exec *iexec) 2584{ 2585 /* 2586 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h') 2587 * 2588 * offset (8 bit): opcode 2589 * 2590 * Equivalent to INIT_DONE on bios version 3 or greater. 2591 * For early bios versions, does early init, loading ram and crystal 2592 * configuration from straps into CR3C 2593 */ 2594 2595 /* no iexec->execute check by design */ 2596 2597 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0); 2598 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & 0x40) >> 6; 2599 2600 if (bios->major_version > 2) 2601 return 0; 2602 2603 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, 2604 NV_CIO_CRE_SCRATCH4__INDEX, cr3c); 2605 2606 return 1; 2607} 2608 2609static int 2610init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2611{ 2612 /* 2613 * INIT_IO opcode: 0x69 ('i') 2614 * 2615 * offset (8 bit): opcode 2616 * offset + 1 (16 bit): CRTC port 2617 * offset + 3 (8 bit): mask 2618 * offset + 4 (8 bit): data 2619 * 2620 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port" 2621 */ 2622 2623 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2624 uint16_t crtcport = ROM16(bios->data[offset + 1]); 2625 uint8_t mask = bios->data[offset + 3]; 2626 uint8_t data = bios->data[offset + 4]; 2627 2628 if (!iexec->execute) 2629 return 5; 2630 2631 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n", 2632 offset, crtcport, mask, data); 2633 2634 /* 2635 * I have no idea what this does, but NVIDIA do this magic sequence 2636 * in the places where this INIT_IO happens.. 2637 */ 2638 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) { 2639 int i; 2640 2641 bios_wr32(bios, 0x614100, (bios_rd32( 2642 bios, 0x614100) & 0x0fffffff) | 0x00800000); 2643 2644 bios_wr32(bios, 0x00e18c, bios_rd32( 2645 bios, 0x00e18c) | 0x00020000); 2646 2647 bios_wr32(bios, 0x614900, (bios_rd32( 2648 bios, 0x614900) & 0x0fffffff) | 0x00800000); 2649 2650 bios_wr32(bios, 0x000200, bios_rd32( 2651 bios, 0x000200) & ~0x40000000); 2652 2653 mdelay(10); 2654 2655 bios_wr32(bios, 0x00e18c, bios_rd32( 2656 bios, 0x00e18c) & ~0x00020000); 2657 2658 bios_wr32(bios, 0x000200, bios_rd32( 2659 bios, 0x000200) | 0x40000000); 2660 2661 bios_wr32(bios, 0x614100, 0x00800018); 2662 bios_wr32(bios, 0x614900, 0x00800018); 2663 2664 mdelay(10); 2665 2666 bios_wr32(bios, 0x614100, 0x10000018); 2667 bios_wr32(bios, 0x614900, 0x10000018); 2668 2669 for (i = 0; i < 3; i++) 2670 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32( 2671 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0); 2672 2673 for (i = 0; i < 2; i++) 2674 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32( 2675 bios, 0x614300 + (i*0x800)) & 0xfffff0f0); 2676 2677 for (i = 0; i < 3; i++) 2678 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32( 2679 bios, 0x614380 + (i*0x800)) & 0xfffff0f0); 2680 2681 for (i = 0; i < 2; i++) 2682 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32( 2683 bios, 0x614200 + (i*0x800)) & 0xfffffff0); 2684 2685 for (i = 0; i < 2; i++) 2686 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32( 2687 bios, 0x614108 + (i*0x800)) & 0x0fffffff); 2688 return 5; 2689 } 2690 2691 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) | 2692 data); 2693 return 5; 2694} 2695 2696static int 2697init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2698{ 2699 /* 2700 * INIT_SUB opcode: 0x6B ('k') 2701 * 2702 * offset (8 bit): opcode 2703 * offset + 1 (8 bit): script number 2704 * 2705 * Execute script number "script number", as a subroutine 2706 */ 2707 2708 uint8_t sub = bios->data[offset + 1]; 2709 2710 if (!iexec->execute) 2711 return 2; 2712 2713 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub); 2714 2715 parse_init_table(bios, 2716 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]), 2717 iexec); 2718 2719 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub); 2720 2721 return 2; 2722} 2723 2724static int 2725init_ram_condition(struct nvbios *bios, uint16_t offset, 2726 struct init_exec *iexec) 2727{ 2728 /* 2729 * INIT_RAM_CONDITION opcode: 0x6D ('m') 2730 * 2731 * offset (8 bit): opcode 2732 * offset + 1 (8 bit): mask 2733 * offset + 2 (8 bit): cmpval 2734 * 2735 * Test if (NV04_PFB_BOOT_0 & "mask") equals "cmpval". 2736 * If condition not met skip subsequent opcodes until condition is 2737 * inverted (INIT_NOT), or we hit INIT_RESUME 2738 */ 2739 2740 uint8_t mask = bios->data[offset + 1]; 2741 uint8_t cmpval = bios->data[offset + 2]; 2742 uint8_t data; 2743 2744 if (!iexec->execute) 2745 return 3; 2746 2747 data = bios_rd32(bios, NV04_PFB_BOOT_0) & mask; 2748 2749 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n", 2750 offset, data, cmpval); 2751 2752 if (data == cmpval) 2753 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 2754 else { 2755 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 2756 iexec->execute = false; 2757 } 2758 2759 return 3; 2760} 2761 2762static int 2763init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2764{ 2765 /* 2766 * INIT_NV_REG opcode: 0x6E ('n') 2767 * 2768 * offset (8 bit): opcode 2769 * offset + 1 (32 bit): register 2770 * offset + 5 (32 bit): mask 2771 * offset + 9 (32 bit): data 2772 * 2773 * Assign ((REGVAL("register") & "mask") | "data") to "register" 2774 */ 2775 2776 uint32_t reg = ROM32(bios->data[offset + 1]); 2777 uint32_t mask = ROM32(bios->data[offset + 5]); 2778 uint32_t data = ROM32(bios->data[offset + 9]); 2779 2780 if (!iexec->execute) 2781 return 13; 2782 2783 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n", 2784 offset, reg, mask, data); 2785 2786 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data); 2787 2788 return 13; 2789} 2790 2791static int 2792init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2793{ 2794 /* 2795 * INIT_MACRO opcode: 0x6F ('o') 2796 * 2797 * offset (8 bit): opcode 2798 * offset + 1 (8 bit): macro number 2799 * 2800 * Look up macro index "macro number" in the macro index table. 2801 * The macro index table entry has 1 byte for the index in the macro 2802 * table, and 1 byte for the number of times to repeat the macro. 2803 * The macro table entry has 4 bytes for the register address and 2804 * 4 bytes for the value to write to that register 2805 */ 2806 2807 uint8_t macro_index_tbl_idx = bios->data[offset + 1]; 2808 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE); 2809 uint8_t macro_tbl_idx = bios->data[tmp]; 2810 uint8_t count = bios->data[tmp + 1]; 2811 uint32_t reg, data; 2812 int i; 2813 2814 if (!iexec->execute) 2815 return 2; 2816 2817 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, " 2818 "Count: 0x%02X\n", 2819 offset, macro_index_tbl_idx, macro_tbl_idx, count); 2820 2821 for (i = 0; i < count; i++) { 2822 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE; 2823 2824 reg = ROM32(bios->data[macroentryptr]); 2825 data = ROM32(bios->data[macroentryptr + 4]); 2826 2827 bios_wr32(bios, reg, data); 2828 } 2829 2830 return 2; 2831} 2832 2833static int 2834init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2835{ 2836 /* 2837 * INIT_DONE opcode: 0x71 ('q') 2838 * 2839 * offset (8 bit): opcode 2840 * 2841 * End the current script 2842 */ 2843 2844 /* mild retval abuse to stop parsing this table */ 2845 return 0; 2846} 2847 2848static int 2849init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2850{ 2851 /* 2852 * INIT_RESUME opcode: 0x72 ('r') 2853 * 2854 * offset (8 bit): opcode 2855 * 2856 * End the current execute / no-execute condition 2857 */ 2858 2859 if (iexec->execute) 2860 return 1; 2861 2862 iexec->execute = true; 2863 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset); 2864 2865 return 1; 2866} 2867 2868static int 2869init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2870{ 2871 /* 2872 * INIT_TIME opcode: 0x74 ('t') 2873 * 2874 * offset (8 bit): opcode 2875 * offset + 1 (16 bit): time 2876 * 2877 * Sleep for "time" microseconds. 2878 */ 2879 2880 unsigned time = ROM16(bios->data[offset + 1]); 2881 2882 if (!iexec->execute) 2883 return 3; 2884 2885 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n", 2886 offset, time); 2887 2888 if (time < 1000) 2889 udelay(time); 2890 else 2891 mdelay((time + 900) / 1000); 2892 2893 return 3; 2894} 2895 2896static int 2897init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2898{ 2899 /* 2900 * INIT_CONDITION opcode: 0x75 ('u') 2901 * 2902 * offset (8 bit): opcode 2903 * offset + 1 (8 bit): condition number 2904 * 2905 * Check condition "condition number" in the condition table. 2906 * If condition not met skip subsequent opcodes until condition is 2907 * inverted (INIT_NOT), or we hit INIT_RESUME 2908 */ 2909 2910 uint8_t cond = bios->data[offset + 1]; 2911 2912 if (!iexec->execute) 2913 return 2; 2914 2915 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond); 2916 2917 if (bios_condition_met(bios, offset, cond)) 2918 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 2919 else { 2920 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 2921 iexec->execute = false; 2922 } 2923 2924 return 2; 2925} 2926 2927static int 2928init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2929{ 2930 /* 2931 * INIT_IO_CONDITION opcode: 0x76 2932 * 2933 * offset (8 bit): opcode 2934 * offset + 1 (8 bit): condition number 2935 * 2936 * Check condition "condition number" in the io condition table. 2937 * If condition not met skip subsequent opcodes until condition is 2938 * inverted (INIT_NOT), or we hit INIT_RESUME 2939 */ 2940 2941 uint8_t cond = bios->data[offset + 1]; 2942 2943 if (!iexec->execute) 2944 return 2; 2945 2946 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond); 2947 2948 if (io_condition_met(bios, offset, cond)) 2949 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 2950 else { 2951 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 2952 iexec->execute = false; 2953 } 2954 2955 return 2; 2956} 2957 2958static int 2959init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2960{ 2961 /* 2962 * INIT_INDEX_IO opcode: 0x78 ('x') 2963 * 2964 * offset (8 bit): opcode 2965 * offset + 1 (16 bit): CRTC port 2966 * offset + 3 (8 bit): CRTC index 2967 * offset + 4 (8 bit): mask 2968 * offset + 5 (8 bit): data 2969 * 2970 * Read value at index "CRTC index" on "CRTC port", AND with "mask", 2971 * OR with "data", write-back 2972 */ 2973 2974 uint16_t crtcport = ROM16(bios->data[offset + 1]); 2975 uint8_t crtcindex = bios->data[offset + 3]; 2976 uint8_t mask = bios->data[offset + 4]; 2977 uint8_t data = bios->data[offset + 5]; 2978 uint8_t value; 2979 2980 if (!iexec->execute) 2981 return 6; 2982 2983 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 2984 "Data: 0x%02X\n", 2985 offset, crtcport, crtcindex, mask, data); 2986 2987 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data; 2988 bios_idxprt_wr(bios, crtcport, crtcindex, value); 2989 2990 return 6; 2991} 2992 2993static int 2994init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2995{ 2996 /* 2997 * INIT_PLL opcode: 0x79 ('y') 2998 * 2999 * offset (8 bit): opcode 3000 * offset + 1 (32 bit): register 3001 * offset + 5 (16 bit): freq 3002 * 3003 * Set PLL register "register" to coefficients for frequency (10kHz) 3004 * "freq" 3005 */ 3006 3007 uint32_t reg = ROM32(bios->data[offset + 1]); 3008 uint16_t freq = ROM16(bios->data[offset + 5]); 3009 3010 if (!iexec->execute) 3011 return 7; 3012 3013 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq); 3014 3015 setPLL(bios, reg, freq * 10); 3016 3017 return 7; 3018} 3019 3020static int 3021init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3022{ 3023 /* 3024 * INIT_ZM_REG opcode: 0x7A ('z') 3025 * 3026 * offset (8 bit): opcode 3027 * offset + 1 (32 bit): register 3028 * offset + 5 (32 bit): value 3029 * 3030 * Assign "value" to "register" 3031 */ 3032 3033 uint32_t reg = ROM32(bios->data[offset + 1]); 3034 uint32_t value = ROM32(bios->data[offset + 5]); 3035 3036 if (!iexec->execute) 3037 return 9; 3038 3039 if (reg == 0x000200) 3040 value |= 1; 3041 3042 bios_wr32(bios, reg, value); 3043 3044 return 9; 3045} 3046 3047static int 3048init_ram_restrict_pll(struct nvbios *bios, uint16_t offset, 3049 struct init_exec *iexec) 3050{ 3051 /* 3052 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('') 3053 * 3054 * offset (8 bit): opcode 3055 * offset + 1 (8 bit): PLL type 3056 * offset + 2 (32 bit): frequency 0 3057 * 3058 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at 3059 * ram_restrict_table_ptr. The value read from there is used to select 3060 * a frequency from the table starting at 'frequency 0' to be 3061 * programmed into the PLL corresponding to 'type'. 3062 * 3063 * The PLL limits table on cards using this opcode has a mapping of 3064 * 'type' to the relevant registers. 3065 */ 3066 3067 struct drm_device *dev = bios->dev; 3068 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2; 3069 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap]; 3070 uint8_t type = bios->data[offset + 1]; 3071 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]); 3072 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry; 3073 int len = 2 + bios->ram_restrict_group_count * 4; 3074 int i; 3075 3076 if (!iexec->execute) 3077 return len; 3078 3079 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) { 3080 NV_ERROR(dev, "PLL limits table not version 3.x\n"); 3081 return len; /* deliberate, allow default clocks to remain */ 3082 } 3083 3084 entry = pll_limits + pll_limits[1]; 3085 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) { 3086 if (entry[0] == type) { 3087 uint32_t reg = ROM32(entry[3]); 3088 3089 BIOSLOG(bios, "0x%04X: " 3090 "Type %02x Reg 0x%08x Freq %dKHz\n", 3091 offset, type, reg, freq); 3092 3093 setPLL(bios, reg, freq); 3094 return len; 3095 } 3096 } 3097 3098 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type); 3099 return len; 3100} 3101 3102static int 3103init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3104{ 3105 /* 3106 * INIT_8C opcode: 0x8C ('') 3107 * 3108 * NOP so far.... 3109 * 3110 */ 3111 3112 return 1; 3113} 3114 3115static int 3116init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3117{ 3118 /* 3119 * INIT_8D opcode: 0x8D ('') 3120 * 3121 * NOP so far.... 3122 * 3123 */ 3124 3125 return 1; 3126} 3127 3128static int 3129init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3130{ 3131 /* 3132 * INIT_GPIO opcode: 0x8E ('') 3133 * 3134 * offset (8 bit): opcode 3135 * 3136 * Loop over all entries in the DCB GPIO table, and initialise 3137 * each GPIO according to various values listed in each entry 3138 */ 3139 3140 if (iexec->execute && bios->execute) 3141 nouveau_gpio_reset(bios->dev); 3142 3143 return 1; 3144} 3145 3146static int 3147init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset, 3148 struct init_exec *iexec) 3149{ 3150 /* 3151 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('') 3152 * 3153 * offset (8 bit): opcode 3154 * offset + 1 (32 bit): reg 3155 * offset + 5 (8 bit): regincrement 3156 * offset + 6 (8 bit): count 3157 * offset + 7 (32 bit): value 1,1 3158 * ... 3159 * 3160 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at 3161 * ram_restrict_table_ptr. The value read from here is 'n', and 3162 * "value 1,n" gets written to "reg". This repeats "count" times and on 3163 * each iteration 'm', "reg" increases by "regincrement" and 3164 * "value m,n" is used. The extent of n is limited by a number read 3165 * from the 'M' BIT table, herein called "blocklen" 3166 */ 3167 3168 uint32_t reg = ROM32(bios->data[offset + 1]); 3169 uint8_t regincrement = bios->data[offset + 5]; 3170 uint8_t count = bios->data[offset + 6]; 3171 uint32_t strap_ramcfg, data; 3172 /* previously set by 'M' BIT table */ 3173 uint16_t blocklen = bios->ram_restrict_group_count * 4; 3174 int len = 7 + count * blocklen; 3175 uint8_t index; 3176 int i; 3177 3178 /* critical! to know the length of the opcode */; 3179 if (!blocklen) { 3180 NV_ERROR(bios->dev, 3181 "0x%04X: Zero block length - has the M table " 3182 "been parsed?\n", offset); 3183 return -EINVAL; 3184 } 3185 3186 if (!iexec->execute) 3187 return len; 3188 3189 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf; 3190 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg]; 3191 3192 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, " 3193 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n", 3194 offset, reg, regincrement, count, strap_ramcfg, index); 3195 3196 for (i = 0; i < count; i++) { 3197 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]); 3198 3199 bios_wr32(bios, reg, data); 3200 3201 reg += regincrement; 3202 } 3203 3204 return len; 3205} 3206 3207static int 3208init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3209{ 3210 /* 3211 * INIT_COPY_ZM_REG opcode: 0x90 ('') 3212 * 3213 * offset (8 bit): opcode 3214 * offset + 1 (32 bit): src reg 3215 * offset + 5 (32 bit): dst reg 3216 * 3217 * Put contents of "src reg" into "dst reg" 3218 */ 3219 3220 uint32_t srcreg = ROM32(bios->data[offset + 1]); 3221 uint32_t dstreg = ROM32(bios->data[offset + 5]); 3222 3223 if (!iexec->execute) 3224 return 9; 3225 3226 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg)); 3227 3228 return 9; 3229} 3230 3231static int 3232init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset, 3233 struct init_exec *iexec) 3234{ 3235 /* 3236 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('') 3237 * 3238 * offset (8 bit): opcode 3239 * offset + 1 (32 bit): dst reg 3240 * offset + 5 (8 bit): count 3241 * offset + 6 (32 bit): data 1 3242 * ... 3243 * 3244 * For each of "count" values write "data n" to "dst reg" 3245 */ 3246 3247 uint32_t reg = ROM32(bios->data[offset + 1]); 3248 uint8_t count = bios->data[offset + 5]; 3249 int len = 6 + count * 4; 3250 int i; 3251 3252 if (!iexec->execute) 3253 return len; 3254 3255 for (i = 0; i < count; i++) { 3256 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]); 3257 bios_wr32(bios, reg, data); 3258 } 3259 3260 return len; 3261} 3262 3263static int 3264init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3265{ 3266 /* 3267 * INIT_RESERVED opcode: 0x92 ('') 3268 * 3269 * offset (8 bit): opcode 3270 * 3271 * Seemingly does nothing 3272 */ 3273 3274 return 1; 3275} 3276 3277static int 3278init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3279{ 3280 /* 3281 * INIT_96 opcode: 0x96 ('') 3282 * 3283 * offset (8 bit): opcode 3284 * offset + 1 (32 bit): sreg 3285 * offset + 5 (8 bit): sshift 3286 * offset + 6 (8 bit): smask 3287 * offset + 7 (8 bit): index 3288 * offset + 8 (32 bit): reg 3289 * offset + 12 (32 bit): mask 3290 * offset + 16 (8 bit): shift 3291 * 3292 */ 3293 3294 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2); 3295 uint32_t reg = ROM32(bios->data[offset + 8]); 3296 uint32_t mask = ROM32(bios->data[offset + 12]); 3297 uint32_t val; 3298 3299 val = bios_rd32(bios, ROM32(bios->data[offset + 1])); 3300 if (bios->data[offset + 5] < 0x80) 3301 val >>= bios->data[offset + 5]; 3302 else 3303 val <<= (0x100 - bios->data[offset + 5]); 3304 val &= bios->data[offset + 6]; 3305 3306 val = bios->data[ROM16(bios->data[xlatptr]) + val]; 3307 val <<= bios->data[offset + 16]; 3308 3309 if (!iexec->execute) 3310 return 17; 3311 3312 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val); 3313 return 17; 3314} 3315 3316static int 3317init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3318{ 3319 /* 3320 * INIT_97 opcode: 0x97 ('') 3321 * 3322 * offset (8 bit): opcode 3323 * offset + 1 (32 bit): register 3324 * offset + 5 (32 bit): mask 3325 * offset + 9 (32 bit): value 3326 * 3327 * Adds "value" to "register" preserving the fields specified 3328 * by "mask" 3329 */ 3330 3331 uint32_t reg = ROM32(bios->data[offset + 1]); 3332 uint32_t mask = ROM32(bios->data[offset + 5]); 3333 uint32_t add = ROM32(bios->data[offset + 9]); 3334 uint32_t val; 3335 3336 val = bios_rd32(bios, reg); 3337 val = (val & mask) | ((val + add) & ~mask); 3338 3339 if (!iexec->execute) 3340 return 13; 3341 3342 bios_wr32(bios, reg, val); 3343 return 13; 3344} 3345 3346static int 3347init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3348{ 3349 /* 3350 * INIT_AUXCH opcode: 0x98 ('') 3351 * 3352 * offset (8 bit): opcode 3353 * offset + 1 (32 bit): address 3354 * offset + 5 (8 bit): count 3355 * offset + 6 (8 bit): mask 0 3356 * offset + 7 (8 bit): data 0 3357 * ... 3358 * 3359 */ 3360 3361 struct drm_device *dev = bios->dev; 3362 struct nouveau_i2c_chan *auxch; 3363 uint32_t addr = ROM32(bios->data[offset + 1]); 3364 uint8_t count = bios->data[offset + 5]; 3365 int len = 6 + count * 2; 3366 int ret, i; 3367 3368 if (!bios->display.output) { 3369 NV_ERROR(dev, "INIT_AUXCH: no active output\n"); 3370 return len; 3371 } 3372 3373 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index); 3374 if (!auxch) { 3375 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n", 3376 bios->display.output->i2c_index); 3377 return len; 3378 } 3379 3380 if (!iexec->execute) 3381 return len; 3382 3383 offset += 6; 3384 for (i = 0; i < count; i++, offset += 2) { 3385 uint8_t data; 3386 3387 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1); 3388 if (ret) { 3389 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret); 3390 return len; 3391 } 3392 3393 data &= bios->data[offset + 0]; 3394 data |= bios->data[offset + 1]; 3395 3396 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1); 3397 if (ret) { 3398 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret); 3399 return len; 3400 } 3401 } 3402 3403 return len; 3404} 3405 3406static int 3407init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3408{ 3409 /* 3410 * INIT_ZM_AUXCH opcode: 0x99 ('') 3411 * 3412 * offset (8 bit): opcode 3413 * offset + 1 (32 bit): address 3414 * offset + 5 (8 bit): count 3415 * offset + 6 (8 bit): data 0 3416 * ... 3417 * 3418 */ 3419 3420 struct drm_device *dev = bios->dev; 3421 struct nouveau_i2c_chan *auxch; 3422 uint32_t addr = ROM32(bios->data[offset + 1]); 3423 uint8_t count = bios->data[offset + 5]; 3424 int len = 6 + count; 3425 int ret, i; 3426 3427 if (!bios->display.output) { 3428 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n"); 3429 return len; 3430 } 3431 3432 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index); 3433 if (!auxch) { 3434 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n", 3435 bios->display.output->i2c_index); 3436 return len; 3437 } 3438 3439 if (!iexec->execute) 3440 return len; 3441 3442 offset += 6; 3443 for (i = 0; i < count; i++, offset++) { 3444 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1); 3445 if (ret) { 3446 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret); 3447 return len; 3448 } 3449 } 3450 3451 return len; 3452} 3453 3454static int 3455init_i2c_long_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3456{ 3457 /* 3458 * INIT_I2C_LONG_IF opcode: 0x9A ('') 3459 * 3460 * offset (8 bit): opcode 3461 * offset + 1 (8 bit): DCB I2C table entry index 3462 * offset + 2 (8 bit): I2C slave address 3463 * offset + 3 (16 bit): I2C register 3464 * offset + 5 (8 bit): mask 3465 * offset + 6 (8 bit): data 3466 * 3467 * Read the register given by "I2C register" on the device addressed 3468 * by "I2C slave address" on the I2C bus given by "DCB I2C table 3469 * entry index". Compare the result AND "mask" to "data". 3470 * If they're not equal, skip subsequent opcodes until condition is 3471 * inverted (INIT_NOT), or we hit INIT_RESUME 3472 */ 3473 3474 uint8_t i2c_index = bios->data[offset + 1]; 3475 uint8_t i2c_address = bios->data[offset + 2] >> 1; 3476 uint8_t reglo = bios->data[offset + 3]; 3477 uint8_t reghi = bios->data[offset + 4]; 3478 uint8_t mask = bios->data[offset + 5]; 3479 uint8_t data = bios->data[offset + 6]; 3480 struct nouveau_i2c_chan *chan; 3481 uint8_t buf0[2] = { reghi, reglo }; 3482 uint8_t buf1[1]; 3483 struct i2c_msg msg[2] = { 3484 { i2c_address, 0, 1, buf0 }, 3485 { i2c_address, I2C_M_RD, 1, buf1 }, 3486 }; 3487 int ret; 3488 3489 /* no execute check by design */ 3490 3491 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n", 3492 offset, i2c_index, i2c_address); 3493 3494 chan = init_i2c_device_find(bios->dev, i2c_index); 3495 if (!chan) 3496 return -ENODEV; 3497 3498 3499 ret = i2c_transfer(&chan->adapter, msg, 2); 3500 if (ret < 0) { 3501 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: [no device], " 3502 "Mask: 0x%02X, Data: 0x%02X\n", 3503 offset, reghi, reglo, mask, data); 3504 iexec->execute = 0; 3505 return 7; 3506 } 3507 3508 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: 0x%02X, " 3509 "Mask: 0x%02X, Data: 0x%02X\n", 3510 offset, reghi, reglo, buf1[0], mask, data); 3511 3512 iexec->execute = ((buf1[0] & mask) == data); 3513 3514 return 7; 3515} 3516 3517static struct init_tbl_entry itbl_entry[] = { 3518 /* command name , id , length , offset , mult , command handler */ 3519 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */ 3520 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog }, 3521 { "INIT_REPEAT" , 0x33, init_repeat }, 3522 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll }, 3523 { "INIT_END_REPEAT" , 0x36, init_end_repeat }, 3524 { "INIT_COPY" , 0x37, init_copy }, 3525 { "INIT_NOT" , 0x38, init_not }, 3526 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition }, 3527 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition }, 3528 { "INIT_OP_3B" , 0x3B, init_op_3b }, 3529 { "INIT_OP_3C" , 0x3C, init_op_3c }, 3530 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched }, 3531 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 }, 3532 { "INIT_PLL2" , 0x4B, init_pll2 }, 3533 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte }, 3534 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte }, 3535 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c }, 3536 { "INIT_TMDS" , 0x4F, init_tmds }, 3537 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group }, 3538 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch }, 3539 { "INIT_CR" , 0x52, init_cr }, 3540 { "INIT_ZM_CR" , 0x53, init_zm_cr }, 3541 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group }, 3542 { "INIT_CONDITION_TIME" , 0x56, init_condition_time }, 3543 { "INIT_LTIME" , 0x57, init_ltime }, 3544 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence }, 3545 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */ 3546 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct }, 3547 { "INIT_JUMP" , 0x5C, init_jump }, 3548 { "INIT_I2C_IF" , 0x5E, init_i2c_if }, 3549 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg }, 3550 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io }, 3551 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem }, 3552 { "INIT_RESET" , 0x65, init_reset }, 3553 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem }, 3554 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk }, 3555 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit }, 3556 { "INIT_IO" , 0x69, init_io }, 3557 { "INIT_SUB" , 0x6B, init_sub }, 3558 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition }, 3559 { "INIT_NV_REG" , 0x6E, init_nv_reg }, 3560 { "INIT_MACRO" , 0x6F, init_macro }, 3561 { "INIT_DONE" , 0x71, init_done }, 3562 { "INIT_RESUME" , 0x72, init_resume }, 3563 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */ 3564 { "INIT_TIME" , 0x74, init_time }, 3565 { "INIT_CONDITION" , 0x75, init_condition }, 3566 { "INIT_IO_CONDITION" , 0x76, init_io_condition }, 3567 { "INIT_INDEX_IO" , 0x78, init_index_io }, 3568 { "INIT_PLL" , 0x79, init_pll }, 3569 { "INIT_ZM_REG" , 0x7A, init_zm_reg }, 3570 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll }, 3571 { "INIT_8C" , 0x8C, init_8c }, 3572 { "INIT_8D" , 0x8D, init_8d }, 3573 { "INIT_GPIO" , 0x8E, init_gpio }, 3574 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group }, 3575 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg }, 3576 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched }, 3577 { "INIT_RESERVED" , 0x92, init_reserved }, 3578 { "INIT_96" , 0x96, init_96 }, 3579 { "INIT_97" , 0x97, init_97 }, 3580 { "INIT_AUXCH" , 0x98, init_auxch }, 3581 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch }, 3582 { "INIT_I2C_LONG_IF" , 0x9A, init_i2c_long_if }, 3583 { NULL , 0 , NULL } 3584}; 3585 3586#define MAX_TABLE_OPS 1000 3587 3588static int 3589parse_init_table(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3590{ 3591 /* 3592 * Parses all commands in an init table. 3593 * 3594 * We start out executing all commands found in the init table. Some 3595 * opcodes may change the status of iexec->execute to SKIP, which will 3596 * cause the following opcodes to perform no operation until the value 3597 * is changed back to EXECUTE. 3598 */ 3599 3600 int count = 0, i, ret; 3601 uint8_t id; 3602 3603 /* catch NULL script pointers */ 3604 if (offset == 0) 3605 return 0; 3606 3607 /* 3608 * Loop until INIT_DONE causes us to break out of the loop 3609 * (or until offset > bios length just in case... ) 3610 * (and no more than MAX_TABLE_OPS iterations, just in case... ) 3611 */ 3612 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) { 3613 id = bios->data[offset]; 3614 3615 /* Find matching id in itbl_entry */ 3616 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++) 3617 ; 3618 3619 if (!itbl_entry[i].name) { 3620 NV_ERROR(bios->dev, 3621 "0x%04X: Init table command not found: " 3622 "0x%02X\n", offset, id); 3623 return -ENOENT; 3624 } 3625 3626 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset, 3627 itbl_entry[i].id, itbl_entry[i].name); 3628 3629 /* execute eventual command handler */ 3630 ret = (*itbl_entry[i].handler)(bios, offset, iexec); 3631 if (ret < 0) { 3632 NV_ERROR(bios->dev, "0x%04X: Failed parsing init " 3633 "table opcode: %s %d\n", offset, 3634 itbl_entry[i].name, ret); 3635 } 3636 3637 if (ret <= 0) 3638 break; 3639 3640 /* 3641 * Add the offset of the current command including all data 3642 * of that command. The offset will then be pointing on the 3643 * next op code. 3644 */ 3645 offset += ret; 3646 } 3647 3648 if (offset >= bios->length) 3649 NV_WARN(bios->dev, 3650 "Offset 0x%04X greater than known bios image length. " 3651 "Corrupt image?\n", offset); 3652 if (count >= MAX_TABLE_OPS) 3653 NV_WARN(bios->dev, 3654 "More than %d opcodes to a table is unlikely, " 3655 "is the bios image corrupt?\n", MAX_TABLE_OPS); 3656 3657 return 0; 3658} 3659 3660static void 3661parse_init_tables(struct nvbios *bios) 3662{ 3663 /* Loops and calls parse_init_table() for each present table. */ 3664 3665 int i = 0; 3666 uint16_t table; 3667 struct init_exec iexec = {true, false}; 3668 3669 if (bios->old_style_init) { 3670 if (bios->init_script_tbls_ptr) 3671 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec); 3672 if (bios->extra_init_script_tbl_ptr) 3673 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec); 3674 3675 return; 3676 } 3677 3678 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) { 3679 NV_INFO(bios->dev, 3680 "Parsing VBIOS init table %d at offset 0x%04X\n", 3681 i / 2, table); 3682 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table); 3683 3684 parse_init_table(bios, table, &iexec); 3685 i += 2; 3686 } 3687} 3688 3689static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk) 3690{ 3691 int compare_record_len, i = 0; 3692 uint16_t compareclk, scriptptr = 0; 3693 3694 if (bios->major_version < 5) /* pre BIT */ 3695 compare_record_len = 3; 3696 else 3697 compare_record_len = 4; 3698 3699 do { 3700 compareclk = ROM16(bios->data[clktable + compare_record_len * i]); 3701 if (pxclk >= compareclk * 10) { 3702 if (bios->major_version < 5) { 3703 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i]; 3704 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]); 3705 } else 3706 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]); 3707 break; 3708 } 3709 i++; 3710 } while (compareclk); 3711 3712 return scriptptr; 3713} 3714 3715static void 3716run_digital_op_script(struct drm_device *dev, uint16_t scriptptr, 3717 struct dcb_entry *dcbent, int head, bool dl) 3718{ 3719 struct drm_nouveau_private *dev_priv = dev->dev_private; 3720 struct nvbios *bios = &dev_priv->vbios; 3721 struct init_exec iexec = {true, false}; 3722 3723 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n", 3724 scriptptr); 3725 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44, 3726 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA); 3727 /* note: if dcb entries have been merged, index may be misleading */ 3728 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index); 3729 parse_init_table(bios, scriptptr, &iexec); 3730 3731 nv04_dfp_bind_head(dev, dcbent, head, dl); 3732} 3733 3734static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script) 3735{ 3736 struct drm_nouveau_private *dev_priv = dev->dev_private; 3737 struct nvbios *bios = &dev_priv->vbios; 3738 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0); 3739 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]); 3740 3741 if (!bios->fp.xlated_entry || !sub || !scriptofs) 3742 return -EINVAL; 3743 3744 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link); 3745 3746 if (script == LVDS_PANEL_OFF) { 3747 /* off-on delay in ms */ 3748 mdelay(ROM16(bios->data[bios->fp.xlated_entry + 7])); 3749 } 3750#ifdef __powerpc__ 3751 /* Powerbook specific quirks */ 3752 if (script == LVDS_RESET && 3753 (dev->pci_device == 0x0179 || dev->pci_device == 0x0189 || 3754 dev->pci_device == 0x0329)) 3755 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72); 3756#endif 3757 3758 return 0; 3759} 3760 3761static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk) 3762{ 3763 /* 3764 * The BIT LVDS table's header has the information to setup the 3765 * necessary registers. Following the standard 4 byte header are: 3766 * A bitmask byte and a dual-link transition pxclk value for use in 3767 * selecting the init script when not using straps; 4 script pointers 3768 * for panel power, selected by output and on/off; and 8 table pointers 3769 * for panel init, the needed one determined by output, and bits in the 3770 * conf byte. These tables are similar to the TMDS tables, consisting 3771 * of a list of pxclks and script pointers. 3772 */ 3773 struct drm_nouveau_private *dev_priv = dev->dev_private; 3774 struct nvbios *bios = &dev_priv->vbios; 3775 unsigned int outputset = (dcbent->or == 4) ? 1 : 0; 3776 uint16_t scriptptr = 0, clktable; 3777 3778 /* 3779 * For now we assume version 3.0 table - g80 support will need some 3780 * changes 3781 */ 3782 3783 switch (script) { 3784 case LVDS_INIT: 3785 return -ENOSYS; 3786 case LVDS_BACKLIGHT_ON: 3787 case LVDS_PANEL_ON: 3788 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]); 3789 break; 3790 case LVDS_BACKLIGHT_OFF: 3791 case LVDS_PANEL_OFF: 3792 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]); 3793 break; 3794 case LVDS_RESET: 3795 clktable = bios->fp.lvdsmanufacturerpointer + 15; 3796 if (dcbent->or == 4) 3797 clktable += 8; 3798 3799 if (dcbent->lvdsconf.use_straps_for_mode) { 3800 if (bios->fp.dual_link) 3801 clktable += 4; 3802 if (bios->fp.if_is_24bit) 3803 clktable += 2; 3804 } else { 3805 /* using EDID */ 3806 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1; 3807 3808 if (bios->fp.dual_link) { 3809 clktable += 4; 3810 cmpval_24bit <<= 1; 3811 } 3812 3813 if (bios->fp.strapless_is_24bit & cmpval_24bit) 3814 clktable += 2; 3815 } 3816 3817 clktable = ROM16(bios->data[clktable]); 3818 if (!clktable) { 3819 NV_ERROR(dev, "Pixel clock comparison table not found\n"); 3820 return -ENOENT; 3821 } 3822 scriptptr = clkcmptable(bios, clktable, pxclk); 3823 } 3824 3825 if (!scriptptr) { 3826 NV_ERROR(dev, "LVDS output init script not found\n"); 3827 return -ENOENT; 3828 } 3829 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link); 3830 3831 return 0; 3832} 3833 3834int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk) 3835{ 3836 /* 3837 * LVDS operations are multiplexed in an effort to present a single API 3838 * which works with two vastly differing underlying structures. 3839 * This acts as the demux 3840 */ 3841 3842 struct drm_nouveau_private *dev_priv = dev->dev_private; 3843 struct nvbios *bios = &dev_priv->vbios; 3844 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer]; 3845 uint32_t sel_clk_binding, sel_clk; 3846 int ret; 3847 3848 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver || 3849 (lvds_ver >= 0x30 && script == LVDS_INIT)) 3850 return 0; 3851 3852 if (!bios->fp.lvds_init_run) { 3853 bios->fp.lvds_init_run = true; 3854 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk); 3855 } 3856 3857 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change) 3858 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk); 3859 if (script == LVDS_RESET && bios->fp.power_off_for_reset) 3860 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk); 3861 3862 NV_TRACE(dev, "Calling LVDS script %d:\n", script); 3863 3864 /* don't let script change pll->head binding */ 3865 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000; 3866 3867 if (lvds_ver < 0x30) 3868 ret = call_lvds_manufacturer_script(dev, dcbent, head, script); 3869 else 3870 ret = run_lvds_table(dev, dcbent, head, script, pxclk); 3871 3872 bios->fp.last_script_invoc = (script << 1 | head); 3873 3874 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; 3875 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); 3876 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */ 3877 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0); 3878 3879 return ret; 3880} 3881 3882struct lvdstableheader { 3883 uint8_t lvds_ver, headerlen, recordlen; 3884}; 3885 3886static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth) 3887{ 3888 /* 3889 * BMP version (0xa) LVDS table has a simple header of version and 3890 * record length. The BIT LVDS table has the typical BIT table header: 3891 * version byte, header length byte, record length byte, and a byte for 3892 * the maximum number of records that can be held in the table. 3893 */ 3894 3895 uint8_t lvds_ver, headerlen, recordlen; 3896 3897 memset(lth, 0, sizeof(struct lvdstableheader)); 3898 3899 if (bios->fp.lvdsmanufacturerpointer == 0x0) { 3900 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n"); 3901 return -EINVAL; 3902 } 3903 3904 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer]; 3905 3906 switch (lvds_ver) { 3907 case 0x0a: /* pre NV40 */ 3908 headerlen = 2; 3909 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 3910 break; 3911 case 0x30: /* NV4x */ 3912 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 3913 if (headerlen < 0x1f) { 3914 NV_ERROR(dev, "LVDS table header not understood\n"); 3915 return -EINVAL; 3916 } 3917 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2]; 3918 break; 3919 case 0x40: /* G80/G90 */ 3920 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 3921 if (headerlen < 0x7) { 3922 NV_ERROR(dev, "LVDS table header not understood\n"); 3923 return -EINVAL; 3924 } 3925 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2]; 3926 break; 3927 default: 3928 NV_ERROR(dev, 3929 "LVDS table revision %d.%d not currently supported\n", 3930 lvds_ver >> 4, lvds_ver & 0xf); 3931 return -ENOSYS; 3932 } 3933 3934 lth->lvds_ver = lvds_ver; 3935 lth->headerlen = headerlen; 3936 lth->recordlen = recordlen; 3937 3938 return 0; 3939} 3940 3941static int 3942get_fp_strap(struct drm_device *dev, struct nvbios *bios) 3943{ 3944 struct drm_nouveau_private *dev_priv = dev->dev_private; 3945 3946 /* 3947 * The fp strap is normally dictated by the "User Strap" in 3948 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the 3949 * Internal_Flags struct at 0x48 is set, the user strap gets overriden 3950 * by the PCI subsystem ID during POST, but not before the previous user 3951 * strap has been committed to CR58 for CR57=0xf on head A, which may be 3952 * read and used instead 3953 */ 3954 3955 if (bios->major_version < 5 && bios->data[0x48] & 0x4) 3956 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf; 3957 3958 if (dev_priv->card_type >= NV_50) 3959 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf; 3960 else 3961 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf; 3962} 3963 3964static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios) 3965{ 3966 uint8_t *fptable; 3967 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex; 3968 int ret, ofs, fpstrapping; 3969 struct lvdstableheader lth; 3970 3971 if (bios->fp.fptablepointer == 0x0) { 3972 /* Apple cards don't have the fp table; the laptops use DDC */ 3973 /* The table is also missing on some x86 IGPs */ 3974#ifndef __powerpc__ 3975 NV_ERROR(dev, "Pointer to flat panel table invalid\n"); 3976#endif 3977 bios->digital_min_front_porch = 0x4b; 3978 return 0; 3979 } 3980 3981 fptable = &bios->data[bios->fp.fptablepointer]; 3982 fptable_ver = fptable[0]; 3983 3984 switch (fptable_ver) { 3985 /* 3986 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no 3987 * version field, and miss one of the spread spectrum/PWM bytes. 3988 * This could affect early GF2Go parts (not seen any appropriate ROMs 3989 * though). Here we assume that a version of 0x05 matches this case 3990 * (combining with a BMP version check would be better), as the 3991 * common case for the panel type field is 0x0005, and that is in 3992 * fact what we are reading the first byte of. 3993 */ 3994 case 0x05: /* some NV10, 11, 15, 16 */ 3995 recordlen = 42; 3996 ofs = -1; 3997 break; 3998 case 0x10: /* some NV15/16, and NV11+ */ 3999 recordlen = 44; 4000 ofs = 0; 4001 break; 4002 case 0x20: /* NV40+ */ 4003 headerlen = fptable[1]; 4004 recordlen = fptable[2]; 4005 fpentries = fptable[3]; 4006 /* 4007 * fptable[4] is the minimum 4008 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap 4009 */ 4010 bios->digital_min_front_porch = fptable[4]; 4011 ofs = -7; 4012 break; 4013 default: 4014 NV_ERROR(dev, 4015 "FP table revision %d.%d not currently supported\n", 4016 fptable_ver >> 4, fptable_ver & 0xf); 4017 return -ENOSYS; 4018 } 4019 4020 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */ 4021 return 0; 4022 4023 ret = parse_lvds_manufacturer_table_header(dev, bios, <h); 4024 if (ret) 4025 return ret; 4026 4027 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) { 4028 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer + 4029 lth.headerlen + 1; 4030 bios->fp.xlatwidth = lth.recordlen; 4031 } 4032 if (bios->fp.fpxlatetableptr == 0x0) { 4033 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n"); 4034 return -EINVAL; 4035 } 4036 4037 fpstrapping = get_fp_strap(dev, bios); 4038 4039 fpindex = bios->data[bios->fp.fpxlatetableptr + 4040 fpstrapping * bios->fp.xlatwidth]; 4041 4042 if (fpindex > fpentries) { 4043 NV_ERROR(dev, "Bad flat panel table index\n"); 4044 return -ENOENT; 4045 } 4046 4047 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */ 4048 if (lth.lvds_ver > 0x10) 4049 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf; 4050 4051 /* 4052 * If either the strap or xlated fpindex value are 0xf there is no 4053 * panel using a strap-derived bios mode present. this condition 4054 * includes, but is different from, the DDC panel indicator above 4055 */ 4056 if (fpstrapping == 0xf || fpindex == 0xf) 4057 return 0; 4058 4059 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen + 4060 recordlen * fpindex + ofs; 4061 4062 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n", 4063 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1, 4064 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1, 4065 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10); 4066 4067 return 0; 4068} 4069 4070bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode) 4071{ 4072 struct drm_nouveau_private *dev_priv = dev->dev_private; 4073 struct nvbios *bios = &dev_priv->vbios; 4074 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr]; 4075 4076 if (!mode) /* just checking whether we can produce a mode */ 4077 return bios->fp.mode_ptr; 4078 4079 memset(mode, 0, sizeof(struct drm_display_mode)); 4080 /* 4081 * For version 1.0 (version in byte 0): 4082 * bytes 1-2 are "panel type", including bits on whether Colour/mono, 4083 * single/dual link, and type (TFT etc.) 4084 * bytes 3-6 are bits per colour in RGBX 4085 */ 4086 mode->clock = ROM16(mode_entry[7]) * 10; 4087 /* bytes 9-10 is HActive */ 4088 mode->hdisplay = ROM16(mode_entry[11]) + 1; 4089 /* 4090 * bytes 13-14 is HValid Start 4091 * bytes 15-16 is HValid End 4092 */ 4093 mode->hsync_start = ROM16(mode_entry[17]) + 1; 4094 mode->hsync_end = ROM16(mode_entry[19]) + 1; 4095 mode->htotal = ROM16(mode_entry[21]) + 1; 4096 /* bytes 23-24, 27-30 similarly, but vertical */ 4097 mode->vdisplay = ROM16(mode_entry[25]) + 1; 4098 mode->vsync_start = ROM16(mode_entry[31]) + 1; 4099 mode->vsync_end = ROM16(mode_entry[33]) + 1; 4100 mode->vtotal = ROM16(mode_entry[35]) + 1; 4101 mode->flags |= (mode_entry[37] & 0x10) ? 4102 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4103 mode->flags |= (mode_entry[37] & 0x1) ? 4104 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4105 /* 4106 * bytes 38-39 relate to spread spectrum settings 4107 * bytes 40-43 are something to do with PWM 4108 */ 4109 4110 mode->status = MODE_OK; 4111 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; 4112 drm_mode_set_name(mode); 4113 return bios->fp.mode_ptr; 4114} 4115 4116int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit) 4117{ 4118 /* 4119 * The LVDS table header is (mostly) described in 4120 * parse_lvds_manufacturer_table_header(): the BIT header additionally 4121 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if 4122 * straps are not being used for the panel, this specifies the frequency 4123 * at which modes should be set up in the dual link style. 4124 * 4125 * Following the header, the BMP (ver 0xa) table has several records, 4126 * indexed by a separate xlat table, indexed in turn by the fp strap in 4127 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script 4128 * numbers for use by INIT_SUB which controlled panel init and power, 4129 * and finally a dword of ms to sleep between power off and on 4130 * operations. 4131 * 4132 * In the BIT versions, the table following the header serves as an 4133 * integrated config and xlat table: the records in the table are 4134 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has 4135 * two bytes - the first as a config byte, the second for indexing the 4136 * fp mode table pointed to by the BIT 'D' table 4137 * 4138 * DDC is not used until after card init, so selecting the correct table 4139 * entry and setting the dual link flag for EDID equipped panels, 4140 * requiring tests against the native-mode pixel clock, cannot be done 4141 * until later, when this function should be called with non-zero pxclk 4142 */ 4143 struct drm_nouveau_private *dev_priv = dev->dev_private; 4144 struct nvbios *bios = &dev_priv->vbios; 4145 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0; 4146 struct lvdstableheader lth; 4147 uint16_t lvdsofs; 4148 int ret, chip_version = bios->chip_version; 4149 4150 ret = parse_lvds_manufacturer_table_header(dev, bios, <h); 4151 if (ret) 4152 return ret; 4153 4154 switch (lth.lvds_ver) { 4155 case 0x0a: /* pre NV40 */ 4156 lvdsmanufacturerindex = bios->data[ 4157 bios->fp.fpxlatemanufacturertableptr + 4158 fpstrapping]; 4159 4160 /* we're done if this isn't the EDID panel case */ 4161 if (!pxclk) 4162 break; 4163 4164 if (chip_version < 0x25) { 4165 /* nv17 behaviour 4166 * 4167 * It seems the old style lvds script pointer is reused 4168 * to select 18/24 bit colour depth for EDID panels. 4169 */ 4170 lvdsmanufacturerindex = 4171 (bios->legacy.lvds_single_a_script_ptr & 1) ? 4172 2 : 0; 4173 if (pxclk >= bios->fp.duallink_transition_clk) 4174 lvdsmanufacturerindex++; 4175 } else if (chip_version < 0x30) { 4176 /* nv28 behaviour (off-chip encoder) 4177 * 4178 * nv28 does a complex dance of first using byte 121 of 4179 * the EDID to choose the lvdsmanufacturerindex, then 4180 * later attempting to match the EDID manufacturer and 4181 * product IDs in a table (signature 'pidt' (panel id 4182 * table?)), setting an lvdsmanufacturerindex of 0 and 4183 * an fp strap of the match index (or 0xf if none) 4184 */ 4185 lvdsmanufacturerindex = 0; 4186 } else { 4187 /* nv31, nv34 behaviour */ 4188 lvdsmanufacturerindex = 0; 4189 if (pxclk >= bios->fp.duallink_transition_clk) 4190 lvdsmanufacturerindex = 2; 4191 if (pxclk >= 140000) 4192 lvdsmanufacturerindex = 3; 4193 } 4194 4195 /* 4196 * nvidia set the high nibble of (cr57=f, cr58) to 4197 * lvdsmanufacturerindex in this case; we don't 4198 */ 4199 break; 4200 case 0x30: /* NV4x */ 4201 case 0x40: /* G80/G90 */ 4202 lvdsmanufacturerindex = fpstrapping; 4203 break; 4204 default: 4205 NV_ERROR(dev, "LVDS table revision not currently supported\n"); 4206 return -ENOSYS; 4207 } 4208 4209 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex; 4210 switch (lth.lvds_ver) { 4211 case 0x0a: 4212 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1; 4213 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2; 4214 bios->fp.dual_link = bios->data[lvdsofs] & 4; 4215 bios->fp.link_c_increment = bios->data[lvdsofs] & 8; 4216 *if_is_24bit = bios->data[lvdsofs] & 16; 4217 break; 4218 case 0x30: 4219 case 0x40: 4220 /* 4221 * No sign of the "power off for reset" or "reset for panel 4222 * on" bits, but it's safer to assume we should 4223 */ 4224 bios->fp.power_off_for_reset = true; 4225 bios->fp.reset_after_pclk_change = true; 4226 4227 /* 4228 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is 4229 * over-written, and if_is_24bit isn't used 4230 */ 4231 bios->fp.dual_link = bios->data[lvdsofs] & 1; 4232 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2; 4233 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4]; 4234 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10; 4235 break; 4236 } 4237 4238 /* set dual_link flag for EDID case */ 4239 if (pxclk && (chip_version < 0x25 || chip_version > 0x28)) 4240 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk); 4241 4242 *dl = bios->fp.dual_link; 4243 4244 return 0; 4245} 4246 4247/* BIT 'U'/'d' table encoder subtables have hashes matching them to 4248 * a particular set of encoders. 4249 * 4250 * This function returns true if a particular DCB entry matches. 4251 */ 4252bool 4253bios_encoder_match(struct dcb_entry *dcb, u32 hash) 4254{ 4255 if ((hash & 0x000000f0) != (dcb->location << 4)) 4256 return false; 4257 if ((hash & 0x0000000f) != dcb->type) 4258 return false; 4259 if (!(hash & (dcb->or << 16))) 4260 return false; 4261 4262 switch (dcb->type) { 4263 case OUTPUT_TMDS: 4264 case OUTPUT_LVDS: 4265 case OUTPUT_DP: 4266 if (hash & 0x00c00000) { 4267 if (!(hash & (dcb->sorconf.link << 22))) 4268 return false; 4269 } 4270 default: 4271 return true; 4272 } 4273} 4274 4275int 4276nouveau_bios_run_display_table(struct drm_device *dev, u16 type, int pclk, 4277 struct dcb_entry *dcbent, int crtc) 4278{ 4279 /* 4280 * The display script table is located by the BIT 'U' table. 4281 * 4282 * It contains an array of pointers to various tables describing 4283 * a particular output type. The first 32-bits of the output 4284 * tables contains similar information to a DCB entry, and is 4285 * used to decide whether that particular table is suitable for 4286 * the output you want to access. 4287 * 4288 * The "record header length" field here seems to indicate the 4289 * offset of the first configuration entry in the output tables. 4290 * This is 10 on most cards I've seen, but 12 has been witnessed 4291 * on DP cards, and there's another script pointer within the 4292 * header. 4293 * 4294 * offset + 0 ( 8 bits): version 4295 * offset + 1 ( 8 bits): header length 4296 * offset + 2 ( 8 bits): record length 4297 * offset + 3 ( 8 bits): number of records 4298 * offset + 4 ( 8 bits): record header length 4299 * offset + 5 (16 bits): pointer to first output script table 4300 */ 4301 4302 struct drm_nouveau_private *dev_priv = dev->dev_private; 4303 struct nvbios *bios = &dev_priv->vbios; 4304 uint8_t *table = &bios->data[bios->display.script_table_ptr]; 4305 uint8_t *otable = NULL; 4306 uint16_t script; 4307 int i; 4308 4309 if (!bios->display.script_table_ptr) { 4310 NV_ERROR(dev, "No pointer to output script table\n"); 4311 return 1; 4312 } 4313 4314 /* 4315 * Nothing useful has been in any of the pre-2.0 tables I've seen, 4316 * so until they are, we really don't need to care. 4317 */ 4318 if (table[0] < 0x20) 4319 return 1; 4320 4321 if (table[0] != 0x20 && table[0] != 0x21) { 4322 NV_ERROR(dev, "Output script table version 0x%02x unknown\n", 4323 table[0]); 4324 return 1; 4325 } 4326 4327 /* 4328 * The output script tables describing a particular output type 4329 * look as follows: 4330 * 4331 * offset + 0 (32 bits): output this table matches (hash of DCB) 4332 * offset + 4 ( 8 bits): unknown 4333 * offset + 5 ( 8 bits): number of configurations 4334 * offset + 6 (16 bits): pointer to some script 4335 * offset + 8 (16 bits): pointer to some script 4336 * 4337 * headerlen == 10 4338 * offset + 10 : configuration 0 4339 * 4340 * headerlen == 12 4341 * offset + 10 : pointer to some script 4342 * offset + 12 : configuration 0 4343 * 4344 * Each config entry is as follows: 4345 * 4346 * offset + 0 (16 bits): unknown, assumed to be a match value 4347 * offset + 2 (16 bits): pointer to script table (clock set?) 4348 * offset + 4 (16 bits): pointer to script table (reset?) 4349 * 4350 * There doesn't appear to be a count value to say how many 4351 * entries exist in each script table, instead, a 0 value in 4352 * the first 16-bit word seems to indicate both the end of the 4353 * list and the default entry. The second 16-bit word in the 4354 * script tables is a pointer to the script to execute. 4355 */ 4356 4357 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n", 4358 dcbent->type, dcbent->location, dcbent->or); 4359 for (i = 0; i < table[3]; i++) { 4360 otable = ROMPTR(dev, table[table[1] + (i * table[2])]); 4361 if (otable && bios_encoder_match(dcbent, ROM32(otable[0]))) 4362 break; 4363 } 4364 4365 if (!otable) { 4366 NV_DEBUG_KMS(dev, "failed to match any output table\n"); 4367 return 1; 4368 } 4369 4370 if (pclk < -2 || pclk > 0) { 4371 /* Try to find matching script table entry */ 4372 for (i = 0; i < otable[5]; i++) { 4373 if (ROM16(otable[table[4] + i*6]) == type) 4374 break; 4375 } 4376 4377 if (i == otable[5]) { 4378 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, " 4379 "using first\n", 4380 type, dcbent->type, dcbent->or); 4381 i = 0; 4382 } 4383 } 4384 4385 if (pclk == 0) { 4386 script = ROM16(otable[6]); 4387 if (!script) { 4388 NV_DEBUG_KMS(dev, "output script 0 not found\n"); 4389 return 1; 4390 } 4391 4392 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 0\n", script); 4393 nouveau_bios_run_init_table(dev, script, dcbent, crtc); 4394 } else 4395 if (pclk == -1) { 4396 script = ROM16(otable[8]); 4397 if (!script) { 4398 NV_DEBUG_KMS(dev, "output script 1 not found\n"); 4399 return 1; 4400 } 4401 4402 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 1\n", script); 4403 nouveau_bios_run_init_table(dev, script, dcbent, crtc); 4404 } else 4405 if (pclk == -2) { 4406 if (table[4] >= 12) 4407 script = ROM16(otable[10]); 4408 else 4409 script = 0; 4410 if (!script) { 4411 NV_DEBUG_KMS(dev, "output script 2 not found\n"); 4412 return 1; 4413 } 4414 4415 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 2\n", script); 4416 nouveau_bios_run_init_table(dev, script, dcbent, crtc); 4417 } else 4418 if (pclk > 0) { 4419 script = ROM16(otable[table[4] + i*6 + 2]); 4420 if (script) 4421 script = clkcmptable(bios, script, pclk); 4422 if (!script) { 4423 NV_DEBUG_KMS(dev, "clock script 0 not found\n"); 4424 return 1; 4425 } 4426 4427 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 0\n", script); 4428 nouveau_bios_run_init_table(dev, script, dcbent, crtc); 4429 } else 4430 if (pclk < 0) { 4431 script = ROM16(otable[table[4] + i*6 + 4]); 4432 if (script) 4433 script = clkcmptable(bios, script, -pclk); 4434 if (!script) { 4435 NV_DEBUG_KMS(dev, "clock script 1 not found\n"); 4436 return 1; 4437 } 4438 4439 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 1\n", script); 4440 nouveau_bios_run_init_table(dev, script, dcbent, crtc); 4441 } 4442 4443 return 0; 4444} 4445 4446 4447int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk) 4448{ 4449 /* 4450 * the pxclk parameter is in kHz 4451 * 4452 * This runs the TMDS regs setting code found on BIT bios cards 4453 * 4454 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and 4455 * ffs(or) == 3, use the second. 4456 */ 4457 4458 struct drm_nouveau_private *dev_priv = dev->dev_private; 4459 struct nvbios *bios = &dev_priv->vbios; 4460 int cv = bios->chip_version; 4461 uint16_t clktable = 0, scriptptr; 4462 uint32_t sel_clk_binding, sel_clk; 4463 4464 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */ 4465 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 && 4466 dcbent->location != DCB_LOC_ON_CHIP) 4467 return 0; 4468 4469 switch (ffs(dcbent->or)) { 4470 case 1: 4471 clktable = bios->tmds.output0_script_ptr; 4472 break; 4473 case 2: 4474 case 3: 4475 clktable = bios->tmds.output1_script_ptr; 4476 break; 4477 } 4478 4479 if (!clktable) { 4480 NV_ERROR(dev, "Pixel clock comparison table not found\n"); 4481 return -EINVAL; 4482 } 4483 4484 scriptptr = clkcmptable(bios, clktable, pxclk); 4485 4486 if (!scriptptr) { 4487 NV_ERROR(dev, "TMDS output init script not found\n"); 4488 return -ENOENT; 4489 } 4490 4491 /* don't let script change pll->head binding */ 4492 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000; 4493 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000); 4494 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; 4495 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); 4496 4497 return 0; 4498} 4499 4500struct pll_mapping { 4501 u8 type; 4502 u32 reg; 4503}; 4504 4505static struct pll_mapping nv04_pll_mapping[] = { 4506 { PLL_CORE , NV_PRAMDAC_NVPLL_COEFF }, 4507 { PLL_MEMORY, NV_PRAMDAC_MPLL_COEFF }, 4508 { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF }, 4509 { PLL_VPLL1 , NV_RAMDAC_VPLL2 }, 4510 {} 4511}; 4512 4513static struct pll_mapping nv40_pll_mapping[] = { 4514 { PLL_CORE , 0x004000 }, 4515 { PLL_MEMORY, 0x004020 }, 4516 { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF }, 4517 { PLL_VPLL1 , NV_RAMDAC_VPLL2 }, 4518 {} 4519}; 4520 4521static struct pll_mapping nv50_pll_mapping[] = { 4522 { PLL_CORE , 0x004028 }, 4523 { PLL_SHADER, 0x004020 }, 4524 { PLL_UNK03 , 0x004000 }, 4525 { PLL_MEMORY, 0x004008 }, 4526 { PLL_UNK40 , 0x00e810 }, 4527 { PLL_UNK41 , 0x00e818 }, 4528 { PLL_UNK42 , 0x00e824 }, 4529 { PLL_VPLL0 , 0x614100 }, 4530 { PLL_VPLL1 , 0x614900 }, 4531 {} 4532}; 4533 4534static struct pll_mapping nv84_pll_mapping[] = { 4535 { PLL_CORE , 0x004028 }, 4536 { PLL_SHADER, 0x004020 }, 4537 { PLL_MEMORY, 0x004008 }, 4538 { PLL_VDEC , 0x004030 }, 4539 { PLL_UNK41 , 0x00e818 }, 4540 { PLL_VPLL0 , 0x614100 }, 4541 { PLL_VPLL1 , 0x614900 }, 4542 {} 4543}; 4544 4545u32 4546get_pll_register(struct drm_device *dev, enum pll_types type) 4547{ 4548 struct drm_nouveau_private *dev_priv = dev->dev_private; 4549 struct nvbios *bios = &dev_priv->vbios; 4550 struct pll_mapping *map; 4551 int i; 4552 4553 if (dev_priv->card_type < NV_40) 4554 map = nv04_pll_mapping; 4555 else 4556 if (dev_priv->card_type < NV_50) 4557 map = nv40_pll_mapping; 4558 else { 4559 u8 *plim = &bios->data[bios->pll_limit_tbl_ptr]; 4560 4561 if (plim[0] >= 0x30) { 4562 u8 *entry = plim + plim[1]; 4563 for (i = 0; i < plim[3]; i++, entry += plim[2]) { 4564 if (entry[0] == type) 4565 return ROM32(entry[3]); 4566 } 4567 4568 return 0; 4569 } 4570 4571 if (dev_priv->chipset == 0x50) 4572 map = nv50_pll_mapping; 4573 else 4574 map = nv84_pll_mapping; 4575 } 4576 4577 while (map->reg) { 4578 if (map->type == type) 4579 return map->reg; 4580 map++; 4581 } 4582 4583 return 0; 4584} 4585 4586int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim) 4587{ 4588 /* 4589 * PLL limits table 4590 * 4591 * Version 0x10: NV30, NV31 4592 * One byte header (version), one record of 24 bytes 4593 * Version 0x11: NV36 - Not implemented 4594 * Seems to have same record style as 0x10, but 3 records rather than 1 4595 * Version 0x20: Found on Geforce 6 cards 4596 * Trivial 4 byte BIT header. 31 (0x1f) byte record length 4597 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards 4598 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record 4599 * length in general, some (integrated) have an extra configuration byte 4600 * Version 0x30: Found on Geforce 8, separates the register mapping 4601 * from the limits tables. 4602 */ 4603 4604 struct drm_nouveau_private *dev_priv = dev->dev_private; 4605 struct nvbios *bios = &dev_priv->vbios; 4606 int cv = bios->chip_version, pllindex = 0; 4607 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0; 4608 uint32_t crystal_strap_mask, crystal_straps; 4609 4610 if (!bios->pll_limit_tbl_ptr) { 4611 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 || 4612 cv >= 0x40) { 4613 NV_ERROR(dev, "Pointer to PLL limits table invalid\n"); 4614 return -EINVAL; 4615 } 4616 } else 4617 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr]; 4618 4619 crystal_strap_mask = 1 << 6; 4620 /* open coded dev->twoHeads test */ 4621 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20) 4622 crystal_strap_mask |= 1 << 22; 4623 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) & 4624 crystal_strap_mask; 4625 4626 switch (pll_lim_ver) { 4627 /* 4628 * We use version 0 to indicate a pre limit table bios (single stage 4629 * pll) and load the hard coded limits instead. 4630 */ 4631 case 0: 4632 break; 4633 case 0x10: 4634 case 0x11: 4635 /* 4636 * Strictly v0x11 has 3 entries, but the last two don't seem 4637 * to get used. 4638 */ 4639 headerlen = 1; 4640 recordlen = 0x18; 4641 entries = 1; 4642 pllindex = 0; 4643 break; 4644 case 0x20: 4645 case 0x21: 4646 case 0x30: 4647 case 0x40: 4648 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1]; 4649 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2]; 4650 entries = bios->data[bios->pll_limit_tbl_ptr + 3]; 4651 break; 4652 default: 4653 NV_ERROR(dev, "PLL limits table revision 0x%X not currently " 4654 "supported\n", pll_lim_ver); 4655 return -ENOSYS; 4656 } 4657 4658 /* initialize all members to zero */ 4659 memset(pll_lim, 0, sizeof(struct pll_lims)); 4660 4661 /* if we were passed a type rather than a register, figure 4662 * out the register and store it 4663 */ 4664 if (limit_match > PLL_MAX) 4665 pll_lim->reg = limit_match; 4666 else { 4667 pll_lim->reg = get_pll_register(dev, limit_match); 4668 if (!pll_lim->reg) 4669 return -ENOENT; 4670 } 4671 4672 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) { 4673 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex]; 4674 4675 pll_lim->vco1.minfreq = ROM32(pll_rec[0]); 4676 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]); 4677 pll_lim->vco2.minfreq = ROM32(pll_rec[8]); 4678 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]); 4679 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]); 4680 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]); 4681 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX; 4682 4683 /* these values taken from nv30/31/36 */ 4684 pll_lim->vco1.min_n = 0x1; 4685 if (cv == 0x36) 4686 pll_lim->vco1.min_n = 0x5; 4687 pll_lim->vco1.max_n = 0xff; 4688 pll_lim->vco1.min_m = 0x1; 4689 pll_lim->vco1.max_m = 0xd; 4690 pll_lim->vco2.min_n = 0x4; 4691 /* 4692 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this 4693 * table version (apart from nv35)), N2 is compared to 4694 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and 4695 * save a comparison 4696 */ 4697 pll_lim->vco2.max_n = 0x28; 4698 if (cv == 0x30 || cv == 0x35) 4699 /* only 5 bits available for N2 on nv30/35 */ 4700 pll_lim->vco2.max_n = 0x1f; 4701 pll_lim->vco2.min_m = 0x1; 4702 pll_lim->vco2.max_m = 0x4; 4703 pll_lim->max_log2p = 0x7; 4704 pll_lim->max_usable_log2p = 0x6; 4705 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) { 4706 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen; 4707 uint8_t *pll_rec; 4708 int i; 4709 4710 /* 4711 * First entry is default match, if nothing better. warn if 4712 * reg field nonzero 4713 */ 4714 if (ROM32(bios->data[plloffs])) 4715 NV_WARN(dev, "Default PLL limit entry has non-zero " 4716 "register field\n"); 4717 4718 for (i = 1; i < entries; i++) 4719 if (ROM32(bios->data[plloffs + recordlen * i]) == pll_lim->reg) { 4720 pllindex = i; 4721 break; 4722 } 4723 4724 if ((dev_priv->card_type >= NV_50) && (pllindex == 0)) { 4725 NV_ERROR(dev, "Register 0x%08x not found in PLL " 4726 "limits table", pll_lim->reg); 4727 return -ENOENT; 4728 } 4729 4730 pll_rec = &bios->data[plloffs + recordlen * pllindex]; 4731 4732 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n", 4733 pllindex ? pll_lim->reg : 0); 4734 4735 /* 4736 * Frequencies are stored in tables in MHz, kHz are more 4737 * useful, so we convert. 4738 */ 4739 4740 /* What output frequencies can each VCO generate? */ 4741 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000; 4742 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000; 4743 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000; 4744 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000; 4745 4746 /* What input frequencies they accept (past the m-divider)? */ 4747 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000; 4748 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000; 4749 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000; 4750 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000; 4751 4752 /* What values are accepted as multiplier and divider? */ 4753 pll_lim->vco1.min_n = pll_rec[20]; 4754 pll_lim->vco1.max_n = pll_rec[21]; 4755 pll_lim->vco1.min_m = pll_rec[22]; 4756 pll_lim->vco1.max_m = pll_rec[23]; 4757 pll_lim->vco2.min_n = pll_rec[24]; 4758 pll_lim->vco2.max_n = pll_rec[25]; 4759 pll_lim->vco2.min_m = pll_rec[26]; 4760 pll_lim->vco2.max_m = pll_rec[27]; 4761 4762 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29]; 4763 if (pll_lim->max_log2p > 0x7) 4764 /* pll decoding in nv_hw.c assumes never > 7 */ 4765 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n", 4766 pll_lim->max_log2p); 4767 if (cv < 0x60) 4768 pll_lim->max_usable_log2p = 0x6; 4769 pll_lim->log2p_bias = pll_rec[30]; 4770 4771 if (recordlen > 0x22) 4772 pll_lim->refclk = ROM32(pll_rec[31]); 4773 4774 if (recordlen > 0x23 && pll_rec[35]) 4775 NV_WARN(dev, 4776 "Bits set in PLL configuration byte (%x)\n", 4777 pll_rec[35]); 4778 4779 /* C51 special not seen elsewhere */ 4780 if (cv == 0x51 && !pll_lim->refclk) { 4781 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK); 4782 4783 if ((pll_lim->reg == NV_PRAMDAC_VPLL_COEFF && sel_clk & 0x20) || 4784 (pll_lim->reg == NV_RAMDAC_VPLL2 && sel_clk & 0x80)) { 4785 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3) 4786 pll_lim->refclk = 200000; 4787 else 4788 pll_lim->refclk = 25000; 4789 } 4790 } 4791 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */ 4792 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen]; 4793 uint8_t *record = NULL; 4794 int i; 4795 4796 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n", 4797 pll_lim->reg); 4798 4799 for (i = 0; i < entries; i++, entry += recordlen) { 4800 if (ROM32(entry[3]) == pll_lim->reg) { 4801 record = &bios->data[ROM16(entry[1])]; 4802 break; 4803 } 4804 } 4805 4806 if (!record) { 4807 NV_ERROR(dev, "Register 0x%08x not found in PLL " 4808 "limits table", pll_lim->reg); 4809 return -ENOENT; 4810 } 4811 4812 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000; 4813 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000; 4814 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000; 4815 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000; 4816 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000; 4817 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000; 4818 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000; 4819 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000; 4820 pll_lim->vco1.min_n = record[16]; 4821 pll_lim->vco1.max_n = record[17]; 4822 pll_lim->vco1.min_m = record[18]; 4823 pll_lim->vco1.max_m = record[19]; 4824 pll_lim->vco2.min_n = record[20]; 4825 pll_lim->vco2.max_n = record[21]; 4826 pll_lim->vco2.min_m = record[22]; 4827 pll_lim->vco2.max_m = record[23]; 4828 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25]; 4829 pll_lim->log2p_bias = record[27]; 4830 pll_lim->refclk = ROM32(record[28]); 4831 } else if (pll_lim_ver) { /* ver 0x40 */ 4832 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen]; 4833 uint8_t *record = NULL; 4834 int i; 4835 4836 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n", 4837 pll_lim->reg); 4838 4839 for (i = 0; i < entries; i++, entry += recordlen) { 4840 if (ROM32(entry[3]) == pll_lim->reg) { 4841 record = &bios->data[ROM16(entry[1])]; 4842 break; 4843 } 4844 } 4845 4846 if (!record) { 4847 NV_ERROR(dev, "Register 0x%08x not found in PLL " 4848 "limits table", pll_lim->reg); 4849 return -ENOENT; 4850 } 4851 4852 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000; 4853 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000; 4854 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000; 4855 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000; 4856 pll_lim->vco1.min_m = record[8]; 4857 pll_lim->vco1.max_m = record[9]; 4858 pll_lim->vco1.min_n = record[10]; 4859 pll_lim->vco1.max_n = record[11]; 4860 pll_lim->min_p = record[12]; 4861 pll_lim->max_p = record[13]; 4862 pll_lim->refclk = ROM16(entry[9]) * 1000; 4863 } 4864 4865 /* 4866 * By now any valid limit table ought to have set a max frequency for 4867 * vco1, so if it's zero it's either a pre limit table bios, or one 4868 * with an empty limit table (seen on nv18) 4869 */ 4870 if (!pll_lim->vco1.maxfreq) { 4871 pll_lim->vco1.minfreq = bios->fminvco; 4872 pll_lim->vco1.maxfreq = bios->fmaxvco; 4873 pll_lim->vco1.min_inputfreq = 0; 4874 pll_lim->vco1.max_inputfreq = INT_MAX; 4875 pll_lim->vco1.min_n = 0x1; 4876 pll_lim->vco1.max_n = 0xff; 4877 pll_lim->vco1.min_m = 0x1; 4878 if (crystal_straps == 0) { 4879 /* nv05 does this, nv11 doesn't, nv10 unknown */ 4880 if (cv < 0x11) 4881 pll_lim->vco1.min_m = 0x7; 4882 pll_lim->vco1.max_m = 0xd; 4883 } else { 4884 if (cv < 0x11) 4885 pll_lim->vco1.min_m = 0x8; 4886 pll_lim->vco1.max_m = 0xe; 4887 } 4888 if (cv < 0x17 || cv == 0x1a || cv == 0x20) 4889 pll_lim->max_log2p = 4; 4890 else 4891 pll_lim->max_log2p = 5; 4892 pll_lim->max_usable_log2p = pll_lim->max_log2p; 4893 } 4894 4895 if (!pll_lim->refclk) 4896 switch (crystal_straps) { 4897 case 0: 4898 pll_lim->refclk = 13500; 4899 break; 4900 case (1 << 6): 4901 pll_lim->refclk = 14318; 4902 break; 4903 case (1 << 22): 4904 pll_lim->refclk = 27000; 4905 break; 4906 case (1 << 22 | 1 << 6): 4907 pll_lim->refclk = 25000; 4908 break; 4909 } 4910 4911 NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq); 4912 NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq); 4913 NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq); 4914 NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq); 4915 NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n); 4916 NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n); 4917 NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m); 4918 NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m); 4919 if (pll_lim->vco2.maxfreq) { 4920 NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq); 4921 NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq); 4922 NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq); 4923 NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq); 4924 NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n); 4925 NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n); 4926 NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m); 4927 NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m); 4928 } 4929 if (!pll_lim->max_p) { 4930 NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p); 4931 NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias); 4932 } else { 4933 NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p); 4934 NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p); 4935 } 4936 NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk); 4937 4938 return 0; 4939} 4940 4941static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset) 4942{ 4943 /* 4944 * offset + 0 (8 bits): Micro version 4945 * offset + 1 (8 bits): Minor version 4946 * offset + 2 (8 bits): Chip version 4947 * offset + 3 (8 bits): Major version 4948 */ 4949 4950 bios->major_version = bios->data[offset + 3]; 4951 bios->chip_version = bios->data[offset + 2]; 4952 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n", 4953 bios->data[offset + 3], bios->data[offset + 2], 4954 bios->data[offset + 1], bios->data[offset]); 4955} 4956 4957static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset) 4958{ 4959 /* 4960 * Parses the init table segment for pointers used in script execution. 4961 * 4962 * offset + 0 (16 bits): init script tables pointer 4963 * offset + 2 (16 bits): macro index table pointer 4964 * offset + 4 (16 bits): macro table pointer 4965 * offset + 6 (16 bits): condition table pointer 4966 * offset + 8 (16 bits): io condition table pointer 4967 * offset + 10 (16 bits): io flag condition table pointer 4968 * offset + 12 (16 bits): init function table pointer 4969 */ 4970 4971 bios->init_script_tbls_ptr = ROM16(bios->data[offset]); 4972 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]); 4973 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]); 4974 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]); 4975 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]); 4976 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]); 4977 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]); 4978} 4979 4980static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4981{ 4982 /* 4983 * Parses the load detect values for g80 cards. 4984 * 4985 * offset + 0 (16 bits): loadval table pointer 4986 */ 4987 4988 uint16_t load_table_ptr; 4989 uint8_t version, headerlen, entrylen, num_entries; 4990 4991 if (bitentry->length != 3) { 4992 NV_ERROR(dev, "Do not understand BIT A table\n"); 4993 return -EINVAL; 4994 } 4995 4996 load_table_ptr = ROM16(bios->data[bitentry->offset]); 4997 4998 if (load_table_ptr == 0x0) { 4999 NV_DEBUG(dev, "Pointer to BIT loadval table invalid\n"); 5000 return -EINVAL; 5001 } 5002 5003 version = bios->data[load_table_ptr]; 5004 5005 if (version != 0x10) { 5006 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n", 5007 version >> 4, version & 0xF); 5008 return -ENOSYS; 5009 } 5010 5011 headerlen = bios->data[load_table_ptr + 1]; 5012 entrylen = bios->data[load_table_ptr + 2]; 5013 num_entries = bios->data[load_table_ptr + 3]; 5014 5015 if (headerlen != 4 || entrylen != 4 || num_entries != 2) { 5016 NV_ERROR(dev, "Do not understand BIT loadval table\n"); 5017 return -EINVAL; 5018 } 5019 5020 /* First entry is normal dac, 2nd tv-out perhaps? */ 5021 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff; 5022 5023 return 0; 5024} 5025 5026static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5027{ 5028 /* 5029 * offset + 8 (16 bits): PLL limits table pointer 5030 * 5031 * There's more in here, but that's unknown. 5032 */ 5033 5034 if (bitentry->length < 10) { 5035 NV_ERROR(dev, "Do not understand BIT C table\n"); 5036 return -EINVAL; 5037 } 5038 5039 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]); 5040 5041 return 0; 5042} 5043 5044static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5045{ 5046 /* 5047 * Parses the flat panel table segment that the bit entry points to. 5048 * Starting at bitentry->offset: 5049 * 5050 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte 5051 * records beginning with a freq. 5052 * offset + 2 (16 bits): mode table pointer 5053 */ 5054 5055 if (bitentry->length != 4) { 5056 NV_ERROR(dev, "Do not understand BIT display table\n"); 5057 return -EINVAL; 5058 } 5059 5060 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]); 5061 5062 return 0; 5063} 5064 5065static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5066{ 5067 /* 5068 * Parses the init table segment that the bit entry points to. 5069 * 5070 * See parse_script_table_pointers for layout 5071 */ 5072 5073 if (bitentry->length < 14) { 5074 NV_ERROR(dev, "Do not understand init table\n"); 5075 return -EINVAL; 5076 } 5077 5078 parse_script_table_pointers(bios, bitentry->offset); 5079 5080 if (bitentry->length >= 16) 5081 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]); 5082 if (bitentry->length >= 18) 5083 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]); 5084 5085 return 0; 5086} 5087 5088static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5089{ 5090 /* 5091 * BIT 'i' (info?) table 5092 * 5093 * offset + 0 (32 bits): BIOS version dword (as in B table) 5094 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?) 5095 * offset + 13 (16 bits): pointer to table containing DAC load 5096 * detection comparison values 5097 * 5098 * There's other things in the table, purpose unknown 5099 */ 5100 5101 uint16_t daccmpoffset; 5102 uint8_t dacver, dacheaderlen; 5103 5104 if (bitentry->length < 6) { 5105 NV_ERROR(dev, "BIT i table too short for needed information\n"); 5106 return -EINVAL; 5107 } 5108 5109 parse_bios_version(dev, bios, bitentry->offset); 5110 5111 /* 5112 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's 5113 * Quadro identity crisis), other bits possibly as for BMP feature byte 5114 */ 5115 bios->feature_byte = bios->data[bitentry->offset + 5]; 5116 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE; 5117 5118 if (bitentry->length < 15) { 5119 NV_WARN(dev, "BIT i table not long enough for DAC load " 5120 "detection comparison table\n"); 5121 return -EINVAL; 5122 } 5123 5124 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]); 5125 5126 /* doesn't exist on g80 */ 5127 if (!daccmpoffset) 5128 return 0; 5129 5130 /* 5131 * The first value in the table, following the header, is the 5132 * comparison value, the second entry is a comparison value for 5133 * TV load detection. 5134 */ 5135 5136 dacver = bios->data[daccmpoffset]; 5137 dacheaderlen = bios->data[daccmpoffset + 1]; 5138 5139 if (dacver != 0x00 && dacver != 0x10) { 5140 NV_WARN(dev, "DAC load detection comparison table version " 5141 "%d.%d not known\n", dacver >> 4, dacver & 0xf); 5142 return -ENOSYS; 5143 } 5144 5145 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]); 5146 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]); 5147 5148 return 0; 5149} 5150 5151static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5152{ 5153 /* 5154 * Parses the LVDS table segment that the bit entry points to. 5155 * Starting at bitentry->offset: 5156 * 5157 * offset + 0 (16 bits): LVDS strap xlate table pointer 5158 */ 5159 5160 if (bitentry->length != 2) { 5161 NV_ERROR(dev, "Do not understand BIT LVDS table\n"); 5162 return -EINVAL; 5163 } 5164 5165 /* 5166 * No idea if it's still called the LVDS manufacturer table, but 5167 * the concept's close enough. 5168 */ 5169 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]); 5170 5171 return 0; 5172} 5173 5174static int 5175parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios, 5176 struct bit_entry *bitentry) 5177{ 5178 /* 5179 * offset + 2 (8 bits): number of options in an 5180 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set 5181 * offset + 3 (16 bits): pointer to strap xlate table for RAM 5182 * restrict option selection 5183 * 5184 * There's a bunch of bits in this table other than the RAM restrict 5185 * stuff that we don't use - their use currently unknown 5186 */ 5187 5188 /* 5189 * Older bios versions don't have a sufficiently long table for 5190 * what we want 5191 */ 5192 if (bitentry->length < 0x5) 5193 return 0; 5194 5195 if (bitentry->version < 2) { 5196 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2]; 5197 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]); 5198 } else { 5199 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0]; 5200 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]); 5201 } 5202 5203 return 0; 5204} 5205 5206static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5207{ 5208 /* 5209 * Parses the pointer to the TMDS table 5210 * 5211 * Starting at bitentry->offset: 5212 * 5213 * offset + 0 (16 bits): TMDS table pointer 5214 * 5215 * The TMDS table is typically found just before the DCB table, with a 5216 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being 5217 * length?) 5218 * 5219 * At offset +7 is a pointer to a script, which I don't know how to 5220 * run yet. 5221 * At offset +9 is a pointer to another script, likewise 5222 * Offset +11 has a pointer to a table where the first word is a pxclk 5223 * frequency and the second word a pointer to a script, which should be 5224 * run if the comparison pxclk frequency is less than the pxclk desired. 5225 * This repeats for decreasing comparison frequencies 5226 * Offset +13 has a pointer to a similar table 5227 * The selection of table (and possibly +7/+9 script) is dictated by 5228 * "or" from the DCB. 5229 */ 5230 5231 uint16_t tmdstableptr, script1, script2; 5232 5233 if (bitentry->length != 2) { 5234 NV_ERROR(dev, "Do not understand BIT TMDS table\n"); 5235 return -EINVAL; 5236 } 5237 5238 tmdstableptr = ROM16(bios->data[bitentry->offset]); 5239 if (!tmdstableptr) { 5240 NV_ERROR(dev, "Pointer to TMDS table invalid\n"); 5241 return -EINVAL; 5242 } 5243 5244 NV_INFO(dev, "TMDS table version %d.%d\n", 5245 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf); 5246 5247 /* nv50+ has v2.0, but we don't parse it atm */ 5248 if (bios->data[tmdstableptr] != 0x11) 5249 return -ENOSYS; 5250 5251 /* 5252 * These two scripts are odd: they don't seem to get run even when 5253 * they are not stubbed. 5254 */ 5255 script1 = ROM16(bios->data[tmdstableptr + 7]); 5256 script2 = ROM16(bios->data[tmdstableptr + 9]); 5257 if (bios->data[script1] != 'q' || bios->data[script2] != 'q') 5258 NV_WARN(dev, "TMDS table script pointers not stubbed\n"); 5259 5260 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]); 5261 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]); 5262 5263 return 0; 5264} 5265 5266static int 5267parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios, 5268 struct bit_entry *bitentry) 5269{ 5270 /* 5271 * Parses the pointer to the G80 output script tables 5272 * 5273 * Starting at bitentry->offset: 5274 * 5275 * offset + 0 (16 bits): output script table pointer 5276 */ 5277 5278 uint16_t outputscripttableptr; 5279 5280 if (bitentry->length != 3) { 5281 NV_ERROR(dev, "Do not understand BIT U table\n"); 5282 return -EINVAL; 5283 } 5284 5285 outputscripttableptr = ROM16(bios->data[bitentry->offset]); 5286 bios->display.script_table_ptr = outputscripttableptr; 5287 return 0; 5288} 5289 5290struct bit_table { 5291 const char id; 5292 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *); 5293}; 5294 5295#define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry }) 5296 5297int 5298bit_table(struct drm_device *dev, u8 id, struct bit_entry *bit) 5299{ 5300 struct drm_nouveau_private *dev_priv = dev->dev_private; 5301 struct nvbios *bios = &dev_priv->vbios; 5302 u8 entries, *entry; 5303 5304 if (bios->type != NVBIOS_BIT) 5305 return -ENODEV; 5306 5307 entries = bios->data[bios->offset + 10]; 5308 entry = &bios->data[bios->offset + 12]; 5309 while (entries--) { 5310 if (entry[0] == id) { 5311 bit->id = entry[0]; 5312 bit->version = entry[1]; 5313 bit->length = ROM16(entry[2]); 5314 bit->offset = ROM16(entry[4]); 5315 bit->data = ROMPTR(dev, entry[4]); 5316 return 0; 5317 } 5318 5319 entry += bios->data[bios->offset + 9]; 5320 } 5321 5322 return -ENOENT; 5323} 5324 5325static int 5326parse_bit_table(struct nvbios *bios, const uint16_t bitoffset, 5327 struct bit_table *table) 5328{ 5329 struct drm_device *dev = bios->dev; 5330 struct bit_entry bitentry; 5331 5332 if (bit_table(dev, table->id, &bitentry) == 0) 5333 return table->parse_fn(dev, bios, &bitentry); 5334 5335 NV_INFO(dev, "BIT table '%c' not found\n", table->id); 5336 return -ENOSYS; 5337} 5338 5339static int 5340parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset) 5341{ 5342 int ret; 5343 5344 /* 5345 * The only restriction on parsing order currently is having 'i' first 5346 * for use of bios->*_version or bios->feature_byte while parsing; 5347 * functions shouldn't be actually *doing* anything apart from pulling 5348 * data from the image into the bios struct, thus no interdependencies 5349 */ 5350 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i)); 5351 if (ret) /* info? */ 5352 return ret; 5353 if (bios->major_version >= 0x60) /* g80+ */ 5354 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A)); 5355 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C)); 5356 if (ret) 5357 return ret; 5358 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display)); 5359 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init)); 5360 if (ret) 5361 return ret; 5362 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */ 5363 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds)); 5364 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds)); 5365 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U)); 5366 5367 return 0; 5368} 5369 5370static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset) 5371{ 5372 /* 5373 * Parses the BMP structure for useful things, but does not act on them 5374 * 5375 * offset + 5: BMP major version 5376 * offset + 6: BMP minor version 5377 * offset + 9: BMP feature byte 5378 * offset + 10: BCD encoded BIOS version 5379 * 5380 * offset + 18: init script table pointer (for bios versions < 5.10h) 5381 * offset + 20: extra init script table pointer (for bios 5382 * versions < 5.10h) 5383 * 5384 * offset + 24: memory init table pointer (used on early bios versions) 5385 * offset + 26: SDR memory sequencing setup data table 5386 * offset + 28: DDR memory sequencing setup data table 5387 * 5388 * offset + 54: index of I2C CRTC pair to use for CRT output 5389 * offset + 55: index of I2C CRTC pair to use for TV output 5390 * offset + 56: index of I2C CRTC pair to use for flat panel output 5391 * offset + 58: write CRTC index for I2C pair 0 5392 * offset + 59: read CRTC index for I2C pair 0 5393 * offset + 60: write CRTC index for I2C pair 1 5394 * offset + 61: read CRTC index for I2C pair 1 5395 * 5396 * offset + 67: maximum internal PLL frequency (single stage PLL) 5397 * offset + 71: minimum internal PLL frequency (single stage PLL) 5398 * 5399 * offset + 75: script table pointers, as described in 5400 * parse_script_table_pointers 5401 * 5402 * offset + 89: TMDS single link output A table pointer 5403 * offset + 91: TMDS single link output B table pointer 5404 * offset + 95: LVDS single link output A table pointer 5405 * offset + 105: flat panel timings table pointer 5406 * offset + 107: flat panel strapping translation table pointer 5407 * offset + 117: LVDS manufacturer panel config table pointer 5408 * offset + 119: LVDS manufacturer strapping translation table pointer 5409 * 5410 * offset + 142: PLL limits table pointer 5411 * 5412 * offset + 156: minimum pixel clock for LVDS dual link 5413 */ 5414 5415 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor; 5416 uint16_t bmplength; 5417 uint16_t legacy_scripts_offset, legacy_i2c_offset; 5418 5419 /* load needed defaults in case we can't parse this info */ 5420 bios->digital_min_front_porch = 0x4b; 5421 bios->fmaxvco = 256000; 5422 bios->fminvco = 128000; 5423 bios->fp.duallink_transition_clk = 90000; 5424 5425 bmp_version_major = bmp[5]; 5426 bmp_version_minor = bmp[6]; 5427 5428 NV_TRACE(dev, "BMP version %d.%d\n", 5429 bmp_version_major, bmp_version_minor); 5430 5431 /* 5432 * Make sure that 0x36 is blank and can't be mistaken for a DCB 5433 * pointer on early versions 5434 */ 5435 if (bmp_version_major < 5) 5436 *(uint16_t *)&bios->data[0x36] = 0; 5437 5438 /* 5439 * Seems that the minor version was 1 for all major versions prior 5440 * to 5. Version 6 could theoretically exist, but I suspect BIT 5441 * happened instead. 5442 */ 5443 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) { 5444 NV_ERROR(dev, "You have an unsupported BMP version. " 5445 "Please send in your bios\n"); 5446 return -ENOSYS; 5447 } 5448 5449 if (bmp_version_major == 0) 5450 /* nothing that's currently useful in this version */ 5451 return 0; 5452 else if (bmp_version_major == 1) 5453 bmplength = 44; /* exact for 1.01 */ 5454 else if (bmp_version_major == 2) 5455 bmplength = 48; /* exact for 2.01 */ 5456 else if (bmp_version_major == 3) 5457 bmplength = 54; 5458 /* guessed - mem init tables added in this version */ 5459 else if (bmp_version_major == 4 || bmp_version_minor < 0x1) 5460 /* don't know if 5.0 exists... */ 5461 bmplength = 62; 5462 /* guessed - BMP I2C indices added in version 4*/ 5463 else if (bmp_version_minor < 0x6) 5464 bmplength = 67; /* exact for 5.01 */ 5465 else if (bmp_version_minor < 0x10) 5466 bmplength = 75; /* exact for 5.06 */ 5467 else if (bmp_version_minor == 0x10) 5468 bmplength = 89; /* exact for 5.10h */ 5469 else if (bmp_version_minor < 0x14) 5470 bmplength = 118; /* exact for 5.11h */ 5471 else if (bmp_version_minor < 0x24) 5472 /* 5473 * Not sure of version where pll limits came in; 5474 * certainly exist by 0x24 though. 5475 */ 5476 /* length not exact: this is long enough to get lvds members */ 5477 bmplength = 123; 5478 else if (bmp_version_minor < 0x27) 5479 /* 5480 * Length not exact: this is long enough to get pll limit 5481 * member 5482 */ 5483 bmplength = 144; 5484 else 5485 /* 5486 * Length not exact: this is long enough to get dual link 5487 * transition clock. 5488 */ 5489 bmplength = 158; 5490 5491 /* checksum */ 5492 if (nv_cksum(bmp, 8)) { 5493 NV_ERROR(dev, "Bad BMP checksum\n"); 5494 return -EINVAL; 5495 } 5496 5497 /* 5498 * Bit 4 seems to indicate either a mobile bios or a quadro card -- 5499 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl 5500 * (not nv10gl), bit 5 that the flat panel tables are present, and 5501 * bit 6 a tv bios. 5502 */ 5503 bios->feature_byte = bmp[9]; 5504 5505 parse_bios_version(dev, bios, offset + 10); 5506 5507 if (bmp_version_major < 5 || bmp_version_minor < 0x10) 5508 bios->old_style_init = true; 5509 legacy_scripts_offset = 18; 5510 if (bmp_version_major < 2) 5511 legacy_scripts_offset -= 4; 5512 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]); 5513 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]); 5514 5515 if (bmp_version_major > 2) { /* appears in BMP 3 */ 5516 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]); 5517 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]); 5518 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]); 5519 } 5520 5521 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */ 5522 if (bmplength > 61) 5523 legacy_i2c_offset = offset + 54; 5524 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset]; 5525 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1]; 5526 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2]; 5527 5528 if (bmplength > 74) { 5529 bios->fmaxvco = ROM32(bmp[67]); 5530 bios->fminvco = ROM32(bmp[71]); 5531 } 5532 if (bmplength > 88) 5533 parse_script_table_pointers(bios, offset + 75); 5534 if (bmplength > 94) { 5535 bios->tmds.output0_script_ptr = ROM16(bmp[89]); 5536 bios->tmds.output1_script_ptr = ROM16(bmp[91]); 5537 /* 5538 * Never observed in use with lvds scripts, but is reused for 5539 * 18/24 bit panel interface default for EDID equipped panels 5540 * (if_is_24bit not set directly to avoid any oscillation). 5541 */ 5542 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]); 5543 } 5544 if (bmplength > 108) { 5545 bios->fp.fptablepointer = ROM16(bmp[105]); 5546 bios->fp.fpxlatetableptr = ROM16(bmp[107]); 5547 bios->fp.xlatwidth = 1; 5548 } 5549 if (bmplength > 120) { 5550 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]); 5551 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]); 5552 } 5553 if (bmplength > 143) 5554 bios->pll_limit_tbl_ptr = ROM16(bmp[142]); 5555 5556 if (bmplength > 157) 5557 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10; 5558 5559 return 0; 5560} 5561 5562static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len) 5563{ 5564 int i, j; 5565 5566 for (i = 0; i <= (n - len); i++) { 5567 for (j = 0; j < len; j++) 5568 if (data[i + j] != str[j]) 5569 break; 5570 if (j == len) 5571 return i; 5572 } 5573 5574 return 0; 5575} 5576 5577void * 5578dcb_table(struct drm_device *dev) 5579{ 5580 struct drm_nouveau_private *dev_priv = dev->dev_private; 5581 u8 *dcb = NULL; 5582 5583 if (dev_priv->card_type > NV_04) 5584 dcb = ROMPTR(dev, dev_priv->vbios.data[0x36]); 5585 if (!dcb) { 5586 NV_WARNONCE(dev, "No DCB data found in VBIOS\n"); 5587 return NULL; 5588 } 5589 5590 if (dcb[0] >= 0x41) { 5591 NV_WARNONCE(dev, "DCB version 0x%02x unknown\n", dcb[0]); 5592 return NULL; 5593 } else 5594 if (dcb[0] >= 0x30) { 5595 if (ROM32(dcb[6]) == 0x4edcbdcb) 5596 return dcb; 5597 } else 5598 if (dcb[0] >= 0x20) { 5599 if (ROM32(dcb[4]) == 0x4edcbdcb) 5600 return dcb; 5601 } else 5602 if (dcb[0] >= 0x15) { 5603 if (!memcmp(&dcb[-7], "DEV_REC", 7)) 5604 return dcb; 5605 } else { 5606 /* 5607 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but 5608 * always has the same single (crt) entry, even when tv-out 5609 * present, so the conclusion is this version cannot really 5610 * be used. 5611 * 5612 * v1.2 tables (some NV6/10, and NV15+) normally have the 5613 * same 5 entries, which are not specific to the card and so 5614 * no use. 5615 * 5616 * v1.2 does have an I2C table that read_dcb_i2c_table can 5617 * handle, but cards exist (nv11 in #14821) with a bad i2c 5618 * table pointer, so use the indices parsed in 5619 * parse_bmp_structure. 5620 * 5621 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful 5622 */ 5623 NV_WARNONCE(dev, "No useful DCB data in VBIOS\n"); 5624 return NULL; 5625 } 5626 5627 NV_WARNONCE(dev, "DCB header validation failed\n"); 5628 return NULL; 5629} 5630 5631void * 5632dcb_outp(struct drm_device *dev, u8 idx) 5633{ 5634 u8 *dcb = dcb_table(dev); 5635 if (dcb && dcb[0] >= 0x30) { 5636 if (idx < dcb[2]) 5637 return dcb + dcb[1] + (idx * dcb[3]); 5638 } else 5639 if (dcb && dcb[0] >= 0x20) { 5640 u8 *i2c = ROMPTR(dev, dcb[2]); 5641 u8 *ent = dcb + 8 + (idx * 8); 5642 if (i2c && ent < i2c) 5643 return ent; 5644 } else 5645 if (dcb && dcb[0] >= 0x15) { 5646 u8 *i2c = ROMPTR(dev, dcb[2]); 5647 u8 *ent = dcb + 4 + (idx * 10); 5648 if (i2c && ent < i2c) 5649 return ent; 5650 } 5651 5652 return NULL; 5653} 5654 5655int 5656dcb_outp_foreach(struct drm_device *dev, void *data, 5657 int (*exec)(struct drm_device *, void *, int idx, u8 *outp)) 5658{ 5659 int ret, idx = -1; 5660 u8 *outp = NULL; 5661 while ((outp = dcb_outp(dev, ++idx))) { 5662 if (ROM32(outp[0]) == 0x00000000) 5663 break; /* seen on an NV11 with DCB v1.5 */ 5664 if (ROM32(outp[0]) == 0xffffffff) 5665 break; /* seen on an NV17 with DCB v2.0 */ 5666 5667 if ((outp[0] & 0x0f) == OUTPUT_UNUSED) 5668 continue; 5669 if ((outp[0] & 0x0f) == OUTPUT_EOL) 5670 break; 5671 5672 ret = exec(dev, data, idx, outp); 5673 if (ret) 5674 return ret; 5675 } 5676 5677 return 0; 5678} 5679 5680u8 * 5681dcb_conntab(struct drm_device *dev) 5682{ 5683 u8 *dcb = dcb_table(dev); 5684 if (dcb && dcb[0] >= 0x30 && dcb[1] >= 0x16) { 5685 u8 *conntab = ROMPTR(dev, dcb[0x14]); 5686 if (conntab && conntab[0] >= 0x30 && conntab[0] <= 0x40) 5687 return conntab; 5688 } 5689 return NULL; 5690} 5691 5692u8 * 5693dcb_conn(struct drm_device *dev, u8 idx) 5694{ 5695 u8 *conntab = dcb_conntab(dev); 5696 if (conntab && idx < conntab[2]) 5697 return conntab + conntab[1] + (idx * conntab[3]); 5698 return NULL; 5699} 5700 5701static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb) 5702{ 5703 struct dcb_entry *entry = &dcb->entry[dcb->entries]; 5704 5705 memset(entry, 0, sizeof(struct dcb_entry)); 5706 entry->index = dcb->entries++; 5707 5708 return entry; 5709} 5710 5711static void fabricate_dcb_output(struct dcb_table *dcb, int type, int i2c, 5712 int heads, int or) 5713{ 5714 struct dcb_entry *entry = new_dcb_entry(dcb); 5715 5716 entry->type = type; 5717 entry->i2c_index = i2c; 5718 entry->heads = heads; 5719 if (type != OUTPUT_ANALOG) 5720 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */ 5721 entry->or = or; 5722} 5723 5724static bool 5725parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb, 5726 uint32_t conn, uint32_t conf, struct dcb_entry *entry) 5727{ 5728 entry->type = conn & 0xf; 5729 entry->i2c_index = (conn >> 4) & 0xf; 5730 entry->heads = (conn >> 8) & 0xf; 5731 entry->connector = (conn >> 12) & 0xf; 5732 entry->bus = (conn >> 16) & 0xf; 5733 entry->location = (conn >> 20) & 0x3; 5734 entry->or = (conn >> 24) & 0xf; 5735 5736 switch (entry->type) { 5737 case OUTPUT_ANALOG: 5738 /* 5739 * Although the rest of a CRT conf dword is usually 5740 * zeros, mac biosen have stuff there so we must mask 5741 */ 5742 entry->crtconf.maxfreq = (dcb->version < 0x30) ? 5743 (conf & 0xffff) * 10 : 5744 (conf & 0xff) * 10000; 5745 break; 5746 case OUTPUT_LVDS: 5747 { 5748 uint32_t mask; 5749 if (conf & 0x1) 5750 entry->lvdsconf.use_straps_for_mode = true; 5751 if (dcb->version < 0x22) { 5752 mask = ~0xd; 5753 /* 5754 * The laptop in bug 14567 lies and claims to not use 5755 * straps when it does, so assume all DCB 2.0 laptops 5756 * use straps, until a broken EDID using one is produced 5757 */ 5758 entry->lvdsconf.use_straps_for_mode = true; 5759 /* 5760 * Both 0x4 and 0x8 show up in v2.0 tables; assume they 5761 * mean the same thing (probably wrong, but might work) 5762 */ 5763 if (conf & 0x4 || conf & 0x8) 5764 entry->lvdsconf.use_power_scripts = true; 5765 } else { 5766 mask = ~0x7; 5767 if (conf & 0x2) 5768 entry->lvdsconf.use_acpi_for_edid = true; 5769 if (conf & 0x4) 5770 entry->lvdsconf.use_power_scripts = true; 5771 entry->lvdsconf.sor.link = (conf & 0x00000030) >> 4; 5772 } 5773 if (conf & mask) { 5774 /* 5775 * Until we even try to use these on G8x, it's 5776 * useless reporting unknown bits. They all are. 5777 */ 5778 if (dcb->version >= 0x40) 5779 break; 5780 5781 NV_ERROR(dev, "Unknown LVDS configuration bits, " 5782 "please report\n"); 5783 } 5784 break; 5785 } 5786 case OUTPUT_TV: 5787 { 5788 if (dcb->version >= 0x30) 5789 entry->tvconf.has_component_output = conf & (0x8 << 4); 5790 else 5791 entry->tvconf.has_component_output = false; 5792 5793 break; 5794 } 5795 case OUTPUT_DP: 5796 entry->dpconf.sor.link = (conf & 0x00000030) >> 4; 5797 switch ((conf & 0x00e00000) >> 21) { 5798 case 0: 5799 entry->dpconf.link_bw = 162000; 5800 break; 5801 default: 5802 entry->dpconf.link_bw = 270000; 5803 break; 5804 } 5805 switch ((conf & 0x0f000000) >> 24) { 5806 case 0xf: 5807 entry->dpconf.link_nr = 4; 5808 break; 5809 case 0x3: 5810 entry->dpconf.link_nr = 2; 5811 break; 5812 default: 5813 entry->dpconf.link_nr = 1; 5814 break; 5815 } 5816 break; 5817 case OUTPUT_TMDS: 5818 if (dcb->version >= 0x40) 5819 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4; 5820 else if (dcb->version >= 0x30) 5821 entry->tmdsconf.slave_addr = (conf & 0x00000700) >> 8; 5822 else if (dcb->version >= 0x22) 5823 entry->tmdsconf.slave_addr = (conf & 0x00000070) >> 4; 5824 5825 break; 5826 case OUTPUT_EOL: 5827 /* weird g80 mobile type that "nv" treats as a terminator */ 5828 dcb->entries--; 5829 return false; 5830 default: 5831 break; 5832 } 5833 5834 if (dcb->version < 0x40) { 5835 /* Normal entries consist of a single bit, but dual link has 5836 * the next most significant bit set too 5837 */ 5838 entry->duallink_possible = 5839 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or); 5840 } else { 5841 entry->duallink_possible = (entry->sorconf.link == 3); 5842 } 5843 5844 /* unsure what DCB version introduces this, 3.0? */ 5845 if (conf & 0x100000) 5846 entry->i2c_upper_default = true; 5847 5848 return true; 5849} 5850 5851static bool 5852parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb, 5853 uint32_t conn, uint32_t conf, struct dcb_entry *entry) 5854{ 5855 switch (conn & 0x0000000f) { 5856 case 0: 5857 entry->type = OUTPUT_ANALOG; 5858 break; 5859 case 1: 5860 entry->type = OUTPUT_TV; 5861 break; 5862 case 2: 5863 case 4: 5864 if (conn & 0x10) 5865 entry->type = OUTPUT_LVDS; 5866 else 5867 entry->type = OUTPUT_TMDS; 5868 break; 5869 case 3: 5870 entry->type = OUTPUT_LVDS; 5871 break; 5872 default: 5873 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f); 5874 return false; 5875 } 5876 5877 entry->i2c_index = (conn & 0x0003c000) >> 14; 5878 entry->heads = ((conn & 0x001c0000) >> 18) + 1; 5879 entry->or = entry->heads; /* same as heads, hopefully safe enough */ 5880 entry->location = (conn & 0x01e00000) >> 21; 5881 entry->bus = (conn & 0x0e000000) >> 25; 5882 entry->duallink_possible = false; 5883 5884 switch (entry->type) { 5885 case OUTPUT_ANALOG: 5886 entry->crtconf.maxfreq = (conf & 0xffff) * 10; 5887 break; 5888 case OUTPUT_TV: 5889 entry->tvconf.has_component_output = false; 5890 break; 5891 case OUTPUT_LVDS: 5892 if ((conn & 0x00003f00) >> 8 != 0x10) 5893 entry->lvdsconf.use_straps_for_mode = true; 5894 entry->lvdsconf.use_power_scripts = true; 5895 break; 5896 default: 5897 break; 5898 } 5899 5900 return true; 5901} 5902 5903static 5904void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb) 5905{ 5906 /* 5907 * DCB v2.0 lists each output combination separately. 5908 * Here we merge compatible entries to have fewer outputs, with 5909 * more options 5910 */ 5911 5912 int i, newentries = 0; 5913 5914 for (i = 0; i < dcb->entries; i++) { 5915 struct dcb_entry *ient = &dcb->entry[i]; 5916 int j; 5917 5918 for (j = i + 1; j < dcb->entries; j++) { 5919 struct dcb_entry *jent = &dcb->entry[j]; 5920 5921 if (jent->type == 100) /* already merged entry */ 5922 continue; 5923 5924 /* merge heads field when all other fields the same */ 5925 if (jent->i2c_index == ient->i2c_index && 5926 jent->type == ient->type && 5927 jent->location == ient->location && 5928 jent->or == ient->or) { 5929 NV_TRACE(dev, "Merging DCB entries %d and %d\n", 5930 i, j); 5931 ient->heads |= jent->heads; 5932 jent->type = 100; /* dummy value */ 5933 } 5934 } 5935 } 5936 5937 /* Compact entries merged into others out of dcb */ 5938 for (i = 0; i < dcb->entries; i++) { 5939 if (dcb->entry[i].type == 100) 5940 continue; 5941 5942 if (newentries != i) { 5943 dcb->entry[newentries] = dcb->entry[i]; 5944 dcb->entry[newentries].index = newentries; 5945 } 5946 newentries++; 5947 } 5948 5949 dcb->entries = newentries; 5950} 5951 5952static bool 5953apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf) 5954{ 5955 struct drm_nouveau_private *dev_priv = dev->dev_private; 5956 struct dcb_table *dcb = &dev_priv->vbios.dcb; 5957 5958 /* Dell Precision M6300 5959 * DCB entry 2: 02025312 00000010 5960 * DCB entry 3: 02026312 00000020 5961 * 5962 * Identical, except apparently a different connector on a 5963 * different SOR link. Not a clue how we're supposed to know 5964 * which one is in use if it even shares an i2c line... 5965 * 5966 * Ignore the connector on the second SOR link to prevent 5967 * nasty problems until this is sorted (assuming it's not a 5968 * VBIOS bug). 5969 */ 5970 if (nv_match_device(dev, 0x040d, 0x1028, 0x019b)) { 5971 if (*conn == 0x02026312 && *conf == 0x00000020) 5972 return false; 5973 } 5974 5975 /* GeForce3 Ti 200 5976 * 5977 * DCB reports an LVDS output that should be TMDS: 5978 * DCB entry 1: f2005014 ffffffff 5979 */ 5980 if (nv_match_device(dev, 0x0201, 0x1462, 0x8851)) { 5981 if (*conn == 0xf2005014 && *conf == 0xffffffff) { 5982 fabricate_dcb_output(dcb, OUTPUT_TMDS, 1, 1, 1); 5983 return false; 5984 } 5985 } 5986 5987 /* XFX GT-240X-YA 5988 * 5989 * So many things wrong here, replace the entire encoder table.. 5990 */ 5991 if (nv_match_device(dev, 0x0ca3, 0x1682, 0x3003)) { 5992 if (idx == 0) { 5993 *conn = 0x02001300; /* VGA, connector 1 */ 5994 *conf = 0x00000028; 5995 } else 5996 if (idx == 1) { 5997 *conn = 0x01010312; /* DVI, connector 0 */ 5998 *conf = 0x00020030; 5999 } else 6000 if (idx == 2) { 6001 *conn = 0x01010310; /* VGA, connector 0 */ 6002 *conf = 0x00000028; 6003 } else 6004 if (idx == 3) { 6005 *conn = 0x02022362; /* HDMI, connector 2 */ 6006 *conf = 0x00020010; 6007 } else { 6008 *conn = 0x0000000e; /* EOL */ 6009 *conf = 0x00000000; 6010 } 6011 } 6012 6013 /* Some other twisted XFX board (rhbz#694914) 6014 * 6015 * The DVI/VGA encoder combo that's supposed to represent the 6016 * DVI-I connector actually point at two different ones, and 6017 * the HDMI connector ends up paired with the VGA instead. 6018 * 6019 * Connector table is missing anything for VGA at all, pointing it 6020 * an invalid conntab entry 2 so we figure it out ourself. 6021 */ 6022 if (nv_match_device(dev, 0x0615, 0x1682, 0x2605)) { 6023 if (idx == 0) { 6024 *conn = 0x02002300; /* VGA, connector 2 */ 6025 *conf = 0x00000028; 6026 } else 6027 if (idx == 1) { 6028 *conn = 0x01010312; /* DVI, connector 0 */ 6029 *conf = 0x00020030; 6030 } else 6031 if (idx == 2) { 6032 *conn = 0x04020310; /* VGA, connector 0 */ 6033 *conf = 0x00000028; 6034 } else 6035 if (idx == 3) { 6036 *conn = 0x02021322; /* HDMI, connector 1 */ 6037 *conf = 0x00020010; 6038 } else { 6039 *conn = 0x0000000e; /* EOL */ 6040 *conf = 0x00000000; 6041 } 6042 } 6043 6044 return true; 6045} 6046 6047static void 6048fabricate_dcb_encoder_table(struct drm_device *dev, struct nvbios *bios) 6049{ 6050 struct dcb_table *dcb = &bios->dcb; 6051 int all_heads = (nv_two_heads(dev) ? 3 : 1); 6052 6053#ifdef __powerpc__ 6054 /* Apple iMac G4 NV17 */ 6055 if (of_machine_is_compatible("PowerMac4,5")) { 6056 fabricate_dcb_output(dcb, OUTPUT_TMDS, 0, all_heads, 1); 6057 fabricate_dcb_output(dcb, OUTPUT_ANALOG, 1, all_heads, 2); 6058 return; 6059 } 6060#endif 6061 6062 /* Make up some sane defaults */ 6063 fabricate_dcb_output(dcb, OUTPUT_ANALOG, 6064 bios->legacy.i2c_indices.crt, 1, 1); 6065 6066 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0) 6067 fabricate_dcb_output(dcb, OUTPUT_TV, 6068 bios->legacy.i2c_indices.tv, 6069 all_heads, 0); 6070 6071 else if (bios->tmds.output0_script_ptr || 6072 bios->tmds.output1_script_ptr) 6073 fabricate_dcb_output(dcb, OUTPUT_TMDS, 6074 bios->legacy.i2c_indices.panel, 6075 all_heads, 1); 6076} 6077 6078static int 6079parse_dcb_entry(struct drm_device *dev, void *data, int idx, u8 *outp) 6080{ 6081 struct drm_nouveau_private *dev_priv = dev->dev_private; 6082 struct dcb_table *dcb = &dev_priv->vbios.dcb; 6083 u32 conf = (dcb->version >= 0x20) ? ROM32(outp[4]) : ROM32(outp[6]); 6084 u32 conn = ROM32(outp[0]); 6085 bool ret; 6086 6087 if (apply_dcb_encoder_quirks(dev, idx, &conn, &conf)) { 6088 struct dcb_entry *entry = new_dcb_entry(dcb); 6089 6090 NV_TRACEWARN(dev, "DCB outp %02d: %08x %08x\n", idx, conn, conf); 6091 6092 if (dcb->version >= 0x20) 6093 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry); 6094 else 6095 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry); 6096 if (!ret) 6097 return 1; /* stop parsing */ 6098 6099 /* Ignore the I2C index for on-chip TV-out, as there 6100 * are cards with bogus values (nv31m in bug 23212), 6101 * and it's otherwise useless. 6102 */ 6103 if (entry->type == OUTPUT_TV && 6104 entry->location == DCB_LOC_ON_CHIP) 6105 entry->i2c_index = 0x0f; 6106 } 6107 6108 return 0; 6109} 6110 6111static void 6112dcb_fake_connectors(struct nvbios *bios) 6113{ 6114 struct dcb_table *dcbt = &bios->dcb; 6115 u8 map[16] = { }; 6116 int i, idx = 0; 6117 6118 /* heuristic: if we ever get a non-zero connector field, assume 6119 * that all the indices are valid and we don't need fake them. 6120 */ 6121 for (i = 0; i < dcbt->entries; i++) { 6122 if (dcbt->entry[i].connector) 6123 return; 6124 } 6125 6126 /* no useful connector info available, we need to make it up 6127 * ourselves. the rule here is: anything on the same i2c bus 6128 * is considered to be on the same connector. any output 6129 * without an associated i2c bus is assigned its own unique 6130 * connector index. 6131 */ 6132 for (i = 0; i < dcbt->entries; i++) { 6133 u8 i2c = dcbt->entry[i].i2c_index; 6134 if (i2c == 0x0f) { 6135 dcbt->entry[i].connector = idx++; 6136 } else { 6137 if (!map[i2c]) 6138 map[i2c] = ++idx; 6139 dcbt->entry[i].connector = map[i2c] - 1; 6140 } 6141 } 6142 6143 /* if we created more than one connector, destroy the connector 6144 * table - just in case it has random, rather than stub, entries. 6145 */ 6146 if (i > 1) { 6147 u8 *conntab = dcb_conntab(bios->dev); 6148 if (conntab) 6149 conntab[0] = 0x00; 6150 } 6151} 6152 6153static int 6154parse_dcb_table(struct drm_device *dev, struct nvbios *bios) 6155{ 6156 struct dcb_table *dcb = &bios->dcb; 6157 u8 *dcbt, *conn; 6158 int idx; 6159 6160 dcbt = dcb_table(dev); 6161 if (!dcbt) { 6162 /* handle pre-DCB boards */ 6163 if (bios->type == NVBIOS_BMP) { 6164 fabricate_dcb_encoder_table(dev, bios); 6165 return 0; 6166 } 6167 6168 return -EINVAL; 6169 } 6170 6171 NV_TRACE(dev, "DCB version %d.%d\n", dcbt[0] >> 4, dcbt[0] & 0xf); 6172 6173 dcb->version = dcbt[0]; 6174 dcb_outp_foreach(dev, NULL, parse_dcb_entry); 6175 6176 /* 6177 * apart for v2.1+ not being known for requiring merging, this 6178 * guarantees dcbent->index is the index of the entry in the rom image 6179 */ 6180 if (dcb->version < 0x21) 6181 merge_like_dcb_entries(dev, dcb); 6182 6183 if (!dcb->entries) 6184 return -ENXIO; 6185 6186 /* dump connector table entries to log, if any exist */ 6187 idx = -1; 6188 while ((conn = dcb_conn(dev, ++idx))) { 6189 if (conn[0] != 0xff) { 6190 NV_TRACE(dev, "DCB conn %02d: ", idx); 6191 if (dcb_conntab(dev)[3] < 4) 6192 printk("%04x\n", ROM16(conn[0])); 6193 else 6194 printk("%08x\n", ROM32(conn[0])); 6195 } 6196 } 6197 dcb_fake_connectors(bios); 6198 return 0; 6199} 6200 6201static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry) 6202{ 6203 /* 6204 * The header following the "HWSQ" signature has the number of entries, 6205 * and the entry size 6206 * 6207 * An entry consists of a dword to write to the sequencer control reg 6208 * (0x00001304), followed by the ucode bytes, written sequentially, 6209 * starting at reg 0x00001400 6210 */ 6211 6212 uint8_t bytes_to_write; 6213 uint16_t hwsq_entry_offset; 6214 int i; 6215 6216 if (bios->data[hwsq_offset] <= entry) { 6217 NV_ERROR(dev, "Too few entries in HW sequencer table for " 6218 "requested entry\n"); 6219 return -ENOENT; 6220 } 6221 6222 bytes_to_write = bios->data[hwsq_offset + 1]; 6223 6224 if (bytes_to_write != 36) { 6225 NV_ERROR(dev, "Unknown HW sequencer entry size\n"); 6226 return -EINVAL; 6227 } 6228 6229 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n"); 6230 6231 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write; 6232 6233 /* set sequencer control */ 6234 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset])); 6235 bytes_to_write -= 4; 6236 6237 /* write ucode */ 6238 for (i = 0; i < bytes_to_write; i += 4) 6239 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4])); 6240 6241 /* twiddle NV_PBUS_DEBUG_4 */ 6242 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18); 6243 6244 return 0; 6245} 6246 6247static int load_nv17_hw_sequencer_ucode(struct drm_device *dev, 6248 struct nvbios *bios) 6249{ 6250 /* 6251 * BMP based cards, from NV17, need a microcode loading to correctly 6252 * control the GPIO etc for LVDS panels 6253 * 6254 * BIT based cards seem to do this directly in the init scripts 6255 * 6256 * The microcode entries are found by the "HWSQ" signature. 6257 */ 6258 6259 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' }; 6260 const int sz = sizeof(hwsq_signature); 6261 int hwsq_offset; 6262 6263 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz); 6264 if (!hwsq_offset) 6265 return 0; 6266 6267 /* always use entry 0? */ 6268 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0); 6269} 6270 6271uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev) 6272{ 6273 struct drm_nouveau_private *dev_priv = dev->dev_private; 6274 struct nvbios *bios = &dev_priv->vbios; 6275 const uint8_t edid_sig[] = { 6276 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 }; 6277 uint16_t offset = 0; 6278 uint16_t newoffset; 6279 int searchlen = NV_PROM_SIZE; 6280 6281 if (bios->fp.edid) 6282 return bios->fp.edid; 6283 6284 while (searchlen) { 6285 newoffset = findstr(&bios->data[offset], searchlen, 6286 edid_sig, 8); 6287 if (!newoffset) 6288 return NULL; 6289 offset += newoffset; 6290 if (!nv_cksum(&bios->data[offset], EDID1_LEN)) 6291 break; 6292 6293 searchlen -= offset; 6294 offset++; 6295 } 6296 6297 NV_TRACE(dev, "Found EDID in BIOS\n"); 6298 6299 return bios->fp.edid = &bios->data[offset]; 6300} 6301 6302void 6303nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table, 6304 struct dcb_entry *dcbent, int crtc) 6305{ 6306 struct drm_nouveau_private *dev_priv = dev->dev_private; 6307 struct nvbios *bios = &dev_priv->vbios; 6308 struct init_exec iexec = { true, false }; 6309 6310 spin_lock_bh(&bios->lock); 6311 bios->display.output = dcbent; 6312 bios->display.crtc = crtc; 6313 parse_init_table(bios, table, &iexec); 6314 bios->display.output = NULL; 6315 spin_unlock_bh(&bios->lock); 6316} 6317 6318void 6319nouveau_bios_init_exec(struct drm_device *dev, uint16_t table) 6320{ 6321 struct drm_nouveau_private *dev_priv = dev->dev_private; 6322 struct nvbios *bios = &dev_priv->vbios; 6323 struct init_exec iexec = { true, false }; 6324 6325 parse_init_table(bios, table, &iexec); 6326} 6327 6328static bool NVInitVBIOS(struct drm_device *dev) 6329{ 6330 struct drm_nouveau_private *dev_priv = dev->dev_private; 6331 struct nvbios *bios = &dev_priv->vbios; 6332 6333 memset(bios, 0, sizeof(struct nvbios)); 6334 spin_lock_init(&bios->lock); 6335 bios->dev = dev; 6336 6337 if (!NVShadowVBIOS(dev, bios->data)) 6338 return false; 6339 6340 bios->length = NV_PROM_SIZE; 6341 return true; 6342} 6343 6344static int nouveau_parse_vbios_struct(struct drm_device *dev) 6345{ 6346 struct drm_nouveau_private *dev_priv = dev->dev_private; 6347 struct nvbios *bios = &dev_priv->vbios; 6348 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' }; 6349 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 }; 6350 int offset; 6351 6352 offset = findstr(bios->data, bios->length, 6353 bit_signature, sizeof(bit_signature)); 6354 if (offset) { 6355 NV_TRACE(dev, "BIT BIOS found\n"); 6356 bios->type = NVBIOS_BIT; 6357 bios->offset = offset; 6358 return parse_bit_structure(bios, offset + 6); 6359 } 6360 6361 offset = findstr(bios->data, bios->length, 6362 bmp_signature, sizeof(bmp_signature)); 6363 if (offset) { 6364 NV_TRACE(dev, "BMP BIOS found\n"); 6365 bios->type = NVBIOS_BMP; 6366 bios->offset = offset; 6367 return parse_bmp_structure(dev, bios, offset); 6368 } 6369 6370 NV_ERROR(dev, "No known BIOS signature found\n"); 6371 return -ENODEV; 6372} 6373 6374int 6375nouveau_run_vbios_init(struct drm_device *dev) 6376{ 6377 struct drm_nouveau_private *dev_priv = dev->dev_private; 6378 struct nvbios *bios = &dev_priv->vbios; 6379 int i, ret = 0; 6380 6381 /* Reset the BIOS head to 0. */ 6382 bios->state.crtchead = 0; 6383 6384 if (bios->major_version < 5) /* BMP only */ 6385 load_nv17_hw_sequencer_ucode(dev, bios); 6386 6387 if (bios->execute) { 6388 bios->fp.last_script_invoc = 0; 6389 bios->fp.lvds_init_run = false; 6390 } 6391 6392 parse_init_tables(bios); 6393 6394 /* 6395 * Runs some additional script seen on G8x VBIOSen. The VBIOS' 6396 * parser will run this right after the init tables, the binary 6397 * driver appears to run it at some point later. 6398 */ 6399 if (bios->some_script_ptr) { 6400 struct init_exec iexec = {true, false}; 6401 6402 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n", 6403 bios->some_script_ptr); 6404 parse_init_table(bios, bios->some_script_ptr, &iexec); 6405 } 6406 6407 if (dev_priv->card_type >= NV_50) { 6408 for (i = 0; i < bios->dcb.entries; i++) { 6409 nouveau_bios_run_display_table(dev, 0, 0, 6410 &bios->dcb.entry[i], -1); 6411 } 6412 } 6413 6414 return ret; 6415} 6416 6417static bool 6418nouveau_bios_posted(struct drm_device *dev) 6419{ 6420 struct drm_nouveau_private *dev_priv = dev->dev_private; 6421 unsigned htotal; 6422 6423 if (dev_priv->card_type >= NV_50) { 6424 if (NVReadVgaCrtc(dev, 0, 0x00) == 0 && 6425 NVReadVgaCrtc(dev, 0, 0x1a) == 0) 6426 return false; 6427 return true; 6428 } 6429 6430 htotal = NVReadVgaCrtc(dev, 0, 0x06); 6431 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8; 6432 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4; 6433 htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10; 6434 htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11; 6435 6436 return (htotal != 0); 6437} 6438 6439int 6440nouveau_bios_init(struct drm_device *dev) 6441{ 6442 struct drm_nouveau_private *dev_priv = dev->dev_private; 6443 struct nvbios *bios = &dev_priv->vbios; 6444 int ret; 6445 6446 if (!NVInitVBIOS(dev)) 6447 return -ENODEV; 6448 6449 ret = nouveau_parse_vbios_struct(dev); 6450 if (ret) 6451 return ret; 6452 6453 ret = nouveau_i2c_init(dev); 6454 if (ret) 6455 return ret; 6456 6457 ret = nouveau_mxm_init(dev); 6458 if (ret) 6459 return ret; 6460 6461 ret = parse_dcb_table(dev, bios); 6462 if (ret) 6463 return ret; 6464 6465 if (!bios->major_version) /* we don't run version 0 bios */ 6466 return 0; 6467 6468 /* init script execution disabled */ 6469 bios->execute = false; 6470 6471 /* ... unless card isn't POSTed already */ 6472 if (!nouveau_bios_posted(dev)) { 6473 NV_INFO(dev, "Adaptor not initialised, " 6474 "running VBIOS init tables.\n"); 6475 bios->execute = true; 6476 } 6477 if (nouveau_force_post) 6478 bios->execute = true; 6479 6480 ret = nouveau_run_vbios_init(dev); 6481 if (ret) 6482 return ret; 6483 6484 /* feature_byte on BMP is poor, but init always sets CR4B */ 6485 if (bios->major_version < 5) 6486 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40; 6487 6488 /* all BIT systems need p_f_m_t for digital_min_front_porch */ 6489 if (bios->is_mobile || bios->major_version >= 5) 6490 ret = parse_fp_mode_table(dev, bios); 6491 6492 /* allow subsequent scripts to execute */ 6493 bios->execute = true; 6494 6495 return 0; 6496} 6497 6498void 6499nouveau_bios_takedown(struct drm_device *dev) 6500{ 6501 nouveau_mxm_fini(dev); 6502 nouveau_i2c_fini(dev); 6503} 6504