nouveau_bios.c revision 0746b5da53af533e3e525aeea47d1020c8f99c67
1/* 2 * Copyright 2005-2006 Erik Waling 3 * Copyright 2006 Stephane Marchesin 4 * Copyright 2007-2009 Stuart Bennett 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 25#include "drmP.h" 26#define NV_DEBUG_NOTRACE 27#include "nouveau_drv.h" 28#include "nouveau_hw.h" 29#include "nouveau_encoder.h" 30 31#include <linux/io-mapping.h> 32 33/* these defines are made up */ 34#define NV_CIO_CRE_44_HEADA 0x0 35#define NV_CIO_CRE_44_HEADB 0x3 36#define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */ 37#define LEGACY_I2C_CRT 0x80 38#define LEGACY_I2C_PANEL 0x81 39#define LEGACY_I2C_TV 0x82 40 41#define EDID1_LEN 128 42 43#define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg) 44#define LOG_OLD_VALUE(x) 45 46#define ROM16(x) le16_to_cpu(*(uint16_t *)&(x)) 47#define ROM32(x) le32_to_cpu(*(uint32_t *)&(x)) 48 49struct init_exec { 50 bool execute; 51 bool repeat; 52}; 53 54static bool nv_cksum(const uint8_t *data, unsigned int length) 55{ 56 /* 57 * There's a few checksums in the BIOS, so here's a generic checking 58 * function. 59 */ 60 int i; 61 uint8_t sum = 0; 62 63 for (i = 0; i < length; i++) 64 sum += data[i]; 65 66 if (sum) 67 return true; 68 69 return false; 70} 71 72static int 73score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable) 74{ 75 if (!(data[0] == 0x55 && data[1] == 0xAA)) { 76 NV_TRACEWARN(dev, "... BIOS signature not found\n"); 77 return 0; 78 } 79 80 if (nv_cksum(data, data[2] * 512)) { 81 NV_TRACEWARN(dev, "... BIOS checksum invalid\n"); 82 /* if a ro image is somewhat bad, it's probably all rubbish */ 83 return writeable ? 2 : 1; 84 } else 85 NV_TRACE(dev, "... appears to be valid\n"); 86 87 return 3; 88} 89 90static void load_vbios_prom(struct drm_device *dev, uint8_t *data) 91{ 92 struct drm_nouveau_private *dev_priv = dev->dev_private; 93 uint32_t pci_nv_20, save_pci_nv_20; 94 int pcir_ptr; 95 int i; 96 97 if (dev_priv->card_type >= NV_50) 98 pci_nv_20 = 0x88050; 99 else 100 pci_nv_20 = NV_PBUS_PCI_NV_20; 101 102 /* enable ROM access */ 103 save_pci_nv_20 = nvReadMC(dev, pci_nv_20); 104 nvWriteMC(dev, pci_nv_20, 105 save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED); 106 107 /* bail if no rom signature */ 108 if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 || 109 nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa) 110 goto out; 111 112 /* additional check (see note below) - read PCI record header */ 113 pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) | 114 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8; 115 if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' || 116 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' || 117 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' || 118 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R') 119 goto out; 120 121 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a 122 * a good read may be obtained by waiting or re-reading (cargocult: 5x) 123 * each byte. we'll hope pramin has something usable instead 124 */ 125 for (i = 0; i < NV_PROM_SIZE; i++) 126 data[i] = nv_rd08(dev, NV_PROM_OFFSET + i); 127 128out: 129 /* disable ROM access */ 130 nvWriteMC(dev, pci_nv_20, 131 save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED); 132} 133 134static void load_vbios_pramin(struct drm_device *dev, uint8_t *data) 135{ 136 struct drm_nouveau_private *dev_priv = dev->dev_private; 137 uint32_t old_bar0_pramin = 0; 138 int i; 139 140 if (dev_priv->card_type >= NV_50) { 141 uint32_t vbios_vram = (nv_rd32(dev, 0x619f04) & ~0xff) << 8; 142 143 if (!vbios_vram) 144 vbios_vram = (nv_rd32(dev, 0x1700) << 16) + 0xf0000; 145 146 old_bar0_pramin = nv_rd32(dev, 0x1700); 147 nv_wr32(dev, 0x1700, vbios_vram >> 16); 148 } 149 150 /* bail if no rom signature */ 151 if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 || 152 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa) 153 goto out; 154 155 for (i = 0; i < NV_PROM_SIZE; i++) 156 data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i); 157 158out: 159 if (dev_priv->card_type >= NV_50) 160 nv_wr32(dev, 0x1700, old_bar0_pramin); 161} 162 163static void load_vbios_pci(struct drm_device *dev, uint8_t *data) 164{ 165 void __iomem *rom = NULL; 166 size_t rom_len; 167 int ret; 168 169 ret = pci_enable_rom(dev->pdev); 170 if (ret) 171 return; 172 173 rom = pci_map_rom(dev->pdev, &rom_len); 174 if (!rom) 175 goto out; 176 memcpy_fromio(data, rom, rom_len); 177 pci_unmap_rom(dev->pdev, rom); 178 179out: 180 pci_disable_rom(dev->pdev); 181} 182 183static void load_vbios_acpi(struct drm_device *dev, uint8_t *data) 184{ 185 int i; 186 int ret; 187 int size = 64 * 1024; 188 189 if (!nouveau_acpi_rom_supported(dev->pdev)) 190 return; 191 192 for (i = 0; i < (size / ROM_BIOS_PAGE); i++) { 193 ret = nouveau_acpi_get_bios_chunk(data, 194 (i * ROM_BIOS_PAGE), 195 ROM_BIOS_PAGE); 196 if (ret <= 0) 197 break; 198 } 199 return; 200} 201 202struct methods { 203 const char desc[8]; 204 void (*loadbios)(struct drm_device *, uint8_t *); 205 const bool rw; 206}; 207 208static struct methods shadow_methods[] = { 209 { "PRAMIN", load_vbios_pramin, true }, 210 { "PROM", load_vbios_prom, false }, 211 { "PCIROM", load_vbios_pci, true }, 212 { "ACPI", load_vbios_acpi, true }, 213}; 214#define NUM_SHADOW_METHODS ARRAY_SIZE(shadow_methods) 215 216static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data) 217{ 218 struct methods *methods = shadow_methods; 219 int testscore = 3; 220 int scores[NUM_SHADOW_METHODS], i; 221 222 if (nouveau_vbios) { 223 for (i = 0; i < NUM_SHADOW_METHODS; i++) 224 if (!strcasecmp(nouveau_vbios, methods[i].desc)) 225 break; 226 227 if (i < NUM_SHADOW_METHODS) { 228 NV_INFO(dev, "Attempting to use BIOS image from %s\n", 229 methods[i].desc); 230 231 methods[i].loadbios(dev, data); 232 if (score_vbios(dev, data, methods[i].rw)) 233 return true; 234 } 235 236 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios); 237 } 238 239 for (i = 0; i < NUM_SHADOW_METHODS; i++) { 240 NV_TRACE(dev, "Attempting to load BIOS image from %s\n", 241 methods[i].desc); 242 data[0] = data[1] = 0; /* avoid reuse of previous image */ 243 methods[i].loadbios(dev, data); 244 scores[i] = score_vbios(dev, data, methods[i].rw); 245 if (scores[i] == testscore) 246 return true; 247 } 248 249 while (--testscore > 0) { 250 for (i = 0; i < NUM_SHADOW_METHODS; i++) { 251 if (scores[i] == testscore) { 252 NV_TRACE(dev, "Using BIOS image from %s\n", 253 methods[i].desc); 254 methods[i].loadbios(dev, data); 255 return true; 256 } 257 } 258 } 259 260 NV_ERROR(dev, "No valid BIOS image found\n"); 261 return false; 262} 263 264struct init_tbl_entry { 265 char *name; 266 uint8_t id; 267 /* Return: 268 * > 0: success, length of opcode 269 * 0: success, but abort further parsing of table (INIT_DONE etc) 270 * < 0: failure, table parsing will be aborted 271 */ 272 int (*handler)(struct nvbios *, uint16_t, struct init_exec *); 273}; 274 275struct bit_entry { 276 uint8_t id[2]; 277 uint16_t length; 278 uint16_t offset; 279}; 280 281static int parse_init_table(struct nvbios *, unsigned int, struct init_exec *); 282 283#define MACRO_INDEX_SIZE 2 284#define MACRO_SIZE 8 285#define CONDITION_SIZE 12 286#define IO_FLAG_CONDITION_SIZE 9 287#define IO_CONDITION_SIZE 5 288#define MEM_INIT_SIZE 66 289 290static void still_alive(void) 291{ 292#if 0 293 sync(); 294 msleep(2); 295#endif 296} 297 298static uint32_t 299munge_reg(struct nvbios *bios, uint32_t reg) 300{ 301 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 302 struct dcb_entry *dcbent = bios->display.output; 303 304 if (dev_priv->card_type < NV_50) 305 return reg; 306 307 if (reg & 0x40000000) { 308 BUG_ON(!dcbent); 309 310 reg += (ffs(dcbent->or) - 1) * 0x800; 311 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1)) 312 reg += 0x00000080; 313 } 314 315 reg &= ~0x60000000; 316 return reg; 317} 318 319static int 320valid_reg(struct nvbios *bios, uint32_t reg) 321{ 322 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 323 struct drm_device *dev = bios->dev; 324 325 /* C51 has misaligned regs on purpose. Marvellous */ 326 if (reg & 0x2 || 327 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51)) 328 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg); 329 330 /* warn on C51 regs that haven't been verified accessible in tracing */ 331 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 && 332 reg != 0x130d && reg != 0x1311 && reg != 0x60081d) 333 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n", 334 reg); 335 336 if (reg >= (8*1024*1024)) { 337 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg); 338 return 0; 339 } 340 341 return 1; 342} 343 344static bool 345valid_idx_port(struct nvbios *bios, uint16_t port) 346{ 347 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 348 struct drm_device *dev = bios->dev; 349 350 /* 351 * If adding more ports here, the read/write functions below will need 352 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is 353 * used for the port in question 354 */ 355 if (dev_priv->card_type < NV_50) { 356 if (port == NV_CIO_CRX__COLOR) 357 return true; 358 if (port == NV_VIO_SRX) 359 return true; 360 } else { 361 if (port == NV_CIO_CRX__COLOR) 362 return true; 363 } 364 365 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n", 366 port); 367 368 return false; 369} 370 371static bool 372valid_port(struct nvbios *bios, uint16_t port) 373{ 374 struct drm_device *dev = bios->dev; 375 376 /* 377 * If adding more ports here, the read/write functions below will need 378 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is 379 * used for the port in question 380 */ 381 if (port == NV_VIO_VSE2) 382 return true; 383 384 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port); 385 386 return false; 387} 388 389static uint32_t 390bios_rd32(struct nvbios *bios, uint32_t reg) 391{ 392 uint32_t data; 393 394 reg = munge_reg(bios, reg); 395 if (!valid_reg(bios, reg)) 396 return 0; 397 398 /* 399 * C51 sometimes uses regs with bit0 set in the address. For these 400 * cases there should exist a translation in a BIOS table to an IO 401 * port address which the BIOS uses for accessing the reg 402 * 403 * These only seem to appear for the power control regs to a flat panel, 404 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs 405 * for 0x1308 and 0x1310 are used - hence the mask below. An S3 406 * suspend-resume mmio trace from a C51 will be required to see if this 407 * is true for the power microcode in 0x14.., or whether the direct IO 408 * port access method is needed 409 */ 410 if (reg & 0x1) 411 reg &= ~0x1; 412 413 data = nv_rd32(bios->dev, reg); 414 415 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data); 416 417 return data; 418} 419 420static void 421bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data) 422{ 423 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 424 425 reg = munge_reg(bios, reg); 426 if (!valid_reg(bios, reg)) 427 return; 428 429 /* see note in bios_rd32 */ 430 if (reg & 0x1) 431 reg &= 0xfffffffe; 432 433 LOG_OLD_VALUE(bios_rd32(bios, reg)); 434 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data); 435 436 if (dev_priv->vbios.execute) { 437 still_alive(); 438 nv_wr32(bios->dev, reg, data); 439 } 440} 441 442static uint8_t 443bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index) 444{ 445 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 446 struct drm_device *dev = bios->dev; 447 uint8_t data; 448 449 if (!valid_idx_port(bios, port)) 450 return 0; 451 452 if (dev_priv->card_type < NV_50) { 453 if (port == NV_VIO_SRX) 454 data = NVReadVgaSeq(dev, bios->state.crtchead, index); 455 else /* assume NV_CIO_CRX__COLOR */ 456 data = NVReadVgaCrtc(dev, bios->state.crtchead, index); 457 } else { 458 uint32_t data32; 459 460 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3)); 461 data = (data32 >> ((index & 3) << 3)) & 0xff; 462 } 463 464 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, " 465 "Head: 0x%02X, Data: 0x%02X\n", 466 port, index, bios->state.crtchead, data); 467 return data; 468} 469 470static void 471bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data) 472{ 473 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 474 struct drm_device *dev = bios->dev; 475 476 if (!valid_idx_port(bios, port)) 477 return; 478 479 /* 480 * The current head is maintained in the nvbios member state.crtchead. 481 * We trap changes to CR44 and update the head variable and hence the 482 * register set written. 483 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance 484 * of the write, and to head1 after the write 485 */ 486 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 && 487 data != NV_CIO_CRE_44_HEADB) 488 bios->state.crtchead = 0; 489 490 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index)); 491 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, " 492 "Head: 0x%02X, Data: 0x%02X\n", 493 port, index, bios->state.crtchead, data); 494 495 if (bios->execute && dev_priv->card_type < NV_50) { 496 still_alive(); 497 if (port == NV_VIO_SRX) 498 NVWriteVgaSeq(dev, bios->state.crtchead, index, data); 499 else /* assume NV_CIO_CRX__COLOR */ 500 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data); 501 } else 502 if (bios->execute) { 503 uint32_t data32, shift = (index & 3) << 3; 504 505 still_alive(); 506 507 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3)); 508 data32 &= ~(0xff << shift); 509 data32 |= (data << shift); 510 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32); 511 } 512 513 if (port == NV_CIO_CRX__COLOR && 514 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB) 515 bios->state.crtchead = 1; 516} 517 518static uint8_t 519bios_port_rd(struct nvbios *bios, uint16_t port) 520{ 521 uint8_t data, head = bios->state.crtchead; 522 523 if (!valid_port(bios, port)) 524 return 0; 525 526 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port); 527 528 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n", 529 port, head, data); 530 531 return data; 532} 533 534static void 535bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data) 536{ 537 int head = bios->state.crtchead; 538 539 if (!valid_port(bios, port)) 540 return; 541 542 LOG_OLD_VALUE(bios_port_rd(bios, port)); 543 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n", 544 port, head, data); 545 546 if (!bios->execute) 547 return; 548 549 still_alive(); 550 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data); 551} 552 553static bool 554io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 555{ 556 /* 557 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte 558 * for the CRTC index; 1 byte for the mask to apply to the value 559 * retrieved from the CRTC; 1 byte for the shift right to apply to the 560 * masked CRTC value; 2 bytes for the offset to the flag array, to 561 * which the shifted value is added; 1 byte for the mask applied to the 562 * value read from the flag array; and 1 byte for the value to compare 563 * against the masked byte from the flag table. 564 */ 565 566 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE; 567 uint16_t crtcport = ROM16(bios->data[condptr]); 568 uint8_t crtcindex = bios->data[condptr + 2]; 569 uint8_t mask = bios->data[condptr + 3]; 570 uint8_t shift = bios->data[condptr + 4]; 571 uint16_t flagarray = ROM16(bios->data[condptr + 5]); 572 uint8_t flagarraymask = bios->data[condptr + 7]; 573 uint8_t cmpval = bios->data[condptr + 8]; 574 uint8_t data; 575 576 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 577 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, " 578 "Cmpval: 0x%02X\n", 579 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval); 580 581 data = bios_idxprt_rd(bios, crtcport, crtcindex); 582 583 data = bios->data[flagarray + ((data & mask) >> shift)]; 584 data &= flagarraymask; 585 586 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n", 587 offset, data, cmpval); 588 589 return (data == cmpval); 590} 591 592static bool 593bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 594{ 595 /* 596 * The condition table entry has 4 bytes for the address of the 597 * register to check, 4 bytes for a mask to apply to the register and 598 * 4 for a test comparison value 599 */ 600 601 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE; 602 uint32_t reg = ROM32(bios->data[condptr]); 603 uint32_t mask = ROM32(bios->data[condptr + 4]); 604 uint32_t cmpval = ROM32(bios->data[condptr + 8]); 605 uint32_t data; 606 607 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n", 608 offset, cond, reg, mask); 609 610 data = bios_rd32(bios, reg) & mask; 611 612 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n", 613 offset, data, cmpval); 614 615 return (data == cmpval); 616} 617 618static bool 619io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 620{ 621 /* 622 * The IO condition entry has 2 bytes for the IO port address; 1 byte 623 * for the index to write to io_port; 1 byte for the mask to apply to 624 * the byte read from io_port+1; and 1 byte for the value to compare 625 * against the masked byte. 626 */ 627 628 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE; 629 uint16_t io_port = ROM16(bios->data[condptr]); 630 uint8_t port_index = bios->data[condptr + 2]; 631 uint8_t mask = bios->data[condptr + 3]; 632 uint8_t cmpval = bios->data[condptr + 4]; 633 634 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask; 635 636 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n", 637 offset, data, cmpval); 638 639 return (data == cmpval); 640} 641 642static int 643nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk) 644{ 645 struct drm_nouveau_private *dev_priv = dev->dev_private; 646 uint32_t reg0 = nv_rd32(dev, reg + 0); 647 uint32_t reg1 = nv_rd32(dev, reg + 4); 648 struct nouveau_pll_vals pll; 649 struct pll_lims pll_limits; 650 int ret; 651 652 ret = get_pll_limits(dev, reg, &pll_limits); 653 if (ret) 654 return ret; 655 656 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll); 657 if (!clk) 658 return -ERANGE; 659 660 reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16); 661 reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1; 662 663 if (dev_priv->vbios.execute) { 664 still_alive(); 665 nv_wr32(dev, reg + 4, reg1); 666 nv_wr32(dev, reg + 0, reg0); 667 } 668 669 return 0; 670} 671 672static int 673setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk) 674{ 675 struct drm_device *dev = bios->dev; 676 struct drm_nouveau_private *dev_priv = dev->dev_private; 677 /* clk in kHz */ 678 struct pll_lims pll_lim; 679 struct nouveau_pll_vals pllvals; 680 int ret; 681 682 if (dev_priv->card_type >= NV_50) 683 return nv50_pll_set(dev, reg, clk); 684 685 /* high regs (such as in the mac g5 table) are not -= 4 */ 686 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim); 687 if (ret) 688 return ret; 689 690 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals); 691 if (!clk) 692 return -ERANGE; 693 694 if (bios->execute) { 695 still_alive(); 696 nouveau_hw_setpll(dev, reg, &pllvals); 697 } 698 699 return 0; 700} 701 702static int dcb_entry_idx_from_crtchead(struct drm_device *dev) 703{ 704 struct drm_nouveau_private *dev_priv = dev->dev_private; 705 struct nvbios *bios = &dev_priv->vbios; 706 707 /* 708 * For the results of this function to be correct, CR44 must have been 709 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0, 710 * and the DCB table parsed, before the script calling the function is 711 * run. run_digital_op_script is example of how to do such setup 712 */ 713 714 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0); 715 716 if (dcb_entry > bios->dcb.entries) { 717 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently " 718 "(%02X)\n", dcb_entry); 719 dcb_entry = 0x7f; /* unused / invalid marker */ 720 } 721 722 return dcb_entry; 723} 724 725static int 726read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, int index, struct dcb_i2c_entry *i2c) 727{ 728 uint8_t dcb_i2c_ver = dcb_version, headerlen = 0, entry_len = 4; 729 int i2c_entries = DCB_MAX_NUM_I2C_ENTRIES; 730 int recordoffset = 0, rdofs = 1, wrofs = 0; 731 uint8_t port_type = 0; 732 733 if (!i2ctable) 734 return -EINVAL; 735 736 if (dcb_version >= 0x30) { 737 if (i2ctable[0] != dcb_version) /* necessary? */ 738 NV_WARN(dev, 739 "DCB I2C table version mismatch (%02X vs %02X)\n", 740 i2ctable[0], dcb_version); 741 dcb_i2c_ver = i2ctable[0]; 742 headerlen = i2ctable[1]; 743 if (i2ctable[2] <= DCB_MAX_NUM_I2C_ENTRIES) 744 i2c_entries = i2ctable[2]; 745 else 746 NV_WARN(dev, 747 "DCB I2C table has more entries than indexable " 748 "(%d entries, max %d)\n", i2ctable[2], 749 DCB_MAX_NUM_I2C_ENTRIES); 750 entry_len = i2ctable[3]; 751 /* [4] is i2c_default_indices, read in parse_dcb_table() */ 752 } 753 /* 754 * It's your own fault if you call this function on a DCB 1.1 BIOS -- 755 * the test below is for DCB 1.2 756 */ 757 if (dcb_version < 0x14) { 758 recordoffset = 2; 759 rdofs = 0; 760 wrofs = 1; 761 } 762 763 if (index == 0xf) 764 return 0; 765 if (index >= i2c_entries) { 766 NV_ERROR(dev, "DCB I2C index too big (%d >= %d)\n", 767 index, i2ctable[2]); 768 return -ENOENT; 769 } 770 if (i2ctable[headerlen + entry_len * index + 3] == 0xff) { 771 NV_ERROR(dev, "DCB I2C entry invalid\n"); 772 return -EINVAL; 773 } 774 775 if (dcb_i2c_ver >= 0x30) { 776 port_type = i2ctable[headerlen + recordoffset + 3 + entry_len * index]; 777 778 /* 779 * Fixup for chips using same address offset for read and 780 * write. 781 */ 782 if (port_type == 4) /* seen on C51 */ 783 rdofs = wrofs = 1; 784 if (port_type >= 5) /* G80+ */ 785 rdofs = wrofs = 0; 786 } 787 788 if (dcb_i2c_ver >= 0x40) { 789 if (port_type != 5 && port_type != 6) 790 NV_WARN(dev, "DCB I2C table has port type %d\n", port_type); 791 792 i2c->entry = ROM32(i2ctable[headerlen + recordoffset + entry_len * index]); 793 } 794 795 i2c->port_type = port_type; 796 i2c->read = i2ctable[headerlen + recordoffset + rdofs + entry_len * index]; 797 i2c->write = i2ctable[headerlen + recordoffset + wrofs + entry_len * index]; 798 799 return 0; 800} 801 802static struct nouveau_i2c_chan * 803init_i2c_device_find(struct drm_device *dev, int i2c_index) 804{ 805 struct drm_nouveau_private *dev_priv = dev->dev_private; 806 struct dcb_table *dcb = &dev_priv->vbios.dcb; 807 808 if (i2c_index == 0xff) { 809 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */ 810 int idx = dcb_entry_idx_from_crtchead(dev), shift = 0; 811 int default_indices = dcb->i2c_default_indices; 812 813 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default) 814 shift = 4; 815 816 i2c_index = (default_indices >> shift) & 0xf; 817 } 818 if (i2c_index == 0x80) /* g80+ */ 819 i2c_index = dcb->i2c_default_indices & 0xf; 820 else 821 if (i2c_index == 0x81) 822 i2c_index = (dcb->i2c_default_indices & 0xf0) >> 4; 823 824 if (i2c_index >= DCB_MAX_NUM_I2C_ENTRIES) { 825 NV_ERROR(dev, "invalid i2c_index 0x%x\n", i2c_index); 826 return NULL; 827 } 828 829 /* Make sure i2c table entry has been parsed, it may not 830 * have been if this is a bus not referenced by a DCB encoder 831 */ 832 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table, 833 i2c_index, &dcb->i2c[i2c_index]); 834 835 return nouveau_i2c_find(dev, i2c_index); 836} 837 838static uint32_t 839get_tmds_index_reg(struct drm_device *dev, uint8_t mlv) 840{ 841 /* 842 * For mlv < 0x80, it is an index into a table of TMDS base addresses. 843 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by 844 * CR58 for CR57 = 0 to index a table of offsets to the basic 845 * 0x6808b0 address. 846 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by 847 * CR58 for CR57 = 0 to index a table of offsets to the basic 848 * 0x6808b0 address, and then flip the offset by 8. 849 */ 850 851 struct drm_nouveau_private *dev_priv = dev->dev_private; 852 struct nvbios *bios = &dev_priv->vbios; 853 const int pramdac_offset[13] = { 854 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 }; 855 const uint32_t pramdac_table[4] = { 856 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 }; 857 858 if (mlv >= 0x80) { 859 int dcb_entry, dacoffset; 860 861 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */ 862 dcb_entry = dcb_entry_idx_from_crtchead(dev); 863 if (dcb_entry == 0x7f) 864 return 0; 865 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or]; 866 if (mlv == 0x81) 867 dacoffset ^= 8; 868 return 0x6808b0 + dacoffset; 869 } else { 870 if (mlv >= ARRAY_SIZE(pramdac_table)) { 871 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n", 872 mlv); 873 return 0; 874 } 875 return pramdac_table[mlv]; 876 } 877} 878 879static int 880init_io_restrict_prog(struct nvbios *bios, uint16_t offset, 881 struct init_exec *iexec) 882{ 883 /* 884 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2') 885 * 886 * offset (8 bit): opcode 887 * offset + 1 (16 bit): CRTC port 888 * offset + 3 (8 bit): CRTC index 889 * offset + 4 (8 bit): mask 890 * offset + 5 (8 bit): shift 891 * offset + 6 (8 bit): count 892 * offset + 7 (32 bit): register 893 * offset + 11 (32 bit): configuration 1 894 * ... 895 * 896 * Starting at offset + 11 there are "count" 32 bit values. 897 * To find out which value to use read index "CRTC index" on "CRTC 898 * port", AND this value with "mask" and then bit shift right "shift" 899 * bits. Read the appropriate value using this index and write to 900 * "register" 901 */ 902 903 uint16_t crtcport = ROM16(bios->data[offset + 1]); 904 uint8_t crtcindex = bios->data[offset + 3]; 905 uint8_t mask = bios->data[offset + 4]; 906 uint8_t shift = bios->data[offset + 5]; 907 uint8_t count = bios->data[offset + 6]; 908 uint32_t reg = ROM32(bios->data[offset + 7]); 909 uint8_t config; 910 uint32_t configval; 911 int len = 11 + count * 4; 912 913 if (!iexec->execute) 914 return len; 915 916 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 917 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n", 918 offset, crtcport, crtcindex, mask, shift, count, reg); 919 920 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 921 if (config > count) { 922 NV_ERROR(bios->dev, 923 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 924 offset, config, count); 925 return len; 926 } 927 928 configval = ROM32(bios->data[offset + 11 + config * 4]); 929 930 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config); 931 932 bios_wr32(bios, reg, configval); 933 934 return len; 935} 936 937static int 938init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 939{ 940 /* 941 * INIT_REPEAT opcode: 0x33 ('3') 942 * 943 * offset (8 bit): opcode 944 * offset + 1 (8 bit): count 945 * 946 * Execute script following this opcode up to INIT_REPEAT_END 947 * "count" times 948 */ 949 950 uint8_t count = bios->data[offset + 1]; 951 uint8_t i; 952 953 /* no iexec->execute check by design */ 954 955 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n", 956 offset, count); 957 958 iexec->repeat = true; 959 960 /* 961 * count - 1, as the script block will execute once when we leave this 962 * opcode -- this is compatible with bios behaviour as: 963 * a) the block is always executed at least once, even if count == 0 964 * b) the bios interpreter skips to the op following INIT_END_REPEAT, 965 * while we don't 966 */ 967 for (i = 0; i < count - 1; i++) 968 parse_init_table(bios, offset + 2, iexec); 969 970 iexec->repeat = false; 971 972 return 2; 973} 974 975static int 976init_io_restrict_pll(struct nvbios *bios, uint16_t offset, 977 struct init_exec *iexec) 978{ 979 /* 980 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4') 981 * 982 * offset (8 bit): opcode 983 * offset + 1 (16 bit): CRTC port 984 * offset + 3 (8 bit): CRTC index 985 * offset + 4 (8 bit): mask 986 * offset + 5 (8 bit): shift 987 * offset + 6 (8 bit): IO flag condition index 988 * offset + 7 (8 bit): count 989 * offset + 8 (32 bit): register 990 * offset + 12 (16 bit): frequency 1 991 * ... 992 * 993 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz). 994 * Set PLL register "register" to coefficients for frequency n, 995 * selected by reading index "CRTC index" of "CRTC port" ANDed with 996 * "mask" and shifted right by "shift". 997 * 998 * If "IO flag condition index" > 0, and condition met, double 999 * frequency before setting it. 1000 */ 1001 1002 uint16_t crtcport = ROM16(bios->data[offset + 1]); 1003 uint8_t crtcindex = bios->data[offset + 3]; 1004 uint8_t mask = bios->data[offset + 4]; 1005 uint8_t shift = bios->data[offset + 5]; 1006 int8_t io_flag_condition_idx = bios->data[offset + 6]; 1007 uint8_t count = bios->data[offset + 7]; 1008 uint32_t reg = ROM32(bios->data[offset + 8]); 1009 uint8_t config; 1010 uint16_t freq; 1011 int len = 12 + count * 2; 1012 1013 if (!iexec->execute) 1014 return len; 1015 1016 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 1017 "Shift: 0x%02X, IO Flag Condition: 0x%02X, " 1018 "Count: 0x%02X, Reg: 0x%08X\n", 1019 offset, crtcport, crtcindex, mask, shift, 1020 io_flag_condition_idx, count, reg); 1021 1022 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 1023 if (config > count) { 1024 NV_ERROR(bios->dev, 1025 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 1026 offset, config, count); 1027 return len; 1028 } 1029 1030 freq = ROM16(bios->data[offset + 12 + config * 2]); 1031 1032 if (io_flag_condition_idx > 0) { 1033 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) { 1034 BIOSLOG(bios, "0x%04X: Condition fulfilled -- " 1035 "frequency doubled\n", offset); 1036 freq *= 2; 1037 } else 1038 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- " 1039 "frequency unchanged\n", offset); 1040 } 1041 1042 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n", 1043 offset, reg, config, freq); 1044 1045 setPLL(bios, reg, freq * 10); 1046 1047 return len; 1048} 1049 1050static int 1051init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1052{ 1053 /* 1054 * INIT_END_REPEAT opcode: 0x36 ('6') 1055 * 1056 * offset (8 bit): opcode 1057 * 1058 * Marks the end of the block for INIT_REPEAT to repeat 1059 */ 1060 1061 /* no iexec->execute check by design */ 1062 1063 /* 1064 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when 1065 * we're not in repeat mode 1066 */ 1067 if (iexec->repeat) 1068 return 0; 1069 1070 return 1; 1071} 1072 1073static int 1074init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1075{ 1076 /* 1077 * INIT_COPY opcode: 0x37 ('7') 1078 * 1079 * offset (8 bit): opcode 1080 * offset + 1 (32 bit): register 1081 * offset + 5 (8 bit): shift 1082 * offset + 6 (8 bit): srcmask 1083 * offset + 7 (16 bit): CRTC port 1084 * offset + 9 (8 bit): CRTC index 1085 * offset + 10 (8 bit): mask 1086 * 1087 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with 1088 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC 1089 * port 1090 */ 1091 1092 uint32_t reg = ROM32(bios->data[offset + 1]); 1093 uint8_t shift = bios->data[offset + 5]; 1094 uint8_t srcmask = bios->data[offset + 6]; 1095 uint16_t crtcport = ROM16(bios->data[offset + 7]); 1096 uint8_t crtcindex = bios->data[offset + 9]; 1097 uint8_t mask = bios->data[offset + 10]; 1098 uint32_t data; 1099 uint8_t crtcdata; 1100 1101 if (!iexec->execute) 1102 return 11; 1103 1104 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, " 1105 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n", 1106 offset, reg, shift, srcmask, crtcport, crtcindex, mask); 1107 1108 data = bios_rd32(bios, reg); 1109 1110 if (shift < 0x80) 1111 data >>= shift; 1112 else 1113 data <<= (0x100 - shift); 1114 1115 data &= srcmask; 1116 1117 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask; 1118 crtcdata |= (uint8_t)data; 1119 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata); 1120 1121 return 11; 1122} 1123 1124static int 1125init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1126{ 1127 /* 1128 * INIT_NOT opcode: 0x38 ('8') 1129 * 1130 * offset (8 bit): opcode 1131 * 1132 * Invert the current execute / no-execute condition (i.e. "else") 1133 */ 1134 if (iexec->execute) 1135 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset); 1136 else 1137 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset); 1138 1139 iexec->execute = !iexec->execute; 1140 return 1; 1141} 1142 1143static int 1144init_io_flag_condition(struct nvbios *bios, uint16_t offset, 1145 struct init_exec *iexec) 1146{ 1147 /* 1148 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9') 1149 * 1150 * offset (8 bit): opcode 1151 * offset + 1 (8 bit): condition number 1152 * 1153 * Check condition "condition number" in the IO flag condition table. 1154 * If condition not met skip subsequent opcodes until condition is 1155 * inverted (INIT_NOT), or we hit INIT_RESUME 1156 */ 1157 1158 uint8_t cond = bios->data[offset + 1]; 1159 1160 if (!iexec->execute) 1161 return 2; 1162 1163 if (io_flag_condition_met(bios, offset, cond)) 1164 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 1165 else { 1166 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 1167 iexec->execute = false; 1168 } 1169 1170 return 2; 1171} 1172 1173static int 1174init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1175{ 1176 /* 1177 * INIT_DP_CONDITION opcode: 0x3A ('') 1178 * 1179 * offset (8 bit): opcode 1180 * offset + 1 (8 bit): "sub" opcode 1181 * offset + 2 (8 bit): unknown 1182 * 1183 */ 1184 1185 struct bit_displayport_encoder_table *dpe = NULL; 1186 struct dcb_entry *dcb = bios->display.output; 1187 struct drm_device *dev = bios->dev; 1188 uint8_t cond = bios->data[offset + 1]; 1189 int dummy; 1190 1191 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond); 1192 1193 if (!iexec->execute) 1194 return 3; 1195 1196 dpe = nouveau_bios_dp_table(dev, dcb, &dummy); 1197 if (!dpe) { 1198 NV_ERROR(dev, "0x%04X: INIT_3A: no encoder table!!\n", offset); 1199 return 3; 1200 } 1201 1202 switch (cond) { 1203 case 0: 1204 { 1205 struct dcb_connector_table_entry *ent = 1206 &bios->dcb.connector.entry[dcb->connector]; 1207 1208 if (ent->type != DCB_CONNECTOR_eDP) 1209 iexec->execute = false; 1210 } 1211 break; 1212 case 1: 1213 case 2: 1214 if (!(dpe->unknown & cond)) 1215 iexec->execute = false; 1216 break; 1217 case 5: 1218 { 1219 struct nouveau_i2c_chan *auxch; 1220 int ret; 1221 1222 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index); 1223 if (!auxch) { 1224 NV_ERROR(dev, "0x%04X: couldn't get auxch\n", offset); 1225 return 3; 1226 } 1227 1228 ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1); 1229 if (ret) { 1230 NV_ERROR(dev, "0x%04X: auxch rd fail: %d\n", offset, ret); 1231 return 3; 1232 } 1233 1234 if (cond & 1) 1235 iexec->execute = false; 1236 } 1237 break; 1238 default: 1239 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond); 1240 break; 1241 } 1242 1243 if (iexec->execute) 1244 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset); 1245 else 1246 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset); 1247 1248 return 3; 1249} 1250 1251static int 1252init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1253{ 1254 /* 1255 * INIT_3B opcode: 0x3B ('') 1256 * 1257 * offset (8 bit): opcode 1258 * offset + 1 (8 bit): crtc index 1259 * 1260 */ 1261 1262 uint8_t or = ffs(bios->display.output->or) - 1; 1263 uint8_t index = bios->data[offset + 1]; 1264 uint8_t data; 1265 1266 if (!iexec->execute) 1267 return 2; 1268 1269 data = bios_idxprt_rd(bios, 0x3d4, index); 1270 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or)); 1271 return 2; 1272} 1273 1274static int 1275init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1276{ 1277 /* 1278 * INIT_3C opcode: 0x3C ('') 1279 * 1280 * offset (8 bit): opcode 1281 * offset + 1 (8 bit): crtc index 1282 * 1283 */ 1284 1285 uint8_t or = ffs(bios->display.output->or) - 1; 1286 uint8_t index = bios->data[offset + 1]; 1287 uint8_t data; 1288 1289 if (!iexec->execute) 1290 return 2; 1291 1292 data = bios_idxprt_rd(bios, 0x3d4, index); 1293 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or)); 1294 return 2; 1295} 1296 1297static int 1298init_idx_addr_latched(struct nvbios *bios, uint16_t offset, 1299 struct init_exec *iexec) 1300{ 1301 /* 1302 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I') 1303 * 1304 * offset (8 bit): opcode 1305 * offset + 1 (32 bit): control register 1306 * offset + 5 (32 bit): data register 1307 * offset + 9 (32 bit): mask 1308 * offset + 13 (32 bit): data 1309 * offset + 17 (8 bit): count 1310 * offset + 18 (8 bit): address 1 1311 * offset + 19 (8 bit): data 1 1312 * ... 1313 * 1314 * For each of "count" address and data pairs, write "data n" to 1315 * "data register", read the current value of "control register", 1316 * and write it back once ANDed with "mask", ORed with "data", 1317 * and ORed with "address n" 1318 */ 1319 1320 uint32_t controlreg = ROM32(bios->data[offset + 1]); 1321 uint32_t datareg = ROM32(bios->data[offset + 5]); 1322 uint32_t mask = ROM32(bios->data[offset + 9]); 1323 uint32_t data = ROM32(bios->data[offset + 13]); 1324 uint8_t count = bios->data[offset + 17]; 1325 int len = 18 + count * 2; 1326 uint32_t value; 1327 int i; 1328 1329 if (!iexec->execute) 1330 return len; 1331 1332 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, " 1333 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n", 1334 offset, controlreg, datareg, mask, data, count); 1335 1336 for (i = 0; i < count; i++) { 1337 uint8_t instaddress = bios->data[offset + 18 + i * 2]; 1338 uint8_t instdata = bios->data[offset + 19 + i * 2]; 1339 1340 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n", 1341 offset, instaddress, instdata); 1342 1343 bios_wr32(bios, datareg, instdata); 1344 value = bios_rd32(bios, controlreg) & mask; 1345 value |= data; 1346 value |= instaddress; 1347 bios_wr32(bios, controlreg, value); 1348 } 1349 1350 return len; 1351} 1352 1353static int 1354init_io_restrict_pll2(struct nvbios *bios, uint16_t offset, 1355 struct init_exec *iexec) 1356{ 1357 /* 1358 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J') 1359 * 1360 * offset (8 bit): opcode 1361 * offset + 1 (16 bit): CRTC port 1362 * offset + 3 (8 bit): CRTC index 1363 * offset + 4 (8 bit): mask 1364 * offset + 5 (8 bit): shift 1365 * offset + 6 (8 bit): count 1366 * offset + 7 (32 bit): register 1367 * offset + 11 (32 bit): frequency 1 1368 * ... 1369 * 1370 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz). 1371 * Set PLL register "register" to coefficients for frequency n, 1372 * selected by reading index "CRTC index" of "CRTC port" ANDed with 1373 * "mask" and shifted right by "shift". 1374 */ 1375 1376 uint16_t crtcport = ROM16(bios->data[offset + 1]); 1377 uint8_t crtcindex = bios->data[offset + 3]; 1378 uint8_t mask = bios->data[offset + 4]; 1379 uint8_t shift = bios->data[offset + 5]; 1380 uint8_t count = bios->data[offset + 6]; 1381 uint32_t reg = ROM32(bios->data[offset + 7]); 1382 int len = 11 + count * 4; 1383 uint8_t config; 1384 uint32_t freq; 1385 1386 if (!iexec->execute) 1387 return len; 1388 1389 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 1390 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n", 1391 offset, crtcport, crtcindex, mask, shift, count, reg); 1392 1393 if (!reg) 1394 return len; 1395 1396 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 1397 if (config > count) { 1398 NV_ERROR(bios->dev, 1399 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 1400 offset, config, count); 1401 return len; 1402 } 1403 1404 freq = ROM32(bios->data[offset + 11 + config * 4]); 1405 1406 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n", 1407 offset, reg, config, freq); 1408 1409 setPLL(bios, reg, freq); 1410 1411 return len; 1412} 1413 1414static int 1415init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1416{ 1417 /* 1418 * INIT_PLL2 opcode: 0x4B ('K') 1419 * 1420 * offset (8 bit): opcode 1421 * offset + 1 (32 bit): register 1422 * offset + 5 (32 bit): freq 1423 * 1424 * Set PLL register "register" to coefficients for frequency "freq" 1425 */ 1426 1427 uint32_t reg = ROM32(bios->data[offset + 1]); 1428 uint32_t freq = ROM32(bios->data[offset + 5]); 1429 1430 if (!iexec->execute) 1431 return 9; 1432 1433 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n", 1434 offset, reg, freq); 1435 1436 setPLL(bios, reg, freq); 1437 return 9; 1438} 1439 1440static int 1441init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1442{ 1443 /* 1444 * INIT_I2C_BYTE opcode: 0x4C ('L') 1445 * 1446 * offset (8 bit): opcode 1447 * offset + 1 (8 bit): DCB I2C table entry index 1448 * offset + 2 (8 bit): I2C slave address 1449 * offset + 3 (8 bit): count 1450 * offset + 4 (8 bit): I2C register 1 1451 * offset + 5 (8 bit): mask 1 1452 * offset + 6 (8 bit): data 1 1453 * ... 1454 * 1455 * For each of "count" registers given by "I2C register n" on the device 1456 * addressed by "I2C slave address" on the I2C bus given by 1457 * "DCB I2C table entry index", read the register, AND the result with 1458 * "mask n" and OR it with "data n" before writing it back to the device 1459 */ 1460 1461 struct drm_device *dev = bios->dev; 1462 uint8_t i2c_index = bios->data[offset + 1]; 1463 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1464 uint8_t count = bios->data[offset + 3]; 1465 struct nouveau_i2c_chan *chan; 1466 int len = 4 + count * 3; 1467 int ret, i; 1468 1469 if (!iexec->execute) 1470 return len; 1471 1472 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1473 "Count: 0x%02X\n", 1474 offset, i2c_index, i2c_address, count); 1475 1476 chan = init_i2c_device_find(dev, i2c_index); 1477 if (!chan) { 1478 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset); 1479 return len; 1480 } 1481 1482 for (i = 0; i < count; i++) { 1483 uint8_t reg = bios->data[offset + 4 + i * 3]; 1484 uint8_t mask = bios->data[offset + 5 + i * 3]; 1485 uint8_t data = bios->data[offset + 6 + i * 3]; 1486 union i2c_smbus_data val; 1487 1488 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 1489 I2C_SMBUS_READ, reg, 1490 I2C_SMBUS_BYTE_DATA, &val); 1491 if (ret < 0) { 1492 NV_ERROR(dev, "0x%04X: i2c rd fail: %d\n", offset, ret); 1493 return len; 1494 } 1495 1496 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, " 1497 "Mask: 0x%02X, Data: 0x%02X\n", 1498 offset, reg, val.byte, mask, data); 1499 1500 if (!bios->execute) 1501 continue; 1502 1503 val.byte &= mask; 1504 val.byte |= data; 1505 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 1506 I2C_SMBUS_WRITE, reg, 1507 I2C_SMBUS_BYTE_DATA, &val); 1508 if (ret < 0) { 1509 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret); 1510 return len; 1511 } 1512 } 1513 1514 return len; 1515} 1516 1517static int 1518init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1519{ 1520 /* 1521 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M') 1522 * 1523 * offset (8 bit): opcode 1524 * offset + 1 (8 bit): DCB I2C table entry index 1525 * offset + 2 (8 bit): I2C slave address 1526 * offset + 3 (8 bit): count 1527 * offset + 4 (8 bit): I2C register 1 1528 * offset + 5 (8 bit): data 1 1529 * ... 1530 * 1531 * For each of "count" registers given by "I2C register n" on the device 1532 * addressed by "I2C slave address" on the I2C bus given by 1533 * "DCB I2C table entry index", set the register to "data n" 1534 */ 1535 1536 struct drm_device *dev = bios->dev; 1537 uint8_t i2c_index = bios->data[offset + 1]; 1538 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1539 uint8_t count = bios->data[offset + 3]; 1540 struct nouveau_i2c_chan *chan; 1541 int len = 4 + count * 2; 1542 int ret, i; 1543 1544 if (!iexec->execute) 1545 return len; 1546 1547 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1548 "Count: 0x%02X\n", 1549 offset, i2c_index, i2c_address, count); 1550 1551 chan = init_i2c_device_find(dev, i2c_index); 1552 if (!chan) { 1553 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset); 1554 return len; 1555 } 1556 1557 for (i = 0; i < count; i++) { 1558 uint8_t reg = bios->data[offset + 4 + i * 2]; 1559 union i2c_smbus_data val; 1560 1561 val.byte = bios->data[offset + 5 + i * 2]; 1562 1563 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n", 1564 offset, reg, val.byte); 1565 1566 if (!bios->execute) 1567 continue; 1568 1569 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 1570 I2C_SMBUS_WRITE, reg, 1571 I2C_SMBUS_BYTE_DATA, &val); 1572 if (ret < 0) { 1573 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret); 1574 return len; 1575 } 1576 } 1577 1578 return len; 1579} 1580 1581static int 1582init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1583{ 1584 /* 1585 * INIT_ZM_I2C opcode: 0x4E ('N') 1586 * 1587 * offset (8 bit): opcode 1588 * offset + 1 (8 bit): DCB I2C table entry index 1589 * offset + 2 (8 bit): I2C slave address 1590 * offset + 3 (8 bit): count 1591 * offset + 4 (8 bit): data 1 1592 * ... 1593 * 1594 * Send "count" bytes ("data n") to the device addressed by "I2C slave 1595 * address" on the I2C bus given by "DCB I2C table entry index" 1596 */ 1597 1598 struct drm_device *dev = bios->dev; 1599 uint8_t i2c_index = bios->data[offset + 1]; 1600 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1601 uint8_t count = bios->data[offset + 3]; 1602 int len = 4 + count; 1603 struct nouveau_i2c_chan *chan; 1604 struct i2c_msg msg; 1605 uint8_t data[256]; 1606 int ret, i; 1607 1608 if (!iexec->execute) 1609 return len; 1610 1611 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1612 "Count: 0x%02X\n", 1613 offset, i2c_index, i2c_address, count); 1614 1615 chan = init_i2c_device_find(dev, i2c_index); 1616 if (!chan) { 1617 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset); 1618 return len; 1619 } 1620 1621 for (i = 0; i < count; i++) { 1622 data[i] = bios->data[offset + 4 + i]; 1623 1624 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]); 1625 } 1626 1627 if (bios->execute) { 1628 msg.addr = i2c_address; 1629 msg.flags = 0; 1630 msg.len = count; 1631 msg.buf = data; 1632 ret = i2c_transfer(&chan->adapter, &msg, 1); 1633 if (ret != 1) { 1634 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret); 1635 return len; 1636 } 1637 } 1638 1639 return len; 1640} 1641 1642static int 1643init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1644{ 1645 /* 1646 * INIT_TMDS opcode: 0x4F ('O') (non-canon name) 1647 * 1648 * offset (8 bit): opcode 1649 * offset + 1 (8 bit): magic lookup value 1650 * offset + 2 (8 bit): TMDS address 1651 * offset + 3 (8 bit): mask 1652 * offset + 4 (8 bit): data 1653 * 1654 * Read the data reg for TMDS address "TMDS address", AND it with mask 1655 * and OR it with data, then write it back 1656 * "magic lookup value" determines which TMDS base address register is 1657 * used -- see get_tmds_index_reg() 1658 */ 1659 1660 struct drm_device *dev = bios->dev; 1661 uint8_t mlv = bios->data[offset + 1]; 1662 uint32_t tmdsaddr = bios->data[offset + 2]; 1663 uint8_t mask = bios->data[offset + 3]; 1664 uint8_t data = bios->data[offset + 4]; 1665 uint32_t reg, value; 1666 1667 if (!iexec->execute) 1668 return 5; 1669 1670 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, " 1671 "Mask: 0x%02X, Data: 0x%02X\n", 1672 offset, mlv, tmdsaddr, mask, data); 1673 1674 reg = get_tmds_index_reg(bios->dev, mlv); 1675 if (!reg) { 1676 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset); 1677 return 5; 1678 } 1679 1680 bios_wr32(bios, reg, 1681 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE); 1682 value = (bios_rd32(bios, reg + 4) & mask) | data; 1683 bios_wr32(bios, reg + 4, value); 1684 bios_wr32(bios, reg, tmdsaddr); 1685 1686 return 5; 1687} 1688 1689static int 1690init_zm_tmds_group(struct nvbios *bios, uint16_t offset, 1691 struct init_exec *iexec) 1692{ 1693 /* 1694 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name) 1695 * 1696 * offset (8 bit): opcode 1697 * offset + 1 (8 bit): magic lookup value 1698 * offset + 2 (8 bit): count 1699 * offset + 3 (8 bit): addr 1 1700 * offset + 4 (8 bit): data 1 1701 * ... 1702 * 1703 * For each of "count" TMDS address and data pairs write "data n" to 1704 * "addr n". "magic lookup value" determines which TMDS base address 1705 * register is used -- see get_tmds_index_reg() 1706 */ 1707 1708 struct drm_device *dev = bios->dev; 1709 uint8_t mlv = bios->data[offset + 1]; 1710 uint8_t count = bios->data[offset + 2]; 1711 int len = 3 + count * 2; 1712 uint32_t reg; 1713 int i; 1714 1715 if (!iexec->execute) 1716 return len; 1717 1718 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n", 1719 offset, mlv, count); 1720 1721 reg = get_tmds_index_reg(bios->dev, mlv); 1722 if (!reg) { 1723 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset); 1724 return len; 1725 } 1726 1727 for (i = 0; i < count; i++) { 1728 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2]; 1729 uint8_t tmdsdata = bios->data[offset + 4 + i * 2]; 1730 1731 bios_wr32(bios, reg + 4, tmdsdata); 1732 bios_wr32(bios, reg, tmdsaddr); 1733 } 1734 1735 return len; 1736} 1737 1738static int 1739init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset, 1740 struct init_exec *iexec) 1741{ 1742 /* 1743 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q') 1744 * 1745 * offset (8 bit): opcode 1746 * offset + 1 (8 bit): CRTC index1 1747 * offset + 2 (8 bit): CRTC index2 1748 * offset + 3 (8 bit): baseaddr 1749 * offset + 4 (8 bit): count 1750 * offset + 5 (8 bit): data 1 1751 * ... 1752 * 1753 * For each of "count" address and data pairs, write "baseaddr + n" to 1754 * "CRTC index1" and "data n" to "CRTC index2" 1755 * Once complete, restore initial value read from "CRTC index1" 1756 */ 1757 uint8_t crtcindex1 = bios->data[offset + 1]; 1758 uint8_t crtcindex2 = bios->data[offset + 2]; 1759 uint8_t baseaddr = bios->data[offset + 3]; 1760 uint8_t count = bios->data[offset + 4]; 1761 int len = 5 + count; 1762 uint8_t oldaddr, data; 1763 int i; 1764 1765 if (!iexec->execute) 1766 return len; 1767 1768 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, " 1769 "BaseAddr: 0x%02X, Count: 0x%02X\n", 1770 offset, crtcindex1, crtcindex2, baseaddr, count); 1771 1772 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1); 1773 1774 for (i = 0; i < count; i++) { 1775 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, 1776 baseaddr + i); 1777 data = bios->data[offset + 5 + i]; 1778 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data); 1779 } 1780 1781 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr); 1782 1783 return len; 1784} 1785 1786static int 1787init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1788{ 1789 /* 1790 * INIT_CR opcode: 0x52 ('R') 1791 * 1792 * offset (8 bit): opcode 1793 * offset + 1 (8 bit): CRTC index 1794 * offset + 2 (8 bit): mask 1795 * offset + 3 (8 bit): data 1796 * 1797 * Assign the value of at "CRTC index" ANDed with mask and ORed with 1798 * data back to "CRTC index" 1799 */ 1800 1801 uint8_t crtcindex = bios->data[offset + 1]; 1802 uint8_t mask = bios->data[offset + 2]; 1803 uint8_t data = bios->data[offset + 3]; 1804 uint8_t value; 1805 1806 if (!iexec->execute) 1807 return 4; 1808 1809 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n", 1810 offset, crtcindex, mask, data); 1811 1812 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask; 1813 value |= data; 1814 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value); 1815 1816 return 4; 1817} 1818 1819static int 1820init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1821{ 1822 /* 1823 * INIT_ZM_CR opcode: 0x53 ('S') 1824 * 1825 * offset (8 bit): opcode 1826 * offset + 1 (8 bit): CRTC index 1827 * offset + 2 (8 bit): value 1828 * 1829 * Assign "value" to CRTC register with index "CRTC index". 1830 */ 1831 1832 uint8_t crtcindex = ROM32(bios->data[offset + 1]); 1833 uint8_t data = bios->data[offset + 2]; 1834 1835 if (!iexec->execute) 1836 return 3; 1837 1838 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data); 1839 1840 return 3; 1841} 1842 1843static int 1844init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1845{ 1846 /* 1847 * INIT_ZM_CR_GROUP opcode: 0x54 ('T') 1848 * 1849 * offset (8 bit): opcode 1850 * offset + 1 (8 bit): count 1851 * offset + 2 (8 bit): CRTC index 1 1852 * offset + 3 (8 bit): value 1 1853 * ... 1854 * 1855 * For "count", assign "value n" to CRTC register with index 1856 * "CRTC index n". 1857 */ 1858 1859 uint8_t count = bios->data[offset + 1]; 1860 int len = 2 + count * 2; 1861 int i; 1862 1863 if (!iexec->execute) 1864 return len; 1865 1866 for (i = 0; i < count; i++) 1867 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec); 1868 1869 return len; 1870} 1871 1872static int 1873init_condition_time(struct nvbios *bios, uint16_t offset, 1874 struct init_exec *iexec) 1875{ 1876 /* 1877 * INIT_CONDITION_TIME opcode: 0x56 ('V') 1878 * 1879 * offset (8 bit): opcode 1880 * offset + 1 (8 bit): condition number 1881 * offset + 2 (8 bit): retries / 50 1882 * 1883 * Check condition "condition number" in the condition table. 1884 * Bios code then sleeps for 2ms if the condition is not met, and 1885 * repeats up to "retries" times, but on one C51 this has proved 1886 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do 1887 * this, and bail after "retries" times, or 2s, whichever is less. 1888 * If still not met after retries, clear execution flag for this table. 1889 */ 1890 1891 uint8_t cond = bios->data[offset + 1]; 1892 uint16_t retries = bios->data[offset + 2] * 50; 1893 unsigned cnt; 1894 1895 if (!iexec->execute) 1896 return 3; 1897 1898 if (retries > 100) 1899 retries = 100; 1900 1901 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n", 1902 offset, cond, retries); 1903 1904 if (!bios->execute) /* avoid 2s delays when "faking" execution */ 1905 retries = 1; 1906 1907 for (cnt = 0; cnt < retries; cnt++) { 1908 if (bios_condition_met(bios, offset, cond)) { 1909 BIOSLOG(bios, "0x%04X: Condition met, continuing\n", 1910 offset); 1911 break; 1912 } else { 1913 BIOSLOG(bios, "0x%04X: " 1914 "Condition not met, sleeping for 20ms\n", 1915 offset); 1916 msleep(20); 1917 } 1918 } 1919 1920 if (!bios_condition_met(bios, offset, cond)) { 1921 NV_WARN(bios->dev, 1922 "0x%04X: Condition still not met after %dms, " 1923 "skipping following opcodes\n", offset, 20 * retries); 1924 iexec->execute = false; 1925 } 1926 1927 return 3; 1928} 1929 1930static int 1931init_ltime(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1932{ 1933 /* 1934 * INIT_LTIME opcode: 0x57 ('V') 1935 * 1936 * offset (8 bit): opcode 1937 * offset + 1 (16 bit): time 1938 * 1939 * Sleep for "time" miliseconds. 1940 */ 1941 1942 unsigned time = ROM16(bios->data[offset + 1]); 1943 1944 if (!iexec->execute) 1945 return 3; 1946 1947 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X miliseconds\n", 1948 offset, time); 1949 1950 msleep(time); 1951 1952 return 3; 1953} 1954 1955static int 1956init_zm_reg_sequence(struct nvbios *bios, uint16_t offset, 1957 struct init_exec *iexec) 1958{ 1959 /* 1960 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X') 1961 * 1962 * offset (8 bit): opcode 1963 * offset + 1 (32 bit): base register 1964 * offset + 5 (8 bit): count 1965 * offset + 6 (32 bit): value 1 1966 * ... 1967 * 1968 * Starting at offset + 6 there are "count" 32 bit values. 1969 * For "count" iterations set "base register" + 4 * current_iteration 1970 * to "value current_iteration" 1971 */ 1972 1973 uint32_t basereg = ROM32(bios->data[offset + 1]); 1974 uint32_t count = bios->data[offset + 5]; 1975 int len = 6 + count * 4; 1976 int i; 1977 1978 if (!iexec->execute) 1979 return len; 1980 1981 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n", 1982 offset, basereg, count); 1983 1984 for (i = 0; i < count; i++) { 1985 uint32_t reg = basereg + i * 4; 1986 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]); 1987 1988 bios_wr32(bios, reg, data); 1989 } 1990 1991 return len; 1992} 1993 1994static int 1995init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1996{ 1997 /* 1998 * INIT_SUB_DIRECT opcode: 0x5B ('[') 1999 * 2000 * offset (8 bit): opcode 2001 * offset + 1 (16 bit): subroutine offset (in bios) 2002 * 2003 * Calls a subroutine that will execute commands until INIT_DONE 2004 * is found. 2005 */ 2006 2007 uint16_t sub_offset = ROM16(bios->data[offset + 1]); 2008 2009 if (!iexec->execute) 2010 return 3; 2011 2012 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n", 2013 offset, sub_offset); 2014 2015 parse_init_table(bios, sub_offset, iexec); 2016 2017 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset); 2018 2019 return 3; 2020} 2021 2022static int 2023init_i2c_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2024{ 2025 /* 2026 * INIT_I2C_IF opcode: 0x5E ('^') 2027 * 2028 * offset (8 bit): opcode 2029 * offset + 1 (8 bit): DCB I2C table entry index 2030 * offset + 2 (8 bit): I2C slave address 2031 * offset + 3 (8 bit): I2C register 2032 * offset + 4 (8 bit): mask 2033 * offset + 5 (8 bit): data 2034 * 2035 * Read the register given by "I2C register" on the device addressed 2036 * by "I2C slave address" on the I2C bus given by "DCB I2C table 2037 * entry index". Compare the result AND "mask" to "data". 2038 * If they're not equal, skip subsequent opcodes until condition is 2039 * inverted (INIT_NOT), or we hit INIT_RESUME 2040 */ 2041 2042 uint8_t i2c_index = bios->data[offset + 1]; 2043 uint8_t i2c_address = bios->data[offset + 2] >> 1; 2044 uint8_t reg = bios->data[offset + 3]; 2045 uint8_t mask = bios->data[offset + 4]; 2046 uint8_t data = bios->data[offset + 5]; 2047 struct nouveau_i2c_chan *chan; 2048 union i2c_smbus_data val; 2049 int ret; 2050 2051 /* no execute check by design */ 2052 2053 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n", 2054 offset, i2c_index, i2c_address); 2055 2056 chan = init_i2c_device_find(bios->dev, i2c_index); 2057 if (!chan) 2058 return -ENODEV; 2059 2060 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 2061 I2C_SMBUS_READ, reg, 2062 I2C_SMBUS_BYTE_DATA, &val); 2063 if (ret < 0) { 2064 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: [no device], " 2065 "Mask: 0x%02X, Data: 0x%02X\n", 2066 offset, reg, mask, data); 2067 iexec->execute = 0; 2068 return 6; 2069 } 2070 2071 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, " 2072 "Mask: 0x%02X, Data: 0x%02X\n", 2073 offset, reg, val.byte, mask, data); 2074 2075 iexec->execute = ((val.byte & mask) == data); 2076 2077 return 6; 2078} 2079 2080static int 2081init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2082{ 2083 /* 2084 * INIT_COPY_NV_REG opcode: 0x5F ('_') 2085 * 2086 * offset (8 bit): opcode 2087 * offset + 1 (32 bit): src reg 2088 * offset + 5 (8 bit): shift 2089 * offset + 6 (32 bit): src mask 2090 * offset + 10 (32 bit): xor 2091 * offset + 14 (32 bit): dst reg 2092 * offset + 18 (32 bit): dst mask 2093 * 2094 * Shift REGVAL("src reg") right by (signed) "shift", AND result with 2095 * "src mask", then XOR with "xor". Write this OR'd with 2096 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg" 2097 */ 2098 2099 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1])); 2100 uint8_t shift = bios->data[offset + 5]; 2101 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6])); 2102 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10])); 2103 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14])); 2104 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18])); 2105 uint32_t srcvalue, dstvalue; 2106 2107 if (!iexec->execute) 2108 return 22; 2109 2110 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, " 2111 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n", 2112 offset, srcreg, shift, srcmask, xor, dstreg, dstmask); 2113 2114 srcvalue = bios_rd32(bios, srcreg); 2115 2116 if (shift < 0x80) 2117 srcvalue >>= shift; 2118 else 2119 srcvalue <<= (0x100 - shift); 2120 2121 srcvalue = (srcvalue & srcmask) ^ xor; 2122 2123 dstvalue = bios_rd32(bios, dstreg) & dstmask; 2124 2125 bios_wr32(bios, dstreg, dstvalue | srcvalue); 2126 2127 return 22; 2128} 2129 2130static int 2131init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2132{ 2133 /* 2134 * INIT_ZM_INDEX_IO opcode: 0x62 ('b') 2135 * 2136 * offset (8 bit): opcode 2137 * offset + 1 (16 bit): CRTC port 2138 * offset + 3 (8 bit): CRTC index 2139 * offset + 4 (8 bit): data 2140 * 2141 * Write "data" to index "CRTC index" of "CRTC port" 2142 */ 2143 uint16_t crtcport = ROM16(bios->data[offset + 1]); 2144 uint8_t crtcindex = bios->data[offset + 3]; 2145 uint8_t data = bios->data[offset + 4]; 2146 2147 if (!iexec->execute) 2148 return 5; 2149 2150 bios_idxprt_wr(bios, crtcport, crtcindex, data); 2151 2152 return 5; 2153} 2154 2155static inline void 2156bios_md32(struct nvbios *bios, uint32_t reg, 2157 uint32_t mask, uint32_t val) 2158{ 2159 bios_wr32(bios, reg, (bios_rd32(bios, reg) & ~mask) | val); 2160} 2161 2162static uint32_t 2163peek_fb(struct drm_device *dev, struct io_mapping *fb, 2164 uint32_t off) 2165{ 2166 uint32_t val = 0; 2167 2168 if (off < pci_resource_len(dev->pdev, 1)) { 2169 uint32_t __iomem *p = 2170 io_mapping_map_atomic_wc(fb, off & PAGE_MASK, KM_USER0); 2171 2172 val = ioread32(p + (off & ~PAGE_MASK)); 2173 2174 io_mapping_unmap_atomic(p, KM_USER0); 2175 } 2176 2177 return val; 2178} 2179 2180static void 2181poke_fb(struct drm_device *dev, struct io_mapping *fb, 2182 uint32_t off, uint32_t val) 2183{ 2184 if (off < pci_resource_len(dev->pdev, 1)) { 2185 uint32_t __iomem *p = 2186 io_mapping_map_atomic_wc(fb, off & PAGE_MASK, KM_USER0); 2187 2188 iowrite32(val, p + (off & ~PAGE_MASK)); 2189 wmb(); 2190 2191 io_mapping_unmap_atomic(p, KM_USER0); 2192 } 2193} 2194 2195static inline bool 2196read_back_fb(struct drm_device *dev, struct io_mapping *fb, 2197 uint32_t off, uint32_t val) 2198{ 2199 poke_fb(dev, fb, off, val); 2200 return val == peek_fb(dev, fb, off); 2201} 2202 2203static int 2204nv04_init_compute_mem(struct nvbios *bios) 2205{ 2206 struct drm_device *dev = bios->dev; 2207 uint32_t patt = 0xdeadbeef; 2208 struct io_mapping *fb; 2209 int i; 2210 2211 /* Map the framebuffer aperture */ 2212 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1), 2213 pci_resource_len(dev->pdev, 1)); 2214 if (!fb) 2215 return -ENOMEM; 2216 2217 /* Sequencer and refresh off */ 2218 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20); 2219 bios_md32(bios, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF); 2220 2221 bios_md32(bios, NV04_PFB_BOOT_0, ~0, 2222 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB | 2223 NV04_PFB_BOOT_0_RAM_WIDTH_128 | 2224 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT); 2225 2226 for (i = 0; i < 4; i++) 2227 poke_fb(dev, fb, 4 * i, patt); 2228 2229 poke_fb(dev, fb, 0x400000, patt + 1); 2230 2231 if (peek_fb(dev, fb, 0) == patt + 1) { 2232 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE, 2233 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT); 2234 bios_md32(bios, NV04_PFB_DEBUG_0, 2235 NV04_PFB_DEBUG_0_REFRESH_OFF, 0); 2236 2237 for (i = 0; i < 4; i++) 2238 poke_fb(dev, fb, 4 * i, patt); 2239 2240 if ((peek_fb(dev, fb, 0xc) & 0xffff) != (patt & 0xffff)) 2241 bios_md32(bios, NV04_PFB_BOOT_0, 2242 NV04_PFB_BOOT_0_RAM_WIDTH_128 | 2243 NV04_PFB_BOOT_0_RAM_AMOUNT, 2244 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 2245 2246 } else if ((peek_fb(dev, fb, 0xc) & 0xffff0000) != 2247 (patt & 0xffff0000)) { 2248 bios_md32(bios, NV04_PFB_BOOT_0, 2249 NV04_PFB_BOOT_0_RAM_WIDTH_128 | 2250 NV04_PFB_BOOT_0_RAM_AMOUNT, 2251 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); 2252 2253 } else if (peek_fb(dev, fb, 0) != patt) { 2254 if (read_back_fb(dev, fb, 0x800000, patt)) 2255 bios_md32(bios, NV04_PFB_BOOT_0, 2256 NV04_PFB_BOOT_0_RAM_AMOUNT, 2257 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 2258 else 2259 bios_md32(bios, NV04_PFB_BOOT_0, 2260 NV04_PFB_BOOT_0_RAM_AMOUNT, 2261 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); 2262 2263 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE, 2264 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT); 2265 2266 } else if (!read_back_fb(dev, fb, 0x800000, patt)) { 2267 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, 2268 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 2269 2270 } 2271 2272 /* Refresh on, sequencer on */ 2273 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0); 2274 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20); 2275 2276 io_mapping_free(fb); 2277 return 0; 2278} 2279 2280static const uint8_t * 2281nv05_memory_config(struct nvbios *bios) 2282{ 2283 /* Defaults for BIOSes lacking a memory config table */ 2284 static const uint8_t default_config_tab[][2] = { 2285 { 0x24, 0x00 }, 2286 { 0x28, 0x00 }, 2287 { 0x24, 0x01 }, 2288 { 0x1f, 0x00 }, 2289 { 0x0f, 0x00 }, 2290 { 0x17, 0x00 }, 2291 { 0x06, 0x00 }, 2292 { 0x00, 0x00 } 2293 }; 2294 int i = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 2295 NV_PEXTDEV_BOOT_0_RAMCFG) >> 2; 2296 2297 if (bios->legacy.mem_init_tbl_ptr) 2298 return &bios->data[bios->legacy.mem_init_tbl_ptr + 2 * i]; 2299 else 2300 return default_config_tab[i]; 2301} 2302 2303static int 2304nv05_init_compute_mem(struct nvbios *bios) 2305{ 2306 struct drm_device *dev = bios->dev; 2307 const uint8_t *ramcfg = nv05_memory_config(bios); 2308 uint32_t patt = 0xdeadbeef; 2309 struct io_mapping *fb; 2310 int i, v; 2311 2312 /* Map the framebuffer aperture */ 2313 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1), 2314 pci_resource_len(dev->pdev, 1)); 2315 if (!fb) 2316 return -ENOMEM; 2317 2318 /* Sequencer off */ 2319 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20); 2320 2321 if (bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE) 2322 goto out; 2323 2324 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0); 2325 2326 /* If present load the hardcoded scrambling table */ 2327 if (bios->legacy.mem_init_tbl_ptr) { 2328 uint32_t *scramble_tab = (uint32_t *)&bios->data[ 2329 bios->legacy.mem_init_tbl_ptr + 0x10]; 2330 2331 for (i = 0; i < 8; i++) 2332 bios_wr32(bios, NV04_PFB_SCRAMBLE(i), 2333 ROM32(scramble_tab[i])); 2334 } 2335 2336 /* Set memory type/width/length defaults depending on the straps */ 2337 bios_md32(bios, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]); 2338 2339 if (ramcfg[1] & 0x80) 2340 bios_md32(bios, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE); 2341 2342 bios_md32(bios, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20); 2343 bios_md32(bios, NV04_PFB_CFG1, 0, 1); 2344 2345 /* Probe memory bus width */ 2346 for (i = 0; i < 4; i++) 2347 poke_fb(dev, fb, 4 * i, patt); 2348 2349 if (peek_fb(dev, fb, 0xc) != patt) 2350 bios_md32(bios, NV04_PFB_BOOT_0, 2351 NV04_PFB_BOOT_0_RAM_WIDTH_128, 0); 2352 2353 /* Probe memory length */ 2354 v = bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT; 2355 2356 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB && 2357 (!read_back_fb(dev, fb, 0x1000000, ++patt) || 2358 !read_back_fb(dev, fb, 0, ++patt))) 2359 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, 2360 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB); 2361 2362 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB && 2363 !read_back_fb(dev, fb, 0x800000, ++patt)) 2364 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, 2365 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 2366 2367 if (!read_back_fb(dev, fb, 0x400000, ++patt)) 2368 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, 2369 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); 2370 2371out: 2372 /* Sequencer on */ 2373 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20); 2374 2375 io_mapping_free(fb); 2376 return 0; 2377} 2378 2379static int 2380nv10_init_compute_mem(struct nvbios *bios) 2381{ 2382 struct drm_device *dev = bios->dev; 2383 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2384 const int mem_width[] = { 0x10, 0x00, 0x20 }; 2385 const int mem_width_count = (dev_priv->chipset >= 0x17 ? 3 : 2); 2386 uint32_t patt = 0xdeadbeef; 2387 struct io_mapping *fb; 2388 int i, j, k; 2389 2390 /* Map the framebuffer aperture */ 2391 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1), 2392 pci_resource_len(dev->pdev, 1)); 2393 if (!fb) 2394 return -ENOMEM; 2395 2396 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1); 2397 2398 /* Probe memory bus width */ 2399 for (i = 0; i < mem_width_count; i++) { 2400 bios_md32(bios, NV04_PFB_CFG0, 0x30, mem_width[i]); 2401 2402 for (j = 0; j < 4; j++) { 2403 for (k = 0; k < 4; k++) 2404 poke_fb(dev, fb, 0x1c, 0); 2405 2406 poke_fb(dev, fb, 0x1c, patt); 2407 poke_fb(dev, fb, 0x3c, 0); 2408 2409 if (peek_fb(dev, fb, 0x1c) == patt) 2410 goto mem_width_found; 2411 } 2412 } 2413 2414mem_width_found: 2415 patt <<= 1; 2416 2417 /* Probe amount of installed memory */ 2418 for (i = 0; i < 4; i++) { 2419 int off = bios_rd32(bios, NV04_PFB_FIFO_DATA) - 0x100000; 2420 2421 poke_fb(dev, fb, off, patt); 2422 poke_fb(dev, fb, 0, 0); 2423 2424 peek_fb(dev, fb, 0); 2425 peek_fb(dev, fb, 0); 2426 peek_fb(dev, fb, 0); 2427 peek_fb(dev, fb, 0); 2428 2429 if (peek_fb(dev, fb, off) == patt) 2430 goto amount_found; 2431 } 2432 2433 /* IC missing - disable the upper half memory space. */ 2434 bios_md32(bios, NV04_PFB_CFG0, 0x1000, 0); 2435 2436amount_found: 2437 io_mapping_free(fb); 2438 return 0; 2439} 2440 2441static int 2442nv20_init_compute_mem(struct nvbios *bios) 2443{ 2444 struct drm_device *dev = bios->dev; 2445 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2446 uint32_t mask = (dev_priv->chipset >= 0x25 ? 0x300 : 0x900); 2447 uint32_t amount, off; 2448 struct io_mapping *fb; 2449 2450 /* Map the framebuffer aperture */ 2451 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1), 2452 pci_resource_len(dev->pdev, 1)); 2453 if (!fb) 2454 return -ENOMEM; 2455 2456 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1); 2457 2458 /* Allow full addressing */ 2459 bios_md32(bios, NV04_PFB_CFG0, 0, mask); 2460 2461 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA); 2462 for (off = amount; off > 0x2000000; off -= 0x2000000) 2463 poke_fb(dev, fb, off - 4, off); 2464 2465 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA); 2466 if (amount != peek_fb(dev, fb, amount - 4)) 2467 /* IC missing - disable the upper half memory space. */ 2468 bios_md32(bios, NV04_PFB_CFG0, mask, 0); 2469 2470 io_mapping_free(fb); 2471 return 0; 2472} 2473 2474static int 2475init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2476{ 2477 /* 2478 * INIT_COMPUTE_MEM opcode: 0x63 ('c') 2479 * 2480 * offset (8 bit): opcode 2481 * 2482 * This opcode is meant to set the PFB memory config registers 2483 * appropriately so that we can correctly calculate how much VRAM it 2484 * has (on nv10 and better chipsets the amount of installed VRAM is 2485 * subsequently reported in NV_PFB_CSTATUS (0x10020C)). 2486 * 2487 * The implementation of this opcode in general consists of several 2488 * parts: 2489 * 2490 * 1) Determination of memory type and density. Only necessary for 2491 * really old chipsets, the memory type reported by the strap bits 2492 * (0x101000) is assumed to be accurate on nv05 and newer. 2493 * 2494 * 2) Determination of the memory bus width. Usually done by a cunning 2495 * combination of writes to offsets 0x1c and 0x3c in the fb, and 2496 * seeing whether the written values are read back correctly. 2497 * 2498 * Only necessary on nv0x-nv1x and nv34, on the other cards we can 2499 * trust the straps. 2500 * 2501 * 3) Determination of how many of the card's RAM pads have ICs 2502 * attached, usually done by a cunning combination of writes to an 2503 * offset slightly less than the maximum memory reported by 2504 * NV_PFB_CSTATUS, then seeing if the test pattern can be read back. 2505 * 2506 * This appears to be a NOP on IGPs and NV4x or newer chipsets, both io 2507 * logs of the VBIOS and kmmio traces of the binary driver POSTing the 2508 * card show nothing being done for this opcode. Why is it still listed 2509 * in the table?! 2510 */ 2511 2512 /* no iexec->execute check by design */ 2513 2514 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2515 int ret; 2516 2517 if (dev_priv->chipset >= 0x40 || 2518 dev_priv->chipset == 0x1a || 2519 dev_priv->chipset == 0x1f) 2520 ret = 0; 2521 else if (dev_priv->chipset >= 0x20 && 2522 dev_priv->chipset != 0x34) 2523 ret = nv20_init_compute_mem(bios); 2524 else if (dev_priv->chipset >= 0x10) 2525 ret = nv10_init_compute_mem(bios); 2526 else if (dev_priv->chipset >= 0x5) 2527 ret = nv05_init_compute_mem(bios); 2528 else 2529 ret = nv04_init_compute_mem(bios); 2530 2531 if (ret) 2532 return ret; 2533 2534 return 1; 2535} 2536 2537static int 2538init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2539{ 2540 /* 2541 * INIT_RESET opcode: 0x65 ('e') 2542 * 2543 * offset (8 bit): opcode 2544 * offset + 1 (32 bit): register 2545 * offset + 5 (32 bit): value1 2546 * offset + 9 (32 bit): value2 2547 * 2548 * Assign "value1" to "register", then assign "value2" to "register" 2549 */ 2550 2551 uint32_t reg = ROM32(bios->data[offset + 1]); 2552 uint32_t value1 = ROM32(bios->data[offset + 5]); 2553 uint32_t value2 = ROM32(bios->data[offset + 9]); 2554 uint32_t pci_nv_19, pci_nv_20; 2555 2556 /* no iexec->execute check by design */ 2557 2558 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19); 2559 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19 & ~0xf00); 2560 2561 bios_wr32(bios, reg, value1); 2562 2563 udelay(10); 2564 2565 bios_wr32(bios, reg, value2); 2566 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19); 2567 2568 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20); 2569 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */ 2570 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20); 2571 2572 return 13; 2573} 2574 2575static int 2576init_configure_mem(struct nvbios *bios, uint16_t offset, 2577 struct init_exec *iexec) 2578{ 2579 /* 2580 * INIT_CONFIGURE_MEM opcode: 0x66 ('f') 2581 * 2582 * offset (8 bit): opcode 2583 * 2584 * Equivalent to INIT_DONE on bios version 3 or greater. 2585 * For early bios versions, sets up the memory registers, using values 2586 * taken from the memory init table 2587 */ 2588 2589 /* no iexec->execute check by design */ 2590 2591 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4); 2592 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6; 2593 uint32_t reg, data; 2594 2595 if (bios->major_version > 2) 2596 return 0; 2597 2598 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd( 2599 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20); 2600 2601 if (bios->data[meminitoffs] & 1) 2602 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr; 2603 2604 for (reg = ROM32(bios->data[seqtbloffs]); 2605 reg != 0xffffffff; 2606 reg = ROM32(bios->data[seqtbloffs += 4])) { 2607 2608 switch (reg) { 2609 case NV04_PFB_PRE: 2610 data = NV04_PFB_PRE_CMD_PRECHARGE; 2611 break; 2612 case NV04_PFB_PAD: 2613 data = NV04_PFB_PAD_CKE_NORMAL; 2614 break; 2615 case NV04_PFB_REF: 2616 data = NV04_PFB_REF_CMD_REFRESH; 2617 break; 2618 default: 2619 data = ROM32(bios->data[meminitdata]); 2620 meminitdata += 4; 2621 if (data == 0xffffffff) 2622 continue; 2623 } 2624 2625 bios_wr32(bios, reg, data); 2626 } 2627 2628 return 1; 2629} 2630 2631static int 2632init_configure_clk(struct nvbios *bios, uint16_t offset, 2633 struct init_exec *iexec) 2634{ 2635 /* 2636 * INIT_CONFIGURE_CLK opcode: 0x67 ('g') 2637 * 2638 * offset (8 bit): opcode 2639 * 2640 * Equivalent to INIT_DONE on bios version 3 or greater. 2641 * For early bios versions, sets up the NVClk and MClk PLLs, using 2642 * values taken from the memory init table 2643 */ 2644 2645 /* no iexec->execute check by design */ 2646 2647 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4); 2648 int clock; 2649 2650 if (bios->major_version > 2) 2651 return 0; 2652 2653 clock = ROM16(bios->data[meminitoffs + 4]) * 10; 2654 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock); 2655 2656 clock = ROM16(bios->data[meminitoffs + 2]) * 10; 2657 if (bios->data[meminitoffs] & 1) /* DDR */ 2658 clock *= 2; 2659 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock); 2660 2661 return 1; 2662} 2663 2664static int 2665init_configure_preinit(struct nvbios *bios, uint16_t offset, 2666 struct init_exec *iexec) 2667{ 2668 /* 2669 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h') 2670 * 2671 * offset (8 bit): opcode 2672 * 2673 * Equivalent to INIT_DONE on bios version 3 or greater. 2674 * For early bios versions, does early init, loading ram and crystal 2675 * configuration from straps into CR3C 2676 */ 2677 2678 /* no iexec->execute check by design */ 2679 2680 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0); 2681 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & 0x40) >> 6; 2682 2683 if (bios->major_version > 2) 2684 return 0; 2685 2686 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, 2687 NV_CIO_CRE_SCRATCH4__INDEX, cr3c); 2688 2689 return 1; 2690} 2691 2692static int 2693init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2694{ 2695 /* 2696 * INIT_IO opcode: 0x69 ('i') 2697 * 2698 * offset (8 bit): opcode 2699 * offset + 1 (16 bit): CRTC port 2700 * offset + 3 (8 bit): mask 2701 * offset + 4 (8 bit): data 2702 * 2703 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port" 2704 */ 2705 2706 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2707 uint16_t crtcport = ROM16(bios->data[offset + 1]); 2708 uint8_t mask = bios->data[offset + 3]; 2709 uint8_t data = bios->data[offset + 4]; 2710 2711 if (!iexec->execute) 2712 return 5; 2713 2714 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n", 2715 offset, crtcport, mask, data); 2716 2717 /* 2718 * I have no idea what this does, but NVIDIA do this magic sequence 2719 * in the places where this INIT_IO happens.. 2720 */ 2721 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) { 2722 int i; 2723 2724 bios_wr32(bios, 0x614100, (bios_rd32( 2725 bios, 0x614100) & 0x0fffffff) | 0x00800000); 2726 2727 bios_wr32(bios, 0x00e18c, bios_rd32( 2728 bios, 0x00e18c) | 0x00020000); 2729 2730 bios_wr32(bios, 0x614900, (bios_rd32( 2731 bios, 0x614900) & 0x0fffffff) | 0x00800000); 2732 2733 bios_wr32(bios, 0x000200, bios_rd32( 2734 bios, 0x000200) & ~0x40000000); 2735 2736 mdelay(10); 2737 2738 bios_wr32(bios, 0x00e18c, bios_rd32( 2739 bios, 0x00e18c) & ~0x00020000); 2740 2741 bios_wr32(bios, 0x000200, bios_rd32( 2742 bios, 0x000200) | 0x40000000); 2743 2744 bios_wr32(bios, 0x614100, 0x00800018); 2745 bios_wr32(bios, 0x614900, 0x00800018); 2746 2747 mdelay(10); 2748 2749 bios_wr32(bios, 0x614100, 0x10000018); 2750 bios_wr32(bios, 0x614900, 0x10000018); 2751 2752 for (i = 0; i < 3; i++) 2753 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32( 2754 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0); 2755 2756 for (i = 0; i < 2; i++) 2757 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32( 2758 bios, 0x614300 + (i*0x800)) & 0xfffff0f0); 2759 2760 for (i = 0; i < 3; i++) 2761 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32( 2762 bios, 0x614380 + (i*0x800)) & 0xfffff0f0); 2763 2764 for (i = 0; i < 2; i++) 2765 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32( 2766 bios, 0x614200 + (i*0x800)) & 0xfffffff0); 2767 2768 for (i = 0; i < 2; i++) 2769 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32( 2770 bios, 0x614108 + (i*0x800)) & 0x0fffffff); 2771 return 5; 2772 } 2773 2774 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) | 2775 data); 2776 return 5; 2777} 2778 2779static int 2780init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2781{ 2782 /* 2783 * INIT_SUB opcode: 0x6B ('k') 2784 * 2785 * offset (8 bit): opcode 2786 * offset + 1 (8 bit): script number 2787 * 2788 * Execute script number "script number", as a subroutine 2789 */ 2790 2791 uint8_t sub = bios->data[offset + 1]; 2792 2793 if (!iexec->execute) 2794 return 2; 2795 2796 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub); 2797 2798 parse_init_table(bios, 2799 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]), 2800 iexec); 2801 2802 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub); 2803 2804 return 2; 2805} 2806 2807static int 2808init_ram_condition(struct nvbios *bios, uint16_t offset, 2809 struct init_exec *iexec) 2810{ 2811 /* 2812 * INIT_RAM_CONDITION opcode: 0x6D ('m') 2813 * 2814 * offset (8 bit): opcode 2815 * offset + 1 (8 bit): mask 2816 * offset + 2 (8 bit): cmpval 2817 * 2818 * Test if (NV04_PFB_BOOT_0 & "mask") equals "cmpval". 2819 * If condition not met skip subsequent opcodes until condition is 2820 * inverted (INIT_NOT), or we hit INIT_RESUME 2821 */ 2822 2823 uint8_t mask = bios->data[offset + 1]; 2824 uint8_t cmpval = bios->data[offset + 2]; 2825 uint8_t data; 2826 2827 if (!iexec->execute) 2828 return 3; 2829 2830 data = bios_rd32(bios, NV04_PFB_BOOT_0) & mask; 2831 2832 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n", 2833 offset, data, cmpval); 2834 2835 if (data == cmpval) 2836 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 2837 else { 2838 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 2839 iexec->execute = false; 2840 } 2841 2842 return 3; 2843} 2844 2845static int 2846init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2847{ 2848 /* 2849 * INIT_NV_REG opcode: 0x6E ('n') 2850 * 2851 * offset (8 bit): opcode 2852 * offset + 1 (32 bit): register 2853 * offset + 5 (32 bit): mask 2854 * offset + 9 (32 bit): data 2855 * 2856 * Assign ((REGVAL("register") & "mask") | "data") to "register" 2857 */ 2858 2859 uint32_t reg = ROM32(bios->data[offset + 1]); 2860 uint32_t mask = ROM32(bios->data[offset + 5]); 2861 uint32_t data = ROM32(bios->data[offset + 9]); 2862 2863 if (!iexec->execute) 2864 return 13; 2865 2866 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n", 2867 offset, reg, mask, data); 2868 2869 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data); 2870 2871 return 13; 2872} 2873 2874static int 2875init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2876{ 2877 /* 2878 * INIT_MACRO opcode: 0x6F ('o') 2879 * 2880 * offset (8 bit): opcode 2881 * offset + 1 (8 bit): macro number 2882 * 2883 * Look up macro index "macro number" in the macro index table. 2884 * The macro index table entry has 1 byte for the index in the macro 2885 * table, and 1 byte for the number of times to repeat the macro. 2886 * The macro table entry has 4 bytes for the register address and 2887 * 4 bytes for the value to write to that register 2888 */ 2889 2890 uint8_t macro_index_tbl_idx = bios->data[offset + 1]; 2891 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE); 2892 uint8_t macro_tbl_idx = bios->data[tmp]; 2893 uint8_t count = bios->data[tmp + 1]; 2894 uint32_t reg, data; 2895 int i; 2896 2897 if (!iexec->execute) 2898 return 2; 2899 2900 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, " 2901 "Count: 0x%02X\n", 2902 offset, macro_index_tbl_idx, macro_tbl_idx, count); 2903 2904 for (i = 0; i < count; i++) { 2905 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE; 2906 2907 reg = ROM32(bios->data[macroentryptr]); 2908 data = ROM32(bios->data[macroentryptr + 4]); 2909 2910 bios_wr32(bios, reg, data); 2911 } 2912 2913 return 2; 2914} 2915 2916static int 2917init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2918{ 2919 /* 2920 * INIT_DONE opcode: 0x71 ('q') 2921 * 2922 * offset (8 bit): opcode 2923 * 2924 * End the current script 2925 */ 2926 2927 /* mild retval abuse to stop parsing this table */ 2928 return 0; 2929} 2930 2931static int 2932init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2933{ 2934 /* 2935 * INIT_RESUME opcode: 0x72 ('r') 2936 * 2937 * offset (8 bit): opcode 2938 * 2939 * End the current execute / no-execute condition 2940 */ 2941 2942 if (iexec->execute) 2943 return 1; 2944 2945 iexec->execute = true; 2946 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset); 2947 2948 return 1; 2949} 2950 2951static int 2952init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2953{ 2954 /* 2955 * INIT_TIME opcode: 0x74 ('t') 2956 * 2957 * offset (8 bit): opcode 2958 * offset + 1 (16 bit): time 2959 * 2960 * Sleep for "time" microseconds. 2961 */ 2962 2963 unsigned time = ROM16(bios->data[offset + 1]); 2964 2965 if (!iexec->execute) 2966 return 3; 2967 2968 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n", 2969 offset, time); 2970 2971 if (time < 1000) 2972 udelay(time); 2973 else 2974 msleep((time + 900) / 1000); 2975 2976 return 3; 2977} 2978 2979static int 2980init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2981{ 2982 /* 2983 * INIT_CONDITION opcode: 0x75 ('u') 2984 * 2985 * offset (8 bit): opcode 2986 * offset + 1 (8 bit): condition number 2987 * 2988 * Check condition "condition number" in the condition table. 2989 * If condition not met skip subsequent opcodes until condition is 2990 * inverted (INIT_NOT), or we hit INIT_RESUME 2991 */ 2992 2993 uint8_t cond = bios->data[offset + 1]; 2994 2995 if (!iexec->execute) 2996 return 2; 2997 2998 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond); 2999 3000 if (bios_condition_met(bios, offset, cond)) 3001 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 3002 else { 3003 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 3004 iexec->execute = false; 3005 } 3006 3007 return 2; 3008} 3009 3010static int 3011init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3012{ 3013 /* 3014 * INIT_IO_CONDITION opcode: 0x76 3015 * 3016 * offset (8 bit): opcode 3017 * offset + 1 (8 bit): condition number 3018 * 3019 * Check condition "condition number" in the io condition table. 3020 * If condition not met skip subsequent opcodes until condition is 3021 * inverted (INIT_NOT), or we hit INIT_RESUME 3022 */ 3023 3024 uint8_t cond = bios->data[offset + 1]; 3025 3026 if (!iexec->execute) 3027 return 2; 3028 3029 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond); 3030 3031 if (io_condition_met(bios, offset, cond)) 3032 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 3033 else { 3034 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 3035 iexec->execute = false; 3036 } 3037 3038 return 2; 3039} 3040 3041static int 3042init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3043{ 3044 /* 3045 * INIT_INDEX_IO opcode: 0x78 ('x') 3046 * 3047 * offset (8 bit): opcode 3048 * offset + 1 (16 bit): CRTC port 3049 * offset + 3 (8 bit): CRTC index 3050 * offset + 4 (8 bit): mask 3051 * offset + 5 (8 bit): data 3052 * 3053 * Read value at index "CRTC index" on "CRTC port", AND with "mask", 3054 * OR with "data", write-back 3055 */ 3056 3057 uint16_t crtcport = ROM16(bios->data[offset + 1]); 3058 uint8_t crtcindex = bios->data[offset + 3]; 3059 uint8_t mask = bios->data[offset + 4]; 3060 uint8_t data = bios->data[offset + 5]; 3061 uint8_t value; 3062 3063 if (!iexec->execute) 3064 return 6; 3065 3066 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 3067 "Data: 0x%02X\n", 3068 offset, crtcport, crtcindex, mask, data); 3069 3070 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data; 3071 bios_idxprt_wr(bios, crtcport, crtcindex, value); 3072 3073 return 6; 3074} 3075 3076static int 3077init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3078{ 3079 /* 3080 * INIT_PLL opcode: 0x79 ('y') 3081 * 3082 * offset (8 bit): opcode 3083 * offset + 1 (32 bit): register 3084 * offset + 5 (16 bit): freq 3085 * 3086 * Set PLL register "register" to coefficients for frequency (10kHz) 3087 * "freq" 3088 */ 3089 3090 uint32_t reg = ROM32(bios->data[offset + 1]); 3091 uint16_t freq = ROM16(bios->data[offset + 5]); 3092 3093 if (!iexec->execute) 3094 return 7; 3095 3096 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq); 3097 3098 setPLL(bios, reg, freq * 10); 3099 3100 return 7; 3101} 3102 3103static int 3104init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3105{ 3106 /* 3107 * INIT_ZM_REG opcode: 0x7A ('z') 3108 * 3109 * offset (8 bit): opcode 3110 * offset + 1 (32 bit): register 3111 * offset + 5 (32 bit): value 3112 * 3113 * Assign "value" to "register" 3114 */ 3115 3116 uint32_t reg = ROM32(bios->data[offset + 1]); 3117 uint32_t value = ROM32(bios->data[offset + 5]); 3118 3119 if (!iexec->execute) 3120 return 9; 3121 3122 if (reg == 0x000200) 3123 value |= 1; 3124 3125 bios_wr32(bios, reg, value); 3126 3127 return 9; 3128} 3129 3130static int 3131init_ram_restrict_pll(struct nvbios *bios, uint16_t offset, 3132 struct init_exec *iexec) 3133{ 3134 /* 3135 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('') 3136 * 3137 * offset (8 bit): opcode 3138 * offset + 1 (8 bit): PLL type 3139 * offset + 2 (32 bit): frequency 0 3140 * 3141 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at 3142 * ram_restrict_table_ptr. The value read from there is used to select 3143 * a frequency from the table starting at 'frequency 0' to be 3144 * programmed into the PLL corresponding to 'type'. 3145 * 3146 * The PLL limits table on cards using this opcode has a mapping of 3147 * 'type' to the relevant registers. 3148 */ 3149 3150 struct drm_device *dev = bios->dev; 3151 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2; 3152 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap]; 3153 uint8_t type = bios->data[offset + 1]; 3154 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]); 3155 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry; 3156 int len = 2 + bios->ram_restrict_group_count * 4; 3157 int i; 3158 3159 if (!iexec->execute) 3160 return len; 3161 3162 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) { 3163 NV_ERROR(dev, "PLL limits table not version 3.x\n"); 3164 return len; /* deliberate, allow default clocks to remain */ 3165 } 3166 3167 entry = pll_limits + pll_limits[1]; 3168 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) { 3169 if (entry[0] == type) { 3170 uint32_t reg = ROM32(entry[3]); 3171 3172 BIOSLOG(bios, "0x%04X: " 3173 "Type %02x Reg 0x%08x Freq %dKHz\n", 3174 offset, type, reg, freq); 3175 3176 setPLL(bios, reg, freq); 3177 return len; 3178 } 3179 } 3180 3181 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type); 3182 return len; 3183} 3184 3185static int 3186init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3187{ 3188 /* 3189 * INIT_8C opcode: 0x8C ('') 3190 * 3191 * NOP so far.... 3192 * 3193 */ 3194 3195 return 1; 3196} 3197 3198static int 3199init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3200{ 3201 /* 3202 * INIT_8D opcode: 0x8D ('') 3203 * 3204 * NOP so far.... 3205 * 3206 */ 3207 3208 return 1; 3209} 3210 3211static int 3212init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3213{ 3214 /* 3215 * INIT_GPIO opcode: 0x8E ('') 3216 * 3217 * offset (8 bit): opcode 3218 * 3219 * Loop over all entries in the DCB GPIO table, and initialise 3220 * each GPIO according to various values listed in each entry 3221 */ 3222 3223 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 3224 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio; 3225 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c }; 3226 int i; 3227 3228 if (dev_priv->card_type < NV_50) { 3229 NV_ERROR(bios->dev, "INIT_GPIO on unsupported chipset\n"); 3230 return 1; 3231 } 3232 3233 if (!iexec->execute) 3234 return 1; 3235 3236 for (i = 0; i < bios->dcb.gpio.entries; i++) { 3237 struct dcb_gpio_entry *gpio = &bios->dcb.gpio.entry[i]; 3238 uint32_t r, s, v; 3239 3240 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, gpio->entry); 3241 3242 BIOSLOG(bios, "0x%04X: set gpio 0x%02x, state %d\n", 3243 offset, gpio->tag, gpio->state_default); 3244 if (bios->execute) 3245 pgpio->set(bios->dev, gpio->tag, gpio->state_default); 3246 3247 /* The NVIDIA binary driver doesn't appear to actually do 3248 * any of this, my VBIOS does however. 3249 */ 3250 /* Not a clue, needs de-magicing */ 3251 r = nv50_gpio_ctl[gpio->line >> 4]; 3252 s = (gpio->line & 0x0f); 3253 v = bios_rd32(bios, r) & ~(0x00010001 << s); 3254 switch ((gpio->entry & 0x06000000) >> 25) { 3255 case 1: 3256 v |= (0x00000001 << s); 3257 break; 3258 case 2: 3259 v |= (0x00010000 << s); 3260 break; 3261 default: 3262 break; 3263 } 3264 bios_wr32(bios, r, v); 3265 } 3266 3267 return 1; 3268} 3269 3270static int 3271init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset, 3272 struct init_exec *iexec) 3273{ 3274 /* 3275 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('') 3276 * 3277 * offset (8 bit): opcode 3278 * offset + 1 (32 bit): reg 3279 * offset + 5 (8 bit): regincrement 3280 * offset + 6 (8 bit): count 3281 * offset + 7 (32 bit): value 1,1 3282 * ... 3283 * 3284 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at 3285 * ram_restrict_table_ptr. The value read from here is 'n', and 3286 * "value 1,n" gets written to "reg". This repeats "count" times and on 3287 * each iteration 'm', "reg" increases by "regincrement" and 3288 * "value m,n" is used. The extent of n is limited by a number read 3289 * from the 'M' BIT table, herein called "blocklen" 3290 */ 3291 3292 uint32_t reg = ROM32(bios->data[offset + 1]); 3293 uint8_t regincrement = bios->data[offset + 5]; 3294 uint8_t count = bios->data[offset + 6]; 3295 uint32_t strap_ramcfg, data; 3296 /* previously set by 'M' BIT table */ 3297 uint16_t blocklen = bios->ram_restrict_group_count * 4; 3298 int len = 7 + count * blocklen; 3299 uint8_t index; 3300 int i; 3301 3302 /* critical! to know the length of the opcode */; 3303 if (!blocklen) { 3304 NV_ERROR(bios->dev, 3305 "0x%04X: Zero block length - has the M table " 3306 "been parsed?\n", offset); 3307 return -EINVAL; 3308 } 3309 3310 if (!iexec->execute) 3311 return len; 3312 3313 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf; 3314 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg]; 3315 3316 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, " 3317 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n", 3318 offset, reg, regincrement, count, strap_ramcfg, index); 3319 3320 for (i = 0; i < count; i++) { 3321 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]); 3322 3323 bios_wr32(bios, reg, data); 3324 3325 reg += regincrement; 3326 } 3327 3328 return len; 3329} 3330 3331static int 3332init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3333{ 3334 /* 3335 * INIT_COPY_ZM_REG opcode: 0x90 ('') 3336 * 3337 * offset (8 bit): opcode 3338 * offset + 1 (32 bit): src reg 3339 * offset + 5 (32 bit): dst reg 3340 * 3341 * Put contents of "src reg" into "dst reg" 3342 */ 3343 3344 uint32_t srcreg = ROM32(bios->data[offset + 1]); 3345 uint32_t dstreg = ROM32(bios->data[offset + 5]); 3346 3347 if (!iexec->execute) 3348 return 9; 3349 3350 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg)); 3351 3352 return 9; 3353} 3354 3355static int 3356init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset, 3357 struct init_exec *iexec) 3358{ 3359 /* 3360 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('') 3361 * 3362 * offset (8 bit): opcode 3363 * offset + 1 (32 bit): dst reg 3364 * offset + 5 (8 bit): count 3365 * offset + 6 (32 bit): data 1 3366 * ... 3367 * 3368 * For each of "count" values write "data n" to "dst reg" 3369 */ 3370 3371 uint32_t reg = ROM32(bios->data[offset + 1]); 3372 uint8_t count = bios->data[offset + 5]; 3373 int len = 6 + count * 4; 3374 int i; 3375 3376 if (!iexec->execute) 3377 return len; 3378 3379 for (i = 0; i < count; i++) { 3380 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]); 3381 bios_wr32(bios, reg, data); 3382 } 3383 3384 return len; 3385} 3386 3387static int 3388init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3389{ 3390 /* 3391 * INIT_RESERVED opcode: 0x92 ('') 3392 * 3393 * offset (8 bit): opcode 3394 * 3395 * Seemingly does nothing 3396 */ 3397 3398 return 1; 3399} 3400 3401static int 3402init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3403{ 3404 /* 3405 * INIT_96 opcode: 0x96 ('') 3406 * 3407 * offset (8 bit): opcode 3408 * offset + 1 (32 bit): sreg 3409 * offset + 5 (8 bit): sshift 3410 * offset + 6 (8 bit): smask 3411 * offset + 7 (8 bit): index 3412 * offset + 8 (32 bit): reg 3413 * offset + 12 (32 bit): mask 3414 * offset + 16 (8 bit): shift 3415 * 3416 */ 3417 3418 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2); 3419 uint32_t reg = ROM32(bios->data[offset + 8]); 3420 uint32_t mask = ROM32(bios->data[offset + 12]); 3421 uint32_t val; 3422 3423 val = bios_rd32(bios, ROM32(bios->data[offset + 1])); 3424 if (bios->data[offset + 5] < 0x80) 3425 val >>= bios->data[offset + 5]; 3426 else 3427 val <<= (0x100 - bios->data[offset + 5]); 3428 val &= bios->data[offset + 6]; 3429 3430 val = bios->data[ROM16(bios->data[xlatptr]) + val]; 3431 val <<= bios->data[offset + 16]; 3432 3433 if (!iexec->execute) 3434 return 17; 3435 3436 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val); 3437 return 17; 3438} 3439 3440static int 3441init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3442{ 3443 /* 3444 * INIT_97 opcode: 0x97 ('') 3445 * 3446 * offset (8 bit): opcode 3447 * offset + 1 (32 bit): register 3448 * offset + 5 (32 bit): mask 3449 * offset + 9 (32 bit): value 3450 * 3451 * Adds "value" to "register" preserving the fields specified 3452 * by "mask" 3453 */ 3454 3455 uint32_t reg = ROM32(bios->data[offset + 1]); 3456 uint32_t mask = ROM32(bios->data[offset + 5]); 3457 uint32_t add = ROM32(bios->data[offset + 9]); 3458 uint32_t val; 3459 3460 val = bios_rd32(bios, reg); 3461 val = (val & mask) | ((val + add) & ~mask); 3462 3463 if (!iexec->execute) 3464 return 13; 3465 3466 bios_wr32(bios, reg, val); 3467 return 13; 3468} 3469 3470static int 3471init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3472{ 3473 /* 3474 * INIT_AUXCH opcode: 0x98 ('') 3475 * 3476 * offset (8 bit): opcode 3477 * offset + 1 (32 bit): address 3478 * offset + 5 (8 bit): count 3479 * offset + 6 (8 bit): mask 0 3480 * offset + 7 (8 bit): data 0 3481 * ... 3482 * 3483 */ 3484 3485 struct drm_device *dev = bios->dev; 3486 struct nouveau_i2c_chan *auxch; 3487 uint32_t addr = ROM32(bios->data[offset + 1]); 3488 uint8_t count = bios->data[offset + 5]; 3489 int len = 6 + count * 2; 3490 int ret, i; 3491 3492 if (!bios->display.output) { 3493 NV_ERROR(dev, "INIT_AUXCH: no active output\n"); 3494 return len; 3495 } 3496 3497 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index); 3498 if (!auxch) { 3499 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n", 3500 bios->display.output->i2c_index); 3501 return len; 3502 } 3503 3504 if (!iexec->execute) 3505 return len; 3506 3507 offset += 6; 3508 for (i = 0; i < count; i++, offset += 2) { 3509 uint8_t data; 3510 3511 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1); 3512 if (ret) { 3513 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret); 3514 return len; 3515 } 3516 3517 data &= bios->data[offset + 0]; 3518 data |= bios->data[offset + 1]; 3519 3520 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1); 3521 if (ret) { 3522 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret); 3523 return len; 3524 } 3525 } 3526 3527 return len; 3528} 3529 3530static int 3531init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3532{ 3533 /* 3534 * INIT_ZM_AUXCH opcode: 0x99 ('') 3535 * 3536 * offset (8 bit): opcode 3537 * offset + 1 (32 bit): address 3538 * offset + 5 (8 bit): count 3539 * offset + 6 (8 bit): data 0 3540 * ... 3541 * 3542 */ 3543 3544 struct drm_device *dev = bios->dev; 3545 struct nouveau_i2c_chan *auxch; 3546 uint32_t addr = ROM32(bios->data[offset + 1]); 3547 uint8_t count = bios->data[offset + 5]; 3548 int len = 6 + count; 3549 int ret, i; 3550 3551 if (!bios->display.output) { 3552 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n"); 3553 return len; 3554 } 3555 3556 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index); 3557 if (!auxch) { 3558 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n", 3559 bios->display.output->i2c_index); 3560 return len; 3561 } 3562 3563 if (!iexec->execute) 3564 return len; 3565 3566 offset += 6; 3567 for (i = 0; i < count; i++, offset++) { 3568 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1); 3569 if (ret) { 3570 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret); 3571 return len; 3572 } 3573 } 3574 3575 return len; 3576} 3577 3578static int 3579init_i2c_long_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3580{ 3581 /* 3582 * INIT_I2C_LONG_IF opcode: 0x9A ('') 3583 * 3584 * offset (8 bit): opcode 3585 * offset + 1 (8 bit): DCB I2C table entry index 3586 * offset + 2 (8 bit): I2C slave address 3587 * offset + 3 (16 bit): I2C register 3588 * offset + 5 (8 bit): mask 3589 * offset + 6 (8 bit): data 3590 * 3591 * Read the register given by "I2C register" on the device addressed 3592 * by "I2C slave address" on the I2C bus given by "DCB I2C table 3593 * entry index". Compare the result AND "mask" to "data". 3594 * If they're not equal, skip subsequent opcodes until condition is 3595 * inverted (INIT_NOT), or we hit INIT_RESUME 3596 */ 3597 3598 uint8_t i2c_index = bios->data[offset + 1]; 3599 uint8_t i2c_address = bios->data[offset + 2] >> 1; 3600 uint8_t reglo = bios->data[offset + 3]; 3601 uint8_t reghi = bios->data[offset + 4]; 3602 uint8_t mask = bios->data[offset + 5]; 3603 uint8_t data = bios->data[offset + 6]; 3604 struct nouveau_i2c_chan *chan; 3605 uint8_t buf0[2] = { reghi, reglo }; 3606 uint8_t buf1[1]; 3607 struct i2c_msg msg[2] = { 3608 { i2c_address, 0, 1, buf0 }, 3609 { i2c_address, I2C_M_RD, 1, buf1 }, 3610 }; 3611 int ret; 3612 3613 /* no execute check by design */ 3614 3615 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n", 3616 offset, i2c_index, i2c_address); 3617 3618 chan = init_i2c_device_find(bios->dev, i2c_index); 3619 if (!chan) 3620 return -ENODEV; 3621 3622 3623 ret = i2c_transfer(&chan->adapter, msg, 2); 3624 if (ret < 0) { 3625 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: [no device], " 3626 "Mask: 0x%02X, Data: 0x%02X\n", 3627 offset, reghi, reglo, mask, data); 3628 iexec->execute = 0; 3629 return 7; 3630 } 3631 3632 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: 0x%02X, " 3633 "Mask: 0x%02X, Data: 0x%02X\n", 3634 offset, reghi, reglo, buf1[0], mask, data); 3635 3636 iexec->execute = ((buf1[0] & mask) == data); 3637 3638 return 7; 3639} 3640 3641static struct init_tbl_entry itbl_entry[] = { 3642 /* command name , id , length , offset , mult , command handler */ 3643 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */ 3644 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog }, 3645 { "INIT_REPEAT" , 0x33, init_repeat }, 3646 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll }, 3647 { "INIT_END_REPEAT" , 0x36, init_end_repeat }, 3648 { "INIT_COPY" , 0x37, init_copy }, 3649 { "INIT_NOT" , 0x38, init_not }, 3650 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition }, 3651 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition }, 3652 { "INIT_OP_3B" , 0x3B, init_op_3b }, 3653 { "INIT_OP_3C" , 0x3C, init_op_3c }, 3654 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched }, 3655 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 }, 3656 { "INIT_PLL2" , 0x4B, init_pll2 }, 3657 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte }, 3658 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte }, 3659 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c }, 3660 { "INIT_TMDS" , 0x4F, init_tmds }, 3661 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group }, 3662 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch }, 3663 { "INIT_CR" , 0x52, init_cr }, 3664 { "INIT_ZM_CR" , 0x53, init_zm_cr }, 3665 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group }, 3666 { "INIT_CONDITION_TIME" , 0x56, init_condition_time }, 3667 { "INIT_LTIME" , 0x57, init_ltime }, 3668 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence }, 3669 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */ 3670 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct }, 3671 { "INIT_I2C_IF" , 0x5E, init_i2c_if }, 3672 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg }, 3673 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io }, 3674 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem }, 3675 { "INIT_RESET" , 0x65, init_reset }, 3676 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem }, 3677 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk }, 3678 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit }, 3679 { "INIT_IO" , 0x69, init_io }, 3680 { "INIT_SUB" , 0x6B, init_sub }, 3681 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition }, 3682 { "INIT_NV_REG" , 0x6E, init_nv_reg }, 3683 { "INIT_MACRO" , 0x6F, init_macro }, 3684 { "INIT_DONE" , 0x71, init_done }, 3685 { "INIT_RESUME" , 0x72, init_resume }, 3686 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */ 3687 { "INIT_TIME" , 0x74, init_time }, 3688 { "INIT_CONDITION" , 0x75, init_condition }, 3689 { "INIT_IO_CONDITION" , 0x76, init_io_condition }, 3690 { "INIT_INDEX_IO" , 0x78, init_index_io }, 3691 { "INIT_PLL" , 0x79, init_pll }, 3692 { "INIT_ZM_REG" , 0x7A, init_zm_reg }, 3693 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll }, 3694 { "INIT_8C" , 0x8C, init_8c }, 3695 { "INIT_8D" , 0x8D, init_8d }, 3696 { "INIT_GPIO" , 0x8E, init_gpio }, 3697 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group }, 3698 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg }, 3699 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched }, 3700 { "INIT_RESERVED" , 0x92, init_reserved }, 3701 { "INIT_96" , 0x96, init_96 }, 3702 { "INIT_97" , 0x97, init_97 }, 3703 { "INIT_AUXCH" , 0x98, init_auxch }, 3704 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch }, 3705 { "INIT_I2C_LONG_IF" , 0x9A, init_i2c_long_if }, 3706 { NULL , 0 , NULL } 3707}; 3708 3709#define MAX_TABLE_OPS 1000 3710 3711static int 3712parse_init_table(struct nvbios *bios, unsigned int offset, 3713 struct init_exec *iexec) 3714{ 3715 /* 3716 * Parses all commands in an init table. 3717 * 3718 * We start out executing all commands found in the init table. Some 3719 * opcodes may change the status of iexec->execute to SKIP, which will 3720 * cause the following opcodes to perform no operation until the value 3721 * is changed back to EXECUTE. 3722 */ 3723 3724 int count = 0, i, ret; 3725 uint8_t id; 3726 3727 /* 3728 * Loop until INIT_DONE causes us to break out of the loop 3729 * (or until offset > bios length just in case... ) 3730 * (and no more than MAX_TABLE_OPS iterations, just in case... ) 3731 */ 3732 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) { 3733 id = bios->data[offset]; 3734 3735 /* Find matching id in itbl_entry */ 3736 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++) 3737 ; 3738 3739 if (!itbl_entry[i].name) { 3740 NV_ERROR(bios->dev, 3741 "0x%04X: Init table command not found: " 3742 "0x%02X\n", offset, id); 3743 return -ENOENT; 3744 } 3745 3746 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset, 3747 itbl_entry[i].id, itbl_entry[i].name); 3748 3749 /* execute eventual command handler */ 3750 ret = (*itbl_entry[i].handler)(bios, offset, iexec); 3751 if (ret < 0) { 3752 NV_ERROR(bios->dev, "0x%04X: Failed parsing init " 3753 "table opcode: %s %d\n", offset, 3754 itbl_entry[i].name, ret); 3755 } 3756 3757 if (ret <= 0) 3758 break; 3759 3760 /* 3761 * Add the offset of the current command including all data 3762 * of that command. The offset will then be pointing on the 3763 * next op code. 3764 */ 3765 offset += ret; 3766 } 3767 3768 if (offset >= bios->length) 3769 NV_WARN(bios->dev, 3770 "Offset 0x%04X greater than known bios image length. " 3771 "Corrupt image?\n", offset); 3772 if (count >= MAX_TABLE_OPS) 3773 NV_WARN(bios->dev, 3774 "More than %d opcodes to a table is unlikely, " 3775 "is the bios image corrupt?\n", MAX_TABLE_OPS); 3776 3777 return 0; 3778} 3779 3780static void 3781parse_init_tables(struct nvbios *bios) 3782{ 3783 /* Loops and calls parse_init_table() for each present table. */ 3784 3785 int i = 0; 3786 uint16_t table; 3787 struct init_exec iexec = {true, false}; 3788 3789 if (bios->old_style_init) { 3790 if (bios->init_script_tbls_ptr) 3791 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec); 3792 if (bios->extra_init_script_tbl_ptr) 3793 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec); 3794 3795 return; 3796 } 3797 3798 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) { 3799 NV_INFO(bios->dev, 3800 "Parsing VBIOS init table %d at offset 0x%04X\n", 3801 i / 2, table); 3802 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table); 3803 3804 parse_init_table(bios, table, &iexec); 3805 i += 2; 3806 } 3807} 3808 3809static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk) 3810{ 3811 int compare_record_len, i = 0; 3812 uint16_t compareclk, scriptptr = 0; 3813 3814 if (bios->major_version < 5) /* pre BIT */ 3815 compare_record_len = 3; 3816 else 3817 compare_record_len = 4; 3818 3819 do { 3820 compareclk = ROM16(bios->data[clktable + compare_record_len * i]); 3821 if (pxclk >= compareclk * 10) { 3822 if (bios->major_version < 5) { 3823 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i]; 3824 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]); 3825 } else 3826 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]); 3827 break; 3828 } 3829 i++; 3830 } while (compareclk); 3831 3832 return scriptptr; 3833} 3834 3835static void 3836run_digital_op_script(struct drm_device *dev, uint16_t scriptptr, 3837 struct dcb_entry *dcbent, int head, bool dl) 3838{ 3839 struct drm_nouveau_private *dev_priv = dev->dev_private; 3840 struct nvbios *bios = &dev_priv->vbios; 3841 struct init_exec iexec = {true, false}; 3842 3843 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n", 3844 scriptptr); 3845 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44, 3846 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA); 3847 /* note: if dcb entries have been merged, index may be misleading */ 3848 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index); 3849 parse_init_table(bios, scriptptr, &iexec); 3850 3851 nv04_dfp_bind_head(dev, dcbent, head, dl); 3852} 3853 3854static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script) 3855{ 3856 struct drm_nouveau_private *dev_priv = dev->dev_private; 3857 struct nvbios *bios = &dev_priv->vbios; 3858 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0); 3859 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]); 3860 3861 if (!bios->fp.xlated_entry || !sub || !scriptofs) 3862 return -EINVAL; 3863 3864 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link); 3865 3866 if (script == LVDS_PANEL_OFF) { 3867 /* off-on delay in ms */ 3868 msleep(ROM16(bios->data[bios->fp.xlated_entry + 7])); 3869 } 3870#ifdef __powerpc__ 3871 /* Powerbook specific quirks */ 3872 if ((dev->pci_device & 0xffff) == 0x0179 || 3873 (dev->pci_device & 0xffff) == 0x0189 || 3874 (dev->pci_device & 0xffff) == 0x0329) { 3875 if (script == LVDS_RESET) { 3876 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72); 3877 3878 } else if (script == LVDS_PANEL_ON) { 3879 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL, 3880 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL) 3881 | (1 << 31)); 3882 bios_wr32(bios, NV_PCRTC_GPIO_EXT, 3883 bios_rd32(bios, NV_PCRTC_GPIO_EXT) | 1); 3884 3885 } else if (script == LVDS_PANEL_OFF) { 3886 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL, 3887 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL) 3888 & ~(1 << 31)); 3889 bios_wr32(bios, NV_PCRTC_GPIO_EXT, 3890 bios_rd32(bios, NV_PCRTC_GPIO_EXT) & ~3); 3891 } 3892 } 3893#endif 3894 3895 return 0; 3896} 3897 3898static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk) 3899{ 3900 /* 3901 * The BIT LVDS table's header has the information to setup the 3902 * necessary registers. Following the standard 4 byte header are: 3903 * A bitmask byte and a dual-link transition pxclk value for use in 3904 * selecting the init script when not using straps; 4 script pointers 3905 * for panel power, selected by output and on/off; and 8 table pointers 3906 * for panel init, the needed one determined by output, and bits in the 3907 * conf byte. These tables are similar to the TMDS tables, consisting 3908 * of a list of pxclks and script pointers. 3909 */ 3910 struct drm_nouveau_private *dev_priv = dev->dev_private; 3911 struct nvbios *bios = &dev_priv->vbios; 3912 unsigned int outputset = (dcbent->or == 4) ? 1 : 0; 3913 uint16_t scriptptr = 0, clktable; 3914 3915 /* 3916 * For now we assume version 3.0 table - g80 support will need some 3917 * changes 3918 */ 3919 3920 switch (script) { 3921 case LVDS_INIT: 3922 return -ENOSYS; 3923 case LVDS_BACKLIGHT_ON: 3924 case LVDS_PANEL_ON: 3925 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]); 3926 break; 3927 case LVDS_BACKLIGHT_OFF: 3928 case LVDS_PANEL_OFF: 3929 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]); 3930 break; 3931 case LVDS_RESET: 3932 clktable = bios->fp.lvdsmanufacturerpointer + 15; 3933 if (dcbent->or == 4) 3934 clktable += 8; 3935 3936 if (dcbent->lvdsconf.use_straps_for_mode) { 3937 if (bios->fp.dual_link) 3938 clktable += 4; 3939 if (bios->fp.if_is_24bit) 3940 clktable += 2; 3941 } else { 3942 /* using EDID */ 3943 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1; 3944 3945 if (bios->fp.dual_link) { 3946 clktable += 4; 3947 cmpval_24bit <<= 1; 3948 } 3949 3950 if (bios->fp.strapless_is_24bit & cmpval_24bit) 3951 clktable += 2; 3952 } 3953 3954 clktable = ROM16(bios->data[clktable]); 3955 if (!clktable) { 3956 NV_ERROR(dev, "Pixel clock comparison table not found\n"); 3957 return -ENOENT; 3958 } 3959 scriptptr = clkcmptable(bios, clktable, pxclk); 3960 } 3961 3962 if (!scriptptr) { 3963 NV_ERROR(dev, "LVDS output init script not found\n"); 3964 return -ENOENT; 3965 } 3966 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link); 3967 3968 return 0; 3969} 3970 3971int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk) 3972{ 3973 /* 3974 * LVDS operations are multiplexed in an effort to present a single API 3975 * which works with two vastly differing underlying structures. 3976 * This acts as the demux 3977 */ 3978 3979 struct drm_nouveau_private *dev_priv = dev->dev_private; 3980 struct nvbios *bios = &dev_priv->vbios; 3981 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer]; 3982 uint32_t sel_clk_binding, sel_clk; 3983 int ret; 3984 3985 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver || 3986 (lvds_ver >= 0x30 && script == LVDS_INIT)) 3987 return 0; 3988 3989 if (!bios->fp.lvds_init_run) { 3990 bios->fp.lvds_init_run = true; 3991 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk); 3992 } 3993 3994 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change) 3995 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk); 3996 if (script == LVDS_RESET && bios->fp.power_off_for_reset) 3997 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk); 3998 3999 NV_TRACE(dev, "Calling LVDS script %d:\n", script); 4000 4001 /* don't let script change pll->head binding */ 4002 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000; 4003 4004 if (lvds_ver < 0x30) 4005 ret = call_lvds_manufacturer_script(dev, dcbent, head, script); 4006 else 4007 ret = run_lvds_table(dev, dcbent, head, script, pxclk); 4008 4009 bios->fp.last_script_invoc = (script << 1 | head); 4010 4011 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; 4012 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); 4013 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */ 4014 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0); 4015 4016 return ret; 4017} 4018 4019struct lvdstableheader { 4020 uint8_t lvds_ver, headerlen, recordlen; 4021}; 4022 4023static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth) 4024{ 4025 /* 4026 * BMP version (0xa) LVDS table has a simple header of version and 4027 * record length. The BIT LVDS table has the typical BIT table header: 4028 * version byte, header length byte, record length byte, and a byte for 4029 * the maximum number of records that can be held in the table. 4030 */ 4031 4032 uint8_t lvds_ver, headerlen, recordlen; 4033 4034 memset(lth, 0, sizeof(struct lvdstableheader)); 4035 4036 if (bios->fp.lvdsmanufacturerpointer == 0x0) { 4037 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n"); 4038 return -EINVAL; 4039 } 4040 4041 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer]; 4042 4043 switch (lvds_ver) { 4044 case 0x0a: /* pre NV40 */ 4045 headerlen = 2; 4046 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 4047 break; 4048 case 0x30: /* NV4x */ 4049 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 4050 if (headerlen < 0x1f) { 4051 NV_ERROR(dev, "LVDS table header not understood\n"); 4052 return -EINVAL; 4053 } 4054 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2]; 4055 break; 4056 case 0x40: /* G80/G90 */ 4057 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 4058 if (headerlen < 0x7) { 4059 NV_ERROR(dev, "LVDS table header not understood\n"); 4060 return -EINVAL; 4061 } 4062 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2]; 4063 break; 4064 default: 4065 NV_ERROR(dev, 4066 "LVDS table revision %d.%d not currently supported\n", 4067 lvds_ver >> 4, lvds_ver & 0xf); 4068 return -ENOSYS; 4069 } 4070 4071 lth->lvds_ver = lvds_ver; 4072 lth->headerlen = headerlen; 4073 lth->recordlen = recordlen; 4074 4075 return 0; 4076} 4077 4078static int 4079get_fp_strap(struct drm_device *dev, struct nvbios *bios) 4080{ 4081 struct drm_nouveau_private *dev_priv = dev->dev_private; 4082 4083 /* 4084 * The fp strap is normally dictated by the "User Strap" in 4085 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the 4086 * Internal_Flags struct at 0x48 is set, the user strap gets overriden 4087 * by the PCI subsystem ID during POST, but not before the previous user 4088 * strap has been committed to CR58 for CR57=0xf on head A, which may be 4089 * read and used instead 4090 */ 4091 4092 if (bios->major_version < 5 && bios->data[0x48] & 0x4) 4093 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf; 4094 4095 if (dev_priv->card_type >= NV_50) 4096 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf; 4097 else 4098 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf; 4099} 4100 4101static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios) 4102{ 4103 uint8_t *fptable; 4104 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex; 4105 int ret, ofs, fpstrapping; 4106 struct lvdstableheader lth; 4107 4108 if (bios->fp.fptablepointer == 0x0) { 4109 /* Apple cards don't have the fp table; the laptops use DDC */ 4110 /* The table is also missing on some x86 IGPs */ 4111#ifndef __powerpc__ 4112 NV_ERROR(dev, "Pointer to flat panel table invalid\n"); 4113#endif 4114 bios->digital_min_front_porch = 0x4b; 4115 return 0; 4116 } 4117 4118 fptable = &bios->data[bios->fp.fptablepointer]; 4119 fptable_ver = fptable[0]; 4120 4121 switch (fptable_ver) { 4122 /* 4123 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no 4124 * version field, and miss one of the spread spectrum/PWM bytes. 4125 * This could affect early GF2Go parts (not seen any appropriate ROMs 4126 * though). Here we assume that a version of 0x05 matches this case 4127 * (combining with a BMP version check would be better), as the 4128 * common case for the panel type field is 0x0005, and that is in 4129 * fact what we are reading the first byte of. 4130 */ 4131 case 0x05: /* some NV10, 11, 15, 16 */ 4132 recordlen = 42; 4133 ofs = -1; 4134 break; 4135 case 0x10: /* some NV15/16, and NV11+ */ 4136 recordlen = 44; 4137 ofs = 0; 4138 break; 4139 case 0x20: /* NV40+ */ 4140 headerlen = fptable[1]; 4141 recordlen = fptable[2]; 4142 fpentries = fptable[3]; 4143 /* 4144 * fptable[4] is the minimum 4145 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap 4146 */ 4147 bios->digital_min_front_porch = fptable[4]; 4148 ofs = -7; 4149 break; 4150 default: 4151 NV_ERROR(dev, 4152 "FP table revision %d.%d not currently supported\n", 4153 fptable_ver >> 4, fptable_ver & 0xf); 4154 return -ENOSYS; 4155 } 4156 4157 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */ 4158 return 0; 4159 4160 ret = parse_lvds_manufacturer_table_header(dev, bios, <h); 4161 if (ret) 4162 return ret; 4163 4164 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) { 4165 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer + 4166 lth.headerlen + 1; 4167 bios->fp.xlatwidth = lth.recordlen; 4168 } 4169 if (bios->fp.fpxlatetableptr == 0x0) { 4170 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n"); 4171 return -EINVAL; 4172 } 4173 4174 fpstrapping = get_fp_strap(dev, bios); 4175 4176 fpindex = bios->data[bios->fp.fpxlatetableptr + 4177 fpstrapping * bios->fp.xlatwidth]; 4178 4179 if (fpindex > fpentries) { 4180 NV_ERROR(dev, "Bad flat panel table index\n"); 4181 return -ENOENT; 4182 } 4183 4184 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */ 4185 if (lth.lvds_ver > 0x10) 4186 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf; 4187 4188 /* 4189 * If either the strap or xlated fpindex value are 0xf there is no 4190 * panel using a strap-derived bios mode present. this condition 4191 * includes, but is different from, the DDC panel indicator above 4192 */ 4193 if (fpstrapping == 0xf || fpindex == 0xf) 4194 return 0; 4195 4196 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen + 4197 recordlen * fpindex + ofs; 4198 4199 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n", 4200 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1, 4201 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1, 4202 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10); 4203 4204 return 0; 4205} 4206 4207bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode) 4208{ 4209 struct drm_nouveau_private *dev_priv = dev->dev_private; 4210 struct nvbios *bios = &dev_priv->vbios; 4211 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr]; 4212 4213 if (!mode) /* just checking whether we can produce a mode */ 4214 return bios->fp.mode_ptr; 4215 4216 memset(mode, 0, sizeof(struct drm_display_mode)); 4217 /* 4218 * For version 1.0 (version in byte 0): 4219 * bytes 1-2 are "panel type", including bits on whether Colour/mono, 4220 * single/dual link, and type (TFT etc.) 4221 * bytes 3-6 are bits per colour in RGBX 4222 */ 4223 mode->clock = ROM16(mode_entry[7]) * 10; 4224 /* bytes 9-10 is HActive */ 4225 mode->hdisplay = ROM16(mode_entry[11]) + 1; 4226 /* 4227 * bytes 13-14 is HValid Start 4228 * bytes 15-16 is HValid End 4229 */ 4230 mode->hsync_start = ROM16(mode_entry[17]) + 1; 4231 mode->hsync_end = ROM16(mode_entry[19]) + 1; 4232 mode->htotal = ROM16(mode_entry[21]) + 1; 4233 /* bytes 23-24, 27-30 similarly, but vertical */ 4234 mode->vdisplay = ROM16(mode_entry[25]) + 1; 4235 mode->vsync_start = ROM16(mode_entry[31]) + 1; 4236 mode->vsync_end = ROM16(mode_entry[33]) + 1; 4237 mode->vtotal = ROM16(mode_entry[35]) + 1; 4238 mode->flags |= (mode_entry[37] & 0x10) ? 4239 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4240 mode->flags |= (mode_entry[37] & 0x1) ? 4241 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4242 /* 4243 * bytes 38-39 relate to spread spectrum settings 4244 * bytes 40-43 are something to do with PWM 4245 */ 4246 4247 mode->status = MODE_OK; 4248 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; 4249 drm_mode_set_name(mode); 4250 return bios->fp.mode_ptr; 4251} 4252 4253int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit) 4254{ 4255 /* 4256 * The LVDS table header is (mostly) described in 4257 * parse_lvds_manufacturer_table_header(): the BIT header additionally 4258 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if 4259 * straps are not being used for the panel, this specifies the frequency 4260 * at which modes should be set up in the dual link style. 4261 * 4262 * Following the header, the BMP (ver 0xa) table has several records, 4263 * indexed by a separate xlat table, indexed in turn by the fp strap in 4264 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script 4265 * numbers for use by INIT_SUB which controlled panel init and power, 4266 * and finally a dword of ms to sleep between power off and on 4267 * operations. 4268 * 4269 * In the BIT versions, the table following the header serves as an 4270 * integrated config and xlat table: the records in the table are 4271 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has 4272 * two bytes - the first as a config byte, the second for indexing the 4273 * fp mode table pointed to by the BIT 'D' table 4274 * 4275 * DDC is not used until after card init, so selecting the correct table 4276 * entry and setting the dual link flag for EDID equipped panels, 4277 * requiring tests against the native-mode pixel clock, cannot be done 4278 * until later, when this function should be called with non-zero pxclk 4279 */ 4280 struct drm_nouveau_private *dev_priv = dev->dev_private; 4281 struct nvbios *bios = &dev_priv->vbios; 4282 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0; 4283 struct lvdstableheader lth; 4284 uint16_t lvdsofs; 4285 int ret, chip_version = bios->chip_version; 4286 4287 ret = parse_lvds_manufacturer_table_header(dev, bios, <h); 4288 if (ret) 4289 return ret; 4290 4291 switch (lth.lvds_ver) { 4292 case 0x0a: /* pre NV40 */ 4293 lvdsmanufacturerindex = bios->data[ 4294 bios->fp.fpxlatemanufacturertableptr + 4295 fpstrapping]; 4296 4297 /* we're done if this isn't the EDID panel case */ 4298 if (!pxclk) 4299 break; 4300 4301 if (chip_version < 0x25) { 4302 /* nv17 behaviour 4303 * 4304 * It seems the old style lvds script pointer is reused 4305 * to select 18/24 bit colour depth for EDID panels. 4306 */ 4307 lvdsmanufacturerindex = 4308 (bios->legacy.lvds_single_a_script_ptr & 1) ? 4309 2 : 0; 4310 if (pxclk >= bios->fp.duallink_transition_clk) 4311 lvdsmanufacturerindex++; 4312 } else if (chip_version < 0x30) { 4313 /* nv28 behaviour (off-chip encoder) 4314 * 4315 * nv28 does a complex dance of first using byte 121 of 4316 * the EDID to choose the lvdsmanufacturerindex, then 4317 * later attempting to match the EDID manufacturer and 4318 * product IDs in a table (signature 'pidt' (panel id 4319 * table?)), setting an lvdsmanufacturerindex of 0 and 4320 * an fp strap of the match index (or 0xf if none) 4321 */ 4322 lvdsmanufacturerindex = 0; 4323 } else { 4324 /* nv31, nv34 behaviour */ 4325 lvdsmanufacturerindex = 0; 4326 if (pxclk >= bios->fp.duallink_transition_clk) 4327 lvdsmanufacturerindex = 2; 4328 if (pxclk >= 140000) 4329 lvdsmanufacturerindex = 3; 4330 } 4331 4332 /* 4333 * nvidia set the high nibble of (cr57=f, cr58) to 4334 * lvdsmanufacturerindex in this case; we don't 4335 */ 4336 break; 4337 case 0x30: /* NV4x */ 4338 case 0x40: /* G80/G90 */ 4339 lvdsmanufacturerindex = fpstrapping; 4340 break; 4341 default: 4342 NV_ERROR(dev, "LVDS table revision not currently supported\n"); 4343 return -ENOSYS; 4344 } 4345 4346 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex; 4347 switch (lth.lvds_ver) { 4348 case 0x0a: 4349 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1; 4350 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2; 4351 bios->fp.dual_link = bios->data[lvdsofs] & 4; 4352 bios->fp.link_c_increment = bios->data[lvdsofs] & 8; 4353 *if_is_24bit = bios->data[lvdsofs] & 16; 4354 break; 4355 case 0x30: 4356 case 0x40: 4357 /* 4358 * No sign of the "power off for reset" or "reset for panel 4359 * on" bits, but it's safer to assume we should 4360 */ 4361 bios->fp.power_off_for_reset = true; 4362 bios->fp.reset_after_pclk_change = true; 4363 4364 /* 4365 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is 4366 * over-written, and if_is_24bit isn't used 4367 */ 4368 bios->fp.dual_link = bios->data[lvdsofs] & 1; 4369 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2; 4370 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4]; 4371 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10; 4372 break; 4373 } 4374 4375 /* Dell Latitude D620 reports a too-high value for the dual-link 4376 * transition freq, causing us to program the panel incorrectly. 4377 * 4378 * It doesn't appear the VBIOS actually uses its transition freq 4379 * (90000kHz), instead it uses the "Number of LVDS channels" field 4380 * out of the panel ID structure (http://www.spwg.org/). 4381 * 4382 * For the moment, a quirk will do :) 4383 */ 4384 if ((dev->pdev->device == 0x01d7) && 4385 (dev->pdev->subsystem_vendor == 0x1028) && 4386 (dev->pdev->subsystem_device == 0x01c2)) { 4387 bios->fp.duallink_transition_clk = 80000; 4388 } 4389 4390 /* set dual_link flag for EDID case */ 4391 if (pxclk && (chip_version < 0x25 || chip_version > 0x28)) 4392 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk); 4393 4394 *dl = bios->fp.dual_link; 4395 4396 return 0; 4397} 4398 4399static uint8_t * 4400bios_output_config_match(struct drm_device *dev, struct dcb_entry *dcbent, 4401 uint16_t record, int record_len, int record_nr, 4402 bool match_link) 4403{ 4404 struct drm_nouveau_private *dev_priv = dev->dev_private; 4405 struct nvbios *bios = &dev_priv->vbios; 4406 uint32_t entry; 4407 uint16_t table; 4408 int i, v; 4409 4410 switch (dcbent->type) { 4411 case OUTPUT_TMDS: 4412 case OUTPUT_LVDS: 4413 case OUTPUT_DP: 4414 break; 4415 default: 4416 match_link = false; 4417 break; 4418 } 4419 4420 for (i = 0; i < record_nr; i++, record += record_len) { 4421 table = ROM16(bios->data[record]); 4422 if (!table) 4423 continue; 4424 entry = ROM32(bios->data[table]); 4425 4426 if (match_link) { 4427 v = (entry & 0x00c00000) >> 22; 4428 if (!(v & dcbent->sorconf.link)) 4429 continue; 4430 } 4431 4432 v = (entry & 0x000f0000) >> 16; 4433 if (!(v & dcbent->or)) 4434 continue; 4435 4436 v = (entry & 0x000000f0) >> 4; 4437 if (v != dcbent->location) 4438 continue; 4439 4440 v = (entry & 0x0000000f); 4441 if (v != dcbent->type) 4442 continue; 4443 4444 return &bios->data[table]; 4445 } 4446 4447 return NULL; 4448} 4449 4450void * 4451nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent, 4452 int *length) 4453{ 4454 struct drm_nouveau_private *dev_priv = dev->dev_private; 4455 struct nvbios *bios = &dev_priv->vbios; 4456 uint8_t *table; 4457 4458 if (!bios->display.dp_table_ptr) { 4459 NV_ERROR(dev, "No pointer to DisplayPort table\n"); 4460 return NULL; 4461 } 4462 table = &bios->data[bios->display.dp_table_ptr]; 4463 4464 if (table[0] != 0x20 && table[0] != 0x21) { 4465 NV_ERROR(dev, "DisplayPort table version 0x%02x unknown\n", 4466 table[0]); 4467 return NULL; 4468 } 4469 4470 *length = table[4]; 4471 return bios_output_config_match(dev, dcbent, 4472 bios->display.dp_table_ptr + table[1], 4473 table[2], table[3], table[0] >= 0x21); 4474} 4475 4476int 4477nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent, 4478 uint32_t sub, int pxclk) 4479{ 4480 /* 4481 * The display script table is located by the BIT 'U' table. 4482 * 4483 * It contains an array of pointers to various tables describing 4484 * a particular output type. The first 32-bits of the output 4485 * tables contains similar information to a DCB entry, and is 4486 * used to decide whether that particular table is suitable for 4487 * the output you want to access. 4488 * 4489 * The "record header length" field here seems to indicate the 4490 * offset of the first configuration entry in the output tables. 4491 * This is 10 on most cards I've seen, but 12 has been witnessed 4492 * on DP cards, and there's another script pointer within the 4493 * header. 4494 * 4495 * offset + 0 ( 8 bits): version 4496 * offset + 1 ( 8 bits): header length 4497 * offset + 2 ( 8 bits): record length 4498 * offset + 3 ( 8 bits): number of records 4499 * offset + 4 ( 8 bits): record header length 4500 * offset + 5 (16 bits): pointer to first output script table 4501 */ 4502 4503 struct drm_nouveau_private *dev_priv = dev->dev_private; 4504 struct nvbios *bios = &dev_priv->vbios; 4505 uint8_t *table = &bios->data[bios->display.script_table_ptr]; 4506 uint8_t *otable = NULL; 4507 uint16_t script; 4508 int i = 0; 4509 4510 if (!bios->display.script_table_ptr) { 4511 NV_ERROR(dev, "No pointer to output script table\n"); 4512 return 1; 4513 } 4514 4515 /* 4516 * Nothing useful has been in any of the pre-2.0 tables I've seen, 4517 * so until they are, we really don't need to care. 4518 */ 4519 if (table[0] < 0x20) 4520 return 1; 4521 4522 if (table[0] != 0x20 && table[0] != 0x21) { 4523 NV_ERROR(dev, "Output script table version 0x%02x unknown\n", 4524 table[0]); 4525 return 1; 4526 } 4527 4528 /* 4529 * The output script tables describing a particular output type 4530 * look as follows: 4531 * 4532 * offset + 0 (32 bits): output this table matches (hash of DCB) 4533 * offset + 4 ( 8 bits): unknown 4534 * offset + 5 ( 8 bits): number of configurations 4535 * offset + 6 (16 bits): pointer to some script 4536 * offset + 8 (16 bits): pointer to some script 4537 * 4538 * headerlen == 10 4539 * offset + 10 : configuration 0 4540 * 4541 * headerlen == 12 4542 * offset + 10 : pointer to some script 4543 * offset + 12 : configuration 0 4544 * 4545 * Each config entry is as follows: 4546 * 4547 * offset + 0 (16 bits): unknown, assumed to be a match value 4548 * offset + 2 (16 bits): pointer to script table (clock set?) 4549 * offset + 4 (16 bits): pointer to script table (reset?) 4550 * 4551 * There doesn't appear to be a count value to say how many 4552 * entries exist in each script table, instead, a 0 value in 4553 * the first 16-bit word seems to indicate both the end of the 4554 * list and the default entry. The second 16-bit word in the 4555 * script tables is a pointer to the script to execute. 4556 */ 4557 4558 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n", 4559 dcbent->type, dcbent->location, dcbent->or); 4560 otable = bios_output_config_match(dev, dcbent, table[1] + 4561 bios->display.script_table_ptr, 4562 table[2], table[3], table[0] >= 0x21); 4563 if (!otable) { 4564 NV_DEBUG_KMS(dev, "failed to match any output table\n"); 4565 return 1; 4566 } 4567 4568 if (pxclk < -2 || pxclk > 0) { 4569 /* Try to find matching script table entry */ 4570 for (i = 0; i < otable[5]; i++) { 4571 if (ROM16(otable[table[4] + i*6]) == sub) 4572 break; 4573 } 4574 4575 if (i == otable[5]) { 4576 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, " 4577 "using first\n", 4578 sub, dcbent->type, dcbent->or); 4579 i = 0; 4580 } 4581 } 4582 4583 if (pxclk == 0) { 4584 script = ROM16(otable[6]); 4585 if (!script) { 4586 NV_DEBUG_KMS(dev, "output script 0 not found\n"); 4587 return 1; 4588 } 4589 4590 NV_TRACE(dev, "0x%04X: parsing output script 0\n", script); 4591 nouveau_bios_run_init_table(dev, script, dcbent); 4592 } else 4593 if (pxclk == -1) { 4594 script = ROM16(otable[8]); 4595 if (!script) { 4596 NV_DEBUG_KMS(dev, "output script 1 not found\n"); 4597 return 1; 4598 } 4599 4600 NV_TRACE(dev, "0x%04X: parsing output script 1\n", script); 4601 nouveau_bios_run_init_table(dev, script, dcbent); 4602 } else 4603 if (pxclk == -2) { 4604 if (table[4] >= 12) 4605 script = ROM16(otable[10]); 4606 else 4607 script = 0; 4608 if (!script) { 4609 NV_DEBUG_KMS(dev, "output script 2 not found\n"); 4610 return 1; 4611 } 4612 4613 NV_TRACE(dev, "0x%04X: parsing output script 2\n", script); 4614 nouveau_bios_run_init_table(dev, script, dcbent); 4615 } else 4616 if (pxclk > 0) { 4617 script = ROM16(otable[table[4] + i*6 + 2]); 4618 if (script) 4619 script = clkcmptable(bios, script, pxclk); 4620 if (!script) { 4621 NV_DEBUG_KMS(dev, "clock script 0 not found\n"); 4622 return 1; 4623 } 4624 4625 NV_TRACE(dev, "0x%04X: parsing clock script 0\n", script); 4626 nouveau_bios_run_init_table(dev, script, dcbent); 4627 } else 4628 if (pxclk < 0) { 4629 script = ROM16(otable[table[4] + i*6 + 4]); 4630 if (script) 4631 script = clkcmptable(bios, script, -pxclk); 4632 if (!script) { 4633 NV_DEBUG_KMS(dev, "clock script 1 not found\n"); 4634 return 1; 4635 } 4636 4637 NV_TRACE(dev, "0x%04X: parsing clock script 1\n", script); 4638 nouveau_bios_run_init_table(dev, script, dcbent); 4639 } 4640 4641 return 0; 4642} 4643 4644 4645int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk) 4646{ 4647 /* 4648 * the pxclk parameter is in kHz 4649 * 4650 * This runs the TMDS regs setting code found on BIT bios cards 4651 * 4652 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and 4653 * ffs(or) == 3, use the second. 4654 */ 4655 4656 struct drm_nouveau_private *dev_priv = dev->dev_private; 4657 struct nvbios *bios = &dev_priv->vbios; 4658 int cv = bios->chip_version; 4659 uint16_t clktable = 0, scriptptr; 4660 uint32_t sel_clk_binding, sel_clk; 4661 4662 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */ 4663 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 && 4664 dcbent->location != DCB_LOC_ON_CHIP) 4665 return 0; 4666 4667 switch (ffs(dcbent->or)) { 4668 case 1: 4669 clktable = bios->tmds.output0_script_ptr; 4670 break; 4671 case 2: 4672 case 3: 4673 clktable = bios->tmds.output1_script_ptr; 4674 break; 4675 } 4676 4677 if (!clktable) { 4678 NV_ERROR(dev, "Pixel clock comparison table not found\n"); 4679 return -EINVAL; 4680 } 4681 4682 scriptptr = clkcmptable(bios, clktable, pxclk); 4683 4684 if (!scriptptr) { 4685 NV_ERROR(dev, "TMDS output init script not found\n"); 4686 return -ENOENT; 4687 } 4688 4689 /* don't let script change pll->head binding */ 4690 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000; 4691 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000); 4692 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; 4693 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); 4694 4695 return 0; 4696} 4697 4698int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim) 4699{ 4700 /* 4701 * PLL limits table 4702 * 4703 * Version 0x10: NV30, NV31 4704 * One byte header (version), one record of 24 bytes 4705 * Version 0x11: NV36 - Not implemented 4706 * Seems to have same record style as 0x10, but 3 records rather than 1 4707 * Version 0x20: Found on Geforce 6 cards 4708 * Trivial 4 byte BIT header. 31 (0x1f) byte record length 4709 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards 4710 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record 4711 * length in general, some (integrated) have an extra configuration byte 4712 * Version 0x30: Found on Geforce 8, separates the register mapping 4713 * from the limits tables. 4714 */ 4715 4716 struct drm_nouveau_private *dev_priv = dev->dev_private; 4717 struct nvbios *bios = &dev_priv->vbios; 4718 int cv = bios->chip_version, pllindex = 0; 4719 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0; 4720 uint32_t crystal_strap_mask, crystal_straps; 4721 4722 if (!bios->pll_limit_tbl_ptr) { 4723 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 || 4724 cv >= 0x40) { 4725 NV_ERROR(dev, "Pointer to PLL limits table invalid\n"); 4726 return -EINVAL; 4727 } 4728 } else 4729 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr]; 4730 4731 crystal_strap_mask = 1 << 6; 4732 /* open coded dev->twoHeads test */ 4733 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20) 4734 crystal_strap_mask |= 1 << 22; 4735 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) & 4736 crystal_strap_mask; 4737 4738 switch (pll_lim_ver) { 4739 /* 4740 * We use version 0 to indicate a pre limit table bios (single stage 4741 * pll) and load the hard coded limits instead. 4742 */ 4743 case 0: 4744 break; 4745 case 0x10: 4746 case 0x11: 4747 /* 4748 * Strictly v0x11 has 3 entries, but the last two don't seem 4749 * to get used. 4750 */ 4751 headerlen = 1; 4752 recordlen = 0x18; 4753 entries = 1; 4754 pllindex = 0; 4755 break; 4756 case 0x20: 4757 case 0x21: 4758 case 0x30: 4759 case 0x40: 4760 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1]; 4761 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2]; 4762 entries = bios->data[bios->pll_limit_tbl_ptr + 3]; 4763 break; 4764 default: 4765 NV_ERROR(dev, "PLL limits table revision 0x%X not currently " 4766 "supported\n", pll_lim_ver); 4767 return -ENOSYS; 4768 } 4769 4770 /* initialize all members to zero */ 4771 memset(pll_lim, 0, sizeof(struct pll_lims)); 4772 4773 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) { 4774 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex]; 4775 4776 pll_lim->vco1.minfreq = ROM32(pll_rec[0]); 4777 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]); 4778 pll_lim->vco2.minfreq = ROM32(pll_rec[8]); 4779 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]); 4780 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]); 4781 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]); 4782 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX; 4783 4784 /* these values taken from nv30/31/36 */ 4785 pll_lim->vco1.min_n = 0x1; 4786 if (cv == 0x36) 4787 pll_lim->vco1.min_n = 0x5; 4788 pll_lim->vco1.max_n = 0xff; 4789 pll_lim->vco1.min_m = 0x1; 4790 pll_lim->vco1.max_m = 0xd; 4791 pll_lim->vco2.min_n = 0x4; 4792 /* 4793 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this 4794 * table version (apart from nv35)), N2 is compared to 4795 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and 4796 * save a comparison 4797 */ 4798 pll_lim->vco2.max_n = 0x28; 4799 if (cv == 0x30 || cv == 0x35) 4800 /* only 5 bits available for N2 on nv30/35 */ 4801 pll_lim->vco2.max_n = 0x1f; 4802 pll_lim->vco2.min_m = 0x1; 4803 pll_lim->vco2.max_m = 0x4; 4804 pll_lim->max_log2p = 0x7; 4805 pll_lim->max_usable_log2p = 0x6; 4806 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) { 4807 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen; 4808 uint32_t reg = 0; /* default match */ 4809 uint8_t *pll_rec; 4810 int i; 4811 4812 /* 4813 * First entry is default match, if nothing better. warn if 4814 * reg field nonzero 4815 */ 4816 if (ROM32(bios->data[plloffs])) 4817 NV_WARN(dev, "Default PLL limit entry has non-zero " 4818 "register field\n"); 4819 4820 if (limit_match > MAX_PLL_TYPES) 4821 /* we've been passed a reg as the match */ 4822 reg = limit_match; 4823 else /* limit match is a pll type */ 4824 for (i = 1; i < entries && !reg; i++) { 4825 uint32_t cmpreg = ROM32(bios->data[plloffs + recordlen * i]); 4826 4827 if (limit_match == NVPLL && 4828 (cmpreg == NV_PRAMDAC_NVPLL_COEFF || cmpreg == 0x4000)) 4829 reg = cmpreg; 4830 if (limit_match == MPLL && 4831 (cmpreg == NV_PRAMDAC_MPLL_COEFF || cmpreg == 0x4020)) 4832 reg = cmpreg; 4833 if (limit_match == VPLL1 && 4834 (cmpreg == NV_PRAMDAC_VPLL_COEFF || cmpreg == 0x4010)) 4835 reg = cmpreg; 4836 if (limit_match == VPLL2 && 4837 (cmpreg == NV_RAMDAC_VPLL2 || cmpreg == 0x4018)) 4838 reg = cmpreg; 4839 } 4840 4841 for (i = 1; i < entries; i++) 4842 if (ROM32(bios->data[plloffs + recordlen * i]) == reg) { 4843 pllindex = i; 4844 break; 4845 } 4846 4847 pll_rec = &bios->data[plloffs + recordlen * pllindex]; 4848 4849 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n", 4850 pllindex ? reg : 0); 4851 4852 /* 4853 * Frequencies are stored in tables in MHz, kHz are more 4854 * useful, so we convert. 4855 */ 4856 4857 /* What output frequencies can each VCO generate? */ 4858 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000; 4859 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000; 4860 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000; 4861 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000; 4862 4863 /* What input frequencies they accept (past the m-divider)? */ 4864 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000; 4865 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000; 4866 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000; 4867 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000; 4868 4869 /* What values are accepted as multiplier and divider? */ 4870 pll_lim->vco1.min_n = pll_rec[20]; 4871 pll_lim->vco1.max_n = pll_rec[21]; 4872 pll_lim->vco1.min_m = pll_rec[22]; 4873 pll_lim->vco1.max_m = pll_rec[23]; 4874 pll_lim->vco2.min_n = pll_rec[24]; 4875 pll_lim->vco2.max_n = pll_rec[25]; 4876 pll_lim->vco2.min_m = pll_rec[26]; 4877 pll_lim->vco2.max_m = pll_rec[27]; 4878 4879 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29]; 4880 if (pll_lim->max_log2p > 0x7) 4881 /* pll decoding in nv_hw.c assumes never > 7 */ 4882 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n", 4883 pll_lim->max_log2p); 4884 if (cv < 0x60) 4885 pll_lim->max_usable_log2p = 0x6; 4886 pll_lim->log2p_bias = pll_rec[30]; 4887 4888 if (recordlen > 0x22) 4889 pll_lim->refclk = ROM32(pll_rec[31]); 4890 4891 if (recordlen > 0x23 && pll_rec[35]) 4892 NV_WARN(dev, 4893 "Bits set in PLL configuration byte (%x)\n", 4894 pll_rec[35]); 4895 4896 /* C51 special not seen elsewhere */ 4897 if (cv == 0x51 && !pll_lim->refclk) { 4898 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK); 4899 4900 if (((limit_match == NV_PRAMDAC_VPLL_COEFF || limit_match == VPLL1) && sel_clk & 0x20) || 4901 ((limit_match == NV_RAMDAC_VPLL2 || limit_match == VPLL2) && sel_clk & 0x80)) { 4902 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3) 4903 pll_lim->refclk = 200000; 4904 else 4905 pll_lim->refclk = 25000; 4906 } 4907 } 4908 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */ 4909 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen]; 4910 uint8_t *record = NULL; 4911 int i; 4912 4913 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n", 4914 limit_match); 4915 4916 for (i = 0; i < entries; i++, entry += recordlen) { 4917 if (ROM32(entry[3]) == limit_match) { 4918 record = &bios->data[ROM16(entry[1])]; 4919 break; 4920 } 4921 } 4922 4923 if (!record) { 4924 NV_ERROR(dev, "Register 0x%08x not found in PLL " 4925 "limits table", limit_match); 4926 return -ENOENT; 4927 } 4928 4929 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000; 4930 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000; 4931 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000; 4932 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000; 4933 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000; 4934 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000; 4935 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000; 4936 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000; 4937 pll_lim->vco1.min_n = record[16]; 4938 pll_lim->vco1.max_n = record[17]; 4939 pll_lim->vco1.min_m = record[18]; 4940 pll_lim->vco1.max_m = record[19]; 4941 pll_lim->vco2.min_n = record[20]; 4942 pll_lim->vco2.max_n = record[21]; 4943 pll_lim->vco2.min_m = record[22]; 4944 pll_lim->vco2.max_m = record[23]; 4945 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25]; 4946 pll_lim->log2p_bias = record[27]; 4947 pll_lim->refclk = ROM32(record[28]); 4948 } else if (pll_lim_ver) { /* ver 0x40 */ 4949 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen]; 4950 uint8_t *record = NULL; 4951 int i; 4952 4953 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n", 4954 limit_match); 4955 4956 for (i = 0; i < entries; i++, entry += recordlen) { 4957 if (ROM32(entry[3]) == limit_match) { 4958 record = &bios->data[ROM16(entry[1])]; 4959 break; 4960 } 4961 } 4962 4963 if (!record) { 4964 NV_ERROR(dev, "Register 0x%08x not found in PLL " 4965 "limits table", limit_match); 4966 return -ENOENT; 4967 } 4968 4969 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000; 4970 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000; 4971 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000; 4972 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000; 4973 pll_lim->vco1.min_m = record[8]; 4974 pll_lim->vco1.max_m = record[9]; 4975 pll_lim->vco1.min_n = record[10]; 4976 pll_lim->vco1.max_n = record[11]; 4977 pll_lim->min_p = record[12]; 4978 pll_lim->max_p = record[13]; 4979 /* where did this go to?? */ 4980 if ((entry[0] & 0xf0) == 0x80) 4981 pll_lim->refclk = 27000; 4982 else 4983 pll_lim->refclk = 100000; 4984 } 4985 4986 /* 4987 * By now any valid limit table ought to have set a max frequency for 4988 * vco1, so if it's zero it's either a pre limit table bios, or one 4989 * with an empty limit table (seen on nv18) 4990 */ 4991 if (!pll_lim->vco1.maxfreq) { 4992 pll_lim->vco1.minfreq = bios->fminvco; 4993 pll_lim->vco1.maxfreq = bios->fmaxvco; 4994 pll_lim->vco1.min_inputfreq = 0; 4995 pll_lim->vco1.max_inputfreq = INT_MAX; 4996 pll_lim->vco1.min_n = 0x1; 4997 pll_lim->vco1.max_n = 0xff; 4998 pll_lim->vco1.min_m = 0x1; 4999 if (crystal_straps == 0) { 5000 /* nv05 does this, nv11 doesn't, nv10 unknown */ 5001 if (cv < 0x11) 5002 pll_lim->vco1.min_m = 0x7; 5003 pll_lim->vco1.max_m = 0xd; 5004 } else { 5005 if (cv < 0x11) 5006 pll_lim->vco1.min_m = 0x8; 5007 pll_lim->vco1.max_m = 0xe; 5008 } 5009 if (cv < 0x17 || cv == 0x1a || cv == 0x20) 5010 pll_lim->max_log2p = 4; 5011 else 5012 pll_lim->max_log2p = 5; 5013 pll_lim->max_usable_log2p = pll_lim->max_log2p; 5014 } 5015 5016 if (!pll_lim->refclk) 5017 switch (crystal_straps) { 5018 case 0: 5019 pll_lim->refclk = 13500; 5020 break; 5021 case (1 << 6): 5022 pll_lim->refclk = 14318; 5023 break; 5024 case (1 << 22): 5025 pll_lim->refclk = 27000; 5026 break; 5027 case (1 << 22 | 1 << 6): 5028 pll_lim->refclk = 25000; 5029 break; 5030 } 5031 5032 NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq); 5033 NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq); 5034 NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq); 5035 NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq); 5036 NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n); 5037 NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n); 5038 NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m); 5039 NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m); 5040 if (pll_lim->vco2.maxfreq) { 5041 NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq); 5042 NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq); 5043 NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq); 5044 NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq); 5045 NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n); 5046 NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n); 5047 NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m); 5048 NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m); 5049 } 5050 if (!pll_lim->max_p) { 5051 NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p); 5052 NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias); 5053 } else { 5054 NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p); 5055 NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p); 5056 } 5057 NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk); 5058 5059 return 0; 5060} 5061 5062static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset) 5063{ 5064 /* 5065 * offset + 0 (8 bits): Micro version 5066 * offset + 1 (8 bits): Minor version 5067 * offset + 2 (8 bits): Chip version 5068 * offset + 3 (8 bits): Major version 5069 */ 5070 5071 bios->major_version = bios->data[offset + 3]; 5072 bios->chip_version = bios->data[offset + 2]; 5073 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n", 5074 bios->data[offset + 3], bios->data[offset + 2], 5075 bios->data[offset + 1], bios->data[offset]); 5076} 5077 5078static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset) 5079{ 5080 /* 5081 * Parses the init table segment for pointers used in script execution. 5082 * 5083 * offset + 0 (16 bits): init script tables pointer 5084 * offset + 2 (16 bits): macro index table pointer 5085 * offset + 4 (16 bits): macro table pointer 5086 * offset + 6 (16 bits): condition table pointer 5087 * offset + 8 (16 bits): io condition table pointer 5088 * offset + 10 (16 bits): io flag condition table pointer 5089 * offset + 12 (16 bits): init function table pointer 5090 */ 5091 5092 bios->init_script_tbls_ptr = ROM16(bios->data[offset]); 5093 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]); 5094 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]); 5095 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]); 5096 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]); 5097 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]); 5098 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]); 5099} 5100 5101static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5102{ 5103 /* 5104 * Parses the load detect values for g80 cards. 5105 * 5106 * offset + 0 (16 bits): loadval table pointer 5107 */ 5108 5109 uint16_t load_table_ptr; 5110 uint8_t version, headerlen, entrylen, num_entries; 5111 5112 if (bitentry->length != 3) { 5113 NV_ERROR(dev, "Do not understand BIT A table\n"); 5114 return -EINVAL; 5115 } 5116 5117 load_table_ptr = ROM16(bios->data[bitentry->offset]); 5118 5119 if (load_table_ptr == 0x0) { 5120 NV_ERROR(dev, "Pointer to BIT loadval table invalid\n"); 5121 return -EINVAL; 5122 } 5123 5124 version = bios->data[load_table_ptr]; 5125 5126 if (version != 0x10) { 5127 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n", 5128 version >> 4, version & 0xF); 5129 return -ENOSYS; 5130 } 5131 5132 headerlen = bios->data[load_table_ptr + 1]; 5133 entrylen = bios->data[load_table_ptr + 2]; 5134 num_entries = bios->data[load_table_ptr + 3]; 5135 5136 if (headerlen != 4 || entrylen != 4 || num_entries != 2) { 5137 NV_ERROR(dev, "Do not understand BIT loadval table\n"); 5138 return -EINVAL; 5139 } 5140 5141 /* First entry is normal dac, 2nd tv-out perhaps? */ 5142 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff; 5143 5144 return 0; 5145} 5146 5147static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5148{ 5149 /* 5150 * offset + 8 (16 bits): PLL limits table pointer 5151 * 5152 * There's more in here, but that's unknown. 5153 */ 5154 5155 if (bitentry->length < 10) { 5156 NV_ERROR(dev, "Do not understand BIT C table\n"); 5157 return -EINVAL; 5158 } 5159 5160 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]); 5161 5162 return 0; 5163} 5164 5165static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5166{ 5167 /* 5168 * Parses the flat panel table segment that the bit entry points to. 5169 * Starting at bitentry->offset: 5170 * 5171 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte 5172 * records beginning with a freq. 5173 * offset + 2 (16 bits): mode table pointer 5174 */ 5175 5176 if (bitentry->length != 4) { 5177 NV_ERROR(dev, "Do not understand BIT display table\n"); 5178 return -EINVAL; 5179 } 5180 5181 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]); 5182 5183 return 0; 5184} 5185 5186static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5187{ 5188 /* 5189 * Parses the init table segment that the bit entry points to. 5190 * 5191 * See parse_script_table_pointers for layout 5192 */ 5193 5194 if (bitentry->length < 14) { 5195 NV_ERROR(dev, "Do not understand init table\n"); 5196 return -EINVAL; 5197 } 5198 5199 parse_script_table_pointers(bios, bitentry->offset); 5200 5201 if (bitentry->length >= 16) 5202 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]); 5203 if (bitentry->length >= 18) 5204 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]); 5205 5206 return 0; 5207} 5208 5209static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5210{ 5211 /* 5212 * BIT 'i' (info?) table 5213 * 5214 * offset + 0 (32 bits): BIOS version dword (as in B table) 5215 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?) 5216 * offset + 13 (16 bits): pointer to table containing DAC load 5217 * detection comparison values 5218 * 5219 * There's other things in the table, purpose unknown 5220 */ 5221 5222 uint16_t daccmpoffset; 5223 uint8_t dacver, dacheaderlen; 5224 5225 if (bitentry->length < 6) { 5226 NV_ERROR(dev, "BIT i table too short for needed information\n"); 5227 return -EINVAL; 5228 } 5229 5230 parse_bios_version(dev, bios, bitentry->offset); 5231 5232 /* 5233 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's 5234 * Quadro identity crisis), other bits possibly as for BMP feature byte 5235 */ 5236 bios->feature_byte = bios->data[bitentry->offset + 5]; 5237 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE; 5238 5239 if (bitentry->length < 15) { 5240 NV_WARN(dev, "BIT i table not long enough for DAC load " 5241 "detection comparison table\n"); 5242 return -EINVAL; 5243 } 5244 5245 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]); 5246 5247 /* doesn't exist on g80 */ 5248 if (!daccmpoffset) 5249 return 0; 5250 5251 /* 5252 * The first value in the table, following the header, is the 5253 * comparison value, the second entry is a comparison value for 5254 * TV load detection. 5255 */ 5256 5257 dacver = bios->data[daccmpoffset]; 5258 dacheaderlen = bios->data[daccmpoffset + 1]; 5259 5260 if (dacver != 0x00 && dacver != 0x10) { 5261 NV_WARN(dev, "DAC load detection comparison table version " 5262 "%d.%d not known\n", dacver >> 4, dacver & 0xf); 5263 return -ENOSYS; 5264 } 5265 5266 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]); 5267 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]); 5268 5269 return 0; 5270} 5271 5272static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5273{ 5274 /* 5275 * Parses the LVDS table segment that the bit entry points to. 5276 * Starting at bitentry->offset: 5277 * 5278 * offset + 0 (16 bits): LVDS strap xlate table pointer 5279 */ 5280 5281 if (bitentry->length != 2) { 5282 NV_ERROR(dev, "Do not understand BIT LVDS table\n"); 5283 return -EINVAL; 5284 } 5285 5286 /* 5287 * No idea if it's still called the LVDS manufacturer table, but 5288 * the concept's close enough. 5289 */ 5290 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]); 5291 5292 return 0; 5293} 5294 5295static int 5296parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios, 5297 struct bit_entry *bitentry) 5298{ 5299 /* 5300 * offset + 2 (8 bits): number of options in an 5301 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set 5302 * offset + 3 (16 bits): pointer to strap xlate table for RAM 5303 * restrict option selection 5304 * 5305 * There's a bunch of bits in this table other than the RAM restrict 5306 * stuff that we don't use - their use currently unknown 5307 */ 5308 5309 /* 5310 * Older bios versions don't have a sufficiently long table for 5311 * what we want 5312 */ 5313 if (bitentry->length < 0x5) 5314 return 0; 5315 5316 if (bitentry->id[1] < 2) { 5317 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2]; 5318 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]); 5319 } else { 5320 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0]; 5321 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]); 5322 } 5323 5324 return 0; 5325} 5326 5327static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5328{ 5329 /* 5330 * Parses the pointer to the TMDS table 5331 * 5332 * Starting at bitentry->offset: 5333 * 5334 * offset + 0 (16 bits): TMDS table pointer 5335 * 5336 * The TMDS table is typically found just before the DCB table, with a 5337 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being 5338 * length?) 5339 * 5340 * At offset +7 is a pointer to a script, which I don't know how to 5341 * run yet. 5342 * At offset +9 is a pointer to another script, likewise 5343 * Offset +11 has a pointer to a table where the first word is a pxclk 5344 * frequency and the second word a pointer to a script, which should be 5345 * run if the comparison pxclk frequency is less than the pxclk desired. 5346 * This repeats for decreasing comparison frequencies 5347 * Offset +13 has a pointer to a similar table 5348 * The selection of table (and possibly +7/+9 script) is dictated by 5349 * "or" from the DCB. 5350 */ 5351 5352 uint16_t tmdstableptr, script1, script2; 5353 5354 if (bitentry->length != 2) { 5355 NV_ERROR(dev, "Do not understand BIT TMDS table\n"); 5356 return -EINVAL; 5357 } 5358 5359 tmdstableptr = ROM16(bios->data[bitentry->offset]); 5360 5361 if (tmdstableptr == 0x0) { 5362 NV_ERROR(dev, "Pointer to TMDS table invalid\n"); 5363 return -EINVAL; 5364 } 5365 5366 /* nv50+ has v2.0, but we don't parse it atm */ 5367 if (bios->data[tmdstableptr] != 0x11) { 5368 NV_WARN(dev, 5369 "TMDS table revision %d.%d not currently supported\n", 5370 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf); 5371 return -ENOSYS; 5372 } 5373 5374 /* 5375 * These two scripts are odd: they don't seem to get run even when 5376 * they are not stubbed. 5377 */ 5378 script1 = ROM16(bios->data[tmdstableptr + 7]); 5379 script2 = ROM16(bios->data[tmdstableptr + 9]); 5380 if (bios->data[script1] != 'q' || bios->data[script2] != 'q') 5381 NV_WARN(dev, "TMDS table script pointers not stubbed\n"); 5382 5383 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]); 5384 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]); 5385 5386 return 0; 5387} 5388 5389static int 5390parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios, 5391 struct bit_entry *bitentry) 5392{ 5393 /* 5394 * Parses the pointer to the G80 output script tables 5395 * 5396 * Starting at bitentry->offset: 5397 * 5398 * offset + 0 (16 bits): output script table pointer 5399 */ 5400 5401 uint16_t outputscripttableptr; 5402 5403 if (bitentry->length != 3) { 5404 NV_ERROR(dev, "Do not understand BIT U table\n"); 5405 return -EINVAL; 5406 } 5407 5408 outputscripttableptr = ROM16(bios->data[bitentry->offset]); 5409 bios->display.script_table_ptr = outputscripttableptr; 5410 return 0; 5411} 5412 5413static int 5414parse_bit_displayport_tbl_entry(struct drm_device *dev, struct nvbios *bios, 5415 struct bit_entry *bitentry) 5416{ 5417 bios->display.dp_table_ptr = ROM16(bios->data[bitentry->offset]); 5418 return 0; 5419} 5420 5421struct bit_table { 5422 const char id; 5423 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *); 5424}; 5425 5426#define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry }) 5427 5428static int 5429parse_bit_table(struct nvbios *bios, const uint16_t bitoffset, 5430 struct bit_table *table) 5431{ 5432 struct drm_device *dev = bios->dev; 5433 uint8_t maxentries = bios->data[bitoffset + 4]; 5434 int i, offset; 5435 struct bit_entry bitentry; 5436 5437 for (i = 0, offset = bitoffset + 6; i < maxentries; i++, offset += 6) { 5438 bitentry.id[0] = bios->data[offset]; 5439 5440 if (bitentry.id[0] != table->id) 5441 continue; 5442 5443 bitentry.id[1] = bios->data[offset + 1]; 5444 bitentry.length = ROM16(bios->data[offset + 2]); 5445 bitentry.offset = ROM16(bios->data[offset + 4]); 5446 5447 return table->parse_fn(dev, bios, &bitentry); 5448 } 5449 5450 NV_INFO(dev, "BIT table '%c' not found\n", table->id); 5451 return -ENOSYS; 5452} 5453 5454static int 5455parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset) 5456{ 5457 int ret; 5458 5459 /* 5460 * The only restriction on parsing order currently is having 'i' first 5461 * for use of bios->*_version or bios->feature_byte while parsing; 5462 * functions shouldn't be actually *doing* anything apart from pulling 5463 * data from the image into the bios struct, thus no interdependencies 5464 */ 5465 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i)); 5466 if (ret) /* info? */ 5467 return ret; 5468 if (bios->major_version >= 0x60) /* g80+ */ 5469 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A)); 5470 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C)); 5471 if (ret) 5472 return ret; 5473 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display)); 5474 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init)); 5475 if (ret) 5476 return ret; 5477 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */ 5478 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds)); 5479 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds)); 5480 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U)); 5481 parse_bit_table(bios, bitoffset, &BIT_TABLE('d', displayport)); 5482 5483 return 0; 5484} 5485 5486static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset) 5487{ 5488 /* 5489 * Parses the BMP structure for useful things, but does not act on them 5490 * 5491 * offset + 5: BMP major version 5492 * offset + 6: BMP minor version 5493 * offset + 9: BMP feature byte 5494 * offset + 10: BCD encoded BIOS version 5495 * 5496 * offset + 18: init script table pointer (for bios versions < 5.10h) 5497 * offset + 20: extra init script table pointer (for bios 5498 * versions < 5.10h) 5499 * 5500 * offset + 24: memory init table pointer (used on early bios versions) 5501 * offset + 26: SDR memory sequencing setup data table 5502 * offset + 28: DDR memory sequencing setup data table 5503 * 5504 * offset + 54: index of I2C CRTC pair to use for CRT output 5505 * offset + 55: index of I2C CRTC pair to use for TV output 5506 * offset + 56: index of I2C CRTC pair to use for flat panel output 5507 * offset + 58: write CRTC index for I2C pair 0 5508 * offset + 59: read CRTC index for I2C pair 0 5509 * offset + 60: write CRTC index for I2C pair 1 5510 * offset + 61: read CRTC index for I2C pair 1 5511 * 5512 * offset + 67: maximum internal PLL frequency (single stage PLL) 5513 * offset + 71: minimum internal PLL frequency (single stage PLL) 5514 * 5515 * offset + 75: script table pointers, as described in 5516 * parse_script_table_pointers 5517 * 5518 * offset + 89: TMDS single link output A table pointer 5519 * offset + 91: TMDS single link output B table pointer 5520 * offset + 95: LVDS single link output A table pointer 5521 * offset + 105: flat panel timings table pointer 5522 * offset + 107: flat panel strapping translation table pointer 5523 * offset + 117: LVDS manufacturer panel config table pointer 5524 * offset + 119: LVDS manufacturer strapping translation table pointer 5525 * 5526 * offset + 142: PLL limits table pointer 5527 * 5528 * offset + 156: minimum pixel clock for LVDS dual link 5529 */ 5530 5531 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor; 5532 uint16_t bmplength; 5533 uint16_t legacy_scripts_offset, legacy_i2c_offset; 5534 5535 /* load needed defaults in case we can't parse this info */ 5536 bios->dcb.i2c[0].write = NV_CIO_CRE_DDC_WR__INDEX; 5537 bios->dcb.i2c[0].read = NV_CIO_CRE_DDC_STATUS__INDEX; 5538 bios->dcb.i2c[1].write = NV_CIO_CRE_DDC0_WR__INDEX; 5539 bios->dcb.i2c[1].read = NV_CIO_CRE_DDC0_STATUS__INDEX; 5540 bios->digital_min_front_porch = 0x4b; 5541 bios->fmaxvco = 256000; 5542 bios->fminvco = 128000; 5543 bios->fp.duallink_transition_clk = 90000; 5544 5545 bmp_version_major = bmp[5]; 5546 bmp_version_minor = bmp[6]; 5547 5548 NV_TRACE(dev, "BMP version %d.%d\n", 5549 bmp_version_major, bmp_version_minor); 5550 5551 /* 5552 * Make sure that 0x36 is blank and can't be mistaken for a DCB 5553 * pointer on early versions 5554 */ 5555 if (bmp_version_major < 5) 5556 *(uint16_t *)&bios->data[0x36] = 0; 5557 5558 /* 5559 * Seems that the minor version was 1 for all major versions prior 5560 * to 5. Version 6 could theoretically exist, but I suspect BIT 5561 * happened instead. 5562 */ 5563 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) { 5564 NV_ERROR(dev, "You have an unsupported BMP version. " 5565 "Please send in your bios\n"); 5566 return -ENOSYS; 5567 } 5568 5569 if (bmp_version_major == 0) 5570 /* nothing that's currently useful in this version */ 5571 return 0; 5572 else if (bmp_version_major == 1) 5573 bmplength = 44; /* exact for 1.01 */ 5574 else if (bmp_version_major == 2) 5575 bmplength = 48; /* exact for 2.01 */ 5576 else if (bmp_version_major == 3) 5577 bmplength = 54; 5578 /* guessed - mem init tables added in this version */ 5579 else if (bmp_version_major == 4 || bmp_version_minor < 0x1) 5580 /* don't know if 5.0 exists... */ 5581 bmplength = 62; 5582 /* guessed - BMP I2C indices added in version 4*/ 5583 else if (bmp_version_minor < 0x6) 5584 bmplength = 67; /* exact for 5.01 */ 5585 else if (bmp_version_minor < 0x10) 5586 bmplength = 75; /* exact for 5.06 */ 5587 else if (bmp_version_minor == 0x10) 5588 bmplength = 89; /* exact for 5.10h */ 5589 else if (bmp_version_minor < 0x14) 5590 bmplength = 118; /* exact for 5.11h */ 5591 else if (bmp_version_minor < 0x24) 5592 /* 5593 * Not sure of version where pll limits came in; 5594 * certainly exist by 0x24 though. 5595 */ 5596 /* length not exact: this is long enough to get lvds members */ 5597 bmplength = 123; 5598 else if (bmp_version_minor < 0x27) 5599 /* 5600 * Length not exact: this is long enough to get pll limit 5601 * member 5602 */ 5603 bmplength = 144; 5604 else 5605 /* 5606 * Length not exact: this is long enough to get dual link 5607 * transition clock. 5608 */ 5609 bmplength = 158; 5610 5611 /* checksum */ 5612 if (nv_cksum(bmp, 8)) { 5613 NV_ERROR(dev, "Bad BMP checksum\n"); 5614 return -EINVAL; 5615 } 5616 5617 /* 5618 * Bit 4 seems to indicate either a mobile bios or a quadro card -- 5619 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl 5620 * (not nv10gl), bit 5 that the flat panel tables are present, and 5621 * bit 6 a tv bios. 5622 */ 5623 bios->feature_byte = bmp[9]; 5624 5625 parse_bios_version(dev, bios, offset + 10); 5626 5627 if (bmp_version_major < 5 || bmp_version_minor < 0x10) 5628 bios->old_style_init = true; 5629 legacy_scripts_offset = 18; 5630 if (bmp_version_major < 2) 5631 legacy_scripts_offset -= 4; 5632 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]); 5633 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]); 5634 5635 if (bmp_version_major > 2) { /* appears in BMP 3 */ 5636 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]); 5637 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]); 5638 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]); 5639 } 5640 5641 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */ 5642 if (bmplength > 61) 5643 legacy_i2c_offset = offset + 54; 5644 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset]; 5645 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1]; 5646 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2]; 5647 if (bios->data[legacy_i2c_offset + 4]) 5648 bios->dcb.i2c[0].write = bios->data[legacy_i2c_offset + 4]; 5649 if (bios->data[legacy_i2c_offset + 5]) 5650 bios->dcb.i2c[0].read = bios->data[legacy_i2c_offset + 5]; 5651 if (bios->data[legacy_i2c_offset + 6]) 5652 bios->dcb.i2c[1].write = bios->data[legacy_i2c_offset + 6]; 5653 if (bios->data[legacy_i2c_offset + 7]) 5654 bios->dcb.i2c[1].read = bios->data[legacy_i2c_offset + 7]; 5655 5656 if (bmplength > 74) { 5657 bios->fmaxvco = ROM32(bmp[67]); 5658 bios->fminvco = ROM32(bmp[71]); 5659 } 5660 if (bmplength > 88) 5661 parse_script_table_pointers(bios, offset + 75); 5662 if (bmplength > 94) { 5663 bios->tmds.output0_script_ptr = ROM16(bmp[89]); 5664 bios->tmds.output1_script_ptr = ROM16(bmp[91]); 5665 /* 5666 * Never observed in use with lvds scripts, but is reused for 5667 * 18/24 bit panel interface default for EDID equipped panels 5668 * (if_is_24bit not set directly to avoid any oscillation). 5669 */ 5670 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]); 5671 } 5672 if (bmplength > 108) { 5673 bios->fp.fptablepointer = ROM16(bmp[105]); 5674 bios->fp.fpxlatetableptr = ROM16(bmp[107]); 5675 bios->fp.xlatwidth = 1; 5676 } 5677 if (bmplength > 120) { 5678 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]); 5679 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]); 5680 } 5681 if (bmplength > 143) 5682 bios->pll_limit_tbl_ptr = ROM16(bmp[142]); 5683 5684 if (bmplength > 157) 5685 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10; 5686 5687 return 0; 5688} 5689 5690static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len) 5691{ 5692 int i, j; 5693 5694 for (i = 0; i <= (n - len); i++) { 5695 for (j = 0; j < len; j++) 5696 if (data[i + j] != str[j]) 5697 break; 5698 if (j == len) 5699 return i; 5700 } 5701 5702 return 0; 5703} 5704 5705static struct dcb_gpio_entry * 5706new_gpio_entry(struct nvbios *bios) 5707{ 5708 struct dcb_gpio_table *gpio = &bios->dcb.gpio; 5709 5710 return &gpio->entry[gpio->entries++]; 5711} 5712 5713struct dcb_gpio_entry * 5714nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag) 5715{ 5716 struct drm_nouveau_private *dev_priv = dev->dev_private; 5717 struct nvbios *bios = &dev_priv->vbios; 5718 int i; 5719 5720 for (i = 0; i < bios->dcb.gpio.entries; i++) { 5721 if (bios->dcb.gpio.entry[i].tag != tag) 5722 continue; 5723 5724 return &bios->dcb.gpio.entry[i]; 5725 } 5726 5727 return NULL; 5728} 5729 5730static void 5731parse_dcb30_gpio_entry(struct nvbios *bios, uint16_t offset) 5732{ 5733 struct dcb_gpio_entry *gpio; 5734 uint16_t ent = ROM16(bios->data[offset]); 5735 uint8_t line = ent & 0x1f, 5736 tag = ent >> 5 & 0x3f, 5737 flags = ent >> 11 & 0x1f; 5738 5739 if (tag == 0x3f) 5740 return; 5741 5742 gpio = new_gpio_entry(bios); 5743 5744 gpio->tag = tag; 5745 gpio->line = line; 5746 gpio->invert = flags != 4; 5747 gpio->entry = ent; 5748} 5749 5750static void 5751parse_dcb40_gpio_entry(struct nvbios *bios, uint16_t offset) 5752{ 5753 uint32_t entry = ROM32(bios->data[offset]); 5754 struct dcb_gpio_entry *gpio; 5755 5756 if ((entry & 0x0000ff00) == 0x0000ff00) 5757 return; 5758 5759 gpio = new_gpio_entry(bios); 5760 gpio->tag = (entry & 0x0000ff00) >> 8; 5761 gpio->line = (entry & 0x0000001f) >> 0; 5762 gpio->state_default = (entry & 0x01000000) >> 24; 5763 gpio->state[0] = (entry & 0x18000000) >> 27; 5764 gpio->state[1] = (entry & 0x60000000) >> 29; 5765 gpio->entry = entry; 5766} 5767 5768static void 5769parse_dcb_gpio_table(struct nvbios *bios) 5770{ 5771 struct drm_device *dev = bios->dev; 5772 uint16_t gpio_table_ptr = bios->dcb.gpio_table_ptr; 5773 uint8_t *gpio_table = &bios->data[gpio_table_ptr]; 5774 int header_len = gpio_table[1], 5775 entries = gpio_table[2], 5776 entry_len = gpio_table[3]; 5777 void (*parse_entry)(struct nvbios *, uint16_t) = NULL; 5778 int i; 5779 5780 if (bios->dcb.version >= 0x40) { 5781 if (gpio_table_ptr && entry_len != 4) { 5782 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n"); 5783 return; 5784 } 5785 5786 parse_entry = parse_dcb40_gpio_entry; 5787 5788 } else if (bios->dcb.version >= 0x30) { 5789 if (gpio_table_ptr && entry_len != 2) { 5790 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n"); 5791 return; 5792 } 5793 5794 parse_entry = parse_dcb30_gpio_entry; 5795 5796 } else if (bios->dcb.version >= 0x22) { 5797 /* 5798 * DCBs older than v3.0 don't really have a GPIO 5799 * table, instead they keep some GPIO info at fixed 5800 * locations. 5801 */ 5802 uint16_t dcbptr = ROM16(bios->data[0x36]); 5803 uint8_t *tvdac_gpio = &bios->data[dcbptr - 5]; 5804 5805 if (tvdac_gpio[0] & 1) { 5806 struct dcb_gpio_entry *gpio = new_gpio_entry(bios); 5807 5808 gpio->tag = DCB_GPIO_TVDAC0; 5809 gpio->line = tvdac_gpio[1] >> 4; 5810 gpio->invert = tvdac_gpio[0] & 2; 5811 } 5812 } 5813 5814 if (!gpio_table_ptr) 5815 return; 5816 5817 if (entries > DCB_MAX_NUM_GPIO_ENTRIES) { 5818 NV_WARN(dev, "Too many entries in the DCB GPIO table.\n"); 5819 entries = DCB_MAX_NUM_GPIO_ENTRIES; 5820 } 5821 5822 for (i = 0; i < entries; i++) 5823 parse_entry(bios, gpio_table_ptr + header_len + entry_len * i); 5824} 5825 5826struct dcb_connector_table_entry * 5827nouveau_bios_connector_entry(struct drm_device *dev, int index) 5828{ 5829 struct drm_nouveau_private *dev_priv = dev->dev_private; 5830 struct nvbios *bios = &dev_priv->vbios; 5831 struct dcb_connector_table_entry *cte; 5832 5833 if (index >= bios->dcb.connector.entries) 5834 return NULL; 5835 5836 cte = &bios->dcb.connector.entry[index]; 5837 if (cte->type == 0xff) 5838 return NULL; 5839 5840 return cte; 5841} 5842 5843static enum dcb_connector_type 5844divine_connector_type(struct nvbios *bios, int index) 5845{ 5846 struct dcb_table *dcb = &bios->dcb; 5847 unsigned encoders = 0, type = DCB_CONNECTOR_NONE; 5848 int i; 5849 5850 for (i = 0; i < dcb->entries; i++) { 5851 if (dcb->entry[i].connector == index) 5852 encoders |= (1 << dcb->entry[i].type); 5853 } 5854 5855 if (encoders & (1 << OUTPUT_DP)) { 5856 if (encoders & (1 << OUTPUT_TMDS)) 5857 type = DCB_CONNECTOR_DP; 5858 else 5859 type = DCB_CONNECTOR_eDP; 5860 } else 5861 if (encoders & (1 << OUTPUT_TMDS)) { 5862 if (encoders & (1 << OUTPUT_ANALOG)) 5863 type = DCB_CONNECTOR_DVI_I; 5864 else 5865 type = DCB_CONNECTOR_DVI_D; 5866 } else 5867 if (encoders & (1 << OUTPUT_ANALOG)) { 5868 type = DCB_CONNECTOR_VGA; 5869 } else 5870 if (encoders & (1 << OUTPUT_LVDS)) { 5871 type = DCB_CONNECTOR_LVDS; 5872 } else 5873 if (encoders & (1 << OUTPUT_TV)) { 5874 type = DCB_CONNECTOR_TV_0; 5875 } 5876 5877 return type; 5878} 5879 5880static void 5881apply_dcb_connector_quirks(struct nvbios *bios, int idx) 5882{ 5883 struct dcb_connector_table_entry *cte = &bios->dcb.connector.entry[idx]; 5884 struct drm_device *dev = bios->dev; 5885 5886 /* Gigabyte NX85T */ 5887 if ((dev->pdev->device == 0x0421) && 5888 (dev->pdev->subsystem_vendor == 0x1458) && 5889 (dev->pdev->subsystem_device == 0x344c)) { 5890 if (cte->type == DCB_CONNECTOR_HDMI_1) 5891 cte->type = DCB_CONNECTOR_DVI_I; 5892 } 5893} 5894 5895static void 5896parse_dcb_connector_table(struct nvbios *bios) 5897{ 5898 struct drm_device *dev = bios->dev; 5899 struct dcb_connector_table *ct = &bios->dcb.connector; 5900 struct dcb_connector_table_entry *cte; 5901 uint8_t *conntab = &bios->data[bios->dcb.connector_table_ptr]; 5902 uint8_t *entry; 5903 int i; 5904 5905 if (!bios->dcb.connector_table_ptr) { 5906 NV_DEBUG_KMS(dev, "No DCB connector table present\n"); 5907 return; 5908 } 5909 5910 NV_INFO(dev, "DCB connector table: VHER 0x%02x %d %d %d\n", 5911 conntab[0], conntab[1], conntab[2], conntab[3]); 5912 if ((conntab[0] != 0x30 && conntab[0] != 0x40) || 5913 (conntab[3] != 2 && conntab[3] != 4)) { 5914 NV_ERROR(dev, " Unknown! Please report.\n"); 5915 return; 5916 } 5917 5918 ct->entries = conntab[2]; 5919 5920 entry = conntab + conntab[1]; 5921 cte = &ct->entry[0]; 5922 for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) { 5923 cte->index = i; 5924 if (conntab[3] == 2) 5925 cte->entry = ROM16(entry[0]); 5926 else 5927 cte->entry = ROM32(entry[0]); 5928 5929 cte->type = (cte->entry & 0x000000ff) >> 0; 5930 cte->index2 = (cte->entry & 0x00000f00) >> 8; 5931 switch (cte->entry & 0x00033000) { 5932 case 0x00001000: 5933 cte->gpio_tag = 0x07; 5934 break; 5935 case 0x00002000: 5936 cte->gpio_tag = 0x08; 5937 break; 5938 case 0x00010000: 5939 cte->gpio_tag = 0x51; 5940 break; 5941 case 0x00020000: 5942 cte->gpio_tag = 0x52; 5943 break; 5944 default: 5945 cte->gpio_tag = 0xff; 5946 break; 5947 } 5948 5949 if (cte->type == 0xff) 5950 continue; 5951 5952 apply_dcb_connector_quirks(bios, i); 5953 5954 NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n", 5955 i, cte->entry, cte->type, cte->index, cte->gpio_tag); 5956 5957 /* check for known types, fallback to guessing the type 5958 * from attached encoders if we hit an unknown. 5959 */ 5960 switch (cte->type) { 5961 case DCB_CONNECTOR_VGA: 5962 case DCB_CONNECTOR_TV_0: 5963 case DCB_CONNECTOR_TV_1: 5964 case DCB_CONNECTOR_TV_3: 5965 case DCB_CONNECTOR_DVI_I: 5966 case DCB_CONNECTOR_DVI_D: 5967 case DCB_CONNECTOR_LVDS: 5968 case DCB_CONNECTOR_DP: 5969 case DCB_CONNECTOR_eDP: 5970 case DCB_CONNECTOR_HDMI_0: 5971 case DCB_CONNECTOR_HDMI_1: 5972 break; 5973 default: 5974 cte->type = divine_connector_type(bios, cte->index); 5975 NV_WARN(dev, "unknown type, using 0x%02x\n", cte->type); 5976 break; 5977 } 5978 5979 if (nouveau_override_conntype) { 5980 int type = divine_connector_type(bios, cte->index); 5981 if (type != cte->type) 5982 NV_WARN(dev, " -> type 0x%02x\n", cte->type); 5983 } 5984 5985 } 5986} 5987 5988static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb) 5989{ 5990 struct dcb_entry *entry = &dcb->entry[dcb->entries]; 5991 5992 memset(entry, 0, sizeof(struct dcb_entry)); 5993 entry->index = dcb->entries++; 5994 5995 return entry; 5996} 5997 5998static void fabricate_vga_output(struct dcb_table *dcb, int i2c, int heads) 5999{ 6000 struct dcb_entry *entry = new_dcb_entry(dcb); 6001 6002 entry->type = 0; 6003 entry->i2c_index = i2c; 6004 entry->heads = heads; 6005 entry->location = DCB_LOC_ON_CHIP; 6006 entry->or = 1; 6007} 6008 6009static void fabricate_dvi_i_output(struct dcb_table *dcb, bool twoHeads) 6010{ 6011 struct dcb_entry *entry = new_dcb_entry(dcb); 6012 6013 entry->type = 2; 6014 entry->i2c_index = LEGACY_I2C_PANEL; 6015 entry->heads = twoHeads ? 3 : 1; 6016 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */ 6017 entry->or = 1; /* means |0x10 gets set on CRE_LCD__INDEX */ 6018 entry->duallink_possible = false; /* SiI164 and co. are single link */ 6019 6020#if 0 6021 /* 6022 * For dvi-a either crtc probably works, but my card appears to only 6023 * support dvi-d. "nvidia" still attempts to program it for dvi-a, 6024 * doing the full fp output setup (program 0x6808.. fp dimension regs, 6025 * setting 0x680848 to 0x10000111 to enable, maybe setting 0x680880); 6026 * the monitor picks up the mode res ok and lights up, but no pixel 6027 * data appears, so the board manufacturer probably connected up the 6028 * sync lines, but missed the video traces / components 6029 * 6030 * with this introduction, dvi-a left as an exercise for the reader. 6031 */ 6032 fabricate_vga_output(dcb, LEGACY_I2C_PANEL, entry->heads); 6033#endif 6034} 6035 6036static void fabricate_tv_output(struct dcb_table *dcb, bool twoHeads) 6037{ 6038 struct dcb_entry *entry = new_dcb_entry(dcb); 6039 6040 entry->type = 1; 6041 entry->i2c_index = LEGACY_I2C_TV; 6042 entry->heads = twoHeads ? 3 : 1; 6043 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */ 6044} 6045 6046static bool 6047parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb, 6048 uint32_t conn, uint32_t conf, struct dcb_entry *entry) 6049{ 6050 entry->type = conn & 0xf; 6051 entry->i2c_index = (conn >> 4) & 0xf; 6052 entry->heads = (conn >> 8) & 0xf; 6053 if (dcb->version >= 0x40) 6054 entry->connector = (conn >> 12) & 0xf; 6055 entry->bus = (conn >> 16) & 0xf; 6056 entry->location = (conn >> 20) & 0x3; 6057 entry->or = (conn >> 24) & 0xf; 6058 6059 switch (entry->type) { 6060 case OUTPUT_ANALOG: 6061 /* 6062 * Although the rest of a CRT conf dword is usually 6063 * zeros, mac biosen have stuff there so we must mask 6064 */ 6065 entry->crtconf.maxfreq = (dcb->version < 0x30) ? 6066 (conf & 0xffff) * 10 : 6067 (conf & 0xff) * 10000; 6068 break; 6069 case OUTPUT_LVDS: 6070 { 6071 uint32_t mask; 6072 if (conf & 0x1) 6073 entry->lvdsconf.use_straps_for_mode = true; 6074 if (dcb->version < 0x22) { 6075 mask = ~0xd; 6076 /* 6077 * The laptop in bug 14567 lies and claims to not use 6078 * straps when it does, so assume all DCB 2.0 laptops 6079 * use straps, until a broken EDID using one is produced 6080 */ 6081 entry->lvdsconf.use_straps_for_mode = true; 6082 /* 6083 * Both 0x4 and 0x8 show up in v2.0 tables; assume they 6084 * mean the same thing (probably wrong, but might work) 6085 */ 6086 if (conf & 0x4 || conf & 0x8) 6087 entry->lvdsconf.use_power_scripts = true; 6088 } else { 6089 mask = ~0x7; 6090 if (conf & 0x2) 6091 entry->lvdsconf.use_acpi_for_edid = true; 6092 if (conf & 0x4) 6093 entry->lvdsconf.use_power_scripts = true; 6094 entry->lvdsconf.sor.link = (conf & 0x00000030) >> 4; 6095 } 6096 if (conf & mask) { 6097 /* 6098 * Until we even try to use these on G8x, it's 6099 * useless reporting unknown bits. They all are. 6100 */ 6101 if (dcb->version >= 0x40) 6102 break; 6103 6104 NV_ERROR(dev, "Unknown LVDS configuration bits, " 6105 "please report\n"); 6106 } 6107 break; 6108 } 6109 case OUTPUT_TV: 6110 { 6111 if (dcb->version >= 0x30) 6112 entry->tvconf.has_component_output = conf & (0x8 << 4); 6113 else 6114 entry->tvconf.has_component_output = false; 6115 6116 break; 6117 } 6118 case OUTPUT_DP: 6119 entry->dpconf.sor.link = (conf & 0x00000030) >> 4; 6120 entry->dpconf.link_bw = (conf & 0x00e00000) >> 21; 6121 switch ((conf & 0x0f000000) >> 24) { 6122 case 0xf: 6123 entry->dpconf.link_nr = 4; 6124 break; 6125 case 0x3: 6126 entry->dpconf.link_nr = 2; 6127 break; 6128 default: 6129 entry->dpconf.link_nr = 1; 6130 break; 6131 } 6132 break; 6133 case OUTPUT_TMDS: 6134 if (dcb->version >= 0x22) 6135 entry->tmdsconf.slave_addr = (conf & 0x00000070) >> 4; 6136 else if (dcb->version >= 0x30) 6137 entry->tmdsconf.slave_addr = (conf & 0x00000700) >> 8; 6138 else if (dcb->version >= 0x40) 6139 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4; 6140 6141 break; 6142 case 0xe: 6143 /* weird g80 mobile type that "nv" treats as a terminator */ 6144 dcb->entries--; 6145 return false; 6146 default: 6147 break; 6148 } 6149 6150 if (dcb->version < 0x40) { 6151 /* Normal entries consist of a single bit, but dual link has 6152 * the next most significant bit set too 6153 */ 6154 entry->duallink_possible = 6155 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or); 6156 } else { 6157 entry->duallink_possible = (entry->sorconf.link == 3); 6158 } 6159 6160 /* unsure what DCB version introduces this, 3.0? */ 6161 if (conf & 0x100000) 6162 entry->i2c_upper_default = true; 6163 6164 return true; 6165} 6166 6167static bool 6168parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb, 6169 uint32_t conn, uint32_t conf, struct dcb_entry *entry) 6170{ 6171 switch (conn & 0x0000000f) { 6172 case 0: 6173 entry->type = OUTPUT_ANALOG; 6174 break; 6175 case 1: 6176 entry->type = OUTPUT_TV; 6177 break; 6178 case 2: 6179 case 3: 6180 entry->type = OUTPUT_LVDS; 6181 break; 6182 case 4: 6183 switch ((conn & 0x000000f0) >> 4) { 6184 case 0: 6185 entry->type = OUTPUT_TMDS; 6186 break; 6187 case 1: 6188 entry->type = OUTPUT_LVDS; 6189 break; 6190 default: 6191 NV_ERROR(dev, "Unknown DCB subtype 4/%d\n", 6192 (conn & 0x000000f0) >> 4); 6193 return false; 6194 } 6195 break; 6196 default: 6197 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f); 6198 return false; 6199 } 6200 6201 entry->i2c_index = (conn & 0x0003c000) >> 14; 6202 entry->heads = ((conn & 0x001c0000) >> 18) + 1; 6203 entry->or = entry->heads; /* same as heads, hopefully safe enough */ 6204 entry->location = (conn & 0x01e00000) >> 21; 6205 entry->bus = (conn & 0x0e000000) >> 25; 6206 entry->duallink_possible = false; 6207 6208 switch (entry->type) { 6209 case OUTPUT_ANALOG: 6210 entry->crtconf.maxfreq = (conf & 0xffff) * 10; 6211 break; 6212 case OUTPUT_TV: 6213 entry->tvconf.has_component_output = false; 6214 break; 6215 case OUTPUT_LVDS: 6216 if ((conn & 0x00003f00) != 0x10) 6217 entry->lvdsconf.use_straps_for_mode = true; 6218 entry->lvdsconf.use_power_scripts = true; 6219 break; 6220 default: 6221 break; 6222 } 6223 6224 return true; 6225} 6226 6227static bool parse_dcb_entry(struct drm_device *dev, struct dcb_table *dcb, 6228 uint32_t conn, uint32_t conf) 6229{ 6230 struct dcb_entry *entry = new_dcb_entry(dcb); 6231 bool ret; 6232 6233 if (dcb->version >= 0x20) 6234 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry); 6235 else 6236 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry); 6237 if (!ret) 6238 return ret; 6239 6240 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table, 6241 entry->i2c_index, &dcb->i2c[entry->i2c_index]); 6242 6243 return true; 6244} 6245 6246static 6247void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb) 6248{ 6249 /* 6250 * DCB v2.0 lists each output combination separately. 6251 * Here we merge compatible entries to have fewer outputs, with 6252 * more options 6253 */ 6254 6255 int i, newentries = 0; 6256 6257 for (i = 0; i < dcb->entries; i++) { 6258 struct dcb_entry *ient = &dcb->entry[i]; 6259 int j; 6260 6261 for (j = i + 1; j < dcb->entries; j++) { 6262 struct dcb_entry *jent = &dcb->entry[j]; 6263 6264 if (jent->type == 100) /* already merged entry */ 6265 continue; 6266 6267 /* merge heads field when all other fields the same */ 6268 if (jent->i2c_index == ient->i2c_index && 6269 jent->type == ient->type && 6270 jent->location == ient->location && 6271 jent->or == ient->or) { 6272 NV_TRACE(dev, "Merging DCB entries %d and %d\n", 6273 i, j); 6274 ient->heads |= jent->heads; 6275 jent->type = 100; /* dummy value */ 6276 } 6277 } 6278 } 6279 6280 /* Compact entries merged into others out of dcb */ 6281 for (i = 0; i < dcb->entries; i++) { 6282 if (dcb->entry[i].type == 100) 6283 continue; 6284 6285 if (newentries != i) { 6286 dcb->entry[newentries] = dcb->entry[i]; 6287 dcb->entry[newentries].index = newentries; 6288 } 6289 newentries++; 6290 } 6291 6292 dcb->entries = newentries; 6293} 6294 6295static bool 6296apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf) 6297{ 6298 /* Dell Precision M6300 6299 * DCB entry 2: 02025312 00000010 6300 * DCB entry 3: 02026312 00000020 6301 * 6302 * Identical, except apparently a different connector on a 6303 * different SOR link. Not a clue how we're supposed to know 6304 * which one is in use if it even shares an i2c line... 6305 * 6306 * Ignore the connector on the second SOR link to prevent 6307 * nasty problems until this is sorted (assuming it's not a 6308 * VBIOS bug). 6309 */ 6310 if ((dev->pdev->device == 0x040d) && 6311 (dev->pdev->subsystem_vendor == 0x1028) && 6312 (dev->pdev->subsystem_device == 0x019b)) { 6313 if (*conn == 0x02026312 && *conf == 0x00000020) 6314 return false; 6315 } 6316 6317 return true; 6318} 6319 6320static int 6321parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads) 6322{ 6323 struct drm_nouveau_private *dev_priv = dev->dev_private; 6324 struct dcb_table *dcb = &bios->dcb; 6325 uint16_t dcbptr = 0, i2ctabptr = 0; 6326 uint8_t *dcbtable; 6327 uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES; 6328 bool configblock = true; 6329 int recordlength = 8, confofs = 4; 6330 int i; 6331 6332 /* get the offset from 0x36 */ 6333 if (dev_priv->card_type > NV_04) { 6334 dcbptr = ROM16(bios->data[0x36]); 6335 if (dcbptr == 0x0000) 6336 NV_WARN(dev, "No output data (DCB) found in BIOS\n"); 6337 } 6338 6339 /* this situation likely means a really old card, pre DCB */ 6340 if (dcbptr == 0x0) { 6341 NV_INFO(dev, "Assuming a CRT output exists\n"); 6342 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1); 6343 6344 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0) 6345 fabricate_tv_output(dcb, twoHeads); 6346 6347 return 0; 6348 } 6349 6350 dcbtable = &bios->data[dcbptr]; 6351 6352 /* get DCB version */ 6353 dcb->version = dcbtable[0]; 6354 NV_TRACE(dev, "Found Display Configuration Block version %d.%d\n", 6355 dcb->version >> 4, dcb->version & 0xf); 6356 6357 if (dcb->version >= 0x20) { /* NV17+ */ 6358 uint32_t sig; 6359 6360 if (dcb->version >= 0x30) { /* NV40+ */ 6361 headerlen = dcbtable[1]; 6362 entries = dcbtable[2]; 6363 recordlength = dcbtable[3]; 6364 i2ctabptr = ROM16(dcbtable[4]); 6365 sig = ROM32(dcbtable[6]); 6366 dcb->gpio_table_ptr = ROM16(dcbtable[10]); 6367 dcb->connector_table_ptr = ROM16(dcbtable[20]); 6368 } else { 6369 i2ctabptr = ROM16(dcbtable[2]); 6370 sig = ROM32(dcbtable[4]); 6371 headerlen = 8; 6372 } 6373 6374 if (sig != 0x4edcbdcb) { 6375 NV_ERROR(dev, "Bad Display Configuration Block " 6376 "signature (%08X)\n", sig); 6377 return -EINVAL; 6378 } 6379 } else if (dcb->version >= 0x15) { /* some NV11 and NV20 */ 6380 char sig[8] = { 0 }; 6381 6382 strncpy(sig, (char *)&dcbtable[-7], 7); 6383 i2ctabptr = ROM16(dcbtable[2]); 6384 recordlength = 10; 6385 confofs = 6; 6386 6387 if (strcmp(sig, "DEV_REC")) { 6388 NV_ERROR(dev, "Bad Display Configuration Block " 6389 "signature (%s)\n", sig); 6390 return -EINVAL; 6391 } 6392 } else { 6393 /* 6394 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always 6395 * has the same single (crt) entry, even when tv-out present, so 6396 * the conclusion is this version cannot really be used. 6397 * v1.2 tables (some NV6/10, and NV15+) normally have the same 6398 * 5 entries, which are not specific to the card and so no use. 6399 * v1.2 does have an I2C table that read_dcb_i2c_table can 6400 * handle, but cards exist (nv11 in #14821) with a bad i2c table 6401 * pointer, so use the indices parsed in parse_bmp_structure. 6402 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful 6403 */ 6404 NV_TRACEWARN(dev, "No useful information in BIOS output table; " 6405 "adding all possible outputs\n"); 6406 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1); 6407 6408 /* 6409 * Attempt to detect TV before DVI because the test 6410 * for the former is more accurate and it rules the 6411 * latter out. 6412 */ 6413 if (nv04_tv_identify(dev, 6414 bios->legacy.i2c_indices.tv) >= 0) 6415 fabricate_tv_output(dcb, twoHeads); 6416 6417 else if (bios->tmds.output0_script_ptr || 6418 bios->tmds.output1_script_ptr) 6419 fabricate_dvi_i_output(dcb, twoHeads); 6420 6421 return 0; 6422 } 6423 6424 if (!i2ctabptr) 6425 NV_WARN(dev, "No pointer to DCB I2C port table\n"); 6426 else { 6427 dcb->i2c_table = &bios->data[i2ctabptr]; 6428 if (dcb->version >= 0x30) 6429 dcb->i2c_default_indices = dcb->i2c_table[4]; 6430 6431 /* 6432 * Parse the "management" I2C bus, used for hardware 6433 * monitoring and some external TMDS transmitters. 6434 */ 6435 if (dcb->version >= 0x22) { 6436 int idx = (dcb->version >= 0x40 ? 6437 dcb->i2c_default_indices & 0xf : 6438 2); 6439 6440 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table, 6441 idx, &dcb->i2c[idx]); 6442 } 6443 } 6444 6445 if (entries > DCB_MAX_NUM_ENTRIES) 6446 entries = DCB_MAX_NUM_ENTRIES; 6447 6448 for (i = 0; i < entries; i++) { 6449 uint32_t connection, config = 0; 6450 6451 connection = ROM32(dcbtable[headerlen + recordlength * i]); 6452 if (configblock) 6453 config = ROM32(dcbtable[headerlen + confofs + recordlength * i]); 6454 6455 /* seen on an NV11 with DCB v1.5 */ 6456 if (connection == 0x00000000) 6457 break; 6458 6459 /* seen on an NV17 with DCB v2.0 */ 6460 if (connection == 0xffffffff) 6461 break; 6462 6463 if ((connection & 0x0000000f) == 0x0000000f) 6464 continue; 6465 6466 if (!apply_dcb_encoder_quirks(dev, i, &connection, &config)) 6467 continue; 6468 6469 NV_TRACEWARN(dev, "Raw DCB entry %d: %08x %08x\n", 6470 dcb->entries, connection, config); 6471 6472 if (!parse_dcb_entry(dev, dcb, connection, config)) 6473 break; 6474 } 6475 6476 /* 6477 * apart for v2.1+ not being known for requiring merging, this 6478 * guarantees dcbent->index is the index of the entry in the rom image 6479 */ 6480 if (dcb->version < 0x21) 6481 merge_like_dcb_entries(dev, dcb); 6482 6483 if (!dcb->entries) 6484 return -ENXIO; 6485 6486 parse_dcb_gpio_table(bios); 6487 parse_dcb_connector_table(bios); 6488 return 0; 6489} 6490 6491static void 6492fixup_legacy_connector(struct nvbios *bios) 6493{ 6494 struct dcb_table *dcb = &bios->dcb; 6495 int i, i2c, i2c_conn[DCB_MAX_NUM_I2C_ENTRIES] = { }; 6496 6497 /* 6498 * DCB 3.0 also has the table in most cases, but there are some cards 6499 * where the table is filled with stub entries, and the DCB entriy 6500 * indices are all 0. We don't need the connector indices on pre-G80 6501 * chips (yet?) so limit the use to DCB 4.0 and above. 6502 */ 6503 if (dcb->version >= 0x40) 6504 return; 6505 6506 dcb->connector.entries = 0; 6507 6508 /* 6509 * No known connector info before v3.0, so make it up. the rule here 6510 * is: anything on the same i2c bus is considered to be on the same 6511 * connector. any output without an associated i2c bus is assigned 6512 * its own unique connector index. 6513 */ 6514 for (i = 0; i < dcb->entries; i++) { 6515 /* 6516 * Ignore the I2C index for on-chip TV-out, as there 6517 * are cards with bogus values (nv31m in bug 23212), 6518 * and it's otherwise useless. 6519 */ 6520 if (dcb->entry[i].type == OUTPUT_TV && 6521 dcb->entry[i].location == DCB_LOC_ON_CHIP) 6522 dcb->entry[i].i2c_index = 0xf; 6523 i2c = dcb->entry[i].i2c_index; 6524 6525 if (i2c_conn[i2c]) { 6526 dcb->entry[i].connector = i2c_conn[i2c] - 1; 6527 continue; 6528 } 6529 6530 dcb->entry[i].connector = dcb->connector.entries++; 6531 if (i2c != 0xf) 6532 i2c_conn[i2c] = dcb->connector.entries; 6533 } 6534 6535 /* Fake the connector table as well as just connector indices */ 6536 for (i = 0; i < dcb->connector.entries; i++) { 6537 dcb->connector.entry[i].index = i; 6538 dcb->connector.entry[i].type = divine_connector_type(bios, i); 6539 dcb->connector.entry[i].gpio_tag = 0xff; 6540 } 6541} 6542 6543static void 6544fixup_legacy_i2c(struct nvbios *bios) 6545{ 6546 struct dcb_table *dcb = &bios->dcb; 6547 int i; 6548 6549 for (i = 0; i < dcb->entries; i++) { 6550 if (dcb->entry[i].i2c_index == LEGACY_I2C_CRT) 6551 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.crt; 6552 if (dcb->entry[i].i2c_index == LEGACY_I2C_PANEL) 6553 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.panel; 6554 if (dcb->entry[i].i2c_index == LEGACY_I2C_TV) 6555 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.tv; 6556 } 6557} 6558 6559static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry) 6560{ 6561 /* 6562 * The header following the "HWSQ" signature has the number of entries, 6563 * and the entry size 6564 * 6565 * An entry consists of a dword to write to the sequencer control reg 6566 * (0x00001304), followed by the ucode bytes, written sequentially, 6567 * starting at reg 0x00001400 6568 */ 6569 6570 uint8_t bytes_to_write; 6571 uint16_t hwsq_entry_offset; 6572 int i; 6573 6574 if (bios->data[hwsq_offset] <= entry) { 6575 NV_ERROR(dev, "Too few entries in HW sequencer table for " 6576 "requested entry\n"); 6577 return -ENOENT; 6578 } 6579 6580 bytes_to_write = bios->data[hwsq_offset + 1]; 6581 6582 if (bytes_to_write != 36) { 6583 NV_ERROR(dev, "Unknown HW sequencer entry size\n"); 6584 return -EINVAL; 6585 } 6586 6587 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n"); 6588 6589 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write; 6590 6591 /* set sequencer control */ 6592 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset])); 6593 bytes_to_write -= 4; 6594 6595 /* write ucode */ 6596 for (i = 0; i < bytes_to_write; i += 4) 6597 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4])); 6598 6599 /* twiddle NV_PBUS_DEBUG_4 */ 6600 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18); 6601 6602 return 0; 6603} 6604 6605static int load_nv17_hw_sequencer_ucode(struct drm_device *dev, 6606 struct nvbios *bios) 6607{ 6608 /* 6609 * BMP based cards, from NV17, need a microcode loading to correctly 6610 * control the GPIO etc for LVDS panels 6611 * 6612 * BIT based cards seem to do this directly in the init scripts 6613 * 6614 * The microcode entries are found by the "HWSQ" signature. 6615 */ 6616 6617 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' }; 6618 const int sz = sizeof(hwsq_signature); 6619 int hwsq_offset; 6620 6621 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz); 6622 if (!hwsq_offset) 6623 return 0; 6624 6625 /* always use entry 0? */ 6626 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0); 6627} 6628 6629uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev) 6630{ 6631 struct drm_nouveau_private *dev_priv = dev->dev_private; 6632 struct nvbios *bios = &dev_priv->vbios; 6633 const uint8_t edid_sig[] = { 6634 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 }; 6635 uint16_t offset = 0; 6636 uint16_t newoffset; 6637 int searchlen = NV_PROM_SIZE; 6638 6639 if (bios->fp.edid) 6640 return bios->fp.edid; 6641 6642 while (searchlen) { 6643 newoffset = findstr(&bios->data[offset], searchlen, 6644 edid_sig, 8); 6645 if (!newoffset) 6646 return NULL; 6647 offset += newoffset; 6648 if (!nv_cksum(&bios->data[offset], EDID1_LEN)) 6649 break; 6650 6651 searchlen -= offset; 6652 offset++; 6653 } 6654 6655 NV_TRACE(dev, "Found EDID in BIOS\n"); 6656 6657 return bios->fp.edid = &bios->data[offset]; 6658} 6659 6660void 6661nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table, 6662 struct dcb_entry *dcbent) 6663{ 6664 struct drm_nouveau_private *dev_priv = dev->dev_private; 6665 struct nvbios *bios = &dev_priv->vbios; 6666 struct init_exec iexec = { true, false }; 6667 6668 mutex_lock(&bios->lock); 6669 bios->display.output = dcbent; 6670 parse_init_table(bios, table, &iexec); 6671 bios->display.output = NULL; 6672 mutex_unlock(&bios->lock); 6673} 6674 6675static bool NVInitVBIOS(struct drm_device *dev) 6676{ 6677 struct drm_nouveau_private *dev_priv = dev->dev_private; 6678 struct nvbios *bios = &dev_priv->vbios; 6679 6680 memset(bios, 0, sizeof(struct nvbios)); 6681 mutex_init(&bios->lock); 6682 bios->dev = dev; 6683 6684 if (!NVShadowVBIOS(dev, bios->data)) 6685 return false; 6686 6687 bios->length = NV_PROM_SIZE; 6688 return true; 6689} 6690 6691static int nouveau_parse_vbios_struct(struct drm_device *dev) 6692{ 6693 struct drm_nouveau_private *dev_priv = dev->dev_private; 6694 struct nvbios *bios = &dev_priv->vbios; 6695 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' }; 6696 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 }; 6697 int offset; 6698 6699 offset = findstr(bios->data, bios->length, 6700 bit_signature, sizeof(bit_signature)); 6701 if (offset) { 6702 NV_TRACE(dev, "BIT BIOS found\n"); 6703 return parse_bit_structure(bios, offset + 6); 6704 } 6705 6706 offset = findstr(bios->data, bios->length, 6707 bmp_signature, sizeof(bmp_signature)); 6708 if (offset) { 6709 NV_TRACE(dev, "BMP BIOS found\n"); 6710 return parse_bmp_structure(dev, bios, offset); 6711 } 6712 6713 NV_ERROR(dev, "No known BIOS signature found\n"); 6714 return -ENODEV; 6715} 6716 6717int 6718nouveau_run_vbios_init(struct drm_device *dev) 6719{ 6720 struct drm_nouveau_private *dev_priv = dev->dev_private; 6721 struct nvbios *bios = &dev_priv->vbios; 6722 int i, ret = 0; 6723 6724 /* Reset the BIOS head to 0. */ 6725 bios->state.crtchead = 0; 6726 6727 if (bios->major_version < 5) /* BMP only */ 6728 load_nv17_hw_sequencer_ucode(dev, bios); 6729 6730 if (bios->execute) { 6731 bios->fp.last_script_invoc = 0; 6732 bios->fp.lvds_init_run = false; 6733 } 6734 6735 parse_init_tables(bios); 6736 6737 /* 6738 * Runs some additional script seen on G8x VBIOSen. The VBIOS' 6739 * parser will run this right after the init tables, the binary 6740 * driver appears to run it at some point later. 6741 */ 6742 if (bios->some_script_ptr) { 6743 struct init_exec iexec = {true, false}; 6744 6745 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n", 6746 bios->some_script_ptr); 6747 parse_init_table(bios, bios->some_script_ptr, &iexec); 6748 } 6749 6750 if (dev_priv->card_type >= NV_50) { 6751 for (i = 0; i < bios->dcb.entries; i++) { 6752 nouveau_bios_run_display_table(dev, 6753 &bios->dcb.entry[i], 6754 0, 0); 6755 } 6756 } 6757 6758 return ret; 6759} 6760 6761static void 6762nouveau_bios_i2c_devices_takedown(struct drm_device *dev) 6763{ 6764 struct drm_nouveau_private *dev_priv = dev->dev_private; 6765 struct nvbios *bios = &dev_priv->vbios; 6766 struct dcb_i2c_entry *entry; 6767 int i; 6768 6769 entry = &bios->dcb.i2c[0]; 6770 for (i = 0; i < DCB_MAX_NUM_I2C_ENTRIES; i++, entry++) 6771 nouveau_i2c_fini(dev, entry); 6772} 6773 6774static bool 6775nouveau_bios_posted(struct drm_device *dev) 6776{ 6777 struct drm_nouveau_private *dev_priv = dev->dev_private; 6778 unsigned htotal; 6779 6780 if (dev_priv->chipset >= NV_50) { 6781 if (NVReadVgaCrtc(dev, 0, 0x00) == 0 && 6782 NVReadVgaCrtc(dev, 0, 0x1a) == 0) 6783 return false; 6784 return true; 6785 } 6786 6787 htotal = NVReadVgaCrtc(dev, 0, 0x06); 6788 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8; 6789 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4; 6790 htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10; 6791 htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11; 6792 6793 return (htotal != 0); 6794} 6795 6796int 6797nouveau_bios_init(struct drm_device *dev) 6798{ 6799 struct drm_nouveau_private *dev_priv = dev->dev_private; 6800 struct nvbios *bios = &dev_priv->vbios; 6801 int ret; 6802 6803 if (!NVInitVBIOS(dev)) 6804 return -ENODEV; 6805 6806 ret = nouveau_parse_vbios_struct(dev); 6807 if (ret) 6808 return ret; 6809 6810 ret = parse_dcb_table(dev, bios, nv_two_heads(dev)); 6811 if (ret) 6812 return ret; 6813 6814 fixup_legacy_i2c(bios); 6815 fixup_legacy_connector(bios); 6816 6817 if (!bios->major_version) /* we don't run version 0 bios */ 6818 return 0; 6819 6820 /* init script execution disabled */ 6821 bios->execute = false; 6822 6823 /* ... unless card isn't POSTed already */ 6824 if (!nouveau_bios_posted(dev)) { 6825 NV_INFO(dev, "Adaptor not initialised, " 6826 "running VBIOS init tables.\n"); 6827 bios->execute = true; 6828 } 6829 6830 ret = nouveau_run_vbios_init(dev); 6831 if (ret) 6832 return ret; 6833 6834 /* feature_byte on BMP is poor, but init always sets CR4B */ 6835 if (bios->major_version < 5) 6836 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40; 6837 6838 /* all BIT systems need p_f_m_t for digital_min_front_porch */ 6839 if (bios->is_mobile || bios->major_version >= 5) 6840 ret = parse_fp_mode_table(dev, bios); 6841 6842 /* allow subsequent scripts to execute */ 6843 bios->execute = true; 6844 6845 return 0; 6846} 6847 6848void 6849nouveau_bios_takedown(struct drm_device *dev) 6850{ 6851 nouveau_bios_i2c_devices_takedown(dev); 6852} 6853