nouveau_bios.c revision 1eb38100abc467f1133e548d82ab171cab34292b
1/* 2 * Copyright 2005-2006 Erik Waling 3 * Copyright 2006 Stephane Marchesin 4 * Copyright 2007-2009 Stuart Bennett 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 25#include "drmP.h" 26#define NV_DEBUG_NOTRACE 27#include "nouveau_drv.h" 28#include "nouveau_hw.h" 29#include "nouveau_encoder.h" 30 31/* these defines are made up */ 32#define NV_CIO_CRE_44_HEADA 0x0 33#define NV_CIO_CRE_44_HEADB 0x3 34#define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */ 35#define LEGACY_I2C_CRT 0x80 36#define LEGACY_I2C_PANEL 0x81 37#define LEGACY_I2C_TV 0x82 38 39#define EDID1_LEN 128 40 41#define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg) 42#define LOG_OLD_VALUE(x) 43 44#define ROM16(x) le16_to_cpu(*(uint16_t *)&(x)) 45#define ROM32(x) le32_to_cpu(*(uint32_t *)&(x)) 46 47struct init_exec { 48 bool execute; 49 bool repeat; 50}; 51 52static bool nv_cksum(const uint8_t *data, unsigned int length) 53{ 54 /* 55 * There's a few checksums in the BIOS, so here's a generic checking 56 * function. 57 */ 58 int i; 59 uint8_t sum = 0; 60 61 for (i = 0; i < length; i++) 62 sum += data[i]; 63 64 if (sum) 65 return true; 66 67 return false; 68} 69 70static int 71score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable) 72{ 73 if (!(data[0] == 0x55 && data[1] == 0xAA)) { 74 NV_TRACEWARN(dev, "... BIOS signature not found\n"); 75 return 0; 76 } 77 78 if (nv_cksum(data, data[2] * 512)) { 79 NV_TRACEWARN(dev, "... BIOS checksum invalid\n"); 80 /* if a ro image is somewhat bad, it's probably all rubbish */ 81 return writeable ? 2 : 1; 82 } else 83 NV_TRACE(dev, "... appears to be valid\n"); 84 85 return 3; 86} 87 88static void load_vbios_prom(struct drm_device *dev, uint8_t *data) 89{ 90 struct drm_nouveau_private *dev_priv = dev->dev_private; 91 uint32_t pci_nv_20, save_pci_nv_20; 92 int pcir_ptr; 93 int i; 94 95 if (dev_priv->card_type >= NV_50) 96 pci_nv_20 = 0x88050; 97 else 98 pci_nv_20 = NV_PBUS_PCI_NV_20; 99 100 /* enable ROM access */ 101 save_pci_nv_20 = nvReadMC(dev, pci_nv_20); 102 nvWriteMC(dev, pci_nv_20, 103 save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED); 104 105 /* bail if no rom signature */ 106 if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 || 107 nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa) 108 goto out; 109 110 /* additional check (see note below) - read PCI record header */ 111 pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) | 112 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8; 113 if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' || 114 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' || 115 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' || 116 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R') 117 goto out; 118 119 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a 120 * a good read may be obtained by waiting or re-reading (cargocult: 5x) 121 * each byte. we'll hope pramin has something usable instead 122 */ 123 for (i = 0; i < NV_PROM_SIZE; i++) 124 data[i] = nv_rd08(dev, NV_PROM_OFFSET + i); 125 126out: 127 /* disable ROM access */ 128 nvWriteMC(dev, pci_nv_20, 129 save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED); 130} 131 132static void load_vbios_pramin(struct drm_device *dev, uint8_t *data) 133{ 134 struct drm_nouveau_private *dev_priv = dev->dev_private; 135 uint32_t old_bar0_pramin = 0; 136 int i; 137 138 if (dev_priv->card_type >= NV_50) { 139 uint32_t vbios_vram = (nv_rd32(dev, 0x619f04) & ~0xff) << 8; 140 141 if (!vbios_vram) 142 vbios_vram = (nv_rd32(dev, 0x1700) << 16) + 0xf0000; 143 144 old_bar0_pramin = nv_rd32(dev, 0x1700); 145 nv_wr32(dev, 0x1700, vbios_vram >> 16); 146 } 147 148 /* bail if no rom signature */ 149 if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 || 150 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa) 151 goto out; 152 153 for (i = 0; i < NV_PROM_SIZE; i++) 154 data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i); 155 156out: 157 if (dev_priv->card_type >= NV_50) 158 nv_wr32(dev, 0x1700, old_bar0_pramin); 159} 160 161static void load_vbios_pci(struct drm_device *dev, uint8_t *data) 162{ 163 void __iomem *rom = NULL; 164 size_t rom_len; 165 int ret; 166 167 ret = pci_enable_rom(dev->pdev); 168 if (ret) 169 return; 170 171 rom = pci_map_rom(dev->pdev, &rom_len); 172 if (!rom) 173 goto out; 174 memcpy_fromio(data, rom, rom_len); 175 pci_unmap_rom(dev->pdev, rom); 176 177out: 178 pci_disable_rom(dev->pdev); 179} 180 181static void load_vbios_acpi(struct drm_device *dev, uint8_t *data) 182{ 183 int i; 184 int ret; 185 int size = 64 * 1024; 186 187 if (!nouveau_acpi_rom_supported(dev->pdev)) 188 return; 189 190 for (i = 0; i < (size / ROM_BIOS_PAGE); i++) { 191 ret = nouveau_acpi_get_bios_chunk(data, 192 (i * ROM_BIOS_PAGE), 193 ROM_BIOS_PAGE); 194 if (ret <= 0) 195 break; 196 } 197 return; 198} 199 200struct methods { 201 const char desc[8]; 202 void (*loadbios)(struct drm_device *, uint8_t *); 203 const bool rw; 204}; 205 206static struct methods nv04_methods[] = { 207 { "PROM", load_vbios_prom, false }, 208 { "PRAMIN", load_vbios_pramin, true }, 209 { "PCIROM", load_vbios_pci, true }, 210}; 211 212static struct methods nv50_methods[] = { 213 { "ACPI", load_vbios_acpi, true }, 214 { "PRAMIN", load_vbios_pramin, true }, 215 { "PROM", load_vbios_prom, false }, 216 { "PCIROM", load_vbios_pci, true }, 217}; 218 219#define METHODCNT 3 220 221static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data) 222{ 223 struct drm_nouveau_private *dev_priv = dev->dev_private; 224 struct methods *methods; 225 int i; 226 int testscore = 3; 227 int scores[METHODCNT]; 228 229 if (nouveau_vbios) { 230 methods = nv04_methods; 231 for (i = 0; i < METHODCNT; i++) 232 if (!strcasecmp(nouveau_vbios, methods[i].desc)) 233 break; 234 235 if (i < METHODCNT) { 236 NV_INFO(dev, "Attempting to use BIOS image from %s\n", 237 methods[i].desc); 238 239 methods[i].loadbios(dev, data); 240 if (score_vbios(dev, data, methods[i].rw)) 241 return true; 242 } 243 244 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios); 245 } 246 247 if (dev_priv->card_type < NV_50) 248 methods = nv04_methods; 249 else 250 methods = nv50_methods; 251 252 for (i = 0; i < METHODCNT; i++) { 253 NV_TRACE(dev, "Attempting to load BIOS image from %s\n", 254 methods[i].desc); 255 data[0] = data[1] = 0; /* avoid reuse of previous image */ 256 methods[i].loadbios(dev, data); 257 scores[i] = score_vbios(dev, data, methods[i].rw); 258 if (scores[i] == testscore) 259 return true; 260 } 261 262 while (--testscore > 0) { 263 for (i = 0; i < METHODCNT; i++) { 264 if (scores[i] == testscore) { 265 NV_TRACE(dev, "Using BIOS image from %s\n", 266 methods[i].desc); 267 methods[i].loadbios(dev, data); 268 return true; 269 } 270 } 271 } 272 273 NV_ERROR(dev, "No valid BIOS image found\n"); 274 return false; 275} 276 277struct init_tbl_entry { 278 char *name; 279 uint8_t id; 280 /* Return: 281 * > 0: success, length of opcode 282 * 0: success, but abort further parsing of table (INIT_DONE etc) 283 * < 0: failure, table parsing will be aborted 284 */ 285 int (*handler)(struct nvbios *, uint16_t, struct init_exec *); 286}; 287 288struct bit_entry { 289 uint8_t id[2]; 290 uint16_t length; 291 uint16_t offset; 292}; 293 294static int parse_init_table(struct nvbios *, unsigned int, struct init_exec *); 295 296#define MACRO_INDEX_SIZE 2 297#define MACRO_SIZE 8 298#define CONDITION_SIZE 12 299#define IO_FLAG_CONDITION_SIZE 9 300#define IO_CONDITION_SIZE 5 301#define MEM_INIT_SIZE 66 302 303static void still_alive(void) 304{ 305#if 0 306 sync(); 307 msleep(2); 308#endif 309} 310 311static uint32_t 312munge_reg(struct nvbios *bios, uint32_t reg) 313{ 314 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 315 struct dcb_entry *dcbent = bios->display.output; 316 317 if (dev_priv->card_type < NV_50) 318 return reg; 319 320 if (reg & 0x40000000) { 321 BUG_ON(!dcbent); 322 323 reg += (ffs(dcbent->or) - 1) * 0x800; 324 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1)) 325 reg += 0x00000080; 326 } 327 328 reg &= ~0x60000000; 329 return reg; 330} 331 332static int 333valid_reg(struct nvbios *bios, uint32_t reg) 334{ 335 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 336 struct drm_device *dev = bios->dev; 337 338 /* C51 has misaligned regs on purpose. Marvellous */ 339 if (reg & 0x2 || 340 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51)) 341 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg); 342 343 /* warn on C51 regs that haven't been verified accessible in tracing */ 344 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 && 345 reg != 0x130d && reg != 0x1311 && reg != 0x60081d) 346 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n", 347 reg); 348 349 if (reg >= (8*1024*1024)) { 350 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg); 351 return 0; 352 } 353 354 return 1; 355} 356 357static bool 358valid_idx_port(struct nvbios *bios, uint16_t port) 359{ 360 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 361 struct drm_device *dev = bios->dev; 362 363 /* 364 * If adding more ports here, the read/write functions below will need 365 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is 366 * used for the port in question 367 */ 368 if (dev_priv->card_type < NV_50) { 369 if (port == NV_CIO_CRX__COLOR) 370 return true; 371 if (port == NV_VIO_SRX) 372 return true; 373 } else { 374 if (port == NV_CIO_CRX__COLOR) 375 return true; 376 } 377 378 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n", 379 port); 380 381 return false; 382} 383 384static bool 385valid_port(struct nvbios *bios, uint16_t port) 386{ 387 struct drm_device *dev = bios->dev; 388 389 /* 390 * If adding more ports here, the read/write functions below will need 391 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is 392 * used for the port in question 393 */ 394 if (port == NV_VIO_VSE2) 395 return true; 396 397 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port); 398 399 return false; 400} 401 402static uint32_t 403bios_rd32(struct nvbios *bios, uint32_t reg) 404{ 405 uint32_t data; 406 407 reg = munge_reg(bios, reg); 408 if (!valid_reg(bios, reg)) 409 return 0; 410 411 /* 412 * C51 sometimes uses regs with bit0 set in the address. For these 413 * cases there should exist a translation in a BIOS table to an IO 414 * port address which the BIOS uses for accessing the reg 415 * 416 * These only seem to appear for the power control regs to a flat panel, 417 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs 418 * for 0x1308 and 0x1310 are used - hence the mask below. An S3 419 * suspend-resume mmio trace from a C51 will be required to see if this 420 * is true for the power microcode in 0x14.., or whether the direct IO 421 * port access method is needed 422 */ 423 if (reg & 0x1) 424 reg &= ~0x1; 425 426 data = nv_rd32(bios->dev, reg); 427 428 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data); 429 430 return data; 431} 432 433static void 434bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data) 435{ 436 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 437 438 reg = munge_reg(bios, reg); 439 if (!valid_reg(bios, reg)) 440 return; 441 442 /* see note in bios_rd32 */ 443 if (reg & 0x1) 444 reg &= 0xfffffffe; 445 446 LOG_OLD_VALUE(bios_rd32(bios, reg)); 447 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data); 448 449 if (dev_priv->vbios.execute) { 450 still_alive(); 451 nv_wr32(bios->dev, reg, data); 452 } 453} 454 455static uint8_t 456bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index) 457{ 458 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 459 struct drm_device *dev = bios->dev; 460 uint8_t data; 461 462 if (!valid_idx_port(bios, port)) 463 return 0; 464 465 if (dev_priv->card_type < NV_50) { 466 if (port == NV_VIO_SRX) 467 data = NVReadVgaSeq(dev, bios->state.crtchead, index); 468 else /* assume NV_CIO_CRX__COLOR */ 469 data = NVReadVgaCrtc(dev, bios->state.crtchead, index); 470 } else { 471 uint32_t data32; 472 473 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3)); 474 data = (data32 >> ((index & 3) << 3)) & 0xff; 475 } 476 477 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, " 478 "Head: 0x%02X, Data: 0x%02X\n", 479 port, index, bios->state.crtchead, data); 480 return data; 481} 482 483static void 484bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data) 485{ 486 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 487 struct drm_device *dev = bios->dev; 488 489 if (!valid_idx_port(bios, port)) 490 return; 491 492 /* 493 * The current head is maintained in the nvbios member state.crtchead. 494 * We trap changes to CR44 and update the head variable and hence the 495 * register set written. 496 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance 497 * of the write, and to head1 after the write 498 */ 499 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 && 500 data != NV_CIO_CRE_44_HEADB) 501 bios->state.crtchead = 0; 502 503 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index)); 504 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, " 505 "Head: 0x%02X, Data: 0x%02X\n", 506 port, index, bios->state.crtchead, data); 507 508 if (bios->execute && dev_priv->card_type < NV_50) { 509 still_alive(); 510 if (port == NV_VIO_SRX) 511 NVWriteVgaSeq(dev, bios->state.crtchead, index, data); 512 else /* assume NV_CIO_CRX__COLOR */ 513 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data); 514 } else 515 if (bios->execute) { 516 uint32_t data32, shift = (index & 3) << 3; 517 518 still_alive(); 519 520 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3)); 521 data32 &= ~(0xff << shift); 522 data32 |= (data << shift); 523 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32); 524 } 525 526 if (port == NV_CIO_CRX__COLOR && 527 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB) 528 bios->state.crtchead = 1; 529} 530 531static uint8_t 532bios_port_rd(struct nvbios *bios, uint16_t port) 533{ 534 uint8_t data, head = bios->state.crtchead; 535 536 if (!valid_port(bios, port)) 537 return 0; 538 539 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port); 540 541 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n", 542 port, head, data); 543 544 return data; 545} 546 547static void 548bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data) 549{ 550 int head = bios->state.crtchead; 551 552 if (!valid_port(bios, port)) 553 return; 554 555 LOG_OLD_VALUE(bios_port_rd(bios, port)); 556 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n", 557 port, head, data); 558 559 if (!bios->execute) 560 return; 561 562 still_alive(); 563 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data); 564} 565 566static bool 567io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 568{ 569 /* 570 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte 571 * for the CRTC index; 1 byte for the mask to apply to the value 572 * retrieved from the CRTC; 1 byte for the shift right to apply to the 573 * masked CRTC value; 2 bytes for the offset to the flag array, to 574 * which the shifted value is added; 1 byte for the mask applied to the 575 * value read from the flag array; and 1 byte for the value to compare 576 * against the masked byte from the flag table. 577 */ 578 579 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE; 580 uint16_t crtcport = ROM16(bios->data[condptr]); 581 uint8_t crtcindex = bios->data[condptr + 2]; 582 uint8_t mask = bios->data[condptr + 3]; 583 uint8_t shift = bios->data[condptr + 4]; 584 uint16_t flagarray = ROM16(bios->data[condptr + 5]); 585 uint8_t flagarraymask = bios->data[condptr + 7]; 586 uint8_t cmpval = bios->data[condptr + 8]; 587 uint8_t data; 588 589 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 590 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, " 591 "Cmpval: 0x%02X\n", 592 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval); 593 594 data = bios_idxprt_rd(bios, crtcport, crtcindex); 595 596 data = bios->data[flagarray + ((data & mask) >> shift)]; 597 data &= flagarraymask; 598 599 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n", 600 offset, data, cmpval); 601 602 return (data == cmpval); 603} 604 605static bool 606bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 607{ 608 /* 609 * The condition table entry has 4 bytes for the address of the 610 * register to check, 4 bytes for a mask to apply to the register and 611 * 4 for a test comparison value 612 */ 613 614 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE; 615 uint32_t reg = ROM32(bios->data[condptr]); 616 uint32_t mask = ROM32(bios->data[condptr + 4]); 617 uint32_t cmpval = ROM32(bios->data[condptr + 8]); 618 uint32_t data; 619 620 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n", 621 offset, cond, reg, mask); 622 623 data = bios_rd32(bios, reg) & mask; 624 625 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n", 626 offset, data, cmpval); 627 628 return (data == cmpval); 629} 630 631static bool 632io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 633{ 634 /* 635 * The IO condition entry has 2 bytes for the IO port address; 1 byte 636 * for the index to write to io_port; 1 byte for the mask to apply to 637 * the byte read from io_port+1; and 1 byte for the value to compare 638 * against the masked byte. 639 */ 640 641 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE; 642 uint16_t io_port = ROM16(bios->data[condptr]); 643 uint8_t port_index = bios->data[condptr + 2]; 644 uint8_t mask = bios->data[condptr + 3]; 645 uint8_t cmpval = bios->data[condptr + 4]; 646 647 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask; 648 649 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n", 650 offset, data, cmpval); 651 652 return (data == cmpval); 653} 654 655static int 656nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk) 657{ 658 struct drm_nouveau_private *dev_priv = dev->dev_private; 659 uint32_t reg0 = nv_rd32(dev, reg + 0); 660 uint32_t reg1 = nv_rd32(dev, reg + 4); 661 struct nouveau_pll_vals pll; 662 struct pll_lims pll_limits; 663 int ret; 664 665 ret = get_pll_limits(dev, reg, &pll_limits); 666 if (ret) 667 return ret; 668 669 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll); 670 if (!clk) 671 return -ERANGE; 672 673 reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16); 674 reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1; 675 676 if (dev_priv->vbios.execute) { 677 still_alive(); 678 nv_wr32(dev, reg + 4, reg1); 679 nv_wr32(dev, reg + 0, reg0); 680 } 681 682 return 0; 683} 684 685static int 686setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk) 687{ 688 struct drm_device *dev = bios->dev; 689 struct drm_nouveau_private *dev_priv = dev->dev_private; 690 /* clk in kHz */ 691 struct pll_lims pll_lim; 692 struct nouveau_pll_vals pllvals; 693 int ret; 694 695 if (dev_priv->card_type >= NV_50) 696 return nv50_pll_set(dev, reg, clk); 697 698 /* high regs (such as in the mac g5 table) are not -= 4 */ 699 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim); 700 if (ret) 701 return ret; 702 703 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals); 704 if (!clk) 705 return -ERANGE; 706 707 if (bios->execute) { 708 still_alive(); 709 nouveau_hw_setpll(dev, reg, &pllvals); 710 } 711 712 return 0; 713} 714 715static int dcb_entry_idx_from_crtchead(struct drm_device *dev) 716{ 717 struct drm_nouveau_private *dev_priv = dev->dev_private; 718 struct nvbios *bios = &dev_priv->vbios; 719 720 /* 721 * For the results of this function to be correct, CR44 must have been 722 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0, 723 * and the DCB table parsed, before the script calling the function is 724 * run. run_digital_op_script is example of how to do such setup 725 */ 726 727 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0); 728 729 if (dcb_entry > bios->dcb.entries) { 730 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently " 731 "(%02X)\n", dcb_entry); 732 dcb_entry = 0x7f; /* unused / invalid marker */ 733 } 734 735 return dcb_entry; 736} 737 738static int 739read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, int index, struct dcb_i2c_entry *i2c) 740{ 741 uint8_t dcb_i2c_ver = dcb_version, headerlen = 0, entry_len = 4; 742 int i2c_entries = DCB_MAX_NUM_I2C_ENTRIES; 743 int recordoffset = 0, rdofs = 1, wrofs = 0; 744 uint8_t port_type = 0; 745 746 if (!i2ctable) 747 return -EINVAL; 748 749 if (dcb_version >= 0x30) { 750 if (i2ctable[0] != dcb_version) /* necessary? */ 751 NV_WARN(dev, 752 "DCB I2C table version mismatch (%02X vs %02X)\n", 753 i2ctable[0], dcb_version); 754 dcb_i2c_ver = i2ctable[0]; 755 headerlen = i2ctable[1]; 756 if (i2ctable[2] <= DCB_MAX_NUM_I2C_ENTRIES) 757 i2c_entries = i2ctable[2]; 758 else 759 NV_WARN(dev, 760 "DCB I2C table has more entries than indexable " 761 "(%d entries, max %d)\n", i2ctable[2], 762 DCB_MAX_NUM_I2C_ENTRIES); 763 entry_len = i2ctable[3]; 764 /* [4] is i2c_default_indices, read in parse_dcb_table() */ 765 } 766 /* 767 * It's your own fault if you call this function on a DCB 1.1 BIOS -- 768 * the test below is for DCB 1.2 769 */ 770 if (dcb_version < 0x14) { 771 recordoffset = 2; 772 rdofs = 0; 773 wrofs = 1; 774 } 775 776 if (index == 0xf) 777 return 0; 778 if (index >= i2c_entries) { 779 NV_ERROR(dev, "DCB I2C index too big (%d >= %d)\n", 780 index, i2ctable[2]); 781 return -ENOENT; 782 } 783 if (i2ctable[headerlen + entry_len * index + 3] == 0xff) { 784 NV_ERROR(dev, "DCB I2C entry invalid\n"); 785 return -EINVAL; 786 } 787 788 if (dcb_i2c_ver >= 0x30) { 789 port_type = i2ctable[headerlen + recordoffset + 3 + entry_len * index]; 790 791 /* 792 * Fixup for chips using same address offset for read and 793 * write. 794 */ 795 if (port_type == 4) /* seen on C51 */ 796 rdofs = wrofs = 1; 797 if (port_type >= 5) /* G80+ */ 798 rdofs = wrofs = 0; 799 } 800 801 if (dcb_i2c_ver >= 0x40) { 802 if (port_type != 5 && port_type != 6) 803 NV_WARN(dev, "DCB I2C table has port type %d\n", port_type); 804 805 i2c->entry = ROM32(i2ctable[headerlen + recordoffset + entry_len * index]); 806 } 807 808 i2c->port_type = port_type; 809 i2c->read = i2ctable[headerlen + recordoffset + rdofs + entry_len * index]; 810 i2c->write = i2ctable[headerlen + recordoffset + wrofs + entry_len * index]; 811 812 return 0; 813} 814 815static struct nouveau_i2c_chan * 816init_i2c_device_find(struct drm_device *dev, int i2c_index) 817{ 818 struct drm_nouveau_private *dev_priv = dev->dev_private; 819 struct dcb_table *dcb = &dev_priv->vbios.dcb; 820 821 if (i2c_index == 0xff) { 822 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */ 823 int idx = dcb_entry_idx_from_crtchead(dev), shift = 0; 824 int default_indices = dcb->i2c_default_indices; 825 826 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default) 827 shift = 4; 828 829 i2c_index = (default_indices >> shift) & 0xf; 830 } 831 if (i2c_index == 0x80) /* g80+ */ 832 i2c_index = dcb->i2c_default_indices & 0xf; 833 else 834 if (i2c_index == 0x81) 835 i2c_index = (dcb->i2c_default_indices & 0xf0) >> 4; 836 837 if (i2c_index > DCB_MAX_NUM_I2C_ENTRIES) { 838 NV_ERROR(dev, "invalid i2c_index 0x%x\n", i2c_index); 839 return NULL; 840 } 841 842 /* Make sure i2c table entry has been parsed, it may not 843 * have been if this is a bus not referenced by a DCB encoder 844 */ 845 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table, 846 i2c_index, &dcb->i2c[i2c_index]); 847 848 return nouveau_i2c_find(dev, i2c_index); 849} 850 851static uint32_t 852get_tmds_index_reg(struct drm_device *dev, uint8_t mlv) 853{ 854 /* 855 * For mlv < 0x80, it is an index into a table of TMDS base addresses. 856 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by 857 * CR58 for CR57 = 0 to index a table of offsets to the basic 858 * 0x6808b0 address. 859 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by 860 * CR58 for CR57 = 0 to index a table of offsets to the basic 861 * 0x6808b0 address, and then flip the offset by 8. 862 */ 863 864 struct drm_nouveau_private *dev_priv = dev->dev_private; 865 struct nvbios *bios = &dev_priv->vbios; 866 const int pramdac_offset[13] = { 867 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 }; 868 const uint32_t pramdac_table[4] = { 869 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 }; 870 871 if (mlv >= 0x80) { 872 int dcb_entry, dacoffset; 873 874 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */ 875 dcb_entry = dcb_entry_idx_from_crtchead(dev); 876 if (dcb_entry == 0x7f) 877 return 0; 878 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or]; 879 if (mlv == 0x81) 880 dacoffset ^= 8; 881 return 0x6808b0 + dacoffset; 882 } else { 883 if (mlv >= ARRAY_SIZE(pramdac_table)) { 884 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n", 885 mlv); 886 return 0; 887 } 888 return pramdac_table[mlv]; 889 } 890} 891 892static int 893init_io_restrict_prog(struct nvbios *bios, uint16_t offset, 894 struct init_exec *iexec) 895{ 896 /* 897 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2') 898 * 899 * offset (8 bit): opcode 900 * offset + 1 (16 bit): CRTC port 901 * offset + 3 (8 bit): CRTC index 902 * offset + 4 (8 bit): mask 903 * offset + 5 (8 bit): shift 904 * offset + 6 (8 bit): count 905 * offset + 7 (32 bit): register 906 * offset + 11 (32 bit): configuration 1 907 * ... 908 * 909 * Starting at offset + 11 there are "count" 32 bit values. 910 * To find out which value to use read index "CRTC index" on "CRTC 911 * port", AND this value with "mask" and then bit shift right "shift" 912 * bits. Read the appropriate value using this index and write to 913 * "register" 914 */ 915 916 uint16_t crtcport = ROM16(bios->data[offset + 1]); 917 uint8_t crtcindex = bios->data[offset + 3]; 918 uint8_t mask = bios->data[offset + 4]; 919 uint8_t shift = bios->data[offset + 5]; 920 uint8_t count = bios->data[offset + 6]; 921 uint32_t reg = ROM32(bios->data[offset + 7]); 922 uint8_t config; 923 uint32_t configval; 924 int len = 11 + count * 4; 925 926 if (!iexec->execute) 927 return len; 928 929 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 930 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n", 931 offset, crtcport, crtcindex, mask, shift, count, reg); 932 933 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 934 if (config > count) { 935 NV_ERROR(bios->dev, 936 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 937 offset, config, count); 938 return -EINVAL; 939 } 940 941 configval = ROM32(bios->data[offset + 11 + config * 4]); 942 943 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config); 944 945 bios_wr32(bios, reg, configval); 946 947 return len; 948} 949 950static int 951init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 952{ 953 /* 954 * INIT_REPEAT opcode: 0x33 ('3') 955 * 956 * offset (8 bit): opcode 957 * offset + 1 (8 bit): count 958 * 959 * Execute script following this opcode up to INIT_REPEAT_END 960 * "count" times 961 */ 962 963 uint8_t count = bios->data[offset + 1]; 964 uint8_t i; 965 966 /* no iexec->execute check by design */ 967 968 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n", 969 offset, count); 970 971 iexec->repeat = true; 972 973 /* 974 * count - 1, as the script block will execute once when we leave this 975 * opcode -- this is compatible with bios behaviour as: 976 * a) the block is always executed at least once, even if count == 0 977 * b) the bios interpreter skips to the op following INIT_END_REPEAT, 978 * while we don't 979 */ 980 for (i = 0; i < count - 1; i++) 981 parse_init_table(bios, offset + 2, iexec); 982 983 iexec->repeat = false; 984 985 return 2; 986} 987 988static int 989init_io_restrict_pll(struct nvbios *bios, uint16_t offset, 990 struct init_exec *iexec) 991{ 992 /* 993 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4') 994 * 995 * offset (8 bit): opcode 996 * offset + 1 (16 bit): CRTC port 997 * offset + 3 (8 bit): CRTC index 998 * offset + 4 (8 bit): mask 999 * offset + 5 (8 bit): shift 1000 * offset + 6 (8 bit): IO flag condition index 1001 * offset + 7 (8 bit): count 1002 * offset + 8 (32 bit): register 1003 * offset + 12 (16 bit): frequency 1 1004 * ... 1005 * 1006 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz). 1007 * Set PLL register "register" to coefficients for frequency n, 1008 * selected by reading index "CRTC index" of "CRTC port" ANDed with 1009 * "mask" and shifted right by "shift". 1010 * 1011 * If "IO flag condition index" > 0, and condition met, double 1012 * frequency before setting it. 1013 */ 1014 1015 uint16_t crtcport = ROM16(bios->data[offset + 1]); 1016 uint8_t crtcindex = bios->data[offset + 3]; 1017 uint8_t mask = bios->data[offset + 4]; 1018 uint8_t shift = bios->data[offset + 5]; 1019 int8_t io_flag_condition_idx = bios->data[offset + 6]; 1020 uint8_t count = bios->data[offset + 7]; 1021 uint32_t reg = ROM32(bios->data[offset + 8]); 1022 uint8_t config; 1023 uint16_t freq; 1024 int len = 12 + count * 2; 1025 1026 if (!iexec->execute) 1027 return len; 1028 1029 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 1030 "Shift: 0x%02X, IO Flag Condition: 0x%02X, " 1031 "Count: 0x%02X, Reg: 0x%08X\n", 1032 offset, crtcport, crtcindex, mask, shift, 1033 io_flag_condition_idx, count, reg); 1034 1035 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 1036 if (config > count) { 1037 NV_ERROR(bios->dev, 1038 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 1039 offset, config, count); 1040 return -EINVAL; 1041 } 1042 1043 freq = ROM16(bios->data[offset + 12 + config * 2]); 1044 1045 if (io_flag_condition_idx > 0) { 1046 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) { 1047 BIOSLOG(bios, "0x%04X: Condition fulfilled -- " 1048 "frequency doubled\n", offset); 1049 freq *= 2; 1050 } else 1051 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- " 1052 "frequency unchanged\n", offset); 1053 } 1054 1055 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n", 1056 offset, reg, config, freq); 1057 1058 setPLL(bios, reg, freq * 10); 1059 1060 return len; 1061} 1062 1063static int 1064init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1065{ 1066 /* 1067 * INIT_END_REPEAT opcode: 0x36 ('6') 1068 * 1069 * offset (8 bit): opcode 1070 * 1071 * Marks the end of the block for INIT_REPEAT to repeat 1072 */ 1073 1074 /* no iexec->execute check by design */ 1075 1076 /* 1077 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when 1078 * we're not in repeat mode 1079 */ 1080 if (iexec->repeat) 1081 return 0; 1082 1083 return 1; 1084} 1085 1086static int 1087init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1088{ 1089 /* 1090 * INIT_COPY opcode: 0x37 ('7') 1091 * 1092 * offset (8 bit): opcode 1093 * offset + 1 (32 bit): register 1094 * offset + 5 (8 bit): shift 1095 * offset + 6 (8 bit): srcmask 1096 * offset + 7 (16 bit): CRTC port 1097 * offset + 9 (8 bit): CRTC index 1098 * offset + 10 (8 bit): mask 1099 * 1100 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with 1101 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC 1102 * port 1103 */ 1104 1105 uint32_t reg = ROM32(bios->data[offset + 1]); 1106 uint8_t shift = bios->data[offset + 5]; 1107 uint8_t srcmask = bios->data[offset + 6]; 1108 uint16_t crtcport = ROM16(bios->data[offset + 7]); 1109 uint8_t crtcindex = bios->data[offset + 9]; 1110 uint8_t mask = bios->data[offset + 10]; 1111 uint32_t data; 1112 uint8_t crtcdata; 1113 1114 if (!iexec->execute) 1115 return 11; 1116 1117 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, " 1118 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n", 1119 offset, reg, shift, srcmask, crtcport, crtcindex, mask); 1120 1121 data = bios_rd32(bios, reg); 1122 1123 if (shift < 0x80) 1124 data >>= shift; 1125 else 1126 data <<= (0x100 - shift); 1127 1128 data &= srcmask; 1129 1130 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask; 1131 crtcdata |= (uint8_t)data; 1132 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata); 1133 1134 return 11; 1135} 1136 1137static int 1138init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1139{ 1140 /* 1141 * INIT_NOT opcode: 0x38 ('8') 1142 * 1143 * offset (8 bit): opcode 1144 * 1145 * Invert the current execute / no-execute condition (i.e. "else") 1146 */ 1147 if (iexec->execute) 1148 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset); 1149 else 1150 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset); 1151 1152 iexec->execute = !iexec->execute; 1153 return 1; 1154} 1155 1156static int 1157init_io_flag_condition(struct nvbios *bios, uint16_t offset, 1158 struct init_exec *iexec) 1159{ 1160 /* 1161 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9') 1162 * 1163 * offset (8 bit): opcode 1164 * offset + 1 (8 bit): condition number 1165 * 1166 * Check condition "condition number" in the IO flag condition table. 1167 * If condition not met skip subsequent opcodes until condition is 1168 * inverted (INIT_NOT), or we hit INIT_RESUME 1169 */ 1170 1171 uint8_t cond = bios->data[offset + 1]; 1172 1173 if (!iexec->execute) 1174 return 2; 1175 1176 if (io_flag_condition_met(bios, offset, cond)) 1177 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 1178 else { 1179 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 1180 iexec->execute = false; 1181 } 1182 1183 return 2; 1184} 1185 1186static int 1187init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1188{ 1189 /* 1190 * INIT_DP_CONDITION opcode: 0x3A ('') 1191 * 1192 * offset (8 bit): opcode 1193 * offset + 1 (8 bit): "sub" opcode 1194 * offset + 2 (8 bit): unknown 1195 * 1196 */ 1197 1198 struct bit_displayport_encoder_table *dpe = NULL; 1199 struct dcb_entry *dcb = bios->display.output; 1200 struct drm_device *dev = bios->dev; 1201 uint8_t cond = bios->data[offset + 1]; 1202 int dummy; 1203 1204 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond); 1205 1206 if (!iexec->execute) 1207 return 3; 1208 1209 dpe = nouveau_bios_dp_table(dev, dcb, &dummy); 1210 if (!dpe) { 1211 NV_ERROR(dev, "0x%04X: INIT_3A: no encoder table!!\n", offset); 1212 return -EINVAL; 1213 } 1214 1215 switch (cond) { 1216 case 0: 1217 { 1218 struct dcb_connector_table_entry *ent = 1219 &bios->dcb.connector.entry[dcb->connector]; 1220 1221 if (ent->type != DCB_CONNECTOR_eDP) 1222 iexec->execute = false; 1223 } 1224 break; 1225 case 1: 1226 case 2: 1227 if (!(dpe->unknown & cond)) 1228 iexec->execute = false; 1229 break; 1230 case 5: 1231 { 1232 struct nouveau_i2c_chan *auxch; 1233 int ret; 1234 1235 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index); 1236 if (!auxch) 1237 return -ENODEV; 1238 1239 ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1); 1240 if (ret) 1241 return ret; 1242 1243 if (cond & 1) 1244 iexec->execute = false; 1245 } 1246 break; 1247 default: 1248 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond); 1249 break; 1250 } 1251 1252 if (iexec->execute) 1253 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset); 1254 else 1255 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset); 1256 1257 return 3; 1258} 1259 1260static int 1261init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1262{ 1263 /* 1264 * INIT_3B opcode: 0x3B ('') 1265 * 1266 * offset (8 bit): opcode 1267 * offset + 1 (8 bit): crtc index 1268 * 1269 */ 1270 1271 uint8_t or = ffs(bios->display.output->or) - 1; 1272 uint8_t index = bios->data[offset + 1]; 1273 uint8_t data; 1274 1275 if (!iexec->execute) 1276 return 2; 1277 1278 data = bios_idxprt_rd(bios, 0x3d4, index); 1279 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or)); 1280 return 2; 1281} 1282 1283static int 1284init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1285{ 1286 /* 1287 * INIT_3C opcode: 0x3C ('') 1288 * 1289 * offset (8 bit): opcode 1290 * offset + 1 (8 bit): crtc index 1291 * 1292 */ 1293 1294 uint8_t or = ffs(bios->display.output->or) - 1; 1295 uint8_t index = bios->data[offset + 1]; 1296 uint8_t data; 1297 1298 if (!iexec->execute) 1299 return 2; 1300 1301 data = bios_idxprt_rd(bios, 0x3d4, index); 1302 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or)); 1303 return 2; 1304} 1305 1306static int 1307init_idx_addr_latched(struct nvbios *bios, uint16_t offset, 1308 struct init_exec *iexec) 1309{ 1310 /* 1311 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I') 1312 * 1313 * offset (8 bit): opcode 1314 * offset + 1 (32 bit): control register 1315 * offset + 5 (32 bit): data register 1316 * offset + 9 (32 bit): mask 1317 * offset + 13 (32 bit): data 1318 * offset + 17 (8 bit): count 1319 * offset + 18 (8 bit): address 1 1320 * offset + 19 (8 bit): data 1 1321 * ... 1322 * 1323 * For each of "count" address and data pairs, write "data n" to 1324 * "data register", read the current value of "control register", 1325 * and write it back once ANDed with "mask", ORed with "data", 1326 * and ORed with "address n" 1327 */ 1328 1329 uint32_t controlreg = ROM32(bios->data[offset + 1]); 1330 uint32_t datareg = ROM32(bios->data[offset + 5]); 1331 uint32_t mask = ROM32(bios->data[offset + 9]); 1332 uint32_t data = ROM32(bios->data[offset + 13]); 1333 uint8_t count = bios->data[offset + 17]; 1334 int len = 18 + count * 2; 1335 uint32_t value; 1336 int i; 1337 1338 if (!iexec->execute) 1339 return len; 1340 1341 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, " 1342 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n", 1343 offset, controlreg, datareg, mask, data, count); 1344 1345 for (i = 0; i < count; i++) { 1346 uint8_t instaddress = bios->data[offset + 18 + i * 2]; 1347 uint8_t instdata = bios->data[offset + 19 + i * 2]; 1348 1349 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n", 1350 offset, instaddress, instdata); 1351 1352 bios_wr32(bios, datareg, instdata); 1353 value = bios_rd32(bios, controlreg) & mask; 1354 value |= data; 1355 value |= instaddress; 1356 bios_wr32(bios, controlreg, value); 1357 } 1358 1359 return len; 1360} 1361 1362static int 1363init_io_restrict_pll2(struct nvbios *bios, uint16_t offset, 1364 struct init_exec *iexec) 1365{ 1366 /* 1367 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J') 1368 * 1369 * offset (8 bit): opcode 1370 * offset + 1 (16 bit): CRTC port 1371 * offset + 3 (8 bit): CRTC index 1372 * offset + 4 (8 bit): mask 1373 * offset + 5 (8 bit): shift 1374 * offset + 6 (8 bit): count 1375 * offset + 7 (32 bit): register 1376 * offset + 11 (32 bit): frequency 1 1377 * ... 1378 * 1379 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz). 1380 * Set PLL register "register" to coefficients for frequency n, 1381 * selected by reading index "CRTC index" of "CRTC port" ANDed with 1382 * "mask" and shifted right by "shift". 1383 */ 1384 1385 uint16_t crtcport = ROM16(bios->data[offset + 1]); 1386 uint8_t crtcindex = bios->data[offset + 3]; 1387 uint8_t mask = bios->data[offset + 4]; 1388 uint8_t shift = bios->data[offset + 5]; 1389 uint8_t count = bios->data[offset + 6]; 1390 uint32_t reg = ROM32(bios->data[offset + 7]); 1391 int len = 11 + count * 4; 1392 uint8_t config; 1393 uint32_t freq; 1394 1395 if (!iexec->execute) 1396 return len; 1397 1398 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 1399 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n", 1400 offset, crtcport, crtcindex, mask, shift, count, reg); 1401 1402 if (!reg) 1403 return len; 1404 1405 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 1406 if (config > count) { 1407 NV_ERROR(bios->dev, 1408 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 1409 offset, config, count); 1410 return -EINVAL; 1411 } 1412 1413 freq = ROM32(bios->data[offset + 11 + config * 4]); 1414 1415 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n", 1416 offset, reg, config, freq); 1417 1418 setPLL(bios, reg, freq); 1419 1420 return len; 1421} 1422 1423static int 1424init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1425{ 1426 /* 1427 * INIT_PLL2 opcode: 0x4B ('K') 1428 * 1429 * offset (8 bit): opcode 1430 * offset + 1 (32 bit): register 1431 * offset + 5 (32 bit): freq 1432 * 1433 * Set PLL register "register" to coefficients for frequency "freq" 1434 */ 1435 1436 uint32_t reg = ROM32(bios->data[offset + 1]); 1437 uint32_t freq = ROM32(bios->data[offset + 5]); 1438 1439 if (!iexec->execute) 1440 return 9; 1441 1442 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n", 1443 offset, reg, freq); 1444 1445 setPLL(bios, reg, freq); 1446 return 9; 1447} 1448 1449static int 1450init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1451{ 1452 /* 1453 * INIT_I2C_BYTE opcode: 0x4C ('L') 1454 * 1455 * offset (8 bit): opcode 1456 * offset + 1 (8 bit): DCB I2C table entry index 1457 * offset + 2 (8 bit): I2C slave address 1458 * offset + 3 (8 bit): count 1459 * offset + 4 (8 bit): I2C register 1 1460 * offset + 5 (8 bit): mask 1 1461 * offset + 6 (8 bit): data 1 1462 * ... 1463 * 1464 * For each of "count" registers given by "I2C register n" on the device 1465 * addressed by "I2C slave address" on the I2C bus given by 1466 * "DCB I2C table entry index", read the register, AND the result with 1467 * "mask n" and OR it with "data n" before writing it back to the device 1468 */ 1469 1470 uint8_t i2c_index = bios->data[offset + 1]; 1471 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1472 uint8_t count = bios->data[offset + 3]; 1473 struct nouveau_i2c_chan *chan; 1474 int len = 4 + count * 3; 1475 int ret, i; 1476 1477 if (!iexec->execute) 1478 return len; 1479 1480 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1481 "Count: 0x%02X\n", 1482 offset, i2c_index, i2c_address, count); 1483 1484 chan = init_i2c_device_find(bios->dev, i2c_index); 1485 if (!chan) 1486 return -ENODEV; 1487 1488 for (i = 0; i < count; i++) { 1489 uint8_t reg = bios->data[offset + 4 + i * 3]; 1490 uint8_t mask = bios->data[offset + 5 + i * 3]; 1491 uint8_t data = bios->data[offset + 6 + i * 3]; 1492 union i2c_smbus_data val; 1493 1494 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 1495 I2C_SMBUS_READ, reg, 1496 I2C_SMBUS_BYTE_DATA, &val); 1497 if (ret < 0) 1498 return ret; 1499 1500 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, " 1501 "Mask: 0x%02X, Data: 0x%02X\n", 1502 offset, reg, val.byte, mask, data); 1503 1504 if (!bios->execute) 1505 continue; 1506 1507 val.byte &= mask; 1508 val.byte |= data; 1509 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 1510 I2C_SMBUS_WRITE, reg, 1511 I2C_SMBUS_BYTE_DATA, &val); 1512 if (ret < 0) 1513 return ret; 1514 } 1515 1516 return len; 1517} 1518 1519static int 1520init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1521{ 1522 /* 1523 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M') 1524 * 1525 * offset (8 bit): opcode 1526 * offset + 1 (8 bit): DCB I2C table entry index 1527 * offset + 2 (8 bit): I2C slave address 1528 * offset + 3 (8 bit): count 1529 * offset + 4 (8 bit): I2C register 1 1530 * offset + 5 (8 bit): data 1 1531 * ... 1532 * 1533 * For each of "count" registers given by "I2C register n" on the device 1534 * addressed by "I2C slave address" on the I2C bus given by 1535 * "DCB I2C table entry index", set the register to "data n" 1536 */ 1537 1538 uint8_t i2c_index = bios->data[offset + 1]; 1539 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1540 uint8_t count = bios->data[offset + 3]; 1541 struct nouveau_i2c_chan *chan; 1542 int len = 4 + count * 2; 1543 int ret, i; 1544 1545 if (!iexec->execute) 1546 return len; 1547 1548 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1549 "Count: 0x%02X\n", 1550 offset, i2c_index, i2c_address, count); 1551 1552 chan = init_i2c_device_find(bios->dev, i2c_index); 1553 if (!chan) 1554 return -ENODEV; 1555 1556 for (i = 0; i < count; i++) { 1557 uint8_t reg = bios->data[offset + 4 + i * 2]; 1558 union i2c_smbus_data val; 1559 1560 val.byte = bios->data[offset + 5 + i * 2]; 1561 1562 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n", 1563 offset, reg, val.byte); 1564 1565 if (!bios->execute) 1566 continue; 1567 1568 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 1569 I2C_SMBUS_WRITE, reg, 1570 I2C_SMBUS_BYTE_DATA, &val); 1571 if (ret < 0) 1572 return ret; 1573 } 1574 1575 return len; 1576} 1577 1578static int 1579init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1580{ 1581 /* 1582 * INIT_ZM_I2C opcode: 0x4E ('N') 1583 * 1584 * offset (8 bit): opcode 1585 * offset + 1 (8 bit): DCB I2C table entry index 1586 * offset + 2 (8 bit): I2C slave address 1587 * offset + 3 (8 bit): count 1588 * offset + 4 (8 bit): data 1 1589 * ... 1590 * 1591 * Send "count" bytes ("data n") to the device addressed by "I2C slave 1592 * address" on the I2C bus given by "DCB I2C table entry index" 1593 */ 1594 1595 uint8_t i2c_index = bios->data[offset + 1]; 1596 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1597 uint8_t count = bios->data[offset + 3]; 1598 int len = 4 + count; 1599 struct nouveau_i2c_chan *chan; 1600 struct i2c_msg msg; 1601 uint8_t data[256]; 1602 int i; 1603 1604 if (!iexec->execute) 1605 return len; 1606 1607 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1608 "Count: 0x%02X\n", 1609 offset, i2c_index, i2c_address, count); 1610 1611 chan = init_i2c_device_find(bios->dev, i2c_index); 1612 if (!chan) 1613 return -ENODEV; 1614 1615 for (i = 0; i < count; i++) { 1616 data[i] = bios->data[offset + 4 + i]; 1617 1618 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]); 1619 } 1620 1621 if (bios->execute) { 1622 msg.addr = i2c_address; 1623 msg.flags = 0; 1624 msg.len = count; 1625 msg.buf = data; 1626 if (i2c_transfer(&chan->adapter, &msg, 1) != 1) 1627 return -EIO; 1628 } 1629 1630 return len; 1631} 1632 1633static int 1634init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1635{ 1636 /* 1637 * INIT_TMDS opcode: 0x4F ('O') (non-canon name) 1638 * 1639 * offset (8 bit): opcode 1640 * offset + 1 (8 bit): magic lookup value 1641 * offset + 2 (8 bit): TMDS address 1642 * offset + 3 (8 bit): mask 1643 * offset + 4 (8 bit): data 1644 * 1645 * Read the data reg for TMDS address "TMDS address", AND it with mask 1646 * and OR it with data, then write it back 1647 * "magic lookup value" determines which TMDS base address register is 1648 * used -- see get_tmds_index_reg() 1649 */ 1650 1651 uint8_t mlv = bios->data[offset + 1]; 1652 uint32_t tmdsaddr = bios->data[offset + 2]; 1653 uint8_t mask = bios->data[offset + 3]; 1654 uint8_t data = bios->data[offset + 4]; 1655 uint32_t reg, value; 1656 1657 if (!iexec->execute) 1658 return 5; 1659 1660 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, " 1661 "Mask: 0x%02X, Data: 0x%02X\n", 1662 offset, mlv, tmdsaddr, mask, data); 1663 1664 reg = get_tmds_index_reg(bios->dev, mlv); 1665 if (!reg) 1666 return -EINVAL; 1667 1668 bios_wr32(bios, reg, 1669 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE); 1670 value = (bios_rd32(bios, reg + 4) & mask) | data; 1671 bios_wr32(bios, reg + 4, value); 1672 bios_wr32(bios, reg, tmdsaddr); 1673 1674 return 5; 1675} 1676 1677static int 1678init_zm_tmds_group(struct nvbios *bios, uint16_t offset, 1679 struct init_exec *iexec) 1680{ 1681 /* 1682 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name) 1683 * 1684 * offset (8 bit): opcode 1685 * offset + 1 (8 bit): magic lookup value 1686 * offset + 2 (8 bit): count 1687 * offset + 3 (8 bit): addr 1 1688 * offset + 4 (8 bit): data 1 1689 * ... 1690 * 1691 * For each of "count" TMDS address and data pairs write "data n" to 1692 * "addr n". "magic lookup value" determines which TMDS base address 1693 * register is used -- see get_tmds_index_reg() 1694 */ 1695 1696 uint8_t mlv = bios->data[offset + 1]; 1697 uint8_t count = bios->data[offset + 2]; 1698 int len = 3 + count * 2; 1699 uint32_t reg; 1700 int i; 1701 1702 if (!iexec->execute) 1703 return len; 1704 1705 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n", 1706 offset, mlv, count); 1707 1708 reg = get_tmds_index_reg(bios->dev, mlv); 1709 if (!reg) 1710 return -EINVAL; 1711 1712 for (i = 0; i < count; i++) { 1713 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2]; 1714 uint8_t tmdsdata = bios->data[offset + 4 + i * 2]; 1715 1716 bios_wr32(bios, reg + 4, tmdsdata); 1717 bios_wr32(bios, reg, tmdsaddr); 1718 } 1719 1720 return len; 1721} 1722 1723static int 1724init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset, 1725 struct init_exec *iexec) 1726{ 1727 /* 1728 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q') 1729 * 1730 * offset (8 bit): opcode 1731 * offset + 1 (8 bit): CRTC index1 1732 * offset + 2 (8 bit): CRTC index2 1733 * offset + 3 (8 bit): baseaddr 1734 * offset + 4 (8 bit): count 1735 * offset + 5 (8 bit): data 1 1736 * ... 1737 * 1738 * For each of "count" address and data pairs, write "baseaddr + n" to 1739 * "CRTC index1" and "data n" to "CRTC index2" 1740 * Once complete, restore initial value read from "CRTC index1" 1741 */ 1742 uint8_t crtcindex1 = bios->data[offset + 1]; 1743 uint8_t crtcindex2 = bios->data[offset + 2]; 1744 uint8_t baseaddr = bios->data[offset + 3]; 1745 uint8_t count = bios->data[offset + 4]; 1746 int len = 5 + count; 1747 uint8_t oldaddr, data; 1748 int i; 1749 1750 if (!iexec->execute) 1751 return len; 1752 1753 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, " 1754 "BaseAddr: 0x%02X, Count: 0x%02X\n", 1755 offset, crtcindex1, crtcindex2, baseaddr, count); 1756 1757 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1); 1758 1759 for (i = 0; i < count; i++) { 1760 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, 1761 baseaddr + i); 1762 data = bios->data[offset + 5 + i]; 1763 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data); 1764 } 1765 1766 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr); 1767 1768 return len; 1769} 1770 1771static int 1772init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1773{ 1774 /* 1775 * INIT_CR opcode: 0x52 ('R') 1776 * 1777 * offset (8 bit): opcode 1778 * offset + 1 (8 bit): CRTC index 1779 * offset + 2 (8 bit): mask 1780 * offset + 3 (8 bit): data 1781 * 1782 * Assign the value of at "CRTC index" ANDed with mask and ORed with 1783 * data back to "CRTC index" 1784 */ 1785 1786 uint8_t crtcindex = bios->data[offset + 1]; 1787 uint8_t mask = bios->data[offset + 2]; 1788 uint8_t data = bios->data[offset + 3]; 1789 uint8_t value; 1790 1791 if (!iexec->execute) 1792 return 4; 1793 1794 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n", 1795 offset, crtcindex, mask, data); 1796 1797 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask; 1798 value |= data; 1799 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value); 1800 1801 return 4; 1802} 1803 1804static int 1805init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1806{ 1807 /* 1808 * INIT_ZM_CR opcode: 0x53 ('S') 1809 * 1810 * offset (8 bit): opcode 1811 * offset + 1 (8 bit): CRTC index 1812 * offset + 2 (8 bit): value 1813 * 1814 * Assign "value" to CRTC register with index "CRTC index". 1815 */ 1816 1817 uint8_t crtcindex = ROM32(bios->data[offset + 1]); 1818 uint8_t data = bios->data[offset + 2]; 1819 1820 if (!iexec->execute) 1821 return 3; 1822 1823 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data); 1824 1825 return 3; 1826} 1827 1828static int 1829init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1830{ 1831 /* 1832 * INIT_ZM_CR_GROUP opcode: 0x54 ('T') 1833 * 1834 * offset (8 bit): opcode 1835 * offset + 1 (8 bit): count 1836 * offset + 2 (8 bit): CRTC index 1 1837 * offset + 3 (8 bit): value 1 1838 * ... 1839 * 1840 * For "count", assign "value n" to CRTC register with index 1841 * "CRTC index n". 1842 */ 1843 1844 uint8_t count = bios->data[offset + 1]; 1845 int len = 2 + count * 2; 1846 int i; 1847 1848 if (!iexec->execute) 1849 return len; 1850 1851 for (i = 0; i < count; i++) 1852 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec); 1853 1854 return len; 1855} 1856 1857static int 1858init_condition_time(struct nvbios *bios, uint16_t offset, 1859 struct init_exec *iexec) 1860{ 1861 /* 1862 * INIT_CONDITION_TIME opcode: 0x56 ('V') 1863 * 1864 * offset (8 bit): opcode 1865 * offset + 1 (8 bit): condition number 1866 * offset + 2 (8 bit): retries / 50 1867 * 1868 * Check condition "condition number" in the condition table. 1869 * Bios code then sleeps for 2ms if the condition is not met, and 1870 * repeats up to "retries" times, but on one C51 this has proved 1871 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do 1872 * this, and bail after "retries" times, or 2s, whichever is less. 1873 * If still not met after retries, clear execution flag for this table. 1874 */ 1875 1876 uint8_t cond = bios->data[offset + 1]; 1877 uint16_t retries = bios->data[offset + 2] * 50; 1878 unsigned cnt; 1879 1880 if (!iexec->execute) 1881 return 3; 1882 1883 if (retries > 100) 1884 retries = 100; 1885 1886 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n", 1887 offset, cond, retries); 1888 1889 if (!bios->execute) /* avoid 2s delays when "faking" execution */ 1890 retries = 1; 1891 1892 for (cnt = 0; cnt < retries; cnt++) { 1893 if (bios_condition_met(bios, offset, cond)) { 1894 BIOSLOG(bios, "0x%04X: Condition met, continuing\n", 1895 offset); 1896 break; 1897 } else { 1898 BIOSLOG(bios, "0x%04X: " 1899 "Condition not met, sleeping for 20ms\n", 1900 offset); 1901 msleep(20); 1902 } 1903 } 1904 1905 if (!bios_condition_met(bios, offset, cond)) { 1906 NV_WARN(bios->dev, 1907 "0x%04X: Condition still not met after %dms, " 1908 "skipping following opcodes\n", offset, 20 * retries); 1909 iexec->execute = false; 1910 } 1911 1912 return 3; 1913} 1914 1915static int 1916init_zm_reg_sequence(struct nvbios *bios, uint16_t offset, 1917 struct init_exec *iexec) 1918{ 1919 /* 1920 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X') 1921 * 1922 * offset (8 bit): opcode 1923 * offset + 1 (32 bit): base register 1924 * offset + 5 (8 bit): count 1925 * offset + 6 (32 bit): value 1 1926 * ... 1927 * 1928 * Starting at offset + 6 there are "count" 32 bit values. 1929 * For "count" iterations set "base register" + 4 * current_iteration 1930 * to "value current_iteration" 1931 */ 1932 1933 uint32_t basereg = ROM32(bios->data[offset + 1]); 1934 uint32_t count = bios->data[offset + 5]; 1935 int len = 6 + count * 4; 1936 int i; 1937 1938 if (!iexec->execute) 1939 return len; 1940 1941 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n", 1942 offset, basereg, count); 1943 1944 for (i = 0; i < count; i++) { 1945 uint32_t reg = basereg + i * 4; 1946 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]); 1947 1948 bios_wr32(bios, reg, data); 1949 } 1950 1951 return len; 1952} 1953 1954static int 1955init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1956{ 1957 /* 1958 * INIT_SUB_DIRECT opcode: 0x5B ('[') 1959 * 1960 * offset (8 bit): opcode 1961 * offset + 1 (16 bit): subroutine offset (in bios) 1962 * 1963 * Calls a subroutine that will execute commands until INIT_DONE 1964 * is found. 1965 */ 1966 1967 uint16_t sub_offset = ROM16(bios->data[offset + 1]); 1968 1969 if (!iexec->execute) 1970 return 3; 1971 1972 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n", 1973 offset, sub_offset); 1974 1975 parse_init_table(bios, sub_offset, iexec); 1976 1977 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset); 1978 1979 return 3; 1980} 1981 1982static int 1983init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1984{ 1985 /* 1986 * INIT_COPY_NV_REG opcode: 0x5F ('_') 1987 * 1988 * offset (8 bit): opcode 1989 * offset + 1 (32 bit): src reg 1990 * offset + 5 (8 bit): shift 1991 * offset + 6 (32 bit): src mask 1992 * offset + 10 (32 bit): xor 1993 * offset + 14 (32 bit): dst reg 1994 * offset + 18 (32 bit): dst mask 1995 * 1996 * Shift REGVAL("src reg") right by (signed) "shift", AND result with 1997 * "src mask", then XOR with "xor". Write this OR'd with 1998 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg" 1999 */ 2000 2001 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1])); 2002 uint8_t shift = bios->data[offset + 5]; 2003 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6])); 2004 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10])); 2005 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14])); 2006 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18])); 2007 uint32_t srcvalue, dstvalue; 2008 2009 if (!iexec->execute) 2010 return 22; 2011 2012 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, " 2013 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n", 2014 offset, srcreg, shift, srcmask, xor, dstreg, dstmask); 2015 2016 srcvalue = bios_rd32(bios, srcreg); 2017 2018 if (shift < 0x80) 2019 srcvalue >>= shift; 2020 else 2021 srcvalue <<= (0x100 - shift); 2022 2023 srcvalue = (srcvalue & srcmask) ^ xor; 2024 2025 dstvalue = bios_rd32(bios, dstreg) & dstmask; 2026 2027 bios_wr32(bios, dstreg, dstvalue | srcvalue); 2028 2029 return 22; 2030} 2031 2032static int 2033init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2034{ 2035 /* 2036 * INIT_ZM_INDEX_IO opcode: 0x62 ('b') 2037 * 2038 * offset (8 bit): opcode 2039 * offset + 1 (16 bit): CRTC port 2040 * offset + 3 (8 bit): CRTC index 2041 * offset + 4 (8 bit): data 2042 * 2043 * Write "data" to index "CRTC index" of "CRTC port" 2044 */ 2045 uint16_t crtcport = ROM16(bios->data[offset + 1]); 2046 uint8_t crtcindex = bios->data[offset + 3]; 2047 uint8_t data = bios->data[offset + 4]; 2048 2049 if (!iexec->execute) 2050 return 5; 2051 2052 bios_idxprt_wr(bios, crtcport, crtcindex, data); 2053 2054 return 5; 2055} 2056 2057static int 2058init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2059{ 2060 /* 2061 * INIT_COMPUTE_MEM opcode: 0x63 ('c') 2062 * 2063 * offset (8 bit): opcode 2064 * 2065 * This opcode is meant to set NV_PFB_CFG0 (0x100200) appropriately so 2066 * that the hardware can correctly calculate how much VRAM it has 2067 * (and subsequently report that value in NV_PFB_CSTATUS (0x10020C)) 2068 * 2069 * The implementation of this opcode in general consists of two parts: 2070 * 1) determination of the memory bus width 2071 * 2) determination of how many of the card's RAM pads have ICs attached 2072 * 2073 * 1) is done by a cunning combination of writes to offsets 0x1c and 2074 * 0x3c in the framebuffer, and seeing whether the written values are 2075 * read back correctly. This then affects bits 4-7 of NV_PFB_CFG0 2076 * 2077 * 2) is done by a cunning combination of writes to an offset slightly 2078 * less than the maximum memory reported by NV_PFB_CSTATUS, then seeing 2079 * if the test pattern can be read back. This then affects bits 12-15 of 2080 * NV_PFB_CFG0 2081 * 2082 * In this context a "cunning combination" may include multiple reads 2083 * and writes to varying locations, often alternating the test pattern 2084 * and 0, doubtless to make sure buffers are filled, residual charges 2085 * on tracks are removed etc. 2086 * 2087 * Unfortunately, the "cunning combination"s mentioned above, and the 2088 * changes to the bits in NV_PFB_CFG0 differ with nearly every bios 2089 * trace I have. 2090 * 2091 * Therefore, we cheat and assume the value of NV_PFB_CFG0 with which 2092 * we started was correct, and use that instead 2093 */ 2094 2095 /* no iexec->execute check by design */ 2096 2097 /* 2098 * This appears to be a NOP on G8x chipsets, both io logs of the VBIOS 2099 * and kmmio traces of the binary driver POSTing the card show nothing 2100 * being done for this opcode. why is it still listed in the table?! 2101 */ 2102 2103 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2104 2105 if (dev_priv->card_type >= NV_40) 2106 return 1; 2107 2108 /* 2109 * On every card I've seen, this step gets done for us earlier in 2110 * the init scripts 2111 uint8_t crdata = bios_idxprt_rd(dev, NV_VIO_SRX, 0x01); 2112 bios_idxprt_wr(dev, NV_VIO_SRX, 0x01, crdata | 0x20); 2113 */ 2114 2115 /* 2116 * This also has probably been done in the scripts, but an mmio trace of 2117 * s3 resume shows nvidia doing it anyway (unlike the NV_VIO_SRX write) 2118 */ 2119 bios_wr32(bios, NV_PFB_REFCTRL, NV_PFB_REFCTRL_VALID_1); 2120 2121 /* write back the saved configuration value */ 2122 bios_wr32(bios, NV_PFB_CFG0, bios->state.saved_nv_pfb_cfg0); 2123 2124 return 1; 2125} 2126 2127static int 2128init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2129{ 2130 /* 2131 * INIT_RESET opcode: 0x65 ('e') 2132 * 2133 * offset (8 bit): opcode 2134 * offset + 1 (32 bit): register 2135 * offset + 5 (32 bit): value1 2136 * offset + 9 (32 bit): value2 2137 * 2138 * Assign "value1" to "register", then assign "value2" to "register" 2139 */ 2140 2141 uint32_t reg = ROM32(bios->data[offset + 1]); 2142 uint32_t value1 = ROM32(bios->data[offset + 5]); 2143 uint32_t value2 = ROM32(bios->data[offset + 9]); 2144 uint32_t pci_nv_19, pci_nv_20; 2145 2146 /* no iexec->execute check by design */ 2147 2148 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19); 2149 bios_wr32(bios, NV_PBUS_PCI_NV_19, 0); 2150 bios_wr32(bios, reg, value1); 2151 2152 udelay(10); 2153 2154 bios_wr32(bios, reg, value2); 2155 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19); 2156 2157 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20); 2158 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */ 2159 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20); 2160 2161 return 13; 2162} 2163 2164static int 2165init_configure_mem(struct nvbios *bios, uint16_t offset, 2166 struct init_exec *iexec) 2167{ 2168 /* 2169 * INIT_CONFIGURE_MEM opcode: 0x66 ('f') 2170 * 2171 * offset (8 bit): opcode 2172 * 2173 * Equivalent to INIT_DONE on bios version 3 or greater. 2174 * For early bios versions, sets up the memory registers, using values 2175 * taken from the memory init table 2176 */ 2177 2178 /* no iexec->execute check by design */ 2179 2180 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4); 2181 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6; 2182 uint32_t reg, data; 2183 2184 if (bios->major_version > 2) 2185 return -ENODEV; 2186 2187 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd( 2188 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20); 2189 2190 if (bios->data[meminitoffs] & 1) 2191 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr; 2192 2193 for (reg = ROM32(bios->data[seqtbloffs]); 2194 reg != 0xffffffff; 2195 reg = ROM32(bios->data[seqtbloffs += 4])) { 2196 2197 switch (reg) { 2198 case NV_PFB_PRE: 2199 data = NV_PFB_PRE_CMD_PRECHARGE; 2200 break; 2201 case NV_PFB_PAD: 2202 data = NV_PFB_PAD_CKE_NORMAL; 2203 break; 2204 case NV_PFB_REF: 2205 data = NV_PFB_REF_CMD_REFRESH; 2206 break; 2207 default: 2208 data = ROM32(bios->data[meminitdata]); 2209 meminitdata += 4; 2210 if (data == 0xffffffff) 2211 continue; 2212 } 2213 2214 bios_wr32(bios, reg, data); 2215 } 2216 2217 return 1; 2218} 2219 2220static int 2221init_configure_clk(struct nvbios *bios, uint16_t offset, 2222 struct init_exec *iexec) 2223{ 2224 /* 2225 * INIT_CONFIGURE_CLK opcode: 0x67 ('g') 2226 * 2227 * offset (8 bit): opcode 2228 * 2229 * Equivalent to INIT_DONE on bios version 3 or greater. 2230 * For early bios versions, sets up the NVClk and MClk PLLs, using 2231 * values taken from the memory init table 2232 */ 2233 2234 /* no iexec->execute check by design */ 2235 2236 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4); 2237 int clock; 2238 2239 if (bios->major_version > 2) 2240 return -ENODEV; 2241 2242 clock = ROM16(bios->data[meminitoffs + 4]) * 10; 2243 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock); 2244 2245 clock = ROM16(bios->data[meminitoffs + 2]) * 10; 2246 if (bios->data[meminitoffs] & 1) /* DDR */ 2247 clock *= 2; 2248 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock); 2249 2250 return 1; 2251} 2252 2253static int 2254init_configure_preinit(struct nvbios *bios, uint16_t offset, 2255 struct init_exec *iexec) 2256{ 2257 /* 2258 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h') 2259 * 2260 * offset (8 bit): opcode 2261 * 2262 * Equivalent to INIT_DONE on bios version 3 or greater. 2263 * For early bios versions, does early init, loading ram and crystal 2264 * configuration from straps into CR3C 2265 */ 2266 2267 /* no iexec->execute check by design */ 2268 2269 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0); 2270 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & (1 << 6)); 2271 2272 if (bios->major_version > 2) 2273 return -ENODEV; 2274 2275 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, 2276 NV_CIO_CRE_SCRATCH4__INDEX, cr3c); 2277 2278 return 1; 2279} 2280 2281static int 2282init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2283{ 2284 /* 2285 * INIT_IO opcode: 0x69 ('i') 2286 * 2287 * offset (8 bit): opcode 2288 * offset + 1 (16 bit): CRTC port 2289 * offset + 3 (8 bit): mask 2290 * offset + 4 (8 bit): data 2291 * 2292 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port" 2293 */ 2294 2295 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2296 uint16_t crtcport = ROM16(bios->data[offset + 1]); 2297 uint8_t mask = bios->data[offset + 3]; 2298 uint8_t data = bios->data[offset + 4]; 2299 2300 if (!iexec->execute) 2301 return 5; 2302 2303 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n", 2304 offset, crtcport, mask, data); 2305 2306 /* 2307 * I have no idea what this does, but NVIDIA do this magic sequence 2308 * in the places where this INIT_IO happens.. 2309 */ 2310 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) { 2311 int i; 2312 2313 bios_wr32(bios, 0x614100, (bios_rd32( 2314 bios, 0x614100) & 0x0fffffff) | 0x00800000); 2315 2316 bios_wr32(bios, 0x00e18c, bios_rd32( 2317 bios, 0x00e18c) | 0x00020000); 2318 2319 bios_wr32(bios, 0x614900, (bios_rd32( 2320 bios, 0x614900) & 0x0fffffff) | 0x00800000); 2321 2322 bios_wr32(bios, 0x000200, bios_rd32( 2323 bios, 0x000200) & ~0x40000000); 2324 2325 mdelay(10); 2326 2327 bios_wr32(bios, 0x00e18c, bios_rd32( 2328 bios, 0x00e18c) & ~0x00020000); 2329 2330 bios_wr32(bios, 0x000200, bios_rd32( 2331 bios, 0x000200) | 0x40000000); 2332 2333 bios_wr32(bios, 0x614100, 0x00800018); 2334 bios_wr32(bios, 0x614900, 0x00800018); 2335 2336 mdelay(10); 2337 2338 bios_wr32(bios, 0x614100, 0x10000018); 2339 bios_wr32(bios, 0x614900, 0x10000018); 2340 2341 for (i = 0; i < 3; i++) 2342 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32( 2343 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0); 2344 2345 for (i = 0; i < 2; i++) 2346 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32( 2347 bios, 0x614300 + (i*0x800)) & 0xfffff0f0); 2348 2349 for (i = 0; i < 3; i++) 2350 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32( 2351 bios, 0x614380 + (i*0x800)) & 0xfffff0f0); 2352 2353 for (i = 0; i < 2; i++) 2354 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32( 2355 bios, 0x614200 + (i*0x800)) & 0xfffffff0); 2356 2357 for (i = 0; i < 2; i++) 2358 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32( 2359 bios, 0x614108 + (i*0x800)) & 0x0fffffff); 2360 return 5; 2361 } 2362 2363 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) | 2364 data); 2365 return 5; 2366} 2367 2368static int 2369init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2370{ 2371 /* 2372 * INIT_SUB opcode: 0x6B ('k') 2373 * 2374 * offset (8 bit): opcode 2375 * offset + 1 (8 bit): script number 2376 * 2377 * Execute script number "script number", as a subroutine 2378 */ 2379 2380 uint8_t sub = bios->data[offset + 1]; 2381 2382 if (!iexec->execute) 2383 return 2; 2384 2385 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub); 2386 2387 parse_init_table(bios, 2388 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]), 2389 iexec); 2390 2391 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub); 2392 2393 return 2; 2394} 2395 2396static int 2397init_ram_condition(struct nvbios *bios, uint16_t offset, 2398 struct init_exec *iexec) 2399{ 2400 /* 2401 * INIT_RAM_CONDITION opcode: 0x6D ('m') 2402 * 2403 * offset (8 bit): opcode 2404 * offset + 1 (8 bit): mask 2405 * offset + 2 (8 bit): cmpval 2406 * 2407 * Test if (NV_PFB_BOOT_0 & "mask") equals "cmpval". 2408 * If condition not met skip subsequent opcodes until condition is 2409 * inverted (INIT_NOT), or we hit INIT_RESUME 2410 */ 2411 2412 uint8_t mask = bios->data[offset + 1]; 2413 uint8_t cmpval = bios->data[offset + 2]; 2414 uint8_t data; 2415 2416 if (!iexec->execute) 2417 return 3; 2418 2419 data = bios_rd32(bios, NV_PFB_BOOT_0) & mask; 2420 2421 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n", 2422 offset, data, cmpval); 2423 2424 if (data == cmpval) 2425 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 2426 else { 2427 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 2428 iexec->execute = false; 2429 } 2430 2431 return 3; 2432} 2433 2434static int 2435init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2436{ 2437 /* 2438 * INIT_NV_REG opcode: 0x6E ('n') 2439 * 2440 * offset (8 bit): opcode 2441 * offset + 1 (32 bit): register 2442 * offset + 5 (32 bit): mask 2443 * offset + 9 (32 bit): data 2444 * 2445 * Assign ((REGVAL("register") & "mask") | "data") to "register" 2446 */ 2447 2448 uint32_t reg = ROM32(bios->data[offset + 1]); 2449 uint32_t mask = ROM32(bios->data[offset + 5]); 2450 uint32_t data = ROM32(bios->data[offset + 9]); 2451 2452 if (!iexec->execute) 2453 return 13; 2454 2455 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n", 2456 offset, reg, mask, data); 2457 2458 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data); 2459 2460 return 13; 2461} 2462 2463static int 2464init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2465{ 2466 /* 2467 * INIT_MACRO opcode: 0x6F ('o') 2468 * 2469 * offset (8 bit): opcode 2470 * offset + 1 (8 bit): macro number 2471 * 2472 * Look up macro index "macro number" in the macro index table. 2473 * The macro index table entry has 1 byte for the index in the macro 2474 * table, and 1 byte for the number of times to repeat the macro. 2475 * The macro table entry has 4 bytes for the register address and 2476 * 4 bytes for the value to write to that register 2477 */ 2478 2479 uint8_t macro_index_tbl_idx = bios->data[offset + 1]; 2480 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE); 2481 uint8_t macro_tbl_idx = bios->data[tmp]; 2482 uint8_t count = bios->data[tmp + 1]; 2483 uint32_t reg, data; 2484 int i; 2485 2486 if (!iexec->execute) 2487 return 2; 2488 2489 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, " 2490 "Count: 0x%02X\n", 2491 offset, macro_index_tbl_idx, macro_tbl_idx, count); 2492 2493 for (i = 0; i < count; i++) { 2494 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE; 2495 2496 reg = ROM32(bios->data[macroentryptr]); 2497 data = ROM32(bios->data[macroentryptr + 4]); 2498 2499 bios_wr32(bios, reg, data); 2500 } 2501 2502 return 2; 2503} 2504 2505static int 2506init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2507{ 2508 /* 2509 * INIT_DONE opcode: 0x71 ('q') 2510 * 2511 * offset (8 bit): opcode 2512 * 2513 * End the current script 2514 */ 2515 2516 /* mild retval abuse to stop parsing this table */ 2517 return 0; 2518} 2519 2520static int 2521init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2522{ 2523 /* 2524 * INIT_RESUME opcode: 0x72 ('r') 2525 * 2526 * offset (8 bit): opcode 2527 * 2528 * End the current execute / no-execute condition 2529 */ 2530 2531 if (iexec->execute) 2532 return 1; 2533 2534 iexec->execute = true; 2535 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset); 2536 2537 return 1; 2538} 2539 2540static int 2541init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2542{ 2543 /* 2544 * INIT_TIME opcode: 0x74 ('t') 2545 * 2546 * offset (8 bit): opcode 2547 * offset + 1 (16 bit): time 2548 * 2549 * Sleep for "time" microseconds. 2550 */ 2551 2552 unsigned time = ROM16(bios->data[offset + 1]); 2553 2554 if (!iexec->execute) 2555 return 3; 2556 2557 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n", 2558 offset, time); 2559 2560 if (time < 1000) 2561 udelay(time); 2562 else 2563 msleep((time + 900) / 1000); 2564 2565 return 3; 2566} 2567 2568static int 2569init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2570{ 2571 /* 2572 * INIT_CONDITION opcode: 0x75 ('u') 2573 * 2574 * offset (8 bit): opcode 2575 * offset + 1 (8 bit): condition number 2576 * 2577 * Check condition "condition number" in the condition table. 2578 * If condition not met skip subsequent opcodes until condition is 2579 * inverted (INIT_NOT), or we hit INIT_RESUME 2580 */ 2581 2582 uint8_t cond = bios->data[offset + 1]; 2583 2584 if (!iexec->execute) 2585 return 2; 2586 2587 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond); 2588 2589 if (bios_condition_met(bios, offset, cond)) 2590 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 2591 else { 2592 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 2593 iexec->execute = false; 2594 } 2595 2596 return 2; 2597} 2598 2599static int 2600init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2601{ 2602 /* 2603 * INIT_IO_CONDITION opcode: 0x76 2604 * 2605 * offset (8 bit): opcode 2606 * offset + 1 (8 bit): condition number 2607 * 2608 * Check condition "condition number" in the io condition table. 2609 * If condition not met skip subsequent opcodes until condition is 2610 * inverted (INIT_NOT), or we hit INIT_RESUME 2611 */ 2612 2613 uint8_t cond = bios->data[offset + 1]; 2614 2615 if (!iexec->execute) 2616 return 2; 2617 2618 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond); 2619 2620 if (io_condition_met(bios, offset, cond)) 2621 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 2622 else { 2623 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 2624 iexec->execute = false; 2625 } 2626 2627 return 2; 2628} 2629 2630static int 2631init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2632{ 2633 /* 2634 * INIT_INDEX_IO opcode: 0x78 ('x') 2635 * 2636 * offset (8 bit): opcode 2637 * offset + 1 (16 bit): CRTC port 2638 * offset + 3 (8 bit): CRTC index 2639 * offset + 4 (8 bit): mask 2640 * offset + 5 (8 bit): data 2641 * 2642 * Read value at index "CRTC index" on "CRTC port", AND with "mask", 2643 * OR with "data", write-back 2644 */ 2645 2646 uint16_t crtcport = ROM16(bios->data[offset + 1]); 2647 uint8_t crtcindex = bios->data[offset + 3]; 2648 uint8_t mask = bios->data[offset + 4]; 2649 uint8_t data = bios->data[offset + 5]; 2650 uint8_t value; 2651 2652 if (!iexec->execute) 2653 return 6; 2654 2655 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 2656 "Data: 0x%02X\n", 2657 offset, crtcport, crtcindex, mask, data); 2658 2659 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data; 2660 bios_idxprt_wr(bios, crtcport, crtcindex, value); 2661 2662 return 6; 2663} 2664 2665static int 2666init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2667{ 2668 /* 2669 * INIT_PLL opcode: 0x79 ('y') 2670 * 2671 * offset (8 bit): opcode 2672 * offset + 1 (32 bit): register 2673 * offset + 5 (16 bit): freq 2674 * 2675 * Set PLL register "register" to coefficients for frequency (10kHz) 2676 * "freq" 2677 */ 2678 2679 uint32_t reg = ROM32(bios->data[offset + 1]); 2680 uint16_t freq = ROM16(bios->data[offset + 5]); 2681 2682 if (!iexec->execute) 2683 return 7; 2684 2685 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq); 2686 2687 setPLL(bios, reg, freq * 10); 2688 2689 return 7; 2690} 2691 2692static int 2693init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2694{ 2695 /* 2696 * INIT_ZM_REG opcode: 0x7A ('z') 2697 * 2698 * offset (8 bit): opcode 2699 * offset + 1 (32 bit): register 2700 * offset + 5 (32 bit): value 2701 * 2702 * Assign "value" to "register" 2703 */ 2704 2705 uint32_t reg = ROM32(bios->data[offset + 1]); 2706 uint32_t value = ROM32(bios->data[offset + 5]); 2707 2708 if (!iexec->execute) 2709 return 9; 2710 2711 if (reg == 0x000200) 2712 value |= 1; 2713 2714 bios_wr32(bios, reg, value); 2715 2716 return 9; 2717} 2718 2719static int 2720init_ram_restrict_pll(struct nvbios *bios, uint16_t offset, 2721 struct init_exec *iexec) 2722{ 2723 /* 2724 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('') 2725 * 2726 * offset (8 bit): opcode 2727 * offset + 1 (8 bit): PLL type 2728 * offset + 2 (32 bit): frequency 0 2729 * 2730 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at 2731 * ram_restrict_table_ptr. The value read from there is used to select 2732 * a frequency from the table starting at 'frequency 0' to be 2733 * programmed into the PLL corresponding to 'type'. 2734 * 2735 * The PLL limits table on cards using this opcode has a mapping of 2736 * 'type' to the relevant registers. 2737 */ 2738 2739 struct drm_device *dev = bios->dev; 2740 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2; 2741 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap]; 2742 uint8_t type = bios->data[offset + 1]; 2743 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]); 2744 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry; 2745 int len = 2 + bios->ram_restrict_group_count * 4; 2746 int i; 2747 2748 if (!iexec->execute) 2749 return len; 2750 2751 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) { 2752 NV_ERROR(dev, "PLL limits table not version 3.x\n"); 2753 return len; /* deliberate, allow default clocks to remain */ 2754 } 2755 2756 entry = pll_limits + pll_limits[1]; 2757 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) { 2758 if (entry[0] == type) { 2759 uint32_t reg = ROM32(entry[3]); 2760 2761 BIOSLOG(bios, "0x%04X: " 2762 "Type %02x Reg 0x%08x Freq %dKHz\n", 2763 offset, type, reg, freq); 2764 2765 setPLL(bios, reg, freq); 2766 return len; 2767 } 2768 } 2769 2770 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type); 2771 return len; 2772} 2773 2774static int 2775init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2776{ 2777 /* 2778 * INIT_8C opcode: 0x8C ('') 2779 * 2780 * NOP so far.... 2781 * 2782 */ 2783 2784 return 1; 2785} 2786 2787static int 2788init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2789{ 2790 /* 2791 * INIT_8D opcode: 0x8D ('') 2792 * 2793 * NOP so far.... 2794 * 2795 */ 2796 2797 return 1; 2798} 2799 2800static int 2801init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2802{ 2803 /* 2804 * INIT_GPIO opcode: 0x8E ('') 2805 * 2806 * offset (8 bit): opcode 2807 * 2808 * Loop over all entries in the DCB GPIO table, and initialise 2809 * each GPIO according to various values listed in each entry 2810 */ 2811 2812 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2813 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c }; 2814 int i; 2815 2816 if (dev_priv->card_type != NV_50) { 2817 NV_ERROR(bios->dev, "INIT_GPIO on unsupported chipset\n"); 2818 return -ENODEV; 2819 } 2820 2821 if (!iexec->execute) 2822 return 1; 2823 2824 for (i = 0; i < bios->dcb.gpio.entries; i++) { 2825 struct dcb_gpio_entry *gpio = &bios->dcb.gpio.entry[i]; 2826 uint32_t r, s, v; 2827 2828 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, gpio->entry); 2829 2830 BIOSLOG(bios, "0x%04X: set gpio 0x%02x, state %d\n", 2831 offset, gpio->tag, gpio->state_default); 2832 if (bios->execute) 2833 nv50_gpio_set(bios->dev, gpio->tag, gpio->state_default); 2834 2835 /* The NVIDIA binary driver doesn't appear to actually do 2836 * any of this, my VBIOS does however. 2837 */ 2838 /* Not a clue, needs de-magicing */ 2839 r = nv50_gpio_ctl[gpio->line >> 4]; 2840 s = (gpio->line & 0x0f); 2841 v = bios_rd32(bios, r) & ~(0x00010001 << s); 2842 switch ((gpio->entry & 0x06000000) >> 25) { 2843 case 1: 2844 v |= (0x00000001 << s); 2845 break; 2846 case 2: 2847 v |= (0x00010000 << s); 2848 break; 2849 default: 2850 break; 2851 } 2852 bios_wr32(bios, r, v); 2853 } 2854 2855 return 1; 2856} 2857 2858static int 2859init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset, 2860 struct init_exec *iexec) 2861{ 2862 /* 2863 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('') 2864 * 2865 * offset (8 bit): opcode 2866 * offset + 1 (32 bit): reg 2867 * offset + 5 (8 bit): regincrement 2868 * offset + 6 (8 bit): count 2869 * offset + 7 (32 bit): value 1,1 2870 * ... 2871 * 2872 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at 2873 * ram_restrict_table_ptr. The value read from here is 'n', and 2874 * "value 1,n" gets written to "reg". This repeats "count" times and on 2875 * each iteration 'm', "reg" increases by "regincrement" and 2876 * "value m,n" is used. The extent of n is limited by a number read 2877 * from the 'M' BIT table, herein called "blocklen" 2878 */ 2879 2880 uint32_t reg = ROM32(bios->data[offset + 1]); 2881 uint8_t regincrement = bios->data[offset + 5]; 2882 uint8_t count = bios->data[offset + 6]; 2883 uint32_t strap_ramcfg, data; 2884 /* previously set by 'M' BIT table */ 2885 uint16_t blocklen = bios->ram_restrict_group_count * 4; 2886 int len = 7 + count * blocklen; 2887 uint8_t index; 2888 int i; 2889 2890 2891 if (!iexec->execute) 2892 return len; 2893 2894 if (!blocklen) { 2895 NV_ERROR(bios->dev, 2896 "0x%04X: Zero block length - has the M table " 2897 "been parsed?\n", offset); 2898 return -EINVAL; 2899 } 2900 2901 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf; 2902 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg]; 2903 2904 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, " 2905 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n", 2906 offset, reg, regincrement, count, strap_ramcfg, index); 2907 2908 for (i = 0; i < count; i++) { 2909 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]); 2910 2911 bios_wr32(bios, reg, data); 2912 2913 reg += regincrement; 2914 } 2915 2916 return len; 2917} 2918 2919static int 2920init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2921{ 2922 /* 2923 * INIT_COPY_ZM_REG opcode: 0x90 ('') 2924 * 2925 * offset (8 bit): opcode 2926 * offset + 1 (32 bit): src reg 2927 * offset + 5 (32 bit): dst reg 2928 * 2929 * Put contents of "src reg" into "dst reg" 2930 */ 2931 2932 uint32_t srcreg = ROM32(bios->data[offset + 1]); 2933 uint32_t dstreg = ROM32(bios->data[offset + 5]); 2934 2935 if (!iexec->execute) 2936 return 9; 2937 2938 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg)); 2939 2940 return 9; 2941} 2942 2943static int 2944init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset, 2945 struct init_exec *iexec) 2946{ 2947 /* 2948 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('') 2949 * 2950 * offset (8 bit): opcode 2951 * offset + 1 (32 bit): dst reg 2952 * offset + 5 (8 bit): count 2953 * offset + 6 (32 bit): data 1 2954 * ... 2955 * 2956 * For each of "count" values write "data n" to "dst reg" 2957 */ 2958 2959 uint32_t reg = ROM32(bios->data[offset + 1]); 2960 uint8_t count = bios->data[offset + 5]; 2961 int len = 6 + count * 4; 2962 int i; 2963 2964 if (!iexec->execute) 2965 return len; 2966 2967 for (i = 0; i < count; i++) { 2968 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]); 2969 bios_wr32(bios, reg, data); 2970 } 2971 2972 return len; 2973} 2974 2975static int 2976init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2977{ 2978 /* 2979 * INIT_RESERVED opcode: 0x92 ('') 2980 * 2981 * offset (8 bit): opcode 2982 * 2983 * Seemingly does nothing 2984 */ 2985 2986 return 1; 2987} 2988 2989static int 2990init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2991{ 2992 /* 2993 * INIT_96 opcode: 0x96 ('') 2994 * 2995 * offset (8 bit): opcode 2996 * offset + 1 (32 bit): sreg 2997 * offset + 5 (8 bit): sshift 2998 * offset + 6 (8 bit): smask 2999 * offset + 7 (8 bit): index 3000 * offset + 8 (32 bit): reg 3001 * offset + 12 (32 bit): mask 3002 * offset + 16 (8 bit): shift 3003 * 3004 */ 3005 3006 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2); 3007 uint32_t reg = ROM32(bios->data[offset + 8]); 3008 uint32_t mask = ROM32(bios->data[offset + 12]); 3009 uint32_t val; 3010 3011 val = bios_rd32(bios, ROM32(bios->data[offset + 1])); 3012 if (bios->data[offset + 5] < 0x80) 3013 val >>= bios->data[offset + 5]; 3014 else 3015 val <<= (0x100 - bios->data[offset + 5]); 3016 val &= bios->data[offset + 6]; 3017 3018 val = bios->data[ROM16(bios->data[xlatptr]) + val]; 3019 val <<= bios->data[offset + 16]; 3020 3021 if (!iexec->execute) 3022 return 17; 3023 3024 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val); 3025 return 17; 3026} 3027 3028static int 3029init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3030{ 3031 /* 3032 * INIT_97 opcode: 0x97 ('') 3033 * 3034 * offset (8 bit): opcode 3035 * offset + 1 (32 bit): register 3036 * offset + 5 (32 bit): mask 3037 * offset + 9 (32 bit): value 3038 * 3039 * Adds "value" to "register" preserving the fields specified 3040 * by "mask" 3041 */ 3042 3043 uint32_t reg = ROM32(bios->data[offset + 1]); 3044 uint32_t mask = ROM32(bios->data[offset + 5]); 3045 uint32_t add = ROM32(bios->data[offset + 9]); 3046 uint32_t val; 3047 3048 val = bios_rd32(bios, reg); 3049 val = (val & mask) | ((val + add) & ~mask); 3050 3051 if (!iexec->execute) 3052 return 13; 3053 3054 bios_wr32(bios, reg, val); 3055 return 13; 3056} 3057 3058static int 3059init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3060{ 3061 /* 3062 * INIT_AUXCH opcode: 0x98 ('') 3063 * 3064 * offset (8 bit): opcode 3065 * offset + 1 (32 bit): address 3066 * offset + 5 (8 bit): count 3067 * offset + 6 (8 bit): mask 0 3068 * offset + 7 (8 bit): data 0 3069 * ... 3070 * 3071 */ 3072 3073 struct drm_device *dev = bios->dev; 3074 struct nouveau_i2c_chan *auxch; 3075 uint32_t addr = ROM32(bios->data[offset + 1]); 3076 uint8_t count = bios->data[offset + 5]; 3077 int len = 6 + count * 2; 3078 int ret, i; 3079 3080 if (!bios->display.output) { 3081 NV_ERROR(dev, "INIT_AUXCH: no active output\n"); 3082 return -EINVAL; 3083 } 3084 3085 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index); 3086 if (!auxch) { 3087 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n", 3088 bios->display.output->i2c_index); 3089 return -ENODEV; 3090 } 3091 3092 if (!iexec->execute) 3093 return len; 3094 3095 offset += 6; 3096 for (i = 0; i < count; i++, offset += 2) { 3097 uint8_t data; 3098 3099 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1); 3100 if (ret) { 3101 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret); 3102 return ret; 3103 } 3104 3105 data &= bios->data[offset + 0]; 3106 data |= bios->data[offset + 1]; 3107 3108 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1); 3109 if (ret) { 3110 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret); 3111 return ret; 3112 } 3113 } 3114 3115 return len; 3116} 3117 3118static int 3119init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3120{ 3121 /* 3122 * INIT_ZM_AUXCH opcode: 0x99 ('') 3123 * 3124 * offset (8 bit): opcode 3125 * offset + 1 (32 bit): address 3126 * offset + 5 (8 bit): count 3127 * offset + 6 (8 bit): data 0 3128 * ... 3129 * 3130 */ 3131 3132 struct drm_device *dev = bios->dev; 3133 struct nouveau_i2c_chan *auxch; 3134 uint32_t addr = ROM32(bios->data[offset + 1]); 3135 uint8_t count = bios->data[offset + 5]; 3136 int len = 6 + count; 3137 int ret, i; 3138 3139 if (!bios->display.output) { 3140 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n"); 3141 return -EINVAL; 3142 } 3143 3144 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index); 3145 if (!auxch) { 3146 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n", 3147 bios->display.output->i2c_index); 3148 return -ENODEV; 3149 } 3150 3151 if (!iexec->execute) 3152 return len; 3153 3154 offset += 6; 3155 for (i = 0; i < count; i++, offset++) { 3156 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1); 3157 if (ret) { 3158 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret); 3159 return ret; 3160 } 3161 } 3162 3163 return len; 3164} 3165 3166static struct init_tbl_entry itbl_entry[] = { 3167 /* command name , id , length , offset , mult , command handler */ 3168 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */ 3169 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog }, 3170 { "INIT_REPEAT" , 0x33, init_repeat }, 3171 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll }, 3172 { "INIT_END_REPEAT" , 0x36, init_end_repeat }, 3173 { "INIT_COPY" , 0x37, init_copy }, 3174 { "INIT_NOT" , 0x38, init_not }, 3175 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition }, 3176 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition }, 3177 { "INIT_OP_3B" , 0x3B, init_op_3b }, 3178 { "INIT_OP_3C" , 0x3C, init_op_3c }, 3179 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched }, 3180 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 }, 3181 { "INIT_PLL2" , 0x4B, init_pll2 }, 3182 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte }, 3183 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte }, 3184 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c }, 3185 { "INIT_TMDS" , 0x4F, init_tmds }, 3186 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group }, 3187 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch }, 3188 { "INIT_CR" , 0x52, init_cr }, 3189 { "INIT_ZM_CR" , 0x53, init_zm_cr }, 3190 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group }, 3191 { "INIT_CONDITION_TIME" , 0x56, init_condition_time }, 3192 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence }, 3193 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */ 3194 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct }, 3195 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg }, 3196 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io }, 3197 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem }, 3198 { "INIT_RESET" , 0x65, init_reset }, 3199 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem }, 3200 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk }, 3201 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit }, 3202 { "INIT_IO" , 0x69, init_io }, 3203 { "INIT_SUB" , 0x6B, init_sub }, 3204 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition }, 3205 { "INIT_NV_REG" , 0x6E, init_nv_reg }, 3206 { "INIT_MACRO" , 0x6F, init_macro }, 3207 { "INIT_DONE" , 0x71, init_done }, 3208 { "INIT_RESUME" , 0x72, init_resume }, 3209 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */ 3210 { "INIT_TIME" , 0x74, init_time }, 3211 { "INIT_CONDITION" , 0x75, init_condition }, 3212 { "INIT_IO_CONDITION" , 0x76, init_io_condition }, 3213 { "INIT_INDEX_IO" , 0x78, init_index_io }, 3214 { "INIT_PLL" , 0x79, init_pll }, 3215 { "INIT_ZM_REG" , 0x7A, init_zm_reg }, 3216 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll }, 3217 { "INIT_8C" , 0x8C, init_8c }, 3218 { "INIT_8D" , 0x8D, init_8d }, 3219 { "INIT_GPIO" , 0x8E, init_gpio }, 3220 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group }, 3221 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg }, 3222 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched }, 3223 { "INIT_RESERVED" , 0x92, init_reserved }, 3224 { "INIT_96" , 0x96, init_96 }, 3225 { "INIT_97" , 0x97, init_97 }, 3226 { "INIT_AUXCH" , 0x98, init_auxch }, 3227 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch }, 3228 { NULL , 0 , NULL } 3229}; 3230 3231#define MAX_TABLE_OPS 1000 3232 3233static int 3234parse_init_table(struct nvbios *bios, unsigned int offset, 3235 struct init_exec *iexec) 3236{ 3237 /* 3238 * Parses all commands in an init table. 3239 * 3240 * We start out executing all commands found in the init table. Some 3241 * opcodes may change the status of iexec->execute to SKIP, which will 3242 * cause the following opcodes to perform no operation until the value 3243 * is changed back to EXECUTE. 3244 */ 3245 3246 int count = 0, i, ret; 3247 uint8_t id; 3248 3249 /* 3250 * Loop until INIT_DONE causes us to break out of the loop 3251 * (or until offset > bios length just in case... ) 3252 * (and no more than MAX_TABLE_OPS iterations, just in case... ) 3253 */ 3254 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) { 3255 id = bios->data[offset]; 3256 3257 /* Find matching id in itbl_entry */ 3258 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++) 3259 ; 3260 3261 if (!itbl_entry[i].name) { 3262 NV_ERROR(bios->dev, 3263 "0x%04X: Init table command not found: " 3264 "0x%02X\n", offset, id); 3265 return -ENOENT; 3266 } 3267 3268 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset, 3269 itbl_entry[i].id, itbl_entry[i].name); 3270 3271 /* execute eventual command handler */ 3272 ret = (*itbl_entry[i].handler)(bios, offset, iexec); 3273 if (ret < 0) { 3274 NV_ERROR(bios->dev, "0x%04X: Failed parsing init " 3275 "table opcode: %s %d\n", offset, 3276 itbl_entry[i].name, ret); 3277 } 3278 3279 if (ret <= 0) 3280 break; 3281 3282 /* 3283 * Add the offset of the current command including all data 3284 * of that command. The offset will then be pointing on the 3285 * next op code. 3286 */ 3287 offset += ret; 3288 } 3289 3290 if (offset >= bios->length) 3291 NV_WARN(bios->dev, 3292 "Offset 0x%04X greater than known bios image length. " 3293 "Corrupt image?\n", offset); 3294 if (count >= MAX_TABLE_OPS) 3295 NV_WARN(bios->dev, 3296 "More than %d opcodes to a table is unlikely, " 3297 "is the bios image corrupt?\n", MAX_TABLE_OPS); 3298 3299 return 0; 3300} 3301 3302static void 3303parse_init_tables(struct nvbios *bios) 3304{ 3305 /* Loops and calls parse_init_table() for each present table. */ 3306 3307 int i = 0; 3308 uint16_t table; 3309 struct init_exec iexec = {true, false}; 3310 3311 if (bios->old_style_init) { 3312 if (bios->init_script_tbls_ptr) 3313 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec); 3314 if (bios->extra_init_script_tbl_ptr) 3315 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec); 3316 3317 return; 3318 } 3319 3320 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) { 3321 NV_INFO(bios->dev, 3322 "Parsing VBIOS init table %d at offset 0x%04X\n", 3323 i / 2, table); 3324 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table); 3325 3326 parse_init_table(bios, table, &iexec); 3327 i += 2; 3328 } 3329} 3330 3331static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk) 3332{ 3333 int compare_record_len, i = 0; 3334 uint16_t compareclk, scriptptr = 0; 3335 3336 if (bios->major_version < 5) /* pre BIT */ 3337 compare_record_len = 3; 3338 else 3339 compare_record_len = 4; 3340 3341 do { 3342 compareclk = ROM16(bios->data[clktable + compare_record_len * i]); 3343 if (pxclk >= compareclk * 10) { 3344 if (bios->major_version < 5) { 3345 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i]; 3346 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]); 3347 } else 3348 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]); 3349 break; 3350 } 3351 i++; 3352 } while (compareclk); 3353 3354 return scriptptr; 3355} 3356 3357static void 3358run_digital_op_script(struct drm_device *dev, uint16_t scriptptr, 3359 struct dcb_entry *dcbent, int head, bool dl) 3360{ 3361 struct drm_nouveau_private *dev_priv = dev->dev_private; 3362 struct nvbios *bios = &dev_priv->vbios; 3363 struct init_exec iexec = {true, false}; 3364 3365 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n", 3366 scriptptr); 3367 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44, 3368 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA); 3369 /* note: if dcb entries have been merged, index may be misleading */ 3370 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index); 3371 parse_init_table(bios, scriptptr, &iexec); 3372 3373 nv04_dfp_bind_head(dev, dcbent, head, dl); 3374} 3375 3376static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script) 3377{ 3378 struct drm_nouveau_private *dev_priv = dev->dev_private; 3379 struct nvbios *bios = &dev_priv->vbios; 3380 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0); 3381 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]); 3382 3383 if (!bios->fp.xlated_entry || !sub || !scriptofs) 3384 return -EINVAL; 3385 3386 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link); 3387 3388 if (script == LVDS_PANEL_OFF) { 3389 /* off-on delay in ms */ 3390 msleep(ROM16(bios->data[bios->fp.xlated_entry + 7])); 3391 } 3392#ifdef __powerpc__ 3393 /* Powerbook specific quirks */ 3394 if ((dev->pci_device & 0xffff) == 0x0179 || 3395 (dev->pci_device & 0xffff) == 0x0189 || 3396 (dev->pci_device & 0xffff) == 0x0329) { 3397 if (script == LVDS_RESET) { 3398 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72); 3399 3400 } else if (script == LVDS_PANEL_ON) { 3401 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL, 3402 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL) 3403 | (1 << 31)); 3404 bios_wr32(bios, NV_PCRTC_GPIO_EXT, 3405 bios_rd32(bios, NV_PCRTC_GPIO_EXT) | 1); 3406 3407 } else if (script == LVDS_PANEL_OFF) { 3408 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL, 3409 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL) 3410 & ~(1 << 31)); 3411 bios_wr32(bios, NV_PCRTC_GPIO_EXT, 3412 bios_rd32(bios, NV_PCRTC_GPIO_EXT) & ~3); 3413 } 3414 } 3415#endif 3416 3417 return 0; 3418} 3419 3420static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk) 3421{ 3422 /* 3423 * The BIT LVDS table's header has the information to setup the 3424 * necessary registers. Following the standard 4 byte header are: 3425 * A bitmask byte and a dual-link transition pxclk value for use in 3426 * selecting the init script when not using straps; 4 script pointers 3427 * for panel power, selected by output and on/off; and 8 table pointers 3428 * for panel init, the needed one determined by output, and bits in the 3429 * conf byte. These tables are similar to the TMDS tables, consisting 3430 * of a list of pxclks and script pointers. 3431 */ 3432 struct drm_nouveau_private *dev_priv = dev->dev_private; 3433 struct nvbios *bios = &dev_priv->vbios; 3434 unsigned int outputset = (dcbent->or == 4) ? 1 : 0; 3435 uint16_t scriptptr = 0, clktable; 3436 3437 /* 3438 * For now we assume version 3.0 table - g80 support will need some 3439 * changes 3440 */ 3441 3442 switch (script) { 3443 case LVDS_INIT: 3444 return -ENOSYS; 3445 case LVDS_BACKLIGHT_ON: 3446 case LVDS_PANEL_ON: 3447 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]); 3448 break; 3449 case LVDS_BACKLIGHT_OFF: 3450 case LVDS_PANEL_OFF: 3451 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]); 3452 break; 3453 case LVDS_RESET: 3454 clktable = bios->fp.lvdsmanufacturerpointer + 15; 3455 if (dcbent->or == 4) 3456 clktable += 8; 3457 3458 if (dcbent->lvdsconf.use_straps_for_mode) { 3459 if (bios->fp.dual_link) 3460 clktable += 4; 3461 if (bios->fp.if_is_24bit) 3462 clktable += 2; 3463 } else { 3464 /* using EDID */ 3465 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1; 3466 3467 if (bios->fp.dual_link) { 3468 clktable += 4; 3469 cmpval_24bit <<= 1; 3470 } 3471 3472 if (bios->fp.strapless_is_24bit & cmpval_24bit) 3473 clktable += 2; 3474 } 3475 3476 clktable = ROM16(bios->data[clktable]); 3477 if (!clktable) { 3478 NV_ERROR(dev, "Pixel clock comparison table not found\n"); 3479 return -ENOENT; 3480 } 3481 scriptptr = clkcmptable(bios, clktable, pxclk); 3482 } 3483 3484 if (!scriptptr) { 3485 NV_ERROR(dev, "LVDS output init script not found\n"); 3486 return -ENOENT; 3487 } 3488 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link); 3489 3490 return 0; 3491} 3492 3493int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk) 3494{ 3495 /* 3496 * LVDS operations are multiplexed in an effort to present a single API 3497 * which works with two vastly differing underlying structures. 3498 * This acts as the demux 3499 */ 3500 3501 struct drm_nouveau_private *dev_priv = dev->dev_private; 3502 struct nvbios *bios = &dev_priv->vbios; 3503 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer]; 3504 uint32_t sel_clk_binding, sel_clk; 3505 int ret; 3506 3507 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver || 3508 (lvds_ver >= 0x30 && script == LVDS_INIT)) 3509 return 0; 3510 3511 if (!bios->fp.lvds_init_run) { 3512 bios->fp.lvds_init_run = true; 3513 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk); 3514 } 3515 3516 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change) 3517 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk); 3518 if (script == LVDS_RESET && bios->fp.power_off_for_reset) 3519 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk); 3520 3521 NV_TRACE(dev, "Calling LVDS script %d:\n", script); 3522 3523 /* don't let script change pll->head binding */ 3524 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000; 3525 3526 if (lvds_ver < 0x30) 3527 ret = call_lvds_manufacturer_script(dev, dcbent, head, script); 3528 else 3529 ret = run_lvds_table(dev, dcbent, head, script, pxclk); 3530 3531 bios->fp.last_script_invoc = (script << 1 | head); 3532 3533 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; 3534 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); 3535 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */ 3536 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0); 3537 3538 return ret; 3539} 3540 3541struct lvdstableheader { 3542 uint8_t lvds_ver, headerlen, recordlen; 3543}; 3544 3545static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth) 3546{ 3547 /* 3548 * BMP version (0xa) LVDS table has a simple header of version and 3549 * record length. The BIT LVDS table has the typical BIT table header: 3550 * version byte, header length byte, record length byte, and a byte for 3551 * the maximum number of records that can be held in the table. 3552 */ 3553 3554 uint8_t lvds_ver, headerlen, recordlen; 3555 3556 memset(lth, 0, sizeof(struct lvdstableheader)); 3557 3558 if (bios->fp.lvdsmanufacturerpointer == 0x0) { 3559 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n"); 3560 return -EINVAL; 3561 } 3562 3563 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer]; 3564 3565 switch (lvds_ver) { 3566 case 0x0a: /* pre NV40 */ 3567 headerlen = 2; 3568 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 3569 break; 3570 case 0x30: /* NV4x */ 3571 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 3572 if (headerlen < 0x1f) { 3573 NV_ERROR(dev, "LVDS table header not understood\n"); 3574 return -EINVAL; 3575 } 3576 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2]; 3577 break; 3578 case 0x40: /* G80/G90 */ 3579 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 3580 if (headerlen < 0x7) { 3581 NV_ERROR(dev, "LVDS table header not understood\n"); 3582 return -EINVAL; 3583 } 3584 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2]; 3585 break; 3586 default: 3587 NV_ERROR(dev, 3588 "LVDS table revision %d.%d not currently supported\n", 3589 lvds_ver >> 4, lvds_ver & 0xf); 3590 return -ENOSYS; 3591 } 3592 3593 lth->lvds_ver = lvds_ver; 3594 lth->headerlen = headerlen; 3595 lth->recordlen = recordlen; 3596 3597 return 0; 3598} 3599 3600static int 3601get_fp_strap(struct drm_device *dev, struct nvbios *bios) 3602{ 3603 struct drm_nouveau_private *dev_priv = dev->dev_private; 3604 3605 /* 3606 * The fp strap is normally dictated by the "User Strap" in 3607 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the 3608 * Internal_Flags struct at 0x48 is set, the user strap gets overriden 3609 * by the PCI subsystem ID during POST, but not before the previous user 3610 * strap has been committed to CR58 for CR57=0xf on head A, which may be 3611 * read and used instead 3612 */ 3613 3614 if (bios->major_version < 5 && bios->data[0x48] & 0x4) 3615 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf; 3616 3617 if (dev_priv->card_type >= NV_50) 3618 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf; 3619 else 3620 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf; 3621} 3622 3623static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios) 3624{ 3625 uint8_t *fptable; 3626 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex; 3627 int ret, ofs, fpstrapping; 3628 struct lvdstableheader lth; 3629 3630 if (bios->fp.fptablepointer == 0x0) { 3631 /* Apple cards don't have the fp table; the laptops use DDC */ 3632 /* The table is also missing on some x86 IGPs */ 3633#ifndef __powerpc__ 3634 NV_ERROR(dev, "Pointer to flat panel table invalid\n"); 3635#endif 3636 bios->digital_min_front_porch = 0x4b; 3637 return 0; 3638 } 3639 3640 fptable = &bios->data[bios->fp.fptablepointer]; 3641 fptable_ver = fptable[0]; 3642 3643 switch (fptable_ver) { 3644 /* 3645 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no 3646 * version field, and miss one of the spread spectrum/PWM bytes. 3647 * This could affect early GF2Go parts (not seen any appropriate ROMs 3648 * though). Here we assume that a version of 0x05 matches this case 3649 * (combining with a BMP version check would be better), as the 3650 * common case for the panel type field is 0x0005, and that is in 3651 * fact what we are reading the first byte of. 3652 */ 3653 case 0x05: /* some NV10, 11, 15, 16 */ 3654 recordlen = 42; 3655 ofs = -1; 3656 break; 3657 case 0x10: /* some NV15/16, and NV11+ */ 3658 recordlen = 44; 3659 ofs = 0; 3660 break; 3661 case 0x20: /* NV40+ */ 3662 headerlen = fptable[1]; 3663 recordlen = fptable[2]; 3664 fpentries = fptable[3]; 3665 /* 3666 * fptable[4] is the minimum 3667 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap 3668 */ 3669 bios->digital_min_front_porch = fptable[4]; 3670 ofs = -7; 3671 break; 3672 default: 3673 NV_ERROR(dev, 3674 "FP table revision %d.%d not currently supported\n", 3675 fptable_ver >> 4, fptable_ver & 0xf); 3676 return -ENOSYS; 3677 } 3678 3679 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */ 3680 return 0; 3681 3682 ret = parse_lvds_manufacturer_table_header(dev, bios, <h); 3683 if (ret) 3684 return ret; 3685 3686 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) { 3687 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer + 3688 lth.headerlen + 1; 3689 bios->fp.xlatwidth = lth.recordlen; 3690 } 3691 if (bios->fp.fpxlatetableptr == 0x0) { 3692 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n"); 3693 return -EINVAL; 3694 } 3695 3696 fpstrapping = get_fp_strap(dev, bios); 3697 3698 fpindex = bios->data[bios->fp.fpxlatetableptr + 3699 fpstrapping * bios->fp.xlatwidth]; 3700 3701 if (fpindex > fpentries) { 3702 NV_ERROR(dev, "Bad flat panel table index\n"); 3703 return -ENOENT; 3704 } 3705 3706 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */ 3707 if (lth.lvds_ver > 0x10) 3708 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf; 3709 3710 /* 3711 * If either the strap or xlated fpindex value are 0xf there is no 3712 * panel using a strap-derived bios mode present. this condition 3713 * includes, but is different from, the DDC panel indicator above 3714 */ 3715 if (fpstrapping == 0xf || fpindex == 0xf) 3716 return 0; 3717 3718 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen + 3719 recordlen * fpindex + ofs; 3720 3721 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n", 3722 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1, 3723 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1, 3724 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10); 3725 3726 return 0; 3727} 3728 3729bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode) 3730{ 3731 struct drm_nouveau_private *dev_priv = dev->dev_private; 3732 struct nvbios *bios = &dev_priv->vbios; 3733 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr]; 3734 3735 if (!mode) /* just checking whether we can produce a mode */ 3736 return bios->fp.mode_ptr; 3737 3738 memset(mode, 0, sizeof(struct drm_display_mode)); 3739 /* 3740 * For version 1.0 (version in byte 0): 3741 * bytes 1-2 are "panel type", including bits on whether Colour/mono, 3742 * single/dual link, and type (TFT etc.) 3743 * bytes 3-6 are bits per colour in RGBX 3744 */ 3745 mode->clock = ROM16(mode_entry[7]) * 10; 3746 /* bytes 9-10 is HActive */ 3747 mode->hdisplay = ROM16(mode_entry[11]) + 1; 3748 /* 3749 * bytes 13-14 is HValid Start 3750 * bytes 15-16 is HValid End 3751 */ 3752 mode->hsync_start = ROM16(mode_entry[17]) + 1; 3753 mode->hsync_end = ROM16(mode_entry[19]) + 1; 3754 mode->htotal = ROM16(mode_entry[21]) + 1; 3755 /* bytes 23-24, 27-30 similarly, but vertical */ 3756 mode->vdisplay = ROM16(mode_entry[25]) + 1; 3757 mode->vsync_start = ROM16(mode_entry[31]) + 1; 3758 mode->vsync_end = ROM16(mode_entry[33]) + 1; 3759 mode->vtotal = ROM16(mode_entry[35]) + 1; 3760 mode->flags |= (mode_entry[37] & 0x10) ? 3761 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3762 mode->flags |= (mode_entry[37] & 0x1) ? 3763 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3764 /* 3765 * bytes 38-39 relate to spread spectrum settings 3766 * bytes 40-43 are something to do with PWM 3767 */ 3768 3769 mode->status = MODE_OK; 3770 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; 3771 drm_mode_set_name(mode); 3772 return bios->fp.mode_ptr; 3773} 3774 3775int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit) 3776{ 3777 /* 3778 * The LVDS table header is (mostly) described in 3779 * parse_lvds_manufacturer_table_header(): the BIT header additionally 3780 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if 3781 * straps are not being used for the panel, this specifies the frequency 3782 * at which modes should be set up in the dual link style. 3783 * 3784 * Following the header, the BMP (ver 0xa) table has several records, 3785 * indexed by a separate xlat table, indexed in turn by the fp strap in 3786 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script 3787 * numbers for use by INIT_SUB which controlled panel init and power, 3788 * and finally a dword of ms to sleep between power off and on 3789 * operations. 3790 * 3791 * In the BIT versions, the table following the header serves as an 3792 * integrated config and xlat table: the records in the table are 3793 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has 3794 * two bytes - the first as a config byte, the second for indexing the 3795 * fp mode table pointed to by the BIT 'D' table 3796 * 3797 * DDC is not used until after card init, so selecting the correct table 3798 * entry and setting the dual link flag for EDID equipped panels, 3799 * requiring tests against the native-mode pixel clock, cannot be done 3800 * until later, when this function should be called with non-zero pxclk 3801 */ 3802 struct drm_nouveau_private *dev_priv = dev->dev_private; 3803 struct nvbios *bios = &dev_priv->vbios; 3804 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0; 3805 struct lvdstableheader lth; 3806 uint16_t lvdsofs; 3807 int ret, chip_version = bios->chip_version; 3808 3809 ret = parse_lvds_manufacturer_table_header(dev, bios, <h); 3810 if (ret) 3811 return ret; 3812 3813 switch (lth.lvds_ver) { 3814 case 0x0a: /* pre NV40 */ 3815 lvdsmanufacturerindex = bios->data[ 3816 bios->fp.fpxlatemanufacturertableptr + 3817 fpstrapping]; 3818 3819 /* we're done if this isn't the EDID panel case */ 3820 if (!pxclk) 3821 break; 3822 3823 if (chip_version < 0x25) { 3824 /* nv17 behaviour 3825 * 3826 * It seems the old style lvds script pointer is reused 3827 * to select 18/24 bit colour depth for EDID panels. 3828 */ 3829 lvdsmanufacturerindex = 3830 (bios->legacy.lvds_single_a_script_ptr & 1) ? 3831 2 : 0; 3832 if (pxclk >= bios->fp.duallink_transition_clk) 3833 lvdsmanufacturerindex++; 3834 } else if (chip_version < 0x30) { 3835 /* nv28 behaviour (off-chip encoder) 3836 * 3837 * nv28 does a complex dance of first using byte 121 of 3838 * the EDID to choose the lvdsmanufacturerindex, then 3839 * later attempting to match the EDID manufacturer and 3840 * product IDs in a table (signature 'pidt' (panel id 3841 * table?)), setting an lvdsmanufacturerindex of 0 and 3842 * an fp strap of the match index (or 0xf if none) 3843 */ 3844 lvdsmanufacturerindex = 0; 3845 } else { 3846 /* nv31, nv34 behaviour */ 3847 lvdsmanufacturerindex = 0; 3848 if (pxclk >= bios->fp.duallink_transition_clk) 3849 lvdsmanufacturerindex = 2; 3850 if (pxclk >= 140000) 3851 lvdsmanufacturerindex = 3; 3852 } 3853 3854 /* 3855 * nvidia set the high nibble of (cr57=f, cr58) to 3856 * lvdsmanufacturerindex in this case; we don't 3857 */ 3858 break; 3859 case 0x30: /* NV4x */ 3860 case 0x40: /* G80/G90 */ 3861 lvdsmanufacturerindex = fpstrapping; 3862 break; 3863 default: 3864 NV_ERROR(dev, "LVDS table revision not currently supported\n"); 3865 return -ENOSYS; 3866 } 3867 3868 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex; 3869 switch (lth.lvds_ver) { 3870 case 0x0a: 3871 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1; 3872 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2; 3873 bios->fp.dual_link = bios->data[lvdsofs] & 4; 3874 bios->fp.link_c_increment = bios->data[lvdsofs] & 8; 3875 *if_is_24bit = bios->data[lvdsofs] & 16; 3876 break; 3877 case 0x30: 3878 case 0x40: 3879 /* 3880 * No sign of the "power off for reset" or "reset for panel 3881 * on" bits, but it's safer to assume we should 3882 */ 3883 bios->fp.power_off_for_reset = true; 3884 bios->fp.reset_after_pclk_change = true; 3885 3886 /* 3887 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is 3888 * over-written, and if_is_24bit isn't used 3889 */ 3890 bios->fp.dual_link = bios->data[lvdsofs] & 1; 3891 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2; 3892 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4]; 3893 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10; 3894 break; 3895 } 3896 3897 /* Dell Latitude D620 reports a too-high value for the dual-link 3898 * transition freq, causing us to program the panel incorrectly. 3899 * 3900 * It doesn't appear the VBIOS actually uses its transition freq 3901 * (90000kHz), instead it uses the "Number of LVDS channels" field 3902 * out of the panel ID structure (http://www.spwg.org/). 3903 * 3904 * For the moment, a quirk will do :) 3905 */ 3906 if ((dev->pdev->device == 0x01d7) && 3907 (dev->pdev->subsystem_vendor == 0x1028) && 3908 (dev->pdev->subsystem_device == 0x01c2)) { 3909 bios->fp.duallink_transition_clk = 80000; 3910 } 3911 3912 /* set dual_link flag for EDID case */ 3913 if (pxclk && (chip_version < 0x25 || chip_version > 0x28)) 3914 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk); 3915 3916 *dl = bios->fp.dual_link; 3917 3918 return 0; 3919} 3920 3921static uint8_t * 3922bios_output_config_match(struct drm_device *dev, struct dcb_entry *dcbent, 3923 uint16_t record, int record_len, int record_nr, 3924 bool match_link) 3925{ 3926 struct drm_nouveau_private *dev_priv = dev->dev_private; 3927 struct nvbios *bios = &dev_priv->vbios; 3928 uint32_t entry; 3929 uint16_t table; 3930 int i, v; 3931 3932 switch (dcbent->type) { 3933 case OUTPUT_TMDS: 3934 case OUTPUT_LVDS: 3935 case OUTPUT_DP: 3936 break; 3937 default: 3938 match_link = false; 3939 break; 3940 } 3941 3942 for (i = 0; i < record_nr; i++, record += record_len) { 3943 table = ROM16(bios->data[record]); 3944 if (!table) 3945 continue; 3946 entry = ROM32(bios->data[table]); 3947 3948 if (match_link) { 3949 v = (entry & 0x00c00000) >> 22; 3950 if (!(v & dcbent->sorconf.link)) 3951 continue; 3952 } 3953 3954 v = (entry & 0x000f0000) >> 16; 3955 if (!(v & dcbent->or)) 3956 continue; 3957 3958 v = (entry & 0x000000f0) >> 4; 3959 if (v != dcbent->location) 3960 continue; 3961 3962 v = (entry & 0x0000000f); 3963 if (v != dcbent->type) 3964 continue; 3965 3966 return &bios->data[table]; 3967 } 3968 3969 return NULL; 3970} 3971 3972void * 3973nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent, 3974 int *length) 3975{ 3976 struct drm_nouveau_private *dev_priv = dev->dev_private; 3977 struct nvbios *bios = &dev_priv->vbios; 3978 uint8_t *table; 3979 3980 if (!bios->display.dp_table_ptr) { 3981 NV_ERROR(dev, "No pointer to DisplayPort table\n"); 3982 return NULL; 3983 } 3984 table = &bios->data[bios->display.dp_table_ptr]; 3985 3986 if (table[0] != 0x20 && table[0] != 0x21) { 3987 NV_ERROR(dev, "DisplayPort table version 0x%02x unknown\n", 3988 table[0]); 3989 return NULL; 3990 } 3991 3992 *length = table[4]; 3993 return bios_output_config_match(dev, dcbent, 3994 bios->display.dp_table_ptr + table[1], 3995 table[2], table[3], table[0] >= 0x21); 3996} 3997 3998int 3999nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent, 4000 uint32_t sub, int pxclk) 4001{ 4002 /* 4003 * The display script table is located by the BIT 'U' table. 4004 * 4005 * It contains an array of pointers to various tables describing 4006 * a particular output type. The first 32-bits of the output 4007 * tables contains similar information to a DCB entry, and is 4008 * used to decide whether that particular table is suitable for 4009 * the output you want to access. 4010 * 4011 * The "record header length" field here seems to indicate the 4012 * offset of the first configuration entry in the output tables. 4013 * This is 10 on most cards I've seen, but 12 has been witnessed 4014 * on DP cards, and there's another script pointer within the 4015 * header. 4016 * 4017 * offset + 0 ( 8 bits): version 4018 * offset + 1 ( 8 bits): header length 4019 * offset + 2 ( 8 bits): record length 4020 * offset + 3 ( 8 bits): number of records 4021 * offset + 4 ( 8 bits): record header length 4022 * offset + 5 (16 bits): pointer to first output script table 4023 */ 4024 4025 struct drm_nouveau_private *dev_priv = dev->dev_private; 4026 struct nvbios *bios = &dev_priv->vbios; 4027 uint8_t *table = &bios->data[bios->display.script_table_ptr]; 4028 uint8_t *otable = NULL; 4029 uint16_t script; 4030 int i = 0; 4031 4032 if (!bios->display.script_table_ptr) { 4033 NV_ERROR(dev, "No pointer to output script table\n"); 4034 return 1; 4035 } 4036 4037 /* 4038 * Nothing useful has been in any of the pre-2.0 tables I've seen, 4039 * so until they are, we really don't need to care. 4040 */ 4041 if (table[0] < 0x20) 4042 return 1; 4043 4044 if (table[0] != 0x20 && table[0] != 0x21) { 4045 NV_ERROR(dev, "Output script table version 0x%02x unknown\n", 4046 table[0]); 4047 return 1; 4048 } 4049 4050 /* 4051 * The output script tables describing a particular output type 4052 * look as follows: 4053 * 4054 * offset + 0 (32 bits): output this table matches (hash of DCB) 4055 * offset + 4 ( 8 bits): unknown 4056 * offset + 5 ( 8 bits): number of configurations 4057 * offset + 6 (16 bits): pointer to some script 4058 * offset + 8 (16 bits): pointer to some script 4059 * 4060 * headerlen == 10 4061 * offset + 10 : configuration 0 4062 * 4063 * headerlen == 12 4064 * offset + 10 : pointer to some script 4065 * offset + 12 : configuration 0 4066 * 4067 * Each config entry is as follows: 4068 * 4069 * offset + 0 (16 bits): unknown, assumed to be a match value 4070 * offset + 2 (16 bits): pointer to script table (clock set?) 4071 * offset + 4 (16 bits): pointer to script table (reset?) 4072 * 4073 * There doesn't appear to be a count value to say how many 4074 * entries exist in each script table, instead, a 0 value in 4075 * the first 16-bit word seems to indicate both the end of the 4076 * list and the default entry. The second 16-bit word in the 4077 * script tables is a pointer to the script to execute. 4078 */ 4079 4080 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n", 4081 dcbent->type, dcbent->location, dcbent->or); 4082 otable = bios_output_config_match(dev, dcbent, table[1] + 4083 bios->display.script_table_ptr, 4084 table[2], table[3], table[0] >= 0x21); 4085 if (!otable) { 4086 NV_ERROR(dev, "Couldn't find matching output script table\n"); 4087 return 1; 4088 } 4089 4090 if (pxclk < -2 || pxclk > 0) { 4091 /* Try to find matching script table entry */ 4092 for (i = 0; i < otable[5]; i++) { 4093 if (ROM16(otable[table[4] + i*6]) == sub) 4094 break; 4095 } 4096 4097 if (i == otable[5]) { 4098 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, " 4099 "using first\n", 4100 sub, dcbent->type, dcbent->or); 4101 i = 0; 4102 } 4103 } 4104 4105 if (pxclk == 0) { 4106 script = ROM16(otable[6]); 4107 if (!script) { 4108 NV_DEBUG_KMS(dev, "output script 0 not found\n"); 4109 return 1; 4110 } 4111 4112 NV_TRACE(dev, "0x%04X: parsing output script 0\n", script); 4113 nouveau_bios_run_init_table(dev, script, dcbent); 4114 } else 4115 if (pxclk == -1) { 4116 script = ROM16(otable[8]); 4117 if (!script) { 4118 NV_DEBUG_KMS(dev, "output script 1 not found\n"); 4119 return 1; 4120 } 4121 4122 NV_TRACE(dev, "0x%04X: parsing output script 1\n", script); 4123 nouveau_bios_run_init_table(dev, script, dcbent); 4124 } else 4125 if (pxclk == -2) { 4126 if (table[4] >= 12) 4127 script = ROM16(otable[10]); 4128 else 4129 script = 0; 4130 if (!script) { 4131 NV_DEBUG_KMS(dev, "output script 2 not found\n"); 4132 return 1; 4133 } 4134 4135 NV_TRACE(dev, "0x%04X: parsing output script 2\n", script); 4136 nouveau_bios_run_init_table(dev, script, dcbent); 4137 } else 4138 if (pxclk > 0) { 4139 script = ROM16(otable[table[4] + i*6 + 2]); 4140 if (script) 4141 script = clkcmptable(bios, script, pxclk); 4142 if (!script) { 4143 NV_ERROR(dev, "clock script 0 not found\n"); 4144 return 1; 4145 } 4146 4147 NV_TRACE(dev, "0x%04X: parsing clock script 0\n", script); 4148 nouveau_bios_run_init_table(dev, script, dcbent); 4149 } else 4150 if (pxclk < 0) { 4151 script = ROM16(otable[table[4] + i*6 + 4]); 4152 if (script) 4153 script = clkcmptable(bios, script, -pxclk); 4154 if (!script) { 4155 NV_DEBUG_KMS(dev, "clock script 1 not found\n"); 4156 return 1; 4157 } 4158 4159 NV_TRACE(dev, "0x%04X: parsing clock script 1\n", script); 4160 nouveau_bios_run_init_table(dev, script, dcbent); 4161 } 4162 4163 return 0; 4164} 4165 4166 4167int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk) 4168{ 4169 /* 4170 * the pxclk parameter is in kHz 4171 * 4172 * This runs the TMDS regs setting code found on BIT bios cards 4173 * 4174 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and 4175 * ffs(or) == 3, use the second. 4176 */ 4177 4178 struct drm_nouveau_private *dev_priv = dev->dev_private; 4179 struct nvbios *bios = &dev_priv->vbios; 4180 int cv = bios->chip_version; 4181 uint16_t clktable = 0, scriptptr; 4182 uint32_t sel_clk_binding, sel_clk; 4183 4184 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */ 4185 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 && 4186 dcbent->location != DCB_LOC_ON_CHIP) 4187 return 0; 4188 4189 switch (ffs(dcbent->or)) { 4190 case 1: 4191 clktable = bios->tmds.output0_script_ptr; 4192 break; 4193 case 2: 4194 case 3: 4195 clktable = bios->tmds.output1_script_ptr; 4196 break; 4197 } 4198 4199 if (!clktable) { 4200 NV_ERROR(dev, "Pixel clock comparison table not found\n"); 4201 return -EINVAL; 4202 } 4203 4204 scriptptr = clkcmptable(bios, clktable, pxclk); 4205 4206 if (!scriptptr) { 4207 NV_ERROR(dev, "TMDS output init script not found\n"); 4208 return -ENOENT; 4209 } 4210 4211 /* don't let script change pll->head binding */ 4212 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000; 4213 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000); 4214 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; 4215 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); 4216 4217 return 0; 4218} 4219 4220int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim) 4221{ 4222 /* 4223 * PLL limits table 4224 * 4225 * Version 0x10: NV30, NV31 4226 * One byte header (version), one record of 24 bytes 4227 * Version 0x11: NV36 - Not implemented 4228 * Seems to have same record style as 0x10, but 3 records rather than 1 4229 * Version 0x20: Found on Geforce 6 cards 4230 * Trivial 4 byte BIT header. 31 (0x1f) byte record length 4231 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards 4232 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record 4233 * length in general, some (integrated) have an extra configuration byte 4234 * Version 0x30: Found on Geforce 8, separates the register mapping 4235 * from the limits tables. 4236 */ 4237 4238 struct drm_nouveau_private *dev_priv = dev->dev_private; 4239 struct nvbios *bios = &dev_priv->vbios; 4240 int cv = bios->chip_version, pllindex = 0; 4241 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0; 4242 uint32_t crystal_strap_mask, crystal_straps; 4243 4244 if (!bios->pll_limit_tbl_ptr) { 4245 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 || 4246 cv >= 0x40) { 4247 NV_ERROR(dev, "Pointer to PLL limits table invalid\n"); 4248 return -EINVAL; 4249 } 4250 } else 4251 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr]; 4252 4253 crystal_strap_mask = 1 << 6; 4254 /* open coded dev->twoHeads test */ 4255 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20) 4256 crystal_strap_mask |= 1 << 22; 4257 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) & 4258 crystal_strap_mask; 4259 4260 switch (pll_lim_ver) { 4261 /* 4262 * We use version 0 to indicate a pre limit table bios (single stage 4263 * pll) and load the hard coded limits instead. 4264 */ 4265 case 0: 4266 break; 4267 case 0x10: 4268 case 0x11: 4269 /* 4270 * Strictly v0x11 has 3 entries, but the last two don't seem 4271 * to get used. 4272 */ 4273 headerlen = 1; 4274 recordlen = 0x18; 4275 entries = 1; 4276 pllindex = 0; 4277 break; 4278 case 0x20: 4279 case 0x21: 4280 case 0x30: 4281 case 0x40: 4282 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1]; 4283 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2]; 4284 entries = bios->data[bios->pll_limit_tbl_ptr + 3]; 4285 break; 4286 default: 4287 NV_ERROR(dev, "PLL limits table revision 0x%X not currently " 4288 "supported\n", pll_lim_ver); 4289 return -ENOSYS; 4290 } 4291 4292 /* initialize all members to zero */ 4293 memset(pll_lim, 0, sizeof(struct pll_lims)); 4294 4295 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) { 4296 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex]; 4297 4298 pll_lim->vco1.minfreq = ROM32(pll_rec[0]); 4299 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]); 4300 pll_lim->vco2.minfreq = ROM32(pll_rec[8]); 4301 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]); 4302 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]); 4303 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]); 4304 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX; 4305 4306 /* these values taken from nv30/31/36 */ 4307 pll_lim->vco1.min_n = 0x1; 4308 if (cv == 0x36) 4309 pll_lim->vco1.min_n = 0x5; 4310 pll_lim->vco1.max_n = 0xff; 4311 pll_lim->vco1.min_m = 0x1; 4312 pll_lim->vco1.max_m = 0xd; 4313 pll_lim->vco2.min_n = 0x4; 4314 /* 4315 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this 4316 * table version (apart from nv35)), N2 is compared to 4317 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and 4318 * save a comparison 4319 */ 4320 pll_lim->vco2.max_n = 0x28; 4321 if (cv == 0x30 || cv == 0x35) 4322 /* only 5 bits available for N2 on nv30/35 */ 4323 pll_lim->vco2.max_n = 0x1f; 4324 pll_lim->vco2.min_m = 0x1; 4325 pll_lim->vco2.max_m = 0x4; 4326 pll_lim->max_log2p = 0x7; 4327 pll_lim->max_usable_log2p = 0x6; 4328 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) { 4329 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen; 4330 uint32_t reg = 0; /* default match */ 4331 uint8_t *pll_rec; 4332 int i; 4333 4334 /* 4335 * First entry is default match, if nothing better. warn if 4336 * reg field nonzero 4337 */ 4338 if (ROM32(bios->data[plloffs])) 4339 NV_WARN(dev, "Default PLL limit entry has non-zero " 4340 "register field\n"); 4341 4342 if (limit_match > MAX_PLL_TYPES) 4343 /* we've been passed a reg as the match */ 4344 reg = limit_match; 4345 else /* limit match is a pll type */ 4346 for (i = 1; i < entries && !reg; i++) { 4347 uint32_t cmpreg = ROM32(bios->data[plloffs + recordlen * i]); 4348 4349 if (limit_match == NVPLL && 4350 (cmpreg == NV_PRAMDAC_NVPLL_COEFF || cmpreg == 0x4000)) 4351 reg = cmpreg; 4352 if (limit_match == MPLL && 4353 (cmpreg == NV_PRAMDAC_MPLL_COEFF || cmpreg == 0x4020)) 4354 reg = cmpreg; 4355 if (limit_match == VPLL1 && 4356 (cmpreg == NV_PRAMDAC_VPLL_COEFF || cmpreg == 0x4010)) 4357 reg = cmpreg; 4358 if (limit_match == VPLL2 && 4359 (cmpreg == NV_RAMDAC_VPLL2 || cmpreg == 0x4018)) 4360 reg = cmpreg; 4361 } 4362 4363 for (i = 1; i < entries; i++) 4364 if (ROM32(bios->data[plloffs + recordlen * i]) == reg) { 4365 pllindex = i; 4366 break; 4367 } 4368 4369 pll_rec = &bios->data[plloffs + recordlen * pllindex]; 4370 4371 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n", 4372 pllindex ? reg : 0); 4373 4374 /* 4375 * Frequencies are stored in tables in MHz, kHz are more 4376 * useful, so we convert. 4377 */ 4378 4379 /* What output frequencies can each VCO generate? */ 4380 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000; 4381 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000; 4382 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000; 4383 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000; 4384 4385 /* What input frequencies they accept (past the m-divider)? */ 4386 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000; 4387 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000; 4388 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000; 4389 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000; 4390 4391 /* What values are accepted as multiplier and divider? */ 4392 pll_lim->vco1.min_n = pll_rec[20]; 4393 pll_lim->vco1.max_n = pll_rec[21]; 4394 pll_lim->vco1.min_m = pll_rec[22]; 4395 pll_lim->vco1.max_m = pll_rec[23]; 4396 pll_lim->vco2.min_n = pll_rec[24]; 4397 pll_lim->vco2.max_n = pll_rec[25]; 4398 pll_lim->vco2.min_m = pll_rec[26]; 4399 pll_lim->vco2.max_m = pll_rec[27]; 4400 4401 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29]; 4402 if (pll_lim->max_log2p > 0x7) 4403 /* pll decoding in nv_hw.c assumes never > 7 */ 4404 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n", 4405 pll_lim->max_log2p); 4406 if (cv < 0x60) 4407 pll_lim->max_usable_log2p = 0x6; 4408 pll_lim->log2p_bias = pll_rec[30]; 4409 4410 if (recordlen > 0x22) 4411 pll_lim->refclk = ROM32(pll_rec[31]); 4412 4413 if (recordlen > 0x23 && pll_rec[35]) 4414 NV_WARN(dev, 4415 "Bits set in PLL configuration byte (%x)\n", 4416 pll_rec[35]); 4417 4418 /* C51 special not seen elsewhere */ 4419 if (cv == 0x51 && !pll_lim->refclk) { 4420 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK); 4421 4422 if (((limit_match == NV_PRAMDAC_VPLL_COEFF || limit_match == VPLL1) && sel_clk & 0x20) || 4423 ((limit_match == NV_RAMDAC_VPLL2 || limit_match == VPLL2) && sel_clk & 0x80)) { 4424 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3) 4425 pll_lim->refclk = 200000; 4426 else 4427 pll_lim->refclk = 25000; 4428 } 4429 } 4430 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */ 4431 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen]; 4432 uint8_t *record = NULL; 4433 int i; 4434 4435 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n", 4436 limit_match); 4437 4438 for (i = 0; i < entries; i++, entry += recordlen) { 4439 if (ROM32(entry[3]) == limit_match) { 4440 record = &bios->data[ROM16(entry[1])]; 4441 break; 4442 } 4443 } 4444 4445 if (!record) { 4446 NV_ERROR(dev, "Register 0x%08x not found in PLL " 4447 "limits table", limit_match); 4448 return -ENOENT; 4449 } 4450 4451 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000; 4452 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000; 4453 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000; 4454 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000; 4455 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000; 4456 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000; 4457 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000; 4458 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000; 4459 pll_lim->vco1.min_n = record[16]; 4460 pll_lim->vco1.max_n = record[17]; 4461 pll_lim->vco1.min_m = record[18]; 4462 pll_lim->vco1.max_m = record[19]; 4463 pll_lim->vco2.min_n = record[20]; 4464 pll_lim->vco2.max_n = record[21]; 4465 pll_lim->vco2.min_m = record[22]; 4466 pll_lim->vco2.max_m = record[23]; 4467 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25]; 4468 pll_lim->log2p_bias = record[27]; 4469 pll_lim->refclk = ROM32(record[28]); 4470 } else if (pll_lim_ver) { /* ver 0x40 */ 4471 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen]; 4472 uint8_t *record = NULL; 4473 int i; 4474 4475 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n", 4476 limit_match); 4477 4478 for (i = 0; i < entries; i++, entry += recordlen) { 4479 if (ROM32(entry[3]) == limit_match) { 4480 record = &bios->data[ROM16(entry[1])]; 4481 break; 4482 } 4483 } 4484 4485 if (!record) { 4486 NV_ERROR(dev, "Register 0x%08x not found in PLL " 4487 "limits table", limit_match); 4488 return -ENOENT; 4489 } 4490 4491 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000; 4492 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000; 4493 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000; 4494 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000; 4495 pll_lim->vco1.min_m = record[8]; 4496 pll_lim->vco1.max_m = record[9]; 4497 pll_lim->vco1.min_n = record[10]; 4498 pll_lim->vco1.max_n = record[11]; 4499 pll_lim->min_p = record[12]; 4500 pll_lim->max_p = record[13]; 4501 /* where did this go to?? */ 4502 if (limit_match == 0x00614100 || limit_match == 0x00614900) 4503 pll_lim->refclk = 27000; 4504 else 4505 pll_lim->refclk = 100000; 4506 } 4507 4508 /* 4509 * By now any valid limit table ought to have set a max frequency for 4510 * vco1, so if it's zero it's either a pre limit table bios, or one 4511 * with an empty limit table (seen on nv18) 4512 */ 4513 if (!pll_lim->vco1.maxfreq) { 4514 pll_lim->vco1.minfreq = bios->fminvco; 4515 pll_lim->vco1.maxfreq = bios->fmaxvco; 4516 pll_lim->vco1.min_inputfreq = 0; 4517 pll_lim->vco1.max_inputfreq = INT_MAX; 4518 pll_lim->vco1.min_n = 0x1; 4519 pll_lim->vco1.max_n = 0xff; 4520 pll_lim->vco1.min_m = 0x1; 4521 if (crystal_straps == 0) { 4522 /* nv05 does this, nv11 doesn't, nv10 unknown */ 4523 if (cv < 0x11) 4524 pll_lim->vco1.min_m = 0x7; 4525 pll_lim->vco1.max_m = 0xd; 4526 } else { 4527 if (cv < 0x11) 4528 pll_lim->vco1.min_m = 0x8; 4529 pll_lim->vco1.max_m = 0xe; 4530 } 4531 if (cv < 0x17 || cv == 0x1a || cv == 0x20) 4532 pll_lim->max_log2p = 4; 4533 else 4534 pll_lim->max_log2p = 5; 4535 pll_lim->max_usable_log2p = pll_lim->max_log2p; 4536 } 4537 4538 if (!pll_lim->refclk) 4539 switch (crystal_straps) { 4540 case 0: 4541 pll_lim->refclk = 13500; 4542 break; 4543 case (1 << 6): 4544 pll_lim->refclk = 14318; 4545 break; 4546 case (1 << 22): 4547 pll_lim->refclk = 27000; 4548 break; 4549 case (1 << 22 | 1 << 6): 4550 pll_lim->refclk = 25000; 4551 break; 4552 } 4553 4554 NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq); 4555 NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq); 4556 NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq); 4557 NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq); 4558 NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n); 4559 NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n); 4560 NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m); 4561 NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m); 4562 if (pll_lim->vco2.maxfreq) { 4563 NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq); 4564 NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq); 4565 NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq); 4566 NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq); 4567 NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n); 4568 NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n); 4569 NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m); 4570 NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m); 4571 } 4572 if (!pll_lim->max_p) { 4573 NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p); 4574 NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias); 4575 } else { 4576 NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p); 4577 NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p); 4578 } 4579 NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk); 4580 4581 return 0; 4582} 4583 4584static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset) 4585{ 4586 /* 4587 * offset + 0 (8 bits): Micro version 4588 * offset + 1 (8 bits): Minor version 4589 * offset + 2 (8 bits): Chip version 4590 * offset + 3 (8 bits): Major version 4591 */ 4592 4593 bios->major_version = bios->data[offset + 3]; 4594 bios->chip_version = bios->data[offset + 2]; 4595 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n", 4596 bios->data[offset + 3], bios->data[offset + 2], 4597 bios->data[offset + 1], bios->data[offset]); 4598} 4599 4600static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset) 4601{ 4602 /* 4603 * Parses the init table segment for pointers used in script execution. 4604 * 4605 * offset + 0 (16 bits): init script tables pointer 4606 * offset + 2 (16 bits): macro index table pointer 4607 * offset + 4 (16 bits): macro table pointer 4608 * offset + 6 (16 bits): condition table pointer 4609 * offset + 8 (16 bits): io condition table pointer 4610 * offset + 10 (16 bits): io flag condition table pointer 4611 * offset + 12 (16 bits): init function table pointer 4612 */ 4613 4614 bios->init_script_tbls_ptr = ROM16(bios->data[offset]); 4615 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]); 4616 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]); 4617 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]); 4618 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]); 4619 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]); 4620 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]); 4621} 4622 4623static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4624{ 4625 /* 4626 * Parses the load detect values for g80 cards. 4627 * 4628 * offset + 0 (16 bits): loadval table pointer 4629 */ 4630 4631 uint16_t load_table_ptr; 4632 uint8_t version, headerlen, entrylen, num_entries; 4633 4634 if (bitentry->length != 3) { 4635 NV_ERROR(dev, "Do not understand BIT A table\n"); 4636 return -EINVAL; 4637 } 4638 4639 load_table_ptr = ROM16(bios->data[bitentry->offset]); 4640 4641 if (load_table_ptr == 0x0) { 4642 NV_ERROR(dev, "Pointer to BIT loadval table invalid\n"); 4643 return -EINVAL; 4644 } 4645 4646 version = bios->data[load_table_ptr]; 4647 4648 if (version != 0x10) { 4649 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n", 4650 version >> 4, version & 0xF); 4651 return -ENOSYS; 4652 } 4653 4654 headerlen = bios->data[load_table_ptr + 1]; 4655 entrylen = bios->data[load_table_ptr + 2]; 4656 num_entries = bios->data[load_table_ptr + 3]; 4657 4658 if (headerlen != 4 || entrylen != 4 || num_entries != 2) { 4659 NV_ERROR(dev, "Do not understand BIT loadval table\n"); 4660 return -EINVAL; 4661 } 4662 4663 /* First entry is normal dac, 2nd tv-out perhaps? */ 4664 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff; 4665 4666 return 0; 4667} 4668 4669static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4670{ 4671 /* 4672 * offset + 8 (16 bits): PLL limits table pointer 4673 * 4674 * There's more in here, but that's unknown. 4675 */ 4676 4677 if (bitentry->length < 10) { 4678 NV_ERROR(dev, "Do not understand BIT C table\n"); 4679 return -EINVAL; 4680 } 4681 4682 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]); 4683 4684 return 0; 4685} 4686 4687static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4688{ 4689 /* 4690 * Parses the flat panel table segment that the bit entry points to. 4691 * Starting at bitentry->offset: 4692 * 4693 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte 4694 * records beginning with a freq. 4695 * offset + 2 (16 bits): mode table pointer 4696 */ 4697 4698 if (bitentry->length != 4) { 4699 NV_ERROR(dev, "Do not understand BIT display table\n"); 4700 return -EINVAL; 4701 } 4702 4703 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]); 4704 4705 return 0; 4706} 4707 4708static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4709{ 4710 /* 4711 * Parses the init table segment that the bit entry points to. 4712 * 4713 * See parse_script_table_pointers for layout 4714 */ 4715 4716 if (bitentry->length < 14) { 4717 NV_ERROR(dev, "Do not understand init table\n"); 4718 return -EINVAL; 4719 } 4720 4721 parse_script_table_pointers(bios, bitentry->offset); 4722 4723 if (bitentry->length >= 16) 4724 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]); 4725 if (bitentry->length >= 18) 4726 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]); 4727 4728 return 0; 4729} 4730 4731static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4732{ 4733 /* 4734 * BIT 'i' (info?) table 4735 * 4736 * offset + 0 (32 bits): BIOS version dword (as in B table) 4737 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?) 4738 * offset + 13 (16 bits): pointer to table containing DAC load 4739 * detection comparison values 4740 * 4741 * There's other things in the table, purpose unknown 4742 */ 4743 4744 uint16_t daccmpoffset; 4745 uint8_t dacver, dacheaderlen; 4746 4747 if (bitentry->length < 6) { 4748 NV_ERROR(dev, "BIT i table too short for needed information\n"); 4749 return -EINVAL; 4750 } 4751 4752 parse_bios_version(dev, bios, bitentry->offset); 4753 4754 /* 4755 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's 4756 * Quadro identity crisis), other bits possibly as for BMP feature byte 4757 */ 4758 bios->feature_byte = bios->data[bitentry->offset + 5]; 4759 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE; 4760 4761 if (bitentry->length < 15) { 4762 NV_WARN(dev, "BIT i table not long enough for DAC load " 4763 "detection comparison table\n"); 4764 return -EINVAL; 4765 } 4766 4767 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]); 4768 4769 /* doesn't exist on g80 */ 4770 if (!daccmpoffset) 4771 return 0; 4772 4773 /* 4774 * The first value in the table, following the header, is the 4775 * comparison value, the second entry is a comparison value for 4776 * TV load detection. 4777 */ 4778 4779 dacver = bios->data[daccmpoffset]; 4780 dacheaderlen = bios->data[daccmpoffset + 1]; 4781 4782 if (dacver != 0x00 && dacver != 0x10) { 4783 NV_WARN(dev, "DAC load detection comparison table version " 4784 "%d.%d not known\n", dacver >> 4, dacver & 0xf); 4785 return -ENOSYS; 4786 } 4787 4788 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]); 4789 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]); 4790 4791 return 0; 4792} 4793 4794static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4795{ 4796 /* 4797 * Parses the LVDS table segment that the bit entry points to. 4798 * Starting at bitentry->offset: 4799 * 4800 * offset + 0 (16 bits): LVDS strap xlate table pointer 4801 */ 4802 4803 if (bitentry->length != 2) { 4804 NV_ERROR(dev, "Do not understand BIT LVDS table\n"); 4805 return -EINVAL; 4806 } 4807 4808 /* 4809 * No idea if it's still called the LVDS manufacturer table, but 4810 * the concept's close enough. 4811 */ 4812 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]); 4813 4814 return 0; 4815} 4816 4817static int 4818parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios, 4819 struct bit_entry *bitentry) 4820{ 4821 /* 4822 * offset + 2 (8 bits): number of options in an 4823 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set 4824 * offset + 3 (16 bits): pointer to strap xlate table for RAM 4825 * restrict option selection 4826 * 4827 * There's a bunch of bits in this table other than the RAM restrict 4828 * stuff that we don't use - their use currently unknown 4829 */ 4830 4831 /* 4832 * Older bios versions don't have a sufficiently long table for 4833 * what we want 4834 */ 4835 if (bitentry->length < 0x5) 4836 return 0; 4837 4838 if (bitentry->id[1] < 2) { 4839 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2]; 4840 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]); 4841 } else { 4842 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0]; 4843 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]); 4844 } 4845 4846 return 0; 4847} 4848 4849static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4850{ 4851 /* 4852 * Parses the pointer to the TMDS table 4853 * 4854 * Starting at bitentry->offset: 4855 * 4856 * offset + 0 (16 bits): TMDS table pointer 4857 * 4858 * The TMDS table is typically found just before the DCB table, with a 4859 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being 4860 * length?) 4861 * 4862 * At offset +7 is a pointer to a script, which I don't know how to 4863 * run yet. 4864 * At offset +9 is a pointer to another script, likewise 4865 * Offset +11 has a pointer to a table where the first word is a pxclk 4866 * frequency and the second word a pointer to a script, which should be 4867 * run if the comparison pxclk frequency is less than the pxclk desired. 4868 * This repeats for decreasing comparison frequencies 4869 * Offset +13 has a pointer to a similar table 4870 * The selection of table (and possibly +7/+9 script) is dictated by 4871 * "or" from the DCB. 4872 */ 4873 4874 uint16_t tmdstableptr, script1, script2; 4875 4876 if (bitentry->length != 2) { 4877 NV_ERROR(dev, "Do not understand BIT TMDS table\n"); 4878 return -EINVAL; 4879 } 4880 4881 tmdstableptr = ROM16(bios->data[bitentry->offset]); 4882 4883 if (tmdstableptr == 0x0) { 4884 NV_ERROR(dev, "Pointer to TMDS table invalid\n"); 4885 return -EINVAL; 4886 } 4887 4888 /* nv50+ has v2.0, but we don't parse it atm */ 4889 if (bios->data[tmdstableptr] != 0x11) { 4890 NV_WARN(dev, 4891 "TMDS table revision %d.%d not currently supported\n", 4892 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf); 4893 return -ENOSYS; 4894 } 4895 4896 /* 4897 * These two scripts are odd: they don't seem to get run even when 4898 * they are not stubbed. 4899 */ 4900 script1 = ROM16(bios->data[tmdstableptr + 7]); 4901 script2 = ROM16(bios->data[tmdstableptr + 9]); 4902 if (bios->data[script1] != 'q' || bios->data[script2] != 'q') 4903 NV_WARN(dev, "TMDS table script pointers not stubbed\n"); 4904 4905 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]); 4906 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]); 4907 4908 return 0; 4909} 4910 4911static int 4912parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios, 4913 struct bit_entry *bitentry) 4914{ 4915 /* 4916 * Parses the pointer to the G80 output script tables 4917 * 4918 * Starting at bitentry->offset: 4919 * 4920 * offset + 0 (16 bits): output script table pointer 4921 */ 4922 4923 uint16_t outputscripttableptr; 4924 4925 if (bitentry->length != 3) { 4926 NV_ERROR(dev, "Do not understand BIT U table\n"); 4927 return -EINVAL; 4928 } 4929 4930 outputscripttableptr = ROM16(bios->data[bitentry->offset]); 4931 bios->display.script_table_ptr = outputscripttableptr; 4932 return 0; 4933} 4934 4935static int 4936parse_bit_displayport_tbl_entry(struct drm_device *dev, struct nvbios *bios, 4937 struct bit_entry *bitentry) 4938{ 4939 bios->display.dp_table_ptr = ROM16(bios->data[bitentry->offset]); 4940 return 0; 4941} 4942 4943struct bit_table { 4944 const char id; 4945 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *); 4946}; 4947 4948#define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry }) 4949 4950static int 4951parse_bit_table(struct nvbios *bios, const uint16_t bitoffset, 4952 struct bit_table *table) 4953{ 4954 struct drm_device *dev = bios->dev; 4955 uint8_t maxentries = bios->data[bitoffset + 4]; 4956 int i, offset; 4957 struct bit_entry bitentry; 4958 4959 for (i = 0, offset = bitoffset + 6; i < maxentries; i++, offset += 6) { 4960 bitentry.id[0] = bios->data[offset]; 4961 4962 if (bitentry.id[0] != table->id) 4963 continue; 4964 4965 bitentry.id[1] = bios->data[offset + 1]; 4966 bitentry.length = ROM16(bios->data[offset + 2]); 4967 bitentry.offset = ROM16(bios->data[offset + 4]); 4968 4969 return table->parse_fn(dev, bios, &bitentry); 4970 } 4971 4972 NV_INFO(dev, "BIT table '%c' not found\n", table->id); 4973 return -ENOSYS; 4974} 4975 4976static int 4977parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset) 4978{ 4979 int ret; 4980 4981 /* 4982 * The only restriction on parsing order currently is having 'i' first 4983 * for use of bios->*_version or bios->feature_byte while parsing; 4984 * functions shouldn't be actually *doing* anything apart from pulling 4985 * data from the image into the bios struct, thus no interdependencies 4986 */ 4987 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i)); 4988 if (ret) /* info? */ 4989 return ret; 4990 if (bios->major_version >= 0x60) /* g80+ */ 4991 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A)); 4992 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C)); 4993 if (ret) 4994 return ret; 4995 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display)); 4996 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init)); 4997 if (ret) 4998 return ret; 4999 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */ 5000 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds)); 5001 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds)); 5002 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U)); 5003 parse_bit_table(bios, bitoffset, &BIT_TABLE('d', displayport)); 5004 5005 return 0; 5006} 5007 5008static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset) 5009{ 5010 /* 5011 * Parses the BMP structure for useful things, but does not act on them 5012 * 5013 * offset + 5: BMP major version 5014 * offset + 6: BMP minor version 5015 * offset + 9: BMP feature byte 5016 * offset + 10: BCD encoded BIOS version 5017 * 5018 * offset + 18: init script table pointer (for bios versions < 5.10h) 5019 * offset + 20: extra init script table pointer (for bios 5020 * versions < 5.10h) 5021 * 5022 * offset + 24: memory init table pointer (used on early bios versions) 5023 * offset + 26: SDR memory sequencing setup data table 5024 * offset + 28: DDR memory sequencing setup data table 5025 * 5026 * offset + 54: index of I2C CRTC pair to use for CRT output 5027 * offset + 55: index of I2C CRTC pair to use for TV output 5028 * offset + 56: index of I2C CRTC pair to use for flat panel output 5029 * offset + 58: write CRTC index for I2C pair 0 5030 * offset + 59: read CRTC index for I2C pair 0 5031 * offset + 60: write CRTC index for I2C pair 1 5032 * offset + 61: read CRTC index for I2C pair 1 5033 * 5034 * offset + 67: maximum internal PLL frequency (single stage PLL) 5035 * offset + 71: minimum internal PLL frequency (single stage PLL) 5036 * 5037 * offset + 75: script table pointers, as described in 5038 * parse_script_table_pointers 5039 * 5040 * offset + 89: TMDS single link output A table pointer 5041 * offset + 91: TMDS single link output B table pointer 5042 * offset + 95: LVDS single link output A table pointer 5043 * offset + 105: flat panel timings table pointer 5044 * offset + 107: flat panel strapping translation table pointer 5045 * offset + 117: LVDS manufacturer panel config table pointer 5046 * offset + 119: LVDS manufacturer strapping translation table pointer 5047 * 5048 * offset + 142: PLL limits table pointer 5049 * 5050 * offset + 156: minimum pixel clock for LVDS dual link 5051 */ 5052 5053 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor; 5054 uint16_t bmplength; 5055 uint16_t legacy_scripts_offset, legacy_i2c_offset; 5056 5057 /* load needed defaults in case we can't parse this info */ 5058 bios->dcb.i2c[0].write = NV_CIO_CRE_DDC_WR__INDEX; 5059 bios->dcb.i2c[0].read = NV_CIO_CRE_DDC_STATUS__INDEX; 5060 bios->dcb.i2c[1].write = NV_CIO_CRE_DDC0_WR__INDEX; 5061 bios->dcb.i2c[1].read = NV_CIO_CRE_DDC0_STATUS__INDEX; 5062 bios->digital_min_front_porch = 0x4b; 5063 bios->fmaxvco = 256000; 5064 bios->fminvco = 128000; 5065 bios->fp.duallink_transition_clk = 90000; 5066 5067 bmp_version_major = bmp[5]; 5068 bmp_version_minor = bmp[6]; 5069 5070 NV_TRACE(dev, "BMP version %d.%d\n", 5071 bmp_version_major, bmp_version_minor); 5072 5073 /* 5074 * Make sure that 0x36 is blank and can't be mistaken for a DCB 5075 * pointer on early versions 5076 */ 5077 if (bmp_version_major < 5) 5078 *(uint16_t *)&bios->data[0x36] = 0; 5079 5080 /* 5081 * Seems that the minor version was 1 for all major versions prior 5082 * to 5. Version 6 could theoretically exist, but I suspect BIT 5083 * happened instead. 5084 */ 5085 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) { 5086 NV_ERROR(dev, "You have an unsupported BMP version. " 5087 "Please send in your bios\n"); 5088 return -ENOSYS; 5089 } 5090 5091 if (bmp_version_major == 0) 5092 /* nothing that's currently useful in this version */ 5093 return 0; 5094 else if (bmp_version_major == 1) 5095 bmplength = 44; /* exact for 1.01 */ 5096 else if (bmp_version_major == 2) 5097 bmplength = 48; /* exact for 2.01 */ 5098 else if (bmp_version_major == 3) 5099 bmplength = 54; 5100 /* guessed - mem init tables added in this version */ 5101 else if (bmp_version_major == 4 || bmp_version_minor < 0x1) 5102 /* don't know if 5.0 exists... */ 5103 bmplength = 62; 5104 /* guessed - BMP I2C indices added in version 4*/ 5105 else if (bmp_version_minor < 0x6) 5106 bmplength = 67; /* exact for 5.01 */ 5107 else if (bmp_version_minor < 0x10) 5108 bmplength = 75; /* exact for 5.06 */ 5109 else if (bmp_version_minor == 0x10) 5110 bmplength = 89; /* exact for 5.10h */ 5111 else if (bmp_version_minor < 0x14) 5112 bmplength = 118; /* exact for 5.11h */ 5113 else if (bmp_version_minor < 0x24) 5114 /* 5115 * Not sure of version where pll limits came in; 5116 * certainly exist by 0x24 though. 5117 */ 5118 /* length not exact: this is long enough to get lvds members */ 5119 bmplength = 123; 5120 else if (bmp_version_minor < 0x27) 5121 /* 5122 * Length not exact: this is long enough to get pll limit 5123 * member 5124 */ 5125 bmplength = 144; 5126 else 5127 /* 5128 * Length not exact: this is long enough to get dual link 5129 * transition clock. 5130 */ 5131 bmplength = 158; 5132 5133 /* checksum */ 5134 if (nv_cksum(bmp, 8)) { 5135 NV_ERROR(dev, "Bad BMP checksum\n"); 5136 return -EINVAL; 5137 } 5138 5139 /* 5140 * Bit 4 seems to indicate either a mobile bios or a quadro card -- 5141 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl 5142 * (not nv10gl), bit 5 that the flat panel tables are present, and 5143 * bit 6 a tv bios. 5144 */ 5145 bios->feature_byte = bmp[9]; 5146 5147 parse_bios_version(dev, bios, offset + 10); 5148 5149 if (bmp_version_major < 5 || bmp_version_minor < 0x10) 5150 bios->old_style_init = true; 5151 legacy_scripts_offset = 18; 5152 if (bmp_version_major < 2) 5153 legacy_scripts_offset -= 4; 5154 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]); 5155 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]); 5156 5157 if (bmp_version_major > 2) { /* appears in BMP 3 */ 5158 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]); 5159 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]); 5160 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]); 5161 } 5162 5163 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */ 5164 if (bmplength > 61) 5165 legacy_i2c_offset = offset + 54; 5166 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset]; 5167 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1]; 5168 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2]; 5169 bios->dcb.i2c[0].write = bios->data[legacy_i2c_offset + 4]; 5170 bios->dcb.i2c[0].read = bios->data[legacy_i2c_offset + 5]; 5171 bios->dcb.i2c[1].write = bios->data[legacy_i2c_offset + 6]; 5172 bios->dcb.i2c[1].read = bios->data[legacy_i2c_offset + 7]; 5173 5174 if (bmplength > 74) { 5175 bios->fmaxvco = ROM32(bmp[67]); 5176 bios->fminvco = ROM32(bmp[71]); 5177 } 5178 if (bmplength > 88) 5179 parse_script_table_pointers(bios, offset + 75); 5180 if (bmplength > 94) { 5181 bios->tmds.output0_script_ptr = ROM16(bmp[89]); 5182 bios->tmds.output1_script_ptr = ROM16(bmp[91]); 5183 /* 5184 * Never observed in use with lvds scripts, but is reused for 5185 * 18/24 bit panel interface default for EDID equipped panels 5186 * (if_is_24bit not set directly to avoid any oscillation). 5187 */ 5188 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]); 5189 } 5190 if (bmplength > 108) { 5191 bios->fp.fptablepointer = ROM16(bmp[105]); 5192 bios->fp.fpxlatetableptr = ROM16(bmp[107]); 5193 bios->fp.xlatwidth = 1; 5194 } 5195 if (bmplength > 120) { 5196 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]); 5197 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]); 5198 } 5199 if (bmplength > 143) 5200 bios->pll_limit_tbl_ptr = ROM16(bmp[142]); 5201 5202 if (bmplength > 157) 5203 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10; 5204 5205 return 0; 5206} 5207 5208static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len) 5209{ 5210 int i, j; 5211 5212 for (i = 0; i <= (n - len); i++) { 5213 for (j = 0; j < len; j++) 5214 if (data[i + j] != str[j]) 5215 break; 5216 if (j == len) 5217 return i; 5218 } 5219 5220 return 0; 5221} 5222 5223static struct dcb_gpio_entry * 5224new_gpio_entry(struct nvbios *bios) 5225{ 5226 struct dcb_gpio_table *gpio = &bios->dcb.gpio; 5227 5228 return &gpio->entry[gpio->entries++]; 5229} 5230 5231struct dcb_gpio_entry * 5232nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag) 5233{ 5234 struct drm_nouveau_private *dev_priv = dev->dev_private; 5235 struct nvbios *bios = &dev_priv->vbios; 5236 int i; 5237 5238 for (i = 0; i < bios->dcb.gpio.entries; i++) { 5239 if (bios->dcb.gpio.entry[i].tag != tag) 5240 continue; 5241 5242 return &bios->dcb.gpio.entry[i]; 5243 } 5244 5245 return NULL; 5246} 5247 5248static void 5249parse_dcb30_gpio_entry(struct nvbios *bios, uint16_t offset) 5250{ 5251 struct dcb_gpio_entry *gpio; 5252 uint16_t ent = ROM16(bios->data[offset]); 5253 uint8_t line = ent & 0x1f, 5254 tag = ent >> 5 & 0x3f, 5255 flags = ent >> 11 & 0x1f; 5256 5257 if (tag == 0x3f) 5258 return; 5259 5260 gpio = new_gpio_entry(bios); 5261 5262 gpio->tag = tag; 5263 gpio->line = line; 5264 gpio->invert = flags != 4; 5265 gpio->entry = ent; 5266} 5267 5268static void 5269parse_dcb40_gpio_entry(struct nvbios *bios, uint16_t offset) 5270{ 5271 uint32_t entry = ROM32(bios->data[offset]); 5272 struct dcb_gpio_entry *gpio; 5273 5274 if ((entry & 0x0000ff00) == 0x0000ff00) 5275 return; 5276 5277 gpio = new_gpio_entry(bios); 5278 gpio->tag = (entry & 0x0000ff00) >> 8; 5279 gpio->line = (entry & 0x0000001f) >> 0; 5280 gpio->state_default = (entry & 0x01000000) >> 24; 5281 gpio->state[0] = (entry & 0x18000000) >> 27; 5282 gpio->state[1] = (entry & 0x60000000) >> 29; 5283 gpio->entry = entry; 5284} 5285 5286static void 5287parse_dcb_gpio_table(struct nvbios *bios) 5288{ 5289 struct drm_device *dev = bios->dev; 5290 uint16_t gpio_table_ptr = bios->dcb.gpio_table_ptr; 5291 uint8_t *gpio_table = &bios->data[gpio_table_ptr]; 5292 int header_len = gpio_table[1], 5293 entries = gpio_table[2], 5294 entry_len = gpio_table[3]; 5295 void (*parse_entry)(struct nvbios *, uint16_t) = NULL; 5296 int i; 5297 5298 if (bios->dcb.version >= 0x40) { 5299 if (gpio_table_ptr && entry_len != 4) { 5300 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n"); 5301 return; 5302 } 5303 5304 parse_entry = parse_dcb40_gpio_entry; 5305 5306 } else if (bios->dcb.version >= 0x30) { 5307 if (gpio_table_ptr && entry_len != 2) { 5308 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n"); 5309 return; 5310 } 5311 5312 parse_entry = parse_dcb30_gpio_entry; 5313 5314 } else if (bios->dcb.version >= 0x22) { 5315 /* 5316 * DCBs older than v3.0 don't really have a GPIO 5317 * table, instead they keep some GPIO info at fixed 5318 * locations. 5319 */ 5320 uint16_t dcbptr = ROM16(bios->data[0x36]); 5321 uint8_t *tvdac_gpio = &bios->data[dcbptr - 5]; 5322 5323 if (tvdac_gpio[0] & 1) { 5324 struct dcb_gpio_entry *gpio = new_gpio_entry(bios); 5325 5326 gpio->tag = DCB_GPIO_TVDAC0; 5327 gpio->line = tvdac_gpio[1] >> 4; 5328 gpio->invert = tvdac_gpio[0] & 2; 5329 } 5330 } 5331 5332 if (!gpio_table_ptr) 5333 return; 5334 5335 if (entries > DCB_MAX_NUM_GPIO_ENTRIES) { 5336 NV_WARN(dev, "Too many entries in the DCB GPIO table.\n"); 5337 entries = DCB_MAX_NUM_GPIO_ENTRIES; 5338 } 5339 5340 for (i = 0; i < entries; i++) 5341 parse_entry(bios, gpio_table_ptr + header_len + entry_len * i); 5342} 5343 5344struct dcb_connector_table_entry * 5345nouveau_bios_connector_entry(struct drm_device *dev, int index) 5346{ 5347 struct drm_nouveau_private *dev_priv = dev->dev_private; 5348 struct nvbios *bios = &dev_priv->vbios; 5349 struct dcb_connector_table_entry *cte; 5350 5351 if (index >= bios->dcb.connector.entries) 5352 return NULL; 5353 5354 cte = &bios->dcb.connector.entry[index]; 5355 if (cte->type == 0xff) 5356 return NULL; 5357 5358 return cte; 5359} 5360 5361static enum dcb_connector_type 5362divine_connector_type(struct nvbios *bios, int index) 5363{ 5364 struct dcb_table *dcb = &bios->dcb; 5365 unsigned encoders = 0, type = DCB_CONNECTOR_NONE; 5366 int i; 5367 5368 for (i = 0; i < dcb->entries; i++) { 5369 if (dcb->entry[i].connector == index) 5370 encoders |= (1 << dcb->entry[i].type); 5371 } 5372 5373 if (encoders & (1 << OUTPUT_DP)) { 5374 if (encoders & (1 << OUTPUT_TMDS)) 5375 type = DCB_CONNECTOR_DP; 5376 else 5377 type = DCB_CONNECTOR_eDP; 5378 } else 5379 if (encoders & (1 << OUTPUT_TMDS)) { 5380 if (encoders & (1 << OUTPUT_ANALOG)) 5381 type = DCB_CONNECTOR_DVI_I; 5382 else 5383 type = DCB_CONNECTOR_DVI_D; 5384 } else 5385 if (encoders & (1 << OUTPUT_ANALOG)) { 5386 type = DCB_CONNECTOR_VGA; 5387 } else 5388 if (encoders & (1 << OUTPUT_LVDS)) { 5389 type = DCB_CONNECTOR_LVDS; 5390 } else 5391 if (encoders & (1 << OUTPUT_TV)) { 5392 type = DCB_CONNECTOR_TV_0; 5393 } 5394 5395 return type; 5396} 5397 5398static void 5399apply_dcb_connector_quirks(struct nvbios *bios, int idx) 5400{ 5401 struct dcb_connector_table_entry *cte = &bios->dcb.connector.entry[idx]; 5402 struct drm_device *dev = bios->dev; 5403 5404 /* Gigabyte NX85T */ 5405 if ((dev->pdev->device == 0x0421) && 5406 (dev->pdev->subsystem_vendor == 0x1458) && 5407 (dev->pdev->subsystem_device == 0x344c)) { 5408 if (cte->type == DCB_CONNECTOR_HDMI_1) 5409 cte->type = DCB_CONNECTOR_DVI_I; 5410 } 5411} 5412 5413static void 5414parse_dcb_connector_table(struct nvbios *bios) 5415{ 5416 struct drm_device *dev = bios->dev; 5417 struct dcb_connector_table *ct = &bios->dcb.connector; 5418 struct dcb_connector_table_entry *cte; 5419 uint8_t *conntab = &bios->data[bios->dcb.connector_table_ptr]; 5420 uint8_t *entry; 5421 int i; 5422 5423 if (!bios->dcb.connector_table_ptr) { 5424 NV_DEBUG_KMS(dev, "No DCB connector table present\n"); 5425 return; 5426 } 5427 5428 NV_INFO(dev, "DCB connector table: VHER 0x%02x %d %d %d\n", 5429 conntab[0], conntab[1], conntab[2], conntab[3]); 5430 if ((conntab[0] != 0x30 && conntab[0] != 0x40) || 5431 (conntab[3] != 2 && conntab[3] != 4)) { 5432 NV_ERROR(dev, " Unknown! Please report.\n"); 5433 return; 5434 } 5435 5436 ct->entries = conntab[2]; 5437 5438 entry = conntab + conntab[1]; 5439 cte = &ct->entry[0]; 5440 for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) { 5441 cte->index = i; 5442 if (conntab[3] == 2) 5443 cte->entry = ROM16(entry[0]); 5444 else 5445 cte->entry = ROM32(entry[0]); 5446 5447 cte->type = (cte->entry & 0x000000ff) >> 0; 5448 cte->index2 = (cte->entry & 0x00000f00) >> 8; 5449 switch (cte->entry & 0x00033000) { 5450 case 0x00001000: 5451 cte->gpio_tag = 0x07; 5452 break; 5453 case 0x00002000: 5454 cte->gpio_tag = 0x08; 5455 break; 5456 case 0x00010000: 5457 cte->gpio_tag = 0x51; 5458 break; 5459 case 0x00020000: 5460 cte->gpio_tag = 0x52; 5461 break; 5462 default: 5463 cte->gpio_tag = 0xff; 5464 break; 5465 } 5466 5467 if (cte->type == 0xff) 5468 continue; 5469 5470 apply_dcb_connector_quirks(bios, i); 5471 5472 NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n", 5473 i, cte->entry, cte->type, cte->index, cte->gpio_tag); 5474 5475 /* check for known types, fallback to guessing the type 5476 * from attached encoders if we hit an unknown. 5477 */ 5478 switch (cte->type) { 5479 case DCB_CONNECTOR_VGA: 5480 case DCB_CONNECTOR_TV_0: 5481 case DCB_CONNECTOR_TV_1: 5482 case DCB_CONNECTOR_TV_3: 5483 case DCB_CONNECTOR_DVI_I: 5484 case DCB_CONNECTOR_DVI_D: 5485 case DCB_CONNECTOR_LVDS: 5486 case DCB_CONNECTOR_DP: 5487 case DCB_CONNECTOR_eDP: 5488 case DCB_CONNECTOR_HDMI_0: 5489 case DCB_CONNECTOR_HDMI_1: 5490 break; 5491 default: 5492 cte->type = divine_connector_type(bios, cte->index); 5493 NV_WARN(dev, "unknown type, using 0x%02x\n", cte->type); 5494 break; 5495 } 5496 5497 if (nouveau_override_conntype) { 5498 int type = divine_connector_type(bios, cte->index); 5499 if (type != cte->type) 5500 NV_WARN(dev, " -> type 0x%02x\n", cte->type); 5501 } 5502 5503 } 5504} 5505 5506static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb) 5507{ 5508 struct dcb_entry *entry = &dcb->entry[dcb->entries]; 5509 5510 memset(entry, 0, sizeof(struct dcb_entry)); 5511 entry->index = dcb->entries++; 5512 5513 return entry; 5514} 5515 5516static void fabricate_vga_output(struct dcb_table *dcb, int i2c, int heads) 5517{ 5518 struct dcb_entry *entry = new_dcb_entry(dcb); 5519 5520 entry->type = 0; 5521 entry->i2c_index = i2c; 5522 entry->heads = heads; 5523 entry->location = DCB_LOC_ON_CHIP; 5524 /* "or" mostly unused in early gen crt modesetting, 0 is fine */ 5525} 5526 5527static void fabricate_dvi_i_output(struct dcb_table *dcb, bool twoHeads) 5528{ 5529 struct dcb_entry *entry = new_dcb_entry(dcb); 5530 5531 entry->type = 2; 5532 entry->i2c_index = LEGACY_I2C_PANEL; 5533 entry->heads = twoHeads ? 3 : 1; 5534 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */ 5535 entry->or = 1; /* means |0x10 gets set on CRE_LCD__INDEX */ 5536 entry->duallink_possible = false; /* SiI164 and co. are single link */ 5537 5538#if 0 5539 /* 5540 * For dvi-a either crtc probably works, but my card appears to only 5541 * support dvi-d. "nvidia" still attempts to program it for dvi-a, 5542 * doing the full fp output setup (program 0x6808.. fp dimension regs, 5543 * setting 0x680848 to 0x10000111 to enable, maybe setting 0x680880); 5544 * the monitor picks up the mode res ok and lights up, but no pixel 5545 * data appears, so the board manufacturer probably connected up the 5546 * sync lines, but missed the video traces / components 5547 * 5548 * with this introduction, dvi-a left as an exercise for the reader. 5549 */ 5550 fabricate_vga_output(dcb, LEGACY_I2C_PANEL, entry->heads); 5551#endif 5552} 5553 5554static void fabricate_tv_output(struct dcb_table *dcb, bool twoHeads) 5555{ 5556 struct dcb_entry *entry = new_dcb_entry(dcb); 5557 5558 entry->type = 1; 5559 entry->i2c_index = LEGACY_I2C_TV; 5560 entry->heads = twoHeads ? 3 : 1; 5561 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */ 5562} 5563 5564static bool 5565parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb, 5566 uint32_t conn, uint32_t conf, struct dcb_entry *entry) 5567{ 5568 entry->type = conn & 0xf; 5569 entry->i2c_index = (conn >> 4) & 0xf; 5570 entry->heads = (conn >> 8) & 0xf; 5571 if (dcb->version >= 0x40) 5572 entry->connector = (conn >> 12) & 0xf; 5573 entry->bus = (conn >> 16) & 0xf; 5574 entry->location = (conn >> 20) & 0x3; 5575 entry->or = (conn >> 24) & 0xf; 5576 5577 switch (entry->type) { 5578 case OUTPUT_ANALOG: 5579 /* 5580 * Although the rest of a CRT conf dword is usually 5581 * zeros, mac biosen have stuff there so we must mask 5582 */ 5583 entry->crtconf.maxfreq = (dcb->version < 0x30) ? 5584 (conf & 0xffff) * 10 : 5585 (conf & 0xff) * 10000; 5586 break; 5587 case OUTPUT_LVDS: 5588 { 5589 uint32_t mask; 5590 if (conf & 0x1) 5591 entry->lvdsconf.use_straps_for_mode = true; 5592 if (dcb->version < 0x22) { 5593 mask = ~0xd; 5594 /* 5595 * The laptop in bug 14567 lies and claims to not use 5596 * straps when it does, so assume all DCB 2.0 laptops 5597 * use straps, until a broken EDID using one is produced 5598 */ 5599 entry->lvdsconf.use_straps_for_mode = true; 5600 /* 5601 * Both 0x4 and 0x8 show up in v2.0 tables; assume they 5602 * mean the same thing (probably wrong, but might work) 5603 */ 5604 if (conf & 0x4 || conf & 0x8) 5605 entry->lvdsconf.use_power_scripts = true; 5606 } else { 5607 mask = ~0x5; 5608 if (conf & 0x4) 5609 entry->lvdsconf.use_power_scripts = true; 5610 } 5611 if (conf & mask) { 5612 /* 5613 * Until we even try to use these on G8x, it's 5614 * useless reporting unknown bits. They all are. 5615 */ 5616 if (dcb->version >= 0x40) 5617 break; 5618 5619 NV_ERROR(dev, "Unknown LVDS configuration bits, " 5620 "please report\n"); 5621 } 5622 break; 5623 } 5624 case OUTPUT_TV: 5625 { 5626 if (dcb->version >= 0x30) 5627 entry->tvconf.has_component_output = conf & (0x8 << 4); 5628 else 5629 entry->tvconf.has_component_output = false; 5630 5631 break; 5632 } 5633 case OUTPUT_DP: 5634 entry->dpconf.sor.link = (conf & 0x00000030) >> 4; 5635 entry->dpconf.link_bw = (conf & 0x00e00000) >> 21; 5636 switch ((conf & 0x0f000000) >> 24) { 5637 case 0xf: 5638 entry->dpconf.link_nr = 4; 5639 break; 5640 case 0x3: 5641 entry->dpconf.link_nr = 2; 5642 break; 5643 default: 5644 entry->dpconf.link_nr = 1; 5645 break; 5646 } 5647 break; 5648 case OUTPUT_TMDS: 5649 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4; 5650 break; 5651 case 0xe: 5652 /* weird g80 mobile type that "nv" treats as a terminator */ 5653 dcb->entries--; 5654 return false; 5655 default: 5656 break; 5657 } 5658 5659 if (dcb->version < 0x40) { 5660 /* Normal entries consist of a single bit, but dual link has 5661 * the next most significant bit set too 5662 */ 5663 entry->duallink_possible = 5664 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or); 5665 } else { 5666 entry->duallink_possible = (entry->sorconf.link == 3); 5667 } 5668 5669 /* unsure what DCB version introduces this, 3.0? */ 5670 if (conf & 0x100000) 5671 entry->i2c_upper_default = true; 5672 5673 return true; 5674} 5675 5676static bool 5677parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb, 5678 uint32_t conn, uint32_t conf, struct dcb_entry *entry) 5679{ 5680 switch (conn & 0x0000000f) { 5681 case 0: 5682 entry->type = OUTPUT_ANALOG; 5683 break; 5684 case 1: 5685 entry->type = OUTPUT_TV; 5686 break; 5687 case 2: 5688 case 3: 5689 entry->type = OUTPUT_LVDS; 5690 break; 5691 case 4: 5692 switch ((conn & 0x000000f0) >> 4) { 5693 case 0: 5694 entry->type = OUTPUT_TMDS; 5695 break; 5696 case 1: 5697 entry->type = OUTPUT_LVDS; 5698 break; 5699 default: 5700 NV_ERROR(dev, "Unknown DCB subtype 4/%d\n", 5701 (conn & 0x000000f0) >> 4); 5702 return false; 5703 } 5704 break; 5705 default: 5706 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f); 5707 return false; 5708 } 5709 5710 entry->i2c_index = (conn & 0x0003c000) >> 14; 5711 entry->heads = ((conn & 0x001c0000) >> 18) + 1; 5712 entry->or = entry->heads; /* same as heads, hopefully safe enough */ 5713 entry->location = (conn & 0x01e00000) >> 21; 5714 entry->bus = (conn & 0x0e000000) >> 25; 5715 entry->duallink_possible = false; 5716 5717 switch (entry->type) { 5718 case OUTPUT_ANALOG: 5719 entry->crtconf.maxfreq = (conf & 0xffff) * 10; 5720 break; 5721 case OUTPUT_TV: 5722 entry->tvconf.has_component_output = false; 5723 break; 5724 case OUTPUT_TMDS: 5725 /* 5726 * Invent a DVI-A output, by copying the fields of the DVI-D 5727 * output; reported to work by math_b on an NV20(!). 5728 */ 5729 fabricate_vga_output(dcb, entry->i2c_index, entry->heads); 5730 break; 5731 case OUTPUT_LVDS: 5732 if ((conn & 0x00003f00) != 0x10) 5733 entry->lvdsconf.use_straps_for_mode = true; 5734 entry->lvdsconf.use_power_scripts = true; 5735 break; 5736 default: 5737 break; 5738 } 5739 5740 return true; 5741} 5742 5743static bool parse_dcb_entry(struct drm_device *dev, struct dcb_table *dcb, 5744 uint32_t conn, uint32_t conf) 5745{ 5746 struct dcb_entry *entry = new_dcb_entry(dcb); 5747 bool ret; 5748 5749 if (dcb->version >= 0x20) 5750 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry); 5751 else 5752 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry); 5753 if (!ret) 5754 return ret; 5755 5756 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table, 5757 entry->i2c_index, &dcb->i2c[entry->i2c_index]); 5758 5759 return true; 5760} 5761 5762static 5763void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb) 5764{ 5765 /* 5766 * DCB v2.0 lists each output combination separately. 5767 * Here we merge compatible entries to have fewer outputs, with 5768 * more options 5769 */ 5770 5771 int i, newentries = 0; 5772 5773 for (i = 0; i < dcb->entries; i++) { 5774 struct dcb_entry *ient = &dcb->entry[i]; 5775 int j; 5776 5777 for (j = i + 1; j < dcb->entries; j++) { 5778 struct dcb_entry *jent = &dcb->entry[j]; 5779 5780 if (jent->type == 100) /* already merged entry */ 5781 continue; 5782 5783 /* merge heads field when all other fields the same */ 5784 if (jent->i2c_index == ient->i2c_index && 5785 jent->type == ient->type && 5786 jent->location == ient->location && 5787 jent->or == ient->or) { 5788 NV_TRACE(dev, "Merging DCB entries %d and %d\n", 5789 i, j); 5790 ient->heads |= jent->heads; 5791 jent->type = 100; /* dummy value */ 5792 } 5793 } 5794 } 5795 5796 /* Compact entries merged into others out of dcb */ 5797 for (i = 0; i < dcb->entries; i++) { 5798 if (dcb->entry[i].type == 100) 5799 continue; 5800 5801 if (newentries != i) { 5802 dcb->entry[newentries] = dcb->entry[i]; 5803 dcb->entry[newentries].index = newentries; 5804 } 5805 newentries++; 5806 } 5807 5808 dcb->entries = newentries; 5809} 5810 5811static int 5812parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads) 5813{ 5814 struct drm_nouveau_private *dev_priv = dev->dev_private; 5815 struct dcb_table *dcb = &bios->dcb; 5816 uint16_t dcbptr = 0, i2ctabptr = 0; 5817 uint8_t *dcbtable; 5818 uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES; 5819 bool configblock = true; 5820 int recordlength = 8, confofs = 4; 5821 int i; 5822 5823 /* get the offset from 0x36 */ 5824 if (dev_priv->card_type > NV_04) { 5825 dcbptr = ROM16(bios->data[0x36]); 5826 if (dcbptr == 0x0000) 5827 NV_WARN(dev, "No output data (DCB) found in BIOS\n"); 5828 } 5829 5830 /* this situation likely means a really old card, pre DCB */ 5831 if (dcbptr == 0x0) { 5832 NV_INFO(dev, "Assuming a CRT output exists\n"); 5833 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1); 5834 5835 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0) 5836 fabricate_tv_output(dcb, twoHeads); 5837 5838 return 0; 5839 } 5840 5841 dcbtable = &bios->data[dcbptr]; 5842 5843 /* get DCB version */ 5844 dcb->version = dcbtable[0]; 5845 NV_TRACE(dev, "Found Display Configuration Block version %d.%d\n", 5846 dcb->version >> 4, dcb->version & 0xf); 5847 5848 if (dcb->version >= 0x20) { /* NV17+ */ 5849 uint32_t sig; 5850 5851 if (dcb->version >= 0x30) { /* NV40+ */ 5852 headerlen = dcbtable[1]; 5853 entries = dcbtable[2]; 5854 recordlength = dcbtable[3]; 5855 i2ctabptr = ROM16(dcbtable[4]); 5856 sig = ROM32(dcbtable[6]); 5857 dcb->gpio_table_ptr = ROM16(dcbtable[10]); 5858 dcb->connector_table_ptr = ROM16(dcbtable[20]); 5859 } else { 5860 i2ctabptr = ROM16(dcbtable[2]); 5861 sig = ROM32(dcbtable[4]); 5862 headerlen = 8; 5863 } 5864 5865 if (sig != 0x4edcbdcb) { 5866 NV_ERROR(dev, "Bad Display Configuration Block " 5867 "signature (%08X)\n", sig); 5868 return -EINVAL; 5869 } 5870 } else if (dcb->version >= 0x15) { /* some NV11 and NV20 */ 5871 char sig[8] = { 0 }; 5872 5873 strncpy(sig, (char *)&dcbtable[-7], 7); 5874 i2ctabptr = ROM16(dcbtable[2]); 5875 recordlength = 10; 5876 confofs = 6; 5877 5878 if (strcmp(sig, "DEV_REC")) { 5879 NV_ERROR(dev, "Bad Display Configuration Block " 5880 "signature (%s)\n", sig); 5881 return -EINVAL; 5882 } 5883 } else { 5884 /* 5885 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always 5886 * has the same single (crt) entry, even when tv-out present, so 5887 * the conclusion is this version cannot really be used. 5888 * v1.2 tables (some NV6/10, and NV15+) normally have the same 5889 * 5 entries, which are not specific to the card and so no use. 5890 * v1.2 does have an I2C table that read_dcb_i2c_table can 5891 * handle, but cards exist (nv11 in #14821) with a bad i2c table 5892 * pointer, so use the indices parsed in parse_bmp_structure. 5893 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful 5894 */ 5895 NV_TRACEWARN(dev, "No useful information in BIOS output table; " 5896 "adding all possible outputs\n"); 5897 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1); 5898 5899 /* 5900 * Attempt to detect TV before DVI because the test 5901 * for the former is more accurate and it rules the 5902 * latter out. 5903 */ 5904 if (nv04_tv_identify(dev, 5905 bios->legacy.i2c_indices.tv) >= 0) 5906 fabricate_tv_output(dcb, twoHeads); 5907 5908 else if (bios->tmds.output0_script_ptr || 5909 bios->tmds.output1_script_ptr) 5910 fabricate_dvi_i_output(dcb, twoHeads); 5911 5912 return 0; 5913 } 5914 5915 if (!i2ctabptr) 5916 NV_WARN(dev, "No pointer to DCB I2C port table\n"); 5917 else { 5918 dcb->i2c_table = &bios->data[i2ctabptr]; 5919 if (dcb->version >= 0x30) 5920 dcb->i2c_default_indices = dcb->i2c_table[4]; 5921 } 5922 5923 if (entries > DCB_MAX_NUM_ENTRIES) 5924 entries = DCB_MAX_NUM_ENTRIES; 5925 5926 for (i = 0; i < entries; i++) { 5927 uint32_t connection, config = 0; 5928 5929 connection = ROM32(dcbtable[headerlen + recordlength * i]); 5930 if (configblock) 5931 config = ROM32(dcbtable[headerlen + confofs + recordlength * i]); 5932 5933 /* seen on an NV11 with DCB v1.5 */ 5934 if (connection == 0x00000000) 5935 break; 5936 5937 /* seen on an NV17 with DCB v2.0 */ 5938 if (connection == 0xffffffff) 5939 break; 5940 5941 if ((connection & 0x0000000f) == 0x0000000f) 5942 continue; 5943 5944 NV_TRACEWARN(dev, "Raw DCB entry %d: %08x %08x\n", 5945 dcb->entries, connection, config); 5946 5947 if (!parse_dcb_entry(dev, dcb, connection, config)) 5948 break; 5949 } 5950 5951 /* 5952 * apart for v2.1+ not being known for requiring merging, this 5953 * guarantees dcbent->index is the index of the entry in the rom image 5954 */ 5955 if (dcb->version < 0x21) 5956 merge_like_dcb_entries(dev, dcb); 5957 5958 if (!dcb->entries) 5959 return -ENXIO; 5960 5961 parse_dcb_gpio_table(bios); 5962 parse_dcb_connector_table(bios); 5963 return 0; 5964} 5965 5966static void 5967fixup_legacy_connector(struct nvbios *bios) 5968{ 5969 struct dcb_table *dcb = &bios->dcb; 5970 int i, i2c, i2c_conn[DCB_MAX_NUM_I2C_ENTRIES] = { }; 5971 5972 /* 5973 * DCB 3.0 also has the table in most cases, but there are some cards 5974 * where the table is filled with stub entries, and the DCB entriy 5975 * indices are all 0. We don't need the connector indices on pre-G80 5976 * chips (yet?) so limit the use to DCB 4.0 and above. 5977 */ 5978 if (dcb->version >= 0x40) 5979 return; 5980 5981 dcb->connector.entries = 0; 5982 5983 /* 5984 * No known connector info before v3.0, so make it up. the rule here 5985 * is: anything on the same i2c bus is considered to be on the same 5986 * connector. any output without an associated i2c bus is assigned 5987 * its own unique connector index. 5988 */ 5989 for (i = 0; i < dcb->entries; i++) { 5990 /* 5991 * Ignore the I2C index for on-chip TV-out, as there 5992 * are cards with bogus values (nv31m in bug 23212), 5993 * and it's otherwise useless. 5994 */ 5995 if (dcb->entry[i].type == OUTPUT_TV && 5996 dcb->entry[i].location == DCB_LOC_ON_CHIP) 5997 dcb->entry[i].i2c_index = 0xf; 5998 i2c = dcb->entry[i].i2c_index; 5999 6000 if (i2c_conn[i2c]) { 6001 dcb->entry[i].connector = i2c_conn[i2c] - 1; 6002 continue; 6003 } 6004 6005 dcb->entry[i].connector = dcb->connector.entries++; 6006 if (i2c != 0xf) 6007 i2c_conn[i2c] = dcb->connector.entries; 6008 } 6009 6010 /* Fake the connector table as well as just connector indices */ 6011 for (i = 0; i < dcb->connector.entries; i++) { 6012 dcb->connector.entry[i].index = i; 6013 dcb->connector.entry[i].type = divine_connector_type(bios, i); 6014 dcb->connector.entry[i].gpio_tag = 0xff; 6015 } 6016} 6017 6018static void 6019fixup_legacy_i2c(struct nvbios *bios) 6020{ 6021 struct dcb_table *dcb = &bios->dcb; 6022 int i; 6023 6024 for (i = 0; i < dcb->entries; i++) { 6025 if (dcb->entry[i].i2c_index == LEGACY_I2C_CRT) 6026 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.crt; 6027 if (dcb->entry[i].i2c_index == LEGACY_I2C_PANEL) 6028 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.panel; 6029 if (dcb->entry[i].i2c_index == LEGACY_I2C_TV) 6030 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.tv; 6031 } 6032} 6033 6034static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry) 6035{ 6036 /* 6037 * The header following the "HWSQ" signature has the number of entries, 6038 * and the entry size 6039 * 6040 * An entry consists of a dword to write to the sequencer control reg 6041 * (0x00001304), followed by the ucode bytes, written sequentially, 6042 * starting at reg 0x00001400 6043 */ 6044 6045 uint8_t bytes_to_write; 6046 uint16_t hwsq_entry_offset; 6047 int i; 6048 6049 if (bios->data[hwsq_offset] <= entry) { 6050 NV_ERROR(dev, "Too few entries in HW sequencer table for " 6051 "requested entry\n"); 6052 return -ENOENT; 6053 } 6054 6055 bytes_to_write = bios->data[hwsq_offset + 1]; 6056 6057 if (bytes_to_write != 36) { 6058 NV_ERROR(dev, "Unknown HW sequencer entry size\n"); 6059 return -EINVAL; 6060 } 6061 6062 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n"); 6063 6064 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write; 6065 6066 /* set sequencer control */ 6067 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset])); 6068 bytes_to_write -= 4; 6069 6070 /* write ucode */ 6071 for (i = 0; i < bytes_to_write; i += 4) 6072 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4])); 6073 6074 /* twiddle NV_PBUS_DEBUG_4 */ 6075 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18); 6076 6077 return 0; 6078} 6079 6080static int load_nv17_hw_sequencer_ucode(struct drm_device *dev, 6081 struct nvbios *bios) 6082{ 6083 /* 6084 * BMP based cards, from NV17, need a microcode loading to correctly 6085 * control the GPIO etc for LVDS panels 6086 * 6087 * BIT based cards seem to do this directly in the init scripts 6088 * 6089 * The microcode entries are found by the "HWSQ" signature. 6090 */ 6091 6092 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' }; 6093 const int sz = sizeof(hwsq_signature); 6094 int hwsq_offset; 6095 6096 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz); 6097 if (!hwsq_offset) 6098 return 0; 6099 6100 /* always use entry 0? */ 6101 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0); 6102} 6103 6104uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev) 6105{ 6106 struct drm_nouveau_private *dev_priv = dev->dev_private; 6107 struct nvbios *bios = &dev_priv->vbios; 6108 const uint8_t edid_sig[] = { 6109 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 }; 6110 uint16_t offset = 0; 6111 uint16_t newoffset; 6112 int searchlen = NV_PROM_SIZE; 6113 6114 if (bios->fp.edid) 6115 return bios->fp.edid; 6116 6117 while (searchlen) { 6118 newoffset = findstr(&bios->data[offset], searchlen, 6119 edid_sig, 8); 6120 if (!newoffset) 6121 return NULL; 6122 offset += newoffset; 6123 if (!nv_cksum(&bios->data[offset], EDID1_LEN)) 6124 break; 6125 6126 searchlen -= offset; 6127 offset++; 6128 } 6129 6130 NV_TRACE(dev, "Found EDID in BIOS\n"); 6131 6132 return bios->fp.edid = &bios->data[offset]; 6133} 6134 6135void 6136nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table, 6137 struct dcb_entry *dcbent) 6138{ 6139 struct drm_nouveau_private *dev_priv = dev->dev_private; 6140 struct nvbios *bios = &dev_priv->vbios; 6141 struct init_exec iexec = { true, false }; 6142 6143 mutex_lock(&bios->lock); 6144 bios->display.output = dcbent; 6145 parse_init_table(bios, table, &iexec); 6146 bios->display.output = NULL; 6147 mutex_unlock(&bios->lock); 6148} 6149 6150static bool NVInitVBIOS(struct drm_device *dev) 6151{ 6152 struct drm_nouveau_private *dev_priv = dev->dev_private; 6153 struct nvbios *bios = &dev_priv->vbios; 6154 6155 memset(bios, 0, sizeof(struct nvbios)); 6156 mutex_init(&bios->lock); 6157 bios->dev = dev; 6158 6159 if (!NVShadowVBIOS(dev, bios->data)) 6160 return false; 6161 6162 bios->length = NV_PROM_SIZE; 6163 return true; 6164} 6165 6166static int nouveau_parse_vbios_struct(struct drm_device *dev) 6167{ 6168 struct drm_nouveau_private *dev_priv = dev->dev_private; 6169 struct nvbios *bios = &dev_priv->vbios; 6170 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' }; 6171 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 }; 6172 int offset; 6173 6174 offset = findstr(bios->data, bios->length, 6175 bit_signature, sizeof(bit_signature)); 6176 if (offset) { 6177 NV_TRACE(dev, "BIT BIOS found\n"); 6178 return parse_bit_structure(bios, offset + 6); 6179 } 6180 6181 offset = findstr(bios->data, bios->length, 6182 bmp_signature, sizeof(bmp_signature)); 6183 if (offset) { 6184 NV_TRACE(dev, "BMP BIOS found\n"); 6185 return parse_bmp_structure(dev, bios, offset); 6186 } 6187 6188 NV_ERROR(dev, "No known BIOS signature found\n"); 6189 return -ENODEV; 6190} 6191 6192int 6193nouveau_run_vbios_init(struct drm_device *dev) 6194{ 6195 struct drm_nouveau_private *dev_priv = dev->dev_private; 6196 struct nvbios *bios = &dev_priv->vbios; 6197 int i, ret = 0; 6198 6199 NVLockVgaCrtcs(dev, false); 6200 if (nv_two_heads(dev)) 6201 NVSetOwner(dev, bios->state.crtchead); 6202 6203 if (bios->major_version < 5) /* BMP only */ 6204 load_nv17_hw_sequencer_ucode(dev, bios); 6205 6206 if (bios->execute) { 6207 bios->fp.last_script_invoc = 0; 6208 bios->fp.lvds_init_run = false; 6209 } 6210 6211 parse_init_tables(bios); 6212 6213 /* 6214 * Runs some additional script seen on G8x VBIOSen. The VBIOS' 6215 * parser will run this right after the init tables, the binary 6216 * driver appears to run it at some point later. 6217 */ 6218 if (bios->some_script_ptr) { 6219 struct init_exec iexec = {true, false}; 6220 6221 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n", 6222 bios->some_script_ptr); 6223 parse_init_table(bios, bios->some_script_ptr, &iexec); 6224 } 6225 6226 if (dev_priv->card_type >= NV_50) { 6227 for (i = 0; i < bios->dcb.entries; i++) { 6228 nouveau_bios_run_display_table(dev, 6229 &bios->dcb.entry[i], 6230 0, 0); 6231 } 6232 } 6233 6234 NVLockVgaCrtcs(dev, true); 6235 6236 return ret; 6237} 6238 6239static void 6240nouveau_bios_i2c_devices_takedown(struct drm_device *dev) 6241{ 6242 struct drm_nouveau_private *dev_priv = dev->dev_private; 6243 struct nvbios *bios = &dev_priv->vbios; 6244 struct dcb_i2c_entry *entry; 6245 int i; 6246 6247 entry = &bios->dcb.i2c[0]; 6248 for (i = 0; i < DCB_MAX_NUM_I2C_ENTRIES; i++, entry++) 6249 nouveau_i2c_fini(dev, entry); 6250} 6251 6252static bool 6253nouveau_bios_posted(struct drm_device *dev) 6254{ 6255 struct drm_nouveau_private *dev_priv = dev->dev_private; 6256 bool was_locked; 6257 unsigned htotal; 6258 6259 if (dev_priv->chipset >= NV_50) { 6260 if (NVReadVgaCrtc(dev, 0, 0x00) == 0 && 6261 NVReadVgaCrtc(dev, 0, 0x1a) == 0) 6262 return false; 6263 return true; 6264 } 6265 6266 was_locked = NVLockVgaCrtcs(dev, false); 6267 htotal = NVReadVgaCrtc(dev, 0, 0x06); 6268 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8; 6269 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4; 6270 htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10; 6271 htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11; 6272 NVLockVgaCrtcs(dev, was_locked); 6273 return (htotal != 0); 6274} 6275 6276int 6277nouveau_bios_init(struct drm_device *dev) 6278{ 6279 struct drm_nouveau_private *dev_priv = dev->dev_private; 6280 struct nvbios *bios = &dev_priv->vbios; 6281 uint32_t saved_nv_pextdev_boot_0; 6282 bool was_locked; 6283 int ret; 6284 6285 if (!NVInitVBIOS(dev)) 6286 return -ENODEV; 6287 6288 ret = nouveau_parse_vbios_struct(dev); 6289 if (ret) 6290 return ret; 6291 6292 ret = parse_dcb_table(dev, bios, nv_two_heads(dev)); 6293 if (ret) 6294 return ret; 6295 6296 fixup_legacy_i2c(bios); 6297 fixup_legacy_connector(bios); 6298 6299 if (!bios->major_version) /* we don't run version 0 bios */ 6300 return 0; 6301 6302 /* these will need remembering across a suspend */ 6303 saved_nv_pextdev_boot_0 = bios_rd32(bios, NV_PEXTDEV_BOOT_0); 6304 bios->state.saved_nv_pfb_cfg0 = bios_rd32(bios, NV_PFB_CFG0); 6305 6306 /* init script execution disabled */ 6307 bios->execute = false; 6308 6309 /* ... unless card isn't POSTed already */ 6310 if (!nouveau_bios_posted(dev)) { 6311 NV_INFO(dev, "Adaptor not initialised\n"); 6312 if (dev_priv->card_type < NV_40) { 6313 NV_ERROR(dev, "Unable to POST this chipset\n"); 6314 return -ENODEV; 6315 } 6316 6317 NV_INFO(dev, "Running VBIOS init tables\n"); 6318 bios->execute = true; 6319 } 6320 6321 bios_wr32(bios, NV_PEXTDEV_BOOT_0, saved_nv_pextdev_boot_0); 6322 6323 ret = nouveau_run_vbios_init(dev); 6324 if (ret) 6325 return ret; 6326 6327 /* feature_byte on BMP is poor, but init always sets CR4B */ 6328 was_locked = NVLockVgaCrtcs(dev, false); 6329 if (bios->major_version < 5) 6330 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40; 6331 6332 /* all BIT systems need p_f_m_t for digital_min_front_porch */ 6333 if (bios->is_mobile || bios->major_version >= 5) 6334 ret = parse_fp_mode_table(dev, bios); 6335 NVLockVgaCrtcs(dev, was_locked); 6336 6337 /* allow subsequent scripts to execute */ 6338 bios->execute = true; 6339 6340 return 0; 6341} 6342 6343void 6344nouveau_bios_takedown(struct drm_device *dev) 6345{ 6346 nouveau_bios_i2c_devices_takedown(dev); 6347} 6348