nouveau_bios.c revision 309b8c89c8ddf9dd8e5f253c185d6af1d0358a79
1/* 2 * Copyright 2005-2006 Erik Waling 3 * Copyright 2006 Stephane Marchesin 4 * Copyright 2007-2009 Stuart Bennett 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 25#include "drmP.h" 26#define NV_DEBUG_NOTRACE 27#include "nouveau_drv.h" 28#include "nouveau_hw.h" 29#include "nouveau_encoder.h" 30 31/* these defines are made up */ 32#define NV_CIO_CRE_44_HEADA 0x0 33#define NV_CIO_CRE_44_HEADB 0x3 34#define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */ 35#define LEGACY_I2C_CRT 0x80 36#define LEGACY_I2C_PANEL 0x81 37#define LEGACY_I2C_TV 0x82 38 39#define EDID1_LEN 128 40 41#define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg) 42#define LOG_OLD_VALUE(x) 43 44#define ROM16(x) le16_to_cpu(*(uint16_t *)&(x)) 45#define ROM32(x) le32_to_cpu(*(uint32_t *)&(x)) 46 47struct init_exec { 48 bool execute; 49 bool repeat; 50}; 51 52static bool nv_cksum(const uint8_t *data, unsigned int length) 53{ 54 /* 55 * There's a few checksums in the BIOS, so here's a generic checking 56 * function. 57 */ 58 int i; 59 uint8_t sum = 0; 60 61 for (i = 0; i < length; i++) 62 sum += data[i]; 63 64 if (sum) 65 return true; 66 67 return false; 68} 69 70static int 71score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable) 72{ 73 if (!(data[0] == 0x55 && data[1] == 0xAA)) { 74 NV_TRACEWARN(dev, "... BIOS signature not found\n"); 75 return 0; 76 } 77 78 if (nv_cksum(data, data[2] * 512)) { 79 NV_TRACEWARN(dev, "... BIOS checksum invalid\n"); 80 /* if a ro image is somewhat bad, it's probably all rubbish */ 81 return writeable ? 2 : 1; 82 } else 83 NV_TRACE(dev, "... appears to be valid\n"); 84 85 return 3; 86} 87 88static void load_vbios_prom(struct drm_device *dev, uint8_t *data) 89{ 90 struct drm_nouveau_private *dev_priv = dev->dev_private; 91 uint32_t pci_nv_20, save_pci_nv_20; 92 int pcir_ptr; 93 int i; 94 95 if (dev_priv->card_type >= NV_50) 96 pci_nv_20 = 0x88050; 97 else 98 pci_nv_20 = NV_PBUS_PCI_NV_20; 99 100 /* enable ROM access */ 101 save_pci_nv_20 = nvReadMC(dev, pci_nv_20); 102 nvWriteMC(dev, pci_nv_20, 103 save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED); 104 105 /* bail if no rom signature */ 106 if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 || 107 nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa) 108 goto out; 109 110 /* additional check (see note below) - read PCI record header */ 111 pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) | 112 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8; 113 if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' || 114 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' || 115 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' || 116 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R') 117 goto out; 118 119 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a 120 * a good read may be obtained by waiting or re-reading (cargocult: 5x) 121 * each byte. we'll hope pramin has something usable instead 122 */ 123 for (i = 0; i < NV_PROM_SIZE; i++) 124 data[i] = nv_rd08(dev, NV_PROM_OFFSET + i); 125 126out: 127 /* disable ROM access */ 128 nvWriteMC(dev, pci_nv_20, 129 save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED); 130} 131 132static void load_vbios_pramin(struct drm_device *dev, uint8_t *data) 133{ 134 struct drm_nouveau_private *dev_priv = dev->dev_private; 135 uint32_t old_bar0_pramin = 0; 136 int i; 137 138 if (dev_priv->card_type >= NV_50) { 139 uint32_t vbios_vram = (nv_rd32(dev, 0x619f04) & ~0xff) << 8; 140 141 if (!vbios_vram) 142 vbios_vram = (nv_rd32(dev, 0x1700) << 16) + 0xf0000; 143 144 old_bar0_pramin = nv_rd32(dev, 0x1700); 145 nv_wr32(dev, 0x1700, vbios_vram >> 16); 146 } 147 148 /* bail if no rom signature */ 149 if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 || 150 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa) 151 goto out; 152 153 for (i = 0; i < NV_PROM_SIZE; i++) 154 data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i); 155 156out: 157 if (dev_priv->card_type >= NV_50) 158 nv_wr32(dev, 0x1700, old_bar0_pramin); 159} 160 161static void load_vbios_pci(struct drm_device *dev, uint8_t *data) 162{ 163 void __iomem *rom = NULL; 164 size_t rom_len; 165 int ret; 166 167 ret = pci_enable_rom(dev->pdev); 168 if (ret) 169 return; 170 171 rom = pci_map_rom(dev->pdev, &rom_len); 172 if (!rom) 173 goto out; 174 memcpy_fromio(data, rom, rom_len); 175 pci_unmap_rom(dev->pdev, rom); 176 177out: 178 pci_disable_rom(dev->pdev); 179} 180 181static void load_vbios_acpi(struct drm_device *dev, uint8_t *data) 182{ 183 int i; 184 int ret; 185 int size = 64 * 1024; 186 187 if (!nouveau_acpi_rom_supported(dev->pdev)) 188 return; 189 190 for (i = 0; i < (size / ROM_BIOS_PAGE); i++) { 191 ret = nouveau_acpi_get_bios_chunk(data, 192 (i * ROM_BIOS_PAGE), 193 ROM_BIOS_PAGE); 194 if (ret <= 0) 195 break; 196 } 197 return; 198} 199 200struct methods { 201 const char desc[8]; 202 void (*loadbios)(struct drm_device *, uint8_t *); 203 const bool rw; 204}; 205 206static struct methods nv04_methods[] = { 207 { "PROM", load_vbios_prom, false }, 208 { "PRAMIN", load_vbios_pramin, true }, 209 { "PCIROM", load_vbios_pci, true }, 210}; 211 212static struct methods nv50_methods[] = { 213 { "ACPI", load_vbios_acpi, true }, 214 { "PRAMIN", load_vbios_pramin, true }, 215 { "PROM", load_vbios_prom, false }, 216 { "PCIROM", load_vbios_pci, true }, 217}; 218 219#define METHODCNT 3 220 221static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data) 222{ 223 struct drm_nouveau_private *dev_priv = dev->dev_private; 224 struct methods *methods; 225 int i; 226 int testscore = 3; 227 int scores[METHODCNT]; 228 229 if (nouveau_vbios) { 230 methods = nv04_methods; 231 for (i = 0; i < METHODCNT; i++) 232 if (!strcasecmp(nouveau_vbios, methods[i].desc)) 233 break; 234 235 if (i < METHODCNT) { 236 NV_INFO(dev, "Attempting to use BIOS image from %s\n", 237 methods[i].desc); 238 239 methods[i].loadbios(dev, data); 240 if (score_vbios(dev, data, methods[i].rw)) 241 return true; 242 } 243 244 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios); 245 } 246 247 if (dev_priv->card_type < NV_50) 248 methods = nv04_methods; 249 else 250 methods = nv50_methods; 251 252 for (i = 0; i < METHODCNT; i++) { 253 NV_TRACE(dev, "Attempting to load BIOS image from %s\n", 254 methods[i].desc); 255 data[0] = data[1] = 0; /* avoid reuse of previous image */ 256 methods[i].loadbios(dev, data); 257 scores[i] = score_vbios(dev, data, methods[i].rw); 258 if (scores[i] == testscore) 259 return true; 260 } 261 262 while (--testscore > 0) { 263 for (i = 0; i < METHODCNT; i++) { 264 if (scores[i] == testscore) { 265 NV_TRACE(dev, "Using BIOS image from %s\n", 266 methods[i].desc); 267 methods[i].loadbios(dev, data); 268 return true; 269 } 270 } 271 } 272 273 NV_ERROR(dev, "No valid BIOS image found\n"); 274 return false; 275} 276 277struct init_tbl_entry { 278 char *name; 279 uint8_t id; 280 /* Return: 281 * > 0: success, length of opcode 282 * 0: success, but abort further parsing of table (INIT_DONE etc) 283 * < 0: failure, table parsing will be aborted 284 */ 285 int (*handler)(struct nvbios *, uint16_t, struct init_exec *); 286}; 287 288struct bit_entry { 289 uint8_t id[2]; 290 uint16_t length; 291 uint16_t offset; 292}; 293 294static int parse_init_table(struct nvbios *, unsigned int, struct init_exec *); 295 296#define MACRO_INDEX_SIZE 2 297#define MACRO_SIZE 8 298#define CONDITION_SIZE 12 299#define IO_FLAG_CONDITION_SIZE 9 300#define IO_CONDITION_SIZE 5 301#define MEM_INIT_SIZE 66 302 303static void still_alive(void) 304{ 305#if 0 306 sync(); 307 msleep(2); 308#endif 309} 310 311static uint32_t 312munge_reg(struct nvbios *bios, uint32_t reg) 313{ 314 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 315 struct dcb_entry *dcbent = bios->display.output; 316 317 if (dev_priv->card_type < NV_50) 318 return reg; 319 320 if (reg & 0x40000000) { 321 BUG_ON(!dcbent); 322 323 reg += (ffs(dcbent->or) - 1) * 0x800; 324 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1)) 325 reg += 0x00000080; 326 } 327 328 reg &= ~0x60000000; 329 return reg; 330} 331 332static int 333valid_reg(struct nvbios *bios, uint32_t reg) 334{ 335 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 336 struct drm_device *dev = bios->dev; 337 338 /* C51 has misaligned regs on purpose. Marvellous */ 339 if (reg & 0x2 || 340 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51)) 341 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg); 342 343 /* warn on C51 regs that haven't been verified accessible in tracing */ 344 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 && 345 reg != 0x130d && reg != 0x1311 && reg != 0x60081d) 346 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n", 347 reg); 348 349 if (reg >= (8*1024*1024)) { 350 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg); 351 return 0; 352 } 353 354 return 1; 355} 356 357static bool 358valid_idx_port(struct nvbios *bios, uint16_t port) 359{ 360 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 361 struct drm_device *dev = bios->dev; 362 363 /* 364 * If adding more ports here, the read/write functions below will need 365 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is 366 * used for the port in question 367 */ 368 if (dev_priv->card_type < NV_50) { 369 if (port == NV_CIO_CRX__COLOR) 370 return true; 371 if (port == NV_VIO_SRX) 372 return true; 373 } else { 374 if (port == NV_CIO_CRX__COLOR) 375 return true; 376 } 377 378 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n", 379 port); 380 381 return false; 382} 383 384static bool 385valid_port(struct nvbios *bios, uint16_t port) 386{ 387 struct drm_device *dev = bios->dev; 388 389 /* 390 * If adding more ports here, the read/write functions below will need 391 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is 392 * used for the port in question 393 */ 394 if (port == NV_VIO_VSE2) 395 return true; 396 397 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port); 398 399 return false; 400} 401 402static uint32_t 403bios_rd32(struct nvbios *bios, uint32_t reg) 404{ 405 uint32_t data; 406 407 reg = munge_reg(bios, reg); 408 if (!valid_reg(bios, reg)) 409 return 0; 410 411 /* 412 * C51 sometimes uses regs with bit0 set in the address. For these 413 * cases there should exist a translation in a BIOS table to an IO 414 * port address which the BIOS uses for accessing the reg 415 * 416 * These only seem to appear for the power control regs to a flat panel, 417 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs 418 * for 0x1308 and 0x1310 are used - hence the mask below. An S3 419 * suspend-resume mmio trace from a C51 will be required to see if this 420 * is true for the power microcode in 0x14.., or whether the direct IO 421 * port access method is needed 422 */ 423 if (reg & 0x1) 424 reg &= ~0x1; 425 426 data = nv_rd32(bios->dev, reg); 427 428 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data); 429 430 return data; 431} 432 433static void 434bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data) 435{ 436 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 437 438 reg = munge_reg(bios, reg); 439 if (!valid_reg(bios, reg)) 440 return; 441 442 /* see note in bios_rd32 */ 443 if (reg & 0x1) 444 reg &= 0xfffffffe; 445 446 LOG_OLD_VALUE(bios_rd32(bios, reg)); 447 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data); 448 449 if (dev_priv->vbios.execute) { 450 still_alive(); 451 nv_wr32(bios->dev, reg, data); 452 } 453} 454 455static uint8_t 456bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index) 457{ 458 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 459 struct drm_device *dev = bios->dev; 460 uint8_t data; 461 462 if (!valid_idx_port(bios, port)) 463 return 0; 464 465 if (dev_priv->card_type < NV_50) { 466 if (port == NV_VIO_SRX) 467 data = NVReadVgaSeq(dev, bios->state.crtchead, index); 468 else /* assume NV_CIO_CRX__COLOR */ 469 data = NVReadVgaCrtc(dev, bios->state.crtchead, index); 470 } else { 471 uint32_t data32; 472 473 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3)); 474 data = (data32 >> ((index & 3) << 3)) & 0xff; 475 } 476 477 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, " 478 "Head: 0x%02X, Data: 0x%02X\n", 479 port, index, bios->state.crtchead, data); 480 return data; 481} 482 483static void 484bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data) 485{ 486 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 487 struct drm_device *dev = bios->dev; 488 489 if (!valid_idx_port(bios, port)) 490 return; 491 492 /* 493 * The current head is maintained in the nvbios member state.crtchead. 494 * We trap changes to CR44 and update the head variable and hence the 495 * register set written. 496 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance 497 * of the write, and to head1 after the write 498 */ 499 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 && 500 data != NV_CIO_CRE_44_HEADB) 501 bios->state.crtchead = 0; 502 503 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index)); 504 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, " 505 "Head: 0x%02X, Data: 0x%02X\n", 506 port, index, bios->state.crtchead, data); 507 508 if (bios->execute && dev_priv->card_type < NV_50) { 509 still_alive(); 510 if (port == NV_VIO_SRX) 511 NVWriteVgaSeq(dev, bios->state.crtchead, index, data); 512 else /* assume NV_CIO_CRX__COLOR */ 513 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data); 514 } else 515 if (bios->execute) { 516 uint32_t data32, shift = (index & 3) << 3; 517 518 still_alive(); 519 520 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3)); 521 data32 &= ~(0xff << shift); 522 data32 |= (data << shift); 523 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32); 524 } 525 526 if (port == NV_CIO_CRX__COLOR && 527 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB) 528 bios->state.crtchead = 1; 529} 530 531static uint8_t 532bios_port_rd(struct nvbios *bios, uint16_t port) 533{ 534 uint8_t data, head = bios->state.crtchead; 535 536 if (!valid_port(bios, port)) 537 return 0; 538 539 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port); 540 541 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n", 542 port, head, data); 543 544 return data; 545} 546 547static void 548bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data) 549{ 550 int head = bios->state.crtchead; 551 552 if (!valid_port(bios, port)) 553 return; 554 555 LOG_OLD_VALUE(bios_port_rd(bios, port)); 556 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n", 557 port, head, data); 558 559 if (!bios->execute) 560 return; 561 562 still_alive(); 563 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data); 564} 565 566static bool 567io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 568{ 569 /* 570 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte 571 * for the CRTC index; 1 byte for the mask to apply to the value 572 * retrieved from the CRTC; 1 byte for the shift right to apply to the 573 * masked CRTC value; 2 bytes for the offset to the flag array, to 574 * which the shifted value is added; 1 byte for the mask applied to the 575 * value read from the flag array; and 1 byte for the value to compare 576 * against the masked byte from the flag table. 577 */ 578 579 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE; 580 uint16_t crtcport = ROM16(bios->data[condptr]); 581 uint8_t crtcindex = bios->data[condptr + 2]; 582 uint8_t mask = bios->data[condptr + 3]; 583 uint8_t shift = bios->data[condptr + 4]; 584 uint16_t flagarray = ROM16(bios->data[condptr + 5]); 585 uint8_t flagarraymask = bios->data[condptr + 7]; 586 uint8_t cmpval = bios->data[condptr + 8]; 587 uint8_t data; 588 589 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 590 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, " 591 "Cmpval: 0x%02X\n", 592 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval); 593 594 data = bios_idxprt_rd(bios, crtcport, crtcindex); 595 596 data = bios->data[flagarray + ((data & mask) >> shift)]; 597 data &= flagarraymask; 598 599 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n", 600 offset, data, cmpval); 601 602 return (data == cmpval); 603} 604 605static bool 606bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 607{ 608 /* 609 * The condition table entry has 4 bytes for the address of the 610 * register to check, 4 bytes for a mask to apply to the register and 611 * 4 for a test comparison value 612 */ 613 614 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE; 615 uint32_t reg = ROM32(bios->data[condptr]); 616 uint32_t mask = ROM32(bios->data[condptr + 4]); 617 uint32_t cmpval = ROM32(bios->data[condptr + 8]); 618 uint32_t data; 619 620 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n", 621 offset, cond, reg, mask); 622 623 data = bios_rd32(bios, reg) & mask; 624 625 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n", 626 offset, data, cmpval); 627 628 return (data == cmpval); 629} 630 631static bool 632io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 633{ 634 /* 635 * The IO condition entry has 2 bytes for the IO port address; 1 byte 636 * for the index to write to io_port; 1 byte for the mask to apply to 637 * the byte read from io_port+1; and 1 byte for the value to compare 638 * against the masked byte. 639 */ 640 641 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE; 642 uint16_t io_port = ROM16(bios->data[condptr]); 643 uint8_t port_index = bios->data[condptr + 2]; 644 uint8_t mask = bios->data[condptr + 3]; 645 uint8_t cmpval = bios->data[condptr + 4]; 646 647 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask; 648 649 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n", 650 offset, data, cmpval); 651 652 return (data == cmpval); 653} 654 655static int 656nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk) 657{ 658 struct drm_nouveau_private *dev_priv = dev->dev_private; 659 uint32_t reg0 = nv_rd32(dev, reg + 0); 660 uint32_t reg1 = nv_rd32(dev, reg + 4); 661 struct nouveau_pll_vals pll; 662 struct pll_lims pll_limits; 663 int ret; 664 665 ret = get_pll_limits(dev, reg, &pll_limits); 666 if (ret) 667 return ret; 668 669 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll); 670 if (!clk) 671 return -ERANGE; 672 673 reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16); 674 reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1; 675 676 if (dev_priv->vbios.execute) { 677 still_alive(); 678 nv_wr32(dev, reg + 4, reg1); 679 nv_wr32(dev, reg + 0, reg0); 680 } 681 682 return 0; 683} 684 685static int 686setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk) 687{ 688 struct drm_device *dev = bios->dev; 689 struct drm_nouveau_private *dev_priv = dev->dev_private; 690 /* clk in kHz */ 691 struct pll_lims pll_lim; 692 struct nouveau_pll_vals pllvals; 693 int ret; 694 695 if (dev_priv->card_type >= NV_50) 696 return nv50_pll_set(dev, reg, clk); 697 698 /* high regs (such as in the mac g5 table) are not -= 4 */ 699 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim); 700 if (ret) 701 return ret; 702 703 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals); 704 if (!clk) 705 return -ERANGE; 706 707 if (bios->execute) { 708 still_alive(); 709 nouveau_hw_setpll(dev, reg, &pllvals); 710 } 711 712 return 0; 713} 714 715static int dcb_entry_idx_from_crtchead(struct drm_device *dev) 716{ 717 struct drm_nouveau_private *dev_priv = dev->dev_private; 718 struct nvbios *bios = &dev_priv->vbios; 719 720 /* 721 * For the results of this function to be correct, CR44 must have been 722 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0, 723 * and the DCB table parsed, before the script calling the function is 724 * run. run_digital_op_script is example of how to do such setup 725 */ 726 727 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0); 728 729 if (dcb_entry > bios->dcb.entries) { 730 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently " 731 "(%02X)\n", dcb_entry); 732 dcb_entry = 0x7f; /* unused / invalid marker */ 733 } 734 735 return dcb_entry; 736} 737 738static int 739read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, int index, struct dcb_i2c_entry *i2c) 740{ 741 uint8_t dcb_i2c_ver = dcb_version, headerlen = 0, entry_len = 4; 742 int i2c_entries = DCB_MAX_NUM_I2C_ENTRIES; 743 int recordoffset = 0, rdofs = 1, wrofs = 0; 744 uint8_t port_type = 0; 745 746 if (!i2ctable) 747 return -EINVAL; 748 749 if (dcb_version >= 0x30) { 750 if (i2ctable[0] != dcb_version) /* necessary? */ 751 NV_WARN(dev, 752 "DCB I2C table version mismatch (%02X vs %02X)\n", 753 i2ctable[0], dcb_version); 754 dcb_i2c_ver = i2ctable[0]; 755 headerlen = i2ctable[1]; 756 if (i2ctable[2] <= DCB_MAX_NUM_I2C_ENTRIES) 757 i2c_entries = i2ctable[2]; 758 else 759 NV_WARN(dev, 760 "DCB I2C table has more entries than indexable " 761 "(%d entries, max %d)\n", i2ctable[2], 762 DCB_MAX_NUM_I2C_ENTRIES); 763 entry_len = i2ctable[3]; 764 /* [4] is i2c_default_indices, read in parse_dcb_table() */ 765 } 766 /* 767 * It's your own fault if you call this function on a DCB 1.1 BIOS -- 768 * the test below is for DCB 1.2 769 */ 770 if (dcb_version < 0x14) { 771 recordoffset = 2; 772 rdofs = 0; 773 wrofs = 1; 774 } 775 776 if (index == 0xf) 777 return 0; 778 if (index >= i2c_entries) { 779 NV_ERROR(dev, "DCB I2C index too big (%d >= %d)\n", 780 index, i2ctable[2]); 781 return -ENOENT; 782 } 783 if (i2ctable[headerlen + entry_len * index + 3] == 0xff) { 784 NV_ERROR(dev, "DCB I2C entry invalid\n"); 785 return -EINVAL; 786 } 787 788 if (dcb_i2c_ver >= 0x30) { 789 port_type = i2ctable[headerlen + recordoffset + 3 + entry_len * index]; 790 791 /* 792 * Fixup for chips using same address offset for read and 793 * write. 794 */ 795 if (port_type == 4) /* seen on C51 */ 796 rdofs = wrofs = 1; 797 if (port_type >= 5) /* G80+ */ 798 rdofs = wrofs = 0; 799 } 800 801 if (dcb_i2c_ver >= 0x40) { 802 if (port_type != 5 && port_type != 6) 803 NV_WARN(dev, "DCB I2C table has port type %d\n", port_type); 804 805 i2c->entry = ROM32(i2ctable[headerlen + recordoffset + entry_len * index]); 806 } 807 808 i2c->port_type = port_type; 809 i2c->read = i2ctable[headerlen + recordoffset + rdofs + entry_len * index]; 810 i2c->write = i2ctable[headerlen + recordoffset + wrofs + entry_len * index]; 811 812 return 0; 813} 814 815static struct nouveau_i2c_chan * 816init_i2c_device_find(struct drm_device *dev, int i2c_index) 817{ 818 struct drm_nouveau_private *dev_priv = dev->dev_private; 819 struct dcb_table *dcb = &dev_priv->vbios.dcb; 820 821 if (i2c_index == 0xff) { 822 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */ 823 int idx = dcb_entry_idx_from_crtchead(dev), shift = 0; 824 int default_indices = dcb->i2c_default_indices; 825 826 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default) 827 shift = 4; 828 829 i2c_index = (default_indices >> shift) & 0xf; 830 } 831 if (i2c_index == 0x80) /* g80+ */ 832 i2c_index = dcb->i2c_default_indices & 0xf; 833 else 834 if (i2c_index == 0x81) 835 i2c_index = (dcb->i2c_default_indices & 0xf0) >> 4; 836 837 if (i2c_index >= DCB_MAX_NUM_I2C_ENTRIES) { 838 NV_ERROR(dev, "invalid i2c_index 0x%x\n", i2c_index); 839 return NULL; 840 } 841 842 /* Make sure i2c table entry has been parsed, it may not 843 * have been if this is a bus not referenced by a DCB encoder 844 */ 845 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table, 846 i2c_index, &dcb->i2c[i2c_index]); 847 848 return nouveau_i2c_find(dev, i2c_index); 849} 850 851static uint32_t 852get_tmds_index_reg(struct drm_device *dev, uint8_t mlv) 853{ 854 /* 855 * For mlv < 0x80, it is an index into a table of TMDS base addresses. 856 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by 857 * CR58 for CR57 = 0 to index a table of offsets to the basic 858 * 0x6808b0 address. 859 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by 860 * CR58 for CR57 = 0 to index a table of offsets to the basic 861 * 0x6808b0 address, and then flip the offset by 8. 862 */ 863 864 struct drm_nouveau_private *dev_priv = dev->dev_private; 865 struct nvbios *bios = &dev_priv->vbios; 866 const int pramdac_offset[13] = { 867 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 }; 868 const uint32_t pramdac_table[4] = { 869 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 }; 870 871 if (mlv >= 0x80) { 872 int dcb_entry, dacoffset; 873 874 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */ 875 dcb_entry = dcb_entry_idx_from_crtchead(dev); 876 if (dcb_entry == 0x7f) 877 return 0; 878 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or]; 879 if (mlv == 0x81) 880 dacoffset ^= 8; 881 return 0x6808b0 + dacoffset; 882 } else { 883 if (mlv >= ARRAY_SIZE(pramdac_table)) { 884 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n", 885 mlv); 886 return 0; 887 } 888 return pramdac_table[mlv]; 889 } 890} 891 892static int 893init_io_restrict_prog(struct nvbios *bios, uint16_t offset, 894 struct init_exec *iexec) 895{ 896 /* 897 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2') 898 * 899 * offset (8 bit): opcode 900 * offset + 1 (16 bit): CRTC port 901 * offset + 3 (8 bit): CRTC index 902 * offset + 4 (8 bit): mask 903 * offset + 5 (8 bit): shift 904 * offset + 6 (8 bit): count 905 * offset + 7 (32 bit): register 906 * offset + 11 (32 bit): configuration 1 907 * ... 908 * 909 * Starting at offset + 11 there are "count" 32 bit values. 910 * To find out which value to use read index "CRTC index" on "CRTC 911 * port", AND this value with "mask" and then bit shift right "shift" 912 * bits. Read the appropriate value using this index and write to 913 * "register" 914 */ 915 916 uint16_t crtcport = ROM16(bios->data[offset + 1]); 917 uint8_t crtcindex = bios->data[offset + 3]; 918 uint8_t mask = bios->data[offset + 4]; 919 uint8_t shift = bios->data[offset + 5]; 920 uint8_t count = bios->data[offset + 6]; 921 uint32_t reg = ROM32(bios->data[offset + 7]); 922 uint8_t config; 923 uint32_t configval; 924 int len = 11 + count * 4; 925 926 if (!iexec->execute) 927 return len; 928 929 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 930 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n", 931 offset, crtcport, crtcindex, mask, shift, count, reg); 932 933 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 934 if (config > count) { 935 NV_ERROR(bios->dev, 936 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 937 offset, config, count); 938 return len; 939 } 940 941 configval = ROM32(bios->data[offset + 11 + config * 4]); 942 943 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config); 944 945 bios_wr32(bios, reg, configval); 946 947 return len; 948} 949 950static int 951init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 952{ 953 /* 954 * INIT_REPEAT opcode: 0x33 ('3') 955 * 956 * offset (8 bit): opcode 957 * offset + 1 (8 bit): count 958 * 959 * Execute script following this opcode up to INIT_REPEAT_END 960 * "count" times 961 */ 962 963 uint8_t count = bios->data[offset + 1]; 964 uint8_t i; 965 966 /* no iexec->execute check by design */ 967 968 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n", 969 offset, count); 970 971 iexec->repeat = true; 972 973 /* 974 * count - 1, as the script block will execute once when we leave this 975 * opcode -- this is compatible with bios behaviour as: 976 * a) the block is always executed at least once, even if count == 0 977 * b) the bios interpreter skips to the op following INIT_END_REPEAT, 978 * while we don't 979 */ 980 for (i = 0; i < count - 1; i++) 981 parse_init_table(bios, offset + 2, iexec); 982 983 iexec->repeat = false; 984 985 return 2; 986} 987 988static int 989init_io_restrict_pll(struct nvbios *bios, uint16_t offset, 990 struct init_exec *iexec) 991{ 992 /* 993 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4') 994 * 995 * offset (8 bit): opcode 996 * offset + 1 (16 bit): CRTC port 997 * offset + 3 (8 bit): CRTC index 998 * offset + 4 (8 bit): mask 999 * offset + 5 (8 bit): shift 1000 * offset + 6 (8 bit): IO flag condition index 1001 * offset + 7 (8 bit): count 1002 * offset + 8 (32 bit): register 1003 * offset + 12 (16 bit): frequency 1 1004 * ... 1005 * 1006 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz). 1007 * Set PLL register "register" to coefficients for frequency n, 1008 * selected by reading index "CRTC index" of "CRTC port" ANDed with 1009 * "mask" and shifted right by "shift". 1010 * 1011 * If "IO flag condition index" > 0, and condition met, double 1012 * frequency before setting it. 1013 */ 1014 1015 uint16_t crtcport = ROM16(bios->data[offset + 1]); 1016 uint8_t crtcindex = bios->data[offset + 3]; 1017 uint8_t mask = bios->data[offset + 4]; 1018 uint8_t shift = bios->data[offset + 5]; 1019 int8_t io_flag_condition_idx = bios->data[offset + 6]; 1020 uint8_t count = bios->data[offset + 7]; 1021 uint32_t reg = ROM32(bios->data[offset + 8]); 1022 uint8_t config; 1023 uint16_t freq; 1024 int len = 12 + count * 2; 1025 1026 if (!iexec->execute) 1027 return len; 1028 1029 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 1030 "Shift: 0x%02X, IO Flag Condition: 0x%02X, " 1031 "Count: 0x%02X, Reg: 0x%08X\n", 1032 offset, crtcport, crtcindex, mask, shift, 1033 io_flag_condition_idx, count, reg); 1034 1035 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 1036 if (config > count) { 1037 NV_ERROR(bios->dev, 1038 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 1039 offset, config, count); 1040 return len; 1041 } 1042 1043 freq = ROM16(bios->data[offset + 12 + config * 2]); 1044 1045 if (io_flag_condition_idx > 0) { 1046 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) { 1047 BIOSLOG(bios, "0x%04X: Condition fulfilled -- " 1048 "frequency doubled\n", offset); 1049 freq *= 2; 1050 } else 1051 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- " 1052 "frequency unchanged\n", offset); 1053 } 1054 1055 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n", 1056 offset, reg, config, freq); 1057 1058 setPLL(bios, reg, freq * 10); 1059 1060 return len; 1061} 1062 1063static int 1064init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1065{ 1066 /* 1067 * INIT_END_REPEAT opcode: 0x36 ('6') 1068 * 1069 * offset (8 bit): opcode 1070 * 1071 * Marks the end of the block for INIT_REPEAT to repeat 1072 */ 1073 1074 /* no iexec->execute check by design */ 1075 1076 /* 1077 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when 1078 * we're not in repeat mode 1079 */ 1080 if (iexec->repeat) 1081 return 0; 1082 1083 return 1; 1084} 1085 1086static int 1087init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1088{ 1089 /* 1090 * INIT_COPY opcode: 0x37 ('7') 1091 * 1092 * offset (8 bit): opcode 1093 * offset + 1 (32 bit): register 1094 * offset + 5 (8 bit): shift 1095 * offset + 6 (8 bit): srcmask 1096 * offset + 7 (16 bit): CRTC port 1097 * offset + 9 (8 bit): CRTC index 1098 * offset + 10 (8 bit): mask 1099 * 1100 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with 1101 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC 1102 * port 1103 */ 1104 1105 uint32_t reg = ROM32(bios->data[offset + 1]); 1106 uint8_t shift = bios->data[offset + 5]; 1107 uint8_t srcmask = bios->data[offset + 6]; 1108 uint16_t crtcport = ROM16(bios->data[offset + 7]); 1109 uint8_t crtcindex = bios->data[offset + 9]; 1110 uint8_t mask = bios->data[offset + 10]; 1111 uint32_t data; 1112 uint8_t crtcdata; 1113 1114 if (!iexec->execute) 1115 return 11; 1116 1117 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, " 1118 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n", 1119 offset, reg, shift, srcmask, crtcport, crtcindex, mask); 1120 1121 data = bios_rd32(bios, reg); 1122 1123 if (shift < 0x80) 1124 data >>= shift; 1125 else 1126 data <<= (0x100 - shift); 1127 1128 data &= srcmask; 1129 1130 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask; 1131 crtcdata |= (uint8_t)data; 1132 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata); 1133 1134 return 11; 1135} 1136 1137static int 1138init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1139{ 1140 /* 1141 * INIT_NOT opcode: 0x38 ('8') 1142 * 1143 * offset (8 bit): opcode 1144 * 1145 * Invert the current execute / no-execute condition (i.e. "else") 1146 */ 1147 if (iexec->execute) 1148 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset); 1149 else 1150 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset); 1151 1152 iexec->execute = !iexec->execute; 1153 return 1; 1154} 1155 1156static int 1157init_io_flag_condition(struct nvbios *bios, uint16_t offset, 1158 struct init_exec *iexec) 1159{ 1160 /* 1161 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9') 1162 * 1163 * offset (8 bit): opcode 1164 * offset + 1 (8 bit): condition number 1165 * 1166 * Check condition "condition number" in the IO flag condition table. 1167 * If condition not met skip subsequent opcodes until condition is 1168 * inverted (INIT_NOT), or we hit INIT_RESUME 1169 */ 1170 1171 uint8_t cond = bios->data[offset + 1]; 1172 1173 if (!iexec->execute) 1174 return 2; 1175 1176 if (io_flag_condition_met(bios, offset, cond)) 1177 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 1178 else { 1179 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 1180 iexec->execute = false; 1181 } 1182 1183 return 2; 1184} 1185 1186static int 1187init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1188{ 1189 /* 1190 * INIT_DP_CONDITION opcode: 0x3A ('') 1191 * 1192 * offset (8 bit): opcode 1193 * offset + 1 (8 bit): "sub" opcode 1194 * offset + 2 (8 bit): unknown 1195 * 1196 */ 1197 1198 struct bit_displayport_encoder_table *dpe = NULL; 1199 struct dcb_entry *dcb = bios->display.output; 1200 struct drm_device *dev = bios->dev; 1201 uint8_t cond = bios->data[offset + 1]; 1202 int dummy; 1203 1204 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond); 1205 1206 if (!iexec->execute) 1207 return 3; 1208 1209 dpe = nouveau_bios_dp_table(dev, dcb, &dummy); 1210 if (!dpe) { 1211 NV_ERROR(dev, "0x%04X: INIT_3A: no encoder table!!\n", offset); 1212 return 3; 1213 } 1214 1215 switch (cond) { 1216 case 0: 1217 { 1218 struct dcb_connector_table_entry *ent = 1219 &bios->dcb.connector.entry[dcb->connector]; 1220 1221 if (ent->type != DCB_CONNECTOR_eDP) 1222 iexec->execute = false; 1223 } 1224 break; 1225 case 1: 1226 case 2: 1227 if (!(dpe->unknown & cond)) 1228 iexec->execute = false; 1229 break; 1230 case 5: 1231 { 1232 struct nouveau_i2c_chan *auxch; 1233 int ret; 1234 1235 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index); 1236 if (!auxch) { 1237 NV_ERROR(dev, "0x%04X: couldn't get auxch\n", offset); 1238 return 3; 1239 } 1240 1241 ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1); 1242 if (ret) { 1243 NV_ERROR(dev, "0x%04X: auxch rd fail: %d\n", offset, ret); 1244 return 3; 1245 } 1246 1247 if (cond & 1) 1248 iexec->execute = false; 1249 } 1250 break; 1251 default: 1252 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond); 1253 break; 1254 } 1255 1256 if (iexec->execute) 1257 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset); 1258 else 1259 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset); 1260 1261 return 3; 1262} 1263 1264static int 1265init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1266{ 1267 /* 1268 * INIT_3B opcode: 0x3B ('') 1269 * 1270 * offset (8 bit): opcode 1271 * offset + 1 (8 bit): crtc index 1272 * 1273 */ 1274 1275 uint8_t or = ffs(bios->display.output->or) - 1; 1276 uint8_t index = bios->data[offset + 1]; 1277 uint8_t data; 1278 1279 if (!iexec->execute) 1280 return 2; 1281 1282 data = bios_idxprt_rd(bios, 0x3d4, index); 1283 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or)); 1284 return 2; 1285} 1286 1287static int 1288init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1289{ 1290 /* 1291 * INIT_3C opcode: 0x3C ('') 1292 * 1293 * offset (8 bit): opcode 1294 * offset + 1 (8 bit): crtc index 1295 * 1296 */ 1297 1298 uint8_t or = ffs(bios->display.output->or) - 1; 1299 uint8_t index = bios->data[offset + 1]; 1300 uint8_t data; 1301 1302 if (!iexec->execute) 1303 return 2; 1304 1305 data = bios_idxprt_rd(bios, 0x3d4, index); 1306 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or)); 1307 return 2; 1308} 1309 1310static int 1311init_idx_addr_latched(struct nvbios *bios, uint16_t offset, 1312 struct init_exec *iexec) 1313{ 1314 /* 1315 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I') 1316 * 1317 * offset (8 bit): opcode 1318 * offset + 1 (32 bit): control register 1319 * offset + 5 (32 bit): data register 1320 * offset + 9 (32 bit): mask 1321 * offset + 13 (32 bit): data 1322 * offset + 17 (8 bit): count 1323 * offset + 18 (8 bit): address 1 1324 * offset + 19 (8 bit): data 1 1325 * ... 1326 * 1327 * For each of "count" address and data pairs, write "data n" to 1328 * "data register", read the current value of "control register", 1329 * and write it back once ANDed with "mask", ORed with "data", 1330 * and ORed with "address n" 1331 */ 1332 1333 uint32_t controlreg = ROM32(bios->data[offset + 1]); 1334 uint32_t datareg = ROM32(bios->data[offset + 5]); 1335 uint32_t mask = ROM32(bios->data[offset + 9]); 1336 uint32_t data = ROM32(bios->data[offset + 13]); 1337 uint8_t count = bios->data[offset + 17]; 1338 int len = 18 + count * 2; 1339 uint32_t value; 1340 int i; 1341 1342 if (!iexec->execute) 1343 return len; 1344 1345 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, " 1346 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n", 1347 offset, controlreg, datareg, mask, data, count); 1348 1349 for (i = 0; i < count; i++) { 1350 uint8_t instaddress = bios->data[offset + 18 + i * 2]; 1351 uint8_t instdata = bios->data[offset + 19 + i * 2]; 1352 1353 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n", 1354 offset, instaddress, instdata); 1355 1356 bios_wr32(bios, datareg, instdata); 1357 value = bios_rd32(bios, controlreg) & mask; 1358 value |= data; 1359 value |= instaddress; 1360 bios_wr32(bios, controlreg, value); 1361 } 1362 1363 return len; 1364} 1365 1366static int 1367init_io_restrict_pll2(struct nvbios *bios, uint16_t offset, 1368 struct init_exec *iexec) 1369{ 1370 /* 1371 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J') 1372 * 1373 * offset (8 bit): opcode 1374 * offset + 1 (16 bit): CRTC port 1375 * offset + 3 (8 bit): CRTC index 1376 * offset + 4 (8 bit): mask 1377 * offset + 5 (8 bit): shift 1378 * offset + 6 (8 bit): count 1379 * offset + 7 (32 bit): register 1380 * offset + 11 (32 bit): frequency 1 1381 * ... 1382 * 1383 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz). 1384 * Set PLL register "register" to coefficients for frequency n, 1385 * selected by reading index "CRTC index" of "CRTC port" ANDed with 1386 * "mask" and shifted right by "shift". 1387 */ 1388 1389 uint16_t crtcport = ROM16(bios->data[offset + 1]); 1390 uint8_t crtcindex = bios->data[offset + 3]; 1391 uint8_t mask = bios->data[offset + 4]; 1392 uint8_t shift = bios->data[offset + 5]; 1393 uint8_t count = bios->data[offset + 6]; 1394 uint32_t reg = ROM32(bios->data[offset + 7]); 1395 int len = 11 + count * 4; 1396 uint8_t config; 1397 uint32_t freq; 1398 1399 if (!iexec->execute) 1400 return len; 1401 1402 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 1403 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n", 1404 offset, crtcport, crtcindex, mask, shift, count, reg); 1405 1406 if (!reg) 1407 return len; 1408 1409 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 1410 if (config > count) { 1411 NV_ERROR(bios->dev, 1412 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 1413 offset, config, count); 1414 return len; 1415 } 1416 1417 freq = ROM32(bios->data[offset + 11 + config * 4]); 1418 1419 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n", 1420 offset, reg, config, freq); 1421 1422 setPLL(bios, reg, freq); 1423 1424 return len; 1425} 1426 1427static int 1428init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1429{ 1430 /* 1431 * INIT_PLL2 opcode: 0x4B ('K') 1432 * 1433 * offset (8 bit): opcode 1434 * offset + 1 (32 bit): register 1435 * offset + 5 (32 bit): freq 1436 * 1437 * Set PLL register "register" to coefficients for frequency "freq" 1438 */ 1439 1440 uint32_t reg = ROM32(bios->data[offset + 1]); 1441 uint32_t freq = ROM32(bios->data[offset + 5]); 1442 1443 if (!iexec->execute) 1444 return 9; 1445 1446 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n", 1447 offset, reg, freq); 1448 1449 setPLL(bios, reg, freq); 1450 return 9; 1451} 1452 1453static int 1454init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1455{ 1456 /* 1457 * INIT_I2C_BYTE opcode: 0x4C ('L') 1458 * 1459 * offset (8 bit): opcode 1460 * offset + 1 (8 bit): DCB I2C table entry index 1461 * offset + 2 (8 bit): I2C slave address 1462 * offset + 3 (8 bit): count 1463 * offset + 4 (8 bit): I2C register 1 1464 * offset + 5 (8 bit): mask 1 1465 * offset + 6 (8 bit): data 1 1466 * ... 1467 * 1468 * For each of "count" registers given by "I2C register n" on the device 1469 * addressed by "I2C slave address" on the I2C bus given by 1470 * "DCB I2C table entry index", read the register, AND the result with 1471 * "mask n" and OR it with "data n" before writing it back to the device 1472 */ 1473 1474 struct drm_device *dev = bios->dev; 1475 uint8_t i2c_index = bios->data[offset + 1]; 1476 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1477 uint8_t count = bios->data[offset + 3]; 1478 struct nouveau_i2c_chan *chan; 1479 int len = 4 + count * 3; 1480 int ret, i; 1481 1482 if (!iexec->execute) 1483 return len; 1484 1485 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1486 "Count: 0x%02X\n", 1487 offset, i2c_index, i2c_address, count); 1488 1489 chan = init_i2c_device_find(dev, i2c_index); 1490 if (!chan) { 1491 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset); 1492 return len; 1493 } 1494 1495 for (i = 0; i < count; i++) { 1496 uint8_t reg = bios->data[offset + 4 + i * 3]; 1497 uint8_t mask = bios->data[offset + 5 + i * 3]; 1498 uint8_t data = bios->data[offset + 6 + i * 3]; 1499 union i2c_smbus_data val; 1500 1501 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 1502 I2C_SMBUS_READ, reg, 1503 I2C_SMBUS_BYTE_DATA, &val); 1504 if (ret < 0) { 1505 NV_ERROR(dev, "0x%04X: i2c rd fail: %d\n", offset, ret); 1506 return len; 1507 } 1508 1509 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, " 1510 "Mask: 0x%02X, Data: 0x%02X\n", 1511 offset, reg, val.byte, mask, data); 1512 1513 if (!bios->execute) 1514 continue; 1515 1516 val.byte &= mask; 1517 val.byte |= data; 1518 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 1519 I2C_SMBUS_WRITE, reg, 1520 I2C_SMBUS_BYTE_DATA, &val); 1521 if (ret < 0) { 1522 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret); 1523 return len; 1524 } 1525 } 1526 1527 return len; 1528} 1529 1530static int 1531init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1532{ 1533 /* 1534 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M') 1535 * 1536 * offset (8 bit): opcode 1537 * offset + 1 (8 bit): DCB I2C table entry index 1538 * offset + 2 (8 bit): I2C slave address 1539 * offset + 3 (8 bit): count 1540 * offset + 4 (8 bit): I2C register 1 1541 * offset + 5 (8 bit): data 1 1542 * ... 1543 * 1544 * For each of "count" registers given by "I2C register n" on the device 1545 * addressed by "I2C slave address" on the I2C bus given by 1546 * "DCB I2C table entry index", set the register to "data n" 1547 */ 1548 1549 struct drm_device *dev = bios->dev; 1550 uint8_t i2c_index = bios->data[offset + 1]; 1551 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1552 uint8_t count = bios->data[offset + 3]; 1553 struct nouveau_i2c_chan *chan; 1554 int len = 4 + count * 2; 1555 int ret, i; 1556 1557 if (!iexec->execute) 1558 return len; 1559 1560 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1561 "Count: 0x%02X\n", 1562 offset, i2c_index, i2c_address, count); 1563 1564 chan = init_i2c_device_find(dev, i2c_index); 1565 if (!chan) { 1566 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset); 1567 return len; 1568 } 1569 1570 for (i = 0; i < count; i++) { 1571 uint8_t reg = bios->data[offset + 4 + i * 2]; 1572 union i2c_smbus_data val; 1573 1574 val.byte = bios->data[offset + 5 + i * 2]; 1575 1576 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n", 1577 offset, reg, val.byte); 1578 1579 if (!bios->execute) 1580 continue; 1581 1582 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 1583 I2C_SMBUS_WRITE, reg, 1584 I2C_SMBUS_BYTE_DATA, &val); 1585 if (ret < 0) { 1586 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret); 1587 return len; 1588 } 1589 } 1590 1591 return len; 1592} 1593 1594static int 1595init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1596{ 1597 /* 1598 * INIT_ZM_I2C opcode: 0x4E ('N') 1599 * 1600 * offset (8 bit): opcode 1601 * offset + 1 (8 bit): DCB I2C table entry index 1602 * offset + 2 (8 bit): I2C slave address 1603 * offset + 3 (8 bit): count 1604 * offset + 4 (8 bit): data 1 1605 * ... 1606 * 1607 * Send "count" bytes ("data n") to the device addressed by "I2C slave 1608 * address" on the I2C bus given by "DCB I2C table entry index" 1609 */ 1610 1611 struct drm_device *dev = bios->dev; 1612 uint8_t i2c_index = bios->data[offset + 1]; 1613 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1614 uint8_t count = bios->data[offset + 3]; 1615 int len = 4 + count; 1616 struct nouveau_i2c_chan *chan; 1617 struct i2c_msg msg; 1618 uint8_t data[256]; 1619 int ret, i; 1620 1621 if (!iexec->execute) 1622 return len; 1623 1624 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1625 "Count: 0x%02X\n", 1626 offset, i2c_index, i2c_address, count); 1627 1628 chan = init_i2c_device_find(dev, i2c_index); 1629 if (!chan) { 1630 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset); 1631 return len; 1632 } 1633 1634 for (i = 0; i < count; i++) { 1635 data[i] = bios->data[offset + 4 + i]; 1636 1637 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]); 1638 } 1639 1640 if (bios->execute) { 1641 msg.addr = i2c_address; 1642 msg.flags = 0; 1643 msg.len = count; 1644 msg.buf = data; 1645 ret = i2c_transfer(&chan->adapter, &msg, 1); 1646 if (ret != 1) { 1647 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret); 1648 return len; 1649 } 1650 } 1651 1652 return len; 1653} 1654 1655static int 1656init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1657{ 1658 /* 1659 * INIT_TMDS opcode: 0x4F ('O') (non-canon name) 1660 * 1661 * offset (8 bit): opcode 1662 * offset + 1 (8 bit): magic lookup value 1663 * offset + 2 (8 bit): TMDS address 1664 * offset + 3 (8 bit): mask 1665 * offset + 4 (8 bit): data 1666 * 1667 * Read the data reg for TMDS address "TMDS address", AND it with mask 1668 * and OR it with data, then write it back 1669 * "magic lookup value" determines which TMDS base address register is 1670 * used -- see get_tmds_index_reg() 1671 */ 1672 1673 struct drm_device *dev = bios->dev; 1674 uint8_t mlv = bios->data[offset + 1]; 1675 uint32_t tmdsaddr = bios->data[offset + 2]; 1676 uint8_t mask = bios->data[offset + 3]; 1677 uint8_t data = bios->data[offset + 4]; 1678 uint32_t reg, value; 1679 1680 if (!iexec->execute) 1681 return 5; 1682 1683 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, " 1684 "Mask: 0x%02X, Data: 0x%02X\n", 1685 offset, mlv, tmdsaddr, mask, data); 1686 1687 reg = get_tmds_index_reg(bios->dev, mlv); 1688 if (!reg) { 1689 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset); 1690 return 5; 1691 } 1692 1693 bios_wr32(bios, reg, 1694 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE); 1695 value = (bios_rd32(bios, reg + 4) & mask) | data; 1696 bios_wr32(bios, reg + 4, value); 1697 bios_wr32(bios, reg, tmdsaddr); 1698 1699 return 5; 1700} 1701 1702static int 1703init_zm_tmds_group(struct nvbios *bios, uint16_t offset, 1704 struct init_exec *iexec) 1705{ 1706 /* 1707 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name) 1708 * 1709 * offset (8 bit): opcode 1710 * offset + 1 (8 bit): magic lookup value 1711 * offset + 2 (8 bit): count 1712 * offset + 3 (8 bit): addr 1 1713 * offset + 4 (8 bit): data 1 1714 * ... 1715 * 1716 * For each of "count" TMDS address and data pairs write "data n" to 1717 * "addr n". "magic lookup value" determines which TMDS base address 1718 * register is used -- see get_tmds_index_reg() 1719 */ 1720 1721 struct drm_device *dev = bios->dev; 1722 uint8_t mlv = bios->data[offset + 1]; 1723 uint8_t count = bios->data[offset + 2]; 1724 int len = 3 + count * 2; 1725 uint32_t reg; 1726 int i; 1727 1728 if (!iexec->execute) 1729 return len; 1730 1731 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n", 1732 offset, mlv, count); 1733 1734 reg = get_tmds_index_reg(bios->dev, mlv); 1735 if (!reg) { 1736 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset); 1737 return len; 1738 } 1739 1740 for (i = 0; i < count; i++) { 1741 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2]; 1742 uint8_t tmdsdata = bios->data[offset + 4 + i * 2]; 1743 1744 bios_wr32(bios, reg + 4, tmdsdata); 1745 bios_wr32(bios, reg, tmdsaddr); 1746 } 1747 1748 return len; 1749} 1750 1751static int 1752init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset, 1753 struct init_exec *iexec) 1754{ 1755 /* 1756 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q') 1757 * 1758 * offset (8 bit): opcode 1759 * offset + 1 (8 bit): CRTC index1 1760 * offset + 2 (8 bit): CRTC index2 1761 * offset + 3 (8 bit): baseaddr 1762 * offset + 4 (8 bit): count 1763 * offset + 5 (8 bit): data 1 1764 * ... 1765 * 1766 * For each of "count" address and data pairs, write "baseaddr + n" to 1767 * "CRTC index1" and "data n" to "CRTC index2" 1768 * Once complete, restore initial value read from "CRTC index1" 1769 */ 1770 uint8_t crtcindex1 = bios->data[offset + 1]; 1771 uint8_t crtcindex2 = bios->data[offset + 2]; 1772 uint8_t baseaddr = bios->data[offset + 3]; 1773 uint8_t count = bios->data[offset + 4]; 1774 int len = 5 + count; 1775 uint8_t oldaddr, data; 1776 int i; 1777 1778 if (!iexec->execute) 1779 return len; 1780 1781 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, " 1782 "BaseAddr: 0x%02X, Count: 0x%02X\n", 1783 offset, crtcindex1, crtcindex2, baseaddr, count); 1784 1785 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1); 1786 1787 for (i = 0; i < count; i++) { 1788 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, 1789 baseaddr + i); 1790 data = bios->data[offset + 5 + i]; 1791 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data); 1792 } 1793 1794 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr); 1795 1796 return len; 1797} 1798 1799static int 1800init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1801{ 1802 /* 1803 * INIT_CR opcode: 0x52 ('R') 1804 * 1805 * offset (8 bit): opcode 1806 * offset + 1 (8 bit): CRTC index 1807 * offset + 2 (8 bit): mask 1808 * offset + 3 (8 bit): data 1809 * 1810 * Assign the value of at "CRTC index" ANDed with mask and ORed with 1811 * data back to "CRTC index" 1812 */ 1813 1814 uint8_t crtcindex = bios->data[offset + 1]; 1815 uint8_t mask = bios->data[offset + 2]; 1816 uint8_t data = bios->data[offset + 3]; 1817 uint8_t value; 1818 1819 if (!iexec->execute) 1820 return 4; 1821 1822 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n", 1823 offset, crtcindex, mask, data); 1824 1825 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask; 1826 value |= data; 1827 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value); 1828 1829 return 4; 1830} 1831 1832static int 1833init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1834{ 1835 /* 1836 * INIT_ZM_CR opcode: 0x53 ('S') 1837 * 1838 * offset (8 bit): opcode 1839 * offset + 1 (8 bit): CRTC index 1840 * offset + 2 (8 bit): value 1841 * 1842 * Assign "value" to CRTC register with index "CRTC index". 1843 */ 1844 1845 uint8_t crtcindex = ROM32(bios->data[offset + 1]); 1846 uint8_t data = bios->data[offset + 2]; 1847 1848 if (!iexec->execute) 1849 return 3; 1850 1851 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data); 1852 1853 return 3; 1854} 1855 1856static int 1857init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1858{ 1859 /* 1860 * INIT_ZM_CR_GROUP opcode: 0x54 ('T') 1861 * 1862 * offset (8 bit): opcode 1863 * offset + 1 (8 bit): count 1864 * offset + 2 (8 bit): CRTC index 1 1865 * offset + 3 (8 bit): value 1 1866 * ... 1867 * 1868 * For "count", assign "value n" to CRTC register with index 1869 * "CRTC index n". 1870 */ 1871 1872 uint8_t count = bios->data[offset + 1]; 1873 int len = 2 + count * 2; 1874 int i; 1875 1876 if (!iexec->execute) 1877 return len; 1878 1879 for (i = 0; i < count; i++) 1880 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec); 1881 1882 return len; 1883} 1884 1885static int 1886init_condition_time(struct nvbios *bios, uint16_t offset, 1887 struct init_exec *iexec) 1888{ 1889 /* 1890 * INIT_CONDITION_TIME opcode: 0x56 ('V') 1891 * 1892 * offset (8 bit): opcode 1893 * offset + 1 (8 bit): condition number 1894 * offset + 2 (8 bit): retries / 50 1895 * 1896 * Check condition "condition number" in the condition table. 1897 * Bios code then sleeps for 2ms if the condition is not met, and 1898 * repeats up to "retries" times, but on one C51 this has proved 1899 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do 1900 * this, and bail after "retries" times, or 2s, whichever is less. 1901 * If still not met after retries, clear execution flag for this table. 1902 */ 1903 1904 uint8_t cond = bios->data[offset + 1]; 1905 uint16_t retries = bios->data[offset + 2] * 50; 1906 unsigned cnt; 1907 1908 if (!iexec->execute) 1909 return 3; 1910 1911 if (retries > 100) 1912 retries = 100; 1913 1914 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n", 1915 offset, cond, retries); 1916 1917 if (!bios->execute) /* avoid 2s delays when "faking" execution */ 1918 retries = 1; 1919 1920 for (cnt = 0; cnt < retries; cnt++) { 1921 if (bios_condition_met(bios, offset, cond)) { 1922 BIOSLOG(bios, "0x%04X: Condition met, continuing\n", 1923 offset); 1924 break; 1925 } else { 1926 BIOSLOG(bios, "0x%04X: " 1927 "Condition not met, sleeping for 20ms\n", 1928 offset); 1929 msleep(20); 1930 } 1931 } 1932 1933 if (!bios_condition_met(bios, offset, cond)) { 1934 NV_WARN(bios->dev, 1935 "0x%04X: Condition still not met after %dms, " 1936 "skipping following opcodes\n", offset, 20 * retries); 1937 iexec->execute = false; 1938 } 1939 1940 return 3; 1941} 1942 1943static int 1944init_zm_reg_sequence(struct nvbios *bios, uint16_t offset, 1945 struct init_exec *iexec) 1946{ 1947 /* 1948 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X') 1949 * 1950 * offset (8 bit): opcode 1951 * offset + 1 (32 bit): base register 1952 * offset + 5 (8 bit): count 1953 * offset + 6 (32 bit): value 1 1954 * ... 1955 * 1956 * Starting at offset + 6 there are "count" 32 bit values. 1957 * For "count" iterations set "base register" + 4 * current_iteration 1958 * to "value current_iteration" 1959 */ 1960 1961 uint32_t basereg = ROM32(bios->data[offset + 1]); 1962 uint32_t count = bios->data[offset + 5]; 1963 int len = 6 + count * 4; 1964 int i; 1965 1966 if (!iexec->execute) 1967 return len; 1968 1969 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n", 1970 offset, basereg, count); 1971 1972 for (i = 0; i < count; i++) { 1973 uint32_t reg = basereg + i * 4; 1974 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]); 1975 1976 bios_wr32(bios, reg, data); 1977 } 1978 1979 return len; 1980} 1981 1982static int 1983init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1984{ 1985 /* 1986 * INIT_SUB_DIRECT opcode: 0x5B ('[') 1987 * 1988 * offset (8 bit): opcode 1989 * offset + 1 (16 bit): subroutine offset (in bios) 1990 * 1991 * Calls a subroutine that will execute commands until INIT_DONE 1992 * is found. 1993 */ 1994 1995 uint16_t sub_offset = ROM16(bios->data[offset + 1]); 1996 1997 if (!iexec->execute) 1998 return 3; 1999 2000 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n", 2001 offset, sub_offset); 2002 2003 parse_init_table(bios, sub_offset, iexec); 2004 2005 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset); 2006 2007 return 3; 2008} 2009 2010static int 2011init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2012{ 2013 /* 2014 * INIT_COPY_NV_REG opcode: 0x5F ('_') 2015 * 2016 * offset (8 bit): opcode 2017 * offset + 1 (32 bit): src reg 2018 * offset + 5 (8 bit): shift 2019 * offset + 6 (32 bit): src mask 2020 * offset + 10 (32 bit): xor 2021 * offset + 14 (32 bit): dst reg 2022 * offset + 18 (32 bit): dst mask 2023 * 2024 * Shift REGVAL("src reg") right by (signed) "shift", AND result with 2025 * "src mask", then XOR with "xor". Write this OR'd with 2026 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg" 2027 */ 2028 2029 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1])); 2030 uint8_t shift = bios->data[offset + 5]; 2031 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6])); 2032 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10])); 2033 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14])); 2034 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18])); 2035 uint32_t srcvalue, dstvalue; 2036 2037 if (!iexec->execute) 2038 return 22; 2039 2040 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, " 2041 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n", 2042 offset, srcreg, shift, srcmask, xor, dstreg, dstmask); 2043 2044 srcvalue = bios_rd32(bios, srcreg); 2045 2046 if (shift < 0x80) 2047 srcvalue >>= shift; 2048 else 2049 srcvalue <<= (0x100 - shift); 2050 2051 srcvalue = (srcvalue & srcmask) ^ xor; 2052 2053 dstvalue = bios_rd32(bios, dstreg) & dstmask; 2054 2055 bios_wr32(bios, dstreg, dstvalue | srcvalue); 2056 2057 return 22; 2058} 2059 2060static int 2061init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2062{ 2063 /* 2064 * INIT_ZM_INDEX_IO opcode: 0x62 ('b') 2065 * 2066 * offset (8 bit): opcode 2067 * offset + 1 (16 bit): CRTC port 2068 * offset + 3 (8 bit): CRTC index 2069 * offset + 4 (8 bit): data 2070 * 2071 * Write "data" to index "CRTC index" of "CRTC port" 2072 */ 2073 uint16_t crtcport = ROM16(bios->data[offset + 1]); 2074 uint8_t crtcindex = bios->data[offset + 3]; 2075 uint8_t data = bios->data[offset + 4]; 2076 2077 if (!iexec->execute) 2078 return 5; 2079 2080 bios_idxprt_wr(bios, crtcport, crtcindex, data); 2081 2082 return 5; 2083} 2084 2085static int 2086init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2087{ 2088 /* 2089 * INIT_COMPUTE_MEM opcode: 0x63 ('c') 2090 * 2091 * offset (8 bit): opcode 2092 * 2093 * This opcode is meant to set NV_PFB_CFG0 (0x100200) appropriately so 2094 * that the hardware can correctly calculate how much VRAM it has 2095 * (and subsequently report that value in NV_PFB_CSTATUS (0x10020C)) 2096 * 2097 * The implementation of this opcode in general consists of two parts: 2098 * 1) determination of the memory bus width 2099 * 2) determination of how many of the card's RAM pads have ICs attached 2100 * 2101 * 1) is done by a cunning combination of writes to offsets 0x1c and 2102 * 0x3c in the framebuffer, and seeing whether the written values are 2103 * read back correctly. This then affects bits 4-7 of NV_PFB_CFG0 2104 * 2105 * 2) is done by a cunning combination of writes to an offset slightly 2106 * less than the maximum memory reported by NV_PFB_CSTATUS, then seeing 2107 * if the test pattern can be read back. This then affects bits 12-15 of 2108 * NV_PFB_CFG0 2109 * 2110 * In this context a "cunning combination" may include multiple reads 2111 * and writes to varying locations, often alternating the test pattern 2112 * and 0, doubtless to make sure buffers are filled, residual charges 2113 * on tracks are removed etc. 2114 * 2115 * Unfortunately, the "cunning combination"s mentioned above, and the 2116 * changes to the bits in NV_PFB_CFG0 differ with nearly every bios 2117 * trace I have. 2118 * 2119 * Therefore, we cheat and assume the value of NV_PFB_CFG0 with which 2120 * we started was correct, and use that instead 2121 */ 2122 2123 /* no iexec->execute check by design */ 2124 2125 /* 2126 * This appears to be a NOP on G8x chipsets, both io logs of the VBIOS 2127 * and kmmio traces of the binary driver POSTing the card show nothing 2128 * being done for this opcode. why is it still listed in the table?! 2129 */ 2130 2131 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2132 2133 if (dev_priv->card_type >= NV_40) 2134 return 1; 2135 2136 /* 2137 * On every card I've seen, this step gets done for us earlier in 2138 * the init scripts 2139 uint8_t crdata = bios_idxprt_rd(dev, NV_VIO_SRX, 0x01); 2140 bios_idxprt_wr(dev, NV_VIO_SRX, 0x01, crdata | 0x20); 2141 */ 2142 2143 /* 2144 * This also has probably been done in the scripts, but an mmio trace of 2145 * s3 resume shows nvidia doing it anyway (unlike the NV_VIO_SRX write) 2146 */ 2147 bios_wr32(bios, NV_PFB_REFCTRL, NV_PFB_REFCTRL_VALID_1); 2148 2149 /* write back the saved configuration value */ 2150 bios_wr32(bios, NV_PFB_CFG0, bios->state.saved_nv_pfb_cfg0); 2151 2152 return 1; 2153} 2154 2155static int 2156init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2157{ 2158 /* 2159 * INIT_RESET opcode: 0x65 ('e') 2160 * 2161 * offset (8 bit): opcode 2162 * offset + 1 (32 bit): register 2163 * offset + 5 (32 bit): value1 2164 * offset + 9 (32 bit): value2 2165 * 2166 * Assign "value1" to "register", then assign "value2" to "register" 2167 */ 2168 2169 uint32_t reg = ROM32(bios->data[offset + 1]); 2170 uint32_t value1 = ROM32(bios->data[offset + 5]); 2171 uint32_t value2 = ROM32(bios->data[offset + 9]); 2172 uint32_t pci_nv_19, pci_nv_20; 2173 2174 /* no iexec->execute check by design */ 2175 2176 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19); 2177 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19 & ~0xf00); 2178 2179 bios_wr32(bios, reg, value1); 2180 2181 udelay(10); 2182 2183 bios_wr32(bios, reg, value2); 2184 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19); 2185 2186 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20); 2187 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */ 2188 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20); 2189 2190 return 13; 2191} 2192 2193static int 2194init_configure_mem(struct nvbios *bios, uint16_t offset, 2195 struct init_exec *iexec) 2196{ 2197 /* 2198 * INIT_CONFIGURE_MEM opcode: 0x66 ('f') 2199 * 2200 * offset (8 bit): opcode 2201 * 2202 * Equivalent to INIT_DONE on bios version 3 or greater. 2203 * For early bios versions, sets up the memory registers, using values 2204 * taken from the memory init table 2205 */ 2206 2207 /* no iexec->execute check by design */ 2208 2209 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4); 2210 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6; 2211 uint32_t reg, data; 2212 2213 if (bios->major_version > 2) 2214 return -ENODEV; 2215 2216 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd( 2217 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20); 2218 2219 if (bios->data[meminitoffs] & 1) 2220 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr; 2221 2222 for (reg = ROM32(bios->data[seqtbloffs]); 2223 reg != 0xffffffff; 2224 reg = ROM32(bios->data[seqtbloffs += 4])) { 2225 2226 switch (reg) { 2227 case NV_PFB_PRE: 2228 data = NV_PFB_PRE_CMD_PRECHARGE; 2229 break; 2230 case NV_PFB_PAD: 2231 data = NV_PFB_PAD_CKE_NORMAL; 2232 break; 2233 case NV_PFB_REF: 2234 data = NV_PFB_REF_CMD_REFRESH; 2235 break; 2236 default: 2237 data = ROM32(bios->data[meminitdata]); 2238 meminitdata += 4; 2239 if (data == 0xffffffff) 2240 continue; 2241 } 2242 2243 bios_wr32(bios, reg, data); 2244 } 2245 2246 return 1; 2247} 2248 2249static int 2250init_configure_clk(struct nvbios *bios, uint16_t offset, 2251 struct init_exec *iexec) 2252{ 2253 /* 2254 * INIT_CONFIGURE_CLK opcode: 0x67 ('g') 2255 * 2256 * offset (8 bit): opcode 2257 * 2258 * Equivalent to INIT_DONE on bios version 3 or greater. 2259 * For early bios versions, sets up the NVClk and MClk PLLs, using 2260 * values taken from the memory init table 2261 */ 2262 2263 /* no iexec->execute check by design */ 2264 2265 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4); 2266 int clock; 2267 2268 if (bios->major_version > 2) 2269 return -ENODEV; 2270 2271 clock = ROM16(bios->data[meminitoffs + 4]) * 10; 2272 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock); 2273 2274 clock = ROM16(bios->data[meminitoffs + 2]) * 10; 2275 if (bios->data[meminitoffs] & 1) /* DDR */ 2276 clock *= 2; 2277 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock); 2278 2279 return 1; 2280} 2281 2282static int 2283init_configure_preinit(struct nvbios *bios, uint16_t offset, 2284 struct init_exec *iexec) 2285{ 2286 /* 2287 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h') 2288 * 2289 * offset (8 bit): opcode 2290 * 2291 * Equivalent to INIT_DONE on bios version 3 or greater. 2292 * For early bios versions, does early init, loading ram and crystal 2293 * configuration from straps into CR3C 2294 */ 2295 2296 /* no iexec->execute check by design */ 2297 2298 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0); 2299 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & (1 << 6)); 2300 2301 if (bios->major_version > 2) 2302 return -ENODEV; 2303 2304 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, 2305 NV_CIO_CRE_SCRATCH4__INDEX, cr3c); 2306 2307 return 1; 2308} 2309 2310static int 2311init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2312{ 2313 /* 2314 * INIT_IO opcode: 0x69 ('i') 2315 * 2316 * offset (8 bit): opcode 2317 * offset + 1 (16 bit): CRTC port 2318 * offset + 3 (8 bit): mask 2319 * offset + 4 (8 bit): data 2320 * 2321 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port" 2322 */ 2323 2324 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2325 uint16_t crtcport = ROM16(bios->data[offset + 1]); 2326 uint8_t mask = bios->data[offset + 3]; 2327 uint8_t data = bios->data[offset + 4]; 2328 2329 if (!iexec->execute) 2330 return 5; 2331 2332 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n", 2333 offset, crtcport, mask, data); 2334 2335 /* 2336 * I have no idea what this does, but NVIDIA do this magic sequence 2337 * in the places where this INIT_IO happens.. 2338 */ 2339 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) { 2340 int i; 2341 2342 bios_wr32(bios, 0x614100, (bios_rd32( 2343 bios, 0x614100) & 0x0fffffff) | 0x00800000); 2344 2345 bios_wr32(bios, 0x00e18c, bios_rd32( 2346 bios, 0x00e18c) | 0x00020000); 2347 2348 bios_wr32(bios, 0x614900, (bios_rd32( 2349 bios, 0x614900) & 0x0fffffff) | 0x00800000); 2350 2351 bios_wr32(bios, 0x000200, bios_rd32( 2352 bios, 0x000200) & ~0x40000000); 2353 2354 mdelay(10); 2355 2356 bios_wr32(bios, 0x00e18c, bios_rd32( 2357 bios, 0x00e18c) & ~0x00020000); 2358 2359 bios_wr32(bios, 0x000200, bios_rd32( 2360 bios, 0x000200) | 0x40000000); 2361 2362 bios_wr32(bios, 0x614100, 0x00800018); 2363 bios_wr32(bios, 0x614900, 0x00800018); 2364 2365 mdelay(10); 2366 2367 bios_wr32(bios, 0x614100, 0x10000018); 2368 bios_wr32(bios, 0x614900, 0x10000018); 2369 2370 for (i = 0; i < 3; i++) 2371 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32( 2372 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0); 2373 2374 for (i = 0; i < 2; i++) 2375 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32( 2376 bios, 0x614300 + (i*0x800)) & 0xfffff0f0); 2377 2378 for (i = 0; i < 3; i++) 2379 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32( 2380 bios, 0x614380 + (i*0x800)) & 0xfffff0f0); 2381 2382 for (i = 0; i < 2; i++) 2383 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32( 2384 bios, 0x614200 + (i*0x800)) & 0xfffffff0); 2385 2386 for (i = 0; i < 2; i++) 2387 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32( 2388 bios, 0x614108 + (i*0x800)) & 0x0fffffff); 2389 return 5; 2390 } 2391 2392 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) | 2393 data); 2394 return 5; 2395} 2396 2397static int 2398init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2399{ 2400 /* 2401 * INIT_SUB opcode: 0x6B ('k') 2402 * 2403 * offset (8 bit): opcode 2404 * offset + 1 (8 bit): script number 2405 * 2406 * Execute script number "script number", as a subroutine 2407 */ 2408 2409 uint8_t sub = bios->data[offset + 1]; 2410 2411 if (!iexec->execute) 2412 return 2; 2413 2414 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub); 2415 2416 parse_init_table(bios, 2417 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]), 2418 iexec); 2419 2420 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub); 2421 2422 return 2; 2423} 2424 2425static int 2426init_ram_condition(struct nvbios *bios, uint16_t offset, 2427 struct init_exec *iexec) 2428{ 2429 /* 2430 * INIT_RAM_CONDITION opcode: 0x6D ('m') 2431 * 2432 * offset (8 bit): opcode 2433 * offset + 1 (8 bit): mask 2434 * offset + 2 (8 bit): cmpval 2435 * 2436 * Test if (NV_PFB_BOOT_0 & "mask") equals "cmpval". 2437 * If condition not met skip subsequent opcodes until condition is 2438 * inverted (INIT_NOT), or we hit INIT_RESUME 2439 */ 2440 2441 uint8_t mask = bios->data[offset + 1]; 2442 uint8_t cmpval = bios->data[offset + 2]; 2443 uint8_t data; 2444 2445 if (!iexec->execute) 2446 return 3; 2447 2448 data = bios_rd32(bios, NV_PFB_BOOT_0) & mask; 2449 2450 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n", 2451 offset, data, cmpval); 2452 2453 if (data == cmpval) 2454 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 2455 else { 2456 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 2457 iexec->execute = false; 2458 } 2459 2460 return 3; 2461} 2462 2463static int 2464init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2465{ 2466 /* 2467 * INIT_NV_REG opcode: 0x6E ('n') 2468 * 2469 * offset (8 bit): opcode 2470 * offset + 1 (32 bit): register 2471 * offset + 5 (32 bit): mask 2472 * offset + 9 (32 bit): data 2473 * 2474 * Assign ((REGVAL("register") & "mask") | "data") to "register" 2475 */ 2476 2477 uint32_t reg = ROM32(bios->data[offset + 1]); 2478 uint32_t mask = ROM32(bios->data[offset + 5]); 2479 uint32_t data = ROM32(bios->data[offset + 9]); 2480 2481 if (!iexec->execute) 2482 return 13; 2483 2484 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n", 2485 offset, reg, mask, data); 2486 2487 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data); 2488 2489 return 13; 2490} 2491 2492static int 2493init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2494{ 2495 /* 2496 * INIT_MACRO opcode: 0x6F ('o') 2497 * 2498 * offset (8 bit): opcode 2499 * offset + 1 (8 bit): macro number 2500 * 2501 * Look up macro index "macro number" in the macro index table. 2502 * The macro index table entry has 1 byte for the index in the macro 2503 * table, and 1 byte for the number of times to repeat the macro. 2504 * The macro table entry has 4 bytes for the register address and 2505 * 4 bytes for the value to write to that register 2506 */ 2507 2508 uint8_t macro_index_tbl_idx = bios->data[offset + 1]; 2509 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE); 2510 uint8_t macro_tbl_idx = bios->data[tmp]; 2511 uint8_t count = bios->data[tmp + 1]; 2512 uint32_t reg, data; 2513 int i; 2514 2515 if (!iexec->execute) 2516 return 2; 2517 2518 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, " 2519 "Count: 0x%02X\n", 2520 offset, macro_index_tbl_idx, macro_tbl_idx, count); 2521 2522 for (i = 0; i < count; i++) { 2523 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE; 2524 2525 reg = ROM32(bios->data[macroentryptr]); 2526 data = ROM32(bios->data[macroentryptr + 4]); 2527 2528 bios_wr32(bios, reg, data); 2529 } 2530 2531 return 2; 2532} 2533 2534static int 2535init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2536{ 2537 /* 2538 * INIT_DONE opcode: 0x71 ('q') 2539 * 2540 * offset (8 bit): opcode 2541 * 2542 * End the current script 2543 */ 2544 2545 /* mild retval abuse to stop parsing this table */ 2546 return 0; 2547} 2548 2549static int 2550init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2551{ 2552 /* 2553 * INIT_RESUME opcode: 0x72 ('r') 2554 * 2555 * offset (8 bit): opcode 2556 * 2557 * End the current execute / no-execute condition 2558 */ 2559 2560 if (iexec->execute) 2561 return 1; 2562 2563 iexec->execute = true; 2564 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset); 2565 2566 return 1; 2567} 2568 2569static int 2570init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2571{ 2572 /* 2573 * INIT_TIME opcode: 0x74 ('t') 2574 * 2575 * offset (8 bit): opcode 2576 * offset + 1 (16 bit): time 2577 * 2578 * Sleep for "time" microseconds. 2579 */ 2580 2581 unsigned time = ROM16(bios->data[offset + 1]); 2582 2583 if (!iexec->execute) 2584 return 3; 2585 2586 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n", 2587 offset, time); 2588 2589 if (time < 1000) 2590 udelay(time); 2591 else 2592 msleep((time + 900) / 1000); 2593 2594 return 3; 2595} 2596 2597static int 2598init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2599{ 2600 /* 2601 * INIT_CONDITION opcode: 0x75 ('u') 2602 * 2603 * offset (8 bit): opcode 2604 * offset + 1 (8 bit): condition number 2605 * 2606 * Check condition "condition number" in the condition table. 2607 * If condition not met skip subsequent opcodes until condition is 2608 * inverted (INIT_NOT), or we hit INIT_RESUME 2609 */ 2610 2611 uint8_t cond = bios->data[offset + 1]; 2612 2613 if (!iexec->execute) 2614 return 2; 2615 2616 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond); 2617 2618 if (bios_condition_met(bios, offset, cond)) 2619 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 2620 else { 2621 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 2622 iexec->execute = false; 2623 } 2624 2625 return 2; 2626} 2627 2628static int 2629init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2630{ 2631 /* 2632 * INIT_IO_CONDITION opcode: 0x76 2633 * 2634 * offset (8 bit): opcode 2635 * offset + 1 (8 bit): condition number 2636 * 2637 * Check condition "condition number" in the io condition table. 2638 * If condition not met skip subsequent opcodes until condition is 2639 * inverted (INIT_NOT), or we hit INIT_RESUME 2640 */ 2641 2642 uint8_t cond = bios->data[offset + 1]; 2643 2644 if (!iexec->execute) 2645 return 2; 2646 2647 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond); 2648 2649 if (io_condition_met(bios, offset, cond)) 2650 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 2651 else { 2652 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 2653 iexec->execute = false; 2654 } 2655 2656 return 2; 2657} 2658 2659static int 2660init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2661{ 2662 /* 2663 * INIT_INDEX_IO opcode: 0x78 ('x') 2664 * 2665 * offset (8 bit): opcode 2666 * offset + 1 (16 bit): CRTC port 2667 * offset + 3 (8 bit): CRTC index 2668 * offset + 4 (8 bit): mask 2669 * offset + 5 (8 bit): data 2670 * 2671 * Read value at index "CRTC index" on "CRTC port", AND with "mask", 2672 * OR with "data", write-back 2673 */ 2674 2675 uint16_t crtcport = ROM16(bios->data[offset + 1]); 2676 uint8_t crtcindex = bios->data[offset + 3]; 2677 uint8_t mask = bios->data[offset + 4]; 2678 uint8_t data = bios->data[offset + 5]; 2679 uint8_t value; 2680 2681 if (!iexec->execute) 2682 return 6; 2683 2684 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 2685 "Data: 0x%02X\n", 2686 offset, crtcport, crtcindex, mask, data); 2687 2688 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data; 2689 bios_idxprt_wr(bios, crtcport, crtcindex, value); 2690 2691 return 6; 2692} 2693 2694static int 2695init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2696{ 2697 /* 2698 * INIT_PLL opcode: 0x79 ('y') 2699 * 2700 * offset (8 bit): opcode 2701 * offset + 1 (32 bit): register 2702 * offset + 5 (16 bit): freq 2703 * 2704 * Set PLL register "register" to coefficients for frequency (10kHz) 2705 * "freq" 2706 */ 2707 2708 uint32_t reg = ROM32(bios->data[offset + 1]); 2709 uint16_t freq = ROM16(bios->data[offset + 5]); 2710 2711 if (!iexec->execute) 2712 return 7; 2713 2714 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq); 2715 2716 setPLL(bios, reg, freq * 10); 2717 2718 return 7; 2719} 2720 2721static int 2722init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2723{ 2724 /* 2725 * INIT_ZM_REG opcode: 0x7A ('z') 2726 * 2727 * offset (8 bit): opcode 2728 * offset + 1 (32 bit): register 2729 * offset + 5 (32 bit): value 2730 * 2731 * Assign "value" to "register" 2732 */ 2733 2734 uint32_t reg = ROM32(bios->data[offset + 1]); 2735 uint32_t value = ROM32(bios->data[offset + 5]); 2736 2737 if (!iexec->execute) 2738 return 9; 2739 2740 if (reg == 0x000200) 2741 value |= 1; 2742 2743 bios_wr32(bios, reg, value); 2744 2745 return 9; 2746} 2747 2748static int 2749init_ram_restrict_pll(struct nvbios *bios, uint16_t offset, 2750 struct init_exec *iexec) 2751{ 2752 /* 2753 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('') 2754 * 2755 * offset (8 bit): opcode 2756 * offset + 1 (8 bit): PLL type 2757 * offset + 2 (32 bit): frequency 0 2758 * 2759 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at 2760 * ram_restrict_table_ptr. The value read from there is used to select 2761 * a frequency from the table starting at 'frequency 0' to be 2762 * programmed into the PLL corresponding to 'type'. 2763 * 2764 * The PLL limits table on cards using this opcode has a mapping of 2765 * 'type' to the relevant registers. 2766 */ 2767 2768 struct drm_device *dev = bios->dev; 2769 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2; 2770 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap]; 2771 uint8_t type = bios->data[offset + 1]; 2772 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]); 2773 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry; 2774 int len = 2 + bios->ram_restrict_group_count * 4; 2775 int i; 2776 2777 if (!iexec->execute) 2778 return len; 2779 2780 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) { 2781 NV_ERROR(dev, "PLL limits table not version 3.x\n"); 2782 return len; /* deliberate, allow default clocks to remain */ 2783 } 2784 2785 entry = pll_limits + pll_limits[1]; 2786 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) { 2787 if (entry[0] == type) { 2788 uint32_t reg = ROM32(entry[3]); 2789 2790 BIOSLOG(bios, "0x%04X: " 2791 "Type %02x Reg 0x%08x Freq %dKHz\n", 2792 offset, type, reg, freq); 2793 2794 setPLL(bios, reg, freq); 2795 return len; 2796 } 2797 } 2798 2799 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type); 2800 return len; 2801} 2802 2803static int 2804init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2805{ 2806 /* 2807 * INIT_8C opcode: 0x8C ('') 2808 * 2809 * NOP so far.... 2810 * 2811 */ 2812 2813 return 1; 2814} 2815 2816static int 2817init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2818{ 2819 /* 2820 * INIT_8D opcode: 0x8D ('') 2821 * 2822 * NOP so far.... 2823 * 2824 */ 2825 2826 return 1; 2827} 2828 2829static int 2830init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2831{ 2832 /* 2833 * INIT_GPIO opcode: 0x8E ('') 2834 * 2835 * offset (8 bit): opcode 2836 * 2837 * Loop over all entries in the DCB GPIO table, and initialise 2838 * each GPIO according to various values listed in each entry 2839 */ 2840 2841 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2842 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c }; 2843 int i; 2844 2845 if (dev_priv->card_type != NV_50) { 2846 NV_ERROR(bios->dev, "INIT_GPIO on unsupported chipset\n"); 2847 return 1; 2848 } 2849 2850 if (!iexec->execute) 2851 return 1; 2852 2853 for (i = 0; i < bios->dcb.gpio.entries; i++) { 2854 struct dcb_gpio_entry *gpio = &bios->dcb.gpio.entry[i]; 2855 uint32_t r, s, v; 2856 2857 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, gpio->entry); 2858 2859 BIOSLOG(bios, "0x%04X: set gpio 0x%02x, state %d\n", 2860 offset, gpio->tag, gpio->state_default); 2861 if (bios->execute) 2862 nv50_gpio_set(bios->dev, gpio->tag, gpio->state_default); 2863 2864 /* The NVIDIA binary driver doesn't appear to actually do 2865 * any of this, my VBIOS does however. 2866 */ 2867 /* Not a clue, needs de-magicing */ 2868 r = nv50_gpio_ctl[gpio->line >> 4]; 2869 s = (gpio->line & 0x0f); 2870 v = bios_rd32(bios, r) & ~(0x00010001 << s); 2871 switch ((gpio->entry & 0x06000000) >> 25) { 2872 case 1: 2873 v |= (0x00000001 << s); 2874 break; 2875 case 2: 2876 v |= (0x00010000 << s); 2877 break; 2878 default: 2879 break; 2880 } 2881 bios_wr32(bios, r, v); 2882 } 2883 2884 return 1; 2885} 2886 2887static int 2888init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset, 2889 struct init_exec *iexec) 2890{ 2891 /* 2892 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('') 2893 * 2894 * offset (8 bit): opcode 2895 * offset + 1 (32 bit): reg 2896 * offset + 5 (8 bit): regincrement 2897 * offset + 6 (8 bit): count 2898 * offset + 7 (32 bit): value 1,1 2899 * ... 2900 * 2901 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at 2902 * ram_restrict_table_ptr. The value read from here is 'n', and 2903 * "value 1,n" gets written to "reg". This repeats "count" times and on 2904 * each iteration 'm', "reg" increases by "regincrement" and 2905 * "value m,n" is used. The extent of n is limited by a number read 2906 * from the 'M' BIT table, herein called "blocklen" 2907 */ 2908 2909 uint32_t reg = ROM32(bios->data[offset + 1]); 2910 uint8_t regincrement = bios->data[offset + 5]; 2911 uint8_t count = bios->data[offset + 6]; 2912 uint32_t strap_ramcfg, data; 2913 /* previously set by 'M' BIT table */ 2914 uint16_t blocklen = bios->ram_restrict_group_count * 4; 2915 int len = 7 + count * blocklen; 2916 uint8_t index; 2917 int i; 2918 2919 /* critical! to know the length of the opcode */; 2920 if (!blocklen) { 2921 NV_ERROR(bios->dev, 2922 "0x%04X: Zero block length - has the M table " 2923 "been parsed?\n", offset); 2924 return -EINVAL; 2925 } 2926 2927 if (!iexec->execute) 2928 return len; 2929 2930 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf; 2931 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg]; 2932 2933 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, " 2934 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n", 2935 offset, reg, regincrement, count, strap_ramcfg, index); 2936 2937 for (i = 0; i < count; i++) { 2938 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]); 2939 2940 bios_wr32(bios, reg, data); 2941 2942 reg += regincrement; 2943 } 2944 2945 return len; 2946} 2947 2948static int 2949init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2950{ 2951 /* 2952 * INIT_COPY_ZM_REG opcode: 0x90 ('') 2953 * 2954 * offset (8 bit): opcode 2955 * offset + 1 (32 bit): src reg 2956 * offset + 5 (32 bit): dst reg 2957 * 2958 * Put contents of "src reg" into "dst reg" 2959 */ 2960 2961 uint32_t srcreg = ROM32(bios->data[offset + 1]); 2962 uint32_t dstreg = ROM32(bios->data[offset + 5]); 2963 2964 if (!iexec->execute) 2965 return 9; 2966 2967 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg)); 2968 2969 return 9; 2970} 2971 2972static int 2973init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset, 2974 struct init_exec *iexec) 2975{ 2976 /* 2977 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('') 2978 * 2979 * offset (8 bit): opcode 2980 * offset + 1 (32 bit): dst reg 2981 * offset + 5 (8 bit): count 2982 * offset + 6 (32 bit): data 1 2983 * ... 2984 * 2985 * For each of "count" values write "data n" to "dst reg" 2986 */ 2987 2988 uint32_t reg = ROM32(bios->data[offset + 1]); 2989 uint8_t count = bios->data[offset + 5]; 2990 int len = 6 + count * 4; 2991 int i; 2992 2993 if (!iexec->execute) 2994 return len; 2995 2996 for (i = 0; i < count; i++) { 2997 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]); 2998 bios_wr32(bios, reg, data); 2999 } 3000 3001 return len; 3002} 3003 3004static int 3005init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3006{ 3007 /* 3008 * INIT_RESERVED opcode: 0x92 ('') 3009 * 3010 * offset (8 bit): opcode 3011 * 3012 * Seemingly does nothing 3013 */ 3014 3015 return 1; 3016} 3017 3018static int 3019init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3020{ 3021 /* 3022 * INIT_96 opcode: 0x96 ('') 3023 * 3024 * offset (8 bit): opcode 3025 * offset + 1 (32 bit): sreg 3026 * offset + 5 (8 bit): sshift 3027 * offset + 6 (8 bit): smask 3028 * offset + 7 (8 bit): index 3029 * offset + 8 (32 bit): reg 3030 * offset + 12 (32 bit): mask 3031 * offset + 16 (8 bit): shift 3032 * 3033 */ 3034 3035 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2); 3036 uint32_t reg = ROM32(bios->data[offset + 8]); 3037 uint32_t mask = ROM32(bios->data[offset + 12]); 3038 uint32_t val; 3039 3040 val = bios_rd32(bios, ROM32(bios->data[offset + 1])); 3041 if (bios->data[offset + 5] < 0x80) 3042 val >>= bios->data[offset + 5]; 3043 else 3044 val <<= (0x100 - bios->data[offset + 5]); 3045 val &= bios->data[offset + 6]; 3046 3047 val = bios->data[ROM16(bios->data[xlatptr]) + val]; 3048 val <<= bios->data[offset + 16]; 3049 3050 if (!iexec->execute) 3051 return 17; 3052 3053 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val); 3054 return 17; 3055} 3056 3057static int 3058init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3059{ 3060 /* 3061 * INIT_97 opcode: 0x97 ('') 3062 * 3063 * offset (8 bit): opcode 3064 * offset + 1 (32 bit): register 3065 * offset + 5 (32 bit): mask 3066 * offset + 9 (32 bit): value 3067 * 3068 * Adds "value" to "register" preserving the fields specified 3069 * by "mask" 3070 */ 3071 3072 uint32_t reg = ROM32(bios->data[offset + 1]); 3073 uint32_t mask = ROM32(bios->data[offset + 5]); 3074 uint32_t add = ROM32(bios->data[offset + 9]); 3075 uint32_t val; 3076 3077 val = bios_rd32(bios, reg); 3078 val = (val & mask) | ((val + add) & ~mask); 3079 3080 if (!iexec->execute) 3081 return 13; 3082 3083 bios_wr32(bios, reg, val); 3084 return 13; 3085} 3086 3087static int 3088init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3089{ 3090 /* 3091 * INIT_AUXCH opcode: 0x98 ('') 3092 * 3093 * offset (8 bit): opcode 3094 * offset + 1 (32 bit): address 3095 * offset + 5 (8 bit): count 3096 * offset + 6 (8 bit): mask 0 3097 * offset + 7 (8 bit): data 0 3098 * ... 3099 * 3100 */ 3101 3102 struct drm_device *dev = bios->dev; 3103 struct nouveau_i2c_chan *auxch; 3104 uint32_t addr = ROM32(bios->data[offset + 1]); 3105 uint8_t count = bios->data[offset + 5]; 3106 int len = 6 + count * 2; 3107 int ret, i; 3108 3109 if (!bios->display.output) { 3110 NV_ERROR(dev, "INIT_AUXCH: no active output\n"); 3111 return len; 3112 } 3113 3114 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index); 3115 if (!auxch) { 3116 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n", 3117 bios->display.output->i2c_index); 3118 return len; 3119 } 3120 3121 if (!iexec->execute) 3122 return len; 3123 3124 offset += 6; 3125 for (i = 0; i < count; i++, offset += 2) { 3126 uint8_t data; 3127 3128 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1); 3129 if (ret) { 3130 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret); 3131 return len; 3132 } 3133 3134 data &= bios->data[offset + 0]; 3135 data |= bios->data[offset + 1]; 3136 3137 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1); 3138 if (ret) { 3139 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret); 3140 return len; 3141 } 3142 } 3143 3144 return len; 3145} 3146 3147static int 3148init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3149{ 3150 /* 3151 * INIT_ZM_AUXCH opcode: 0x99 ('') 3152 * 3153 * offset (8 bit): opcode 3154 * offset + 1 (32 bit): address 3155 * offset + 5 (8 bit): count 3156 * offset + 6 (8 bit): data 0 3157 * ... 3158 * 3159 */ 3160 3161 struct drm_device *dev = bios->dev; 3162 struct nouveau_i2c_chan *auxch; 3163 uint32_t addr = ROM32(bios->data[offset + 1]); 3164 uint8_t count = bios->data[offset + 5]; 3165 int len = 6 + count; 3166 int ret, i; 3167 3168 if (!bios->display.output) { 3169 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n"); 3170 return len; 3171 } 3172 3173 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index); 3174 if (!auxch) { 3175 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n", 3176 bios->display.output->i2c_index); 3177 return len; 3178 } 3179 3180 if (!iexec->execute) 3181 return len; 3182 3183 offset += 6; 3184 for (i = 0; i < count; i++, offset++) { 3185 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1); 3186 if (ret) { 3187 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret); 3188 return len; 3189 } 3190 } 3191 3192 return len; 3193} 3194 3195static struct init_tbl_entry itbl_entry[] = { 3196 /* command name , id , length , offset , mult , command handler */ 3197 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */ 3198 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog }, 3199 { "INIT_REPEAT" , 0x33, init_repeat }, 3200 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll }, 3201 { "INIT_END_REPEAT" , 0x36, init_end_repeat }, 3202 { "INIT_COPY" , 0x37, init_copy }, 3203 { "INIT_NOT" , 0x38, init_not }, 3204 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition }, 3205 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition }, 3206 { "INIT_OP_3B" , 0x3B, init_op_3b }, 3207 { "INIT_OP_3C" , 0x3C, init_op_3c }, 3208 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched }, 3209 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 }, 3210 { "INIT_PLL2" , 0x4B, init_pll2 }, 3211 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte }, 3212 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte }, 3213 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c }, 3214 { "INIT_TMDS" , 0x4F, init_tmds }, 3215 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group }, 3216 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch }, 3217 { "INIT_CR" , 0x52, init_cr }, 3218 { "INIT_ZM_CR" , 0x53, init_zm_cr }, 3219 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group }, 3220 { "INIT_CONDITION_TIME" , 0x56, init_condition_time }, 3221 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence }, 3222 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */ 3223 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct }, 3224 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg }, 3225 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io }, 3226 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem }, 3227 { "INIT_RESET" , 0x65, init_reset }, 3228 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem }, 3229 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk }, 3230 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit }, 3231 { "INIT_IO" , 0x69, init_io }, 3232 { "INIT_SUB" , 0x6B, init_sub }, 3233 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition }, 3234 { "INIT_NV_REG" , 0x6E, init_nv_reg }, 3235 { "INIT_MACRO" , 0x6F, init_macro }, 3236 { "INIT_DONE" , 0x71, init_done }, 3237 { "INIT_RESUME" , 0x72, init_resume }, 3238 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */ 3239 { "INIT_TIME" , 0x74, init_time }, 3240 { "INIT_CONDITION" , 0x75, init_condition }, 3241 { "INIT_IO_CONDITION" , 0x76, init_io_condition }, 3242 { "INIT_INDEX_IO" , 0x78, init_index_io }, 3243 { "INIT_PLL" , 0x79, init_pll }, 3244 { "INIT_ZM_REG" , 0x7A, init_zm_reg }, 3245 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll }, 3246 { "INIT_8C" , 0x8C, init_8c }, 3247 { "INIT_8D" , 0x8D, init_8d }, 3248 { "INIT_GPIO" , 0x8E, init_gpio }, 3249 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group }, 3250 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg }, 3251 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched }, 3252 { "INIT_RESERVED" , 0x92, init_reserved }, 3253 { "INIT_96" , 0x96, init_96 }, 3254 { "INIT_97" , 0x97, init_97 }, 3255 { "INIT_AUXCH" , 0x98, init_auxch }, 3256 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch }, 3257 { NULL , 0 , NULL } 3258}; 3259 3260#define MAX_TABLE_OPS 1000 3261 3262static int 3263parse_init_table(struct nvbios *bios, unsigned int offset, 3264 struct init_exec *iexec) 3265{ 3266 /* 3267 * Parses all commands in an init table. 3268 * 3269 * We start out executing all commands found in the init table. Some 3270 * opcodes may change the status of iexec->execute to SKIP, which will 3271 * cause the following opcodes to perform no operation until the value 3272 * is changed back to EXECUTE. 3273 */ 3274 3275 int count = 0, i, ret; 3276 uint8_t id; 3277 3278 /* 3279 * Loop until INIT_DONE causes us to break out of the loop 3280 * (or until offset > bios length just in case... ) 3281 * (and no more than MAX_TABLE_OPS iterations, just in case... ) 3282 */ 3283 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) { 3284 id = bios->data[offset]; 3285 3286 /* Find matching id in itbl_entry */ 3287 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++) 3288 ; 3289 3290 if (!itbl_entry[i].name) { 3291 NV_ERROR(bios->dev, 3292 "0x%04X: Init table command not found: " 3293 "0x%02X\n", offset, id); 3294 return -ENOENT; 3295 } 3296 3297 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset, 3298 itbl_entry[i].id, itbl_entry[i].name); 3299 3300 /* execute eventual command handler */ 3301 ret = (*itbl_entry[i].handler)(bios, offset, iexec); 3302 if (ret < 0) { 3303 NV_ERROR(bios->dev, "0x%04X: Failed parsing init " 3304 "table opcode: %s %d\n", offset, 3305 itbl_entry[i].name, ret); 3306 } 3307 3308 if (ret <= 0) 3309 break; 3310 3311 /* 3312 * Add the offset of the current command including all data 3313 * of that command. The offset will then be pointing on the 3314 * next op code. 3315 */ 3316 offset += ret; 3317 } 3318 3319 if (offset >= bios->length) 3320 NV_WARN(bios->dev, 3321 "Offset 0x%04X greater than known bios image length. " 3322 "Corrupt image?\n", offset); 3323 if (count >= MAX_TABLE_OPS) 3324 NV_WARN(bios->dev, 3325 "More than %d opcodes to a table is unlikely, " 3326 "is the bios image corrupt?\n", MAX_TABLE_OPS); 3327 3328 return 0; 3329} 3330 3331static void 3332parse_init_tables(struct nvbios *bios) 3333{ 3334 /* Loops and calls parse_init_table() for each present table. */ 3335 3336 int i = 0; 3337 uint16_t table; 3338 struct init_exec iexec = {true, false}; 3339 3340 if (bios->old_style_init) { 3341 if (bios->init_script_tbls_ptr) 3342 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec); 3343 if (bios->extra_init_script_tbl_ptr) 3344 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec); 3345 3346 return; 3347 } 3348 3349 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) { 3350 NV_INFO(bios->dev, 3351 "Parsing VBIOS init table %d at offset 0x%04X\n", 3352 i / 2, table); 3353 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table); 3354 3355 parse_init_table(bios, table, &iexec); 3356 i += 2; 3357 } 3358} 3359 3360static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk) 3361{ 3362 int compare_record_len, i = 0; 3363 uint16_t compareclk, scriptptr = 0; 3364 3365 if (bios->major_version < 5) /* pre BIT */ 3366 compare_record_len = 3; 3367 else 3368 compare_record_len = 4; 3369 3370 do { 3371 compareclk = ROM16(bios->data[clktable + compare_record_len * i]); 3372 if (pxclk >= compareclk * 10) { 3373 if (bios->major_version < 5) { 3374 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i]; 3375 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]); 3376 } else 3377 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]); 3378 break; 3379 } 3380 i++; 3381 } while (compareclk); 3382 3383 return scriptptr; 3384} 3385 3386static void 3387run_digital_op_script(struct drm_device *dev, uint16_t scriptptr, 3388 struct dcb_entry *dcbent, int head, bool dl) 3389{ 3390 struct drm_nouveau_private *dev_priv = dev->dev_private; 3391 struct nvbios *bios = &dev_priv->vbios; 3392 struct init_exec iexec = {true, false}; 3393 3394 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n", 3395 scriptptr); 3396 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44, 3397 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA); 3398 /* note: if dcb entries have been merged, index may be misleading */ 3399 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index); 3400 parse_init_table(bios, scriptptr, &iexec); 3401 3402 nv04_dfp_bind_head(dev, dcbent, head, dl); 3403} 3404 3405static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script) 3406{ 3407 struct drm_nouveau_private *dev_priv = dev->dev_private; 3408 struct nvbios *bios = &dev_priv->vbios; 3409 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0); 3410 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]); 3411 3412 if (!bios->fp.xlated_entry || !sub || !scriptofs) 3413 return -EINVAL; 3414 3415 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link); 3416 3417 if (script == LVDS_PANEL_OFF) { 3418 /* off-on delay in ms */ 3419 msleep(ROM16(bios->data[bios->fp.xlated_entry + 7])); 3420 } 3421#ifdef __powerpc__ 3422 /* Powerbook specific quirks */ 3423 if ((dev->pci_device & 0xffff) == 0x0179 || 3424 (dev->pci_device & 0xffff) == 0x0189 || 3425 (dev->pci_device & 0xffff) == 0x0329) { 3426 if (script == LVDS_RESET) { 3427 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72); 3428 3429 } else if (script == LVDS_PANEL_ON) { 3430 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL, 3431 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL) 3432 | (1 << 31)); 3433 bios_wr32(bios, NV_PCRTC_GPIO_EXT, 3434 bios_rd32(bios, NV_PCRTC_GPIO_EXT) | 1); 3435 3436 } else if (script == LVDS_PANEL_OFF) { 3437 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL, 3438 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL) 3439 & ~(1 << 31)); 3440 bios_wr32(bios, NV_PCRTC_GPIO_EXT, 3441 bios_rd32(bios, NV_PCRTC_GPIO_EXT) & ~3); 3442 } 3443 } 3444#endif 3445 3446 return 0; 3447} 3448 3449static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk) 3450{ 3451 /* 3452 * The BIT LVDS table's header has the information to setup the 3453 * necessary registers. Following the standard 4 byte header are: 3454 * A bitmask byte and a dual-link transition pxclk value for use in 3455 * selecting the init script when not using straps; 4 script pointers 3456 * for panel power, selected by output and on/off; and 8 table pointers 3457 * for panel init, the needed one determined by output, and bits in the 3458 * conf byte. These tables are similar to the TMDS tables, consisting 3459 * of a list of pxclks and script pointers. 3460 */ 3461 struct drm_nouveau_private *dev_priv = dev->dev_private; 3462 struct nvbios *bios = &dev_priv->vbios; 3463 unsigned int outputset = (dcbent->or == 4) ? 1 : 0; 3464 uint16_t scriptptr = 0, clktable; 3465 3466 /* 3467 * For now we assume version 3.0 table - g80 support will need some 3468 * changes 3469 */ 3470 3471 switch (script) { 3472 case LVDS_INIT: 3473 return -ENOSYS; 3474 case LVDS_BACKLIGHT_ON: 3475 case LVDS_PANEL_ON: 3476 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]); 3477 break; 3478 case LVDS_BACKLIGHT_OFF: 3479 case LVDS_PANEL_OFF: 3480 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]); 3481 break; 3482 case LVDS_RESET: 3483 clktable = bios->fp.lvdsmanufacturerpointer + 15; 3484 if (dcbent->or == 4) 3485 clktable += 8; 3486 3487 if (dcbent->lvdsconf.use_straps_for_mode) { 3488 if (bios->fp.dual_link) 3489 clktable += 4; 3490 if (bios->fp.if_is_24bit) 3491 clktable += 2; 3492 } else { 3493 /* using EDID */ 3494 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1; 3495 3496 if (bios->fp.dual_link) { 3497 clktable += 4; 3498 cmpval_24bit <<= 1; 3499 } 3500 3501 if (bios->fp.strapless_is_24bit & cmpval_24bit) 3502 clktable += 2; 3503 } 3504 3505 clktable = ROM16(bios->data[clktable]); 3506 if (!clktable) { 3507 NV_ERROR(dev, "Pixel clock comparison table not found\n"); 3508 return -ENOENT; 3509 } 3510 scriptptr = clkcmptable(bios, clktable, pxclk); 3511 } 3512 3513 if (!scriptptr) { 3514 NV_ERROR(dev, "LVDS output init script not found\n"); 3515 return -ENOENT; 3516 } 3517 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link); 3518 3519 return 0; 3520} 3521 3522int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk) 3523{ 3524 /* 3525 * LVDS operations are multiplexed in an effort to present a single API 3526 * which works with two vastly differing underlying structures. 3527 * This acts as the demux 3528 */ 3529 3530 struct drm_nouveau_private *dev_priv = dev->dev_private; 3531 struct nvbios *bios = &dev_priv->vbios; 3532 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer]; 3533 uint32_t sel_clk_binding, sel_clk; 3534 int ret; 3535 3536 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver || 3537 (lvds_ver >= 0x30 && script == LVDS_INIT)) 3538 return 0; 3539 3540 if (!bios->fp.lvds_init_run) { 3541 bios->fp.lvds_init_run = true; 3542 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk); 3543 } 3544 3545 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change) 3546 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk); 3547 if (script == LVDS_RESET && bios->fp.power_off_for_reset) 3548 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk); 3549 3550 NV_TRACE(dev, "Calling LVDS script %d:\n", script); 3551 3552 /* don't let script change pll->head binding */ 3553 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000; 3554 3555 if (lvds_ver < 0x30) 3556 ret = call_lvds_manufacturer_script(dev, dcbent, head, script); 3557 else 3558 ret = run_lvds_table(dev, dcbent, head, script, pxclk); 3559 3560 bios->fp.last_script_invoc = (script << 1 | head); 3561 3562 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; 3563 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); 3564 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */ 3565 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0); 3566 3567 return ret; 3568} 3569 3570struct lvdstableheader { 3571 uint8_t lvds_ver, headerlen, recordlen; 3572}; 3573 3574static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth) 3575{ 3576 /* 3577 * BMP version (0xa) LVDS table has a simple header of version and 3578 * record length. The BIT LVDS table has the typical BIT table header: 3579 * version byte, header length byte, record length byte, and a byte for 3580 * the maximum number of records that can be held in the table. 3581 */ 3582 3583 uint8_t lvds_ver, headerlen, recordlen; 3584 3585 memset(lth, 0, sizeof(struct lvdstableheader)); 3586 3587 if (bios->fp.lvdsmanufacturerpointer == 0x0) { 3588 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n"); 3589 return -EINVAL; 3590 } 3591 3592 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer]; 3593 3594 switch (lvds_ver) { 3595 case 0x0a: /* pre NV40 */ 3596 headerlen = 2; 3597 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 3598 break; 3599 case 0x30: /* NV4x */ 3600 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 3601 if (headerlen < 0x1f) { 3602 NV_ERROR(dev, "LVDS table header not understood\n"); 3603 return -EINVAL; 3604 } 3605 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2]; 3606 break; 3607 case 0x40: /* G80/G90 */ 3608 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 3609 if (headerlen < 0x7) { 3610 NV_ERROR(dev, "LVDS table header not understood\n"); 3611 return -EINVAL; 3612 } 3613 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2]; 3614 break; 3615 default: 3616 NV_ERROR(dev, 3617 "LVDS table revision %d.%d not currently supported\n", 3618 lvds_ver >> 4, lvds_ver & 0xf); 3619 return -ENOSYS; 3620 } 3621 3622 lth->lvds_ver = lvds_ver; 3623 lth->headerlen = headerlen; 3624 lth->recordlen = recordlen; 3625 3626 return 0; 3627} 3628 3629static int 3630get_fp_strap(struct drm_device *dev, struct nvbios *bios) 3631{ 3632 struct drm_nouveau_private *dev_priv = dev->dev_private; 3633 3634 /* 3635 * The fp strap is normally dictated by the "User Strap" in 3636 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the 3637 * Internal_Flags struct at 0x48 is set, the user strap gets overriden 3638 * by the PCI subsystem ID during POST, but not before the previous user 3639 * strap has been committed to CR58 for CR57=0xf on head A, which may be 3640 * read and used instead 3641 */ 3642 3643 if (bios->major_version < 5 && bios->data[0x48] & 0x4) 3644 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf; 3645 3646 if (dev_priv->card_type >= NV_50) 3647 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf; 3648 else 3649 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf; 3650} 3651 3652static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios) 3653{ 3654 uint8_t *fptable; 3655 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex; 3656 int ret, ofs, fpstrapping; 3657 struct lvdstableheader lth; 3658 3659 if (bios->fp.fptablepointer == 0x0) { 3660 /* Apple cards don't have the fp table; the laptops use DDC */ 3661 /* The table is also missing on some x86 IGPs */ 3662#ifndef __powerpc__ 3663 NV_ERROR(dev, "Pointer to flat panel table invalid\n"); 3664#endif 3665 bios->digital_min_front_porch = 0x4b; 3666 return 0; 3667 } 3668 3669 fptable = &bios->data[bios->fp.fptablepointer]; 3670 fptable_ver = fptable[0]; 3671 3672 switch (fptable_ver) { 3673 /* 3674 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no 3675 * version field, and miss one of the spread spectrum/PWM bytes. 3676 * This could affect early GF2Go parts (not seen any appropriate ROMs 3677 * though). Here we assume that a version of 0x05 matches this case 3678 * (combining with a BMP version check would be better), as the 3679 * common case for the panel type field is 0x0005, and that is in 3680 * fact what we are reading the first byte of. 3681 */ 3682 case 0x05: /* some NV10, 11, 15, 16 */ 3683 recordlen = 42; 3684 ofs = -1; 3685 break; 3686 case 0x10: /* some NV15/16, and NV11+ */ 3687 recordlen = 44; 3688 ofs = 0; 3689 break; 3690 case 0x20: /* NV40+ */ 3691 headerlen = fptable[1]; 3692 recordlen = fptable[2]; 3693 fpentries = fptable[3]; 3694 /* 3695 * fptable[4] is the minimum 3696 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap 3697 */ 3698 bios->digital_min_front_porch = fptable[4]; 3699 ofs = -7; 3700 break; 3701 default: 3702 NV_ERROR(dev, 3703 "FP table revision %d.%d not currently supported\n", 3704 fptable_ver >> 4, fptable_ver & 0xf); 3705 return -ENOSYS; 3706 } 3707 3708 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */ 3709 return 0; 3710 3711 ret = parse_lvds_manufacturer_table_header(dev, bios, <h); 3712 if (ret) 3713 return ret; 3714 3715 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) { 3716 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer + 3717 lth.headerlen + 1; 3718 bios->fp.xlatwidth = lth.recordlen; 3719 } 3720 if (bios->fp.fpxlatetableptr == 0x0) { 3721 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n"); 3722 return -EINVAL; 3723 } 3724 3725 fpstrapping = get_fp_strap(dev, bios); 3726 3727 fpindex = bios->data[bios->fp.fpxlatetableptr + 3728 fpstrapping * bios->fp.xlatwidth]; 3729 3730 if (fpindex > fpentries) { 3731 NV_ERROR(dev, "Bad flat panel table index\n"); 3732 return -ENOENT; 3733 } 3734 3735 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */ 3736 if (lth.lvds_ver > 0x10) 3737 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf; 3738 3739 /* 3740 * If either the strap or xlated fpindex value are 0xf there is no 3741 * panel using a strap-derived bios mode present. this condition 3742 * includes, but is different from, the DDC panel indicator above 3743 */ 3744 if (fpstrapping == 0xf || fpindex == 0xf) 3745 return 0; 3746 3747 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen + 3748 recordlen * fpindex + ofs; 3749 3750 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n", 3751 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1, 3752 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1, 3753 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10); 3754 3755 return 0; 3756} 3757 3758bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode) 3759{ 3760 struct drm_nouveau_private *dev_priv = dev->dev_private; 3761 struct nvbios *bios = &dev_priv->vbios; 3762 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr]; 3763 3764 if (!mode) /* just checking whether we can produce a mode */ 3765 return bios->fp.mode_ptr; 3766 3767 memset(mode, 0, sizeof(struct drm_display_mode)); 3768 /* 3769 * For version 1.0 (version in byte 0): 3770 * bytes 1-2 are "panel type", including bits on whether Colour/mono, 3771 * single/dual link, and type (TFT etc.) 3772 * bytes 3-6 are bits per colour in RGBX 3773 */ 3774 mode->clock = ROM16(mode_entry[7]) * 10; 3775 /* bytes 9-10 is HActive */ 3776 mode->hdisplay = ROM16(mode_entry[11]) + 1; 3777 /* 3778 * bytes 13-14 is HValid Start 3779 * bytes 15-16 is HValid End 3780 */ 3781 mode->hsync_start = ROM16(mode_entry[17]) + 1; 3782 mode->hsync_end = ROM16(mode_entry[19]) + 1; 3783 mode->htotal = ROM16(mode_entry[21]) + 1; 3784 /* bytes 23-24, 27-30 similarly, but vertical */ 3785 mode->vdisplay = ROM16(mode_entry[25]) + 1; 3786 mode->vsync_start = ROM16(mode_entry[31]) + 1; 3787 mode->vsync_end = ROM16(mode_entry[33]) + 1; 3788 mode->vtotal = ROM16(mode_entry[35]) + 1; 3789 mode->flags |= (mode_entry[37] & 0x10) ? 3790 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3791 mode->flags |= (mode_entry[37] & 0x1) ? 3792 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3793 /* 3794 * bytes 38-39 relate to spread spectrum settings 3795 * bytes 40-43 are something to do with PWM 3796 */ 3797 3798 mode->status = MODE_OK; 3799 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; 3800 drm_mode_set_name(mode); 3801 return bios->fp.mode_ptr; 3802} 3803 3804int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit) 3805{ 3806 /* 3807 * The LVDS table header is (mostly) described in 3808 * parse_lvds_manufacturer_table_header(): the BIT header additionally 3809 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if 3810 * straps are not being used for the panel, this specifies the frequency 3811 * at which modes should be set up in the dual link style. 3812 * 3813 * Following the header, the BMP (ver 0xa) table has several records, 3814 * indexed by a separate xlat table, indexed in turn by the fp strap in 3815 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script 3816 * numbers for use by INIT_SUB which controlled panel init and power, 3817 * and finally a dword of ms to sleep between power off and on 3818 * operations. 3819 * 3820 * In the BIT versions, the table following the header serves as an 3821 * integrated config and xlat table: the records in the table are 3822 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has 3823 * two bytes - the first as a config byte, the second for indexing the 3824 * fp mode table pointed to by the BIT 'D' table 3825 * 3826 * DDC is not used until after card init, so selecting the correct table 3827 * entry and setting the dual link flag for EDID equipped panels, 3828 * requiring tests against the native-mode pixel clock, cannot be done 3829 * until later, when this function should be called with non-zero pxclk 3830 */ 3831 struct drm_nouveau_private *dev_priv = dev->dev_private; 3832 struct nvbios *bios = &dev_priv->vbios; 3833 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0; 3834 struct lvdstableheader lth; 3835 uint16_t lvdsofs; 3836 int ret, chip_version = bios->chip_version; 3837 3838 ret = parse_lvds_manufacturer_table_header(dev, bios, <h); 3839 if (ret) 3840 return ret; 3841 3842 switch (lth.lvds_ver) { 3843 case 0x0a: /* pre NV40 */ 3844 lvdsmanufacturerindex = bios->data[ 3845 bios->fp.fpxlatemanufacturertableptr + 3846 fpstrapping]; 3847 3848 /* we're done if this isn't the EDID panel case */ 3849 if (!pxclk) 3850 break; 3851 3852 if (chip_version < 0x25) { 3853 /* nv17 behaviour 3854 * 3855 * It seems the old style lvds script pointer is reused 3856 * to select 18/24 bit colour depth for EDID panels. 3857 */ 3858 lvdsmanufacturerindex = 3859 (bios->legacy.lvds_single_a_script_ptr & 1) ? 3860 2 : 0; 3861 if (pxclk >= bios->fp.duallink_transition_clk) 3862 lvdsmanufacturerindex++; 3863 } else if (chip_version < 0x30) { 3864 /* nv28 behaviour (off-chip encoder) 3865 * 3866 * nv28 does a complex dance of first using byte 121 of 3867 * the EDID to choose the lvdsmanufacturerindex, then 3868 * later attempting to match the EDID manufacturer and 3869 * product IDs in a table (signature 'pidt' (panel id 3870 * table?)), setting an lvdsmanufacturerindex of 0 and 3871 * an fp strap of the match index (or 0xf if none) 3872 */ 3873 lvdsmanufacturerindex = 0; 3874 } else { 3875 /* nv31, nv34 behaviour */ 3876 lvdsmanufacturerindex = 0; 3877 if (pxclk >= bios->fp.duallink_transition_clk) 3878 lvdsmanufacturerindex = 2; 3879 if (pxclk >= 140000) 3880 lvdsmanufacturerindex = 3; 3881 } 3882 3883 /* 3884 * nvidia set the high nibble of (cr57=f, cr58) to 3885 * lvdsmanufacturerindex in this case; we don't 3886 */ 3887 break; 3888 case 0x30: /* NV4x */ 3889 case 0x40: /* G80/G90 */ 3890 lvdsmanufacturerindex = fpstrapping; 3891 break; 3892 default: 3893 NV_ERROR(dev, "LVDS table revision not currently supported\n"); 3894 return -ENOSYS; 3895 } 3896 3897 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex; 3898 switch (lth.lvds_ver) { 3899 case 0x0a: 3900 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1; 3901 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2; 3902 bios->fp.dual_link = bios->data[lvdsofs] & 4; 3903 bios->fp.link_c_increment = bios->data[lvdsofs] & 8; 3904 *if_is_24bit = bios->data[lvdsofs] & 16; 3905 break; 3906 case 0x30: 3907 case 0x40: 3908 /* 3909 * No sign of the "power off for reset" or "reset for panel 3910 * on" bits, but it's safer to assume we should 3911 */ 3912 bios->fp.power_off_for_reset = true; 3913 bios->fp.reset_after_pclk_change = true; 3914 3915 /* 3916 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is 3917 * over-written, and if_is_24bit isn't used 3918 */ 3919 bios->fp.dual_link = bios->data[lvdsofs] & 1; 3920 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2; 3921 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4]; 3922 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10; 3923 break; 3924 } 3925 3926 /* Dell Latitude D620 reports a too-high value for the dual-link 3927 * transition freq, causing us to program the panel incorrectly. 3928 * 3929 * It doesn't appear the VBIOS actually uses its transition freq 3930 * (90000kHz), instead it uses the "Number of LVDS channels" field 3931 * out of the panel ID structure (http://www.spwg.org/). 3932 * 3933 * For the moment, a quirk will do :) 3934 */ 3935 if ((dev->pdev->device == 0x01d7) && 3936 (dev->pdev->subsystem_vendor == 0x1028) && 3937 (dev->pdev->subsystem_device == 0x01c2)) { 3938 bios->fp.duallink_transition_clk = 80000; 3939 } 3940 3941 /* set dual_link flag for EDID case */ 3942 if (pxclk && (chip_version < 0x25 || chip_version > 0x28)) 3943 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk); 3944 3945 *dl = bios->fp.dual_link; 3946 3947 return 0; 3948} 3949 3950static uint8_t * 3951bios_output_config_match(struct drm_device *dev, struct dcb_entry *dcbent, 3952 uint16_t record, int record_len, int record_nr, 3953 bool match_link) 3954{ 3955 struct drm_nouveau_private *dev_priv = dev->dev_private; 3956 struct nvbios *bios = &dev_priv->vbios; 3957 uint32_t entry; 3958 uint16_t table; 3959 int i, v; 3960 3961 switch (dcbent->type) { 3962 case OUTPUT_TMDS: 3963 case OUTPUT_LVDS: 3964 case OUTPUT_DP: 3965 break; 3966 default: 3967 match_link = false; 3968 break; 3969 } 3970 3971 for (i = 0; i < record_nr; i++, record += record_len) { 3972 table = ROM16(bios->data[record]); 3973 if (!table) 3974 continue; 3975 entry = ROM32(bios->data[table]); 3976 3977 if (match_link) { 3978 v = (entry & 0x00c00000) >> 22; 3979 if (!(v & dcbent->sorconf.link)) 3980 continue; 3981 } 3982 3983 v = (entry & 0x000f0000) >> 16; 3984 if (!(v & dcbent->or)) 3985 continue; 3986 3987 v = (entry & 0x000000f0) >> 4; 3988 if (v != dcbent->location) 3989 continue; 3990 3991 v = (entry & 0x0000000f); 3992 if (v != dcbent->type) 3993 continue; 3994 3995 return &bios->data[table]; 3996 } 3997 3998 return NULL; 3999} 4000 4001void * 4002nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent, 4003 int *length) 4004{ 4005 struct drm_nouveau_private *dev_priv = dev->dev_private; 4006 struct nvbios *bios = &dev_priv->vbios; 4007 uint8_t *table; 4008 4009 if (!bios->display.dp_table_ptr) { 4010 NV_ERROR(dev, "No pointer to DisplayPort table\n"); 4011 return NULL; 4012 } 4013 table = &bios->data[bios->display.dp_table_ptr]; 4014 4015 if (table[0] != 0x20 && table[0] != 0x21) { 4016 NV_ERROR(dev, "DisplayPort table version 0x%02x unknown\n", 4017 table[0]); 4018 return NULL; 4019 } 4020 4021 *length = table[4]; 4022 return bios_output_config_match(dev, dcbent, 4023 bios->display.dp_table_ptr + table[1], 4024 table[2], table[3], table[0] >= 0x21); 4025} 4026 4027int 4028nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent, 4029 uint32_t sub, int pxclk) 4030{ 4031 /* 4032 * The display script table is located by the BIT 'U' table. 4033 * 4034 * It contains an array of pointers to various tables describing 4035 * a particular output type. The first 32-bits of the output 4036 * tables contains similar information to a DCB entry, and is 4037 * used to decide whether that particular table is suitable for 4038 * the output you want to access. 4039 * 4040 * The "record header length" field here seems to indicate the 4041 * offset of the first configuration entry in the output tables. 4042 * This is 10 on most cards I've seen, but 12 has been witnessed 4043 * on DP cards, and there's another script pointer within the 4044 * header. 4045 * 4046 * offset + 0 ( 8 bits): version 4047 * offset + 1 ( 8 bits): header length 4048 * offset + 2 ( 8 bits): record length 4049 * offset + 3 ( 8 bits): number of records 4050 * offset + 4 ( 8 bits): record header length 4051 * offset + 5 (16 bits): pointer to first output script table 4052 */ 4053 4054 struct drm_nouveau_private *dev_priv = dev->dev_private; 4055 struct nvbios *bios = &dev_priv->vbios; 4056 uint8_t *table = &bios->data[bios->display.script_table_ptr]; 4057 uint8_t *otable = NULL; 4058 uint16_t script; 4059 int i = 0; 4060 4061 if (!bios->display.script_table_ptr) { 4062 NV_ERROR(dev, "No pointer to output script table\n"); 4063 return 1; 4064 } 4065 4066 /* 4067 * Nothing useful has been in any of the pre-2.0 tables I've seen, 4068 * so until they are, we really don't need to care. 4069 */ 4070 if (table[0] < 0x20) 4071 return 1; 4072 4073 if (table[0] != 0x20 && table[0] != 0x21) { 4074 NV_ERROR(dev, "Output script table version 0x%02x unknown\n", 4075 table[0]); 4076 return 1; 4077 } 4078 4079 /* 4080 * The output script tables describing a particular output type 4081 * look as follows: 4082 * 4083 * offset + 0 (32 bits): output this table matches (hash of DCB) 4084 * offset + 4 ( 8 bits): unknown 4085 * offset + 5 ( 8 bits): number of configurations 4086 * offset + 6 (16 bits): pointer to some script 4087 * offset + 8 (16 bits): pointer to some script 4088 * 4089 * headerlen == 10 4090 * offset + 10 : configuration 0 4091 * 4092 * headerlen == 12 4093 * offset + 10 : pointer to some script 4094 * offset + 12 : configuration 0 4095 * 4096 * Each config entry is as follows: 4097 * 4098 * offset + 0 (16 bits): unknown, assumed to be a match value 4099 * offset + 2 (16 bits): pointer to script table (clock set?) 4100 * offset + 4 (16 bits): pointer to script table (reset?) 4101 * 4102 * There doesn't appear to be a count value to say how many 4103 * entries exist in each script table, instead, a 0 value in 4104 * the first 16-bit word seems to indicate both the end of the 4105 * list and the default entry. The second 16-bit word in the 4106 * script tables is a pointer to the script to execute. 4107 */ 4108 4109 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n", 4110 dcbent->type, dcbent->location, dcbent->or); 4111 otable = bios_output_config_match(dev, dcbent, table[1] + 4112 bios->display.script_table_ptr, 4113 table[2], table[3], table[0] >= 0x21); 4114 if (!otable) { 4115 NV_ERROR(dev, "Couldn't find matching output script table\n"); 4116 return 1; 4117 } 4118 4119 if (pxclk < -2 || pxclk > 0) { 4120 /* Try to find matching script table entry */ 4121 for (i = 0; i < otable[5]; i++) { 4122 if (ROM16(otable[table[4] + i*6]) == sub) 4123 break; 4124 } 4125 4126 if (i == otable[5]) { 4127 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, " 4128 "using first\n", 4129 sub, dcbent->type, dcbent->or); 4130 i = 0; 4131 } 4132 } 4133 4134 if (pxclk == 0) { 4135 script = ROM16(otable[6]); 4136 if (!script) { 4137 NV_DEBUG_KMS(dev, "output script 0 not found\n"); 4138 return 1; 4139 } 4140 4141 NV_TRACE(dev, "0x%04X: parsing output script 0\n", script); 4142 nouveau_bios_run_init_table(dev, script, dcbent); 4143 } else 4144 if (pxclk == -1) { 4145 script = ROM16(otable[8]); 4146 if (!script) { 4147 NV_DEBUG_KMS(dev, "output script 1 not found\n"); 4148 return 1; 4149 } 4150 4151 NV_TRACE(dev, "0x%04X: parsing output script 1\n", script); 4152 nouveau_bios_run_init_table(dev, script, dcbent); 4153 } else 4154 if (pxclk == -2) { 4155 if (table[4] >= 12) 4156 script = ROM16(otable[10]); 4157 else 4158 script = 0; 4159 if (!script) { 4160 NV_DEBUG_KMS(dev, "output script 2 not found\n"); 4161 return 1; 4162 } 4163 4164 NV_TRACE(dev, "0x%04X: parsing output script 2\n", script); 4165 nouveau_bios_run_init_table(dev, script, dcbent); 4166 } else 4167 if (pxclk > 0) { 4168 script = ROM16(otable[table[4] + i*6 + 2]); 4169 if (script) 4170 script = clkcmptable(bios, script, pxclk); 4171 if (!script) { 4172 NV_ERROR(dev, "clock script 0 not found\n"); 4173 return 1; 4174 } 4175 4176 NV_TRACE(dev, "0x%04X: parsing clock script 0\n", script); 4177 nouveau_bios_run_init_table(dev, script, dcbent); 4178 } else 4179 if (pxclk < 0) { 4180 script = ROM16(otable[table[4] + i*6 + 4]); 4181 if (script) 4182 script = clkcmptable(bios, script, -pxclk); 4183 if (!script) { 4184 NV_DEBUG_KMS(dev, "clock script 1 not found\n"); 4185 return 1; 4186 } 4187 4188 NV_TRACE(dev, "0x%04X: parsing clock script 1\n", script); 4189 nouveau_bios_run_init_table(dev, script, dcbent); 4190 } 4191 4192 return 0; 4193} 4194 4195 4196int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk) 4197{ 4198 /* 4199 * the pxclk parameter is in kHz 4200 * 4201 * This runs the TMDS regs setting code found on BIT bios cards 4202 * 4203 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and 4204 * ffs(or) == 3, use the second. 4205 */ 4206 4207 struct drm_nouveau_private *dev_priv = dev->dev_private; 4208 struct nvbios *bios = &dev_priv->vbios; 4209 int cv = bios->chip_version; 4210 uint16_t clktable = 0, scriptptr; 4211 uint32_t sel_clk_binding, sel_clk; 4212 4213 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */ 4214 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 && 4215 dcbent->location != DCB_LOC_ON_CHIP) 4216 return 0; 4217 4218 switch (ffs(dcbent->or)) { 4219 case 1: 4220 clktable = bios->tmds.output0_script_ptr; 4221 break; 4222 case 2: 4223 case 3: 4224 clktable = bios->tmds.output1_script_ptr; 4225 break; 4226 } 4227 4228 if (!clktable) { 4229 NV_ERROR(dev, "Pixel clock comparison table not found\n"); 4230 return -EINVAL; 4231 } 4232 4233 scriptptr = clkcmptable(bios, clktable, pxclk); 4234 4235 if (!scriptptr) { 4236 NV_ERROR(dev, "TMDS output init script not found\n"); 4237 return -ENOENT; 4238 } 4239 4240 /* don't let script change pll->head binding */ 4241 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000; 4242 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000); 4243 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; 4244 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); 4245 4246 return 0; 4247} 4248 4249int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim) 4250{ 4251 /* 4252 * PLL limits table 4253 * 4254 * Version 0x10: NV30, NV31 4255 * One byte header (version), one record of 24 bytes 4256 * Version 0x11: NV36 - Not implemented 4257 * Seems to have same record style as 0x10, but 3 records rather than 1 4258 * Version 0x20: Found on Geforce 6 cards 4259 * Trivial 4 byte BIT header. 31 (0x1f) byte record length 4260 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards 4261 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record 4262 * length in general, some (integrated) have an extra configuration byte 4263 * Version 0x30: Found on Geforce 8, separates the register mapping 4264 * from the limits tables. 4265 */ 4266 4267 struct drm_nouveau_private *dev_priv = dev->dev_private; 4268 struct nvbios *bios = &dev_priv->vbios; 4269 int cv = bios->chip_version, pllindex = 0; 4270 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0; 4271 uint32_t crystal_strap_mask, crystal_straps; 4272 4273 if (!bios->pll_limit_tbl_ptr) { 4274 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 || 4275 cv >= 0x40) { 4276 NV_ERROR(dev, "Pointer to PLL limits table invalid\n"); 4277 return -EINVAL; 4278 } 4279 } else 4280 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr]; 4281 4282 crystal_strap_mask = 1 << 6; 4283 /* open coded dev->twoHeads test */ 4284 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20) 4285 crystal_strap_mask |= 1 << 22; 4286 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) & 4287 crystal_strap_mask; 4288 4289 switch (pll_lim_ver) { 4290 /* 4291 * We use version 0 to indicate a pre limit table bios (single stage 4292 * pll) and load the hard coded limits instead. 4293 */ 4294 case 0: 4295 break; 4296 case 0x10: 4297 case 0x11: 4298 /* 4299 * Strictly v0x11 has 3 entries, but the last two don't seem 4300 * to get used. 4301 */ 4302 headerlen = 1; 4303 recordlen = 0x18; 4304 entries = 1; 4305 pllindex = 0; 4306 break; 4307 case 0x20: 4308 case 0x21: 4309 case 0x30: 4310 case 0x40: 4311 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1]; 4312 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2]; 4313 entries = bios->data[bios->pll_limit_tbl_ptr + 3]; 4314 break; 4315 default: 4316 NV_ERROR(dev, "PLL limits table revision 0x%X not currently " 4317 "supported\n", pll_lim_ver); 4318 return -ENOSYS; 4319 } 4320 4321 /* initialize all members to zero */ 4322 memset(pll_lim, 0, sizeof(struct pll_lims)); 4323 4324 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) { 4325 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex]; 4326 4327 pll_lim->vco1.minfreq = ROM32(pll_rec[0]); 4328 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]); 4329 pll_lim->vco2.minfreq = ROM32(pll_rec[8]); 4330 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]); 4331 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]); 4332 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]); 4333 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX; 4334 4335 /* these values taken from nv30/31/36 */ 4336 pll_lim->vco1.min_n = 0x1; 4337 if (cv == 0x36) 4338 pll_lim->vco1.min_n = 0x5; 4339 pll_lim->vco1.max_n = 0xff; 4340 pll_lim->vco1.min_m = 0x1; 4341 pll_lim->vco1.max_m = 0xd; 4342 pll_lim->vco2.min_n = 0x4; 4343 /* 4344 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this 4345 * table version (apart from nv35)), N2 is compared to 4346 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and 4347 * save a comparison 4348 */ 4349 pll_lim->vco2.max_n = 0x28; 4350 if (cv == 0x30 || cv == 0x35) 4351 /* only 5 bits available for N2 on nv30/35 */ 4352 pll_lim->vco2.max_n = 0x1f; 4353 pll_lim->vco2.min_m = 0x1; 4354 pll_lim->vco2.max_m = 0x4; 4355 pll_lim->max_log2p = 0x7; 4356 pll_lim->max_usable_log2p = 0x6; 4357 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) { 4358 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen; 4359 uint32_t reg = 0; /* default match */ 4360 uint8_t *pll_rec; 4361 int i; 4362 4363 /* 4364 * First entry is default match, if nothing better. warn if 4365 * reg field nonzero 4366 */ 4367 if (ROM32(bios->data[plloffs])) 4368 NV_WARN(dev, "Default PLL limit entry has non-zero " 4369 "register field\n"); 4370 4371 if (limit_match > MAX_PLL_TYPES) 4372 /* we've been passed a reg as the match */ 4373 reg = limit_match; 4374 else /* limit match is a pll type */ 4375 for (i = 1; i < entries && !reg; i++) { 4376 uint32_t cmpreg = ROM32(bios->data[plloffs + recordlen * i]); 4377 4378 if (limit_match == NVPLL && 4379 (cmpreg == NV_PRAMDAC_NVPLL_COEFF || cmpreg == 0x4000)) 4380 reg = cmpreg; 4381 if (limit_match == MPLL && 4382 (cmpreg == NV_PRAMDAC_MPLL_COEFF || cmpreg == 0x4020)) 4383 reg = cmpreg; 4384 if (limit_match == VPLL1 && 4385 (cmpreg == NV_PRAMDAC_VPLL_COEFF || cmpreg == 0x4010)) 4386 reg = cmpreg; 4387 if (limit_match == VPLL2 && 4388 (cmpreg == NV_RAMDAC_VPLL2 || cmpreg == 0x4018)) 4389 reg = cmpreg; 4390 } 4391 4392 for (i = 1; i < entries; i++) 4393 if (ROM32(bios->data[plloffs + recordlen * i]) == reg) { 4394 pllindex = i; 4395 break; 4396 } 4397 4398 pll_rec = &bios->data[plloffs + recordlen * pllindex]; 4399 4400 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n", 4401 pllindex ? reg : 0); 4402 4403 /* 4404 * Frequencies are stored in tables in MHz, kHz are more 4405 * useful, so we convert. 4406 */ 4407 4408 /* What output frequencies can each VCO generate? */ 4409 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000; 4410 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000; 4411 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000; 4412 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000; 4413 4414 /* What input frequencies they accept (past the m-divider)? */ 4415 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000; 4416 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000; 4417 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000; 4418 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000; 4419 4420 /* What values are accepted as multiplier and divider? */ 4421 pll_lim->vco1.min_n = pll_rec[20]; 4422 pll_lim->vco1.max_n = pll_rec[21]; 4423 pll_lim->vco1.min_m = pll_rec[22]; 4424 pll_lim->vco1.max_m = pll_rec[23]; 4425 pll_lim->vco2.min_n = pll_rec[24]; 4426 pll_lim->vco2.max_n = pll_rec[25]; 4427 pll_lim->vco2.min_m = pll_rec[26]; 4428 pll_lim->vco2.max_m = pll_rec[27]; 4429 4430 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29]; 4431 if (pll_lim->max_log2p > 0x7) 4432 /* pll decoding in nv_hw.c assumes never > 7 */ 4433 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n", 4434 pll_lim->max_log2p); 4435 if (cv < 0x60) 4436 pll_lim->max_usable_log2p = 0x6; 4437 pll_lim->log2p_bias = pll_rec[30]; 4438 4439 if (recordlen > 0x22) 4440 pll_lim->refclk = ROM32(pll_rec[31]); 4441 4442 if (recordlen > 0x23 && pll_rec[35]) 4443 NV_WARN(dev, 4444 "Bits set in PLL configuration byte (%x)\n", 4445 pll_rec[35]); 4446 4447 /* C51 special not seen elsewhere */ 4448 if (cv == 0x51 && !pll_lim->refclk) { 4449 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK); 4450 4451 if (((limit_match == NV_PRAMDAC_VPLL_COEFF || limit_match == VPLL1) && sel_clk & 0x20) || 4452 ((limit_match == NV_RAMDAC_VPLL2 || limit_match == VPLL2) && sel_clk & 0x80)) { 4453 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3) 4454 pll_lim->refclk = 200000; 4455 else 4456 pll_lim->refclk = 25000; 4457 } 4458 } 4459 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */ 4460 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen]; 4461 uint8_t *record = NULL; 4462 int i; 4463 4464 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n", 4465 limit_match); 4466 4467 for (i = 0; i < entries; i++, entry += recordlen) { 4468 if (ROM32(entry[3]) == limit_match) { 4469 record = &bios->data[ROM16(entry[1])]; 4470 break; 4471 } 4472 } 4473 4474 if (!record) { 4475 NV_ERROR(dev, "Register 0x%08x not found in PLL " 4476 "limits table", limit_match); 4477 return -ENOENT; 4478 } 4479 4480 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000; 4481 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000; 4482 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000; 4483 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000; 4484 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000; 4485 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000; 4486 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000; 4487 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000; 4488 pll_lim->vco1.min_n = record[16]; 4489 pll_lim->vco1.max_n = record[17]; 4490 pll_lim->vco1.min_m = record[18]; 4491 pll_lim->vco1.max_m = record[19]; 4492 pll_lim->vco2.min_n = record[20]; 4493 pll_lim->vco2.max_n = record[21]; 4494 pll_lim->vco2.min_m = record[22]; 4495 pll_lim->vco2.max_m = record[23]; 4496 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25]; 4497 pll_lim->log2p_bias = record[27]; 4498 pll_lim->refclk = ROM32(record[28]); 4499 } else if (pll_lim_ver) { /* ver 0x40 */ 4500 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen]; 4501 uint8_t *record = NULL; 4502 int i; 4503 4504 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n", 4505 limit_match); 4506 4507 for (i = 0; i < entries; i++, entry += recordlen) { 4508 if (ROM32(entry[3]) == limit_match) { 4509 record = &bios->data[ROM16(entry[1])]; 4510 break; 4511 } 4512 } 4513 4514 if (!record) { 4515 NV_ERROR(dev, "Register 0x%08x not found in PLL " 4516 "limits table", limit_match); 4517 return -ENOENT; 4518 } 4519 4520 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000; 4521 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000; 4522 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000; 4523 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000; 4524 pll_lim->vco1.min_m = record[8]; 4525 pll_lim->vco1.max_m = record[9]; 4526 pll_lim->vco1.min_n = record[10]; 4527 pll_lim->vco1.max_n = record[11]; 4528 pll_lim->min_p = record[12]; 4529 pll_lim->max_p = record[13]; 4530 /* where did this go to?? */ 4531 if (limit_match == 0x00614100 || limit_match == 0x00614900) 4532 pll_lim->refclk = 27000; 4533 else 4534 pll_lim->refclk = 100000; 4535 } 4536 4537 /* 4538 * By now any valid limit table ought to have set a max frequency for 4539 * vco1, so if it's zero it's either a pre limit table bios, or one 4540 * with an empty limit table (seen on nv18) 4541 */ 4542 if (!pll_lim->vco1.maxfreq) { 4543 pll_lim->vco1.minfreq = bios->fminvco; 4544 pll_lim->vco1.maxfreq = bios->fmaxvco; 4545 pll_lim->vco1.min_inputfreq = 0; 4546 pll_lim->vco1.max_inputfreq = INT_MAX; 4547 pll_lim->vco1.min_n = 0x1; 4548 pll_lim->vco1.max_n = 0xff; 4549 pll_lim->vco1.min_m = 0x1; 4550 if (crystal_straps == 0) { 4551 /* nv05 does this, nv11 doesn't, nv10 unknown */ 4552 if (cv < 0x11) 4553 pll_lim->vco1.min_m = 0x7; 4554 pll_lim->vco1.max_m = 0xd; 4555 } else { 4556 if (cv < 0x11) 4557 pll_lim->vco1.min_m = 0x8; 4558 pll_lim->vco1.max_m = 0xe; 4559 } 4560 if (cv < 0x17 || cv == 0x1a || cv == 0x20) 4561 pll_lim->max_log2p = 4; 4562 else 4563 pll_lim->max_log2p = 5; 4564 pll_lim->max_usable_log2p = pll_lim->max_log2p; 4565 } 4566 4567 if (!pll_lim->refclk) 4568 switch (crystal_straps) { 4569 case 0: 4570 pll_lim->refclk = 13500; 4571 break; 4572 case (1 << 6): 4573 pll_lim->refclk = 14318; 4574 break; 4575 case (1 << 22): 4576 pll_lim->refclk = 27000; 4577 break; 4578 case (1 << 22 | 1 << 6): 4579 pll_lim->refclk = 25000; 4580 break; 4581 } 4582 4583 NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq); 4584 NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq); 4585 NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq); 4586 NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq); 4587 NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n); 4588 NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n); 4589 NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m); 4590 NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m); 4591 if (pll_lim->vco2.maxfreq) { 4592 NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq); 4593 NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq); 4594 NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq); 4595 NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq); 4596 NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n); 4597 NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n); 4598 NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m); 4599 NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m); 4600 } 4601 if (!pll_lim->max_p) { 4602 NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p); 4603 NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias); 4604 } else { 4605 NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p); 4606 NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p); 4607 } 4608 NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk); 4609 4610 return 0; 4611} 4612 4613static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset) 4614{ 4615 /* 4616 * offset + 0 (8 bits): Micro version 4617 * offset + 1 (8 bits): Minor version 4618 * offset + 2 (8 bits): Chip version 4619 * offset + 3 (8 bits): Major version 4620 */ 4621 4622 bios->major_version = bios->data[offset + 3]; 4623 bios->chip_version = bios->data[offset + 2]; 4624 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n", 4625 bios->data[offset + 3], bios->data[offset + 2], 4626 bios->data[offset + 1], bios->data[offset]); 4627} 4628 4629static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset) 4630{ 4631 /* 4632 * Parses the init table segment for pointers used in script execution. 4633 * 4634 * offset + 0 (16 bits): init script tables pointer 4635 * offset + 2 (16 bits): macro index table pointer 4636 * offset + 4 (16 bits): macro table pointer 4637 * offset + 6 (16 bits): condition table pointer 4638 * offset + 8 (16 bits): io condition table pointer 4639 * offset + 10 (16 bits): io flag condition table pointer 4640 * offset + 12 (16 bits): init function table pointer 4641 */ 4642 4643 bios->init_script_tbls_ptr = ROM16(bios->data[offset]); 4644 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]); 4645 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]); 4646 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]); 4647 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]); 4648 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]); 4649 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]); 4650} 4651 4652static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4653{ 4654 /* 4655 * Parses the load detect values for g80 cards. 4656 * 4657 * offset + 0 (16 bits): loadval table pointer 4658 */ 4659 4660 uint16_t load_table_ptr; 4661 uint8_t version, headerlen, entrylen, num_entries; 4662 4663 if (bitentry->length != 3) { 4664 NV_ERROR(dev, "Do not understand BIT A table\n"); 4665 return -EINVAL; 4666 } 4667 4668 load_table_ptr = ROM16(bios->data[bitentry->offset]); 4669 4670 if (load_table_ptr == 0x0) { 4671 NV_ERROR(dev, "Pointer to BIT loadval table invalid\n"); 4672 return -EINVAL; 4673 } 4674 4675 version = bios->data[load_table_ptr]; 4676 4677 if (version != 0x10) { 4678 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n", 4679 version >> 4, version & 0xF); 4680 return -ENOSYS; 4681 } 4682 4683 headerlen = bios->data[load_table_ptr + 1]; 4684 entrylen = bios->data[load_table_ptr + 2]; 4685 num_entries = bios->data[load_table_ptr + 3]; 4686 4687 if (headerlen != 4 || entrylen != 4 || num_entries != 2) { 4688 NV_ERROR(dev, "Do not understand BIT loadval table\n"); 4689 return -EINVAL; 4690 } 4691 4692 /* First entry is normal dac, 2nd tv-out perhaps? */ 4693 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff; 4694 4695 return 0; 4696} 4697 4698static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4699{ 4700 /* 4701 * offset + 8 (16 bits): PLL limits table pointer 4702 * 4703 * There's more in here, but that's unknown. 4704 */ 4705 4706 if (bitentry->length < 10) { 4707 NV_ERROR(dev, "Do not understand BIT C table\n"); 4708 return -EINVAL; 4709 } 4710 4711 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]); 4712 4713 return 0; 4714} 4715 4716static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4717{ 4718 /* 4719 * Parses the flat panel table segment that the bit entry points to. 4720 * Starting at bitentry->offset: 4721 * 4722 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte 4723 * records beginning with a freq. 4724 * offset + 2 (16 bits): mode table pointer 4725 */ 4726 4727 if (bitentry->length != 4) { 4728 NV_ERROR(dev, "Do not understand BIT display table\n"); 4729 return -EINVAL; 4730 } 4731 4732 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]); 4733 4734 return 0; 4735} 4736 4737static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4738{ 4739 /* 4740 * Parses the init table segment that the bit entry points to. 4741 * 4742 * See parse_script_table_pointers for layout 4743 */ 4744 4745 if (bitentry->length < 14) { 4746 NV_ERROR(dev, "Do not understand init table\n"); 4747 return -EINVAL; 4748 } 4749 4750 parse_script_table_pointers(bios, bitentry->offset); 4751 4752 if (bitentry->length >= 16) 4753 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]); 4754 if (bitentry->length >= 18) 4755 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]); 4756 4757 return 0; 4758} 4759 4760static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4761{ 4762 /* 4763 * BIT 'i' (info?) table 4764 * 4765 * offset + 0 (32 bits): BIOS version dword (as in B table) 4766 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?) 4767 * offset + 13 (16 bits): pointer to table containing DAC load 4768 * detection comparison values 4769 * 4770 * There's other things in the table, purpose unknown 4771 */ 4772 4773 uint16_t daccmpoffset; 4774 uint8_t dacver, dacheaderlen; 4775 4776 if (bitentry->length < 6) { 4777 NV_ERROR(dev, "BIT i table too short for needed information\n"); 4778 return -EINVAL; 4779 } 4780 4781 parse_bios_version(dev, bios, bitentry->offset); 4782 4783 /* 4784 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's 4785 * Quadro identity crisis), other bits possibly as for BMP feature byte 4786 */ 4787 bios->feature_byte = bios->data[bitentry->offset + 5]; 4788 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE; 4789 4790 if (bitentry->length < 15) { 4791 NV_WARN(dev, "BIT i table not long enough for DAC load " 4792 "detection comparison table\n"); 4793 return -EINVAL; 4794 } 4795 4796 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]); 4797 4798 /* doesn't exist on g80 */ 4799 if (!daccmpoffset) 4800 return 0; 4801 4802 /* 4803 * The first value in the table, following the header, is the 4804 * comparison value, the second entry is a comparison value for 4805 * TV load detection. 4806 */ 4807 4808 dacver = bios->data[daccmpoffset]; 4809 dacheaderlen = bios->data[daccmpoffset + 1]; 4810 4811 if (dacver != 0x00 && dacver != 0x10) { 4812 NV_WARN(dev, "DAC load detection comparison table version " 4813 "%d.%d not known\n", dacver >> 4, dacver & 0xf); 4814 return -ENOSYS; 4815 } 4816 4817 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]); 4818 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]); 4819 4820 return 0; 4821} 4822 4823static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4824{ 4825 /* 4826 * Parses the LVDS table segment that the bit entry points to. 4827 * Starting at bitentry->offset: 4828 * 4829 * offset + 0 (16 bits): LVDS strap xlate table pointer 4830 */ 4831 4832 if (bitentry->length != 2) { 4833 NV_ERROR(dev, "Do not understand BIT LVDS table\n"); 4834 return -EINVAL; 4835 } 4836 4837 /* 4838 * No idea if it's still called the LVDS manufacturer table, but 4839 * the concept's close enough. 4840 */ 4841 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]); 4842 4843 return 0; 4844} 4845 4846static int 4847parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios, 4848 struct bit_entry *bitentry) 4849{ 4850 /* 4851 * offset + 2 (8 bits): number of options in an 4852 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set 4853 * offset + 3 (16 bits): pointer to strap xlate table for RAM 4854 * restrict option selection 4855 * 4856 * There's a bunch of bits in this table other than the RAM restrict 4857 * stuff that we don't use - their use currently unknown 4858 */ 4859 4860 /* 4861 * Older bios versions don't have a sufficiently long table for 4862 * what we want 4863 */ 4864 if (bitentry->length < 0x5) 4865 return 0; 4866 4867 if (bitentry->id[1] < 2) { 4868 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2]; 4869 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]); 4870 } else { 4871 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0]; 4872 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]); 4873 } 4874 4875 return 0; 4876} 4877 4878static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4879{ 4880 /* 4881 * Parses the pointer to the TMDS table 4882 * 4883 * Starting at bitentry->offset: 4884 * 4885 * offset + 0 (16 bits): TMDS table pointer 4886 * 4887 * The TMDS table is typically found just before the DCB table, with a 4888 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being 4889 * length?) 4890 * 4891 * At offset +7 is a pointer to a script, which I don't know how to 4892 * run yet. 4893 * At offset +9 is a pointer to another script, likewise 4894 * Offset +11 has a pointer to a table where the first word is a pxclk 4895 * frequency and the second word a pointer to a script, which should be 4896 * run if the comparison pxclk frequency is less than the pxclk desired. 4897 * This repeats for decreasing comparison frequencies 4898 * Offset +13 has a pointer to a similar table 4899 * The selection of table (and possibly +7/+9 script) is dictated by 4900 * "or" from the DCB. 4901 */ 4902 4903 uint16_t tmdstableptr, script1, script2; 4904 4905 if (bitentry->length != 2) { 4906 NV_ERROR(dev, "Do not understand BIT TMDS table\n"); 4907 return -EINVAL; 4908 } 4909 4910 tmdstableptr = ROM16(bios->data[bitentry->offset]); 4911 4912 if (tmdstableptr == 0x0) { 4913 NV_ERROR(dev, "Pointer to TMDS table invalid\n"); 4914 return -EINVAL; 4915 } 4916 4917 /* nv50+ has v2.0, but we don't parse it atm */ 4918 if (bios->data[tmdstableptr] != 0x11) { 4919 NV_WARN(dev, 4920 "TMDS table revision %d.%d not currently supported\n", 4921 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf); 4922 return -ENOSYS; 4923 } 4924 4925 /* 4926 * These two scripts are odd: they don't seem to get run even when 4927 * they are not stubbed. 4928 */ 4929 script1 = ROM16(bios->data[tmdstableptr + 7]); 4930 script2 = ROM16(bios->data[tmdstableptr + 9]); 4931 if (bios->data[script1] != 'q' || bios->data[script2] != 'q') 4932 NV_WARN(dev, "TMDS table script pointers not stubbed\n"); 4933 4934 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]); 4935 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]); 4936 4937 return 0; 4938} 4939 4940static int 4941parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios, 4942 struct bit_entry *bitentry) 4943{ 4944 /* 4945 * Parses the pointer to the G80 output script tables 4946 * 4947 * Starting at bitentry->offset: 4948 * 4949 * offset + 0 (16 bits): output script table pointer 4950 */ 4951 4952 uint16_t outputscripttableptr; 4953 4954 if (bitentry->length != 3) { 4955 NV_ERROR(dev, "Do not understand BIT U table\n"); 4956 return -EINVAL; 4957 } 4958 4959 outputscripttableptr = ROM16(bios->data[bitentry->offset]); 4960 bios->display.script_table_ptr = outputscripttableptr; 4961 return 0; 4962} 4963 4964static int 4965parse_bit_displayport_tbl_entry(struct drm_device *dev, struct nvbios *bios, 4966 struct bit_entry *bitentry) 4967{ 4968 bios->display.dp_table_ptr = ROM16(bios->data[bitentry->offset]); 4969 return 0; 4970} 4971 4972struct bit_table { 4973 const char id; 4974 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *); 4975}; 4976 4977#define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry }) 4978 4979static int 4980parse_bit_table(struct nvbios *bios, const uint16_t bitoffset, 4981 struct bit_table *table) 4982{ 4983 struct drm_device *dev = bios->dev; 4984 uint8_t maxentries = bios->data[bitoffset + 4]; 4985 int i, offset; 4986 struct bit_entry bitentry; 4987 4988 for (i = 0, offset = bitoffset + 6; i < maxentries; i++, offset += 6) { 4989 bitentry.id[0] = bios->data[offset]; 4990 4991 if (bitentry.id[0] != table->id) 4992 continue; 4993 4994 bitentry.id[1] = bios->data[offset + 1]; 4995 bitentry.length = ROM16(bios->data[offset + 2]); 4996 bitentry.offset = ROM16(bios->data[offset + 4]); 4997 4998 return table->parse_fn(dev, bios, &bitentry); 4999 } 5000 5001 NV_INFO(dev, "BIT table '%c' not found\n", table->id); 5002 return -ENOSYS; 5003} 5004 5005static int 5006parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset) 5007{ 5008 int ret; 5009 5010 /* 5011 * The only restriction on parsing order currently is having 'i' first 5012 * for use of bios->*_version or bios->feature_byte while parsing; 5013 * functions shouldn't be actually *doing* anything apart from pulling 5014 * data from the image into the bios struct, thus no interdependencies 5015 */ 5016 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i)); 5017 if (ret) /* info? */ 5018 return ret; 5019 if (bios->major_version >= 0x60) /* g80+ */ 5020 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A)); 5021 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C)); 5022 if (ret) 5023 return ret; 5024 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display)); 5025 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init)); 5026 if (ret) 5027 return ret; 5028 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */ 5029 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds)); 5030 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds)); 5031 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U)); 5032 parse_bit_table(bios, bitoffset, &BIT_TABLE('d', displayport)); 5033 5034 return 0; 5035} 5036 5037static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset) 5038{ 5039 /* 5040 * Parses the BMP structure for useful things, but does not act on them 5041 * 5042 * offset + 5: BMP major version 5043 * offset + 6: BMP minor version 5044 * offset + 9: BMP feature byte 5045 * offset + 10: BCD encoded BIOS version 5046 * 5047 * offset + 18: init script table pointer (for bios versions < 5.10h) 5048 * offset + 20: extra init script table pointer (for bios 5049 * versions < 5.10h) 5050 * 5051 * offset + 24: memory init table pointer (used on early bios versions) 5052 * offset + 26: SDR memory sequencing setup data table 5053 * offset + 28: DDR memory sequencing setup data table 5054 * 5055 * offset + 54: index of I2C CRTC pair to use for CRT output 5056 * offset + 55: index of I2C CRTC pair to use for TV output 5057 * offset + 56: index of I2C CRTC pair to use for flat panel output 5058 * offset + 58: write CRTC index for I2C pair 0 5059 * offset + 59: read CRTC index for I2C pair 0 5060 * offset + 60: write CRTC index for I2C pair 1 5061 * offset + 61: read CRTC index for I2C pair 1 5062 * 5063 * offset + 67: maximum internal PLL frequency (single stage PLL) 5064 * offset + 71: minimum internal PLL frequency (single stage PLL) 5065 * 5066 * offset + 75: script table pointers, as described in 5067 * parse_script_table_pointers 5068 * 5069 * offset + 89: TMDS single link output A table pointer 5070 * offset + 91: TMDS single link output B table pointer 5071 * offset + 95: LVDS single link output A table pointer 5072 * offset + 105: flat panel timings table pointer 5073 * offset + 107: flat panel strapping translation table pointer 5074 * offset + 117: LVDS manufacturer panel config table pointer 5075 * offset + 119: LVDS manufacturer strapping translation table pointer 5076 * 5077 * offset + 142: PLL limits table pointer 5078 * 5079 * offset + 156: minimum pixel clock for LVDS dual link 5080 */ 5081 5082 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor; 5083 uint16_t bmplength; 5084 uint16_t legacy_scripts_offset, legacy_i2c_offset; 5085 5086 /* load needed defaults in case we can't parse this info */ 5087 bios->dcb.i2c[0].write = NV_CIO_CRE_DDC_WR__INDEX; 5088 bios->dcb.i2c[0].read = NV_CIO_CRE_DDC_STATUS__INDEX; 5089 bios->dcb.i2c[1].write = NV_CIO_CRE_DDC0_WR__INDEX; 5090 bios->dcb.i2c[1].read = NV_CIO_CRE_DDC0_STATUS__INDEX; 5091 bios->digital_min_front_porch = 0x4b; 5092 bios->fmaxvco = 256000; 5093 bios->fminvco = 128000; 5094 bios->fp.duallink_transition_clk = 90000; 5095 5096 bmp_version_major = bmp[5]; 5097 bmp_version_minor = bmp[6]; 5098 5099 NV_TRACE(dev, "BMP version %d.%d\n", 5100 bmp_version_major, bmp_version_minor); 5101 5102 /* 5103 * Make sure that 0x36 is blank and can't be mistaken for a DCB 5104 * pointer on early versions 5105 */ 5106 if (bmp_version_major < 5) 5107 *(uint16_t *)&bios->data[0x36] = 0; 5108 5109 /* 5110 * Seems that the minor version was 1 for all major versions prior 5111 * to 5. Version 6 could theoretically exist, but I suspect BIT 5112 * happened instead. 5113 */ 5114 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) { 5115 NV_ERROR(dev, "You have an unsupported BMP version. " 5116 "Please send in your bios\n"); 5117 return -ENOSYS; 5118 } 5119 5120 if (bmp_version_major == 0) 5121 /* nothing that's currently useful in this version */ 5122 return 0; 5123 else if (bmp_version_major == 1) 5124 bmplength = 44; /* exact for 1.01 */ 5125 else if (bmp_version_major == 2) 5126 bmplength = 48; /* exact for 2.01 */ 5127 else if (bmp_version_major == 3) 5128 bmplength = 54; 5129 /* guessed - mem init tables added in this version */ 5130 else if (bmp_version_major == 4 || bmp_version_minor < 0x1) 5131 /* don't know if 5.0 exists... */ 5132 bmplength = 62; 5133 /* guessed - BMP I2C indices added in version 4*/ 5134 else if (bmp_version_minor < 0x6) 5135 bmplength = 67; /* exact for 5.01 */ 5136 else if (bmp_version_minor < 0x10) 5137 bmplength = 75; /* exact for 5.06 */ 5138 else if (bmp_version_minor == 0x10) 5139 bmplength = 89; /* exact for 5.10h */ 5140 else if (bmp_version_minor < 0x14) 5141 bmplength = 118; /* exact for 5.11h */ 5142 else if (bmp_version_minor < 0x24) 5143 /* 5144 * Not sure of version where pll limits came in; 5145 * certainly exist by 0x24 though. 5146 */ 5147 /* length not exact: this is long enough to get lvds members */ 5148 bmplength = 123; 5149 else if (bmp_version_minor < 0x27) 5150 /* 5151 * Length not exact: this is long enough to get pll limit 5152 * member 5153 */ 5154 bmplength = 144; 5155 else 5156 /* 5157 * Length not exact: this is long enough to get dual link 5158 * transition clock. 5159 */ 5160 bmplength = 158; 5161 5162 /* checksum */ 5163 if (nv_cksum(bmp, 8)) { 5164 NV_ERROR(dev, "Bad BMP checksum\n"); 5165 return -EINVAL; 5166 } 5167 5168 /* 5169 * Bit 4 seems to indicate either a mobile bios or a quadro card -- 5170 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl 5171 * (not nv10gl), bit 5 that the flat panel tables are present, and 5172 * bit 6 a tv bios. 5173 */ 5174 bios->feature_byte = bmp[9]; 5175 5176 parse_bios_version(dev, bios, offset + 10); 5177 5178 if (bmp_version_major < 5 || bmp_version_minor < 0x10) 5179 bios->old_style_init = true; 5180 legacy_scripts_offset = 18; 5181 if (bmp_version_major < 2) 5182 legacy_scripts_offset -= 4; 5183 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]); 5184 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]); 5185 5186 if (bmp_version_major > 2) { /* appears in BMP 3 */ 5187 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]); 5188 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]); 5189 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]); 5190 } 5191 5192 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */ 5193 if (bmplength > 61) 5194 legacy_i2c_offset = offset + 54; 5195 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset]; 5196 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1]; 5197 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2]; 5198 if (bios->data[legacy_i2c_offset + 4]) 5199 bios->dcb.i2c[0].write = bios->data[legacy_i2c_offset + 4]; 5200 if (bios->data[legacy_i2c_offset + 5]) 5201 bios->dcb.i2c[0].read = bios->data[legacy_i2c_offset + 5]; 5202 if (bios->data[legacy_i2c_offset + 6]) 5203 bios->dcb.i2c[1].write = bios->data[legacy_i2c_offset + 6]; 5204 if (bios->data[legacy_i2c_offset + 7]) 5205 bios->dcb.i2c[1].read = bios->data[legacy_i2c_offset + 7]; 5206 5207 if (bmplength > 74) { 5208 bios->fmaxvco = ROM32(bmp[67]); 5209 bios->fminvco = ROM32(bmp[71]); 5210 } 5211 if (bmplength > 88) 5212 parse_script_table_pointers(bios, offset + 75); 5213 if (bmplength > 94) { 5214 bios->tmds.output0_script_ptr = ROM16(bmp[89]); 5215 bios->tmds.output1_script_ptr = ROM16(bmp[91]); 5216 /* 5217 * Never observed in use with lvds scripts, but is reused for 5218 * 18/24 bit panel interface default for EDID equipped panels 5219 * (if_is_24bit not set directly to avoid any oscillation). 5220 */ 5221 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]); 5222 } 5223 if (bmplength > 108) { 5224 bios->fp.fptablepointer = ROM16(bmp[105]); 5225 bios->fp.fpxlatetableptr = ROM16(bmp[107]); 5226 bios->fp.xlatwidth = 1; 5227 } 5228 if (bmplength > 120) { 5229 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]); 5230 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]); 5231 } 5232 if (bmplength > 143) 5233 bios->pll_limit_tbl_ptr = ROM16(bmp[142]); 5234 5235 if (bmplength > 157) 5236 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10; 5237 5238 return 0; 5239} 5240 5241static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len) 5242{ 5243 int i, j; 5244 5245 for (i = 0; i <= (n - len); i++) { 5246 for (j = 0; j < len; j++) 5247 if (data[i + j] != str[j]) 5248 break; 5249 if (j == len) 5250 return i; 5251 } 5252 5253 return 0; 5254} 5255 5256static struct dcb_gpio_entry * 5257new_gpio_entry(struct nvbios *bios) 5258{ 5259 struct dcb_gpio_table *gpio = &bios->dcb.gpio; 5260 5261 return &gpio->entry[gpio->entries++]; 5262} 5263 5264struct dcb_gpio_entry * 5265nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag) 5266{ 5267 struct drm_nouveau_private *dev_priv = dev->dev_private; 5268 struct nvbios *bios = &dev_priv->vbios; 5269 int i; 5270 5271 for (i = 0; i < bios->dcb.gpio.entries; i++) { 5272 if (bios->dcb.gpio.entry[i].tag != tag) 5273 continue; 5274 5275 return &bios->dcb.gpio.entry[i]; 5276 } 5277 5278 return NULL; 5279} 5280 5281static void 5282parse_dcb30_gpio_entry(struct nvbios *bios, uint16_t offset) 5283{ 5284 struct dcb_gpio_entry *gpio; 5285 uint16_t ent = ROM16(bios->data[offset]); 5286 uint8_t line = ent & 0x1f, 5287 tag = ent >> 5 & 0x3f, 5288 flags = ent >> 11 & 0x1f; 5289 5290 if (tag == 0x3f) 5291 return; 5292 5293 gpio = new_gpio_entry(bios); 5294 5295 gpio->tag = tag; 5296 gpio->line = line; 5297 gpio->invert = flags != 4; 5298 gpio->entry = ent; 5299} 5300 5301static void 5302parse_dcb40_gpio_entry(struct nvbios *bios, uint16_t offset) 5303{ 5304 uint32_t entry = ROM32(bios->data[offset]); 5305 struct dcb_gpio_entry *gpio; 5306 5307 if ((entry & 0x0000ff00) == 0x0000ff00) 5308 return; 5309 5310 gpio = new_gpio_entry(bios); 5311 gpio->tag = (entry & 0x0000ff00) >> 8; 5312 gpio->line = (entry & 0x0000001f) >> 0; 5313 gpio->state_default = (entry & 0x01000000) >> 24; 5314 gpio->state[0] = (entry & 0x18000000) >> 27; 5315 gpio->state[1] = (entry & 0x60000000) >> 29; 5316 gpio->entry = entry; 5317} 5318 5319static void 5320parse_dcb_gpio_table(struct nvbios *bios) 5321{ 5322 struct drm_device *dev = bios->dev; 5323 uint16_t gpio_table_ptr = bios->dcb.gpio_table_ptr; 5324 uint8_t *gpio_table = &bios->data[gpio_table_ptr]; 5325 int header_len = gpio_table[1], 5326 entries = gpio_table[2], 5327 entry_len = gpio_table[3]; 5328 void (*parse_entry)(struct nvbios *, uint16_t) = NULL; 5329 int i; 5330 5331 if (bios->dcb.version >= 0x40) { 5332 if (gpio_table_ptr && entry_len != 4) { 5333 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n"); 5334 return; 5335 } 5336 5337 parse_entry = parse_dcb40_gpio_entry; 5338 5339 } else if (bios->dcb.version >= 0x30) { 5340 if (gpio_table_ptr && entry_len != 2) { 5341 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n"); 5342 return; 5343 } 5344 5345 parse_entry = parse_dcb30_gpio_entry; 5346 5347 } else if (bios->dcb.version >= 0x22) { 5348 /* 5349 * DCBs older than v3.0 don't really have a GPIO 5350 * table, instead they keep some GPIO info at fixed 5351 * locations. 5352 */ 5353 uint16_t dcbptr = ROM16(bios->data[0x36]); 5354 uint8_t *tvdac_gpio = &bios->data[dcbptr - 5]; 5355 5356 if (tvdac_gpio[0] & 1) { 5357 struct dcb_gpio_entry *gpio = new_gpio_entry(bios); 5358 5359 gpio->tag = DCB_GPIO_TVDAC0; 5360 gpio->line = tvdac_gpio[1] >> 4; 5361 gpio->invert = tvdac_gpio[0] & 2; 5362 } 5363 } 5364 5365 if (!gpio_table_ptr) 5366 return; 5367 5368 if (entries > DCB_MAX_NUM_GPIO_ENTRIES) { 5369 NV_WARN(dev, "Too many entries in the DCB GPIO table.\n"); 5370 entries = DCB_MAX_NUM_GPIO_ENTRIES; 5371 } 5372 5373 for (i = 0; i < entries; i++) 5374 parse_entry(bios, gpio_table_ptr + header_len + entry_len * i); 5375} 5376 5377struct dcb_connector_table_entry * 5378nouveau_bios_connector_entry(struct drm_device *dev, int index) 5379{ 5380 struct drm_nouveau_private *dev_priv = dev->dev_private; 5381 struct nvbios *bios = &dev_priv->vbios; 5382 struct dcb_connector_table_entry *cte; 5383 5384 if (index >= bios->dcb.connector.entries) 5385 return NULL; 5386 5387 cte = &bios->dcb.connector.entry[index]; 5388 if (cte->type == 0xff) 5389 return NULL; 5390 5391 return cte; 5392} 5393 5394static enum dcb_connector_type 5395divine_connector_type(struct nvbios *bios, int index) 5396{ 5397 struct dcb_table *dcb = &bios->dcb; 5398 unsigned encoders = 0, type = DCB_CONNECTOR_NONE; 5399 int i; 5400 5401 for (i = 0; i < dcb->entries; i++) { 5402 if (dcb->entry[i].connector == index) 5403 encoders |= (1 << dcb->entry[i].type); 5404 } 5405 5406 if (encoders & (1 << OUTPUT_DP)) { 5407 if (encoders & (1 << OUTPUT_TMDS)) 5408 type = DCB_CONNECTOR_DP; 5409 else 5410 type = DCB_CONNECTOR_eDP; 5411 } else 5412 if (encoders & (1 << OUTPUT_TMDS)) { 5413 if (encoders & (1 << OUTPUT_ANALOG)) 5414 type = DCB_CONNECTOR_DVI_I; 5415 else 5416 type = DCB_CONNECTOR_DVI_D; 5417 } else 5418 if (encoders & (1 << OUTPUT_ANALOG)) { 5419 type = DCB_CONNECTOR_VGA; 5420 } else 5421 if (encoders & (1 << OUTPUT_LVDS)) { 5422 type = DCB_CONNECTOR_LVDS; 5423 } else 5424 if (encoders & (1 << OUTPUT_TV)) { 5425 type = DCB_CONNECTOR_TV_0; 5426 } 5427 5428 return type; 5429} 5430 5431static void 5432apply_dcb_connector_quirks(struct nvbios *bios, int idx) 5433{ 5434 struct dcb_connector_table_entry *cte = &bios->dcb.connector.entry[idx]; 5435 struct drm_device *dev = bios->dev; 5436 5437 /* Gigabyte NX85T */ 5438 if ((dev->pdev->device == 0x0421) && 5439 (dev->pdev->subsystem_vendor == 0x1458) && 5440 (dev->pdev->subsystem_device == 0x344c)) { 5441 if (cte->type == DCB_CONNECTOR_HDMI_1) 5442 cte->type = DCB_CONNECTOR_DVI_I; 5443 } 5444} 5445 5446static void 5447parse_dcb_connector_table(struct nvbios *bios) 5448{ 5449 struct drm_device *dev = bios->dev; 5450 struct dcb_connector_table *ct = &bios->dcb.connector; 5451 struct dcb_connector_table_entry *cte; 5452 uint8_t *conntab = &bios->data[bios->dcb.connector_table_ptr]; 5453 uint8_t *entry; 5454 int i; 5455 5456 if (!bios->dcb.connector_table_ptr) { 5457 NV_DEBUG_KMS(dev, "No DCB connector table present\n"); 5458 return; 5459 } 5460 5461 NV_INFO(dev, "DCB connector table: VHER 0x%02x %d %d %d\n", 5462 conntab[0], conntab[1], conntab[2], conntab[3]); 5463 if ((conntab[0] != 0x30 && conntab[0] != 0x40) || 5464 (conntab[3] != 2 && conntab[3] != 4)) { 5465 NV_ERROR(dev, " Unknown! Please report.\n"); 5466 return; 5467 } 5468 5469 ct->entries = conntab[2]; 5470 5471 entry = conntab + conntab[1]; 5472 cte = &ct->entry[0]; 5473 for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) { 5474 cte->index = i; 5475 if (conntab[3] == 2) 5476 cte->entry = ROM16(entry[0]); 5477 else 5478 cte->entry = ROM32(entry[0]); 5479 5480 cte->type = (cte->entry & 0x000000ff) >> 0; 5481 cte->index2 = (cte->entry & 0x00000f00) >> 8; 5482 switch (cte->entry & 0x00033000) { 5483 case 0x00001000: 5484 cte->gpio_tag = 0x07; 5485 break; 5486 case 0x00002000: 5487 cte->gpio_tag = 0x08; 5488 break; 5489 case 0x00010000: 5490 cte->gpio_tag = 0x51; 5491 break; 5492 case 0x00020000: 5493 cte->gpio_tag = 0x52; 5494 break; 5495 default: 5496 cte->gpio_tag = 0xff; 5497 break; 5498 } 5499 5500 if (cte->type == 0xff) 5501 continue; 5502 5503 apply_dcb_connector_quirks(bios, i); 5504 5505 NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n", 5506 i, cte->entry, cte->type, cte->index, cte->gpio_tag); 5507 5508 /* check for known types, fallback to guessing the type 5509 * from attached encoders if we hit an unknown. 5510 */ 5511 switch (cte->type) { 5512 case DCB_CONNECTOR_VGA: 5513 case DCB_CONNECTOR_TV_0: 5514 case DCB_CONNECTOR_TV_1: 5515 case DCB_CONNECTOR_TV_3: 5516 case DCB_CONNECTOR_DVI_I: 5517 case DCB_CONNECTOR_DVI_D: 5518 case DCB_CONNECTOR_LVDS: 5519 case DCB_CONNECTOR_DP: 5520 case DCB_CONNECTOR_eDP: 5521 case DCB_CONNECTOR_HDMI_0: 5522 case DCB_CONNECTOR_HDMI_1: 5523 break; 5524 default: 5525 cte->type = divine_connector_type(bios, cte->index); 5526 NV_WARN(dev, "unknown type, using 0x%02x\n", cte->type); 5527 break; 5528 } 5529 5530 if (nouveau_override_conntype) { 5531 int type = divine_connector_type(bios, cte->index); 5532 if (type != cte->type) 5533 NV_WARN(dev, " -> type 0x%02x\n", cte->type); 5534 } 5535 5536 } 5537} 5538 5539static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb) 5540{ 5541 struct dcb_entry *entry = &dcb->entry[dcb->entries]; 5542 5543 memset(entry, 0, sizeof(struct dcb_entry)); 5544 entry->index = dcb->entries++; 5545 5546 return entry; 5547} 5548 5549static void fabricate_vga_output(struct dcb_table *dcb, int i2c, int heads) 5550{ 5551 struct dcb_entry *entry = new_dcb_entry(dcb); 5552 5553 entry->type = 0; 5554 entry->i2c_index = i2c; 5555 entry->heads = heads; 5556 entry->location = DCB_LOC_ON_CHIP; 5557 /* "or" mostly unused in early gen crt modesetting, 0 is fine */ 5558} 5559 5560static void fabricate_dvi_i_output(struct dcb_table *dcb, bool twoHeads) 5561{ 5562 struct dcb_entry *entry = new_dcb_entry(dcb); 5563 5564 entry->type = 2; 5565 entry->i2c_index = LEGACY_I2C_PANEL; 5566 entry->heads = twoHeads ? 3 : 1; 5567 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */ 5568 entry->or = 1; /* means |0x10 gets set on CRE_LCD__INDEX */ 5569 entry->duallink_possible = false; /* SiI164 and co. are single link */ 5570 5571#if 0 5572 /* 5573 * For dvi-a either crtc probably works, but my card appears to only 5574 * support dvi-d. "nvidia" still attempts to program it for dvi-a, 5575 * doing the full fp output setup (program 0x6808.. fp dimension regs, 5576 * setting 0x680848 to 0x10000111 to enable, maybe setting 0x680880); 5577 * the monitor picks up the mode res ok and lights up, but no pixel 5578 * data appears, so the board manufacturer probably connected up the 5579 * sync lines, but missed the video traces / components 5580 * 5581 * with this introduction, dvi-a left as an exercise for the reader. 5582 */ 5583 fabricate_vga_output(dcb, LEGACY_I2C_PANEL, entry->heads); 5584#endif 5585} 5586 5587static void fabricate_tv_output(struct dcb_table *dcb, bool twoHeads) 5588{ 5589 struct dcb_entry *entry = new_dcb_entry(dcb); 5590 5591 entry->type = 1; 5592 entry->i2c_index = LEGACY_I2C_TV; 5593 entry->heads = twoHeads ? 3 : 1; 5594 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */ 5595} 5596 5597static bool 5598parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb, 5599 uint32_t conn, uint32_t conf, struct dcb_entry *entry) 5600{ 5601 entry->type = conn & 0xf; 5602 entry->i2c_index = (conn >> 4) & 0xf; 5603 entry->heads = (conn >> 8) & 0xf; 5604 if (dcb->version >= 0x40) 5605 entry->connector = (conn >> 12) & 0xf; 5606 entry->bus = (conn >> 16) & 0xf; 5607 entry->location = (conn >> 20) & 0x3; 5608 entry->or = (conn >> 24) & 0xf; 5609 5610 switch (entry->type) { 5611 case OUTPUT_ANALOG: 5612 /* 5613 * Although the rest of a CRT conf dword is usually 5614 * zeros, mac biosen have stuff there so we must mask 5615 */ 5616 entry->crtconf.maxfreq = (dcb->version < 0x30) ? 5617 (conf & 0xffff) * 10 : 5618 (conf & 0xff) * 10000; 5619 break; 5620 case OUTPUT_LVDS: 5621 { 5622 uint32_t mask; 5623 if (conf & 0x1) 5624 entry->lvdsconf.use_straps_for_mode = true; 5625 if (dcb->version < 0x22) { 5626 mask = ~0xd; 5627 /* 5628 * The laptop in bug 14567 lies and claims to not use 5629 * straps when it does, so assume all DCB 2.0 laptops 5630 * use straps, until a broken EDID using one is produced 5631 */ 5632 entry->lvdsconf.use_straps_for_mode = true; 5633 /* 5634 * Both 0x4 and 0x8 show up in v2.0 tables; assume they 5635 * mean the same thing (probably wrong, but might work) 5636 */ 5637 if (conf & 0x4 || conf & 0x8) 5638 entry->lvdsconf.use_power_scripts = true; 5639 } else { 5640 mask = ~0x5; 5641 if (conf & 0x4) 5642 entry->lvdsconf.use_power_scripts = true; 5643 } 5644 if (conf & mask) { 5645 /* 5646 * Until we even try to use these on G8x, it's 5647 * useless reporting unknown bits. They all are. 5648 */ 5649 if (dcb->version >= 0x40) 5650 break; 5651 5652 NV_ERROR(dev, "Unknown LVDS configuration bits, " 5653 "please report\n"); 5654 } 5655 break; 5656 } 5657 case OUTPUT_TV: 5658 { 5659 if (dcb->version >= 0x30) 5660 entry->tvconf.has_component_output = conf & (0x8 << 4); 5661 else 5662 entry->tvconf.has_component_output = false; 5663 5664 break; 5665 } 5666 case OUTPUT_DP: 5667 entry->dpconf.sor.link = (conf & 0x00000030) >> 4; 5668 entry->dpconf.link_bw = (conf & 0x00e00000) >> 21; 5669 switch ((conf & 0x0f000000) >> 24) { 5670 case 0xf: 5671 entry->dpconf.link_nr = 4; 5672 break; 5673 case 0x3: 5674 entry->dpconf.link_nr = 2; 5675 break; 5676 default: 5677 entry->dpconf.link_nr = 1; 5678 break; 5679 } 5680 break; 5681 case OUTPUT_TMDS: 5682 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4; 5683 break; 5684 case 0xe: 5685 /* weird g80 mobile type that "nv" treats as a terminator */ 5686 dcb->entries--; 5687 return false; 5688 default: 5689 break; 5690 } 5691 5692 if (dcb->version < 0x40) { 5693 /* Normal entries consist of a single bit, but dual link has 5694 * the next most significant bit set too 5695 */ 5696 entry->duallink_possible = 5697 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or); 5698 } else { 5699 entry->duallink_possible = (entry->sorconf.link == 3); 5700 } 5701 5702 /* unsure what DCB version introduces this, 3.0? */ 5703 if (conf & 0x100000) 5704 entry->i2c_upper_default = true; 5705 5706 return true; 5707} 5708 5709static bool 5710parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb, 5711 uint32_t conn, uint32_t conf, struct dcb_entry *entry) 5712{ 5713 switch (conn & 0x0000000f) { 5714 case 0: 5715 entry->type = OUTPUT_ANALOG; 5716 break; 5717 case 1: 5718 entry->type = OUTPUT_TV; 5719 break; 5720 case 2: 5721 case 3: 5722 entry->type = OUTPUT_LVDS; 5723 break; 5724 case 4: 5725 switch ((conn & 0x000000f0) >> 4) { 5726 case 0: 5727 entry->type = OUTPUT_TMDS; 5728 break; 5729 case 1: 5730 entry->type = OUTPUT_LVDS; 5731 break; 5732 default: 5733 NV_ERROR(dev, "Unknown DCB subtype 4/%d\n", 5734 (conn & 0x000000f0) >> 4); 5735 return false; 5736 } 5737 break; 5738 default: 5739 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f); 5740 return false; 5741 } 5742 5743 entry->i2c_index = (conn & 0x0003c000) >> 14; 5744 entry->heads = ((conn & 0x001c0000) >> 18) + 1; 5745 entry->or = entry->heads; /* same as heads, hopefully safe enough */ 5746 entry->location = (conn & 0x01e00000) >> 21; 5747 entry->bus = (conn & 0x0e000000) >> 25; 5748 entry->duallink_possible = false; 5749 5750 switch (entry->type) { 5751 case OUTPUT_ANALOG: 5752 entry->crtconf.maxfreq = (conf & 0xffff) * 10; 5753 break; 5754 case OUTPUT_TV: 5755 entry->tvconf.has_component_output = false; 5756 break; 5757 case OUTPUT_TMDS: 5758 /* 5759 * Invent a DVI-A output, by copying the fields of the DVI-D 5760 * output; reported to work by math_b on an NV20(!). 5761 */ 5762 fabricate_vga_output(dcb, entry->i2c_index, entry->heads); 5763 break; 5764 case OUTPUT_LVDS: 5765 if ((conn & 0x00003f00) != 0x10) 5766 entry->lvdsconf.use_straps_for_mode = true; 5767 entry->lvdsconf.use_power_scripts = true; 5768 break; 5769 default: 5770 break; 5771 } 5772 5773 return true; 5774} 5775 5776static bool parse_dcb_entry(struct drm_device *dev, struct dcb_table *dcb, 5777 uint32_t conn, uint32_t conf) 5778{ 5779 struct dcb_entry *entry = new_dcb_entry(dcb); 5780 bool ret; 5781 5782 if (dcb->version >= 0x20) 5783 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry); 5784 else 5785 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry); 5786 if (!ret) 5787 return ret; 5788 5789 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table, 5790 entry->i2c_index, &dcb->i2c[entry->i2c_index]); 5791 5792 return true; 5793} 5794 5795static 5796void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb) 5797{ 5798 /* 5799 * DCB v2.0 lists each output combination separately. 5800 * Here we merge compatible entries to have fewer outputs, with 5801 * more options 5802 */ 5803 5804 int i, newentries = 0; 5805 5806 for (i = 0; i < dcb->entries; i++) { 5807 struct dcb_entry *ient = &dcb->entry[i]; 5808 int j; 5809 5810 for (j = i + 1; j < dcb->entries; j++) { 5811 struct dcb_entry *jent = &dcb->entry[j]; 5812 5813 if (jent->type == 100) /* already merged entry */ 5814 continue; 5815 5816 /* merge heads field when all other fields the same */ 5817 if (jent->i2c_index == ient->i2c_index && 5818 jent->type == ient->type && 5819 jent->location == ient->location && 5820 jent->or == ient->or) { 5821 NV_TRACE(dev, "Merging DCB entries %d and %d\n", 5822 i, j); 5823 ient->heads |= jent->heads; 5824 jent->type = 100; /* dummy value */ 5825 } 5826 } 5827 } 5828 5829 /* Compact entries merged into others out of dcb */ 5830 for (i = 0; i < dcb->entries; i++) { 5831 if (dcb->entry[i].type == 100) 5832 continue; 5833 5834 if (newentries != i) { 5835 dcb->entry[newentries] = dcb->entry[i]; 5836 dcb->entry[newentries].index = newentries; 5837 } 5838 newentries++; 5839 } 5840 5841 dcb->entries = newentries; 5842} 5843 5844static int 5845parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads) 5846{ 5847 struct drm_nouveau_private *dev_priv = dev->dev_private; 5848 struct dcb_table *dcb = &bios->dcb; 5849 uint16_t dcbptr = 0, i2ctabptr = 0; 5850 uint8_t *dcbtable; 5851 uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES; 5852 bool configblock = true; 5853 int recordlength = 8, confofs = 4; 5854 int i; 5855 5856 /* get the offset from 0x36 */ 5857 if (dev_priv->card_type > NV_04) { 5858 dcbptr = ROM16(bios->data[0x36]); 5859 if (dcbptr == 0x0000) 5860 NV_WARN(dev, "No output data (DCB) found in BIOS\n"); 5861 } 5862 5863 /* this situation likely means a really old card, pre DCB */ 5864 if (dcbptr == 0x0) { 5865 NV_INFO(dev, "Assuming a CRT output exists\n"); 5866 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1); 5867 5868 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0) 5869 fabricate_tv_output(dcb, twoHeads); 5870 5871 return 0; 5872 } 5873 5874 dcbtable = &bios->data[dcbptr]; 5875 5876 /* get DCB version */ 5877 dcb->version = dcbtable[0]; 5878 NV_TRACE(dev, "Found Display Configuration Block version %d.%d\n", 5879 dcb->version >> 4, dcb->version & 0xf); 5880 5881 if (dcb->version >= 0x20) { /* NV17+ */ 5882 uint32_t sig; 5883 5884 if (dcb->version >= 0x30) { /* NV40+ */ 5885 headerlen = dcbtable[1]; 5886 entries = dcbtable[2]; 5887 recordlength = dcbtable[3]; 5888 i2ctabptr = ROM16(dcbtable[4]); 5889 sig = ROM32(dcbtable[6]); 5890 dcb->gpio_table_ptr = ROM16(dcbtable[10]); 5891 dcb->connector_table_ptr = ROM16(dcbtable[20]); 5892 } else { 5893 i2ctabptr = ROM16(dcbtable[2]); 5894 sig = ROM32(dcbtable[4]); 5895 headerlen = 8; 5896 } 5897 5898 if (sig != 0x4edcbdcb) { 5899 NV_ERROR(dev, "Bad Display Configuration Block " 5900 "signature (%08X)\n", sig); 5901 return -EINVAL; 5902 } 5903 } else if (dcb->version >= 0x15) { /* some NV11 and NV20 */ 5904 char sig[8] = { 0 }; 5905 5906 strncpy(sig, (char *)&dcbtable[-7], 7); 5907 i2ctabptr = ROM16(dcbtable[2]); 5908 recordlength = 10; 5909 confofs = 6; 5910 5911 if (strcmp(sig, "DEV_REC")) { 5912 NV_ERROR(dev, "Bad Display Configuration Block " 5913 "signature (%s)\n", sig); 5914 return -EINVAL; 5915 } 5916 } else { 5917 /* 5918 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always 5919 * has the same single (crt) entry, even when tv-out present, so 5920 * the conclusion is this version cannot really be used. 5921 * v1.2 tables (some NV6/10, and NV15+) normally have the same 5922 * 5 entries, which are not specific to the card and so no use. 5923 * v1.2 does have an I2C table that read_dcb_i2c_table can 5924 * handle, but cards exist (nv11 in #14821) with a bad i2c table 5925 * pointer, so use the indices parsed in parse_bmp_structure. 5926 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful 5927 */ 5928 NV_TRACEWARN(dev, "No useful information in BIOS output table; " 5929 "adding all possible outputs\n"); 5930 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1); 5931 5932 /* 5933 * Attempt to detect TV before DVI because the test 5934 * for the former is more accurate and it rules the 5935 * latter out. 5936 */ 5937 if (nv04_tv_identify(dev, 5938 bios->legacy.i2c_indices.tv) >= 0) 5939 fabricate_tv_output(dcb, twoHeads); 5940 5941 else if (bios->tmds.output0_script_ptr || 5942 bios->tmds.output1_script_ptr) 5943 fabricate_dvi_i_output(dcb, twoHeads); 5944 5945 return 0; 5946 } 5947 5948 if (!i2ctabptr) 5949 NV_WARN(dev, "No pointer to DCB I2C port table\n"); 5950 else { 5951 dcb->i2c_table = &bios->data[i2ctabptr]; 5952 if (dcb->version >= 0x30) 5953 dcb->i2c_default_indices = dcb->i2c_table[4]; 5954 } 5955 5956 if (entries > DCB_MAX_NUM_ENTRIES) 5957 entries = DCB_MAX_NUM_ENTRIES; 5958 5959 for (i = 0; i < entries; i++) { 5960 uint32_t connection, config = 0; 5961 5962 connection = ROM32(dcbtable[headerlen + recordlength * i]); 5963 if (configblock) 5964 config = ROM32(dcbtable[headerlen + confofs + recordlength * i]); 5965 5966 /* seen on an NV11 with DCB v1.5 */ 5967 if (connection == 0x00000000) 5968 break; 5969 5970 /* seen on an NV17 with DCB v2.0 */ 5971 if (connection == 0xffffffff) 5972 break; 5973 5974 if ((connection & 0x0000000f) == 0x0000000f) 5975 continue; 5976 5977 NV_TRACEWARN(dev, "Raw DCB entry %d: %08x %08x\n", 5978 dcb->entries, connection, config); 5979 5980 if (!parse_dcb_entry(dev, dcb, connection, config)) 5981 break; 5982 } 5983 5984 /* 5985 * apart for v2.1+ not being known for requiring merging, this 5986 * guarantees dcbent->index is the index of the entry in the rom image 5987 */ 5988 if (dcb->version < 0x21) 5989 merge_like_dcb_entries(dev, dcb); 5990 5991 if (!dcb->entries) 5992 return -ENXIO; 5993 5994 parse_dcb_gpio_table(bios); 5995 parse_dcb_connector_table(bios); 5996 return 0; 5997} 5998 5999static void 6000fixup_legacy_connector(struct nvbios *bios) 6001{ 6002 struct dcb_table *dcb = &bios->dcb; 6003 int i, i2c, i2c_conn[DCB_MAX_NUM_I2C_ENTRIES] = { }; 6004 6005 /* 6006 * DCB 3.0 also has the table in most cases, but there are some cards 6007 * where the table is filled with stub entries, and the DCB entriy 6008 * indices are all 0. We don't need the connector indices on pre-G80 6009 * chips (yet?) so limit the use to DCB 4.0 and above. 6010 */ 6011 if (dcb->version >= 0x40) 6012 return; 6013 6014 dcb->connector.entries = 0; 6015 6016 /* 6017 * No known connector info before v3.0, so make it up. the rule here 6018 * is: anything on the same i2c bus is considered to be on the same 6019 * connector. any output without an associated i2c bus is assigned 6020 * its own unique connector index. 6021 */ 6022 for (i = 0; i < dcb->entries; i++) { 6023 /* 6024 * Ignore the I2C index for on-chip TV-out, as there 6025 * are cards with bogus values (nv31m in bug 23212), 6026 * and it's otherwise useless. 6027 */ 6028 if (dcb->entry[i].type == OUTPUT_TV && 6029 dcb->entry[i].location == DCB_LOC_ON_CHIP) 6030 dcb->entry[i].i2c_index = 0xf; 6031 i2c = dcb->entry[i].i2c_index; 6032 6033 if (i2c_conn[i2c]) { 6034 dcb->entry[i].connector = i2c_conn[i2c] - 1; 6035 continue; 6036 } 6037 6038 dcb->entry[i].connector = dcb->connector.entries++; 6039 if (i2c != 0xf) 6040 i2c_conn[i2c] = dcb->connector.entries; 6041 } 6042 6043 /* Fake the connector table as well as just connector indices */ 6044 for (i = 0; i < dcb->connector.entries; i++) { 6045 dcb->connector.entry[i].index = i; 6046 dcb->connector.entry[i].type = divine_connector_type(bios, i); 6047 dcb->connector.entry[i].gpio_tag = 0xff; 6048 } 6049} 6050 6051static void 6052fixup_legacy_i2c(struct nvbios *bios) 6053{ 6054 struct dcb_table *dcb = &bios->dcb; 6055 int i; 6056 6057 for (i = 0; i < dcb->entries; i++) { 6058 if (dcb->entry[i].i2c_index == LEGACY_I2C_CRT) 6059 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.crt; 6060 if (dcb->entry[i].i2c_index == LEGACY_I2C_PANEL) 6061 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.panel; 6062 if (dcb->entry[i].i2c_index == LEGACY_I2C_TV) 6063 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.tv; 6064 } 6065} 6066 6067static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry) 6068{ 6069 /* 6070 * The header following the "HWSQ" signature has the number of entries, 6071 * and the entry size 6072 * 6073 * An entry consists of a dword to write to the sequencer control reg 6074 * (0x00001304), followed by the ucode bytes, written sequentially, 6075 * starting at reg 0x00001400 6076 */ 6077 6078 uint8_t bytes_to_write; 6079 uint16_t hwsq_entry_offset; 6080 int i; 6081 6082 if (bios->data[hwsq_offset] <= entry) { 6083 NV_ERROR(dev, "Too few entries in HW sequencer table for " 6084 "requested entry\n"); 6085 return -ENOENT; 6086 } 6087 6088 bytes_to_write = bios->data[hwsq_offset + 1]; 6089 6090 if (bytes_to_write != 36) { 6091 NV_ERROR(dev, "Unknown HW sequencer entry size\n"); 6092 return -EINVAL; 6093 } 6094 6095 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n"); 6096 6097 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write; 6098 6099 /* set sequencer control */ 6100 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset])); 6101 bytes_to_write -= 4; 6102 6103 /* write ucode */ 6104 for (i = 0; i < bytes_to_write; i += 4) 6105 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4])); 6106 6107 /* twiddle NV_PBUS_DEBUG_4 */ 6108 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18); 6109 6110 return 0; 6111} 6112 6113static int load_nv17_hw_sequencer_ucode(struct drm_device *dev, 6114 struct nvbios *bios) 6115{ 6116 /* 6117 * BMP based cards, from NV17, need a microcode loading to correctly 6118 * control the GPIO etc for LVDS panels 6119 * 6120 * BIT based cards seem to do this directly in the init scripts 6121 * 6122 * The microcode entries are found by the "HWSQ" signature. 6123 */ 6124 6125 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' }; 6126 const int sz = sizeof(hwsq_signature); 6127 int hwsq_offset; 6128 6129 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz); 6130 if (!hwsq_offset) 6131 return 0; 6132 6133 /* always use entry 0? */ 6134 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0); 6135} 6136 6137uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev) 6138{ 6139 struct drm_nouveau_private *dev_priv = dev->dev_private; 6140 struct nvbios *bios = &dev_priv->vbios; 6141 const uint8_t edid_sig[] = { 6142 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 }; 6143 uint16_t offset = 0; 6144 uint16_t newoffset; 6145 int searchlen = NV_PROM_SIZE; 6146 6147 if (bios->fp.edid) 6148 return bios->fp.edid; 6149 6150 while (searchlen) { 6151 newoffset = findstr(&bios->data[offset], searchlen, 6152 edid_sig, 8); 6153 if (!newoffset) 6154 return NULL; 6155 offset += newoffset; 6156 if (!nv_cksum(&bios->data[offset], EDID1_LEN)) 6157 break; 6158 6159 searchlen -= offset; 6160 offset++; 6161 } 6162 6163 NV_TRACE(dev, "Found EDID in BIOS\n"); 6164 6165 return bios->fp.edid = &bios->data[offset]; 6166} 6167 6168void 6169nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table, 6170 struct dcb_entry *dcbent) 6171{ 6172 struct drm_nouveau_private *dev_priv = dev->dev_private; 6173 struct nvbios *bios = &dev_priv->vbios; 6174 struct init_exec iexec = { true, false }; 6175 6176 mutex_lock(&bios->lock); 6177 bios->display.output = dcbent; 6178 parse_init_table(bios, table, &iexec); 6179 bios->display.output = NULL; 6180 mutex_unlock(&bios->lock); 6181} 6182 6183static bool NVInitVBIOS(struct drm_device *dev) 6184{ 6185 struct drm_nouveau_private *dev_priv = dev->dev_private; 6186 struct nvbios *bios = &dev_priv->vbios; 6187 6188 memset(bios, 0, sizeof(struct nvbios)); 6189 mutex_init(&bios->lock); 6190 bios->dev = dev; 6191 6192 if (!NVShadowVBIOS(dev, bios->data)) 6193 return false; 6194 6195 bios->length = NV_PROM_SIZE; 6196 return true; 6197} 6198 6199static int nouveau_parse_vbios_struct(struct drm_device *dev) 6200{ 6201 struct drm_nouveau_private *dev_priv = dev->dev_private; 6202 struct nvbios *bios = &dev_priv->vbios; 6203 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' }; 6204 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 }; 6205 int offset; 6206 6207 offset = findstr(bios->data, bios->length, 6208 bit_signature, sizeof(bit_signature)); 6209 if (offset) { 6210 NV_TRACE(dev, "BIT BIOS found\n"); 6211 return parse_bit_structure(bios, offset + 6); 6212 } 6213 6214 offset = findstr(bios->data, bios->length, 6215 bmp_signature, sizeof(bmp_signature)); 6216 if (offset) { 6217 NV_TRACE(dev, "BMP BIOS found\n"); 6218 return parse_bmp_structure(dev, bios, offset); 6219 } 6220 6221 NV_ERROR(dev, "No known BIOS signature found\n"); 6222 return -ENODEV; 6223} 6224 6225int 6226nouveau_run_vbios_init(struct drm_device *dev) 6227{ 6228 struct drm_nouveau_private *dev_priv = dev->dev_private; 6229 struct nvbios *bios = &dev_priv->vbios; 6230 int i, ret = 0; 6231 6232 NVLockVgaCrtcs(dev, false); 6233 if (nv_two_heads(dev)) 6234 NVSetOwner(dev, bios->state.crtchead); 6235 6236 if (bios->major_version < 5) /* BMP only */ 6237 load_nv17_hw_sequencer_ucode(dev, bios); 6238 6239 if (bios->execute) { 6240 bios->fp.last_script_invoc = 0; 6241 bios->fp.lvds_init_run = false; 6242 } 6243 6244 parse_init_tables(bios); 6245 6246 /* 6247 * Runs some additional script seen on G8x VBIOSen. The VBIOS' 6248 * parser will run this right after the init tables, the binary 6249 * driver appears to run it at some point later. 6250 */ 6251 if (bios->some_script_ptr) { 6252 struct init_exec iexec = {true, false}; 6253 6254 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n", 6255 bios->some_script_ptr); 6256 parse_init_table(bios, bios->some_script_ptr, &iexec); 6257 } 6258 6259 if (dev_priv->card_type >= NV_50) { 6260 for (i = 0; i < bios->dcb.entries; i++) { 6261 nouveau_bios_run_display_table(dev, 6262 &bios->dcb.entry[i], 6263 0, 0); 6264 } 6265 } 6266 6267 NVLockVgaCrtcs(dev, true); 6268 6269 return ret; 6270} 6271 6272static void 6273nouveau_bios_i2c_devices_takedown(struct drm_device *dev) 6274{ 6275 struct drm_nouveau_private *dev_priv = dev->dev_private; 6276 struct nvbios *bios = &dev_priv->vbios; 6277 struct dcb_i2c_entry *entry; 6278 int i; 6279 6280 entry = &bios->dcb.i2c[0]; 6281 for (i = 0; i < DCB_MAX_NUM_I2C_ENTRIES; i++, entry++) 6282 nouveau_i2c_fini(dev, entry); 6283} 6284 6285static bool 6286nouveau_bios_posted(struct drm_device *dev) 6287{ 6288 struct drm_nouveau_private *dev_priv = dev->dev_private; 6289 bool was_locked; 6290 unsigned htotal; 6291 6292 if (dev_priv->chipset >= NV_50) { 6293 if (NVReadVgaCrtc(dev, 0, 0x00) == 0 && 6294 NVReadVgaCrtc(dev, 0, 0x1a) == 0) 6295 return false; 6296 return true; 6297 } 6298 6299 was_locked = NVLockVgaCrtcs(dev, false); 6300 htotal = NVReadVgaCrtc(dev, 0, 0x06); 6301 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8; 6302 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4; 6303 htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10; 6304 htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11; 6305 NVLockVgaCrtcs(dev, was_locked); 6306 return (htotal != 0); 6307} 6308 6309int 6310nouveau_bios_init(struct drm_device *dev) 6311{ 6312 struct drm_nouveau_private *dev_priv = dev->dev_private; 6313 struct nvbios *bios = &dev_priv->vbios; 6314 uint32_t saved_nv_pextdev_boot_0; 6315 bool was_locked; 6316 int ret; 6317 6318 if (!NVInitVBIOS(dev)) 6319 return -ENODEV; 6320 6321 ret = nouveau_parse_vbios_struct(dev); 6322 if (ret) 6323 return ret; 6324 6325 ret = parse_dcb_table(dev, bios, nv_two_heads(dev)); 6326 if (ret) 6327 return ret; 6328 6329 fixup_legacy_i2c(bios); 6330 fixup_legacy_connector(bios); 6331 6332 if (!bios->major_version) /* we don't run version 0 bios */ 6333 return 0; 6334 6335 /* these will need remembering across a suspend */ 6336 saved_nv_pextdev_boot_0 = bios_rd32(bios, NV_PEXTDEV_BOOT_0); 6337 bios->state.saved_nv_pfb_cfg0 = bios_rd32(bios, NV_PFB_CFG0); 6338 6339 /* init script execution disabled */ 6340 bios->execute = false; 6341 6342 /* ... unless card isn't POSTed already */ 6343 if (!nouveau_bios_posted(dev)) { 6344 NV_INFO(dev, "Adaptor not initialised\n"); 6345 if (dev_priv->card_type < NV_40) { 6346 NV_ERROR(dev, "Unable to POST this chipset\n"); 6347 return -ENODEV; 6348 } 6349 6350 NV_INFO(dev, "Running VBIOS init tables\n"); 6351 bios->execute = true; 6352 } 6353 6354 bios_wr32(bios, NV_PEXTDEV_BOOT_0, saved_nv_pextdev_boot_0); 6355 6356 ret = nouveau_run_vbios_init(dev); 6357 if (ret) 6358 return ret; 6359 6360 /* feature_byte on BMP is poor, but init always sets CR4B */ 6361 was_locked = NVLockVgaCrtcs(dev, false); 6362 if (bios->major_version < 5) 6363 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40; 6364 6365 /* all BIT systems need p_f_m_t for digital_min_front_porch */ 6366 if (bios->is_mobile || bios->major_version >= 5) 6367 ret = parse_fp_mode_table(dev, bios); 6368 NVLockVgaCrtcs(dev, was_locked); 6369 6370 /* allow subsequent scripts to execute */ 6371 bios->execute = true; 6372 6373 return 0; 6374} 6375 6376void 6377nouveau_bios_takedown(struct drm_device *dev) 6378{ 6379 nouveau_bios_i2c_devices_takedown(dev); 6380} 6381