nouveau_bios.c revision 4489b9835a0867617a9ec29cc978a9c2c9eca363
1/* 2 * Copyright 2005-2006 Erik Waling 3 * Copyright 2006 Stephane Marchesin 4 * Copyright 2007-2009 Stuart Bennett 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 25#include "drmP.h" 26#define NV_DEBUG_NOTRACE 27#include "nouveau_drv.h" 28#include "nouveau_hw.h" 29#include "nouveau_encoder.h" 30#include "nouveau_gpio.h" 31 32#include <linux/io-mapping.h> 33 34/* these defines are made up */ 35#define NV_CIO_CRE_44_HEADA 0x0 36#define NV_CIO_CRE_44_HEADB 0x3 37#define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */ 38 39#define EDID1_LEN 128 40 41#define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg) 42#define LOG_OLD_VALUE(x) 43 44struct init_exec { 45 bool execute; 46 bool repeat; 47}; 48 49static bool nv_cksum(const uint8_t *data, unsigned int length) 50{ 51 /* 52 * There's a few checksums in the BIOS, so here's a generic checking 53 * function. 54 */ 55 int i; 56 uint8_t sum = 0; 57 58 for (i = 0; i < length; i++) 59 sum += data[i]; 60 61 if (sum) 62 return true; 63 64 return false; 65} 66 67static int 68score_vbios(struct nvbios *bios, const bool writeable) 69{ 70 if (!bios->data || bios->data[0] != 0x55 || bios->data[1] != 0xAA) { 71 NV_TRACEWARN(bios->dev, "... BIOS signature not found\n"); 72 return 0; 73 } 74 75 if (nv_cksum(bios->data, bios->data[2] * 512)) { 76 NV_TRACEWARN(bios->dev, "... BIOS checksum invalid\n"); 77 /* if a ro image is somewhat bad, it's probably all rubbish */ 78 return writeable ? 2 : 1; 79 } 80 81 NV_TRACE(bios->dev, "... appears to be valid\n"); 82 return 3; 83} 84 85static void 86bios_shadow_prom(struct nvbios *bios) 87{ 88 struct drm_device *dev = bios->dev; 89 struct drm_nouveau_private *dev_priv = dev->dev_private; 90 u32 pcireg, access; 91 u16 pcir; 92 int i; 93 94 /* enable access to rom */ 95 if (dev_priv->card_type >= NV_50) 96 pcireg = 0x088050; 97 else 98 pcireg = NV_PBUS_PCI_NV_20; 99 access = nv_mask(dev, pcireg, 0x00000001, 0x00000000); 100 101 /* bail if no rom signature, with a workaround for a PROM reading 102 * issue on some chipsets. the first read after a period of 103 * inactivity returns the wrong result, so retry the first header 104 * byte a few times before giving up as a workaround 105 */ 106 i = 16; 107 do { 108 if (nv_rd08(dev, NV_PROM_OFFSET + 0) == 0x55) 109 break; 110 } while (i--); 111 112 if (!i || nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa) 113 goto out; 114 115 /* additional check (see note below) - read PCI record header */ 116 pcir = nv_rd08(dev, NV_PROM_OFFSET + 0x18) | 117 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8; 118 if (nv_rd08(dev, NV_PROM_OFFSET + pcir + 0) != 'P' || 119 nv_rd08(dev, NV_PROM_OFFSET + pcir + 1) != 'C' || 120 nv_rd08(dev, NV_PROM_OFFSET + pcir + 2) != 'I' || 121 nv_rd08(dev, NV_PROM_OFFSET + pcir + 3) != 'R') 122 goto out; 123 124 /* read entire bios image to system memory */ 125 bios->length = nv_rd08(dev, NV_PROM_OFFSET + 2) * 512; 126 bios->data = kmalloc(bios->length, GFP_KERNEL); 127 if (bios->data) { 128 for (i = 0; i < bios->length; i++) 129 bios->data[i] = nv_rd08(dev, NV_PROM_OFFSET + i); 130 } 131 132out: 133 /* disable access to rom */ 134 nv_wr32(dev, pcireg, access); 135} 136 137static void 138bios_shadow_pramin(struct nvbios *bios) 139{ 140 struct drm_device *dev = bios->dev; 141 struct drm_nouveau_private *dev_priv = dev->dev_private; 142 u32 bar0 = 0; 143 int i; 144 145 if (dev_priv->card_type >= NV_50) { 146 u64 addr = (u64)(nv_rd32(dev, 0x619f04) & 0xffffff00) << 8; 147 if (!addr) { 148 addr = (u64)nv_rd32(dev, 0x001700) << 16; 149 addr += 0xf0000; 150 } 151 152 bar0 = nv_mask(dev, 0x001700, 0xffffffff, addr >> 16); 153 } 154 155 /* bail if no rom signature */ 156 if (nv_rd08(dev, NV_PRAMIN_OFFSET + 0) != 0x55 || 157 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa) 158 goto out; 159 160 bios->length = nv_rd08(dev, NV_PRAMIN_OFFSET + 2) * 512; 161 bios->data = kmalloc(bios->length, GFP_KERNEL); 162 if (bios->data) { 163 for (i = 0; i < bios->length; i++) 164 bios->data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i); 165 } 166 167out: 168 if (dev_priv->card_type >= NV_50) 169 nv_wr32(dev, 0x001700, bar0); 170} 171 172static void 173bios_shadow_pci(struct nvbios *bios) 174{ 175 struct pci_dev *pdev = bios->dev->pdev; 176 size_t length; 177 178 if (!pci_enable_rom(pdev)) { 179 void __iomem *rom = pci_map_rom(pdev, &length); 180 if (rom) { 181 bios->data = kmalloc(length, GFP_KERNEL); 182 if (bios->data) { 183 memcpy_fromio(bios->data, rom, length); 184 bios->length = length; 185 } 186 pci_unmap_rom(pdev, rom); 187 } 188 189 pci_disable_rom(pdev); 190 } 191} 192 193static void 194bios_shadow_acpi(struct nvbios *bios) 195{ 196 struct pci_dev *pdev = bios->dev->pdev; 197 int ptr, len, ret; 198 u8 data[3]; 199 200 if (!nouveau_acpi_rom_supported(pdev)) 201 return; 202 203 ret = nouveau_acpi_get_bios_chunk(data, 0, sizeof(data)); 204 if (ret != sizeof(data)) 205 return; 206 207 bios->length = min(data[2] * 512, 65536); 208 bios->data = kmalloc(bios->length, GFP_KERNEL); 209 if (!bios->data) 210 return; 211 212 len = bios->length; 213 ptr = 0; 214 while (len) { 215 int size = (len > ROM_BIOS_PAGE) ? ROM_BIOS_PAGE : len; 216 217 ret = nouveau_acpi_get_bios_chunk(bios->data, ptr, size); 218 if (ret != size) { 219 kfree(bios->data); 220 bios->data = NULL; 221 return; 222 } 223 224 len -= size; 225 ptr += size; 226 } 227} 228 229struct methods { 230 const char desc[8]; 231 void (*shadow)(struct nvbios *); 232 const bool rw; 233 int score; 234 u32 size; 235 u8 *data; 236}; 237 238static bool 239bios_shadow(struct drm_device *dev) 240{ 241 struct methods shadow_methods[] = { 242 { "PRAMIN", bios_shadow_pramin, true, 0, 0, NULL }, 243 { "PROM", bios_shadow_prom, false, 0, 0, NULL }, 244 { "ACPI", bios_shadow_acpi, true, 0, 0, NULL }, 245 { "PCIROM", bios_shadow_pci, true, 0, 0, NULL }, 246 {} 247 }; 248 struct drm_nouveau_private *dev_priv = dev->dev_private; 249 struct nvbios *bios = &dev_priv->vbios; 250 struct methods *mthd, *best; 251 252 if (nouveau_vbios) { 253 mthd = shadow_methods; 254 do { 255 if (strcasecmp(nouveau_vbios, mthd->desc)) 256 continue; 257 NV_INFO(dev, "VBIOS source: %s\n", mthd->desc); 258 259 mthd->shadow(bios); 260 mthd->score = score_vbios(bios, mthd->rw); 261 if (mthd->score) 262 return true; 263 } while ((++mthd)->shadow); 264 265 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios); 266 } 267 268 mthd = shadow_methods; 269 do { 270 NV_TRACE(dev, "Checking %s for VBIOS\n", mthd->desc); 271 mthd->shadow(bios); 272 mthd->score = score_vbios(bios, mthd->rw); 273 mthd->size = bios->length; 274 mthd->data = bios->data; 275 } while (mthd->score != 3 && (++mthd)->shadow); 276 277 mthd = shadow_methods; 278 best = mthd; 279 do { 280 if (mthd->score > best->score) { 281 kfree(best->data); 282 best = mthd; 283 } 284 } while ((++mthd)->shadow); 285 286 if (best->score) { 287 NV_TRACE(dev, "Using VBIOS from %s\n", best->desc); 288 bios->length = best->size; 289 bios->data = best->data; 290 return true; 291 } 292 293 NV_ERROR(dev, "No valid VBIOS image found\n"); 294 return false; 295} 296 297struct init_tbl_entry { 298 char *name; 299 uint8_t id; 300 /* Return: 301 * > 0: success, length of opcode 302 * 0: success, but abort further parsing of table (INIT_DONE etc) 303 * < 0: failure, table parsing will be aborted 304 */ 305 int (*handler)(struct nvbios *, uint16_t, struct init_exec *); 306}; 307 308static int parse_init_table(struct nvbios *, uint16_t, struct init_exec *); 309 310#define MACRO_INDEX_SIZE 2 311#define MACRO_SIZE 8 312#define CONDITION_SIZE 12 313#define IO_FLAG_CONDITION_SIZE 9 314#define IO_CONDITION_SIZE 5 315#define MEM_INIT_SIZE 66 316 317static void still_alive(void) 318{ 319#if 0 320 sync(); 321 mdelay(2); 322#endif 323} 324 325static uint32_t 326munge_reg(struct nvbios *bios, uint32_t reg) 327{ 328 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 329 struct dcb_entry *dcbent = bios->display.output; 330 331 if (dev_priv->card_type < NV_50) 332 return reg; 333 334 if (reg & 0x80000000) { 335 BUG_ON(bios->display.crtc < 0); 336 reg += bios->display.crtc * 0x800; 337 } 338 339 if (reg & 0x40000000) { 340 BUG_ON(!dcbent); 341 342 reg += (ffs(dcbent->or) - 1) * 0x800; 343 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1)) 344 reg += 0x00000080; 345 } 346 347 reg &= ~0xe0000000; 348 return reg; 349} 350 351static int 352valid_reg(struct nvbios *bios, uint32_t reg) 353{ 354 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 355 struct drm_device *dev = bios->dev; 356 357 /* C51 has misaligned regs on purpose. Marvellous */ 358 if (reg & 0x2 || 359 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51)) 360 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg); 361 362 /* warn on C51 regs that haven't been verified accessible in tracing */ 363 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 && 364 reg != 0x130d && reg != 0x1311 && reg != 0x60081d) 365 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n", 366 reg); 367 368 if (reg >= (8*1024*1024)) { 369 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg); 370 return 0; 371 } 372 373 return 1; 374} 375 376static bool 377valid_idx_port(struct nvbios *bios, uint16_t port) 378{ 379 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 380 struct drm_device *dev = bios->dev; 381 382 /* 383 * If adding more ports here, the read/write functions below will need 384 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is 385 * used for the port in question 386 */ 387 if (dev_priv->card_type < NV_50) { 388 if (port == NV_CIO_CRX__COLOR) 389 return true; 390 if (port == NV_VIO_SRX) 391 return true; 392 } else { 393 if (port == NV_CIO_CRX__COLOR) 394 return true; 395 } 396 397 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n", 398 port); 399 400 return false; 401} 402 403static bool 404valid_port(struct nvbios *bios, uint16_t port) 405{ 406 struct drm_device *dev = bios->dev; 407 408 /* 409 * If adding more ports here, the read/write functions below will need 410 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is 411 * used for the port in question 412 */ 413 if (port == NV_VIO_VSE2) 414 return true; 415 416 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port); 417 418 return false; 419} 420 421static uint32_t 422bios_rd32(struct nvbios *bios, uint32_t reg) 423{ 424 uint32_t data; 425 426 reg = munge_reg(bios, reg); 427 if (!valid_reg(bios, reg)) 428 return 0; 429 430 /* 431 * C51 sometimes uses regs with bit0 set in the address. For these 432 * cases there should exist a translation in a BIOS table to an IO 433 * port address which the BIOS uses for accessing the reg 434 * 435 * These only seem to appear for the power control regs to a flat panel, 436 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs 437 * for 0x1308 and 0x1310 are used - hence the mask below. An S3 438 * suspend-resume mmio trace from a C51 will be required to see if this 439 * is true for the power microcode in 0x14.., or whether the direct IO 440 * port access method is needed 441 */ 442 if (reg & 0x1) 443 reg &= ~0x1; 444 445 data = nv_rd32(bios->dev, reg); 446 447 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data); 448 449 return data; 450} 451 452static void 453bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data) 454{ 455 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 456 457 reg = munge_reg(bios, reg); 458 if (!valid_reg(bios, reg)) 459 return; 460 461 /* see note in bios_rd32 */ 462 if (reg & 0x1) 463 reg &= 0xfffffffe; 464 465 LOG_OLD_VALUE(bios_rd32(bios, reg)); 466 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data); 467 468 if (dev_priv->vbios.execute) { 469 still_alive(); 470 nv_wr32(bios->dev, reg, data); 471 } 472} 473 474static uint8_t 475bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index) 476{ 477 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 478 struct drm_device *dev = bios->dev; 479 uint8_t data; 480 481 if (!valid_idx_port(bios, port)) 482 return 0; 483 484 if (dev_priv->card_type < NV_50) { 485 if (port == NV_VIO_SRX) 486 data = NVReadVgaSeq(dev, bios->state.crtchead, index); 487 else /* assume NV_CIO_CRX__COLOR */ 488 data = NVReadVgaCrtc(dev, bios->state.crtchead, index); 489 } else { 490 uint32_t data32; 491 492 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3)); 493 data = (data32 >> ((index & 3) << 3)) & 0xff; 494 } 495 496 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, " 497 "Head: 0x%02X, Data: 0x%02X\n", 498 port, index, bios->state.crtchead, data); 499 return data; 500} 501 502static void 503bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data) 504{ 505 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 506 struct drm_device *dev = bios->dev; 507 508 if (!valid_idx_port(bios, port)) 509 return; 510 511 /* 512 * The current head is maintained in the nvbios member state.crtchead. 513 * We trap changes to CR44 and update the head variable and hence the 514 * register set written. 515 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance 516 * of the write, and to head1 after the write 517 */ 518 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 && 519 data != NV_CIO_CRE_44_HEADB) 520 bios->state.crtchead = 0; 521 522 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index)); 523 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, " 524 "Head: 0x%02X, Data: 0x%02X\n", 525 port, index, bios->state.crtchead, data); 526 527 if (bios->execute && dev_priv->card_type < NV_50) { 528 still_alive(); 529 if (port == NV_VIO_SRX) 530 NVWriteVgaSeq(dev, bios->state.crtchead, index, data); 531 else /* assume NV_CIO_CRX__COLOR */ 532 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data); 533 } else 534 if (bios->execute) { 535 uint32_t data32, shift = (index & 3) << 3; 536 537 still_alive(); 538 539 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3)); 540 data32 &= ~(0xff << shift); 541 data32 |= (data << shift); 542 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32); 543 } 544 545 if (port == NV_CIO_CRX__COLOR && 546 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB) 547 bios->state.crtchead = 1; 548} 549 550static uint8_t 551bios_port_rd(struct nvbios *bios, uint16_t port) 552{ 553 uint8_t data, head = bios->state.crtchead; 554 555 if (!valid_port(bios, port)) 556 return 0; 557 558 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port); 559 560 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n", 561 port, head, data); 562 563 return data; 564} 565 566static void 567bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data) 568{ 569 int head = bios->state.crtchead; 570 571 if (!valid_port(bios, port)) 572 return; 573 574 LOG_OLD_VALUE(bios_port_rd(bios, port)); 575 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n", 576 port, head, data); 577 578 if (!bios->execute) 579 return; 580 581 still_alive(); 582 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data); 583} 584 585static bool 586io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 587{ 588 /* 589 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte 590 * for the CRTC index; 1 byte for the mask to apply to the value 591 * retrieved from the CRTC; 1 byte for the shift right to apply to the 592 * masked CRTC value; 2 bytes for the offset to the flag array, to 593 * which the shifted value is added; 1 byte for the mask applied to the 594 * value read from the flag array; and 1 byte for the value to compare 595 * against the masked byte from the flag table. 596 */ 597 598 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE; 599 uint16_t crtcport = ROM16(bios->data[condptr]); 600 uint8_t crtcindex = bios->data[condptr + 2]; 601 uint8_t mask = bios->data[condptr + 3]; 602 uint8_t shift = bios->data[condptr + 4]; 603 uint16_t flagarray = ROM16(bios->data[condptr + 5]); 604 uint8_t flagarraymask = bios->data[condptr + 7]; 605 uint8_t cmpval = bios->data[condptr + 8]; 606 uint8_t data; 607 608 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 609 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, " 610 "Cmpval: 0x%02X\n", 611 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval); 612 613 data = bios_idxprt_rd(bios, crtcport, crtcindex); 614 615 data = bios->data[flagarray + ((data & mask) >> shift)]; 616 data &= flagarraymask; 617 618 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n", 619 offset, data, cmpval); 620 621 return (data == cmpval); 622} 623 624static bool 625bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 626{ 627 /* 628 * The condition table entry has 4 bytes for the address of the 629 * register to check, 4 bytes for a mask to apply to the register and 630 * 4 for a test comparison value 631 */ 632 633 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE; 634 uint32_t reg = ROM32(bios->data[condptr]); 635 uint32_t mask = ROM32(bios->data[condptr + 4]); 636 uint32_t cmpval = ROM32(bios->data[condptr + 8]); 637 uint32_t data; 638 639 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n", 640 offset, cond, reg, mask); 641 642 data = bios_rd32(bios, reg) & mask; 643 644 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n", 645 offset, data, cmpval); 646 647 return (data == cmpval); 648} 649 650static bool 651io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 652{ 653 /* 654 * The IO condition entry has 2 bytes for the IO port address; 1 byte 655 * for the index to write to io_port; 1 byte for the mask to apply to 656 * the byte read from io_port+1; and 1 byte for the value to compare 657 * against the masked byte. 658 */ 659 660 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE; 661 uint16_t io_port = ROM16(bios->data[condptr]); 662 uint8_t port_index = bios->data[condptr + 2]; 663 uint8_t mask = bios->data[condptr + 3]; 664 uint8_t cmpval = bios->data[condptr + 4]; 665 666 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask; 667 668 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n", 669 offset, data, cmpval); 670 671 return (data == cmpval); 672} 673 674static int 675nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk) 676{ 677 struct drm_nouveau_private *dev_priv = dev->dev_private; 678 struct nouveau_pll_vals pll; 679 struct pll_lims pll_limits; 680 u32 ctrl, mask, coef; 681 int ret; 682 683 ret = get_pll_limits(dev, reg, &pll_limits); 684 if (ret) 685 return ret; 686 687 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll); 688 if (!clk) 689 return -ERANGE; 690 691 coef = pll.N1 << 8 | pll.M1; 692 ctrl = pll.log2P << 16; 693 mask = 0x00070000; 694 if (reg == 0x004008) { 695 mask |= 0x01f80000; 696 ctrl |= (pll_limits.log2p_bias << 19); 697 ctrl |= (pll.log2P << 22); 698 } 699 700 if (!dev_priv->vbios.execute) 701 return 0; 702 703 nv_mask(dev, reg + 0, mask, ctrl); 704 nv_wr32(dev, reg + 4, coef); 705 return 0; 706} 707 708static int 709setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk) 710{ 711 struct drm_device *dev = bios->dev; 712 struct drm_nouveau_private *dev_priv = dev->dev_private; 713 /* clk in kHz */ 714 struct pll_lims pll_lim; 715 struct nouveau_pll_vals pllvals; 716 int ret; 717 718 if (dev_priv->card_type >= NV_50) 719 return nv50_pll_set(dev, reg, clk); 720 721 /* high regs (such as in the mac g5 table) are not -= 4 */ 722 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim); 723 if (ret) 724 return ret; 725 726 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals); 727 if (!clk) 728 return -ERANGE; 729 730 if (bios->execute) { 731 still_alive(); 732 nouveau_hw_setpll(dev, reg, &pllvals); 733 } 734 735 return 0; 736} 737 738static int dcb_entry_idx_from_crtchead(struct drm_device *dev) 739{ 740 struct drm_nouveau_private *dev_priv = dev->dev_private; 741 struct nvbios *bios = &dev_priv->vbios; 742 743 /* 744 * For the results of this function to be correct, CR44 must have been 745 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0, 746 * and the DCB table parsed, before the script calling the function is 747 * run. run_digital_op_script is example of how to do such setup 748 */ 749 750 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0); 751 752 if (dcb_entry > bios->dcb.entries) { 753 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently " 754 "(%02X)\n", dcb_entry); 755 dcb_entry = 0x7f; /* unused / invalid marker */ 756 } 757 758 return dcb_entry; 759} 760 761static struct nouveau_i2c_chan * 762init_i2c_device_find(struct drm_device *dev, int i2c_index) 763{ 764 if (i2c_index == 0xff) { 765 struct drm_nouveau_private *dev_priv = dev->dev_private; 766 struct dcb_table *dcb = &dev_priv->vbios.dcb; 767 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */ 768 int idx = dcb_entry_idx_from_crtchead(dev); 769 770 i2c_index = NV_I2C_DEFAULT(0); 771 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default) 772 i2c_index = NV_I2C_DEFAULT(1); 773 } 774 775 return nouveau_i2c_find(dev, i2c_index); 776} 777 778static uint32_t 779get_tmds_index_reg(struct drm_device *dev, uint8_t mlv) 780{ 781 /* 782 * For mlv < 0x80, it is an index into a table of TMDS base addresses. 783 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by 784 * CR58 for CR57 = 0 to index a table of offsets to the basic 785 * 0x6808b0 address. 786 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by 787 * CR58 for CR57 = 0 to index a table of offsets to the basic 788 * 0x6808b0 address, and then flip the offset by 8. 789 */ 790 791 struct drm_nouveau_private *dev_priv = dev->dev_private; 792 struct nvbios *bios = &dev_priv->vbios; 793 const int pramdac_offset[13] = { 794 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 }; 795 const uint32_t pramdac_table[4] = { 796 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 }; 797 798 if (mlv >= 0x80) { 799 int dcb_entry, dacoffset; 800 801 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */ 802 dcb_entry = dcb_entry_idx_from_crtchead(dev); 803 if (dcb_entry == 0x7f) 804 return 0; 805 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or]; 806 if (mlv == 0x81) 807 dacoffset ^= 8; 808 return 0x6808b0 + dacoffset; 809 } else { 810 if (mlv >= ARRAY_SIZE(pramdac_table)) { 811 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n", 812 mlv); 813 return 0; 814 } 815 return pramdac_table[mlv]; 816 } 817} 818 819static int 820init_io_restrict_prog(struct nvbios *bios, uint16_t offset, 821 struct init_exec *iexec) 822{ 823 /* 824 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2') 825 * 826 * offset (8 bit): opcode 827 * offset + 1 (16 bit): CRTC port 828 * offset + 3 (8 bit): CRTC index 829 * offset + 4 (8 bit): mask 830 * offset + 5 (8 bit): shift 831 * offset + 6 (8 bit): count 832 * offset + 7 (32 bit): register 833 * offset + 11 (32 bit): configuration 1 834 * ... 835 * 836 * Starting at offset + 11 there are "count" 32 bit values. 837 * To find out which value to use read index "CRTC index" on "CRTC 838 * port", AND this value with "mask" and then bit shift right "shift" 839 * bits. Read the appropriate value using this index and write to 840 * "register" 841 */ 842 843 uint16_t crtcport = ROM16(bios->data[offset + 1]); 844 uint8_t crtcindex = bios->data[offset + 3]; 845 uint8_t mask = bios->data[offset + 4]; 846 uint8_t shift = bios->data[offset + 5]; 847 uint8_t count = bios->data[offset + 6]; 848 uint32_t reg = ROM32(bios->data[offset + 7]); 849 uint8_t config; 850 uint32_t configval; 851 int len = 11 + count * 4; 852 853 if (!iexec->execute) 854 return len; 855 856 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 857 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n", 858 offset, crtcport, crtcindex, mask, shift, count, reg); 859 860 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 861 if (config > count) { 862 NV_ERROR(bios->dev, 863 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 864 offset, config, count); 865 return len; 866 } 867 868 configval = ROM32(bios->data[offset + 11 + config * 4]); 869 870 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config); 871 872 bios_wr32(bios, reg, configval); 873 874 return len; 875} 876 877static int 878init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 879{ 880 /* 881 * INIT_REPEAT opcode: 0x33 ('3') 882 * 883 * offset (8 bit): opcode 884 * offset + 1 (8 bit): count 885 * 886 * Execute script following this opcode up to INIT_REPEAT_END 887 * "count" times 888 */ 889 890 uint8_t count = bios->data[offset + 1]; 891 uint8_t i; 892 893 /* no iexec->execute check by design */ 894 895 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n", 896 offset, count); 897 898 iexec->repeat = true; 899 900 /* 901 * count - 1, as the script block will execute once when we leave this 902 * opcode -- this is compatible with bios behaviour as: 903 * a) the block is always executed at least once, even if count == 0 904 * b) the bios interpreter skips to the op following INIT_END_REPEAT, 905 * while we don't 906 */ 907 for (i = 0; i < count - 1; i++) 908 parse_init_table(bios, offset + 2, iexec); 909 910 iexec->repeat = false; 911 912 return 2; 913} 914 915static int 916init_io_restrict_pll(struct nvbios *bios, uint16_t offset, 917 struct init_exec *iexec) 918{ 919 /* 920 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4') 921 * 922 * offset (8 bit): opcode 923 * offset + 1 (16 bit): CRTC port 924 * offset + 3 (8 bit): CRTC index 925 * offset + 4 (8 bit): mask 926 * offset + 5 (8 bit): shift 927 * offset + 6 (8 bit): IO flag condition index 928 * offset + 7 (8 bit): count 929 * offset + 8 (32 bit): register 930 * offset + 12 (16 bit): frequency 1 931 * ... 932 * 933 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz). 934 * Set PLL register "register" to coefficients for frequency n, 935 * selected by reading index "CRTC index" of "CRTC port" ANDed with 936 * "mask" and shifted right by "shift". 937 * 938 * If "IO flag condition index" > 0, and condition met, double 939 * frequency before setting it. 940 */ 941 942 uint16_t crtcport = ROM16(bios->data[offset + 1]); 943 uint8_t crtcindex = bios->data[offset + 3]; 944 uint8_t mask = bios->data[offset + 4]; 945 uint8_t shift = bios->data[offset + 5]; 946 int8_t io_flag_condition_idx = bios->data[offset + 6]; 947 uint8_t count = bios->data[offset + 7]; 948 uint32_t reg = ROM32(bios->data[offset + 8]); 949 uint8_t config; 950 uint16_t freq; 951 int len = 12 + count * 2; 952 953 if (!iexec->execute) 954 return len; 955 956 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 957 "Shift: 0x%02X, IO Flag Condition: 0x%02X, " 958 "Count: 0x%02X, Reg: 0x%08X\n", 959 offset, crtcport, crtcindex, mask, shift, 960 io_flag_condition_idx, count, reg); 961 962 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 963 if (config > count) { 964 NV_ERROR(bios->dev, 965 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 966 offset, config, count); 967 return len; 968 } 969 970 freq = ROM16(bios->data[offset + 12 + config * 2]); 971 972 if (io_flag_condition_idx > 0) { 973 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) { 974 BIOSLOG(bios, "0x%04X: Condition fulfilled -- " 975 "frequency doubled\n", offset); 976 freq *= 2; 977 } else 978 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- " 979 "frequency unchanged\n", offset); 980 } 981 982 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n", 983 offset, reg, config, freq); 984 985 setPLL(bios, reg, freq * 10); 986 987 return len; 988} 989 990static int 991init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 992{ 993 /* 994 * INIT_END_REPEAT opcode: 0x36 ('6') 995 * 996 * offset (8 bit): opcode 997 * 998 * Marks the end of the block for INIT_REPEAT to repeat 999 */ 1000 1001 /* no iexec->execute check by design */ 1002 1003 /* 1004 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when 1005 * we're not in repeat mode 1006 */ 1007 if (iexec->repeat) 1008 return 0; 1009 1010 return 1; 1011} 1012 1013static int 1014init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1015{ 1016 /* 1017 * INIT_COPY opcode: 0x37 ('7') 1018 * 1019 * offset (8 bit): opcode 1020 * offset + 1 (32 bit): register 1021 * offset + 5 (8 bit): shift 1022 * offset + 6 (8 bit): srcmask 1023 * offset + 7 (16 bit): CRTC port 1024 * offset + 9 (8 bit): CRTC index 1025 * offset + 10 (8 bit): mask 1026 * 1027 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with 1028 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC 1029 * port 1030 */ 1031 1032 uint32_t reg = ROM32(bios->data[offset + 1]); 1033 uint8_t shift = bios->data[offset + 5]; 1034 uint8_t srcmask = bios->data[offset + 6]; 1035 uint16_t crtcport = ROM16(bios->data[offset + 7]); 1036 uint8_t crtcindex = bios->data[offset + 9]; 1037 uint8_t mask = bios->data[offset + 10]; 1038 uint32_t data; 1039 uint8_t crtcdata; 1040 1041 if (!iexec->execute) 1042 return 11; 1043 1044 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, " 1045 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n", 1046 offset, reg, shift, srcmask, crtcport, crtcindex, mask); 1047 1048 data = bios_rd32(bios, reg); 1049 1050 if (shift < 0x80) 1051 data >>= shift; 1052 else 1053 data <<= (0x100 - shift); 1054 1055 data &= srcmask; 1056 1057 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask; 1058 crtcdata |= (uint8_t)data; 1059 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata); 1060 1061 return 11; 1062} 1063 1064static int 1065init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1066{ 1067 /* 1068 * INIT_NOT opcode: 0x38 ('8') 1069 * 1070 * offset (8 bit): opcode 1071 * 1072 * Invert the current execute / no-execute condition (i.e. "else") 1073 */ 1074 if (iexec->execute) 1075 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset); 1076 else 1077 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset); 1078 1079 iexec->execute = !iexec->execute; 1080 return 1; 1081} 1082 1083static int 1084init_io_flag_condition(struct nvbios *bios, uint16_t offset, 1085 struct init_exec *iexec) 1086{ 1087 /* 1088 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9') 1089 * 1090 * offset (8 bit): opcode 1091 * offset + 1 (8 bit): condition number 1092 * 1093 * Check condition "condition number" in the IO flag condition table. 1094 * If condition not met skip subsequent opcodes until condition is 1095 * inverted (INIT_NOT), or we hit INIT_RESUME 1096 */ 1097 1098 uint8_t cond = bios->data[offset + 1]; 1099 1100 if (!iexec->execute) 1101 return 2; 1102 1103 if (io_flag_condition_met(bios, offset, cond)) 1104 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 1105 else { 1106 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 1107 iexec->execute = false; 1108 } 1109 1110 return 2; 1111} 1112 1113static int 1114init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1115{ 1116 /* 1117 * INIT_DP_CONDITION opcode: 0x3A ('') 1118 * 1119 * offset (8 bit): opcode 1120 * offset + 1 (8 bit): "sub" opcode 1121 * offset + 2 (8 bit): unknown 1122 * 1123 */ 1124 1125 struct dcb_entry *dcb = bios->display.output; 1126 struct drm_device *dev = bios->dev; 1127 uint8_t cond = bios->data[offset + 1]; 1128 uint8_t *table, *entry; 1129 1130 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond); 1131 1132 if (!iexec->execute) 1133 return 3; 1134 1135 table = nouveau_dp_bios_data(dev, dcb, &entry); 1136 if (!table) 1137 return 3; 1138 1139 switch (cond) { 1140 case 0: 1141 entry = dcb_conn(dev, dcb->connector); 1142 if (!entry || entry[0] != DCB_CONNECTOR_eDP) 1143 iexec->execute = false; 1144 break; 1145 case 1: 1146 case 2: 1147 if (!(entry[5] & cond)) 1148 iexec->execute = false; 1149 break; 1150 case 5: 1151 { 1152 struct nouveau_i2c_chan *auxch; 1153 int ret; 1154 1155 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index); 1156 if (!auxch) { 1157 NV_ERROR(dev, "0x%04X: couldn't get auxch\n", offset); 1158 return 3; 1159 } 1160 1161 ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1); 1162 if (ret) { 1163 NV_ERROR(dev, "0x%04X: auxch rd fail: %d\n", offset, ret); 1164 return 3; 1165 } 1166 1167 if (!(cond & 1)) 1168 iexec->execute = false; 1169 } 1170 break; 1171 default: 1172 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond); 1173 break; 1174 } 1175 1176 if (iexec->execute) 1177 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset); 1178 else 1179 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset); 1180 1181 return 3; 1182} 1183 1184static int 1185init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1186{ 1187 /* 1188 * INIT_3B opcode: 0x3B ('') 1189 * 1190 * offset (8 bit): opcode 1191 * offset + 1 (8 bit): crtc index 1192 * 1193 */ 1194 1195 uint8_t or = ffs(bios->display.output->or) - 1; 1196 uint8_t index = bios->data[offset + 1]; 1197 uint8_t data; 1198 1199 if (!iexec->execute) 1200 return 2; 1201 1202 data = bios_idxprt_rd(bios, 0x3d4, index); 1203 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or)); 1204 return 2; 1205} 1206 1207static int 1208init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1209{ 1210 /* 1211 * INIT_3C opcode: 0x3C ('') 1212 * 1213 * offset (8 bit): opcode 1214 * offset + 1 (8 bit): crtc index 1215 * 1216 */ 1217 1218 uint8_t or = ffs(bios->display.output->or) - 1; 1219 uint8_t index = bios->data[offset + 1]; 1220 uint8_t data; 1221 1222 if (!iexec->execute) 1223 return 2; 1224 1225 data = bios_idxprt_rd(bios, 0x3d4, index); 1226 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or)); 1227 return 2; 1228} 1229 1230static int 1231init_idx_addr_latched(struct nvbios *bios, uint16_t offset, 1232 struct init_exec *iexec) 1233{ 1234 /* 1235 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I') 1236 * 1237 * offset (8 bit): opcode 1238 * offset + 1 (32 bit): control register 1239 * offset + 5 (32 bit): data register 1240 * offset + 9 (32 bit): mask 1241 * offset + 13 (32 bit): data 1242 * offset + 17 (8 bit): count 1243 * offset + 18 (8 bit): address 1 1244 * offset + 19 (8 bit): data 1 1245 * ... 1246 * 1247 * For each of "count" address and data pairs, write "data n" to 1248 * "data register", read the current value of "control register", 1249 * and write it back once ANDed with "mask", ORed with "data", 1250 * and ORed with "address n" 1251 */ 1252 1253 uint32_t controlreg = ROM32(bios->data[offset + 1]); 1254 uint32_t datareg = ROM32(bios->data[offset + 5]); 1255 uint32_t mask = ROM32(bios->data[offset + 9]); 1256 uint32_t data = ROM32(bios->data[offset + 13]); 1257 uint8_t count = bios->data[offset + 17]; 1258 int len = 18 + count * 2; 1259 uint32_t value; 1260 int i; 1261 1262 if (!iexec->execute) 1263 return len; 1264 1265 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, " 1266 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n", 1267 offset, controlreg, datareg, mask, data, count); 1268 1269 for (i = 0; i < count; i++) { 1270 uint8_t instaddress = bios->data[offset + 18 + i * 2]; 1271 uint8_t instdata = bios->data[offset + 19 + i * 2]; 1272 1273 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n", 1274 offset, instaddress, instdata); 1275 1276 bios_wr32(bios, datareg, instdata); 1277 value = bios_rd32(bios, controlreg) & mask; 1278 value |= data; 1279 value |= instaddress; 1280 bios_wr32(bios, controlreg, value); 1281 } 1282 1283 return len; 1284} 1285 1286static int 1287init_io_restrict_pll2(struct nvbios *bios, uint16_t offset, 1288 struct init_exec *iexec) 1289{ 1290 /* 1291 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J') 1292 * 1293 * offset (8 bit): opcode 1294 * offset + 1 (16 bit): CRTC port 1295 * offset + 3 (8 bit): CRTC index 1296 * offset + 4 (8 bit): mask 1297 * offset + 5 (8 bit): shift 1298 * offset + 6 (8 bit): count 1299 * offset + 7 (32 bit): register 1300 * offset + 11 (32 bit): frequency 1 1301 * ... 1302 * 1303 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz). 1304 * Set PLL register "register" to coefficients for frequency n, 1305 * selected by reading index "CRTC index" of "CRTC port" ANDed with 1306 * "mask" and shifted right by "shift". 1307 */ 1308 1309 uint16_t crtcport = ROM16(bios->data[offset + 1]); 1310 uint8_t crtcindex = bios->data[offset + 3]; 1311 uint8_t mask = bios->data[offset + 4]; 1312 uint8_t shift = bios->data[offset + 5]; 1313 uint8_t count = bios->data[offset + 6]; 1314 uint32_t reg = ROM32(bios->data[offset + 7]); 1315 int len = 11 + count * 4; 1316 uint8_t config; 1317 uint32_t freq; 1318 1319 if (!iexec->execute) 1320 return len; 1321 1322 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 1323 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n", 1324 offset, crtcport, crtcindex, mask, shift, count, reg); 1325 1326 if (!reg) 1327 return len; 1328 1329 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 1330 if (config > count) { 1331 NV_ERROR(bios->dev, 1332 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 1333 offset, config, count); 1334 return len; 1335 } 1336 1337 freq = ROM32(bios->data[offset + 11 + config * 4]); 1338 1339 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n", 1340 offset, reg, config, freq); 1341 1342 setPLL(bios, reg, freq); 1343 1344 return len; 1345} 1346 1347static int 1348init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1349{ 1350 /* 1351 * INIT_PLL2 opcode: 0x4B ('K') 1352 * 1353 * offset (8 bit): opcode 1354 * offset + 1 (32 bit): register 1355 * offset + 5 (32 bit): freq 1356 * 1357 * Set PLL register "register" to coefficients for frequency "freq" 1358 */ 1359 1360 uint32_t reg = ROM32(bios->data[offset + 1]); 1361 uint32_t freq = ROM32(bios->data[offset + 5]); 1362 1363 if (!iexec->execute) 1364 return 9; 1365 1366 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n", 1367 offset, reg, freq); 1368 1369 setPLL(bios, reg, freq); 1370 return 9; 1371} 1372 1373static int 1374init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1375{ 1376 /* 1377 * INIT_I2C_BYTE opcode: 0x4C ('L') 1378 * 1379 * offset (8 bit): opcode 1380 * offset + 1 (8 bit): DCB I2C table entry index 1381 * offset + 2 (8 bit): I2C slave address 1382 * offset + 3 (8 bit): count 1383 * offset + 4 (8 bit): I2C register 1 1384 * offset + 5 (8 bit): mask 1 1385 * offset + 6 (8 bit): data 1 1386 * ... 1387 * 1388 * For each of "count" registers given by "I2C register n" on the device 1389 * addressed by "I2C slave address" on the I2C bus given by 1390 * "DCB I2C table entry index", read the register, AND the result with 1391 * "mask n" and OR it with "data n" before writing it back to the device 1392 */ 1393 1394 struct drm_device *dev = bios->dev; 1395 uint8_t i2c_index = bios->data[offset + 1]; 1396 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1397 uint8_t count = bios->data[offset + 3]; 1398 struct nouveau_i2c_chan *chan; 1399 int len = 4 + count * 3; 1400 int ret, i; 1401 1402 if (!iexec->execute) 1403 return len; 1404 1405 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1406 "Count: 0x%02X\n", 1407 offset, i2c_index, i2c_address, count); 1408 1409 chan = init_i2c_device_find(dev, i2c_index); 1410 if (!chan) { 1411 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset); 1412 return len; 1413 } 1414 1415 for (i = 0; i < count; i++) { 1416 uint8_t reg = bios->data[offset + 4 + i * 3]; 1417 uint8_t mask = bios->data[offset + 5 + i * 3]; 1418 uint8_t data = bios->data[offset + 6 + i * 3]; 1419 union i2c_smbus_data val; 1420 1421 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 1422 I2C_SMBUS_READ, reg, 1423 I2C_SMBUS_BYTE_DATA, &val); 1424 if (ret < 0) { 1425 NV_ERROR(dev, "0x%04X: i2c rd fail: %d\n", offset, ret); 1426 return len; 1427 } 1428 1429 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, " 1430 "Mask: 0x%02X, Data: 0x%02X\n", 1431 offset, reg, val.byte, mask, data); 1432 1433 if (!bios->execute) 1434 continue; 1435 1436 val.byte &= mask; 1437 val.byte |= data; 1438 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 1439 I2C_SMBUS_WRITE, reg, 1440 I2C_SMBUS_BYTE_DATA, &val); 1441 if (ret < 0) { 1442 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret); 1443 return len; 1444 } 1445 } 1446 1447 return len; 1448} 1449 1450static int 1451init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1452{ 1453 /* 1454 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M') 1455 * 1456 * offset (8 bit): opcode 1457 * offset + 1 (8 bit): DCB I2C table entry index 1458 * offset + 2 (8 bit): I2C slave address 1459 * offset + 3 (8 bit): count 1460 * offset + 4 (8 bit): I2C register 1 1461 * offset + 5 (8 bit): data 1 1462 * ... 1463 * 1464 * For each of "count" registers given by "I2C register n" on the device 1465 * addressed by "I2C slave address" on the I2C bus given by 1466 * "DCB I2C table entry index", set the register to "data n" 1467 */ 1468 1469 struct drm_device *dev = bios->dev; 1470 uint8_t i2c_index = bios->data[offset + 1]; 1471 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1472 uint8_t count = bios->data[offset + 3]; 1473 struct nouveau_i2c_chan *chan; 1474 int len = 4 + count * 2; 1475 int ret, i; 1476 1477 if (!iexec->execute) 1478 return len; 1479 1480 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1481 "Count: 0x%02X\n", 1482 offset, i2c_index, i2c_address, count); 1483 1484 chan = init_i2c_device_find(dev, i2c_index); 1485 if (!chan) { 1486 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset); 1487 return len; 1488 } 1489 1490 for (i = 0; i < count; i++) { 1491 uint8_t reg = bios->data[offset + 4 + i * 2]; 1492 union i2c_smbus_data val; 1493 1494 val.byte = bios->data[offset + 5 + i * 2]; 1495 1496 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n", 1497 offset, reg, val.byte); 1498 1499 if (!bios->execute) 1500 continue; 1501 1502 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 1503 I2C_SMBUS_WRITE, reg, 1504 I2C_SMBUS_BYTE_DATA, &val); 1505 if (ret < 0) { 1506 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret); 1507 return len; 1508 } 1509 } 1510 1511 return len; 1512} 1513 1514static int 1515init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1516{ 1517 /* 1518 * INIT_ZM_I2C opcode: 0x4E ('N') 1519 * 1520 * offset (8 bit): opcode 1521 * offset + 1 (8 bit): DCB I2C table entry index 1522 * offset + 2 (8 bit): I2C slave address 1523 * offset + 3 (8 bit): count 1524 * offset + 4 (8 bit): data 1 1525 * ... 1526 * 1527 * Send "count" bytes ("data n") to the device addressed by "I2C slave 1528 * address" on the I2C bus given by "DCB I2C table entry index" 1529 */ 1530 1531 struct drm_device *dev = bios->dev; 1532 uint8_t i2c_index = bios->data[offset + 1]; 1533 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1534 uint8_t count = bios->data[offset + 3]; 1535 int len = 4 + count; 1536 struct nouveau_i2c_chan *chan; 1537 struct i2c_msg msg; 1538 uint8_t data[256]; 1539 int ret, i; 1540 1541 if (!iexec->execute) 1542 return len; 1543 1544 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1545 "Count: 0x%02X\n", 1546 offset, i2c_index, i2c_address, count); 1547 1548 chan = init_i2c_device_find(dev, i2c_index); 1549 if (!chan) { 1550 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset); 1551 return len; 1552 } 1553 1554 for (i = 0; i < count; i++) { 1555 data[i] = bios->data[offset + 4 + i]; 1556 1557 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]); 1558 } 1559 1560 if (bios->execute) { 1561 msg.addr = i2c_address; 1562 msg.flags = 0; 1563 msg.len = count; 1564 msg.buf = data; 1565 ret = i2c_transfer(&chan->adapter, &msg, 1); 1566 if (ret != 1) { 1567 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret); 1568 return len; 1569 } 1570 } 1571 1572 return len; 1573} 1574 1575static int 1576init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1577{ 1578 /* 1579 * INIT_TMDS opcode: 0x4F ('O') (non-canon name) 1580 * 1581 * offset (8 bit): opcode 1582 * offset + 1 (8 bit): magic lookup value 1583 * offset + 2 (8 bit): TMDS address 1584 * offset + 3 (8 bit): mask 1585 * offset + 4 (8 bit): data 1586 * 1587 * Read the data reg for TMDS address "TMDS address", AND it with mask 1588 * and OR it with data, then write it back 1589 * "magic lookup value" determines which TMDS base address register is 1590 * used -- see get_tmds_index_reg() 1591 */ 1592 1593 struct drm_device *dev = bios->dev; 1594 uint8_t mlv = bios->data[offset + 1]; 1595 uint32_t tmdsaddr = bios->data[offset + 2]; 1596 uint8_t mask = bios->data[offset + 3]; 1597 uint8_t data = bios->data[offset + 4]; 1598 uint32_t reg, value; 1599 1600 if (!iexec->execute) 1601 return 5; 1602 1603 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, " 1604 "Mask: 0x%02X, Data: 0x%02X\n", 1605 offset, mlv, tmdsaddr, mask, data); 1606 1607 reg = get_tmds_index_reg(bios->dev, mlv); 1608 if (!reg) { 1609 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset); 1610 return 5; 1611 } 1612 1613 bios_wr32(bios, reg, 1614 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE); 1615 value = (bios_rd32(bios, reg + 4) & mask) | data; 1616 bios_wr32(bios, reg + 4, value); 1617 bios_wr32(bios, reg, tmdsaddr); 1618 1619 return 5; 1620} 1621 1622static int 1623init_zm_tmds_group(struct nvbios *bios, uint16_t offset, 1624 struct init_exec *iexec) 1625{ 1626 /* 1627 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name) 1628 * 1629 * offset (8 bit): opcode 1630 * offset + 1 (8 bit): magic lookup value 1631 * offset + 2 (8 bit): count 1632 * offset + 3 (8 bit): addr 1 1633 * offset + 4 (8 bit): data 1 1634 * ... 1635 * 1636 * For each of "count" TMDS address and data pairs write "data n" to 1637 * "addr n". "magic lookup value" determines which TMDS base address 1638 * register is used -- see get_tmds_index_reg() 1639 */ 1640 1641 struct drm_device *dev = bios->dev; 1642 uint8_t mlv = bios->data[offset + 1]; 1643 uint8_t count = bios->data[offset + 2]; 1644 int len = 3 + count * 2; 1645 uint32_t reg; 1646 int i; 1647 1648 if (!iexec->execute) 1649 return len; 1650 1651 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n", 1652 offset, mlv, count); 1653 1654 reg = get_tmds_index_reg(bios->dev, mlv); 1655 if (!reg) { 1656 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset); 1657 return len; 1658 } 1659 1660 for (i = 0; i < count; i++) { 1661 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2]; 1662 uint8_t tmdsdata = bios->data[offset + 4 + i * 2]; 1663 1664 bios_wr32(bios, reg + 4, tmdsdata); 1665 bios_wr32(bios, reg, tmdsaddr); 1666 } 1667 1668 return len; 1669} 1670 1671static int 1672init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset, 1673 struct init_exec *iexec) 1674{ 1675 /* 1676 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q') 1677 * 1678 * offset (8 bit): opcode 1679 * offset + 1 (8 bit): CRTC index1 1680 * offset + 2 (8 bit): CRTC index2 1681 * offset + 3 (8 bit): baseaddr 1682 * offset + 4 (8 bit): count 1683 * offset + 5 (8 bit): data 1 1684 * ... 1685 * 1686 * For each of "count" address and data pairs, write "baseaddr + n" to 1687 * "CRTC index1" and "data n" to "CRTC index2" 1688 * Once complete, restore initial value read from "CRTC index1" 1689 */ 1690 uint8_t crtcindex1 = bios->data[offset + 1]; 1691 uint8_t crtcindex2 = bios->data[offset + 2]; 1692 uint8_t baseaddr = bios->data[offset + 3]; 1693 uint8_t count = bios->data[offset + 4]; 1694 int len = 5 + count; 1695 uint8_t oldaddr, data; 1696 int i; 1697 1698 if (!iexec->execute) 1699 return len; 1700 1701 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, " 1702 "BaseAddr: 0x%02X, Count: 0x%02X\n", 1703 offset, crtcindex1, crtcindex2, baseaddr, count); 1704 1705 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1); 1706 1707 for (i = 0; i < count; i++) { 1708 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, 1709 baseaddr + i); 1710 data = bios->data[offset + 5 + i]; 1711 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data); 1712 } 1713 1714 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr); 1715 1716 return len; 1717} 1718 1719static int 1720init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1721{ 1722 /* 1723 * INIT_CR opcode: 0x52 ('R') 1724 * 1725 * offset (8 bit): opcode 1726 * offset + 1 (8 bit): CRTC index 1727 * offset + 2 (8 bit): mask 1728 * offset + 3 (8 bit): data 1729 * 1730 * Assign the value of at "CRTC index" ANDed with mask and ORed with 1731 * data back to "CRTC index" 1732 */ 1733 1734 uint8_t crtcindex = bios->data[offset + 1]; 1735 uint8_t mask = bios->data[offset + 2]; 1736 uint8_t data = bios->data[offset + 3]; 1737 uint8_t value; 1738 1739 if (!iexec->execute) 1740 return 4; 1741 1742 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n", 1743 offset, crtcindex, mask, data); 1744 1745 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask; 1746 value |= data; 1747 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value); 1748 1749 return 4; 1750} 1751 1752static int 1753init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1754{ 1755 /* 1756 * INIT_ZM_CR opcode: 0x53 ('S') 1757 * 1758 * offset (8 bit): opcode 1759 * offset + 1 (8 bit): CRTC index 1760 * offset + 2 (8 bit): value 1761 * 1762 * Assign "value" to CRTC register with index "CRTC index". 1763 */ 1764 1765 uint8_t crtcindex = ROM32(bios->data[offset + 1]); 1766 uint8_t data = bios->data[offset + 2]; 1767 1768 if (!iexec->execute) 1769 return 3; 1770 1771 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data); 1772 1773 return 3; 1774} 1775 1776static int 1777init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1778{ 1779 /* 1780 * INIT_ZM_CR_GROUP opcode: 0x54 ('T') 1781 * 1782 * offset (8 bit): opcode 1783 * offset + 1 (8 bit): count 1784 * offset + 2 (8 bit): CRTC index 1 1785 * offset + 3 (8 bit): value 1 1786 * ... 1787 * 1788 * For "count", assign "value n" to CRTC register with index 1789 * "CRTC index n". 1790 */ 1791 1792 uint8_t count = bios->data[offset + 1]; 1793 int len = 2 + count * 2; 1794 int i; 1795 1796 if (!iexec->execute) 1797 return len; 1798 1799 for (i = 0; i < count; i++) 1800 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec); 1801 1802 return len; 1803} 1804 1805static int 1806init_condition_time(struct nvbios *bios, uint16_t offset, 1807 struct init_exec *iexec) 1808{ 1809 /* 1810 * INIT_CONDITION_TIME opcode: 0x56 ('V') 1811 * 1812 * offset (8 bit): opcode 1813 * offset + 1 (8 bit): condition number 1814 * offset + 2 (8 bit): retries / 50 1815 * 1816 * Check condition "condition number" in the condition table. 1817 * Bios code then sleeps for 2ms if the condition is not met, and 1818 * repeats up to "retries" times, but on one C51 this has proved 1819 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do 1820 * this, and bail after "retries" times, or 2s, whichever is less. 1821 * If still not met after retries, clear execution flag for this table. 1822 */ 1823 1824 uint8_t cond = bios->data[offset + 1]; 1825 uint16_t retries = bios->data[offset + 2] * 50; 1826 unsigned cnt; 1827 1828 if (!iexec->execute) 1829 return 3; 1830 1831 if (retries > 100) 1832 retries = 100; 1833 1834 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n", 1835 offset, cond, retries); 1836 1837 if (!bios->execute) /* avoid 2s delays when "faking" execution */ 1838 retries = 1; 1839 1840 for (cnt = 0; cnt < retries; cnt++) { 1841 if (bios_condition_met(bios, offset, cond)) { 1842 BIOSLOG(bios, "0x%04X: Condition met, continuing\n", 1843 offset); 1844 break; 1845 } else { 1846 BIOSLOG(bios, "0x%04X: " 1847 "Condition not met, sleeping for 20ms\n", 1848 offset); 1849 mdelay(20); 1850 } 1851 } 1852 1853 if (!bios_condition_met(bios, offset, cond)) { 1854 NV_WARN(bios->dev, 1855 "0x%04X: Condition still not met after %dms, " 1856 "skipping following opcodes\n", offset, 20 * retries); 1857 iexec->execute = false; 1858 } 1859 1860 return 3; 1861} 1862 1863static int 1864init_ltime(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1865{ 1866 /* 1867 * INIT_LTIME opcode: 0x57 ('V') 1868 * 1869 * offset (8 bit): opcode 1870 * offset + 1 (16 bit): time 1871 * 1872 * Sleep for "time" milliseconds. 1873 */ 1874 1875 unsigned time = ROM16(bios->data[offset + 1]); 1876 1877 if (!iexec->execute) 1878 return 3; 1879 1880 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X milliseconds\n", 1881 offset, time); 1882 1883 mdelay(time); 1884 1885 return 3; 1886} 1887 1888static int 1889init_zm_reg_sequence(struct nvbios *bios, uint16_t offset, 1890 struct init_exec *iexec) 1891{ 1892 /* 1893 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X') 1894 * 1895 * offset (8 bit): opcode 1896 * offset + 1 (32 bit): base register 1897 * offset + 5 (8 bit): count 1898 * offset + 6 (32 bit): value 1 1899 * ... 1900 * 1901 * Starting at offset + 6 there are "count" 32 bit values. 1902 * For "count" iterations set "base register" + 4 * current_iteration 1903 * to "value current_iteration" 1904 */ 1905 1906 uint32_t basereg = ROM32(bios->data[offset + 1]); 1907 uint32_t count = bios->data[offset + 5]; 1908 int len = 6 + count * 4; 1909 int i; 1910 1911 if (!iexec->execute) 1912 return len; 1913 1914 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n", 1915 offset, basereg, count); 1916 1917 for (i = 0; i < count; i++) { 1918 uint32_t reg = basereg + i * 4; 1919 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]); 1920 1921 bios_wr32(bios, reg, data); 1922 } 1923 1924 return len; 1925} 1926 1927static int 1928init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1929{ 1930 /* 1931 * INIT_SUB_DIRECT opcode: 0x5B ('[') 1932 * 1933 * offset (8 bit): opcode 1934 * offset + 1 (16 bit): subroutine offset (in bios) 1935 * 1936 * Calls a subroutine that will execute commands until INIT_DONE 1937 * is found. 1938 */ 1939 1940 uint16_t sub_offset = ROM16(bios->data[offset + 1]); 1941 1942 if (!iexec->execute) 1943 return 3; 1944 1945 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n", 1946 offset, sub_offset); 1947 1948 parse_init_table(bios, sub_offset, iexec); 1949 1950 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset); 1951 1952 return 3; 1953} 1954 1955static int 1956init_jump(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1957{ 1958 /* 1959 * INIT_JUMP opcode: 0x5C ('\') 1960 * 1961 * offset (8 bit): opcode 1962 * offset + 1 (16 bit): offset (in bios) 1963 * 1964 * Continue execution of init table from 'offset' 1965 */ 1966 1967 uint16_t jmp_offset = ROM16(bios->data[offset + 1]); 1968 1969 if (!iexec->execute) 1970 return 3; 1971 1972 BIOSLOG(bios, "0x%04X: Jump to 0x%04X\n", offset, jmp_offset); 1973 return jmp_offset - offset; 1974} 1975 1976static int 1977init_i2c_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1978{ 1979 /* 1980 * INIT_I2C_IF opcode: 0x5E ('^') 1981 * 1982 * offset (8 bit): opcode 1983 * offset + 1 (8 bit): DCB I2C table entry index 1984 * offset + 2 (8 bit): I2C slave address 1985 * offset + 3 (8 bit): I2C register 1986 * offset + 4 (8 bit): mask 1987 * offset + 5 (8 bit): data 1988 * 1989 * Read the register given by "I2C register" on the device addressed 1990 * by "I2C slave address" on the I2C bus given by "DCB I2C table 1991 * entry index". Compare the result AND "mask" to "data". 1992 * If they're not equal, skip subsequent opcodes until condition is 1993 * inverted (INIT_NOT), or we hit INIT_RESUME 1994 */ 1995 1996 uint8_t i2c_index = bios->data[offset + 1]; 1997 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1998 uint8_t reg = bios->data[offset + 3]; 1999 uint8_t mask = bios->data[offset + 4]; 2000 uint8_t data = bios->data[offset + 5]; 2001 struct nouveau_i2c_chan *chan; 2002 union i2c_smbus_data val; 2003 int ret; 2004 2005 /* no execute check by design */ 2006 2007 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n", 2008 offset, i2c_index, i2c_address); 2009 2010 chan = init_i2c_device_find(bios->dev, i2c_index); 2011 if (!chan) 2012 return -ENODEV; 2013 2014 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 2015 I2C_SMBUS_READ, reg, 2016 I2C_SMBUS_BYTE_DATA, &val); 2017 if (ret < 0) { 2018 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: [no device], " 2019 "Mask: 0x%02X, Data: 0x%02X\n", 2020 offset, reg, mask, data); 2021 iexec->execute = 0; 2022 return 6; 2023 } 2024 2025 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, " 2026 "Mask: 0x%02X, Data: 0x%02X\n", 2027 offset, reg, val.byte, mask, data); 2028 2029 iexec->execute = ((val.byte & mask) == data); 2030 2031 return 6; 2032} 2033 2034static int 2035init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2036{ 2037 /* 2038 * INIT_COPY_NV_REG opcode: 0x5F ('_') 2039 * 2040 * offset (8 bit): opcode 2041 * offset + 1 (32 bit): src reg 2042 * offset + 5 (8 bit): shift 2043 * offset + 6 (32 bit): src mask 2044 * offset + 10 (32 bit): xor 2045 * offset + 14 (32 bit): dst reg 2046 * offset + 18 (32 bit): dst mask 2047 * 2048 * Shift REGVAL("src reg") right by (signed) "shift", AND result with 2049 * "src mask", then XOR with "xor". Write this OR'd with 2050 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg" 2051 */ 2052 2053 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1])); 2054 uint8_t shift = bios->data[offset + 5]; 2055 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6])); 2056 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10])); 2057 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14])); 2058 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18])); 2059 uint32_t srcvalue, dstvalue; 2060 2061 if (!iexec->execute) 2062 return 22; 2063 2064 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, " 2065 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n", 2066 offset, srcreg, shift, srcmask, xor, dstreg, dstmask); 2067 2068 srcvalue = bios_rd32(bios, srcreg); 2069 2070 if (shift < 0x80) 2071 srcvalue >>= shift; 2072 else 2073 srcvalue <<= (0x100 - shift); 2074 2075 srcvalue = (srcvalue & srcmask) ^ xor; 2076 2077 dstvalue = bios_rd32(bios, dstreg) & dstmask; 2078 2079 bios_wr32(bios, dstreg, dstvalue | srcvalue); 2080 2081 return 22; 2082} 2083 2084static int 2085init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2086{ 2087 /* 2088 * INIT_ZM_INDEX_IO opcode: 0x62 ('b') 2089 * 2090 * offset (8 bit): opcode 2091 * offset + 1 (16 bit): CRTC port 2092 * offset + 3 (8 bit): CRTC index 2093 * offset + 4 (8 bit): data 2094 * 2095 * Write "data" to index "CRTC index" of "CRTC port" 2096 */ 2097 uint16_t crtcport = ROM16(bios->data[offset + 1]); 2098 uint8_t crtcindex = bios->data[offset + 3]; 2099 uint8_t data = bios->data[offset + 4]; 2100 2101 if (!iexec->execute) 2102 return 5; 2103 2104 bios_idxprt_wr(bios, crtcport, crtcindex, data); 2105 2106 return 5; 2107} 2108 2109static inline void 2110bios_md32(struct nvbios *bios, uint32_t reg, 2111 uint32_t mask, uint32_t val) 2112{ 2113 bios_wr32(bios, reg, (bios_rd32(bios, reg) & ~mask) | val); 2114} 2115 2116static uint32_t 2117peek_fb(struct drm_device *dev, struct io_mapping *fb, 2118 uint32_t off) 2119{ 2120 uint32_t val = 0; 2121 2122 if (off < pci_resource_len(dev->pdev, 1)) { 2123 uint8_t __iomem *p = 2124 io_mapping_map_atomic_wc(fb, off & PAGE_MASK); 2125 2126 val = ioread32(p + (off & ~PAGE_MASK)); 2127 2128 io_mapping_unmap_atomic(p); 2129 } 2130 2131 return val; 2132} 2133 2134static void 2135poke_fb(struct drm_device *dev, struct io_mapping *fb, 2136 uint32_t off, uint32_t val) 2137{ 2138 if (off < pci_resource_len(dev->pdev, 1)) { 2139 uint8_t __iomem *p = 2140 io_mapping_map_atomic_wc(fb, off & PAGE_MASK); 2141 2142 iowrite32(val, p + (off & ~PAGE_MASK)); 2143 wmb(); 2144 2145 io_mapping_unmap_atomic(p); 2146 } 2147} 2148 2149static inline bool 2150read_back_fb(struct drm_device *dev, struct io_mapping *fb, 2151 uint32_t off, uint32_t val) 2152{ 2153 poke_fb(dev, fb, off, val); 2154 return val == peek_fb(dev, fb, off); 2155} 2156 2157static int 2158nv04_init_compute_mem(struct nvbios *bios) 2159{ 2160 struct drm_device *dev = bios->dev; 2161 uint32_t patt = 0xdeadbeef; 2162 struct io_mapping *fb; 2163 int i; 2164 2165 /* Map the framebuffer aperture */ 2166 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1), 2167 pci_resource_len(dev->pdev, 1)); 2168 if (!fb) 2169 return -ENOMEM; 2170 2171 /* Sequencer and refresh off */ 2172 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20); 2173 bios_md32(bios, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF); 2174 2175 bios_md32(bios, NV04_PFB_BOOT_0, ~0, 2176 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB | 2177 NV04_PFB_BOOT_0_RAM_WIDTH_128 | 2178 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT); 2179 2180 for (i = 0; i < 4; i++) 2181 poke_fb(dev, fb, 4 * i, patt); 2182 2183 poke_fb(dev, fb, 0x400000, patt + 1); 2184 2185 if (peek_fb(dev, fb, 0) == patt + 1) { 2186 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE, 2187 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT); 2188 bios_md32(bios, NV04_PFB_DEBUG_0, 2189 NV04_PFB_DEBUG_0_REFRESH_OFF, 0); 2190 2191 for (i = 0; i < 4; i++) 2192 poke_fb(dev, fb, 4 * i, patt); 2193 2194 if ((peek_fb(dev, fb, 0xc) & 0xffff) != (patt & 0xffff)) 2195 bios_md32(bios, NV04_PFB_BOOT_0, 2196 NV04_PFB_BOOT_0_RAM_WIDTH_128 | 2197 NV04_PFB_BOOT_0_RAM_AMOUNT, 2198 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 2199 2200 } else if ((peek_fb(dev, fb, 0xc) & 0xffff0000) != 2201 (patt & 0xffff0000)) { 2202 bios_md32(bios, NV04_PFB_BOOT_0, 2203 NV04_PFB_BOOT_0_RAM_WIDTH_128 | 2204 NV04_PFB_BOOT_0_RAM_AMOUNT, 2205 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); 2206 2207 } else if (peek_fb(dev, fb, 0) != patt) { 2208 if (read_back_fb(dev, fb, 0x800000, patt)) 2209 bios_md32(bios, NV04_PFB_BOOT_0, 2210 NV04_PFB_BOOT_0_RAM_AMOUNT, 2211 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 2212 else 2213 bios_md32(bios, NV04_PFB_BOOT_0, 2214 NV04_PFB_BOOT_0_RAM_AMOUNT, 2215 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); 2216 2217 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE, 2218 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT); 2219 2220 } else if (!read_back_fb(dev, fb, 0x800000, patt)) { 2221 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, 2222 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 2223 2224 } 2225 2226 /* Refresh on, sequencer on */ 2227 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0); 2228 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20); 2229 2230 io_mapping_free(fb); 2231 return 0; 2232} 2233 2234static const uint8_t * 2235nv05_memory_config(struct nvbios *bios) 2236{ 2237 /* Defaults for BIOSes lacking a memory config table */ 2238 static const uint8_t default_config_tab[][2] = { 2239 { 0x24, 0x00 }, 2240 { 0x28, 0x00 }, 2241 { 0x24, 0x01 }, 2242 { 0x1f, 0x00 }, 2243 { 0x0f, 0x00 }, 2244 { 0x17, 0x00 }, 2245 { 0x06, 0x00 }, 2246 { 0x00, 0x00 } 2247 }; 2248 int i = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 2249 NV_PEXTDEV_BOOT_0_RAMCFG) >> 2; 2250 2251 if (bios->legacy.mem_init_tbl_ptr) 2252 return &bios->data[bios->legacy.mem_init_tbl_ptr + 2 * i]; 2253 else 2254 return default_config_tab[i]; 2255} 2256 2257static int 2258nv05_init_compute_mem(struct nvbios *bios) 2259{ 2260 struct drm_device *dev = bios->dev; 2261 const uint8_t *ramcfg = nv05_memory_config(bios); 2262 uint32_t patt = 0xdeadbeef; 2263 struct io_mapping *fb; 2264 int i, v; 2265 2266 /* Map the framebuffer aperture */ 2267 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1), 2268 pci_resource_len(dev->pdev, 1)); 2269 if (!fb) 2270 return -ENOMEM; 2271 2272 /* Sequencer off */ 2273 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20); 2274 2275 if (bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE) 2276 goto out; 2277 2278 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0); 2279 2280 /* If present load the hardcoded scrambling table */ 2281 if (bios->legacy.mem_init_tbl_ptr) { 2282 uint32_t *scramble_tab = (uint32_t *)&bios->data[ 2283 bios->legacy.mem_init_tbl_ptr + 0x10]; 2284 2285 for (i = 0; i < 8; i++) 2286 bios_wr32(bios, NV04_PFB_SCRAMBLE(i), 2287 ROM32(scramble_tab[i])); 2288 } 2289 2290 /* Set memory type/width/length defaults depending on the straps */ 2291 bios_md32(bios, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]); 2292 2293 if (ramcfg[1] & 0x80) 2294 bios_md32(bios, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE); 2295 2296 bios_md32(bios, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20); 2297 bios_md32(bios, NV04_PFB_CFG1, 0, 1); 2298 2299 /* Probe memory bus width */ 2300 for (i = 0; i < 4; i++) 2301 poke_fb(dev, fb, 4 * i, patt); 2302 2303 if (peek_fb(dev, fb, 0xc) != patt) 2304 bios_md32(bios, NV04_PFB_BOOT_0, 2305 NV04_PFB_BOOT_0_RAM_WIDTH_128, 0); 2306 2307 /* Probe memory length */ 2308 v = bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT; 2309 2310 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB && 2311 (!read_back_fb(dev, fb, 0x1000000, ++patt) || 2312 !read_back_fb(dev, fb, 0, ++patt))) 2313 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, 2314 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB); 2315 2316 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB && 2317 !read_back_fb(dev, fb, 0x800000, ++patt)) 2318 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, 2319 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 2320 2321 if (!read_back_fb(dev, fb, 0x400000, ++patt)) 2322 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, 2323 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); 2324 2325out: 2326 /* Sequencer on */ 2327 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20); 2328 2329 io_mapping_free(fb); 2330 return 0; 2331} 2332 2333static int 2334nv10_init_compute_mem(struct nvbios *bios) 2335{ 2336 struct drm_device *dev = bios->dev; 2337 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2338 const int mem_width[] = { 0x10, 0x00, 0x20 }; 2339 const int mem_width_count = (dev_priv->chipset >= 0x17 ? 3 : 2); 2340 uint32_t patt = 0xdeadbeef; 2341 struct io_mapping *fb; 2342 int i, j, k; 2343 2344 /* Map the framebuffer aperture */ 2345 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1), 2346 pci_resource_len(dev->pdev, 1)); 2347 if (!fb) 2348 return -ENOMEM; 2349 2350 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1); 2351 2352 /* Probe memory bus width */ 2353 for (i = 0; i < mem_width_count; i++) { 2354 bios_md32(bios, NV04_PFB_CFG0, 0x30, mem_width[i]); 2355 2356 for (j = 0; j < 4; j++) { 2357 for (k = 0; k < 4; k++) 2358 poke_fb(dev, fb, 0x1c, 0); 2359 2360 poke_fb(dev, fb, 0x1c, patt); 2361 poke_fb(dev, fb, 0x3c, 0); 2362 2363 if (peek_fb(dev, fb, 0x1c) == patt) 2364 goto mem_width_found; 2365 } 2366 } 2367 2368mem_width_found: 2369 patt <<= 1; 2370 2371 /* Probe amount of installed memory */ 2372 for (i = 0; i < 4; i++) { 2373 int off = bios_rd32(bios, NV04_PFB_FIFO_DATA) - 0x100000; 2374 2375 poke_fb(dev, fb, off, patt); 2376 poke_fb(dev, fb, 0, 0); 2377 2378 peek_fb(dev, fb, 0); 2379 peek_fb(dev, fb, 0); 2380 peek_fb(dev, fb, 0); 2381 peek_fb(dev, fb, 0); 2382 2383 if (peek_fb(dev, fb, off) == patt) 2384 goto amount_found; 2385 } 2386 2387 /* IC missing - disable the upper half memory space. */ 2388 bios_md32(bios, NV04_PFB_CFG0, 0x1000, 0); 2389 2390amount_found: 2391 io_mapping_free(fb); 2392 return 0; 2393} 2394 2395static int 2396nv20_init_compute_mem(struct nvbios *bios) 2397{ 2398 struct drm_device *dev = bios->dev; 2399 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2400 uint32_t mask = (dev_priv->chipset >= 0x25 ? 0x300 : 0x900); 2401 uint32_t amount, off; 2402 struct io_mapping *fb; 2403 2404 /* Map the framebuffer aperture */ 2405 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1), 2406 pci_resource_len(dev->pdev, 1)); 2407 if (!fb) 2408 return -ENOMEM; 2409 2410 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1); 2411 2412 /* Allow full addressing */ 2413 bios_md32(bios, NV04_PFB_CFG0, 0, mask); 2414 2415 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA); 2416 for (off = amount; off > 0x2000000; off -= 0x2000000) 2417 poke_fb(dev, fb, off - 4, off); 2418 2419 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA); 2420 if (amount != peek_fb(dev, fb, amount - 4)) 2421 /* IC missing - disable the upper half memory space. */ 2422 bios_md32(bios, NV04_PFB_CFG0, mask, 0); 2423 2424 io_mapping_free(fb); 2425 return 0; 2426} 2427 2428static int 2429init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2430{ 2431 /* 2432 * INIT_COMPUTE_MEM opcode: 0x63 ('c') 2433 * 2434 * offset (8 bit): opcode 2435 * 2436 * This opcode is meant to set the PFB memory config registers 2437 * appropriately so that we can correctly calculate how much VRAM it 2438 * has (on nv10 and better chipsets the amount of installed VRAM is 2439 * subsequently reported in NV_PFB_CSTATUS (0x10020C)). 2440 * 2441 * The implementation of this opcode in general consists of several 2442 * parts: 2443 * 2444 * 1) Determination of memory type and density. Only necessary for 2445 * really old chipsets, the memory type reported by the strap bits 2446 * (0x101000) is assumed to be accurate on nv05 and newer. 2447 * 2448 * 2) Determination of the memory bus width. Usually done by a cunning 2449 * combination of writes to offsets 0x1c and 0x3c in the fb, and 2450 * seeing whether the written values are read back correctly. 2451 * 2452 * Only necessary on nv0x-nv1x and nv34, on the other cards we can 2453 * trust the straps. 2454 * 2455 * 3) Determination of how many of the card's RAM pads have ICs 2456 * attached, usually done by a cunning combination of writes to an 2457 * offset slightly less than the maximum memory reported by 2458 * NV_PFB_CSTATUS, then seeing if the test pattern can be read back. 2459 * 2460 * This appears to be a NOP on IGPs and NV4x or newer chipsets, both io 2461 * logs of the VBIOS and kmmio traces of the binary driver POSTing the 2462 * card show nothing being done for this opcode. Why is it still listed 2463 * in the table?! 2464 */ 2465 2466 /* no iexec->execute check by design */ 2467 2468 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2469 int ret; 2470 2471 if (dev_priv->chipset >= 0x40 || 2472 dev_priv->chipset == 0x1a || 2473 dev_priv->chipset == 0x1f) 2474 ret = 0; 2475 else if (dev_priv->chipset >= 0x20 && 2476 dev_priv->chipset != 0x34) 2477 ret = nv20_init_compute_mem(bios); 2478 else if (dev_priv->chipset >= 0x10) 2479 ret = nv10_init_compute_mem(bios); 2480 else if (dev_priv->chipset >= 0x5) 2481 ret = nv05_init_compute_mem(bios); 2482 else 2483 ret = nv04_init_compute_mem(bios); 2484 2485 if (ret) 2486 return ret; 2487 2488 return 1; 2489} 2490 2491static int 2492init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2493{ 2494 /* 2495 * INIT_RESET opcode: 0x65 ('e') 2496 * 2497 * offset (8 bit): opcode 2498 * offset + 1 (32 bit): register 2499 * offset + 5 (32 bit): value1 2500 * offset + 9 (32 bit): value2 2501 * 2502 * Assign "value1" to "register", then assign "value2" to "register" 2503 */ 2504 2505 uint32_t reg = ROM32(bios->data[offset + 1]); 2506 uint32_t value1 = ROM32(bios->data[offset + 5]); 2507 uint32_t value2 = ROM32(bios->data[offset + 9]); 2508 uint32_t pci_nv_19, pci_nv_20; 2509 2510 /* no iexec->execute check by design */ 2511 2512 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19); 2513 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19 & ~0xf00); 2514 2515 bios_wr32(bios, reg, value1); 2516 2517 udelay(10); 2518 2519 bios_wr32(bios, reg, value2); 2520 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19); 2521 2522 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20); 2523 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */ 2524 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20); 2525 2526 return 13; 2527} 2528 2529static int 2530init_configure_mem(struct nvbios *bios, uint16_t offset, 2531 struct init_exec *iexec) 2532{ 2533 /* 2534 * INIT_CONFIGURE_MEM opcode: 0x66 ('f') 2535 * 2536 * offset (8 bit): opcode 2537 * 2538 * Equivalent to INIT_DONE on bios version 3 or greater. 2539 * For early bios versions, sets up the memory registers, using values 2540 * taken from the memory init table 2541 */ 2542 2543 /* no iexec->execute check by design */ 2544 2545 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4); 2546 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6; 2547 uint32_t reg, data; 2548 2549 if (bios->major_version > 2) 2550 return 0; 2551 2552 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd( 2553 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20); 2554 2555 if (bios->data[meminitoffs] & 1) 2556 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr; 2557 2558 for (reg = ROM32(bios->data[seqtbloffs]); 2559 reg != 0xffffffff; 2560 reg = ROM32(bios->data[seqtbloffs += 4])) { 2561 2562 switch (reg) { 2563 case NV04_PFB_PRE: 2564 data = NV04_PFB_PRE_CMD_PRECHARGE; 2565 break; 2566 case NV04_PFB_PAD: 2567 data = NV04_PFB_PAD_CKE_NORMAL; 2568 break; 2569 case NV04_PFB_REF: 2570 data = NV04_PFB_REF_CMD_REFRESH; 2571 break; 2572 default: 2573 data = ROM32(bios->data[meminitdata]); 2574 meminitdata += 4; 2575 if (data == 0xffffffff) 2576 continue; 2577 } 2578 2579 bios_wr32(bios, reg, data); 2580 } 2581 2582 return 1; 2583} 2584 2585static int 2586init_configure_clk(struct nvbios *bios, uint16_t offset, 2587 struct init_exec *iexec) 2588{ 2589 /* 2590 * INIT_CONFIGURE_CLK opcode: 0x67 ('g') 2591 * 2592 * offset (8 bit): opcode 2593 * 2594 * Equivalent to INIT_DONE on bios version 3 or greater. 2595 * For early bios versions, sets up the NVClk and MClk PLLs, using 2596 * values taken from the memory init table 2597 */ 2598 2599 /* no iexec->execute check by design */ 2600 2601 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4); 2602 int clock; 2603 2604 if (bios->major_version > 2) 2605 return 0; 2606 2607 clock = ROM16(bios->data[meminitoffs + 4]) * 10; 2608 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock); 2609 2610 clock = ROM16(bios->data[meminitoffs + 2]) * 10; 2611 if (bios->data[meminitoffs] & 1) /* DDR */ 2612 clock *= 2; 2613 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock); 2614 2615 return 1; 2616} 2617 2618static int 2619init_configure_preinit(struct nvbios *bios, uint16_t offset, 2620 struct init_exec *iexec) 2621{ 2622 /* 2623 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h') 2624 * 2625 * offset (8 bit): opcode 2626 * 2627 * Equivalent to INIT_DONE on bios version 3 or greater. 2628 * For early bios versions, does early init, loading ram and crystal 2629 * configuration from straps into CR3C 2630 */ 2631 2632 /* no iexec->execute check by design */ 2633 2634 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0); 2635 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & 0x40) >> 6; 2636 2637 if (bios->major_version > 2) 2638 return 0; 2639 2640 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, 2641 NV_CIO_CRE_SCRATCH4__INDEX, cr3c); 2642 2643 return 1; 2644} 2645 2646static int 2647init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2648{ 2649 /* 2650 * INIT_IO opcode: 0x69 ('i') 2651 * 2652 * offset (8 bit): opcode 2653 * offset + 1 (16 bit): CRTC port 2654 * offset + 3 (8 bit): mask 2655 * offset + 4 (8 bit): data 2656 * 2657 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port" 2658 */ 2659 2660 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2661 uint16_t crtcport = ROM16(bios->data[offset + 1]); 2662 uint8_t mask = bios->data[offset + 3]; 2663 uint8_t data = bios->data[offset + 4]; 2664 2665 if (!iexec->execute) 2666 return 5; 2667 2668 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n", 2669 offset, crtcport, mask, data); 2670 2671 /* 2672 * I have no idea what this does, but NVIDIA do this magic sequence 2673 * in the places where this INIT_IO happens.. 2674 */ 2675 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) { 2676 int i; 2677 2678 bios_wr32(bios, 0x614100, (bios_rd32( 2679 bios, 0x614100) & 0x0fffffff) | 0x00800000); 2680 2681 bios_wr32(bios, 0x00e18c, bios_rd32( 2682 bios, 0x00e18c) | 0x00020000); 2683 2684 bios_wr32(bios, 0x614900, (bios_rd32( 2685 bios, 0x614900) & 0x0fffffff) | 0x00800000); 2686 2687 bios_wr32(bios, 0x000200, bios_rd32( 2688 bios, 0x000200) & ~0x40000000); 2689 2690 mdelay(10); 2691 2692 bios_wr32(bios, 0x00e18c, bios_rd32( 2693 bios, 0x00e18c) & ~0x00020000); 2694 2695 bios_wr32(bios, 0x000200, bios_rd32( 2696 bios, 0x000200) | 0x40000000); 2697 2698 bios_wr32(bios, 0x614100, 0x00800018); 2699 bios_wr32(bios, 0x614900, 0x00800018); 2700 2701 mdelay(10); 2702 2703 bios_wr32(bios, 0x614100, 0x10000018); 2704 bios_wr32(bios, 0x614900, 0x10000018); 2705 2706 for (i = 0; i < 3; i++) 2707 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32( 2708 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0); 2709 2710 for (i = 0; i < 2; i++) 2711 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32( 2712 bios, 0x614300 + (i*0x800)) & 0xfffff0f0); 2713 2714 for (i = 0; i < 3; i++) 2715 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32( 2716 bios, 0x614380 + (i*0x800)) & 0xfffff0f0); 2717 2718 for (i = 0; i < 2; i++) 2719 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32( 2720 bios, 0x614200 + (i*0x800)) & 0xfffffff0); 2721 2722 for (i = 0; i < 2; i++) 2723 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32( 2724 bios, 0x614108 + (i*0x800)) & 0x0fffffff); 2725 return 5; 2726 } 2727 2728 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) | 2729 data); 2730 return 5; 2731} 2732 2733static int 2734init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2735{ 2736 /* 2737 * INIT_SUB opcode: 0x6B ('k') 2738 * 2739 * offset (8 bit): opcode 2740 * offset + 1 (8 bit): script number 2741 * 2742 * Execute script number "script number", as a subroutine 2743 */ 2744 2745 uint8_t sub = bios->data[offset + 1]; 2746 2747 if (!iexec->execute) 2748 return 2; 2749 2750 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub); 2751 2752 parse_init_table(bios, 2753 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]), 2754 iexec); 2755 2756 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub); 2757 2758 return 2; 2759} 2760 2761static int 2762init_ram_condition(struct nvbios *bios, uint16_t offset, 2763 struct init_exec *iexec) 2764{ 2765 /* 2766 * INIT_RAM_CONDITION opcode: 0x6D ('m') 2767 * 2768 * offset (8 bit): opcode 2769 * offset + 1 (8 bit): mask 2770 * offset + 2 (8 bit): cmpval 2771 * 2772 * Test if (NV04_PFB_BOOT_0 & "mask") equals "cmpval". 2773 * If condition not met skip subsequent opcodes until condition is 2774 * inverted (INIT_NOT), or we hit INIT_RESUME 2775 */ 2776 2777 uint8_t mask = bios->data[offset + 1]; 2778 uint8_t cmpval = bios->data[offset + 2]; 2779 uint8_t data; 2780 2781 if (!iexec->execute) 2782 return 3; 2783 2784 data = bios_rd32(bios, NV04_PFB_BOOT_0) & mask; 2785 2786 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n", 2787 offset, data, cmpval); 2788 2789 if (data == cmpval) 2790 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 2791 else { 2792 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 2793 iexec->execute = false; 2794 } 2795 2796 return 3; 2797} 2798 2799static int 2800init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2801{ 2802 /* 2803 * INIT_NV_REG opcode: 0x6E ('n') 2804 * 2805 * offset (8 bit): opcode 2806 * offset + 1 (32 bit): register 2807 * offset + 5 (32 bit): mask 2808 * offset + 9 (32 bit): data 2809 * 2810 * Assign ((REGVAL("register") & "mask") | "data") to "register" 2811 */ 2812 2813 uint32_t reg = ROM32(bios->data[offset + 1]); 2814 uint32_t mask = ROM32(bios->data[offset + 5]); 2815 uint32_t data = ROM32(bios->data[offset + 9]); 2816 2817 if (!iexec->execute) 2818 return 13; 2819 2820 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n", 2821 offset, reg, mask, data); 2822 2823 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data); 2824 2825 return 13; 2826} 2827 2828static int 2829init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2830{ 2831 /* 2832 * INIT_MACRO opcode: 0x6F ('o') 2833 * 2834 * offset (8 bit): opcode 2835 * offset + 1 (8 bit): macro number 2836 * 2837 * Look up macro index "macro number" in the macro index table. 2838 * The macro index table entry has 1 byte for the index in the macro 2839 * table, and 1 byte for the number of times to repeat the macro. 2840 * The macro table entry has 4 bytes for the register address and 2841 * 4 bytes for the value to write to that register 2842 */ 2843 2844 uint8_t macro_index_tbl_idx = bios->data[offset + 1]; 2845 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE); 2846 uint8_t macro_tbl_idx = bios->data[tmp]; 2847 uint8_t count = bios->data[tmp + 1]; 2848 uint32_t reg, data; 2849 int i; 2850 2851 if (!iexec->execute) 2852 return 2; 2853 2854 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, " 2855 "Count: 0x%02X\n", 2856 offset, macro_index_tbl_idx, macro_tbl_idx, count); 2857 2858 for (i = 0; i < count; i++) { 2859 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE; 2860 2861 reg = ROM32(bios->data[macroentryptr]); 2862 data = ROM32(bios->data[macroentryptr + 4]); 2863 2864 bios_wr32(bios, reg, data); 2865 } 2866 2867 return 2; 2868} 2869 2870static int 2871init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2872{ 2873 /* 2874 * INIT_DONE opcode: 0x71 ('q') 2875 * 2876 * offset (8 bit): opcode 2877 * 2878 * End the current script 2879 */ 2880 2881 /* mild retval abuse to stop parsing this table */ 2882 return 0; 2883} 2884 2885static int 2886init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2887{ 2888 /* 2889 * INIT_RESUME opcode: 0x72 ('r') 2890 * 2891 * offset (8 bit): opcode 2892 * 2893 * End the current execute / no-execute condition 2894 */ 2895 2896 if (iexec->execute) 2897 return 1; 2898 2899 iexec->execute = true; 2900 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset); 2901 2902 return 1; 2903} 2904 2905static int 2906init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2907{ 2908 /* 2909 * INIT_TIME opcode: 0x74 ('t') 2910 * 2911 * offset (8 bit): opcode 2912 * offset + 1 (16 bit): time 2913 * 2914 * Sleep for "time" microseconds. 2915 */ 2916 2917 unsigned time = ROM16(bios->data[offset + 1]); 2918 2919 if (!iexec->execute) 2920 return 3; 2921 2922 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n", 2923 offset, time); 2924 2925 if (time < 1000) 2926 udelay(time); 2927 else 2928 mdelay((time + 900) / 1000); 2929 2930 return 3; 2931} 2932 2933static int 2934init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2935{ 2936 /* 2937 * INIT_CONDITION opcode: 0x75 ('u') 2938 * 2939 * offset (8 bit): opcode 2940 * offset + 1 (8 bit): condition number 2941 * 2942 * Check condition "condition number" in the condition table. 2943 * If condition not met skip subsequent opcodes until condition is 2944 * inverted (INIT_NOT), or we hit INIT_RESUME 2945 */ 2946 2947 uint8_t cond = bios->data[offset + 1]; 2948 2949 if (!iexec->execute) 2950 return 2; 2951 2952 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond); 2953 2954 if (bios_condition_met(bios, offset, cond)) 2955 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 2956 else { 2957 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 2958 iexec->execute = false; 2959 } 2960 2961 return 2; 2962} 2963 2964static int 2965init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2966{ 2967 /* 2968 * INIT_IO_CONDITION opcode: 0x76 2969 * 2970 * offset (8 bit): opcode 2971 * offset + 1 (8 bit): condition number 2972 * 2973 * Check condition "condition number" in the io condition table. 2974 * If condition not met skip subsequent opcodes until condition is 2975 * inverted (INIT_NOT), or we hit INIT_RESUME 2976 */ 2977 2978 uint8_t cond = bios->data[offset + 1]; 2979 2980 if (!iexec->execute) 2981 return 2; 2982 2983 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond); 2984 2985 if (io_condition_met(bios, offset, cond)) 2986 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 2987 else { 2988 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 2989 iexec->execute = false; 2990 } 2991 2992 return 2; 2993} 2994 2995static int 2996init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2997{ 2998 /* 2999 * INIT_INDEX_IO opcode: 0x78 ('x') 3000 * 3001 * offset (8 bit): opcode 3002 * offset + 1 (16 bit): CRTC port 3003 * offset + 3 (8 bit): CRTC index 3004 * offset + 4 (8 bit): mask 3005 * offset + 5 (8 bit): data 3006 * 3007 * Read value at index "CRTC index" on "CRTC port", AND with "mask", 3008 * OR with "data", write-back 3009 */ 3010 3011 uint16_t crtcport = ROM16(bios->data[offset + 1]); 3012 uint8_t crtcindex = bios->data[offset + 3]; 3013 uint8_t mask = bios->data[offset + 4]; 3014 uint8_t data = bios->data[offset + 5]; 3015 uint8_t value; 3016 3017 if (!iexec->execute) 3018 return 6; 3019 3020 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 3021 "Data: 0x%02X\n", 3022 offset, crtcport, crtcindex, mask, data); 3023 3024 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data; 3025 bios_idxprt_wr(bios, crtcport, crtcindex, value); 3026 3027 return 6; 3028} 3029 3030static int 3031init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3032{ 3033 /* 3034 * INIT_PLL opcode: 0x79 ('y') 3035 * 3036 * offset (8 bit): opcode 3037 * offset + 1 (32 bit): register 3038 * offset + 5 (16 bit): freq 3039 * 3040 * Set PLL register "register" to coefficients for frequency (10kHz) 3041 * "freq" 3042 */ 3043 3044 uint32_t reg = ROM32(bios->data[offset + 1]); 3045 uint16_t freq = ROM16(bios->data[offset + 5]); 3046 3047 if (!iexec->execute) 3048 return 7; 3049 3050 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq); 3051 3052 setPLL(bios, reg, freq * 10); 3053 3054 return 7; 3055} 3056 3057static int 3058init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3059{ 3060 /* 3061 * INIT_ZM_REG opcode: 0x7A ('z') 3062 * 3063 * offset (8 bit): opcode 3064 * offset + 1 (32 bit): register 3065 * offset + 5 (32 bit): value 3066 * 3067 * Assign "value" to "register" 3068 */ 3069 3070 uint32_t reg = ROM32(bios->data[offset + 1]); 3071 uint32_t value = ROM32(bios->data[offset + 5]); 3072 3073 if (!iexec->execute) 3074 return 9; 3075 3076 if (reg == 0x000200) 3077 value |= 1; 3078 3079 bios_wr32(bios, reg, value); 3080 3081 return 9; 3082} 3083 3084static int 3085init_ram_restrict_pll(struct nvbios *bios, uint16_t offset, 3086 struct init_exec *iexec) 3087{ 3088 /* 3089 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('') 3090 * 3091 * offset (8 bit): opcode 3092 * offset + 1 (8 bit): PLL type 3093 * offset + 2 (32 bit): frequency 0 3094 * 3095 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at 3096 * ram_restrict_table_ptr. The value read from there is used to select 3097 * a frequency from the table starting at 'frequency 0' to be 3098 * programmed into the PLL corresponding to 'type'. 3099 * 3100 * The PLL limits table on cards using this opcode has a mapping of 3101 * 'type' to the relevant registers. 3102 */ 3103 3104 struct drm_device *dev = bios->dev; 3105 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2; 3106 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap]; 3107 uint8_t type = bios->data[offset + 1]; 3108 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]); 3109 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry; 3110 int len = 2 + bios->ram_restrict_group_count * 4; 3111 int i; 3112 3113 if (!iexec->execute) 3114 return len; 3115 3116 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) { 3117 NV_ERROR(dev, "PLL limits table not version 3.x\n"); 3118 return len; /* deliberate, allow default clocks to remain */ 3119 } 3120 3121 entry = pll_limits + pll_limits[1]; 3122 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) { 3123 if (entry[0] == type) { 3124 uint32_t reg = ROM32(entry[3]); 3125 3126 BIOSLOG(bios, "0x%04X: " 3127 "Type %02x Reg 0x%08x Freq %dKHz\n", 3128 offset, type, reg, freq); 3129 3130 setPLL(bios, reg, freq); 3131 return len; 3132 } 3133 } 3134 3135 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type); 3136 return len; 3137} 3138 3139static int 3140init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3141{ 3142 /* 3143 * INIT_8C opcode: 0x8C ('') 3144 * 3145 * NOP so far.... 3146 * 3147 */ 3148 3149 return 1; 3150} 3151 3152static int 3153init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3154{ 3155 /* 3156 * INIT_8D opcode: 0x8D ('') 3157 * 3158 * NOP so far.... 3159 * 3160 */ 3161 3162 return 1; 3163} 3164 3165static int 3166init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3167{ 3168 /* 3169 * INIT_GPIO opcode: 0x8E ('') 3170 * 3171 * offset (8 bit): opcode 3172 * 3173 * Loop over all entries in the DCB GPIO table, and initialise 3174 * each GPIO according to various values listed in each entry 3175 */ 3176 3177 if (iexec->execute && bios->execute) 3178 nouveau_gpio_reset(bios->dev); 3179 3180 return 1; 3181} 3182 3183static int 3184init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset, 3185 struct init_exec *iexec) 3186{ 3187 /* 3188 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('') 3189 * 3190 * offset (8 bit): opcode 3191 * offset + 1 (32 bit): reg 3192 * offset + 5 (8 bit): regincrement 3193 * offset + 6 (8 bit): count 3194 * offset + 7 (32 bit): value 1,1 3195 * ... 3196 * 3197 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at 3198 * ram_restrict_table_ptr. The value read from here is 'n', and 3199 * "value 1,n" gets written to "reg". This repeats "count" times and on 3200 * each iteration 'm', "reg" increases by "regincrement" and 3201 * "value m,n" is used. The extent of n is limited by a number read 3202 * from the 'M' BIT table, herein called "blocklen" 3203 */ 3204 3205 uint32_t reg = ROM32(bios->data[offset + 1]); 3206 uint8_t regincrement = bios->data[offset + 5]; 3207 uint8_t count = bios->data[offset + 6]; 3208 uint32_t strap_ramcfg, data; 3209 /* previously set by 'M' BIT table */ 3210 uint16_t blocklen = bios->ram_restrict_group_count * 4; 3211 int len = 7 + count * blocklen; 3212 uint8_t index; 3213 int i; 3214 3215 /* critical! to know the length of the opcode */; 3216 if (!blocklen) { 3217 NV_ERROR(bios->dev, 3218 "0x%04X: Zero block length - has the M table " 3219 "been parsed?\n", offset); 3220 return -EINVAL; 3221 } 3222 3223 if (!iexec->execute) 3224 return len; 3225 3226 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf; 3227 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg]; 3228 3229 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, " 3230 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n", 3231 offset, reg, regincrement, count, strap_ramcfg, index); 3232 3233 for (i = 0; i < count; i++) { 3234 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]); 3235 3236 bios_wr32(bios, reg, data); 3237 3238 reg += regincrement; 3239 } 3240 3241 return len; 3242} 3243 3244static int 3245init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3246{ 3247 /* 3248 * INIT_COPY_ZM_REG opcode: 0x90 ('') 3249 * 3250 * offset (8 bit): opcode 3251 * offset + 1 (32 bit): src reg 3252 * offset + 5 (32 bit): dst reg 3253 * 3254 * Put contents of "src reg" into "dst reg" 3255 */ 3256 3257 uint32_t srcreg = ROM32(bios->data[offset + 1]); 3258 uint32_t dstreg = ROM32(bios->data[offset + 5]); 3259 3260 if (!iexec->execute) 3261 return 9; 3262 3263 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg)); 3264 3265 return 9; 3266} 3267 3268static int 3269init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset, 3270 struct init_exec *iexec) 3271{ 3272 /* 3273 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('') 3274 * 3275 * offset (8 bit): opcode 3276 * offset + 1 (32 bit): dst reg 3277 * offset + 5 (8 bit): count 3278 * offset + 6 (32 bit): data 1 3279 * ... 3280 * 3281 * For each of "count" values write "data n" to "dst reg" 3282 */ 3283 3284 uint32_t reg = ROM32(bios->data[offset + 1]); 3285 uint8_t count = bios->data[offset + 5]; 3286 int len = 6 + count * 4; 3287 int i; 3288 3289 if (!iexec->execute) 3290 return len; 3291 3292 for (i = 0; i < count; i++) { 3293 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]); 3294 bios_wr32(bios, reg, data); 3295 } 3296 3297 return len; 3298} 3299 3300static int 3301init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3302{ 3303 /* 3304 * INIT_RESERVED opcode: 0x92 ('') 3305 * 3306 * offset (8 bit): opcode 3307 * 3308 * Seemingly does nothing 3309 */ 3310 3311 return 1; 3312} 3313 3314static int 3315init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3316{ 3317 /* 3318 * INIT_96 opcode: 0x96 ('') 3319 * 3320 * offset (8 bit): opcode 3321 * offset + 1 (32 bit): sreg 3322 * offset + 5 (8 bit): sshift 3323 * offset + 6 (8 bit): smask 3324 * offset + 7 (8 bit): index 3325 * offset + 8 (32 bit): reg 3326 * offset + 12 (32 bit): mask 3327 * offset + 16 (8 bit): shift 3328 * 3329 */ 3330 3331 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2); 3332 uint32_t reg = ROM32(bios->data[offset + 8]); 3333 uint32_t mask = ROM32(bios->data[offset + 12]); 3334 uint32_t val; 3335 3336 val = bios_rd32(bios, ROM32(bios->data[offset + 1])); 3337 if (bios->data[offset + 5] < 0x80) 3338 val >>= bios->data[offset + 5]; 3339 else 3340 val <<= (0x100 - bios->data[offset + 5]); 3341 val &= bios->data[offset + 6]; 3342 3343 val = bios->data[ROM16(bios->data[xlatptr]) + val]; 3344 val <<= bios->data[offset + 16]; 3345 3346 if (!iexec->execute) 3347 return 17; 3348 3349 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val); 3350 return 17; 3351} 3352 3353static int 3354init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3355{ 3356 /* 3357 * INIT_97 opcode: 0x97 ('') 3358 * 3359 * offset (8 bit): opcode 3360 * offset + 1 (32 bit): register 3361 * offset + 5 (32 bit): mask 3362 * offset + 9 (32 bit): value 3363 * 3364 * Adds "value" to "register" preserving the fields specified 3365 * by "mask" 3366 */ 3367 3368 uint32_t reg = ROM32(bios->data[offset + 1]); 3369 uint32_t mask = ROM32(bios->data[offset + 5]); 3370 uint32_t add = ROM32(bios->data[offset + 9]); 3371 uint32_t val; 3372 3373 val = bios_rd32(bios, reg); 3374 val = (val & mask) | ((val + add) & ~mask); 3375 3376 if (!iexec->execute) 3377 return 13; 3378 3379 bios_wr32(bios, reg, val); 3380 return 13; 3381} 3382 3383static int 3384init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3385{ 3386 /* 3387 * INIT_AUXCH opcode: 0x98 ('') 3388 * 3389 * offset (8 bit): opcode 3390 * offset + 1 (32 bit): address 3391 * offset + 5 (8 bit): count 3392 * offset + 6 (8 bit): mask 0 3393 * offset + 7 (8 bit): data 0 3394 * ... 3395 * 3396 */ 3397 3398 struct drm_device *dev = bios->dev; 3399 struct nouveau_i2c_chan *auxch; 3400 uint32_t addr = ROM32(bios->data[offset + 1]); 3401 uint8_t count = bios->data[offset + 5]; 3402 int len = 6 + count * 2; 3403 int ret, i; 3404 3405 if (!bios->display.output) { 3406 NV_ERROR(dev, "INIT_AUXCH: no active output\n"); 3407 return len; 3408 } 3409 3410 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index); 3411 if (!auxch) { 3412 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n", 3413 bios->display.output->i2c_index); 3414 return len; 3415 } 3416 3417 if (!iexec->execute) 3418 return len; 3419 3420 offset += 6; 3421 for (i = 0; i < count; i++, offset += 2) { 3422 uint8_t data; 3423 3424 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1); 3425 if (ret) { 3426 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret); 3427 return len; 3428 } 3429 3430 data &= bios->data[offset + 0]; 3431 data |= bios->data[offset + 1]; 3432 3433 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1); 3434 if (ret) { 3435 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret); 3436 return len; 3437 } 3438 } 3439 3440 return len; 3441} 3442 3443static int 3444init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3445{ 3446 /* 3447 * INIT_ZM_AUXCH opcode: 0x99 ('') 3448 * 3449 * offset (8 bit): opcode 3450 * offset + 1 (32 bit): address 3451 * offset + 5 (8 bit): count 3452 * offset + 6 (8 bit): data 0 3453 * ... 3454 * 3455 */ 3456 3457 struct drm_device *dev = bios->dev; 3458 struct nouveau_i2c_chan *auxch; 3459 uint32_t addr = ROM32(bios->data[offset + 1]); 3460 uint8_t count = bios->data[offset + 5]; 3461 int len = 6 + count; 3462 int ret, i; 3463 3464 if (!bios->display.output) { 3465 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n"); 3466 return len; 3467 } 3468 3469 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index); 3470 if (!auxch) { 3471 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n", 3472 bios->display.output->i2c_index); 3473 return len; 3474 } 3475 3476 if (!iexec->execute) 3477 return len; 3478 3479 offset += 6; 3480 for (i = 0; i < count; i++, offset++) { 3481 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1); 3482 if (ret) { 3483 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret); 3484 return len; 3485 } 3486 } 3487 3488 return len; 3489} 3490 3491static int 3492init_i2c_long_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3493{ 3494 /* 3495 * INIT_I2C_LONG_IF opcode: 0x9A ('') 3496 * 3497 * offset (8 bit): opcode 3498 * offset + 1 (8 bit): DCB I2C table entry index 3499 * offset + 2 (8 bit): I2C slave address 3500 * offset + 3 (16 bit): I2C register 3501 * offset + 5 (8 bit): mask 3502 * offset + 6 (8 bit): data 3503 * 3504 * Read the register given by "I2C register" on the device addressed 3505 * by "I2C slave address" on the I2C bus given by "DCB I2C table 3506 * entry index". Compare the result AND "mask" to "data". 3507 * If they're not equal, skip subsequent opcodes until condition is 3508 * inverted (INIT_NOT), or we hit INIT_RESUME 3509 */ 3510 3511 uint8_t i2c_index = bios->data[offset + 1]; 3512 uint8_t i2c_address = bios->data[offset + 2] >> 1; 3513 uint8_t reglo = bios->data[offset + 3]; 3514 uint8_t reghi = bios->data[offset + 4]; 3515 uint8_t mask = bios->data[offset + 5]; 3516 uint8_t data = bios->data[offset + 6]; 3517 struct nouveau_i2c_chan *chan; 3518 uint8_t buf0[2] = { reghi, reglo }; 3519 uint8_t buf1[1]; 3520 struct i2c_msg msg[2] = { 3521 { i2c_address, 0, 1, buf0 }, 3522 { i2c_address, I2C_M_RD, 1, buf1 }, 3523 }; 3524 int ret; 3525 3526 /* no execute check by design */ 3527 3528 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n", 3529 offset, i2c_index, i2c_address); 3530 3531 chan = init_i2c_device_find(bios->dev, i2c_index); 3532 if (!chan) 3533 return -ENODEV; 3534 3535 3536 ret = i2c_transfer(&chan->adapter, msg, 2); 3537 if (ret < 0) { 3538 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: [no device], " 3539 "Mask: 0x%02X, Data: 0x%02X\n", 3540 offset, reghi, reglo, mask, data); 3541 iexec->execute = 0; 3542 return 7; 3543 } 3544 3545 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: 0x%02X, " 3546 "Mask: 0x%02X, Data: 0x%02X\n", 3547 offset, reghi, reglo, buf1[0], mask, data); 3548 3549 iexec->execute = ((buf1[0] & mask) == data); 3550 3551 return 7; 3552} 3553 3554static struct init_tbl_entry itbl_entry[] = { 3555 /* command name , id , length , offset , mult , command handler */ 3556 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */ 3557 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog }, 3558 { "INIT_REPEAT" , 0x33, init_repeat }, 3559 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll }, 3560 { "INIT_END_REPEAT" , 0x36, init_end_repeat }, 3561 { "INIT_COPY" , 0x37, init_copy }, 3562 { "INIT_NOT" , 0x38, init_not }, 3563 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition }, 3564 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition }, 3565 { "INIT_OP_3B" , 0x3B, init_op_3b }, 3566 { "INIT_OP_3C" , 0x3C, init_op_3c }, 3567 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched }, 3568 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 }, 3569 { "INIT_PLL2" , 0x4B, init_pll2 }, 3570 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte }, 3571 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte }, 3572 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c }, 3573 { "INIT_TMDS" , 0x4F, init_tmds }, 3574 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group }, 3575 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch }, 3576 { "INIT_CR" , 0x52, init_cr }, 3577 { "INIT_ZM_CR" , 0x53, init_zm_cr }, 3578 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group }, 3579 { "INIT_CONDITION_TIME" , 0x56, init_condition_time }, 3580 { "INIT_LTIME" , 0x57, init_ltime }, 3581 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence }, 3582 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */ 3583 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct }, 3584 { "INIT_JUMP" , 0x5C, init_jump }, 3585 { "INIT_I2C_IF" , 0x5E, init_i2c_if }, 3586 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg }, 3587 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io }, 3588 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem }, 3589 { "INIT_RESET" , 0x65, init_reset }, 3590 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem }, 3591 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk }, 3592 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit }, 3593 { "INIT_IO" , 0x69, init_io }, 3594 { "INIT_SUB" , 0x6B, init_sub }, 3595 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition }, 3596 { "INIT_NV_REG" , 0x6E, init_nv_reg }, 3597 { "INIT_MACRO" , 0x6F, init_macro }, 3598 { "INIT_DONE" , 0x71, init_done }, 3599 { "INIT_RESUME" , 0x72, init_resume }, 3600 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */ 3601 { "INIT_TIME" , 0x74, init_time }, 3602 { "INIT_CONDITION" , 0x75, init_condition }, 3603 { "INIT_IO_CONDITION" , 0x76, init_io_condition }, 3604 { "INIT_INDEX_IO" , 0x78, init_index_io }, 3605 { "INIT_PLL" , 0x79, init_pll }, 3606 { "INIT_ZM_REG" , 0x7A, init_zm_reg }, 3607 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll }, 3608 { "INIT_8C" , 0x8C, init_8c }, 3609 { "INIT_8D" , 0x8D, init_8d }, 3610 { "INIT_GPIO" , 0x8E, init_gpio }, 3611 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group }, 3612 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg }, 3613 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched }, 3614 { "INIT_RESERVED" , 0x92, init_reserved }, 3615 { "INIT_96" , 0x96, init_96 }, 3616 { "INIT_97" , 0x97, init_97 }, 3617 { "INIT_AUXCH" , 0x98, init_auxch }, 3618 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch }, 3619 { "INIT_I2C_LONG_IF" , 0x9A, init_i2c_long_if }, 3620 { NULL , 0 , NULL } 3621}; 3622 3623#define MAX_TABLE_OPS 1000 3624 3625static int 3626parse_init_table(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3627{ 3628 /* 3629 * Parses all commands in an init table. 3630 * 3631 * We start out executing all commands found in the init table. Some 3632 * opcodes may change the status of iexec->execute to SKIP, which will 3633 * cause the following opcodes to perform no operation until the value 3634 * is changed back to EXECUTE. 3635 */ 3636 3637 int count = 0, i, ret; 3638 uint8_t id; 3639 3640 /* catch NULL script pointers */ 3641 if (offset == 0) 3642 return 0; 3643 3644 /* 3645 * Loop until INIT_DONE causes us to break out of the loop 3646 * (or until offset > bios length just in case... ) 3647 * (and no more than MAX_TABLE_OPS iterations, just in case... ) 3648 */ 3649 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) { 3650 id = bios->data[offset]; 3651 3652 /* Find matching id in itbl_entry */ 3653 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++) 3654 ; 3655 3656 if (!itbl_entry[i].name) { 3657 NV_ERROR(bios->dev, 3658 "0x%04X: Init table command not found: " 3659 "0x%02X\n", offset, id); 3660 return -ENOENT; 3661 } 3662 3663 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset, 3664 itbl_entry[i].id, itbl_entry[i].name); 3665 3666 /* execute eventual command handler */ 3667 ret = (*itbl_entry[i].handler)(bios, offset, iexec); 3668 if (ret < 0) { 3669 NV_ERROR(bios->dev, "0x%04X: Failed parsing init " 3670 "table opcode: %s %d\n", offset, 3671 itbl_entry[i].name, ret); 3672 } 3673 3674 if (ret <= 0) 3675 break; 3676 3677 /* 3678 * Add the offset of the current command including all data 3679 * of that command. The offset will then be pointing on the 3680 * next op code. 3681 */ 3682 offset += ret; 3683 } 3684 3685 if (offset >= bios->length) 3686 NV_WARN(bios->dev, 3687 "Offset 0x%04X greater than known bios image length. " 3688 "Corrupt image?\n", offset); 3689 if (count >= MAX_TABLE_OPS) 3690 NV_WARN(bios->dev, 3691 "More than %d opcodes to a table is unlikely, " 3692 "is the bios image corrupt?\n", MAX_TABLE_OPS); 3693 3694 return 0; 3695} 3696 3697static void 3698parse_init_tables(struct nvbios *bios) 3699{ 3700 /* Loops and calls parse_init_table() for each present table. */ 3701 3702 int i = 0; 3703 uint16_t table; 3704 struct init_exec iexec = {true, false}; 3705 3706 if (bios->old_style_init) { 3707 if (bios->init_script_tbls_ptr) 3708 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec); 3709 if (bios->extra_init_script_tbl_ptr) 3710 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec); 3711 3712 return; 3713 } 3714 3715 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) { 3716 NV_INFO(bios->dev, 3717 "Parsing VBIOS init table %d at offset 0x%04X\n", 3718 i / 2, table); 3719 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table); 3720 3721 parse_init_table(bios, table, &iexec); 3722 i += 2; 3723 } 3724} 3725 3726static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk) 3727{ 3728 int compare_record_len, i = 0; 3729 uint16_t compareclk, scriptptr = 0; 3730 3731 if (bios->major_version < 5) /* pre BIT */ 3732 compare_record_len = 3; 3733 else 3734 compare_record_len = 4; 3735 3736 do { 3737 compareclk = ROM16(bios->data[clktable + compare_record_len * i]); 3738 if (pxclk >= compareclk * 10) { 3739 if (bios->major_version < 5) { 3740 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i]; 3741 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]); 3742 } else 3743 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]); 3744 break; 3745 } 3746 i++; 3747 } while (compareclk); 3748 3749 return scriptptr; 3750} 3751 3752static void 3753run_digital_op_script(struct drm_device *dev, uint16_t scriptptr, 3754 struct dcb_entry *dcbent, int head, bool dl) 3755{ 3756 struct drm_nouveau_private *dev_priv = dev->dev_private; 3757 struct nvbios *bios = &dev_priv->vbios; 3758 struct init_exec iexec = {true, false}; 3759 3760 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n", 3761 scriptptr); 3762 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44, 3763 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA); 3764 /* note: if dcb entries have been merged, index may be misleading */ 3765 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index); 3766 parse_init_table(bios, scriptptr, &iexec); 3767 3768 nv04_dfp_bind_head(dev, dcbent, head, dl); 3769} 3770 3771static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script) 3772{ 3773 struct drm_nouveau_private *dev_priv = dev->dev_private; 3774 struct nvbios *bios = &dev_priv->vbios; 3775 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0); 3776 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]); 3777 3778 if (!bios->fp.xlated_entry || !sub || !scriptofs) 3779 return -EINVAL; 3780 3781 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link); 3782 3783 if (script == LVDS_PANEL_OFF) { 3784 /* off-on delay in ms */ 3785 mdelay(ROM16(bios->data[bios->fp.xlated_entry + 7])); 3786 } 3787#ifdef __powerpc__ 3788 /* Powerbook specific quirks */ 3789 if (script == LVDS_RESET && 3790 (dev->pci_device == 0x0179 || dev->pci_device == 0x0189 || 3791 dev->pci_device == 0x0329)) 3792 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72); 3793#endif 3794 3795 return 0; 3796} 3797 3798static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk) 3799{ 3800 /* 3801 * The BIT LVDS table's header has the information to setup the 3802 * necessary registers. Following the standard 4 byte header are: 3803 * A bitmask byte and a dual-link transition pxclk value for use in 3804 * selecting the init script when not using straps; 4 script pointers 3805 * for panel power, selected by output and on/off; and 8 table pointers 3806 * for panel init, the needed one determined by output, and bits in the 3807 * conf byte. These tables are similar to the TMDS tables, consisting 3808 * of a list of pxclks and script pointers. 3809 */ 3810 struct drm_nouveau_private *dev_priv = dev->dev_private; 3811 struct nvbios *bios = &dev_priv->vbios; 3812 unsigned int outputset = (dcbent->or == 4) ? 1 : 0; 3813 uint16_t scriptptr = 0, clktable; 3814 3815 /* 3816 * For now we assume version 3.0 table - g80 support will need some 3817 * changes 3818 */ 3819 3820 switch (script) { 3821 case LVDS_INIT: 3822 return -ENOSYS; 3823 case LVDS_BACKLIGHT_ON: 3824 case LVDS_PANEL_ON: 3825 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]); 3826 break; 3827 case LVDS_BACKLIGHT_OFF: 3828 case LVDS_PANEL_OFF: 3829 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]); 3830 break; 3831 case LVDS_RESET: 3832 clktable = bios->fp.lvdsmanufacturerpointer + 15; 3833 if (dcbent->or == 4) 3834 clktable += 8; 3835 3836 if (dcbent->lvdsconf.use_straps_for_mode) { 3837 if (bios->fp.dual_link) 3838 clktable += 4; 3839 if (bios->fp.if_is_24bit) 3840 clktable += 2; 3841 } else { 3842 /* using EDID */ 3843 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1; 3844 3845 if (bios->fp.dual_link) { 3846 clktable += 4; 3847 cmpval_24bit <<= 1; 3848 } 3849 3850 if (bios->fp.strapless_is_24bit & cmpval_24bit) 3851 clktable += 2; 3852 } 3853 3854 clktable = ROM16(bios->data[clktable]); 3855 if (!clktable) { 3856 NV_ERROR(dev, "Pixel clock comparison table not found\n"); 3857 return -ENOENT; 3858 } 3859 scriptptr = clkcmptable(bios, clktable, pxclk); 3860 } 3861 3862 if (!scriptptr) { 3863 NV_ERROR(dev, "LVDS output init script not found\n"); 3864 return -ENOENT; 3865 } 3866 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link); 3867 3868 return 0; 3869} 3870 3871int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk) 3872{ 3873 /* 3874 * LVDS operations are multiplexed in an effort to present a single API 3875 * which works with two vastly differing underlying structures. 3876 * This acts as the demux 3877 */ 3878 3879 struct drm_nouveau_private *dev_priv = dev->dev_private; 3880 struct nvbios *bios = &dev_priv->vbios; 3881 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer]; 3882 uint32_t sel_clk_binding, sel_clk; 3883 int ret; 3884 3885 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver || 3886 (lvds_ver >= 0x30 && script == LVDS_INIT)) 3887 return 0; 3888 3889 if (!bios->fp.lvds_init_run) { 3890 bios->fp.lvds_init_run = true; 3891 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk); 3892 } 3893 3894 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change) 3895 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk); 3896 if (script == LVDS_RESET && bios->fp.power_off_for_reset) 3897 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk); 3898 3899 NV_TRACE(dev, "Calling LVDS script %d:\n", script); 3900 3901 /* don't let script change pll->head binding */ 3902 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000; 3903 3904 if (lvds_ver < 0x30) 3905 ret = call_lvds_manufacturer_script(dev, dcbent, head, script); 3906 else 3907 ret = run_lvds_table(dev, dcbent, head, script, pxclk); 3908 3909 bios->fp.last_script_invoc = (script << 1 | head); 3910 3911 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; 3912 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); 3913 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */ 3914 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0); 3915 3916 return ret; 3917} 3918 3919struct lvdstableheader { 3920 uint8_t lvds_ver, headerlen, recordlen; 3921}; 3922 3923static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth) 3924{ 3925 /* 3926 * BMP version (0xa) LVDS table has a simple header of version and 3927 * record length. The BIT LVDS table has the typical BIT table header: 3928 * version byte, header length byte, record length byte, and a byte for 3929 * the maximum number of records that can be held in the table. 3930 */ 3931 3932 uint8_t lvds_ver, headerlen, recordlen; 3933 3934 memset(lth, 0, sizeof(struct lvdstableheader)); 3935 3936 if (bios->fp.lvdsmanufacturerpointer == 0x0) { 3937 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n"); 3938 return -EINVAL; 3939 } 3940 3941 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer]; 3942 3943 switch (lvds_ver) { 3944 case 0x0a: /* pre NV40 */ 3945 headerlen = 2; 3946 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 3947 break; 3948 case 0x30: /* NV4x */ 3949 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 3950 if (headerlen < 0x1f) { 3951 NV_ERROR(dev, "LVDS table header not understood\n"); 3952 return -EINVAL; 3953 } 3954 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2]; 3955 break; 3956 case 0x40: /* G80/G90 */ 3957 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 3958 if (headerlen < 0x7) { 3959 NV_ERROR(dev, "LVDS table header not understood\n"); 3960 return -EINVAL; 3961 } 3962 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2]; 3963 break; 3964 default: 3965 NV_ERROR(dev, 3966 "LVDS table revision %d.%d not currently supported\n", 3967 lvds_ver >> 4, lvds_ver & 0xf); 3968 return -ENOSYS; 3969 } 3970 3971 lth->lvds_ver = lvds_ver; 3972 lth->headerlen = headerlen; 3973 lth->recordlen = recordlen; 3974 3975 return 0; 3976} 3977 3978static int 3979get_fp_strap(struct drm_device *dev, struct nvbios *bios) 3980{ 3981 struct drm_nouveau_private *dev_priv = dev->dev_private; 3982 3983 /* 3984 * The fp strap is normally dictated by the "User Strap" in 3985 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the 3986 * Internal_Flags struct at 0x48 is set, the user strap gets overriden 3987 * by the PCI subsystem ID during POST, but not before the previous user 3988 * strap has been committed to CR58 for CR57=0xf on head A, which may be 3989 * read and used instead 3990 */ 3991 3992 if (bios->major_version < 5 && bios->data[0x48] & 0x4) 3993 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf; 3994 3995 if (dev_priv->card_type >= NV_50) 3996 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf; 3997 else 3998 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf; 3999} 4000 4001static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios) 4002{ 4003 uint8_t *fptable; 4004 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex; 4005 int ret, ofs, fpstrapping; 4006 struct lvdstableheader lth; 4007 4008 if (bios->fp.fptablepointer == 0x0) { 4009 /* Apple cards don't have the fp table; the laptops use DDC */ 4010 /* The table is also missing on some x86 IGPs */ 4011#ifndef __powerpc__ 4012 NV_ERROR(dev, "Pointer to flat panel table invalid\n"); 4013#endif 4014 bios->digital_min_front_porch = 0x4b; 4015 return 0; 4016 } 4017 4018 fptable = &bios->data[bios->fp.fptablepointer]; 4019 fptable_ver = fptable[0]; 4020 4021 switch (fptable_ver) { 4022 /* 4023 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no 4024 * version field, and miss one of the spread spectrum/PWM bytes. 4025 * This could affect early GF2Go parts (not seen any appropriate ROMs 4026 * though). Here we assume that a version of 0x05 matches this case 4027 * (combining with a BMP version check would be better), as the 4028 * common case for the panel type field is 0x0005, and that is in 4029 * fact what we are reading the first byte of. 4030 */ 4031 case 0x05: /* some NV10, 11, 15, 16 */ 4032 recordlen = 42; 4033 ofs = -1; 4034 break; 4035 case 0x10: /* some NV15/16, and NV11+ */ 4036 recordlen = 44; 4037 ofs = 0; 4038 break; 4039 case 0x20: /* NV40+ */ 4040 headerlen = fptable[1]; 4041 recordlen = fptable[2]; 4042 fpentries = fptable[3]; 4043 /* 4044 * fptable[4] is the minimum 4045 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap 4046 */ 4047 bios->digital_min_front_porch = fptable[4]; 4048 ofs = -7; 4049 break; 4050 default: 4051 NV_ERROR(dev, 4052 "FP table revision %d.%d not currently supported\n", 4053 fptable_ver >> 4, fptable_ver & 0xf); 4054 return -ENOSYS; 4055 } 4056 4057 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */ 4058 return 0; 4059 4060 ret = parse_lvds_manufacturer_table_header(dev, bios, <h); 4061 if (ret) 4062 return ret; 4063 4064 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) { 4065 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer + 4066 lth.headerlen + 1; 4067 bios->fp.xlatwidth = lth.recordlen; 4068 } 4069 if (bios->fp.fpxlatetableptr == 0x0) { 4070 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n"); 4071 return -EINVAL; 4072 } 4073 4074 fpstrapping = get_fp_strap(dev, bios); 4075 4076 fpindex = bios->data[bios->fp.fpxlatetableptr + 4077 fpstrapping * bios->fp.xlatwidth]; 4078 4079 if (fpindex > fpentries) { 4080 NV_ERROR(dev, "Bad flat panel table index\n"); 4081 return -ENOENT; 4082 } 4083 4084 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */ 4085 if (lth.lvds_ver > 0x10) 4086 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf; 4087 4088 /* 4089 * If either the strap or xlated fpindex value are 0xf there is no 4090 * panel using a strap-derived bios mode present. this condition 4091 * includes, but is different from, the DDC panel indicator above 4092 */ 4093 if (fpstrapping == 0xf || fpindex == 0xf) 4094 return 0; 4095 4096 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen + 4097 recordlen * fpindex + ofs; 4098 4099 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n", 4100 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1, 4101 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1, 4102 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10); 4103 4104 return 0; 4105} 4106 4107bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode) 4108{ 4109 struct drm_nouveau_private *dev_priv = dev->dev_private; 4110 struct nvbios *bios = &dev_priv->vbios; 4111 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr]; 4112 4113 if (!mode) /* just checking whether we can produce a mode */ 4114 return bios->fp.mode_ptr; 4115 4116 memset(mode, 0, sizeof(struct drm_display_mode)); 4117 /* 4118 * For version 1.0 (version in byte 0): 4119 * bytes 1-2 are "panel type", including bits on whether Colour/mono, 4120 * single/dual link, and type (TFT etc.) 4121 * bytes 3-6 are bits per colour in RGBX 4122 */ 4123 mode->clock = ROM16(mode_entry[7]) * 10; 4124 /* bytes 9-10 is HActive */ 4125 mode->hdisplay = ROM16(mode_entry[11]) + 1; 4126 /* 4127 * bytes 13-14 is HValid Start 4128 * bytes 15-16 is HValid End 4129 */ 4130 mode->hsync_start = ROM16(mode_entry[17]) + 1; 4131 mode->hsync_end = ROM16(mode_entry[19]) + 1; 4132 mode->htotal = ROM16(mode_entry[21]) + 1; 4133 /* bytes 23-24, 27-30 similarly, but vertical */ 4134 mode->vdisplay = ROM16(mode_entry[25]) + 1; 4135 mode->vsync_start = ROM16(mode_entry[31]) + 1; 4136 mode->vsync_end = ROM16(mode_entry[33]) + 1; 4137 mode->vtotal = ROM16(mode_entry[35]) + 1; 4138 mode->flags |= (mode_entry[37] & 0x10) ? 4139 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4140 mode->flags |= (mode_entry[37] & 0x1) ? 4141 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4142 /* 4143 * bytes 38-39 relate to spread spectrum settings 4144 * bytes 40-43 are something to do with PWM 4145 */ 4146 4147 mode->status = MODE_OK; 4148 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; 4149 drm_mode_set_name(mode); 4150 return bios->fp.mode_ptr; 4151} 4152 4153int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit) 4154{ 4155 /* 4156 * The LVDS table header is (mostly) described in 4157 * parse_lvds_manufacturer_table_header(): the BIT header additionally 4158 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if 4159 * straps are not being used for the panel, this specifies the frequency 4160 * at which modes should be set up in the dual link style. 4161 * 4162 * Following the header, the BMP (ver 0xa) table has several records, 4163 * indexed by a separate xlat table, indexed in turn by the fp strap in 4164 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script 4165 * numbers for use by INIT_SUB which controlled panel init and power, 4166 * and finally a dword of ms to sleep between power off and on 4167 * operations. 4168 * 4169 * In the BIT versions, the table following the header serves as an 4170 * integrated config and xlat table: the records in the table are 4171 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has 4172 * two bytes - the first as a config byte, the second for indexing the 4173 * fp mode table pointed to by the BIT 'D' table 4174 * 4175 * DDC is not used until after card init, so selecting the correct table 4176 * entry and setting the dual link flag for EDID equipped panels, 4177 * requiring tests against the native-mode pixel clock, cannot be done 4178 * until later, when this function should be called with non-zero pxclk 4179 */ 4180 struct drm_nouveau_private *dev_priv = dev->dev_private; 4181 struct nvbios *bios = &dev_priv->vbios; 4182 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0; 4183 struct lvdstableheader lth; 4184 uint16_t lvdsofs; 4185 int ret, chip_version = bios->chip_version; 4186 4187 ret = parse_lvds_manufacturer_table_header(dev, bios, <h); 4188 if (ret) 4189 return ret; 4190 4191 switch (lth.lvds_ver) { 4192 case 0x0a: /* pre NV40 */ 4193 lvdsmanufacturerindex = bios->data[ 4194 bios->fp.fpxlatemanufacturertableptr + 4195 fpstrapping]; 4196 4197 /* we're done if this isn't the EDID panel case */ 4198 if (!pxclk) 4199 break; 4200 4201 if (chip_version < 0x25) { 4202 /* nv17 behaviour 4203 * 4204 * It seems the old style lvds script pointer is reused 4205 * to select 18/24 bit colour depth for EDID panels. 4206 */ 4207 lvdsmanufacturerindex = 4208 (bios->legacy.lvds_single_a_script_ptr & 1) ? 4209 2 : 0; 4210 if (pxclk >= bios->fp.duallink_transition_clk) 4211 lvdsmanufacturerindex++; 4212 } else if (chip_version < 0x30) { 4213 /* nv28 behaviour (off-chip encoder) 4214 * 4215 * nv28 does a complex dance of first using byte 121 of 4216 * the EDID to choose the lvdsmanufacturerindex, then 4217 * later attempting to match the EDID manufacturer and 4218 * product IDs in a table (signature 'pidt' (panel id 4219 * table?)), setting an lvdsmanufacturerindex of 0 and 4220 * an fp strap of the match index (or 0xf if none) 4221 */ 4222 lvdsmanufacturerindex = 0; 4223 } else { 4224 /* nv31, nv34 behaviour */ 4225 lvdsmanufacturerindex = 0; 4226 if (pxclk >= bios->fp.duallink_transition_clk) 4227 lvdsmanufacturerindex = 2; 4228 if (pxclk >= 140000) 4229 lvdsmanufacturerindex = 3; 4230 } 4231 4232 /* 4233 * nvidia set the high nibble of (cr57=f, cr58) to 4234 * lvdsmanufacturerindex in this case; we don't 4235 */ 4236 break; 4237 case 0x30: /* NV4x */ 4238 case 0x40: /* G80/G90 */ 4239 lvdsmanufacturerindex = fpstrapping; 4240 break; 4241 default: 4242 NV_ERROR(dev, "LVDS table revision not currently supported\n"); 4243 return -ENOSYS; 4244 } 4245 4246 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex; 4247 switch (lth.lvds_ver) { 4248 case 0x0a: 4249 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1; 4250 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2; 4251 bios->fp.dual_link = bios->data[lvdsofs] & 4; 4252 bios->fp.link_c_increment = bios->data[lvdsofs] & 8; 4253 *if_is_24bit = bios->data[lvdsofs] & 16; 4254 break; 4255 case 0x30: 4256 case 0x40: 4257 /* 4258 * No sign of the "power off for reset" or "reset for panel 4259 * on" bits, but it's safer to assume we should 4260 */ 4261 bios->fp.power_off_for_reset = true; 4262 bios->fp.reset_after_pclk_change = true; 4263 4264 /* 4265 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is 4266 * over-written, and if_is_24bit isn't used 4267 */ 4268 bios->fp.dual_link = bios->data[lvdsofs] & 1; 4269 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2; 4270 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4]; 4271 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10; 4272 break; 4273 } 4274 4275 /* set dual_link flag for EDID case */ 4276 if (pxclk && (chip_version < 0x25 || chip_version > 0x28)) 4277 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk); 4278 4279 *dl = bios->fp.dual_link; 4280 4281 return 0; 4282} 4283 4284/* BIT 'U'/'d' table encoder subtables have hashes matching them to 4285 * a particular set of encoders. 4286 * 4287 * This function returns true if a particular DCB entry matches. 4288 */ 4289bool 4290bios_encoder_match(struct dcb_entry *dcb, u32 hash) 4291{ 4292 if ((hash & 0x000000f0) != (dcb->location << 4)) 4293 return false; 4294 if ((hash & 0x0000000f) != dcb->type) 4295 return false; 4296 if (!(hash & (dcb->or << 16))) 4297 return false; 4298 4299 switch (dcb->type) { 4300 case OUTPUT_TMDS: 4301 case OUTPUT_LVDS: 4302 case OUTPUT_DP: 4303 if (hash & 0x00c00000) { 4304 if (!(hash & (dcb->sorconf.link << 22))) 4305 return false; 4306 } 4307 default: 4308 return true; 4309 } 4310} 4311 4312int 4313nouveau_bios_run_display_table(struct drm_device *dev, u16 type, int pclk, 4314 struct dcb_entry *dcbent, int crtc) 4315{ 4316 /* 4317 * The display script table is located by the BIT 'U' table. 4318 * 4319 * It contains an array of pointers to various tables describing 4320 * a particular output type. The first 32-bits of the output 4321 * tables contains similar information to a DCB entry, and is 4322 * used to decide whether that particular table is suitable for 4323 * the output you want to access. 4324 * 4325 * The "record header length" field here seems to indicate the 4326 * offset of the first configuration entry in the output tables. 4327 * This is 10 on most cards I've seen, but 12 has been witnessed 4328 * on DP cards, and there's another script pointer within the 4329 * header. 4330 * 4331 * offset + 0 ( 8 bits): version 4332 * offset + 1 ( 8 bits): header length 4333 * offset + 2 ( 8 bits): record length 4334 * offset + 3 ( 8 bits): number of records 4335 * offset + 4 ( 8 bits): record header length 4336 * offset + 5 (16 bits): pointer to first output script table 4337 */ 4338 4339 struct drm_nouveau_private *dev_priv = dev->dev_private; 4340 struct nvbios *bios = &dev_priv->vbios; 4341 uint8_t *table = &bios->data[bios->display.script_table_ptr]; 4342 uint8_t *otable = NULL; 4343 uint16_t script; 4344 int i; 4345 4346 if (!bios->display.script_table_ptr) { 4347 NV_ERROR(dev, "No pointer to output script table\n"); 4348 return 1; 4349 } 4350 4351 /* 4352 * Nothing useful has been in any of the pre-2.0 tables I've seen, 4353 * so until they are, we really don't need to care. 4354 */ 4355 if (table[0] < 0x20) 4356 return 1; 4357 4358 if (table[0] != 0x20 && table[0] != 0x21) { 4359 NV_ERROR(dev, "Output script table version 0x%02x unknown\n", 4360 table[0]); 4361 return 1; 4362 } 4363 4364 /* 4365 * The output script tables describing a particular output type 4366 * look as follows: 4367 * 4368 * offset + 0 (32 bits): output this table matches (hash of DCB) 4369 * offset + 4 ( 8 bits): unknown 4370 * offset + 5 ( 8 bits): number of configurations 4371 * offset + 6 (16 bits): pointer to some script 4372 * offset + 8 (16 bits): pointer to some script 4373 * 4374 * headerlen == 10 4375 * offset + 10 : configuration 0 4376 * 4377 * headerlen == 12 4378 * offset + 10 : pointer to some script 4379 * offset + 12 : configuration 0 4380 * 4381 * Each config entry is as follows: 4382 * 4383 * offset + 0 (16 bits): unknown, assumed to be a match value 4384 * offset + 2 (16 bits): pointer to script table (clock set?) 4385 * offset + 4 (16 bits): pointer to script table (reset?) 4386 * 4387 * There doesn't appear to be a count value to say how many 4388 * entries exist in each script table, instead, a 0 value in 4389 * the first 16-bit word seems to indicate both the end of the 4390 * list and the default entry. The second 16-bit word in the 4391 * script tables is a pointer to the script to execute. 4392 */ 4393 4394 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n", 4395 dcbent->type, dcbent->location, dcbent->or); 4396 for (i = 0; i < table[3]; i++) { 4397 otable = ROMPTR(dev, table[table[1] + (i * table[2])]); 4398 if (otable && bios_encoder_match(dcbent, ROM32(otable[0]))) 4399 break; 4400 } 4401 4402 if (!otable) { 4403 NV_DEBUG_KMS(dev, "failed to match any output table\n"); 4404 return 1; 4405 } 4406 4407 if (pclk < -2 || pclk > 0) { 4408 /* Try to find matching script table entry */ 4409 for (i = 0; i < otable[5]; i++) { 4410 if (ROM16(otable[table[4] + i*6]) == type) 4411 break; 4412 } 4413 4414 if (i == otable[5]) { 4415 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, " 4416 "using first\n", 4417 type, dcbent->type, dcbent->or); 4418 i = 0; 4419 } 4420 } 4421 4422 if (pclk == 0) { 4423 script = ROM16(otable[6]); 4424 if (!script) { 4425 NV_DEBUG_KMS(dev, "output script 0 not found\n"); 4426 return 1; 4427 } 4428 4429 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 0\n", script); 4430 nouveau_bios_run_init_table(dev, script, dcbent, crtc); 4431 } else 4432 if (pclk == -1) { 4433 script = ROM16(otable[8]); 4434 if (!script) { 4435 NV_DEBUG_KMS(dev, "output script 1 not found\n"); 4436 return 1; 4437 } 4438 4439 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 1\n", script); 4440 nouveau_bios_run_init_table(dev, script, dcbent, crtc); 4441 } else 4442 if (pclk == -2) { 4443 if (table[4] >= 12) 4444 script = ROM16(otable[10]); 4445 else 4446 script = 0; 4447 if (!script) { 4448 NV_DEBUG_KMS(dev, "output script 2 not found\n"); 4449 return 1; 4450 } 4451 4452 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 2\n", script); 4453 nouveau_bios_run_init_table(dev, script, dcbent, crtc); 4454 } else 4455 if (pclk > 0) { 4456 script = ROM16(otable[table[4] + i*6 + 2]); 4457 if (script) 4458 script = clkcmptable(bios, script, pclk); 4459 if (!script) { 4460 NV_DEBUG_KMS(dev, "clock script 0 not found\n"); 4461 return 1; 4462 } 4463 4464 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 0\n", script); 4465 nouveau_bios_run_init_table(dev, script, dcbent, crtc); 4466 } else 4467 if (pclk < 0) { 4468 script = ROM16(otable[table[4] + i*6 + 4]); 4469 if (script) 4470 script = clkcmptable(bios, script, -pclk); 4471 if (!script) { 4472 NV_DEBUG_KMS(dev, "clock script 1 not found\n"); 4473 return 1; 4474 } 4475 4476 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 1\n", script); 4477 nouveau_bios_run_init_table(dev, script, dcbent, crtc); 4478 } 4479 4480 return 0; 4481} 4482 4483 4484int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk) 4485{ 4486 /* 4487 * the pxclk parameter is in kHz 4488 * 4489 * This runs the TMDS regs setting code found on BIT bios cards 4490 * 4491 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and 4492 * ffs(or) == 3, use the second. 4493 */ 4494 4495 struct drm_nouveau_private *dev_priv = dev->dev_private; 4496 struct nvbios *bios = &dev_priv->vbios; 4497 int cv = bios->chip_version; 4498 uint16_t clktable = 0, scriptptr; 4499 uint32_t sel_clk_binding, sel_clk; 4500 4501 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */ 4502 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 && 4503 dcbent->location != DCB_LOC_ON_CHIP) 4504 return 0; 4505 4506 switch (ffs(dcbent->or)) { 4507 case 1: 4508 clktable = bios->tmds.output0_script_ptr; 4509 break; 4510 case 2: 4511 case 3: 4512 clktable = bios->tmds.output1_script_ptr; 4513 break; 4514 } 4515 4516 if (!clktable) { 4517 NV_ERROR(dev, "Pixel clock comparison table not found\n"); 4518 return -EINVAL; 4519 } 4520 4521 scriptptr = clkcmptable(bios, clktable, pxclk); 4522 4523 if (!scriptptr) { 4524 NV_ERROR(dev, "TMDS output init script not found\n"); 4525 return -ENOENT; 4526 } 4527 4528 /* don't let script change pll->head binding */ 4529 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000; 4530 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000); 4531 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; 4532 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); 4533 4534 return 0; 4535} 4536 4537struct pll_mapping { 4538 u8 type; 4539 u32 reg; 4540}; 4541 4542static struct pll_mapping nv04_pll_mapping[] = { 4543 { PLL_CORE , NV_PRAMDAC_NVPLL_COEFF }, 4544 { PLL_MEMORY, NV_PRAMDAC_MPLL_COEFF }, 4545 { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF }, 4546 { PLL_VPLL1 , NV_RAMDAC_VPLL2 }, 4547 {} 4548}; 4549 4550static struct pll_mapping nv40_pll_mapping[] = { 4551 { PLL_CORE , 0x004000 }, 4552 { PLL_MEMORY, 0x004020 }, 4553 { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF }, 4554 { PLL_VPLL1 , NV_RAMDAC_VPLL2 }, 4555 {} 4556}; 4557 4558static struct pll_mapping nv50_pll_mapping[] = { 4559 { PLL_CORE , 0x004028 }, 4560 { PLL_SHADER, 0x004020 }, 4561 { PLL_UNK03 , 0x004000 }, 4562 { PLL_MEMORY, 0x004008 }, 4563 { PLL_UNK40 , 0x00e810 }, 4564 { PLL_UNK41 , 0x00e818 }, 4565 { PLL_UNK42 , 0x00e824 }, 4566 { PLL_VPLL0 , 0x614100 }, 4567 { PLL_VPLL1 , 0x614900 }, 4568 {} 4569}; 4570 4571static struct pll_mapping nv84_pll_mapping[] = { 4572 { PLL_CORE , 0x004028 }, 4573 { PLL_SHADER, 0x004020 }, 4574 { PLL_MEMORY, 0x004008 }, 4575 { PLL_VDEC , 0x004030 }, 4576 { PLL_UNK41 , 0x00e818 }, 4577 { PLL_VPLL0 , 0x614100 }, 4578 { PLL_VPLL1 , 0x614900 }, 4579 {} 4580}; 4581 4582u32 4583get_pll_register(struct drm_device *dev, enum pll_types type) 4584{ 4585 struct drm_nouveau_private *dev_priv = dev->dev_private; 4586 struct nvbios *bios = &dev_priv->vbios; 4587 struct pll_mapping *map; 4588 int i; 4589 4590 if (dev_priv->card_type < NV_40) 4591 map = nv04_pll_mapping; 4592 else 4593 if (dev_priv->card_type < NV_50) 4594 map = nv40_pll_mapping; 4595 else { 4596 u8 *plim = &bios->data[bios->pll_limit_tbl_ptr]; 4597 4598 if (plim[0] >= 0x30) { 4599 u8 *entry = plim + plim[1]; 4600 for (i = 0; i < plim[3]; i++, entry += plim[2]) { 4601 if (entry[0] == type) 4602 return ROM32(entry[3]); 4603 } 4604 4605 return 0; 4606 } 4607 4608 if (dev_priv->chipset == 0x50) 4609 map = nv50_pll_mapping; 4610 else 4611 map = nv84_pll_mapping; 4612 } 4613 4614 while (map->reg) { 4615 if (map->type == type) 4616 return map->reg; 4617 map++; 4618 } 4619 4620 return 0; 4621} 4622 4623int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim) 4624{ 4625 /* 4626 * PLL limits table 4627 * 4628 * Version 0x10: NV30, NV31 4629 * One byte header (version), one record of 24 bytes 4630 * Version 0x11: NV36 - Not implemented 4631 * Seems to have same record style as 0x10, but 3 records rather than 1 4632 * Version 0x20: Found on Geforce 6 cards 4633 * Trivial 4 byte BIT header. 31 (0x1f) byte record length 4634 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards 4635 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record 4636 * length in general, some (integrated) have an extra configuration byte 4637 * Version 0x30: Found on Geforce 8, separates the register mapping 4638 * from the limits tables. 4639 */ 4640 4641 struct drm_nouveau_private *dev_priv = dev->dev_private; 4642 struct nvbios *bios = &dev_priv->vbios; 4643 int cv = bios->chip_version, pllindex = 0; 4644 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0; 4645 uint32_t crystal_strap_mask, crystal_straps; 4646 4647 if (!bios->pll_limit_tbl_ptr) { 4648 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 || 4649 cv >= 0x40) { 4650 NV_ERROR(dev, "Pointer to PLL limits table invalid\n"); 4651 return -EINVAL; 4652 } 4653 } else 4654 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr]; 4655 4656 crystal_strap_mask = 1 << 6; 4657 /* open coded dev->twoHeads test */ 4658 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20) 4659 crystal_strap_mask |= 1 << 22; 4660 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) & 4661 crystal_strap_mask; 4662 4663 switch (pll_lim_ver) { 4664 /* 4665 * We use version 0 to indicate a pre limit table bios (single stage 4666 * pll) and load the hard coded limits instead. 4667 */ 4668 case 0: 4669 break; 4670 case 0x10: 4671 case 0x11: 4672 /* 4673 * Strictly v0x11 has 3 entries, but the last two don't seem 4674 * to get used. 4675 */ 4676 headerlen = 1; 4677 recordlen = 0x18; 4678 entries = 1; 4679 pllindex = 0; 4680 break; 4681 case 0x20: 4682 case 0x21: 4683 case 0x30: 4684 case 0x40: 4685 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1]; 4686 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2]; 4687 entries = bios->data[bios->pll_limit_tbl_ptr + 3]; 4688 break; 4689 default: 4690 NV_ERROR(dev, "PLL limits table revision 0x%X not currently " 4691 "supported\n", pll_lim_ver); 4692 return -ENOSYS; 4693 } 4694 4695 /* initialize all members to zero */ 4696 memset(pll_lim, 0, sizeof(struct pll_lims)); 4697 4698 /* if we were passed a type rather than a register, figure 4699 * out the register and store it 4700 */ 4701 if (limit_match > PLL_MAX) 4702 pll_lim->reg = limit_match; 4703 else { 4704 pll_lim->reg = get_pll_register(dev, limit_match); 4705 if (!pll_lim->reg) 4706 return -ENOENT; 4707 } 4708 4709 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) { 4710 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex]; 4711 4712 pll_lim->vco1.minfreq = ROM32(pll_rec[0]); 4713 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]); 4714 pll_lim->vco2.minfreq = ROM32(pll_rec[8]); 4715 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]); 4716 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]); 4717 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]); 4718 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX; 4719 4720 /* these values taken from nv30/31/36 */ 4721 pll_lim->vco1.min_n = 0x1; 4722 if (cv == 0x36) 4723 pll_lim->vco1.min_n = 0x5; 4724 pll_lim->vco1.max_n = 0xff; 4725 pll_lim->vco1.min_m = 0x1; 4726 pll_lim->vco1.max_m = 0xd; 4727 pll_lim->vco2.min_n = 0x4; 4728 /* 4729 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this 4730 * table version (apart from nv35)), N2 is compared to 4731 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and 4732 * save a comparison 4733 */ 4734 pll_lim->vco2.max_n = 0x28; 4735 if (cv == 0x30 || cv == 0x35) 4736 /* only 5 bits available for N2 on nv30/35 */ 4737 pll_lim->vco2.max_n = 0x1f; 4738 pll_lim->vco2.min_m = 0x1; 4739 pll_lim->vco2.max_m = 0x4; 4740 pll_lim->max_log2p = 0x7; 4741 pll_lim->max_usable_log2p = 0x6; 4742 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) { 4743 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen; 4744 uint8_t *pll_rec; 4745 int i; 4746 4747 /* 4748 * First entry is default match, if nothing better. warn if 4749 * reg field nonzero 4750 */ 4751 if (ROM32(bios->data[plloffs])) 4752 NV_WARN(dev, "Default PLL limit entry has non-zero " 4753 "register field\n"); 4754 4755 for (i = 1; i < entries; i++) 4756 if (ROM32(bios->data[plloffs + recordlen * i]) == pll_lim->reg) { 4757 pllindex = i; 4758 break; 4759 } 4760 4761 if ((dev_priv->card_type >= NV_50) && (pllindex == 0)) { 4762 NV_ERROR(dev, "Register 0x%08x not found in PLL " 4763 "limits table", pll_lim->reg); 4764 return -ENOENT; 4765 } 4766 4767 pll_rec = &bios->data[plloffs + recordlen * pllindex]; 4768 4769 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n", 4770 pllindex ? pll_lim->reg : 0); 4771 4772 /* 4773 * Frequencies are stored in tables in MHz, kHz are more 4774 * useful, so we convert. 4775 */ 4776 4777 /* What output frequencies can each VCO generate? */ 4778 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000; 4779 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000; 4780 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000; 4781 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000; 4782 4783 /* What input frequencies they accept (past the m-divider)? */ 4784 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000; 4785 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000; 4786 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000; 4787 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000; 4788 4789 /* What values are accepted as multiplier and divider? */ 4790 pll_lim->vco1.min_n = pll_rec[20]; 4791 pll_lim->vco1.max_n = pll_rec[21]; 4792 pll_lim->vco1.min_m = pll_rec[22]; 4793 pll_lim->vco1.max_m = pll_rec[23]; 4794 pll_lim->vco2.min_n = pll_rec[24]; 4795 pll_lim->vco2.max_n = pll_rec[25]; 4796 pll_lim->vco2.min_m = pll_rec[26]; 4797 pll_lim->vco2.max_m = pll_rec[27]; 4798 4799 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29]; 4800 if (pll_lim->max_log2p > 0x7) 4801 /* pll decoding in nv_hw.c assumes never > 7 */ 4802 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n", 4803 pll_lim->max_log2p); 4804 if (cv < 0x60) 4805 pll_lim->max_usable_log2p = 0x6; 4806 pll_lim->log2p_bias = pll_rec[30]; 4807 4808 if (recordlen > 0x22) 4809 pll_lim->refclk = ROM32(pll_rec[31]); 4810 4811 if (recordlen > 0x23 && pll_rec[35]) 4812 NV_WARN(dev, 4813 "Bits set in PLL configuration byte (%x)\n", 4814 pll_rec[35]); 4815 4816 /* C51 special not seen elsewhere */ 4817 if (cv == 0x51 && !pll_lim->refclk) { 4818 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK); 4819 4820 if ((pll_lim->reg == NV_PRAMDAC_VPLL_COEFF && sel_clk & 0x20) || 4821 (pll_lim->reg == NV_RAMDAC_VPLL2 && sel_clk & 0x80)) { 4822 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3) 4823 pll_lim->refclk = 200000; 4824 else 4825 pll_lim->refclk = 25000; 4826 } 4827 } 4828 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */ 4829 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen]; 4830 uint8_t *record = NULL; 4831 int i; 4832 4833 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n", 4834 pll_lim->reg); 4835 4836 for (i = 0; i < entries; i++, entry += recordlen) { 4837 if (ROM32(entry[3]) == pll_lim->reg) { 4838 record = &bios->data[ROM16(entry[1])]; 4839 break; 4840 } 4841 } 4842 4843 if (!record) { 4844 NV_ERROR(dev, "Register 0x%08x not found in PLL " 4845 "limits table", pll_lim->reg); 4846 return -ENOENT; 4847 } 4848 4849 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000; 4850 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000; 4851 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000; 4852 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000; 4853 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000; 4854 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000; 4855 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000; 4856 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000; 4857 pll_lim->vco1.min_n = record[16]; 4858 pll_lim->vco1.max_n = record[17]; 4859 pll_lim->vco1.min_m = record[18]; 4860 pll_lim->vco1.max_m = record[19]; 4861 pll_lim->vco2.min_n = record[20]; 4862 pll_lim->vco2.max_n = record[21]; 4863 pll_lim->vco2.min_m = record[22]; 4864 pll_lim->vco2.max_m = record[23]; 4865 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25]; 4866 pll_lim->log2p_bias = record[27]; 4867 pll_lim->refclk = ROM32(record[28]); 4868 } else if (pll_lim_ver) { /* ver 0x40 */ 4869 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen]; 4870 uint8_t *record = NULL; 4871 int i; 4872 4873 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n", 4874 pll_lim->reg); 4875 4876 for (i = 0; i < entries; i++, entry += recordlen) { 4877 if (ROM32(entry[3]) == pll_lim->reg) { 4878 record = &bios->data[ROM16(entry[1])]; 4879 break; 4880 } 4881 } 4882 4883 if (!record) { 4884 NV_ERROR(dev, "Register 0x%08x not found in PLL " 4885 "limits table", pll_lim->reg); 4886 return -ENOENT; 4887 } 4888 4889 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000; 4890 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000; 4891 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000; 4892 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000; 4893 pll_lim->vco1.min_m = record[8]; 4894 pll_lim->vco1.max_m = record[9]; 4895 pll_lim->vco1.min_n = record[10]; 4896 pll_lim->vco1.max_n = record[11]; 4897 pll_lim->min_p = record[12]; 4898 pll_lim->max_p = record[13]; 4899 pll_lim->refclk = ROM16(entry[9]) * 1000; 4900 } 4901 4902 /* 4903 * By now any valid limit table ought to have set a max frequency for 4904 * vco1, so if it's zero it's either a pre limit table bios, or one 4905 * with an empty limit table (seen on nv18) 4906 */ 4907 if (!pll_lim->vco1.maxfreq) { 4908 pll_lim->vco1.minfreq = bios->fminvco; 4909 pll_lim->vco1.maxfreq = bios->fmaxvco; 4910 pll_lim->vco1.min_inputfreq = 0; 4911 pll_lim->vco1.max_inputfreq = INT_MAX; 4912 pll_lim->vco1.min_n = 0x1; 4913 pll_lim->vco1.max_n = 0xff; 4914 pll_lim->vco1.min_m = 0x1; 4915 if (crystal_straps == 0) { 4916 /* nv05 does this, nv11 doesn't, nv10 unknown */ 4917 if (cv < 0x11) 4918 pll_lim->vco1.min_m = 0x7; 4919 pll_lim->vco1.max_m = 0xd; 4920 } else { 4921 if (cv < 0x11) 4922 pll_lim->vco1.min_m = 0x8; 4923 pll_lim->vco1.max_m = 0xe; 4924 } 4925 if (cv < 0x17 || cv == 0x1a || cv == 0x20) 4926 pll_lim->max_log2p = 4; 4927 else 4928 pll_lim->max_log2p = 5; 4929 pll_lim->max_usable_log2p = pll_lim->max_log2p; 4930 } 4931 4932 if (!pll_lim->refclk) 4933 switch (crystal_straps) { 4934 case 0: 4935 pll_lim->refclk = 13500; 4936 break; 4937 case (1 << 6): 4938 pll_lim->refclk = 14318; 4939 break; 4940 case (1 << 22): 4941 pll_lim->refclk = 27000; 4942 break; 4943 case (1 << 22 | 1 << 6): 4944 pll_lim->refclk = 25000; 4945 break; 4946 } 4947 4948 NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq); 4949 NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq); 4950 NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq); 4951 NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq); 4952 NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n); 4953 NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n); 4954 NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m); 4955 NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m); 4956 if (pll_lim->vco2.maxfreq) { 4957 NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq); 4958 NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq); 4959 NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq); 4960 NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq); 4961 NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n); 4962 NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n); 4963 NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m); 4964 NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m); 4965 } 4966 if (!pll_lim->max_p) { 4967 NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p); 4968 NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias); 4969 } else { 4970 NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p); 4971 NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p); 4972 } 4973 NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk); 4974 4975 return 0; 4976} 4977 4978static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset) 4979{ 4980 /* 4981 * offset + 0 (8 bits): Micro version 4982 * offset + 1 (8 bits): Minor version 4983 * offset + 2 (8 bits): Chip version 4984 * offset + 3 (8 bits): Major version 4985 */ 4986 4987 bios->major_version = bios->data[offset + 3]; 4988 bios->chip_version = bios->data[offset + 2]; 4989 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n", 4990 bios->data[offset + 3], bios->data[offset + 2], 4991 bios->data[offset + 1], bios->data[offset]); 4992} 4993 4994static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset) 4995{ 4996 /* 4997 * Parses the init table segment for pointers used in script execution. 4998 * 4999 * offset + 0 (16 bits): init script tables pointer 5000 * offset + 2 (16 bits): macro index table pointer 5001 * offset + 4 (16 bits): macro table pointer 5002 * offset + 6 (16 bits): condition table pointer 5003 * offset + 8 (16 bits): io condition table pointer 5004 * offset + 10 (16 bits): io flag condition table pointer 5005 * offset + 12 (16 bits): init function table pointer 5006 */ 5007 5008 bios->init_script_tbls_ptr = ROM16(bios->data[offset]); 5009 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]); 5010 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]); 5011 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]); 5012 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]); 5013 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]); 5014 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]); 5015} 5016 5017static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5018{ 5019 /* 5020 * Parses the load detect values for g80 cards. 5021 * 5022 * offset + 0 (16 bits): loadval table pointer 5023 */ 5024 5025 uint16_t load_table_ptr; 5026 uint8_t version, headerlen, entrylen, num_entries; 5027 5028 if (bitentry->length != 3) { 5029 NV_ERROR(dev, "Do not understand BIT A table\n"); 5030 return -EINVAL; 5031 } 5032 5033 load_table_ptr = ROM16(bios->data[bitentry->offset]); 5034 5035 if (load_table_ptr == 0x0) { 5036 NV_DEBUG(dev, "Pointer to BIT loadval table invalid\n"); 5037 return -EINVAL; 5038 } 5039 5040 version = bios->data[load_table_ptr]; 5041 5042 if (version != 0x10) { 5043 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n", 5044 version >> 4, version & 0xF); 5045 return -ENOSYS; 5046 } 5047 5048 headerlen = bios->data[load_table_ptr + 1]; 5049 entrylen = bios->data[load_table_ptr + 2]; 5050 num_entries = bios->data[load_table_ptr + 3]; 5051 5052 if (headerlen != 4 || entrylen != 4 || num_entries != 2) { 5053 NV_ERROR(dev, "Do not understand BIT loadval table\n"); 5054 return -EINVAL; 5055 } 5056 5057 /* First entry is normal dac, 2nd tv-out perhaps? */ 5058 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff; 5059 5060 return 0; 5061} 5062 5063static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5064{ 5065 /* 5066 * offset + 8 (16 bits): PLL limits table pointer 5067 * 5068 * There's more in here, but that's unknown. 5069 */ 5070 5071 if (bitentry->length < 10) { 5072 NV_ERROR(dev, "Do not understand BIT C table\n"); 5073 return -EINVAL; 5074 } 5075 5076 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]); 5077 5078 return 0; 5079} 5080 5081static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5082{ 5083 /* 5084 * Parses the flat panel table segment that the bit entry points to. 5085 * Starting at bitentry->offset: 5086 * 5087 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte 5088 * records beginning with a freq. 5089 * offset + 2 (16 bits): mode table pointer 5090 */ 5091 5092 if (bitentry->length != 4) { 5093 NV_ERROR(dev, "Do not understand BIT display table\n"); 5094 return -EINVAL; 5095 } 5096 5097 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]); 5098 5099 return 0; 5100} 5101 5102static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5103{ 5104 /* 5105 * Parses the init table segment that the bit entry points to. 5106 * 5107 * See parse_script_table_pointers for layout 5108 */ 5109 5110 if (bitentry->length < 14) { 5111 NV_ERROR(dev, "Do not understand init table\n"); 5112 return -EINVAL; 5113 } 5114 5115 parse_script_table_pointers(bios, bitentry->offset); 5116 5117 if (bitentry->length >= 16) 5118 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]); 5119 if (bitentry->length >= 18) 5120 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]); 5121 5122 return 0; 5123} 5124 5125static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5126{ 5127 /* 5128 * BIT 'i' (info?) table 5129 * 5130 * offset + 0 (32 bits): BIOS version dword (as in B table) 5131 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?) 5132 * offset + 13 (16 bits): pointer to table containing DAC load 5133 * detection comparison values 5134 * 5135 * There's other things in the table, purpose unknown 5136 */ 5137 5138 uint16_t daccmpoffset; 5139 uint8_t dacver, dacheaderlen; 5140 5141 if (bitentry->length < 6) { 5142 NV_ERROR(dev, "BIT i table too short for needed information\n"); 5143 return -EINVAL; 5144 } 5145 5146 parse_bios_version(dev, bios, bitentry->offset); 5147 5148 /* 5149 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's 5150 * Quadro identity crisis), other bits possibly as for BMP feature byte 5151 */ 5152 bios->feature_byte = bios->data[bitentry->offset + 5]; 5153 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE; 5154 5155 if (bitentry->length < 15) { 5156 NV_WARN(dev, "BIT i table not long enough for DAC load " 5157 "detection comparison table\n"); 5158 return -EINVAL; 5159 } 5160 5161 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]); 5162 5163 /* doesn't exist on g80 */ 5164 if (!daccmpoffset) 5165 return 0; 5166 5167 /* 5168 * The first value in the table, following the header, is the 5169 * comparison value, the second entry is a comparison value for 5170 * TV load detection. 5171 */ 5172 5173 dacver = bios->data[daccmpoffset]; 5174 dacheaderlen = bios->data[daccmpoffset + 1]; 5175 5176 if (dacver != 0x00 && dacver != 0x10) { 5177 NV_WARN(dev, "DAC load detection comparison table version " 5178 "%d.%d not known\n", dacver >> 4, dacver & 0xf); 5179 return -ENOSYS; 5180 } 5181 5182 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]); 5183 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]); 5184 5185 return 0; 5186} 5187 5188static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5189{ 5190 /* 5191 * Parses the LVDS table segment that the bit entry points to. 5192 * Starting at bitentry->offset: 5193 * 5194 * offset + 0 (16 bits): LVDS strap xlate table pointer 5195 */ 5196 5197 if (bitentry->length != 2) { 5198 NV_ERROR(dev, "Do not understand BIT LVDS table\n"); 5199 return -EINVAL; 5200 } 5201 5202 /* 5203 * No idea if it's still called the LVDS manufacturer table, but 5204 * the concept's close enough. 5205 */ 5206 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]); 5207 5208 return 0; 5209} 5210 5211static int 5212parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios, 5213 struct bit_entry *bitentry) 5214{ 5215 /* 5216 * offset + 2 (8 bits): number of options in an 5217 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set 5218 * offset + 3 (16 bits): pointer to strap xlate table for RAM 5219 * restrict option selection 5220 * 5221 * There's a bunch of bits in this table other than the RAM restrict 5222 * stuff that we don't use - their use currently unknown 5223 */ 5224 5225 /* 5226 * Older bios versions don't have a sufficiently long table for 5227 * what we want 5228 */ 5229 if (bitentry->length < 0x5) 5230 return 0; 5231 5232 if (bitentry->version < 2) { 5233 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2]; 5234 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]); 5235 } else { 5236 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0]; 5237 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]); 5238 } 5239 5240 return 0; 5241} 5242 5243static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5244{ 5245 /* 5246 * Parses the pointer to the TMDS table 5247 * 5248 * Starting at bitentry->offset: 5249 * 5250 * offset + 0 (16 bits): TMDS table pointer 5251 * 5252 * The TMDS table is typically found just before the DCB table, with a 5253 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being 5254 * length?) 5255 * 5256 * At offset +7 is a pointer to a script, which I don't know how to 5257 * run yet. 5258 * At offset +9 is a pointer to another script, likewise 5259 * Offset +11 has a pointer to a table where the first word is a pxclk 5260 * frequency and the second word a pointer to a script, which should be 5261 * run if the comparison pxclk frequency is less than the pxclk desired. 5262 * This repeats for decreasing comparison frequencies 5263 * Offset +13 has a pointer to a similar table 5264 * The selection of table (and possibly +7/+9 script) is dictated by 5265 * "or" from the DCB. 5266 */ 5267 5268 uint16_t tmdstableptr, script1, script2; 5269 5270 if (bitentry->length != 2) { 5271 NV_ERROR(dev, "Do not understand BIT TMDS table\n"); 5272 return -EINVAL; 5273 } 5274 5275 tmdstableptr = ROM16(bios->data[bitentry->offset]); 5276 if (!tmdstableptr) { 5277 NV_ERROR(dev, "Pointer to TMDS table invalid\n"); 5278 return -EINVAL; 5279 } 5280 5281 NV_INFO(dev, "TMDS table version %d.%d\n", 5282 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf); 5283 5284 /* nv50+ has v2.0, but we don't parse it atm */ 5285 if (bios->data[tmdstableptr] != 0x11) 5286 return -ENOSYS; 5287 5288 /* 5289 * These two scripts are odd: they don't seem to get run even when 5290 * they are not stubbed. 5291 */ 5292 script1 = ROM16(bios->data[tmdstableptr + 7]); 5293 script2 = ROM16(bios->data[tmdstableptr + 9]); 5294 if (bios->data[script1] != 'q' || bios->data[script2] != 'q') 5295 NV_WARN(dev, "TMDS table script pointers not stubbed\n"); 5296 5297 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]); 5298 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]); 5299 5300 return 0; 5301} 5302 5303static int 5304parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios, 5305 struct bit_entry *bitentry) 5306{ 5307 /* 5308 * Parses the pointer to the G80 output script tables 5309 * 5310 * Starting at bitentry->offset: 5311 * 5312 * offset + 0 (16 bits): output script table pointer 5313 */ 5314 5315 uint16_t outputscripttableptr; 5316 5317 if (bitentry->length != 3) { 5318 NV_ERROR(dev, "Do not understand BIT U table\n"); 5319 return -EINVAL; 5320 } 5321 5322 outputscripttableptr = ROM16(bios->data[bitentry->offset]); 5323 bios->display.script_table_ptr = outputscripttableptr; 5324 return 0; 5325} 5326 5327struct bit_table { 5328 const char id; 5329 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *); 5330}; 5331 5332#define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry }) 5333 5334int 5335bit_table(struct drm_device *dev, u8 id, struct bit_entry *bit) 5336{ 5337 struct drm_nouveau_private *dev_priv = dev->dev_private; 5338 struct nvbios *bios = &dev_priv->vbios; 5339 u8 entries, *entry; 5340 5341 if (bios->type != NVBIOS_BIT) 5342 return -ENODEV; 5343 5344 entries = bios->data[bios->offset + 10]; 5345 entry = &bios->data[bios->offset + 12]; 5346 while (entries--) { 5347 if (entry[0] == id) { 5348 bit->id = entry[0]; 5349 bit->version = entry[1]; 5350 bit->length = ROM16(entry[2]); 5351 bit->offset = ROM16(entry[4]); 5352 bit->data = ROMPTR(dev, entry[4]); 5353 return 0; 5354 } 5355 5356 entry += bios->data[bios->offset + 9]; 5357 } 5358 5359 return -ENOENT; 5360} 5361 5362static int 5363parse_bit_table(struct nvbios *bios, const uint16_t bitoffset, 5364 struct bit_table *table) 5365{ 5366 struct drm_device *dev = bios->dev; 5367 struct bit_entry bitentry; 5368 5369 if (bit_table(dev, table->id, &bitentry) == 0) 5370 return table->parse_fn(dev, bios, &bitentry); 5371 5372 NV_INFO(dev, "BIT table '%c' not found\n", table->id); 5373 return -ENOSYS; 5374} 5375 5376static int 5377parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset) 5378{ 5379 int ret; 5380 5381 /* 5382 * The only restriction on parsing order currently is having 'i' first 5383 * for use of bios->*_version or bios->feature_byte while parsing; 5384 * functions shouldn't be actually *doing* anything apart from pulling 5385 * data from the image into the bios struct, thus no interdependencies 5386 */ 5387 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i)); 5388 if (ret) /* info? */ 5389 return ret; 5390 if (bios->major_version >= 0x60) /* g80+ */ 5391 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A)); 5392 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C)); 5393 if (ret) 5394 return ret; 5395 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display)); 5396 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init)); 5397 if (ret) 5398 return ret; 5399 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */ 5400 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds)); 5401 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds)); 5402 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U)); 5403 5404 return 0; 5405} 5406 5407static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset) 5408{ 5409 /* 5410 * Parses the BMP structure for useful things, but does not act on them 5411 * 5412 * offset + 5: BMP major version 5413 * offset + 6: BMP minor version 5414 * offset + 9: BMP feature byte 5415 * offset + 10: BCD encoded BIOS version 5416 * 5417 * offset + 18: init script table pointer (for bios versions < 5.10h) 5418 * offset + 20: extra init script table pointer (for bios 5419 * versions < 5.10h) 5420 * 5421 * offset + 24: memory init table pointer (used on early bios versions) 5422 * offset + 26: SDR memory sequencing setup data table 5423 * offset + 28: DDR memory sequencing setup data table 5424 * 5425 * offset + 54: index of I2C CRTC pair to use for CRT output 5426 * offset + 55: index of I2C CRTC pair to use for TV output 5427 * offset + 56: index of I2C CRTC pair to use for flat panel output 5428 * offset + 58: write CRTC index for I2C pair 0 5429 * offset + 59: read CRTC index for I2C pair 0 5430 * offset + 60: write CRTC index for I2C pair 1 5431 * offset + 61: read CRTC index for I2C pair 1 5432 * 5433 * offset + 67: maximum internal PLL frequency (single stage PLL) 5434 * offset + 71: minimum internal PLL frequency (single stage PLL) 5435 * 5436 * offset + 75: script table pointers, as described in 5437 * parse_script_table_pointers 5438 * 5439 * offset + 89: TMDS single link output A table pointer 5440 * offset + 91: TMDS single link output B table pointer 5441 * offset + 95: LVDS single link output A table pointer 5442 * offset + 105: flat panel timings table pointer 5443 * offset + 107: flat panel strapping translation table pointer 5444 * offset + 117: LVDS manufacturer panel config table pointer 5445 * offset + 119: LVDS manufacturer strapping translation table pointer 5446 * 5447 * offset + 142: PLL limits table pointer 5448 * 5449 * offset + 156: minimum pixel clock for LVDS dual link 5450 */ 5451 5452 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor; 5453 uint16_t bmplength; 5454 uint16_t legacy_scripts_offset, legacy_i2c_offset; 5455 5456 /* load needed defaults in case we can't parse this info */ 5457 bios->digital_min_front_porch = 0x4b; 5458 bios->fmaxvco = 256000; 5459 bios->fminvco = 128000; 5460 bios->fp.duallink_transition_clk = 90000; 5461 5462 bmp_version_major = bmp[5]; 5463 bmp_version_minor = bmp[6]; 5464 5465 NV_TRACE(dev, "BMP version %d.%d\n", 5466 bmp_version_major, bmp_version_minor); 5467 5468 /* 5469 * Make sure that 0x36 is blank and can't be mistaken for a DCB 5470 * pointer on early versions 5471 */ 5472 if (bmp_version_major < 5) 5473 *(uint16_t *)&bios->data[0x36] = 0; 5474 5475 /* 5476 * Seems that the minor version was 1 for all major versions prior 5477 * to 5. Version 6 could theoretically exist, but I suspect BIT 5478 * happened instead. 5479 */ 5480 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) { 5481 NV_ERROR(dev, "You have an unsupported BMP version. " 5482 "Please send in your bios\n"); 5483 return -ENOSYS; 5484 } 5485 5486 if (bmp_version_major == 0) 5487 /* nothing that's currently useful in this version */ 5488 return 0; 5489 else if (bmp_version_major == 1) 5490 bmplength = 44; /* exact for 1.01 */ 5491 else if (bmp_version_major == 2) 5492 bmplength = 48; /* exact for 2.01 */ 5493 else if (bmp_version_major == 3) 5494 bmplength = 54; 5495 /* guessed - mem init tables added in this version */ 5496 else if (bmp_version_major == 4 || bmp_version_minor < 0x1) 5497 /* don't know if 5.0 exists... */ 5498 bmplength = 62; 5499 /* guessed - BMP I2C indices added in version 4*/ 5500 else if (bmp_version_minor < 0x6) 5501 bmplength = 67; /* exact for 5.01 */ 5502 else if (bmp_version_minor < 0x10) 5503 bmplength = 75; /* exact for 5.06 */ 5504 else if (bmp_version_minor == 0x10) 5505 bmplength = 89; /* exact for 5.10h */ 5506 else if (bmp_version_minor < 0x14) 5507 bmplength = 118; /* exact for 5.11h */ 5508 else if (bmp_version_minor < 0x24) 5509 /* 5510 * Not sure of version where pll limits came in; 5511 * certainly exist by 0x24 though. 5512 */ 5513 /* length not exact: this is long enough to get lvds members */ 5514 bmplength = 123; 5515 else if (bmp_version_minor < 0x27) 5516 /* 5517 * Length not exact: this is long enough to get pll limit 5518 * member 5519 */ 5520 bmplength = 144; 5521 else 5522 /* 5523 * Length not exact: this is long enough to get dual link 5524 * transition clock. 5525 */ 5526 bmplength = 158; 5527 5528 /* checksum */ 5529 if (nv_cksum(bmp, 8)) { 5530 NV_ERROR(dev, "Bad BMP checksum\n"); 5531 return -EINVAL; 5532 } 5533 5534 /* 5535 * Bit 4 seems to indicate either a mobile bios or a quadro card -- 5536 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl 5537 * (not nv10gl), bit 5 that the flat panel tables are present, and 5538 * bit 6 a tv bios. 5539 */ 5540 bios->feature_byte = bmp[9]; 5541 5542 parse_bios_version(dev, bios, offset + 10); 5543 5544 if (bmp_version_major < 5 || bmp_version_minor < 0x10) 5545 bios->old_style_init = true; 5546 legacy_scripts_offset = 18; 5547 if (bmp_version_major < 2) 5548 legacy_scripts_offset -= 4; 5549 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]); 5550 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]); 5551 5552 if (bmp_version_major > 2) { /* appears in BMP 3 */ 5553 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]); 5554 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]); 5555 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]); 5556 } 5557 5558 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */ 5559 if (bmplength > 61) 5560 legacy_i2c_offset = offset + 54; 5561 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset]; 5562 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1]; 5563 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2]; 5564 5565 if (bmplength > 74) { 5566 bios->fmaxvco = ROM32(bmp[67]); 5567 bios->fminvco = ROM32(bmp[71]); 5568 } 5569 if (bmplength > 88) 5570 parse_script_table_pointers(bios, offset + 75); 5571 if (bmplength > 94) { 5572 bios->tmds.output0_script_ptr = ROM16(bmp[89]); 5573 bios->tmds.output1_script_ptr = ROM16(bmp[91]); 5574 /* 5575 * Never observed in use with lvds scripts, but is reused for 5576 * 18/24 bit panel interface default for EDID equipped panels 5577 * (if_is_24bit not set directly to avoid any oscillation). 5578 */ 5579 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]); 5580 } 5581 if (bmplength > 108) { 5582 bios->fp.fptablepointer = ROM16(bmp[105]); 5583 bios->fp.fpxlatetableptr = ROM16(bmp[107]); 5584 bios->fp.xlatwidth = 1; 5585 } 5586 if (bmplength > 120) { 5587 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]); 5588 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]); 5589 } 5590 if (bmplength > 143) 5591 bios->pll_limit_tbl_ptr = ROM16(bmp[142]); 5592 5593 if (bmplength > 157) 5594 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10; 5595 5596 return 0; 5597} 5598 5599static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len) 5600{ 5601 int i, j; 5602 5603 for (i = 0; i <= (n - len); i++) { 5604 for (j = 0; j < len; j++) 5605 if (data[i + j] != str[j]) 5606 break; 5607 if (j == len) 5608 return i; 5609 } 5610 5611 return 0; 5612} 5613 5614void * 5615dcb_table(struct drm_device *dev) 5616{ 5617 struct drm_nouveau_private *dev_priv = dev->dev_private; 5618 u8 *dcb = NULL; 5619 5620 if (dev_priv->card_type > NV_04) 5621 dcb = ROMPTR(dev, dev_priv->vbios.data[0x36]); 5622 if (!dcb) { 5623 NV_WARNONCE(dev, "No DCB data found in VBIOS\n"); 5624 return NULL; 5625 } 5626 5627 if (dcb[0] >= 0x41) { 5628 NV_WARNONCE(dev, "DCB version 0x%02x unknown\n", dcb[0]); 5629 return NULL; 5630 } else 5631 if (dcb[0] >= 0x30) { 5632 if (ROM32(dcb[6]) == 0x4edcbdcb) 5633 return dcb; 5634 } else 5635 if (dcb[0] >= 0x20) { 5636 if (ROM32(dcb[4]) == 0x4edcbdcb) 5637 return dcb; 5638 } else 5639 if (dcb[0] >= 0x15) { 5640 if (!memcmp(&dcb[-7], "DEV_REC", 7)) 5641 return dcb; 5642 } else { 5643 /* 5644 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but 5645 * always has the same single (crt) entry, even when tv-out 5646 * present, so the conclusion is this version cannot really 5647 * be used. 5648 * 5649 * v1.2 tables (some NV6/10, and NV15+) normally have the 5650 * same 5 entries, which are not specific to the card and so 5651 * no use. 5652 * 5653 * v1.2 does have an I2C table that read_dcb_i2c_table can 5654 * handle, but cards exist (nv11 in #14821) with a bad i2c 5655 * table pointer, so use the indices parsed in 5656 * parse_bmp_structure. 5657 * 5658 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful 5659 */ 5660 NV_WARNONCE(dev, "No useful DCB data in VBIOS\n"); 5661 return NULL; 5662 } 5663 5664 NV_WARNONCE(dev, "DCB header validation failed\n"); 5665 return NULL; 5666} 5667 5668void * 5669dcb_outp(struct drm_device *dev, u8 idx) 5670{ 5671 u8 *dcb = dcb_table(dev); 5672 if (dcb && dcb[0] >= 0x30) { 5673 if (idx < dcb[2]) 5674 return dcb + dcb[1] + (idx * dcb[3]); 5675 } else 5676 if (dcb && dcb[0] >= 0x20) { 5677 u8 *i2c = ROMPTR(dev, dcb[2]); 5678 u8 *ent = dcb + 8 + (idx * 8); 5679 if (i2c && ent < i2c) 5680 return ent; 5681 } else 5682 if (dcb && dcb[0] >= 0x15) { 5683 u8 *i2c = ROMPTR(dev, dcb[2]); 5684 u8 *ent = dcb + 4 + (idx * 10); 5685 if (i2c && ent < i2c) 5686 return ent; 5687 } 5688 5689 return NULL; 5690} 5691 5692int 5693dcb_outp_foreach(struct drm_device *dev, void *data, 5694 int (*exec)(struct drm_device *, void *, int idx, u8 *outp)) 5695{ 5696 int ret, idx = -1; 5697 u8 *outp = NULL; 5698 while ((outp = dcb_outp(dev, ++idx))) { 5699 if (ROM32(outp[0]) == 0x00000000) 5700 break; /* seen on an NV11 with DCB v1.5 */ 5701 if (ROM32(outp[0]) == 0xffffffff) 5702 break; /* seen on an NV17 with DCB v2.0 */ 5703 5704 if ((outp[0] & 0x0f) == OUTPUT_UNUSED) 5705 continue; 5706 if ((outp[0] & 0x0f) == OUTPUT_EOL) 5707 break; 5708 5709 ret = exec(dev, data, idx, outp); 5710 if (ret) 5711 return ret; 5712 } 5713 5714 return 0; 5715} 5716 5717u8 * 5718dcb_conntab(struct drm_device *dev) 5719{ 5720 u8 *dcb = dcb_table(dev); 5721 if (dcb && dcb[0] >= 0x30 && dcb[1] >= 0x16) { 5722 u8 *conntab = ROMPTR(dev, dcb[0x14]); 5723 if (conntab && conntab[0] >= 0x30 && conntab[0] <= 0x40) 5724 return conntab; 5725 } 5726 return NULL; 5727} 5728 5729u8 * 5730dcb_conn(struct drm_device *dev, u8 idx) 5731{ 5732 u8 *conntab = dcb_conntab(dev); 5733 if (conntab && idx < conntab[2]) 5734 return conntab + conntab[1] + (idx * conntab[3]); 5735 return NULL; 5736} 5737 5738static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb) 5739{ 5740 struct dcb_entry *entry = &dcb->entry[dcb->entries]; 5741 5742 memset(entry, 0, sizeof(struct dcb_entry)); 5743 entry->index = dcb->entries++; 5744 5745 return entry; 5746} 5747 5748static void fabricate_dcb_output(struct dcb_table *dcb, int type, int i2c, 5749 int heads, int or) 5750{ 5751 struct dcb_entry *entry = new_dcb_entry(dcb); 5752 5753 entry->type = type; 5754 entry->i2c_index = i2c; 5755 entry->heads = heads; 5756 if (type != OUTPUT_ANALOG) 5757 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */ 5758 entry->or = or; 5759} 5760 5761static bool 5762parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb, 5763 uint32_t conn, uint32_t conf, struct dcb_entry *entry) 5764{ 5765 entry->type = conn & 0xf; 5766 entry->i2c_index = (conn >> 4) & 0xf; 5767 entry->heads = (conn >> 8) & 0xf; 5768 entry->connector = (conn >> 12) & 0xf; 5769 entry->bus = (conn >> 16) & 0xf; 5770 entry->location = (conn >> 20) & 0x3; 5771 entry->or = (conn >> 24) & 0xf; 5772 5773 switch (entry->type) { 5774 case OUTPUT_ANALOG: 5775 /* 5776 * Although the rest of a CRT conf dword is usually 5777 * zeros, mac biosen have stuff there so we must mask 5778 */ 5779 entry->crtconf.maxfreq = (dcb->version < 0x30) ? 5780 (conf & 0xffff) * 10 : 5781 (conf & 0xff) * 10000; 5782 break; 5783 case OUTPUT_LVDS: 5784 { 5785 uint32_t mask; 5786 if (conf & 0x1) 5787 entry->lvdsconf.use_straps_for_mode = true; 5788 if (dcb->version < 0x22) { 5789 mask = ~0xd; 5790 /* 5791 * The laptop in bug 14567 lies and claims to not use 5792 * straps when it does, so assume all DCB 2.0 laptops 5793 * use straps, until a broken EDID using one is produced 5794 */ 5795 entry->lvdsconf.use_straps_for_mode = true; 5796 /* 5797 * Both 0x4 and 0x8 show up in v2.0 tables; assume they 5798 * mean the same thing (probably wrong, but might work) 5799 */ 5800 if (conf & 0x4 || conf & 0x8) 5801 entry->lvdsconf.use_power_scripts = true; 5802 } else { 5803 mask = ~0x7; 5804 if (conf & 0x2) 5805 entry->lvdsconf.use_acpi_for_edid = true; 5806 if (conf & 0x4) 5807 entry->lvdsconf.use_power_scripts = true; 5808 entry->lvdsconf.sor.link = (conf & 0x00000030) >> 4; 5809 } 5810 if (conf & mask) { 5811 /* 5812 * Until we even try to use these on G8x, it's 5813 * useless reporting unknown bits. They all are. 5814 */ 5815 if (dcb->version >= 0x40) 5816 break; 5817 5818 NV_ERROR(dev, "Unknown LVDS configuration bits, " 5819 "please report\n"); 5820 } 5821 break; 5822 } 5823 case OUTPUT_TV: 5824 { 5825 if (dcb->version >= 0x30) 5826 entry->tvconf.has_component_output = conf & (0x8 << 4); 5827 else 5828 entry->tvconf.has_component_output = false; 5829 5830 break; 5831 } 5832 case OUTPUT_DP: 5833 entry->dpconf.sor.link = (conf & 0x00000030) >> 4; 5834 switch ((conf & 0x00e00000) >> 21) { 5835 case 0: 5836 entry->dpconf.link_bw = 162000; 5837 break; 5838 default: 5839 entry->dpconf.link_bw = 270000; 5840 break; 5841 } 5842 switch ((conf & 0x0f000000) >> 24) { 5843 case 0xf: 5844 entry->dpconf.link_nr = 4; 5845 break; 5846 case 0x3: 5847 entry->dpconf.link_nr = 2; 5848 break; 5849 default: 5850 entry->dpconf.link_nr = 1; 5851 break; 5852 } 5853 break; 5854 case OUTPUT_TMDS: 5855 if (dcb->version >= 0x40) 5856 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4; 5857 else if (dcb->version >= 0x30) 5858 entry->tmdsconf.slave_addr = (conf & 0x00000700) >> 8; 5859 else if (dcb->version >= 0x22) 5860 entry->tmdsconf.slave_addr = (conf & 0x00000070) >> 4; 5861 5862 break; 5863 case OUTPUT_EOL: 5864 /* weird g80 mobile type that "nv" treats as a terminator */ 5865 dcb->entries--; 5866 return false; 5867 default: 5868 break; 5869 } 5870 5871 if (dcb->version < 0x40) { 5872 /* Normal entries consist of a single bit, but dual link has 5873 * the next most significant bit set too 5874 */ 5875 entry->duallink_possible = 5876 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or); 5877 } else { 5878 entry->duallink_possible = (entry->sorconf.link == 3); 5879 } 5880 5881 /* unsure what DCB version introduces this, 3.0? */ 5882 if (conf & 0x100000) 5883 entry->i2c_upper_default = true; 5884 5885 return true; 5886} 5887 5888static bool 5889parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb, 5890 uint32_t conn, uint32_t conf, struct dcb_entry *entry) 5891{ 5892 switch (conn & 0x0000000f) { 5893 case 0: 5894 entry->type = OUTPUT_ANALOG; 5895 break; 5896 case 1: 5897 entry->type = OUTPUT_TV; 5898 break; 5899 case 2: 5900 case 4: 5901 if (conn & 0x10) 5902 entry->type = OUTPUT_LVDS; 5903 else 5904 entry->type = OUTPUT_TMDS; 5905 break; 5906 case 3: 5907 entry->type = OUTPUT_LVDS; 5908 break; 5909 default: 5910 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f); 5911 return false; 5912 } 5913 5914 entry->i2c_index = (conn & 0x0003c000) >> 14; 5915 entry->heads = ((conn & 0x001c0000) >> 18) + 1; 5916 entry->or = entry->heads; /* same as heads, hopefully safe enough */ 5917 entry->location = (conn & 0x01e00000) >> 21; 5918 entry->bus = (conn & 0x0e000000) >> 25; 5919 entry->duallink_possible = false; 5920 5921 switch (entry->type) { 5922 case OUTPUT_ANALOG: 5923 entry->crtconf.maxfreq = (conf & 0xffff) * 10; 5924 break; 5925 case OUTPUT_TV: 5926 entry->tvconf.has_component_output = false; 5927 break; 5928 case OUTPUT_LVDS: 5929 if ((conn & 0x00003f00) >> 8 != 0x10) 5930 entry->lvdsconf.use_straps_for_mode = true; 5931 entry->lvdsconf.use_power_scripts = true; 5932 break; 5933 default: 5934 break; 5935 } 5936 5937 return true; 5938} 5939 5940static 5941void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb) 5942{ 5943 /* 5944 * DCB v2.0 lists each output combination separately. 5945 * Here we merge compatible entries to have fewer outputs, with 5946 * more options 5947 */ 5948 5949 int i, newentries = 0; 5950 5951 for (i = 0; i < dcb->entries; i++) { 5952 struct dcb_entry *ient = &dcb->entry[i]; 5953 int j; 5954 5955 for (j = i + 1; j < dcb->entries; j++) { 5956 struct dcb_entry *jent = &dcb->entry[j]; 5957 5958 if (jent->type == 100) /* already merged entry */ 5959 continue; 5960 5961 /* merge heads field when all other fields the same */ 5962 if (jent->i2c_index == ient->i2c_index && 5963 jent->type == ient->type && 5964 jent->location == ient->location && 5965 jent->or == ient->or) { 5966 NV_TRACE(dev, "Merging DCB entries %d and %d\n", 5967 i, j); 5968 ient->heads |= jent->heads; 5969 jent->type = 100; /* dummy value */ 5970 } 5971 } 5972 } 5973 5974 /* Compact entries merged into others out of dcb */ 5975 for (i = 0; i < dcb->entries; i++) { 5976 if (dcb->entry[i].type == 100) 5977 continue; 5978 5979 if (newentries != i) { 5980 dcb->entry[newentries] = dcb->entry[i]; 5981 dcb->entry[newentries].index = newentries; 5982 } 5983 newentries++; 5984 } 5985 5986 dcb->entries = newentries; 5987} 5988 5989static bool 5990apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf) 5991{ 5992 struct drm_nouveau_private *dev_priv = dev->dev_private; 5993 struct dcb_table *dcb = &dev_priv->vbios.dcb; 5994 5995 /* Dell Precision M6300 5996 * DCB entry 2: 02025312 00000010 5997 * DCB entry 3: 02026312 00000020 5998 * 5999 * Identical, except apparently a different connector on a 6000 * different SOR link. Not a clue how we're supposed to know 6001 * which one is in use if it even shares an i2c line... 6002 * 6003 * Ignore the connector on the second SOR link to prevent 6004 * nasty problems until this is sorted (assuming it's not a 6005 * VBIOS bug). 6006 */ 6007 if (nv_match_device(dev, 0x040d, 0x1028, 0x019b)) { 6008 if (*conn == 0x02026312 && *conf == 0x00000020) 6009 return false; 6010 } 6011 6012 /* GeForce3 Ti 200 6013 * 6014 * DCB reports an LVDS output that should be TMDS: 6015 * DCB entry 1: f2005014 ffffffff 6016 */ 6017 if (nv_match_device(dev, 0x0201, 0x1462, 0x8851)) { 6018 if (*conn == 0xf2005014 && *conf == 0xffffffff) { 6019 fabricate_dcb_output(dcb, OUTPUT_TMDS, 1, 1, 1); 6020 return false; 6021 } 6022 } 6023 6024 /* XFX GT-240X-YA 6025 * 6026 * So many things wrong here, replace the entire encoder table.. 6027 */ 6028 if (nv_match_device(dev, 0x0ca3, 0x1682, 0x3003)) { 6029 if (idx == 0) { 6030 *conn = 0x02001300; /* VGA, connector 1 */ 6031 *conf = 0x00000028; 6032 } else 6033 if (idx == 1) { 6034 *conn = 0x01010312; /* DVI, connector 0 */ 6035 *conf = 0x00020030; 6036 } else 6037 if (idx == 2) { 6038 *conn = 0x01010310; /* VGA, connector 0 */ 6039 *conf = 0x00000028; 6040 } else 6041 if (idx == 3) { 6042 *conn = 0x02022362; /* HDMI, connector 2 */ 6043 *conf = 0x00020010; 6044 } else { 6045 *conn = 0x0000000e; /* EOL */ 6046 *conf = 0x00000000; 6047 } 6048 } 6049 6050 /* Some other twisted XFX board (rhbz#694914) 6051 * 6052 * The DVI/VGA encoder combo that's supposed to represent the 6053 * DVI-I connector actually point at two different ones, and 6054 * the HDMI connector ends up paired with the VGA instead. 6055 * 6056 * Connector table is missing anything for VGA at all, pointing it 6057 * an invalid conntab entry 2 so we figure it out ourself. 6058 */ 6059 if (nv_match_device(dev, 0x0615, 0x1682, 0x2605)) { 6060 if (idx == 0) { 6061 *conn = 0x02002300; /* VGA, connector 2 */ 6062 *conf = 0x00000028; 6063 } else 6064 if (idx == 1) { 6065 *conn = 0x01010312; /* DVI, connector 0 */ 6066 *conf = 0x00020030; 6067 } else 6068 if (idx == 2) { 6069 *conn = 0x04020310; /* VGA, connector 0 */ 6070 *conf = 0x00000028; 6071 } else 6072 if (idx == 3) { 6073 *conn = 0x02021322; /* HDMI, connector 1 */ 6074 *conf = 0x00020010; 6075 } else { 6076 *conn = 0x0000000e; /* EOL */ 6077 *conf = 0x00000000; 6078 } 6079 } 6080 6081 return true; 6082} 6083 6084static void 6085fabricate_dcb_encoder_table(struct drm_device *dev, struct nvbios *bios) 6086{ 6087 struct dcb_table *dcb = &bios->dcb; 6088 int all_heads = (nv_two_heads(dev) ? 3 : 1); 6089 6090#ifdef __powerpc__ 6091 /* Apple iMac G4 NV17 */ 6092 if (of_machine_is_compatible("PowerMac4,5")) { 6093 fabricate_dcb_output(dcb, OUTPUT_TMDS, 0, all_heads, 1); 6094 fabricate_dcb_output(dcb, OUTPUT_ANALOG, 1, all_heads, 2); 6095 return; 6096 } 6097#endif 6098 6099 /* Make up some sane defaults */ 6100 fabricate_dcb_output(dcb, OUTPUT_ANALOG, 6101 bios->legacy.i2c_indices.crt, 1, 1); 6102 6103 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0) 6104 fabricate_dcb_output(dcb, OUTPUT_TV, 6105 bios->legacy.i2c_indices.tv, 6106 all_heads, 0); 6107 6108 else if (bios->tmds.output0_script_ptr || 6109 bios->tmds.output1_script_ptr) 6110 fabricate_dcb_output(dcb, OUTPUT_TMDS, 6111 bios->legacy.i2c_indices.panel, 6112 all_heads, 1); 6113} 6114 6115static int 6116parse_dcb_entry(struct drm_device *dev, void *data, int idx, u8 *outp) 6117{ 6118 struct drm_nouveau_private *dev_priv = dev->dev_private; 6119 struct dcb_table *dcb = &dev_priv->vbios.dcb; 6120 u32 conf = (dcb->version >= 0x20) ? ROM32(outp[4]) : ROM32(outp[6]); 6121 u32 conn = ROM32(outp[0]); 6122 bool ret; 6123 6124 if (apply_dcb_encoder_quirks(dev, idx, &conn, &conf)) { 6125 struct dcb_entry *entry = new_dcb_entry(dcb); 6126 6127 NV_TRACEWARN(dev, "DCB outp %02d: %08x %08x\n", idx, conn, conf); 6128 6129 if (dcb->version >= 0x20) 6130 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry); 6131 else 6132 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry); 6133 if (!ret) 6134 return 1; /* stop parsing */ 6135 6136 /* Ignore the I2C index for on-chip TV-out, as there 6137 * are cards with bogus values (nv31m in bug 23212), 6138 * and it's otherwise useless. 6139 */ 6140 if (entry->type == OUTPUT_TV && 6141 entry->location == DCB_LOC_ON_CHIP) 6142 entry->i2c_index = 0x0f; 6143 } 6144 6145 return 0; 6146} 6147 6148static void 6149dcb_fake_connectors(struct nvbios *bios) 6150{ 6151 struct dcb_table *dcbt = &bios->dcb; 6152 u8 map[16] = { }; 6153 int i, idx = 0; 6154 6155 /* heuristic: if we ever get a non-zero connector field, assume 6156 * that all the indices are valid and we don't need fake them. 6157 */ 6158 for (i = 0; i < dcbt->entries; i++) { 6159 if (dcbt->entry[i].connector) 6160 return; 6161 } 6162 6163 /* no useful connector info available, we need to make it up 6164 * ourselves. the rule here is: anything on the same i2c bus 6165 * is considered to be on the same connector. any output 6166 * without an associated i2c bus is assigned its own unique 6167 * connector index. 6168 */ 6169 for (i = 0; i < dcbt->entries; i++) { 6170 u8 i2c = dcbt->entry[i].i2c_index; 6171 if (i2c == 0x0f) { 6172 dcbt->entry[i].connector = idx++; 6173 } else { 6174 if (!map[i2c]) 6175 map[i2c] = ++idx; 6176 dcbt->entry[i].connector = map[i2c] - 1; 6177 } 6178 } 6179 6180 /* if we created more than one connector, destroy the connector 6181 * table - just in case it has random, rather than stub, entries. 6182 */ 6183 if (i > 1) { 6184 u8 *conntab = dcb_conntab(bios->dev); 6185 if (conntab) 6186 conntab[0] = 0x00; 6187 } 6188} 6189 6190static int 6191parse_dcb_table(struct drm_device *dev, struct nvbios *bios) 6192{ 6193 struct dcb_table *dcb = &bios->dcb; 6194 u8 *dcbt, *conn; 6195 int idx; 6196 6197 dcbt = dcb_table(dev); 6198 if (!dcbt) { 6199 /* handle pre-DCB boards */ 6200 if (bios->type == NVBIOS_BMP) { 6201 fabricate_dcb_encoder_table(dev, bios); 6202 return 0; 6203 } 6204 6205 return -EINVAL; 6206 } 6207 6208 NV_TRACE(dev, "DCB version %d.%d\n", dcbt[0] >> 4, dcbt[0] & 0xf); 6209 6210 dcb->version = dcbt[0]; 6211 dcb_outp_foreach(dev, NULL, parse_dcb_entry); 6212 6213 /* 6214 * apart for v2.1+ not being known for requiring merging, this 6215 * guarantees dcbent->index is the index of the entry in the rom image 6216 */ 6217 if (dcb->version < 0x21) 6218 merge_like_dcb_entries(dev, dcb); 6219 6220 if (!dcb->entries) 6221 return -ENXIO; 6222 6223 /* dump connector table entries to log, if any exist */ 6224 idx = -1; 6225 while ((conn = dcb_conn(dev, ++idx))) { 6226 if (conn[0] != 0xff) { 6227 NV_TRACE(dev, "DCB conn %02d: ", idx); 6228 if (dcb_conntab(dev)[3] < 4) 6229 printk("%04x\n", ROM16(conn[0])); 6230 else 6231 printk("%08x\n", ROM32(conn[0])); 6232 } 6233 } 6234 dcb_fake_connectors(bios); 6235 return 0; 6236} 6237 6238static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry) 6239{ 6240 /* 6241 * The header following the "HWSQ" signature has the number of entries, 6242 * and the entry size 6243 * 6244 * An entry consists of a dword to write to the sequencer control reg 6245 * (0x00001304), followed by the ucode bytes, written sequentially, 6246 * starting at reg 0x00001400 6247 */ 6248 6249 uint8_t bytes_to_write; 6250 uint16_t hwsq_entry_offset; 6251 int i; 6252 6253 if (bios->data[hwsq_offset] <= entry) { 6254 NV_ERROR(dev, "Too few entries in HW sequencer table for " 6255 "requested entry\n"); 6256 return -ENOENT; 6257 } 6258 6259 bytes_to_write = bios->data[hwsq_offset + 1]; 6260 6261 if (bytes_to_write != 36) { 6262 NV_ERROR(dev, "Unknown HW sequencer entry size\n"); 6263 return -EINVAL; 6264 } 6265 6266 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n"); 6267 6268 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write; 6269 6270 /* set sequencer control */ 6271 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset])); 6272 bytes_to_write -= 4; 6273 6274 /* write ucode */ 6275 for (i = 0; i < bytes_to_write; i += 4) 6276 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4])); 6277 6278 /* twiddle NV_PBUS_DEBUG_4 */ 6279 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18); 6280 6281 return 0; 6282} 6283 6284static int load_nv17_hw_sequencer_ucode(struct drm_device *dev, 6285 struct nvbios *bios) 6286{ 6287 /* 6288 * BMP based cards, from NV17, need a microcode loading to correctly 6289 * control the GPIO etc for LVDS panels 6290 * 6291 * BIT based cards seem to do this directly in the init scripts 6292 * 6293 * The microcode entries are found by the "HWSQ" signature. 6294 */ 6295 6296 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' }; 6297 const int sz = sizeof(hwsq_signature); 6298 int hwsq_offset; 6299 6300 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz); 6301 if (!hwsq_offset) 6302 return 0; 6303 6304 /* always use entry 0? */ 6305 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0); 6306} 6307 6308uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev) 6309{ 6310 struct drm_nouveau_private *dev_priv = dev->dev_private; 6311 struct nvbios *bios = &dev_priv->vbios; 6312 const uint8_t edid_sig[] = { 6313 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 }; 6314 uint16_t offset = 0; 6315 uint16_t newoffset; 6316 int searchlen = NV_PROM_SIZE; 6317 6318 if (bios->fp.edid) 6319 return bios->fp.edid; 6320 6321 while (searchlen) { 6322 newoffset = findstr(&bios->data[offset], searchlen, 6323 edid_sig, 8); 6324 if (!newoffset) 6325 return NULL; 6326 offset += newoffset; 6327 if (!nv_cksum(&bios->data[offset], EDID1_LEN)) 6328 break; 6329 6330 searchlen -= offset; 6331 offset++; 6332 } 6333 6334 NV_TRACE(dev, "Found EDID in BIOS\n"); 6335 6336 return bios->fp.edid = &bios->data[offset]; 6337} 6338 6339void 6340nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table, 6341 struct dcb_entry *dcbent, int crtc) 6342{ 6343 struct drm_nouveau_private *dev_priv = dev->dev_private; 6344 struct nvbios *bios = &dev_priv->vbios; 6345 struct init_exec iexec = { true, false }; 6346 6347 spin_lock_bh(&bios->lock); 6348 bios->display.output = dcbent; 6349 bios->display.crtc = crtc; 6350 parse_init_table(bios, table, &iexec); 6351 bios->display.output = NULL; 6352 spin_unlock_bh(&bios->lock); 6353} 6354 6355void 6356nouveau_bios_init_exec(struct drm_device *dev, uint16_t table) 6357{ 6358 struct drm_nouveau_private *dev_priv = dev->dev_private; 6359 struct nvbios *bios = &dev_priv->vbios; 6360 struct init_exec iexec = { true, false }; 6361 6362 parse_init_table(bios, table, &iexec); 6363} 6364 6365static bool NVInitVBIOS(struct drm_device *dev) 6366{ 6367 struct drm_nouveau_private *dev_priv = dev->dev_private; 6368 struct nvbios *bios = &dev_priv->vbios; 6369 6370 memset(bios, 0, sizeof(struct nvbios)); 6371 spin_lock_init(&bios->lock); 6372 bios->dev = dev; 6373 6374 return bios_shadow(dev); 6375} 6376 6377static int nouveau_parse_vbios_struct(struct drm_device *dev) 6378{ 6379 struct drm_nouveau_private *dev_priv = dev->dev_private; 6380 struct nvbios *bios = &dev_priv->vbios; 6381 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' }; 6382 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 }; 6383 int offset; 6384 6385 offset = findstr(bios->data, bios->length, 6386 bit_signature, sizeof(bit_signature)); 6387 if (offset) { 6388 NV_TRACE(dev, "BIT BIOS found\n"); 6389 bios->type = NVBIOS_BIT; 6390 bios->offset = offset; 6391 return parse_bit_structure(bios, offset + 6); 6392 } 6393 6394 offset = findstr(bios->data, bios->length, 6395 bmp_signature, sizeof(bmp_signature)); 6396 if (offset) { 6397 NV_TRACE(dev, "BMP BIOS found\n"); 6398 bios->type = NVBIOS_BMP; 6399 bios->offset = offset; 6400 return parse_bmp_structure(dev, bios, offset); 6401 } 6402 6403 NV_ERROR(dev, "No known BIOS signature found\n"); 6404 return -ENODEV; 6405} 6406 6407int 6408nouveau_run_vbios_init(struct drm_device *dev) 6409{ 6410 struct drm_nouveau_private *dev_priv = dev->dev_private; 6411 struct nvbios *bios = &dev_priv->vbios; 6412 int i, ret = 0; 6413 6414 /* Reset the BIOS head to 0. */ 6415 bios->state.crtchead = 0; 6416 6417 if (bios->major_version < 5) /* BMP only */ 6418 load_nv17_hw_sequencer_ucode(dev, bios); 6419 6420 if (bios->execute) { 6421 bios->fp.last_script_invoc = 0; 6422 bios->fp.lvds_init_run = false; 6423 } 6424 6425 parse_init_tables(bios); 6426 6427 /* 6428 * Runs some additional script seen on G8x VBIOSen. The VBIOS' 6429 * parser will run this right after the init tables, the binary 6430 * driver appears to run it at some point later. 6431 */ 6432 if (bios->some_script_ptr) { 6433 struct init_exec iexec = {true, false}; 6434 6435 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n", 6436 bios->some_script_ptr); 6437 parse_init_table(bios, bios->some_script_ptr, &iexec); 6438 } 6439 6440 if (dev_priv->card_type >= NV_50) { 6441 for (i = 0; i < bios->dcb.entries; i++) { 6442 nouveau_bios_run_display_table(dev, 0, 0, 6443 &bios->dcb.entry[i], -1); 6444 } 6445 } 6446 6447 return ret; 6448} 6449 6450static bool 6451nouveau_bios_posted(struct drm_device *dev) 6452{ 6453 struct drm_nouveau_private *dev_priv = dev->dev_private; 6454 unsigned htotal; 6455 6456 if (dev_priv->card_type >= NV_50) { 6457 if (NVReadVgaCrtc(dev, 0, 0x00) == 0 && 6458 NVReadVgaCrtc(dev, 0, 0x1a) == 0) 6459 return false; 6460 return true; 6461 } 6462 6463 htotal = NVReadVgaCrtc(dev, 0, 0x06); 6464 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8; 6465 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4; 6466 htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10; 6467 htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11; 6468 6469 return (htotal != 0); 6470} 6471 6472int 6473nouveau_bios_init(struct drm_device *dev) 6474{ 6475 struct drm_nouveau_private *dev_priv = dev->dev_private; 6476 struct nvbios *bios = &dev_priv->vbios; 6477 int ret; 6478 6479 if (!NVInitVBIOS(dev)) 6480 return -ENODEV; 6481 6482 ret = nouveau_parse_vbios_struct(dev); 6483 if (ret) 6484 return ret; 6485 6486 ret = nouveau_i2c_init(dev); 6487 if (ret) 6488 return ret; 6489 6490 ret = nouveau_mxm_init(dev); 6491 if (ret) 6492 return ret; 6493 6494 ret = parse_dcb_table(dev, bios); 6495 if (ret) 6496 return ret; 6497 6498 if (!bios->major_version) /* we don't run version 0 bios */ 6499 return 0; 6500 6501 /* init script execution disabled */ 6502 bios->execute = false; 6503 6504 /* ... unless card isn't POSTed already */ 6505 if (!nouveau_bios_posted(dev)) { 6506 NV_INFO(dev, "Adaptor not initialised, " 6507 "running VBIOS init tables.\n"); 6508 bios->execute = true; 6509 } 6510 if (nouveau_force_post) 6511 bios->execute = true; 6512 6513 ret = nouveau_run_vbios_init(dev); 6514 if (ret) 6515 return ret; 6516 6517 /* feature_byte on BMP is poor, but init always sets CR4B */ 6518 if (bios->major_version < 5) 6519 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40; 6520 6521 /* all BIT systems need p_f_m_t for digital_min_front_porch */ 6522 if (bios->is_mobile || bios->major_version >= 5) 6523 ret = parse_fp_mode_table(dev, bios); 6524 6525 /* allow subsequent scripts to execute */ 6526 bios->execute = true; 6527 6528 return 0; 6529} 6530 6531void 6532nouveau_bios_takedown(struct drm_device *dev) 6533{ 6534 struct drm_nouveau_private *dev_priv = dev->dev_private; 6535 6536 nouveau_mxm_fini(dev); 6537 nouveau_i2c_fini(dev); 6538 6539 kfree(dev_priv->vbios.data); 6540} 6541