nouveau_bios.c revision 75a1fccf92ac6703e7cd4d2a2d1d25b87102402b
1/* 2 * Copyright 2005-2006 Erik Waling 3 * Copyright 2006 Stephane Marchesin 4 * Copyright 2007-2009 Stuart Bennett 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 25#include "drmP.h" 26#define NV_DEBUG_NOTRACE 27#include "nouveau_drv.h" 28#include "nouveau_hw.h" 29#include "nouveau_encoder.h" 30 31#include <linux/io-mapping.h> 32 33/* these defines are made up */ 34#define NV_CIO_CRE_44_HEADA 0x0 35#define NV_CIO_CRE_44_HEADB 0x3 36#define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */ 37#define LEGACY_I2C_CRT 0x80 38#define LEGACY_I2C_PANEL 0x81 39#define LEGACY_I2C_TV 0x82 40 41#define EDID1_LEN 128 42 43#define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg) 44#define LOG_OLD_VALUE(x) 45 46struct init_exec { 47 bool execute; 48 bool repeat; 49}; 50 51static bool nv_cksum(const uint8_t *data, unsigned int length) 52{ 53 /* 54 * There's a few checksums in the BIOS, so here's a generic checking 55 * function. 56 */ 57 int i; 58 uint8_t sum = 0; 59 60 for (i = 0; i < length; i++) 61 sum += data[i]; 62 63 if (sum) 64 return true; 65 66 return false; 67} 68 69static int 70score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable) 71{ 72 if (!(data[0] == 0x55 && data[1] == 0xAA)) { 73 NV_TRACEWARN(dev, "... BIOS signature not found\n"); 74 return 0; 75 } 76 77 if (nv_cksum(data, data[2] * 512)) { 78 NV_TRACEWARN(dev, "... BIOS checksum invalid\n"); 79 /* if a ro image is somewhat bad, it's probably all rubbish */ 80 return writeable ? 2 : 1; 81 } else 82 NV_TRACE(dev, "... appears to be valid\n"); 83 84 return 3; 85} 86 87static void load_vbios_prom(struct drm_device *dev, uint8_t *data) 88{ 89 struct drm_nouveau_private *dev_priv = dev->dev_private; 90 uint32_t pci_nv_20, save_pci_nv_20; 91 int pcir_ptr; 92 int i; 93 94 if (dev_priv->card_type >= NV_50) 95 pci_nv_20 = 0x88050; 96 else 97 pci_nv_20 = NV_PBUS_PCI_NV_20; 98 99 /* enable ROM access */ 100 save_pci_nv_20 = nvReadMC(dev, pci_nv_20); 101 nvWriteMC(dev, pci_nv_20, 102 save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED); 103 104 /* bail if no rom signature */ 105 if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 || 106 nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa) 107 goto out; 108 109 /* additional check (see note below) - read PCI record header */ 110 pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) | 111 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8; 112 if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' || 113 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' || 114 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' || 115 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R') 116 goto out; 117 118 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a 119 * a good read may be obtained by waiting or re-reading (cargocult: 5x) 120 * each byte. we'll hope pramin has something usable instead 121 */ 122 for (i = 0; i < NV_PROM_SIZE; i++) 123 data[i] = nv_rd08(dev, NV_PROM_OFFSET + i); 124 125out: 126 /* disable ROM access */ 127 nvWriteMC(dev, pci_nv_20, 128 save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED); 129} 130 131static void load_vbios_pramin(struct drm_device *dev, uint8_t *data) 132{ 133 struct drm_nouveau_private *dev_priv = dev->dev_private; 134 uint32_t old_bar0_pramin = 0; 135 int i; 136 137 if (dev_priv->card_type >= NV_50) { 138 u64 addr = (u64)(nv_rd32(dev, 0x619f04) & 0xffffff00) << 8; 139 if (!addr) { 140 addr = (u64)nv_rd32(dev, 0x1700) << 16; 141 addr += 0xf0000; 142 } 143 144 old_bar0_pramin = nv_rd32(dev, 0x1700); 145 nv_wr32(dev, 0x1700, addr >> 16); 146 } 147 148 /* bail if no rom signature */ 149 if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 || 150 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa) 151 goto out; 152 153 for (i = 0; i < NV_PROM_SIZE; i++) 154 data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i); 155 156out: 157 if (dev_priv->card_type >= NV_50) 158 nv_wr32(dev, 0x1700, old_bar0_pramin); 159} 160 161static void load_vbios_pci(struct drm_device *dev, uint8_t *data) 162{ 163 void __iomem *rom = NULL; 164 size_t rom_len; 165 int ret; 166 167 ret = pci_enable_rom(dev->pdev); 168 if (ret) 169 return; 170 171 rom = pci_map_rom(dev->pdev, &rom_len); 172 if (!rom) 173 goto out; 174 memcpy_fromio(data, rom, rom_len); 175 pci_unmap_rom(dev->pdev, rom); 176 177out: 178 pci_disable_rom(dev->pdev); 179} 180 181static void load_vbios_acpi(struct drm_device *dev, uint8_t *data) 182{ 183 int i; 184 int ret; 185 int size = 64 * 1024; 186 187 if (!nouveau_acpi_rom_supported(dev->pdev)) 188 return; 189 190 for (i = 0; i < (size / ROM_BIOS_PAGE); i++) { 191 ret = nouveau_acpi_get_bios_chunk(data, 192 (i * ROM_BIOS_PAGE), 193 ROM_BIOS_PAGE); 194 if (ret <= 0) 195 break; 196 } 197 return; 198} 199 200struct methods { 201 const char desc[8]; 202 void (*loadbios)(struct drm_device *, uint8_t *); 203 const bool rw; 204}; 205 206static struct methods shadow_methods[] = { 207 { "PRAMIN", load_vbios_pramin, true }, 208 { "PROM", load_vbios_prom, false }, 209 { "PCIROM", load_vbios_pci, true }, 210 { "ACPI", load_vbios_acpi, true }, 211}; 212#define NUM_SHADOW_METHODS ARRAY_SIZE(shadow_methods) 213 214static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data) 215{ 216 struct methods *methods = shadow_methods; 217 int testscore = 3; 218 int scores[NUM_SHADOW_METHODS], i; 219 220 if (nouveau_vbios) { 221 for (i = 0; i < NUM_SHADOW_METHODS; i++) 222 if (!strcasecmp(nouveau_vbios, methods[i].desc)) 223 break; 224 225 if (i < NUM_SHADOW_METHODS) { 226 NV_INFO(dev, "Attempting to use BIOS image from %s\n", 227 methods[i].desc); 228 229 methods[i].loadbios(dev, data); 230 if (score_vbios(dev, data, methods[i].rw)) 231 return true; 232 } 233 234 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios); 235 } 236 237 for (i = 0; i < NUM_SHADOW_METHODS; i++) { 238 NV_TRACE(dev, "Attempting to load BIOS image from %s\n", 239 methods[i].desc); 240 data[0] = data[1] = 0; /* avoid reuse of previous image */ 241 methods[i].loadbios(dev, data); 242 scores[i] = score_vbios(dev, data, methods[i].rw); 243 if (scores[i] == testscore) 244 return true; 245 } 246 247 while (--testscore > 0) { 248 for (i = 0; i < NUM_SHADOW_METHODS; i++) { 249 if (scores[i] == testscore) { 250 NV_TRACE(dev, "Using BIOS image from %s\n", 251 methods[i].desc); 252 methods[i].loadbios(dev, data); 253 return true; 254 } 255 } 256 } 257 258 NV_ERROR(dev, "No valid BIOS image found\n"); 259 return false; 260} 261 262struct init_tbl_entry { 263 char *name; 264 uint8_t id; 265 /* Return: 266 * > 0: success, length of opcode 267 * 0: success, but abort further parsing of table (INIT_DONE etc) 268 * < 0: failure, table parsing will be aborted 269 */ 270 int (*handler)(struct nvbios *, uint16_t, struct init_exec *); 271}; 272 273static int parse_init_table(struct nvbios *, uint16_t, struct init_exec *); 274 275#define MACRO_INDEX_SIZE 2 276#define MACRO_SIZE 8 277#define CONDITION_SIZE 12 278#define IO_FLAG_CONDITION_SIZE 9 279#define IO_CONDITION_SIZE 5 280#define MEM_INIT_SIZE 66 281 282static void still_alive(void) 283{ 284#if 0 285 sync(); 286 mdelay(2); 287#endif 288} 289 290static uint32_t 291munge_reg(struct nvbios *bios, uint32_t reg) 292{ 293 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 294 struct dcb_entry *dcbent = bios->display.output; 295 296 if (dev_priv->card_type < NV_50) 297 return reg; 298 299 if (reg & 0x80000000) { 300 BUG_ON(bios->display.crtc < 0); 301 reg += bios->display.crtc * 0x800; 302 } 303 304 if (reg & 0x40000000) { 305 BUG_ON(!dcbent); 306 307 reg += (ffs(dcbent->or) - 1) * 0x800; 308 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1)) 309 reg += 0x00000080; 310 } 311 312 reg &= ~0xe0000000; 313 return reg; 314} 315 316static int 317valid_reg(struct nvbios *bios, uint32_t reg) 318{ 319 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 320 struct drm_device *dev = bios->dev; 321 322 /* C51 has misaligned regs on purpose. Marvellous */ 323 if (reg & 0x2 || 324 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51)) 325 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg); 326 327 /* warn on C51 regs that haven't been verified accessible in tracing */ 328 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 && 329 reg != 0x130d && reg != 0x1311 && reg != 0x60081d) 330 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n", 331 reg); 332 333 if (reg >= (8*1024*1024)) { 334 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg); 335 return 0; 336 } 337 338 return 1; 339} 340 341static bool 342valid_idx_port(struct nvbios *bios, uint16_t port) 343{ 344 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 345 struct drm_device *dev = bios->dev; 346 347 /* 348 * If adding more ports here, the read/write functions below will need 349 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is 350 * used for the port in question 351 */ 352 if (dev_priv->card_type < NV_50) { 353 if (port == NV_CIO_CRX__COLOR) 354 return true; 355 if (port == NV_VIO_SRX) 356 return true; 357 } else { 358 if (port == NV_CIO_CRX__COLOR) 359 return true; 360 } 361 362 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n", 363 port); 364 365 return false; 366} 367 368static bool 369valid_port(struct nvbios *bios, uint16_t port) 370{ 371 struct drm_device *dev = bios->dev; 372 373 /* 374 * If adding more ports here, the read/write functions below will need 375 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is 376 * used for the port in question 377 */ 378 if (port == NV_VIO_VSE2) 379 return true; 380 381 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port); 382 383 return false; 384} 385 386static uint32_t 387bios_rd32(struct nvbios *bios, uint32_t reg) 388{ 389 uint32_t data; 390 391 reg = munge_reg(bios, reg); 392 if (!valid_reg(bios, reg)) 393 return 0; 394 395 /* 396 * C51 sometimes uses regs with bit0 set in the address. For these 397 * cases there should exist a translation in a BIOS table to an IO 398 * port address which the BIOS uses for accessing the reg 399 * 400 * These only seem to appear for the power control regs to a flat panel, 401 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs 402 * for 0x1308 and 0x1310 are used - hence the mask below. An S3 403 * suspend-resume mmio trace from a C51 will be required to see if this 404 * is true for the power microcode in 0x14.., or whether the direct IO 405 * port access method is needed 406 */ 407 if (reg & 0x1) 408 reg &= ~0x1; 409 410 data = nv_rd32(bios->dev, reg); 411 412 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data); 413 414 return data; 415} 416 417static void 418bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data) 419{ 420 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 421 422 reg = munge_reg(bios, reg); 423 if (!valid_reg(bios, reg)) 424 return; 425 426 /* see note in bios_rd32 */ 427 if (reg & 0x1) 428 reg &= 0xfffffffe; 429 430 LOG_OLD_VALUE(bios_rd32(bios, reg)); 431 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data); 432 433 if (dev_priv->vbios.execute) { 434 still_alive(); 435 nv_wr32(bios->dev, reg, data); 436 } 437} 438 439static uint8_t 440bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index) 441{ 442 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 443 struct drm_device *dev = bios->dev; 444 uint8_t data; 445 446 if (!valid_idx_port(bios, port)) 447 return 0; 448 449 if (dev_priv->card_type < NV_50) { 450 if (port == NV_VIO_SRX) 451 data = NVReadVgaSeq(dev, bios->state.crtchead, index); 452 else /* assume NV_CIO_CRX__COLOR */ 453 data = NVReadVgaCrtc(dev, bios->state.crtchead, index); 454 } else { 455 uint32_t data32; 456 457 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3)); 458 data = (data32 >> ((index & 3) << 3)) & 0xff; 459 } 460 461 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, " 462 "Head: 0x%02X, Data: 0x%02X\n", 463 port, index, bios->state.crtchead, data); 464 return data; 465} 466 467static void 468bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data) 469{ 470 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 471 struct drm_device *dev = bios->dev; 472 473 if (!valid_idx_port(bios, port)) 474 return; 475 476 /* 477 * The current head is maintained in the nvbios member state.crtchead. 478 * We trap changes to CR44 and update the head variable and hence the 479 * register set written. 480 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance 481 * of the write, and to head1 after the write 482 */ 483 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 && 484 data != NV_CIO_CRE_44_HEADB) 485 bios->state.crtchead = 0; 486 487 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index)); 488 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, " 489 "Head: 0x%02X, Data: 0x%02X\n", 490 port, index, bios->state.crtchead, data); 491 492 if (bios->execute && dev_priv->card_type < NV_50) { 493 still_alive(); 494 if (port == NV_VIO_SRX) 495 NVWriteVgaSeq(dev, bios->state.crtchead, index, data); 496 else /* assume NV_CIO_CRX__COLOR */ 497 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data); 498 } else 499 if (bios->execute) { 500 uint32_t data32, shift = (index & 3) << 3; 501 502 still_alive(); 503 504 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3)); 505 data32 &= ~(0xff << shift); 506 data32 |= (data << shift); 507 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32); 508 } 509 510 if (port == NV_CIO_CRX__COLOR && 511 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB) 512 bios->state.crtchead = 1; 513} 514 515static uint8_t 516bios_port_rd(struct nvbios *bios, uint16_t port) 517{ 518 uint8_t data, head = bios->state.crtchead; 519 520 if (!valid_port(bios, port)) 521 return 0; 522 523 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port); 524 525 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n", 526 port, head, data); 527 528 return data; 529} 530 531static void 532bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data) 533{ 534 int head = bios->state.crtchead; 535 536 if (!valid_port(bios, port)) 537 return; 538 539 LOG_OLD_VALUE(bios_port_rd(bios, port)); 540 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n", 541 port, head, data); 542 543 if (!bios->execute) 544 return; 545 546 still_alive(); 547 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data); 548} 549 550static bool 551io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 552{ 553 /* 554 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte 555 * for the CRTC index; 1 byte for the mask to apply to the value 556 * retrieved from the CRTC; 1 byte for the shift right to apply to the 557 * masked CRTC value; 2 bytes for the offset to the flag array, to 558 * which the shifted value is added; 1 byte for the mask applied to the 559 * value read from the flag array; and 1 byte for the value to compare 560 * against the masked byte from the flag table. 561 */ 562 563 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE; 564 uint16_t crtcport = ROM16(bios->data[condptr]); 565 uint8_t crtcindex = bios->data[condptr + 2]; 566 uint8_t mask = bios->data[condptr + 3]; 567 uint8_t shift = bios->data[condptr + 4]; 568 uint16_t flagarray = ROM16(bios->data[condptr + 5]); 569 uint8_t flagarraymask = bios->data[condptr + 7]; 570 uint8_t cmpval = bios->data[condptr + 8]; 571 uint8_t data; 572 573 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 574 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, " 575 "Cmpval: 0x%02X\n", 576 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval); 577 578 data = bios_idxprt_rd(bios, crtcport, crtcindex); 579 580 data = bios->data[flagarray + ((data & mask) >> shift)]; 581 data &= flagarraymask; 582 583 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n", 584 offset, data, cmpval); 585 586 return (data == cmpval); 587} 588 589static bool 590bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 591{ 592 /* 593 * The condition table entry has 4 bytes for the address of the 594 * register to check, 4 bytes for a mask to apply to the register and 595 * 4 for a test comparison value 596 */ 597 598 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE; 599 uint32_t reg = ROM32(bios->data[condptr]); 600 uint32_t mask = ROM32(bios->data[condptr + 4]); 601 uint32_t cmpval = ROM32(bios->data[condptr + 8]); 602 uint32_t data; 603 604 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n", 605 offset, cond, reg, mask); 606 607 data = bios_rd32(bios, reg) & mask; 608 609 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n", 610 offset, data, cmpval); 611 612 return (data == cmpval); 613} 614 615static bool 616io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 617{ 618 /* 619 * The IO condition entry has 2 bytes for the IO port address; 1 byte 620 * for the index to write to io_port; 1 byte for the mask to apply to 621 * the byte read from io_port+1; and 1 byte for the value to compare 622 * against the masked byte. 623 */ 624 625 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE; 626 uint16_t io_port = ROM16(bios->data[condptr]); 627 uint8_t port_index = bios->data[condptr + 2]; 628 uint8_t mask = bios->data[condptr + 3]; 629 uint8_t cmpval = bios->data[condptr + 4]; 630 631 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask; 632 633 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n", 634 offset, data, cmpval); 635 636 return (data == cmpval); 637} 638 639static int 640nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk) 641{ 642 struct drm_nouveau_private *dev_priv = dev->dev_private; 643 uint32_t reg0 = nv_rd32(dev, reg + 0); 644 uint32_t reg1 = nv_rd32(dev, reg + 4); 645 struct nouveau_pll_vals pll; 646 struct pll_lims pll_limits; 647 int ret; 648 649 ret = get_pll_limits(dev, reg, &pll_limits); 650 if (ret) 651 return ret; 652 653 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll); 654 if (!clk) 655 return -ERANGE; 656 657 reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16); 658 reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1; 659 660 if (dev_priv->vbios.execute) { 661 still_alive(); 662 nv_wr32(dev, reg + 4, reg1); 663 nv_wr32(dev, reg + 0, reg0); 664 } 665 666 return 0; 667} 668 669static int 670setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk) 671{ 672 struct drm_device *dev = bios->dev; 673 struct drm_nouveau_private *dev_priv = dev->dev_private; 674 /* clk in kHz */ 675 struct pll_lims pll_lim; 676 struct nouveau_pll_vals pllvals; 677 int ret; 678 679 if (dev_priv->card_type >= NV_50) 680 return nv50_pll_set(dev, reg, clk); 681 682 /* high regs (such as in the mac g5 table) are not -= 4 */ 683 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim); 684 if (ret) 685 return ret; 686 687 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals); 688 if (!clk) 689 return -ERANGE; 690 691 if (bios->execute) { 692 still_alive(); 693 nouveau_hw_setpll(dev, reg, &pllvals); 694 } 695 696 return 0; 697} 698 699static int dcb_entry_idx_from_crtchead(struct drm_device *dev) 700{ 701 struct drm_nouveau_private *dev_priv = dev->dev_private; 702 struct nvbios *bios = &dev_priv->vbios; 703 704 /* 705 * For the results of this function to be correct, CR44 must have been 706 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0, 707 * and the DCB table parsed, before the script calling the function is 708 * run. run_digital_op_script is example of how to do such setup 709 */ 710 711 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0); 712 713 if (dcb_entry > bios->dcb.entries) { 714 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently " 715 "(%02X)\n", dcb_entry); 716 dcb_entry = 0x7f; /* unused / invalid marker */ 717 } 718 719 return dcb_entry; 720} 721 722static int 723read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, int index, struct dcb_i2c_entry *i2c) 724{ 725 uint8_t dcb_i2c_ver = dcb_version, headerlen = 0, entry_len = 4; 726 int i2c_entries = DCB_MAX_NUM_I2C_ENTRIES; 727 int recordoffset = 0, rdofs = 1, wrofs = 0; 728 uint8_t port_type = 0; 729 730 if (!i2ctable) 731 return -EINVAL; 732 733 if (dcb_version >= 0x30) { 734 if (i2ctable[0] != dcb_version) /* necessary? */ 735 NV_WARN(dev, 736 "DCB I2C table version mismatch (%02X vs %02X)\n", 737 i2ctable[0], dcb_version); 738 dcb_i2c_ver = i2ctable[0]; 739 headerlen = i2ctable[1]; 740 if (i2ctable[2] <= DCB_MAX_NUM_I2C_ENTRIES) 741 i2c_entries = i2ctable[2]; 742 else 743 NV_WARN(dev, 744 "DCB I2C table has more entries than indexable " 745 "(%d entries, max %d)\n", i2ctable[2], 746 DCB_MAX_NUM_I2C_ENTRIES); 747 entry_len = i2ctable[3]; 748 /* [4] is i2c_default_indices, read in parse_dcb_table() */ 749 } 750 /* 751 * It's your own fault if you call this function on a DCB 1.1 BIOS -- 752 * the test below is for DCB 1.2 753 */ 754 if (dcb_version < 0x14) { 755 recordoffset = 2; 756 rdofs = 0; 757 wrofs = 1; 758 } 759 760 if (index == 0xf) 761 return 0; 762 if (index >= i2c_entries) { 763 NV_ERROR(dev, "DCB I2C index too big (%d >= %d)\n", 764 index, i2ctable[2]); 765 return -ENOENT; 766 } 767 if (i2ctable[headerlen + entry_len * index + 3] == 0xff) { 768 NV_ERROR(dev, "DCB I2C entry invalid\n"); 769 return -EINVAL; 770 } 771 772 if (dcb_i2c_ver >= 0x30) { 773 port_type = i2ctable[headerlen + recordoffset + 3 + entry_len * index]; 774 775 /* 776 * Fixup for chips using same address offset for read and 777 * write. 778 */ 779 if (port_type == 4) /* seen on C51 */ 780 rdofs = wrofs = 1; 781 if (port_type >= 5) /* G80+ */ 782 rdofs = wrofs = 0; 783 } 784 785 if (dcb_i2c_ver >= 0x40) { 786 if (port_type != 5 && port_type != 6) 787 NV_WARN(dev, "DCB I2C table has port type %d\n", port_type); 788 789 i2c->entry = ROM32(i2ctable[headerlen + recordoffset + entry_len * index]); 790 } 791 792 i2c->port_type = port_type; 793 i2c->read = i2ctable[headerlen + recordoffset + rdofs + entry_len * index]; 794 i2c->write = i2ctable[headerlen + recordoffset + wrofs + entry_len * index]; 795 796 return 0; 797} 798 799static struct nouveau_i2c_chan * 800init_i2c_device_find(struct drm_device *dev, int i2c_index) 801{ 802 struct drm_nouveau_private *dev_priv = dev->dev_private; 803 struct dcb_table *dcb = &dev_priv->vbios.dcb; 804 805 if (i2c_index == 0xff) { 806 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */ 807 int idx = dcb_entry_idx_from_crtchead(dev), shift = 0; 808 int default_indices = dcb->i2c_default_indices; 809 810 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default) 811 shift = 4; 812 813 i2c_index = (default_indices >> shift) & 0xf; 814 } 815 if (i2c_index == 0x80) /* g80+ */ 816 i2c_index = dcb->i2c_default_indices & 0xf; 817 else 818 if (i2c_index == 0x81) 819 i2c_index = (dcb->i2c_default_indices & 0xf0) >> 4; 820 821 if (i2c_index >= DCB_MAX_NUM_I2C_ENTRIES) { 822 NV_ERROR(dev, "invalid i2c_index 0x%x\n", i2c_index); 823 return NULL; 824 } 825 826 /* Make sure i2c table entry has been parsed, it may not 827 * have been if this is a bus not referenced by a DCB encoder 828 */ 829 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table, 830 i2c_index, &dcb->i2c[i2c_index]); 831 832 return nouveau_i2c_find(dev, i2c_index); 833} 834 835static uint32_t 836get_tmds_index_reg(struct drm_device *dev, uint8_t mlv) 837{ 838 /* 839 * For mlv < 0x80, it is an index into a table of TMDS base addresses. 840 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by 841 * CR58 for CR57 = 0 to index a table of offsets to the basic 842 * 0x6808b0 address. 843 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by 844 * CR58 for CR57 = 0 to index a table of offsets to the basic 845 * 0x6808b0 address, and then flip the offset by 8. 846 */ 847 848 struct drm_nouveau_private *dev_priv = dev->dev_private; 849 struct nvbios *bios = &dev_priv->vbios; 850 const int pramdac_offset[13] = { 851 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 }; 852 const uint32_t pramdac_table[4] = { 853 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 }; 854 855 if (mlv >= 0x80) { 856 int dcb_entry, dacoffset; 857 858 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */ 859 dcb_entry = dcb_entry_idx_from_crtchead(dev); 860 if (dcb_entry == 0x7f) 861 return 0; 862 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or]; 863 if (mlv == 0x81) 864 dacoffset ^= 8; 865 return 0x6808b0 + dacoffset; 866 } else { 867 if (mlv >= ARRAY_SIZE(pramdac_table)) { 868 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n", 869 mlv); 870 return 0; 871 } 872 return pramdac_table[mlv]; 873 } 874} 875 876static int 877init_io_restrict_prog(struct nvbios *bios, uint16_t offset, 878 struct init_exec *iexec) 879{ 880 /* 881 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2') 882 * 883 * offset (8 bit): opcode 884 * offset + 1 (16 bit): CRTC port 885 * offset + 3 (8 bit): CRTC index 886 * offset + 4 (8 bit): mask 887 * offset + 5 (8 bit): shift 888 * offset + 6 (8 bit): count 889 * offset + 7 (32 bit): register 890 * offset + 11 (32 bit): configuration 1 891 * ... 892 * 893 * Starting at offset + 11 there are "count" 32 bit values. 894 * To find out which value to use read index "CRTC index" on "CRTC 895 * port", AND this value with "mask" and then bit shift right "shift" 896 * bits. Read the appropriate value using this index and write to 897 * "register" 898 */ 899 900 uint16_t crtcport = ROM16(bios->data[offset + 1]); 901 uint8_t crtcindex = bios->data[offset + 3]; 902 uint8_t mask = bios->data[offset + 4]; 903 uint8_t shift = bios->data[offset + 5]; 904 uint8_t count = bios->data[offset + 6]; 905 uint32_t reg = ROM32(bios->data[offset + 7]); 906 uint8_t config; 907 uint32_t configval; 908 int len = 11 + count * 4; 909 910 if (!iexec->execute) 911 return len; 912 913 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 914 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n", 915 offset, crtcport, crtcindex, mask, shift, count, reg); 916 917 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 918 if (config > count) { 919 NV_ERROR(bios->dev, 920 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 921 offset, config, count); 922 return len; 923 } 924 925 configval = ROM32(bios->data[offset + 11 + config * 4]); 926 927 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config); 928 929 bios_wr32(bios, reg, configval); 930 931 return len; 932} 933 934static int 935init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 936{ 937 /* 938 * INIT_REPEAT opcode: 0x33 ('3') 939 * 940 * offset (8 bit): opcode 941 * offset + 1 (8 bit): count 942 * 943 * Execute script following this opcode up to INIT_REPEAT_END 944 * "count" times 945 */ 946 947 uint8_t count = bios->data[offset + 1]; 948 uint8_t i; 949 950 /* no iexec->execute check by design */ 951 952 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n", 953 offset, count); 954 955 iexec->repeat = true; 956 957 /* 958 * count - 1, as the script block will execute once when we leave this 959 * opcode -- this is compatible with bios behaviour as: 960 * a) the block is always executed at least once, even if count == 0 961 * b) the bios interpreter skips to the op following INIT_END_REPEAT, 962 * while we don't 963 */ 964 for (i = 0; i < count - 1; i++) 965 parse_init_table(bios, offset + 2, iexec); 966 967 iexec->repeat = false; 968 969 return 2; 970} 971 972static int 973init_io_restrict_pll(struct nvbios *bios, uint16_t offset, 974 struct init_exec *iexec) 975{ 976 /* 977 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4') 978 * 979 * offset (8 bit): opcode 980 * offset + 1 (16 bit): CRTC port 981 * offset + 3 (8 bit): CRTC index 982 * offset + 4 (8 bit): mask 983 * offset + 5 (8 bit): shift 984 * offset + 6 (8 bit): IO flag condition index 985 * offset + 7 (8 bit): count 986 * offset + 8 (32 bit): register 987 * offset + 12 (16 bit): frequency 1 988 * ... 989 * 990 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz). 991 * Set PLL register "register" to coefficients for frequency n, 992 * selected by reading index "CRTC index" of "CRTC port" ANDed with 993 * "mask" and shifted right by "shift". 994 * 995 * If "IO flag condition index" > 0, and condition met, double 996 * frequency before setting it. 997 */ 998 999 uint16_t crtcport = ROM16(bios->data[offset + 1]); 1000 uint8_t crtcindex = bios->data[offset + 3]; 1001 uint8_t mask = bios->data[offset + 4]; 1002 uint8_t shift = bios->data[offset + 5]; 1003 int8_t io_flag_condition_idx = bios->data[offset + 6]; 1004 uint8_t count = bios->data[offset + 7]; 1005 uint32_t reg = ROM32(bios->data[offset + 8]); 1006 uint8_t config; 1007 uint16_t freq; 1008 int len = 12 + count * 2; 1009 1010 if (!iexec->execute) 1011 return len; 1012 1013 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 1014 "Shift: 0x%02X, IO Flag Condition: 0x%02X, " 1015 "Count: 0x%02X, Reg: 0x%08X\n", 1016 offset, crtcport, crtcindex, mask, shift, 1017 io_flag_condition_idx, count, reg); 1018 1019 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 1020 if (config > count) { 1021 NV_ERROR(bios->dev, 1022 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 1023 offset, config, count); 1024 return len; 1025 } 1026 1027 freq = ROM16(bios->data[offset + 12 + config * 2]); 1028 1029 if (io_flag_condition_idx > 0) { 1030 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) { 1031 BIOSLOG(bios, "0x%04X: Condition fulfilled -- " 1032 "frequency doubled\n", offset); 1033 freq *= 2; 1034 } else 1035 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- " 1036 "frequency unchanged\n", offset); 1037 } 1038 1039 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n", 1040 offset, reg, config, freq); 1041 1042 setPLL(bios, reg, freq * 10); 1043 1044 return len; 1045} 1046 1047static int 1048init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1049{ 1050 /* 1051 * INIT_END_REPEAT opcode: 0x36 ('6') 1052 * 1053 * offset (8 bit): opcode 1054 * 1055 * Marks the end of the block for INIT_REPEAT to repeat 1056 */ 1057 1058 /* no iexec->execute check by design */ 1059 1060 /* 1061 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when 1062 * we're not in repeat mode 1063 */ 1064 if (iexec->repeat) 1065 return 0; 1066 1067 return 1; 1068} 1069 1070static int 1071init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1072{ 1073 /* 1074 * INIT_COPY opcode: 0x37 ('7') 1075 * 1076 * offset (8 bit): opcode 1077 * offset + 1 (32 bit): register 1078 * offset + 5 (8 bit): shift 1079 * offset + 6 (8 bit): srcmask 1080 * offset + 7 (16 bit): CRTC port 1081 * offset + 9 (8 bit): CRTC index 1082 * offset + 10 (8 bit): mask 1083 * 1084 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with 1085 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC 1086 * port 1087 */ 1088 1089 uint32_t reg = ROM32(bios->data[offset + 1]); 1090 uint8_t shift = bios->data[offset + 5]; 1091 uint8_t srcmask = bios->data[offset + 6]; 1092 uint16_t crtcport = ROM16(bios->data[offset + 7]); 1093 uint8_t crtcindex = bios->data[offset + 9]; 1094 uint8_t mask = bios->data[offset + 10]; 1095 uint32_t data; 1096 uint8_t crtcdata; 1097 1098 if (!iexec->execute) 1099 return 11; 1100 1101 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, " 1102 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n", 1103 offset, reg, shift, srcmask, crtcport, crtcindex, mask); 1104 1105 data = bios_rd32(bios, reg); 1106 1107 if (shift < 0x80) 1108 data >>= shift; 1109 else 1110 data <<= (0x100 - shift); 1111 1112 data &= srcmask; 1113 1114 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask; 1115 crtcdata |= (uint8_t)data; 1116 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata); 1117 1118 return 11; 1119} 1120 1121static int 1122init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1123{ 1124 /* 1125 * INIT_NOT opcode: 0x38 ('8') 1126 * 1127 * offset (8 bit): opcode 1128 * 1129 * Invert the current execute / no-execute condition (i.e. "else") 1130 */ 1131 if (iexec->execute) 1132 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset); 1133 else 1134 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset); 1135 1136 iexec->execute = !iexec->execute; 1137 return 1; 1138} 1139 1140static int 1141init_io_flag_condition(struct nvbios *bios, uint16_t offset, 1142 struct init_exec *iexec) 1143{ 1144 /* 1145 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9') 1146 * 1147 * offset (8 bit): opcode 1148 * offset + 1 (8 bit): condition number 1149 * 1150 * Check condition "condition number" in the IO flag condition table. 1151 * If condition not met skip subsequent opcodes until condition is 1152 * inverted (INIT_NOT), or we hit INIT_RESUME 1153 */ 1154 1155 uint8_t cond = bios->data[offset + 1]; 1156 1157 if (!iexec->execute) 1158 return 2; 1159 1160 if (io_flag_condition_met(bios, offset, cond)) 1161 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 1162 else { 1163 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 1164 iexec->execute = false; 1165 } 1166 1167 return 2; 1168} 1169 1170static int 1171init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1172{ 1173 /* 1174 * INIT_DP_CONDITION opcode: 0x3A ('') 1175 * 1176 * offset (8 bit): opcode 1177 * offset + 1 (8 bit): "sub" opcode 1178 * offset + 2 (8 bit): unknown 1179 * 1180 */ 1181 1182 struct dcb_entry *dcb = bios->display.output; 1183 struct drm_device *dev = bios->dev; 1184 uint8_t cond = bios->data[offset + 1]; 1185 uint8_t *table, headerlen; 1186 1187 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond); 1188 1189 if (!iexec->execute) 1190 return 3; 1191 1192 table = nouveau_bios_dp_table(dev, dcb, &headerlen); 1193 if (!table) { 1194 NV_ERROR(dev, "0x%04X: INIT_3A: no encoder table!!\n", offset); 1195 return 3; 1196 } 1197 1198 switch (cond) { 1199 case 0: 1200 { 1201 struct dcb_connector_table_entry *ent = 1202 &bios->dcb.connector.entry[dcb->connector]; 1203 1204 if (ent->type != DCB_CONNECTOR_eDP) 1205 iexec->execute = false; 1206 } 1207 break; 1208 case 1: 1209 case 2: 1210 if (!(table[5] & cond)) 1211 iexec->execute = false; 1212 break; 1213 case 5: 1214 { 1215 struct nouveau_i2c_chan *auxch; 1216 int ret; 1217 1218 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index); 1219 if (!auxch) { 1220 NV_ERROR(dev, "0x%04X: couldn't get auxch\n", offset); 1221 return 3; 1222 } 1223 1224 ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1); 1225 if (ret) { 1226 NV_ERROR(dev, "0x%04X: auxch rd fail: %d\n", offset, ret); 1227 return 3; 1228 } 1229 1230 if (!(cond & 1)) 1231 iexec->execute = false; 1232 } 1233 break; 1234 default: 1235 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond); 1236 break; 1237 } 1238 1239 if (iexec->execute) 1240 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset); 1241 else 1242 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset); 1243 1244 return 3; 1245} 1246 1247static int 1248init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1249{ 1250 /* 1251 * INIT_3B opcode: 0x3B ('') 1252 * 1253 * offset (8 bit): opcode 1254 * offset + 1 (8 bit): crtc index 1255 * 1256 */ 1257 1258 uint8_t or = ffs(bios->display.output->or) - 1; 1259 uint8_t index = bios->data[offset + 1]; 1260 uint8_t data; 1261 1262 if (!iexec->execute) 1263 return 2; 1264 1265 data = bios_idxprt_rd(bios, 0x3d4, index); 1266 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or)); 1267 return 2; 1268} 1269 1270static int 1271init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1272{ 1273 /* 1274 * INIT_3C opcode: 0x3C ('') 1275 * 1276 * offset (8 bit): opcode 1277 * offset + 1 (8 bit): crtc index 1278 * 1279 */ 1280 1281 uint8_t or = ffs(bios->display.output->or) - 1; 1282 uint8_t index = bios->data[offset + 1]; 1283 uint8_t data; 1284 1285 if (!iexec->execute) 1286 return 2; 1287 1288 data = bios_idxprt_rd(bios, 0x3d4, index); 1289 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or)); 1290 return 2; 1291} 1292 1293static int 1294init_idx_addr_latched(struct nvbios *bios, uint16_t offset, 1295 struct init_exec *iexec) 1296{ 1297 /* 1298 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I') 1299 * 1300 * offset (8 bit): opcode 1301 * offset + 1 (32 bit): control register 1302 * offset + 5 (32 bit): data register 1303 * offset + 9 (32 bit): mask 1304 * offset + 13 (32 bit): data 1305 * offset + 17 (8 bit): count 1306 * offset + 18 (8 bit): address 1 1307 * offset + 19 (8 bit): data 1 1308 * ... 1309 * 1310 * For each of "count" address and data pairs, write "data n" to 1311 * "data register", read the current value of "control register", 1312 * and write it back once ANDed with "mask", ORed with "data", 1313 * and ORed with "address n" 1314 */ 1315 1316 uint32_t controlreg = ROM32(bios->data[offset + 1]); 1317 uint32_t datareg = ROM32(bios->data[offset + 5]); 1318 uint32_t mask = ROM32(bios->data[offset + 9]); 1319 uint32_t data = ROM32(bios->data[offset + 13]); 1320 uint8_t count = bios->data[offset + 17]; 1321 int len = 18 + count * 2; 1322 uint32_t value; 1323 int i; 1324 1325 if (!iexec->execute) 1326 return len; 1327 1328 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, " 1329 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n", 1330 offset, controlreg, datareg, mask, data, count); 1331 1332 for (i = 0; i < count; i++) { 1333 uint8_t instaddress = bios->data[offset + 18 + i * 2]; 1334 uint8_t instdata = bios->data[offset + 19 + i * 2]; 1335 1336 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n", 1337 offset, instaddress, instdata); 1338 1339 bios_wr32(bios, datareg, instdata); 1340 value = bios_rd32(bios, controlreg) & mask; 1341 value |= data; 1342 value |= instaddress; 1343 bios_wr32(bios, controlreg, value); 1344 } 1345 1346 return len; 1347} 1348 1349static int 1350init_io_restrict_pll2(struct nvbios *bios, uint16_t offset, 1351 struct init_exec *iexec) 1352{ 1353 /* 1354 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J') 1355 * 1356 * offset (8 bit): opcode 1357 * offset + 1 (16 bit): CRTC port 1358 * offset + 3 (8 bit): CRTC index 1359 * offset + 4 (8 bit): mask 1360 * offset + 5 (8 bit): shift 1361 * offset + 6 (8 bit): count 1362 * offset + 7 (32 bit): register 1363 * offset + 11 (32 bit): frequency 1 1364 * ... 1365 * 1366 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz). 1367 * Set PLL register "register" to coefficients for frequency n, 1368 * selected by reading index "CRTC index" of "CRTC port" ANDed with 1369 * "mask" and shifted right by "shift". 1370 */ 1371 1372 uint16_t crtcport = ROM16(bios->data[offset + 1]); 1373 uint8_t crtcindex = bios->data[offset + 3]; 1374 uint8_t mask = bios->data[offset + 4]; 1375 uint8_t shift = bios->data[offset + 5]; 1376 uint8_t count = bios->data[offset + 6]; 1377 uint32_t reg = ROM32(bios->data[offset + 7]); 1378 int len = 11 + count * 4; 1379 uint8_t config; 1380 uint32_t freq; 1381 1382 if (!iexec->execute) 1383 return len; 1384 1385 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 1386 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n", 1387 offset, crtcport, crtcindex, mask, shift, count, reg); 1388 1389 if (!reg) 1390 return len; 1391 1392 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 1393 if (config > count) { 1394 NV_ERROR(bios->dev, 1395 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 1396 offset, config, count); 1397 return len; 1398 } 1399 1400 freq = ROM32(bios->data[offset + 11 + config * 4]); 1401 1402 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n", 1403 offset, reg, config, freq); 1404 1405 setPLL(bios, reg, freq); 1406 1407 return len; 1408} 1409 1410static int 1411init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1412{ 1413 /* 1414 * INIT_PLL2 opcode: 0x4B ('K') 1415 * 1416 * offset (8 bit): opcode 1417 * offset + 1 (32 bit): register 1418 * offset + 5 (32 bit): freq 1419 * 1420 * Set PLL register "register" to coefficients for frequency "freq" 1421 */ 1422 1423 uint32_t reg = ROM32(bios->data[offset + 1]); 1424 uint32_t freq = ROM32(bios->data[offset + 5]); 1425 1426 if (!iexec->execute) 1427 return 9; 1428 1429 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n", 1430 offset, reg, freq); 1431 1432 setPLL(bios, reg, freq); 1433 return 9; 1434} 1435 1436static int 1437init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1438{ 1439 /* 1440 * INIT_I2C_BYTE opcode: 0x4C ('L') 1441 * 1442 * offset (8 bit): opcode 1443 * offset + 1 (8 bit): DCB I2C table entry index 1444 * offset + 2 (8 bit): I2C slave address 1445 * offset + 3 (8 bit): count 1446 * offset + 4 (8 bit): I2C register 1 1447 * offset + 5 (8 bit): mask 1 1448 * offset + 6 (8 bit): data 1 1449 * ... 1450 * 1451 * For each of "count" registers given by "I2C register n" on the device 1452 * addressed by "I2C slave address" on the I2C bus given by 1453 * "DCB I2C table entry index", read the register, AND the result with 1454 * "mask n" and OR it with "data n" before writing it back to the device 1455 */ 1456 1457 struct drm_device *dev = bios->dev; 1458 uint8_t i2c_index = bios->data[offset + 1]; 1459 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1460 uint8_t count = bios->data[offset + 3]; 1461 struct nouveau_i2c_chan *chan; 1462 int len = 4 + count * 3; 1463 int ret, i; 1464 1465 if (!iexec->execute) 1466 return len; 1467 1468 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1469 "Count: 0x%02X\n", 1470 offset, i2c_index, i2c_address, count); 1471 1472 chan = init_i2c_device_find(dev, i2c_index); 1473 if (!chan) { 1474 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset); 1475 return len; 1476 } 1477 1478 for (i = 0; i < count; i++) { 1479 uint8_t reg = bios->data[offset + 4 + i * 3]; 1480 uint8_t mask = bios->data[offset + 5 + i * 3]; 1481 uint8_t data = bios->data[offset + 6 + i * 3]; 1482 union i2c_smbus_data val; 1483 1484 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 1485 I2C_SMBUS_READ, reg, 1486 I2C_SMBUS_BYTE_DATA, &val); 1487 if (ret < 0) { 1488 NV_ERROR(dev, "0x%04X: i2c rd fail: %d\n", offset, ret); 1489 return len; 1490 } 1491 1492 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, " 1493 "Mask: 0x%02X, Data: 0x%02X\n", 1494 offset, reg, val.byte, mask, data); 1495 1496 if (!bios->execute) 1497 continue; 1498 1499 val.byte &= mask; 1500 val.byte |= data; 1501 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 1502 I2C_SMBUS_WRITE, reg, 1503 I2C_SMBUS_BYTE_DATA, &val); 1504 if (ret < 0) { 1505 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret); 1506 return len; 1507 } 1508 } 1509 1510 return len; 1511} 1512 1513static int 1514init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1515{ 1516 /* 1517 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M') 1518 * 1519 * offset (8 bit): opcode 1520 * offset + 1 (8 bit): DCB I2C table entry index 1521 * offset + 2 (8 bit): I2C slave address 1522 * offset + 3 (8 bit): count 1523 * offset + 4 (8 bit): I2C register 1 1524 * offset + 5 (8 bit): data 1 1525 * ... 1526 * 1527 * For each of "count" registers given by "I2C register n" on the device 1528 * addressed by "I2C slave address" on the I2C bus given by 1529 * "DCB I2C table entry index", set the register to "data n" 1530 */ 1531 1532 struct drm_device *dev = bios->dev; 1533 uint8_t i2c_index = bios->data[offset + 1]; 1534 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1535 uint8_t count = bios->data[offset + 3]; 1536 struct nouveau_i2c_chan *chan; 1537 int len = 4 + count * 2; 1538 int ret, i; 1539 1540 if (!iexec->execute) 1541 return len; 1542 1543 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1544 "Count: 0x%02X\n", 1545 offset, i2c_index, i2c_address, count); 1546 1547 chan = init_i2c_device_find(dev, i2c_index); 1548 if (!chan) { 1549 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset); 1550 return len; 1551 } 1552 1553 for (i = 0; i < count; i++) { 1554 uint8_t reg = bios->data[offset + 4 + i * 2]; 1555 union i2c_smbus_data val; 1556 1557 val.byte = bios->data[offset + 5 + i * 2]; 1558 1559 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n", 1560 offset, reg, val.byte); 1561 1562 if (!bios->execute) 1563 continue; 1564 1565 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 1566 I2C_SMBUS_WRITE, reg, 1567 I2C_SMBUS_BYTE_DATA, &val); 1568 if (ret < 0) { 1569 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret); 1570 return len; 1571 } 1572 } 1573 1574 return len; 1575} 1576 1577static int 1578init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1579{ 1580 /* 1581 * INIT_ZM_I2C opcode: 0x4E ('N') 1582 * 1583 * offset (8 bit): opcode 1584 * offset + 1 (8 bit): DCB I2C table entry index 1585 * offset + 2 (8 bit): I2C slave address 1586 * offset + 3 (8 bit): count 1587 * offset + 4 (8 bit): data 1 1588 * ... 1589 * 1590 * Send "count" bytes ("data n") to the device addressed by "I2C slave 1591 * address" on the I2C bus given by "DCB I2C table entry index" 1592 */ 1593 1594 struct drm_device *dev = bios->dev; 1595 uint8_t i2c_index = bios->data[offset + 1]; 1596 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1597 uint8_t count = bios->data[offset + 3]; 1598 int len = 4 + count; 1599 struct nouveau_i2c_chan *chan; 1600 struct i2c_msg msg; 1601 uint8_t data[256]; 1602 int ret, i; 1603 1604 if (!iexec->execute) 1605 return len; 1606 1607 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1608 "Count: 0x%02X\n", 1609 offset, i2c_index, i2c_address, count); 1610 1611 chan = init_i2c_device_find(dev, i2c_index); 1612 if (!chan) { 1613 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset); 1614 return len; 1615 } 1616 1617 for (i = 0; i < count; i++) { 1618 data[i] = bios->data[offset + 4 + i]; 1619 1620 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]); 1621 } 1622 1623 if (bios->execute) { 1624 msg.addr = i2c_address; 1625 msg.flags = 0; 1626 msg.len = count; 1627 msg.buf = data; 1628 ret = i2c_transfer(&chan->adapter, &msg, 1); 1629 if (ret != 1) { 1630 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret); 1631 return len; 1632 } 1633 } 1634 1635 return len; 1636} 1637 1638static int 1639init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1640{ 1641 /* 1642 * INIT_TMDS opcode: 0x4F ('O') (non-canon name) 1643 * 1644 * offset (8 bit): opcode 1645 * offset + 1 (8 bit): magic lookup value 1646 * offset + 2 (8 bit): TMDS address 1647 * offset + 3 (8 bit): mask 1648 * offset + 4 (8 bit): data 1649 * 1650 * Read the data reg for TMDS address "TMDS address", AND it with mask 1651 * and OR it with data, then write it back 1652 * "magic lookup value" determines which TMDS base address register is 1653 * used -- see get_tmds_index_reg() 1654 */ 1655 1656 struct drm_device *dev = bios->dev; 1657 uint8_t mlv = bios->data[offset + 1]; 1658 uint32_t tmdsaddr = bios->data[offset + 2]; 1659 uint8_t mask = bios->data[offset + 3]; 1660 uint8_t data = bios->data[offset + 4]; 1661 uint32_t reg, value; 1662 1663 if (!iexec->execute) 1664 return 5; 1665 1666 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, " 1667 "Mask: 0x%02X, Data: 0x%02X\n", 1668 offset, mlv, tmdsaddr, mask, data); 1669 1670 reg = get_tmds_index_reg(bios->dev, mlv); 1671 if (!reg) { 1672 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset); 1673 return 5; 1674 } 1675 1676 bios_wr32(bios, reg, 1677 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE); 1678 value = (bios_rd32(bios, reg + 4) & mask) | data; 1679 bios_wr32(bios, reg + 4, value); 1680 bios_wr32(bios, reg, tmdsaddr); 1681 1682 return 5; 1683} 1684 1685static int 1686init_zm_tmds_group(struct nvbios *bios, uint16_t offset, 1687 struct init_exec *iexec) 1688{ 1689 /* 1690 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name) 1691 * 1692 * offset (8 bit): opcode 1693 * offset + 1 (8 bit): magic lookup value 1694 * offset + 2 (8 bit): count 1695 * offset + 3 (8 bit): addr 1 1696 * offset + 4 (8 bit): data 1 1697 * ... 1698 * 1699 * For each of "count" TMDS address and data pairs write "data n" to 1700 * "addr n". "magic lookup value" determines which TMDS base address 1701 * register is used -- see get_tmds_index_reg() 1702 */ 1703 1704 struct drm_device *dev = bios->dev; 1705 uint8_t mlv = bios->data[offset + 1]; 1706 uint8_t count = bios->data[offset + 2]; 1707 int len = 3 + count * 2; 1708 uint32_t reg; 1709 int i; 1710 1711 if (!iexec->execute) 1712 return len; 1713 1714 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n", 1715 offset, mlv, count); 1716 1717 reg = get_tmds_index_reg(bios->dev, mlv); 1718 if (!reg) { 1719 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset); 1720 return len; 1721 } 1722 1723 for (i = 0; i < count; i++) { 1724 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2]; 1725 uint8_t tmdsdata = bios->data[offset + 4 + i * 2]; 1726 1727 bios_wr32(bios, reg + 4, tmdsdata); 1728 bios_wr32(bios, reg, tmdsaddr); 1729 } 1730 1731 return len; 1732} 1733 1734static int 1735init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset, 1736 struct init_exec *iexec) 1737{ 1738 /* 1739 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q') 1740 * 1741 * offset (8 bit): opcode 1742 * offset + 1 (8 bit): CRTC index1 1743 * offset + 2 (8 bit): CRTC index2 1744 * offset + 3 (8 bit): baseaddr 1745 * offset + 4 (8 bit): count 1746 * offset + 5 (8 bit): data 1 1747 * ... 1748 * 1749 * For each of "count" address and data pairs, write "baseaddr + n" to 1750 * "CRTC index1" and "data n" to "CRTC index2" 1751 * Once complete, restore initial value read from "CRTC index1" 1752 */ 1753 uint8_t crtcindex1 = bios->data[offset + 1]; 1754 uint8_t crtcindex2 = bios->data[offset + 2]; 1755 uint8_t baseaddr = bios->data[offset + 3]; 1756 uint8_t count = bios->data[offset + 4]; 1757 int len = 5 + count; 1758 uint8_t oldaddr, data; 1759 int i; 1760 1761 if (!iexec->execute) 1762 return len; 1763 1764 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, " 1765 "BaseAddr: 0x%02X, Count: 0x%02X\n", 1766 offset, crtcindex1, crtcindex2, baseaddr, count); 1767 1768 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1); 1769 1770 for (i = 0; i < count; i++) { 1771 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, 1772 baseaddr + i); 1773 data = bios->data[offset + 5 + i]; 1774 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data); 1775 } 1776 1777 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr); 1778 1779 return len; 1780} 1781 1782static int 1783init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1784{ 1785 /* 1786 * INIT_CR opcode: 0x52 ('R') 1787 * 1788 * offset (8 bit): opcode 1789 * offset + 1 (8 bit): CRTC index 1790 * offset + 2 (8 bit): mask 1791 * offset + 3 (8 bit): data 1792 * 1793 * Assign the value of at "CRTC index" ANDed with mask and ORed with 1794 * data back to "CRTC index" 1795 */ 1796 1797 uint8_t crtcindex = bios->data[offset + 1]; 1798 uint8_t mask = bios->data[offset + 2]; 1799 uint8_t data = bios->data[offset + 3]; 1800 uint8_t value; 1801 1802 if (!iexec->execute) 1803 return 4; 1804 1805 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n", 1806 offset, crtcindex, mask, data); 1807 1808 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask; 1809 value |= data; 1810 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value); 1811 1812 return 4; 1813} 1814 1815static int 1816init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1817{ 1818 /* 1819 * INIT_ZM_CR opcode: 0x53 ('S') 1820 * 1821 * offset (8 bit): opcode 1822 * offset + 1 (8 bit): CRTC index 1823 * offset + 2 (8 bit): value 1824 * 1825 * Assign "value" to CRTC register with index "CRTC index". 1826 */ 1827 1828 uint8_t crtcindex = ROM32(bios->data[offset + 1]); 1829 uint8_t data = bios->data[offset + 2]; 1830 1831 if (!iexec->execute) 1832 return 3; 1833 1834 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data); 1835 1836 return 3; 1837} 1838 1839static int 1840init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1841{ 1842 /* 1843 * INIT_ZM_CR_GROUP opcode: 0x54 ('T') 1844 * 1845 * offset (8 bit): opcode 1846 * offset + 1 (8 bit): count 1847 * offset + 2 (8 bit): CRTC index 1 1848 * offset + 3 (8 bit): value 1 1849 * ... 1850 * 1851 * For "count", assign "value n" to CRTC register with index 1852 * "CRTC index n". 1853 */ 1854 1855 uint8_t count = bios->data[offset + 1]; 1856 int len = 2 + count * 2; 1857 int i; 1858 1859 if (!iexec->execute) 1860 return len; 1861 1862 for (i = 0; i < count; i++) 1863 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec); 1864 1865 return len; 1866} 1867 1868static int 1869init_condition_time(struct nvbios *bios, uint16_t offset, 1870 struct init_exec *iexec) 1871{ 1872 /* 1873 * INIT_CONDITION_TIME opcode: 0x56 ('V') 1874 * 1875 * offset (8 bit): opcode 1876 * offset + 1 (8 bit): condition number 1877 * offset + 2 (8 bit): retries / 50 1878 * 1879 * Check condition "condition number" in the condition table. 1880 * Bios code then sleeps for 2ms if the condition is not met, and 1881 * repeats up to "retries" times, but on one C51 this has proved 1882 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do 1883 * this, and bail after "retries" times, or 2s, whichever is less. 1884 * If still not met after retries, clear execution flag for this table. 1885 */ 1886 1887 uint8_t cond = bios->data[offset + 1]; 1888 uint16_t retries = bios->data[offset + 2] * 50; 1889 unsigned cnt; 1890 1891 if (!iexec->execute) 1892 return 3; 1893 1894 if (retries > 100) 1895 retries = 100; 1896 1897 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n", 1898 offset, cond, retries); 1899 1900 if (!bios->execute) /* avoid 2s delays when "faking" execution */ 1901 retries = 1; 1902 1903 for (cnt = 0; cnt < retries; cnt++) { 1904 if (bios_condition_met(bios, offset, cond)) { 1905 BIOSLOG(bios, "0x%04X: Condition met, continuing\n", 1906 offset); 1907 break; 1908 } else { 1909 BIOSLOG(bios, "0x%04X: " 1910 "Condition not met, sleeping for 20ms\n", 1911 offset); 1912 mdelay(20); 1913 } 1914 } 1915 1916 if (!bios_condition_met(bios, offset, cond)) { 1917 NV_WARN(bios->dev, 1918 "0x%04X: Condition still not met after %dms, " 1919 "skipping following opcodes\n", offset, 20 * retries); 1920 iexec->execute = false; 1921 } 1922 1923 return 3; 1924} 1925 1926static int 1927init_ltime(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1928{ 1929 /* 1930 * INIT_LTIME opcode: 0x57 ('V') 1931 * 1932 * offset (8 bit): opcode 1933 * offset + 1 (16 bit): time 1934 * 1935 * Sleep for "time" milliseconds. 1936 */ 1937 1938 unsigned time = ROM16(bios->data[offset + 1]); 1939 1940 if (!iexec->execute) 1941 return 3; 1942 1943 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X milliseconds\n", 1944 offset, time); 1945 1946 mdelay(time); 1947 1948 return 3; 1949} 1950 1951static int 1952init_zm_reg_sequence(struct nvbios *bios, uint16_t offset, 1953 struct init_exec *iexec) 1954{ 1955 /* 1956 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X') 1957 * 1958 * offset (8 bit): opcode 1959 * offset + 1 (32 bit): base register 1960 * offset + 5 (8 bit): count 1961 * offset + 6 (32 bit): value 1 1962 * ... 1963 * 1964 * Starting at offset + 6 there are "count" 32 bit values. 1965 * For "count" iterations set "base register" + 4 * current_iteration 1966 * to "value current_iteration" 1967 */ 1968 1969 uint32_t basereg = ROM32(bios->data[offset + 1]); 1970 uint32_t count = bios->data[offset + 5]; 1971 int len = 6 + count * 4; 1972 int i; 1973 1974 if (!iexec->execute) 1975 return len; 1976 1977 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n", 1978 offset, basereg, count); 1979 1980 for (i = 0; i < count; i++) { 1981 uint32_t reg = basereg + i * 4; 1982 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]); 1983 1984 bios_wr32(bios, reg, data); 1985 } 1986 1987 return len; 1988} 1989 1990static int 1991init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1992{ 1993 /* 1994 * INIT_SUB_DIRECT opcode: 0x5B ('[') 1995 * 1996 * offset (8 bit): opcode 1997 * offset + 1 (16 bit): subroutine offset (in bios) 1998 * 1999 * Calls a subroutine that will execute commands until INIT_DONE 2000 * is found. 2001 */ 2002 2003 uint16_t sub_offset = ROM16(bios->data[offset + 1]); 2004 2005 if (!iexec->execute) 2006 return 3; 2007 2008 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n", 2009 offset, sub_offset); 2010 2011 parse_init_table(bios, sub_offset, iexec); 2012 2013 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset); 2014 2015 return 3; 2016} 2017 2018static int 2019init_jump(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2020{ 2021 /* 2022 * INIT_JUMP opcode: 0x5C ('\') 2023 * 2024 * offset (8 bit): opcode 2025 * offset + 1 (16 bit): offset (in bios) 2026 * 2027 * Continue execution of init table from 'offset' 2028 */ 2029 2030 uint16_t jmp_offset = ROM16(bios->data[offset + 1]); 2031 2032 if (!iexec->execute) 2033 return 3; 2034 2035 BIOSLOG(bios, "0x%04X: Jump to 0x%04X\n", offset, jmp_offset); 2036 return jmp_offset - offset; 2037} 2038 2039static int 2040init_i2c_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2041{ 2042 /* 2043 * INIT_I2C_IF opcode: 0x5E ('^') 2044 * 2045 * offset (8 bit): opcode 2046 * offset + 1 (8 bit): DCB I2C table entry index 2047 * offset + 2 (8 bit): I2C slave address 2048 * offset + 3 (8 bit): I2C register 2049 * offset + 4 (8 bit): mask 2050 * offset + 5 (8 bit): data 2051 * 2052 * Read the register given by "I2C register" on the device addressed 2053 * by "I2C slave address" on the I2C bus given by "DCB I2C table 2054 * entry index". Compare the result AND "mask" to "data". 2055 * If they're not equal, skip subsequent opcodes until condition is 2056 * inverted (INIT_NOT), or we hit INIT_RESUME 2057 */ 2058 2059 uint8_t i2c_index = bios->data[offset + 1]; 2060 uint8_t i2c_address = bios->data[offset + 2] >> 1; 2061 uint8_t reg = bios->data[offset + 3]; 2062 uint8_t mask = bios->data[offset + 4]; 2063 uint8_t data = bios->data[offset + 5]; 2064 struct nouveau_i2c_chan *chan; 2065 union i2c_smbus_data val; 2066 int ret; 2067 2068 /* no execute check by design */ 2069 2070 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n", 2071 offset, i2c_index, i2c_address); 2072 2073 chan = init_i2c_device_find(bios->dev, i2c_index); 2074 if (!chan) 2075 return -ENODEV; 2076 2077 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 2078 I2C_SMBUS_READ, reg, 2079 I2C_SMBUS_BYTE_DATA, &val); 2080 if (ret < 0) { 2081 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: [no device], " 2082 "Mask: 0x%02X, Data: 0x%02X\n", 2083 offset, reg, mask, data); 2084 iexec->execute = 0; 2085 return 6; 2086 } 2087 2088 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, " 2089 "Mask: 0x%02X, Data: 0x%02X\n", 2090 offset, reg, val.byte, mask, data); 2091 2092 iexec->execute = ((val.byte & mask) == data); 2093 2094 return 6; 2095} 2096 2097static int 2098init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2099{ 2100 /* 2101 * INIT_COPY_NV_REG opcode: 0x5F ('_') 2102 * 2103 * offset (8 bit): opcode 2104 * offset + 1 (32 bit): src reg 2105 * offset + 5 (8 bit): shift 2106 * offset + 6 (32 bit): src mask 2107 * offset + 10 (32 bit): xor 2108 * offset + 14 (32 bit): dst reg 2109 * offset + 18 (32 bit): dst mask 2110 * 2111 * Shift REGVAL("src reg") right by (signed) "shift", AND result with 2112 * "src mask", then XOR with "xor". Write this OR'd with 2113 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg" 2114 */ 2115 2116 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1])); 2117 uint8_t shift = bios->data[offset + 5]; 2118 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6])); 2119 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10])); 2120 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14])); 2121 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18])); 2122 uint32_t srcvalue, dstvalue; 2123 2124 if (!iexec->execute) 2125 return 22; 2126 2127 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, " 2128 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n", 2129 offset, srcreg, shift, srcmask, xor, dstreg, dstmask); 2130 2131 srcvalue = bios_rd32(bios, srcreg); 2132 2133 if (shift < 0x80) 2134 srcvalue >>= shift; 2135 else 2136 srcvalue <<= (0x100 - shift); 2137 2138 srcvalue = (srcvalue & srcmask) ^ xor; 2139 2140 dstvalue = bios_rd32(bios, dstreg) & dstmask; 2141 2142 bios_wr32(bios, dstreg, dstvalue | srcvalue); 2143 2144 return 22; 2145} 2146 2147static int 2148init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2149{ 2150 /* 2151 * INIT_ZM_INDEX_IO opcode: 0x62 ('b') 2152 * 2153 * offset (8 bit): opcode 2154 * offset + 1 (16 bit): CRTC port 2155 * offset + 3 (8 bit): CRTC index 2156 * offset + 4 (8 bit): data 2157 * 2158 * Write "data" to index "CRTC index" of "CRTC port" 2159 */ 2160 uint16_t crtcport = ROM16(bios->data[offset + 1]); 2161 uint8_t crtcindex = bios->data[offset + 3]; 2162 uint8_t data = bios->data[offset + 4]; 2163 2164 if (!iexec->execute) 2165 return 5; 2166 2167 bios_idxprt_wr(bios, crtcport, crtcindex, data); 2168 2169 return 5; 2170} 2171 2172static inline void 2173bios_md32(struct nvbios *bios, uint32_t reg, 2174 uint32_t mask, uint32_t val) 2175{ 2176 bios_wr32(bios, reg, (bios_rd32(bios, reg) & ~mask) | val); 2177} 2178 2179static uint32_t 2180peek_fb(struct drm_device *dev, struct io_mapping *fb, 2181 uint32_t off) 2182{ 2183 uint32_t val = 0; 2184 2185 if (off < pci_resource_len(dev->pdev, 1)) { 2186 uint8_t __iomem *p = 2187 io_mapping_map_atomic_wc(fb, off & PAGE_MASK); 2188 2189 val = ioread32(p + (off & ~PAGE_MASK)); 2190 2191 io_mapping_unmap_atomic(p); 2192 } 2193 2194 return val; 2195} 2196 2197static void 2198poke_fb(struct drm_device *dev, struct io_mapping *fb, 2199 uint32_t off, uint32_t val) 2200{ 2201 if (off < pci_resource_len(dev->pdev, 1)) { 2202 uint8_t __iomem *p = 2203 io_mapping_map_atomic_wc(fb, off & PAGE_MASK); 2204 2205 iowrite32(val, p + (off & ~PAGE_MASK)); 2206 wmb(); 2207 2208 io_mapping_unmap_atomic(p); 2209 } 2210} 2211 2212static inline bool 2213read_back_fb(struct drm_device *dev, struct io_mapping *fb, 2214 uint32_t off, uint32_t val) 2215{ 2216 poke_fb(dev, fb, off, val); 2217 return val == peek_fb(dev, fb, off); 2218} 2219 2220static int 2221nv04_init_compute_mem(struct nvbios *bios) 2222{ 2223 struct drm_device *dev = bios->dev; 2224 uint32_t patt = 0xdeadbeef; 2225 struct io_mapping *fb; 2226 int i; 2227 2228 /* Map the framebuffer aperture */ 2229 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1), 2230 pci_resource_len(dev->pdev, 1)); 2231 if (!fb) 2232 return -ENOMEM; 2233 2234 /* Sequencer and refresh off */ 2235 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20); 2236 bios_md32(bios, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF); 2237 2238 bios_md32(bios, NV04_PFB_BOOT_0, ~0, 2239 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB | 2240 NV04_PFB_BOOT_0_RAM_WIDTH_128 | 2241 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT); 2242 2243 for (i = 0; i < 4; i++) 2244 poke_fb(dev, fb, 4 * i, patt); 2245 2246 poke_fb(dev, fb, 0x400000, patt + 1); 2247 2248 if (peek_fb(dev, fb, 0) == patt + 1) { 2249 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE, 2250 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT); 2251 bios_md32(bios, NV04_PFB_DEBUG_0, 2252 NV04_PFB_DEBUG_0_REFRESH_OFF, 0); 2253 2254 for (i = 0; i < 4; i++) 2255 poke_fb(dev, fb, 4 * i, patt); 2256 2257 if ((peek_fb(dev, fb, 0xc) & 0xffff) != (patt & 0xffff)) 2258 bios_md32(bios, NV04_PFB_BOOT_0, 2259 NV04_PFB_BOOT_0_RAM_WIDTH_128 | 2260 NV04_PFB_BOOT_0_RAM_AMOUNT, 2261 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 2262 2263 } else if ((peek_fb(dev, fb, 0xc) & 0xffff0000) != 2264 (patt & 0xffff0000)) { 2265 bios_md32(bios, NV04_PFB_BOOT_0, 2266 NV04_PFB_BOOT_0_RAM_WIDTH_128 | 2267 NV04_PFB_BOOT_0_RAM_AMOUNT, 2268 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); 2269 2270 } else if (peek_fb(dev, fb, 0) != patt) { 2271 if (read_back_fb(dev, fb, 0x800000, patt)) 2272 bios_md32(bios, NV04_PFB_BOOT_0, 2273 NV04_PFB_BOOT_0_RAM_AMOUNT, 2274 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 2275 else 2276 bios_md32(bios, NV04_PFB_BOOT_0, 2277 NV04_PFB_BOOT_0_RAM_AMOUNT, 2278 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); 2279 2280 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE, 2281 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT); 2282 2283 } else if (!read_back_fb(dev, fb, 0x800000, patt)) { 2284 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, 2285 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 2286 2287 } 2288 2289 /* Refresh on, sequencer on */ 2290 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0); 2291 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20); 2292 2293 io_mapping_free(fb); 2294 return 0; 2295} 2296 2297static const uint8_t * 2298nv05_memory_config(struct nvbios *bios) 2299{ 2300 /* Defaults for BIOSes lacking a memory config table */ 2301 static const uint8_t default_config_tab[][2] = { 2302 { 0x24, 0x00 }, 2303 { 0x28, 0x00 }, 2304 { 0x24, 0x01 }, 2305 { 0x1f, 0x00 }, 2306 { 0x0f, 0x00 }, 2307 { 0x17, 0x00 }, 2308 { 0x06, 0x00 }, 2309 { 0x00, 0x00 } 2310 }; 2311 int i = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 2312 NV_PEXTDEV_BOOT_0_RAMCFG) >> 2; 2313 2314 if (bios->legacy.mem_init_tbl_ptr) 2315 return &bios->data[bios->legacy.mem_init_tbl_ptr + 2 * i]; 2316 else 2317 return default_config_tab[i]; 2318} 2319 2320static int 2321nv05_init_compute_mem(struct nvbios *bios) 2322{ 2323 struct drm_device *dev = bios->dev; 2324 const uint8_t *ramcfg = nv05_memory_config(bios); 2325 uint32_t patt = 0xdeadbeef; 2326 struct io_mapping *fb; 2327 int i, v; 2328 2329 /* Map the framebuffer aperture */ 2330 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1), 2331 pci_resource_len(dev->pdev, 1)); 2332 if (!fb) 2333 return -ENOMEM; 2334 2335 /* Sequencer off */ 2336 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20); 2337 2338 if (bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE) 2339 goto out; 2340 2341 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0); 2342 2343 /* If present load the hardcoded scrambling table */ 2344 if (bios->legacy.mem_init_tbl_ptr) { 2345 uint32_t *scramble_tab = (uint32_t *)&bios->data[ 2346 bios->legacy.mem_init_tbl_ptr + 0x10]; 2347 2348 for (i = 0; i < 8; i++) 2349 bios_wr32(bios, NV04_PFB_SCRAMBLE(i), 2350 ROM32(scramble_tab[i])); 2351 } 2352 2353 /* Set memory type/width/length defaults depending on the straps */ 2354 bios_md32(bios, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]); 2355 2356 if (ramcfg[1] & 0x80) 2357 bios_md32(bios, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE); 2358 2359 bios_md32(bios, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20); 2360 bios_md32(bios, NV04_PFB_CFG1, 0, 1); 2361 2362 /* Probe memory bus width */ 2363 for (i = 0; i < 4; i++) 2364 poke_fb(dev, fb, 4 * i, patt); 2365 2366 if (peek_fb(dev, fb, 0xc) != patt) 2367 bios_md32(bios, NV04_PFB_BOOT_0, 2368 NV04_PFB_BOOT_0_RAM_WIDTH_128, 0); 2369 2370 /* Probe memory length */ 2371 v = bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT; 2372 2373 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB && 2374 (!read_back_fb(dev, fb, 0x1000000, ++patt) || 2375 !read_back_fb(dev, fb, 0, ++patt))) 2376 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, 2377 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB); 2378 2379 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB && 2380 !read_back_fb(dev, fb, 0x800000, ++patt)) 2381 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, 2382 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 2383 2384 if (!read_back_fb(dev, fb, 0x400000, ++patt)) 2385 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, 2386 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); 2387 2388out: 2389 /* Sequencer on */ 2390 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20); 2391 2392 io_mapping_free(fb); 2393 return 0; 2394} 2395 2396static int 2397nv10_init_compute_mem(struct nvbios *bios) 2398{ 2399 struct drm_device *dev = bios->dev; 2400 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2401 const int mem_width[] = { 0x10, 0x00, 0x20 }; 2402 const int mem_width_count = (dev_priv->chipset >= 0x17 ? 3 : 2); 2403 uint32_t patt = 0xdeadbeef; 2404 struct io_mapping *fb; 2405 int i, j, k; 2406 2407 /* Map the framebuffer aperture */ 2408 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1), 2409 pci_resource_len(dev->pdev, 1)); 2410 if (!fb) 2411 return -ENOMEM; 2412 2413 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1); 2414 2415 /* Probe memory bus width */ 2416 for (i = 0; i < mem_width_count; i++) { 2417 bios_md32(bios, NV04_PFB_CFG0, 0x30, mem_width[i]); 2418 2419 for (j = 0; j < 4; j++) { 2420 for (k = 0; k < 4; k++) 2421 poke_fb(dev, fb, 0x1c, 0); 2422 2423 poke_fb(dev, fb, 0x1c, patt); 2424 poke_fb(dev, fb, 0x3c, 0); 2425 2426 if (peek_fb(dev, fb, 0x1c) == patt) 2427 goto mem_width_found; 2428 } 2429 } 2430 2431mem_width_found: 2432 patt <<= 1; 2433 2434 /* Probe amount of installed memory */ 2435 for (i = 0; i < 4; i++) { 2436 int off = bios_rd32(bios, NV04_PFB_FIFO_DATA) - 0x100000; 2437 2438 poke_fb(dev, fb, off, patt); 2439 poke_fb(dev, fb, 0, 0); 2440 2441 peek_fb(dev, fb, 0); 2442 peek_fb(dev, fb, 0); 2443 peek_fb(dev, fb, 0); 2444 peek_fb(dev, fb, 0); 2445 2446 if (peek_fb(dev, fb, off) == patt) 2447 goto amount_found; 2448 } 2449 2450 /* IC missing - disable the upper half memory space. */ 2451 bios_md32(bios, NV04_PFB_CFG0, 0x1000, 0); 2452 2453amount_found: 2454 io_mapping_free(fb); 2455 return 0; 2456} 2457 2458static int 2459nv20_init_compute_mem(struct nvbios *bios) 2460{ 2461 struct drm_device *dev = bios->dev; 2462 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2463 uint32_t mask = (dev_priv->chipset >= 0x25 ? 0x300 : 0x900); 2464 uint32_t amount, off; 2465 struct io_mapping *fb; 2466 2467 /* Map the framebuffer aperture */ 2468 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1), 2469 pci_resource_len(dev->pdev, 1)); 2470 if (!fb) 2471 return -ENOMEM; 2472 2473 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1); 2474 2475 /* Allow full addressing */ 2476 bios_md32(bios, NV04_PFB_CFG0, 0, mask); 2477 2478 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA); 2479 for (off = amount; off > 0x2000000; off -= 0x2000000) 2480 poke_fb(dev, fb, off - 4, off); 2481 2482 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA); 2483 if (amount != peek_fb(dev, fb, amount - 4)) 2484 /* IC missing - disable the upper half memory space. */ 2485 bios_md32(bios, NV04_PFB_CFG0, mask, 0); 2486 2487 io_mapping_free(fb); 2488 return 0; 2489} 2490 2491static int 2492init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2493{ 2494 /* 2495 * INIT_COMPUTE_MEM opcode: 0x63 ('c') 2496 * 2497 * offset (8 bit): opcode 2498 * 2499 * This opcode is meant to set the PFB memory config registers 2500 * appropriately so that we can correctly calculate how much VRAM it 2501 * has (on nv10 and better chipsets the amount of installed VRAM is 2502 * subsequently reported in NV_PFB_CSTATUS (0x10020C)). 2503 * 2504 * The implementation of this opcode in general consists of several 2505 * parts: 2506 * 2507 * 1) Determination of memory type and density. Only necessary for 2508 * really old chipsets, the memory type reported by the strap bits 2509 * (0x101000) is assumed to be accurate on nv05 and newer. 2510 * 2511 * 2) Determination of the memory bus width. Usually done by a cunning 2512 * combination of writes to offsets 0x1c and 0x3c in the fb, and 2513 * seeing whether the written values are read back correctly. 2514 * 2515 * Only necessary on nv0x-nv1x and nv34, on the other cards we can 2516 * trust the straps. 2517 * 2518 * 3) Determination of how many of the card's RAM pads have ICs 2519 * attached, usually done by a cunning combination of writes to an 2520 * offset slightly less than the maximum memory reported by 2521 * NV_PFB_CSTATUS, then seeing if the test pattern can be read back. 2522 * 2523 * This appears to be a NOP on IGPs and NV4x or newer chipsets, both io 2524 * logs of the VBIOS and kmmio traces of the binary driver POSTing the 2525 * card show nothing being done for this opcode. Why is it still listed 2526 * in the table?! 2527 */ 2528 2529 /* no iexec->execute check by design */ 2530 2531 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2532 int ret; 2533 2534 if (dev_priv->chipset >= 0x40 || 2535 dev_priv->chipset == 0x1a || 2536 dev_priv->chipset == 0x1f) 2537 ret = 0; 2538 else if (dev_priv->chipset >= 0x20 && 2539 dev_priv->chipset != 0x34) 2540 ret = nv20_init_compute_mem(bios); 2541 else if (dev_priv->chipset >= 0x10) 2542 ret = nv10_init_compute_mem(bios); 2543 else if (dev_priv->chipset >= 0x5) 2544 ret = nv05_init_compute_mem(bios); 2545 else 2546 ret = nv04_init_compute_mem(bios); 2547 2548 if (ret) 2549 return ret; 2550 2551 return 1; 2552} 2553 2554static int 2555init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2556{ 2557 /* 2558 * INIT_RESET opcode: 0x65 ('e') 2559 * 2560 * offset (8 bit): opcode 2561 * offset + 1 (32 bit): register 2562 * offset + 5 (32 bit): value1 2563 * offset + 9 (32 bit): value2 2564 * 2565 * Assign "value1" to "register", then assign "value2" to "register" 2566 */ 2567 2568 uint32_t reg = ROM32(bios->data[offset + 1]); 2569 uint32_t value1 = ROM32(bios->data[offset + 5]); 2570 uint32_t value2 = ROM32(bios->data[offset + 9]); 2571 uint32_t pci_nv_19, pci_nv_20; 2572 2573 /* no iexec->execute check by design */ 2574 2575 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19); 2576 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19 & ~0xf00); 2577 2578 bios_wr32(bios, reg, value1); 2579 2580 udelay(10); 2581 2582 bios_wr32(bios, reg, value2); 2583 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19); 2584 2585 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20); 2586 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */ 2587 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20); 2588 2589 return 13; 2590} 2591 2592static int 2593init_configure_mem(struct nvbios *bios, uint16_t offset, 2594 struct init_exec *iexec) 2595{ 2596 /* 2597 * INIT_CONFIGURE_MEM opcode: 0x66 ('f') 2598 * 2599 * offset (8 bit): opcode 2600 * 2601 * Equivalent to INIT_DONE on bios version 3 or greater. 2602 * For early bios versions, sets up the memory registers, using values 2603 * taken from the memory init table 2604 */ 2605 2606 /* no iexec->execute check by design */ 2607 2608 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4); 2609 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6; 2610 uint32_t reg, data; 2611 2612 if (bios->major_version > 2) 2613 return 0; 2614 2615 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd( 2616 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20); 2617 2618 if (bios->data[meminitoffs] & 1) 2619 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr; 2620 2621 for (reg = ROM32(bios->data[seqtbloffs]); 2622 reg != 0xffffffff; 2623 reg = ROM32(bios->data[seqtbloffs += 4])) { 2624 2625 switch (reg) { 2626 case NV04_PFB_PRE: 2627 data = NV04_PFB_PRE_CMD_PRECHARGE; 2628 break; 2629 case NV04_PFB_PAD: 2630 data = NV04_PFB_PAD_CKE_NORMAL; 2631 break; 2632 case NV04_PFB_REF: 2633 data = NV04_PFB_REF_CMD_REFRESH; 2634 break; 2635 default: 2636 data = ROM32(bios->data[meminitdata]); 2637 meminitdata += 4; 2638 if (data == 0xffffffff) 2639 continue; 2640 } 2641 2642 bios_wr32(bios, reg, data); 2643 } 2644 2645 return 1; 2646} 2647 2648static int 2649init_configure_clk(struct nvbios *bios, uint16_t offset, 2650 struct init_exec *iexec) 2651{ 2652 /* 2653 * INIT_CONFIGURE_CLK opcode: 0x67 ('g') 2654 * 2655 * offset (8 bit): opcode 2656 * 2657 * Equivalent to INIT_DONE on bios version 3 or greater. 2658 * For early bios versions, sets up the NVClk and MClk PLLs, using 2659 * values taken from the memory init table 2660 */ 2661 2662 /* no iexec->execute check by design */ 2663 2664 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4); 2665 int clock; 2666 2667 if (bios->major_version > 2) 2668 return 0; 2669 2670 clock = ROM16(bios->data[meminitoffs + 4]) * 10; 2671 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock); 2672 2673 clock = ROM16(bios->data[meminitoffs + 2]) * 10; 2674 if (bios->data[meminitoffs] & 1) /* DDR */ 2675 clock *= 2; 2676 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock); 2677 2678 return 1; 2679} 2680 2681static int 2682init_configure_preinit(struct nvbios *bios, uint16_t offset, 2683 struct init_exec *iexec) 2684{ 2685 /* 2686 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h') 2687 * 2688 * offset (8 bit): opcode 2689 * 2690 * Equivalent to INIT_DONE on bios version 3 or greater. 2691 * For early bios versions, does early init, loading ram and crystal 2692 * configuration from straps into CR3C 2693 */ 2694 2695 /* no iexec->execute check by design */ 2696 2697 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0); 2698 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & 0x40) >> 6; 2699 2700 if (bios->major_version > 2) 2701 return 0; 2702 2703 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, 2704 NV_CIO_CRE_SCRATCH4__INDEX, cr3c); 2705 2706 return 1; 2707} 2708 2709static int 2710init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2711{ 2712 /* 2713 * INIT_IO opcode: 0x69 ('i') 2714 * 2715 * offset (8 bit): opcode 2716 * offset + 1 (16 bit): CRTC port 2717 * offset + 3 (8 bit): mask 2718 * offset + 4 (8 bit): data 2719 * 2720 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port" 2721 */ 2722 2723 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2724 uint16_t crtcport = ROM16(bios->data[offset + 1]); 2725 uint8_t mask = bios->data[offset + 3]; 2726 uint8_t data = bios->data[offset + 4]; 2727 2728 if (!iexec->execute) 2729 return 5; 2730 2731 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n", 2732 offset, crtcport, mask, data); 2733 2734 /* 2735 * I have no idea what this does, but NVIDIA do this magic sequence 2736 * in the places where this INIT_IO happens.. 2737 */ 2738 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) { 2739 int i; 2740 2741 bios_wr32(bios, 0x614100, (bios_rd32( 2742 bios, 0x614100) & 0x0fffffff) | 0x00800000); 2743 2744 bios_wr32(bios, 0x00e18c, bios_rd32( 2745 bios, 0x00e18c) | 0x00020000); 2746 2747 bios_wr32(bios, 0x614900, (bios_rd32( 2748 bios, 0x614900) & 0x0fffffff) | 0x00800000); 2749 2750 bios_wr32(bios, 0x000200, bios_rd32( 2751 bios, 0x000200) & ~0x40000000); 2752 2753 mdelay(10); 2754 2755 bios_wr32(bios, 0x00e18c, bios_rd32( 2756 bios, 0x00e18c) & ~0x00020000); 2757 2758 bios_wr32(bios, 0x000200, bios_rd32( 2759 bios, 0x000200) | 0x40000000); 2760 2761 bios_wr32(bios, 0x614100, 0x00800018); 2762 bios_wr32(bios, 0x614900, 0x00800018); 2763 2764 mdelay(10); 2765 2766 bios_wr32(bios, 0x614100, 0x10000018); 2767 bios_wr32(bios, 0x614900, 0x10000018); 2768 2769 for (i = 0; i < 3; i++) 2770 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32( 2771 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0); 2772 2773 for (i = 0; i < 2; i++) 2774 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32( 2775 bios, 0x614300 + (i*0x800)) & 0xfffff0f0); 2776 2777 for (i = 0; i < 3; i++) 2778 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32( 2779 bios, 0x614380 + (i*0x800)) & 0xfffff0f0); 2780 2781 for (i = 0; i < 2; i++) 2782 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32( 2783 bios, 0x614200 + (i*0x800)) & 0xfffffff0); 2784 2785 for (i = 0; i < 2; i++) 2786 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32( 2787 bios, 0x614108 + (i*0x800)) & 0x0fffffff); 2788 return 5; 2789 } 2790 2791 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) | 2792 data); 2793 return 5; 2794} 2795 2796static int 2797init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2798{ 2799 /* 2800 * INIT_SUB opcode: 0x6B ('k') 2801 * 2802 * offset (8 bit): opcode 2803 * offset + 1 (8 bit): script number 2804 * 2805 * Execute script number "script number", as a subroutine 2806 */ 2807 2808 uint8_t sub = bios->data[offset + 1]; 2809 2810 if (!iexec->execute) 2811 return 2; 2812 2813 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub); 2814 2815 parse_init_table(bios, 2816 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]), 2817 iexec); 2818 2819 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub); 2820 2821 return 2; 2822} 2823 2824static int 2825init_ram_condition(struct nvbios *bios, uint16_t offset, 2826 struct init_exec *iexec) 2827{ 2828 /* 2829 * INIT_RAM_CONDITION opcode: 0x6D ('m') 2830 * 2831 * offset (8 bit): opcode 2832 * offset + 1 (8 bit): mask 2833 * offset + 2 (8 bit): cmpval 2834 * 2835 * Test if (NV04_PFB_BOOT_0 & "mask") equals "cmpval". 2836 * If condition not met skip subsequent opcodes until condition is 2837 * inverted (INIT_NOT), or we hit INIT_RESUME 2838 */ 2839 2840 uint8_t mask = bios->data[offset + 1]; 2841 uint8_t cmpval = bios->data[offset + 2]; 2842 uint8_t data; 2843 2844 if (!iexec->execute) 2845 return 3; 2846 2847 data = bios_rd32(bios, NV04_PFB_BOOT_0) & mask; 2848 2849 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n", 2850 offset, data, cmpval); 2851 2852 if (data == cmpval) 2853 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 2854 else { 2855 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 2856 iexec->execute = false; 2857 } 2858 2859 return 3; 2860} 2861 2862static int 2863init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2864{ 2865 /* 2866 * INIT_NV_REG opcode: 0x6E ('n') 2867 * 2868 * offset (8 bit): opcode 2869 * offset + 1 (32 bit): register 2870 * offset + 5 (32 bit): mask 2871 * offset + 9 (32 bit): data 2872 * 2873 * Assign ((REGVAL("register") & "mask") | "data") to "register" 2874 */ 2875 2876 uint32_t reg = ROM32(bios->data[offset + 1]); 2877 uint32_t mask = ROM32(bios->data[offset + 5]); 2878 uint32_t data = ROM32(bios->data[offset + 9]); 2879 2880 if (!iexec->execute) 2881 return 13; 2882 2883 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n", 2884 offset, reg, mask, data); 2885 2886 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data); 2887 2888 return 13; 2889} 2890 2891static int 2892init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2893{ 2894 /* 2895 * INIT_MACRO opcode: 0x6F ('o') 2896 * 2897 * offset (8 bit): opcode 2898 * offset + 1 (8 bit): macro number 2899 * 2900 * Look up macro index "macro number" in the macro index table. 2901 * The macro index table entry has 1 byte for the index in the macro 2902 * table, and 1 byte for the number of times to repeat the macro. 2903 * The macro table entry has 4 bytes for the register address and 2904 * 4 bytes for the value to write to that register 2905 */ 2906 2907 uint8_t macro_index_tbl_idx = bios->data[offset + 1]; 2908 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE); 2909 uint8_t macro_tbl_idx = bios->data[tmp]; 2910 uint8_t count = bios->data[tmp + 1]; 2911 uint32_t reg, data; 2912 int i; 2913 2914 if (!iexec->execute) 2915 return 2; 2916 2917 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, " 2918 "Count: 0x%02X\n", 2919 offset, macro_index_tbl_idx, macro_tbl_idx, count); 2920 2921 for (i = 0; i < count; i++) { 2922 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE; 2923 2924 reg = ROM32(bios->data[macroentryptr]); 2925 data = ROM32(bios->data[macroentryptr + 4]); 2926 2927 bios_wr32(bios, reg, data); 2928 } 2929 2930 return 2; 2931} 2932 2933static int 2934init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2935{ 2936 /* 2937 * INIT_DONE opcode: 0x71 ('q') 2938 * 2939 * offset (8 bit): opcode 2940 * 2941 * End the current script 2942 */ 2943 2944 /* mild retval abuse to stop parsing this table */ 2945 return 0; 2946} 2947 2948static int 2949init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2950{ 2951 /* 2952 * INIT_RESUME opcode: 0x72 ('r') 2953 * 2954 * offset (8 bit): opcode 2955 * 2956 * End the current execute / no-execute condition 2957 */ 2958 2959 if (iexec->execute) 2960 return 1; 2961 2962 iexec->execute = true; 2963 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset); 2964 2965 return 1; 2966} 2967 2968static int 2969init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2970{ 2971 /* 2972 * INIT_TIME opcode: 0x74 ('t') 2973 * 2974 * offset (8 bit): opcode 2975 * offset + 1 (16 bit): time 2976 * 2977 * Sleep for "time" microseconds. 2978 */ 2979 2980 unsigned time = ROM16(bios->data[offset + 1]); 2981 2982 if (!iexec->execute) 2983 return 3; 2984 2985 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n", 2986 offset, time); 2987 2988 if (time < 1000) 2989 udelay(time); 2990 else 2991 mdelay((time + 900) / 1000); 2992 2993 return 3; 2994} 2995 2996static int 2997init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2998{ 2999 /* 3000 * INIT_CONDITION opcode: 0x75 ('u') 3001 * 3002 * offset (8 bit): opcode 3003 * offset + 1 (8 bit): condition number 3004 * 3005 * Check condition "condition number" in the condition table. 3006 * If condition not met skip subsequent opcodes until condition is 3007 * inverted (INIT_NOT), or we hit INIT_RESUME 3008 */ 3009 3010 uint8_t cond = bios->data[offset + 1]; 3011 3012 if (!iexec->execute) 3013 return 2; 3014 3015 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond); 3016 3017 if (bios_condition_met(bios, offset, cond)) 3018 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 3019 else { 3020 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 3021 iexec->execute = false; 3022 } 3023 3024 return 2; 3025} 3026 3027static int 3028init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3029{ 3030 /* 3031 * INIT_IO_CONDITION opcode: 0x76 3032 * 3033 * offset (8 bit): opcode 3034 * offset + 1 (8 bit): condition number 3035 * 3036 * Check condition "condition number" in the io condition table. 3037 * If condition not met skip subsequent opcodes until condition is 3038 * inverted (INIT_NOT), or we hit INIT_RESUME 3039 */ 3040 3041 uint8_t cond = bios->data[offset + 1]; 3042 3043 if (!iexec->execute) 3044 return 2; 3045 3046 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond); 3047 3048 if (io_condition_met(bios, offset, cond)) 3049 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 3050 else { 3051 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 3052 iexec->execute = false; 3053 } 3054 3055 return 2; 3056} 3057 3058static int 3059init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3060{ 3061 /* 3062 * INIT_INDEX_IO opcode: 0x78 ('x') 3063 * 3064 * offset (8 bit): opcode 3065 * offset + 1 (16 bit): CRTC port 3066 * offset + 3 (8 bit): CRTC index 3067 * offset + 4 (8 bit): mask 3068 * offset + 5 (8 bit): data 3069 * 3070 * Read value at index "CRTC index" on "CRTC port", AND with "mask", 3071 * OR with "data", write-back 3072 */ 3073 3074 uint16_t crtcport = ROM16(bios->data[offset + 1]); 3075 uint8_t crtcindex = bios->data[offset + 3]; 3076 uint8_t mask = bios->data[offset + 4]; 3077 uint8_t data = bios->data[offset + 5]; 3078 uint8_t value; 3079 3080 if (!iexec->execute) 3081 return 6; 3082 3083 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 3084 "Data: 0x%02X\n", 3085 offset, crtcport, crtcindex, mask, data); 3086 3087 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data; 3088 bios_idxprt_wr(bios, crtcport, crtcindex, value); 3089 3090 return 6; 3091} 3092 3093static int 3094init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3095{ 3096 /* 3097 * INIT_PLL opcode: 0x79 ('y') 3098 * 3099 * offset (8 bit): opcode 3100 * offset + 1 (32 bit): register 3101 * offset + 5 (16 bit): freq 3102 * 3103 * Set PLL register "register" to coefficients for frequency (10kHz) 3104 * "freq" 3105 */ 3106 3107 uint32_t reg = ROM32(bios->data[offset + 1]); 3108 uint16_t freq = ROM16(bios->data[offset + 5]); 3109 3110 if (!iexec->execute) 3111 return 7; 3112 3113 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq); 3114 3115 setPLL(bios, reg, freq * 10); 3116 3117 return 7; 3118} 3119 3120static int 3121init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3122{ 3123 /* 3124 * INIT_ZM_REG opcode: 0x7A ('z') 3125 * 3126 * offset (8 bit): opcode 3127 * offset + 1 (32 bit): register 3128 * offset + 5 (32 bit): value 3129 * 3130 * Assign "value" to "register" 3131 */ 3132 3133 uint32_t reg = ROM32(bios->data[offset + 1]); 3134 uint32_t value = ROM32(bios->data[offset + 5]); 3135 3136 if (!iexec->execute) 3137 return 9; 3138 3139 if (reg == 0x000200) 3140 value |= 1; 3141 3142 bios_wr32(bios, reg, value); 3143 3144 return 9; 3145} 3146 3147static int 3148init_ram_restrict_pll(struct nvbios *bios, uint16_t offset, 3149 struct init_exec *iexec) 3150{ 3151 /* 3152 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('') 3153 * 3154 * offset (8 bit): opcode 3155 * offset + 1 (8 bit): PLL type 3156 * offset + 2 (32 bit): frequency 0 3157 * 3158 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at 3159 * ram_restrict_table_ptr. The value read from there is used to select 3160 * a frequency from the table starting at 'frequency 0' to be 3161 * programmed into the PLL corresponding to 'type'. 3162 * 3163 * The PLL limits table on cards using this opcode has a mapping of 3164 * 'type' to the relevant registers. 3165 */ 3166 3167 struct drm_device *dev = bios->dev; 3168 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2; 3169 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap]; 3170 uint8_t type = bios->data[offset + 1]; 3171 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]); 3172 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry; 3173 int len = 2 + bios->ram_restrict_group_count * 4; 3174 int i; 3175 3176 if (!iexec->execute) 3177 return len; 3178 3179 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) { 3180 NV_ERROR(dev, "PLL limits table not version 3.x\n"); 3181 return len; /* deliberate, allow default clocks to remain */ 3182 } 3183 3184 entry = pll_limits + pll_limits[1]; 3185 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) { 3186 if (entry[0] == type) { 3187 uint32_t reg = ROM32(entry[3]); 3188 3189 BIOSLOG(bios, "0x%04X: " 3190 "Type %02x Reg 0x%08x Freq %dKHz\n", 3191 offset, type, reg, freq); 3192 3193 setPLL(bios, reg, freq); 3194 return len; 3195 } 3196 } 3197 3198 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type); 3199 return len; 3200} 3201 3202static int 3203init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3204{ 3205 /* 3206 * INIT_8C opcode: 0x8C ('') 3207 * 3208 * NOP so far.... 3209 * 3210 */ 3211 3212 return 1; 3213} 3214 3215static int 3216init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3217{ 3218 /* 3219 * INIT_8D opcode: 0x8D ('') 3220 * 3221 * NOP so far.... 3222 * 3223 */ 3224 3225 return 1; 3226} 3227 3228static void 3229init_gpio_unknv50(struct nvbios *bios, struct dcb_gpio_entry *gpio) 3230{ 3231 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c }; 3232 u32 r, s, v; 3233 3234 /* Not a clue, needs de-magicing */ 3235 r = nv50_gpio_ctl[gpio->line >> 4]; 3236 s = (gpio->line & 0x0f); 3237 v = bios_rd32(bios, r) & ~(0x00010001 << s); 3238 switch ((gpio->entry & 0x06000000) >> 25) { 3239 case 1: 3240 v |= (0x00000001 << s); 3241 break; 3242 case 2: 3243 v |= (0x00010000 << s); 3244 break; 3245 default: 3246 break; 3247 } 3248 3249 bios_wr32(bios, r, v); 3250} 3251 3252static void 3253init_gpio_unknvd0(struct nvbios *bios, struct dcb_gpio_entry *gpio) 3254{ 3255 u32 v, i; 3256 3257 v = bios_rd32(bios, 0x00d610 + (gpio->line * 4)); 3258 v &= 0xffffff00; 3259 v |= (gpio->entry & 0x00ff0000) >> 16; 3260 bios_wr32(bios, 0x00d610 + (gpio->line * 4), v); 3261 3262 i = (gpio->entry & 0x1f000000) >> 24; 3263 if (i) { 3264 v = bios_rd32(bios, 0x00d640 + ((i - 1) * 4)); 3265 v &= 0xffffff00; 3266 v |= gpio->line; 3267 bios_wr32(bios, 0x00d640 + ((i - 1) * 4), v); 3268 } 3269} 3270 3271static int 3272init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3273{ 3274 /* 3275 * INIT_GPIO opcode: 0x8E ('') 3276 * 3277 * offset (8 bit): opcode 3278 * 3279 * Loop over all entries in the DCB GPIO table, and initialise 3280 * each GPIO according to various values listed in each entry 3281 */ 3282 3283 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 3284 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio; 3285 int i; 3286 3287 if (dev_priv->card_type < NV_50) { 3288 NV_ERROR(bios->dev, "INIT_GPIO on unsupported chipset\n"); 3289 return 1; 3290 } 3291 3292 if (!iexec->execute) 3293 return 1; 3294 3295 for (i = 0; i < bios->dcb.gpio.entries; i++) { 3296 struct dcb_gpio_entry *gpio = &bios->dcb.gpio.entry[i]; 3297 3298 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, gpio->entry); 3299 3300 BIOSLOG(bios, "0x%04X: set gpio 0x%02x, state %d\n", 3301 offset, gpio->tag, gpio->state_default); 3302 3303 if (!bios->execute) 3304 continue; 3305 3306 pgpio->set(bios->dev, gpio->tag, gpio->state_default); 3307 if (dev_priv->card_type < NV_D0) 3308 init_gpio_unknv50(bios, gpio); 3309 else 3310 init_gpio_unknvd0(bios, gpio); 3311 } 3312 3313 return 1; 3314} 3315 3316static int 3317init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset, 3318 struct init_exec *iexec) 3319{ 3320 /* 3321 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('') 3322 * 3323 * offset (8 bit): opcode 3324 * offset + 1 (32 bit): reg 3325 * offset + 5 (8 bit): regincrement 3326 * offset + 6 (8 bit): count 3327 * offset + 7 (32 bit): value 1,1 3328 * ... 3329 * 3330 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at 3331 * ram_restrict_table_ptr. The value read from here is 'n', and 3332 * "value 1,n" gets written to "reg". This repeats "count" times and on 3333 * each iteration 'm', "reg" increases by "regincrement" and 3334 * "value m,n" is used. The extent of n is limited by a number read 3335 * from the 'M' BIT table, herein called "blocklen" 3336 */ 3337 3338 uint32_t reg = ROM32(bios->data[offset + 1]); 3339 uint8_t regincrement = bios->data[offset + 5]; 3340 uint8_t count = bios->data[offset + 6]; 3341 uint32_t strap_ramcfg, data; 3342 /* previously set by 'M' BIT table */ 3343 uint16_t blocklen = bios->ram_restrict_group_count * 4; 3344 int len = 7 + count * blocklen; 3345 uint8_t index; 3346 int i; 3347 3348 /* critical! to know the length of the opcode */; 3349 if (!blocklen) { 3350 NV_ERROR(bios->dev, 3351 "0x%04X: Zero block length - has the M table " 3352 "been parsed?\n", offset); 3353 return -EINVAL; 3354 } 3355 3356 if (!iexec->execute) 3357 return len; 3358 3359 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf; 3360 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg]; 3361 3362 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, " 3363 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n", 3364 offset, reg, regincrement, count, strap_ramcfg, index); 3365 3366 for (i = 0; i < count; i++) { 3367 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]); 3368 3369 bios_wr32(bios, reg, data); 3370 3371 reg += regincrement; 3372 } 3373 3374 return len; 3375} 3376 3377static int 3378init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3379{ 3380 /* 3381 * INIT_COPY_ZM_REG opcode: 0x90 ('') 3382 * 3383 * offset (8 bit): opcode 3384 * offset + 1 (32 bit): src reg 3385 * offset + 5 (32 bit): dst reg 3386 * 3387 * Put contents of "src reg" into "dst reg" 3388 */ 3389 3390 uint32_t srcreg = ROM32(bios->data[offset + 1]); 3391 uint32_t dstreg = ROM32(bios->data[offset + 5]); 3392 3393 if (!iexec->execute) 3394 return 9; 3395 3396 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg)); 3397 3398 return 9; 3399} 3400 3401static int 3402init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset, 3403 struct init_exec *iexec) 3404{ 3405 /* 3406 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('') 3407 * 3408 * offset (8 bit): opcode 3409 * offset + 1 (32 bit): dst reg 3410 * offset + 5 (8 bit): count 3411 * offset + 6 (32 bit): data 1 3412 * ... 3413 * 3414 * For each of "count" values write "data n" to "dst reg" 3415 */ 3416 3417 uint32_t reg = ROM32(bios->data[offset + 1]); 3418 uint8_t count = bios->data[offset + 5]; 3419 int len = 6 + count * 4; 3420 int i; 3421 3422 if (!iexec->execute) 3423 return len; 3424 3425 for (i = 0; i < count; i++) { 3426 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]); 3427 bios_wr32(bios, reg, data); 3428 } 3429 3430 return len; 3431} 3432 3433static int 3434init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3435{ 3436 /* 3437 * INIT_RESERVED opcode: 0x92 ('') 3438 * 3439 * offset (8 bit): opcode 3440 * 3441 * Seemingly does nothing 3442 */ 3443 3444 return 1; 3445} 3446 3447static int 3448init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3449{ 3450 /* 3451 * INIT_96 opcode: 0x96 ('') 3452 * 3453 * offset (8 bit): opcode 3454 * offset + 1 (32 bit): sreg 3455 * offset + 5 (8 bit): sshift 3456 * offset + 6 (8 bit): smask 3457 * offset + 7 (8 bit): index 3458 * offset + 8 (32 bit): reg 3459 * offset + 12 (32 bit): mask 3460 * offset + 16 (8 bit): shift 3461 * 3462 */ 3463 3464 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2); 3465 uint32_t reg = ROM32(bios->data[offset + 8]); 3466 uint32_t mask = ROM32(bios->data[offset + 12]); 3467 uint32_t val; 3468 3469 val = bios_rd32(bios, ROM32(bios->data[offset + 1])); 3470 if (bios->data[offset + 5] < 0x80) 3471 val >>= bios->data[offset + 5]; 3472 else 3473 val <<= (0x100 - bios->data[offset + 5]); 3474 val &= bios->data[offset + 6]; 3475 3476 val = bios->data[ROM16(bios->data[xlatptr]) + val]; 3477 val <<= bios->data[offset + 16]; 3478 3479 if (!iexec->execute) 3480 return 17; 3481 3482 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val); 3483 return 17; 3484} 3485 3486static int 3487init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3488{ 3489 /* 3490 * INIT_97 opcode: 0x97 ('') 3491 * 3492 * offset (8 bit): opcode 3493 * offset + 1 (32 bit): register 3494 * offset + 5 (32 bit): mask 3495 * offset + 9 (32 bit): value 3496 * 3497 * Adds "value" to "register" preserving the fields specified 3498 * by "mask" 3499 */ 3500 3501 uint32_t reg = ROM32(bios->data[offset + 1]); 3502 uint32_t mask = ROM32(bios->data[offset + 5]); 3503 uint32_t add = ROM32(bios->data[offset + 9]); 3504 uint32_t val; 3505 3506 val = bios_rd32(bios, reg); 3507 val = (val & mask) | ((val + add) & ~mask); 3508 3509 if (!iexec->execute) 3510 return 13; 3511 3512 bios_wr32(bios, reg, val); 3513 return 13; 3514} 3515 3516static int 3517init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3518{ 3519 /* 3520 * INIT_AUXCH opcode: 0x98 ('') 3521 * 3522 * offset (8 bit): opcode 3523 * offset + 1 (32 bit): address 3524 * offset + 5 (8 bit): count 3525 * offset + 6 (8 bit): mask 0 3526 * offset + 7 (8 bit): data 0 3527 * ... 3528 * 3529 */ 3530 3531 struct drm_device *dev = bios->dev; 3532 struct nouveau_i2c_chan *auxch; 3533 uint32_t addr = ROM32(bios->data[offset + 1]); 3534 uint8_t count = bios->data[offset + 5]; 3535 int len = 6 + count * 2; 3536 int ret, i; 3537 3538 if (!bios->display.output) { 3539 NV_ERROR(dev, "INIT_AUXCH: no active output\n"); 3540 return len; 3541 } 3542 3543 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index); 3544 if (!auxch) { 3545 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n", 3546 bios->display.output->i2c_index); 3547 return len; 3548 } 3549 3550 if (!iexec->execute) 3551 return len; 3552 3553 offset += 6; 3554 for (i = 0; i < count; i++, offset += 2) { 3555 uint8_t data; 3556 3557 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1); 3558 if (ret) { 3559 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret); 3560 return len; 3561 } 3562 3563 data &= bios->data[offset + 0]; 3564 data |= bios->data[offset + 1]; 3565 3566 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1); 3567 if (ret) { 3568 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret); 3569 return len; 3570 } 3571 } 3572 3573 return len; 3574} 3575 3576static int 3577init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3578{ 3579 /* 3580 * INIT_ZM_AUXCH opcode: 0x99 ('') 3581 * 3582 * offset (8 bit): opcode 3583 * offset + 1 (32 bit): address 3584 * offset + 5 (8 bit): count 3585 * offset + 6 (8 bit): data 0 3586 * ... 3587 * 3588 */ 3589 3590 struct drm_device *dev = bios->dev; 3591 struct nouveau_i2c_chan *auxch; 3592 uint32_t addr = ROM32(bios->data[offset + 1]); 3593 uint8_t count = bios->data[offset + 5]; 3594 int len = 6 + count; 3595 int ret, i; 3596 3597 if (!bios->display.output) { 3598 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n"); 3599 return len; 3600 } 3601 3602 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index); 3603 if (!auxch) { 3604 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n", 3605 bios->display.output->i2c_index); 3606 return len; 3607 } 3608 3609 if (!iexec->execute) 3610 return len; 3611 3612 offset += 6; 3613 for (i = 0; i < count; i++, offset++) { 3614 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1); 3615 if (ret) { 3616 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret); 3617 return len; 3618 } 3619 } 3620 3621 return len; 3622} 3623 3624static int 3625init_i2c_long_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3626{ 3627 /* 3628 * INIT_I2C_LONG_IF opcode: 0x9A ('') 3629 * 3630 * offset (8 bit): opcode 3631 * offset + 1 (8 bit): DCB I2C table entry index 3632 * offset + 2 (8 bit): I2C slave address 3633 * offset + 3 (16 bit): I2C register 3634 * offset + 5 (8 bit): mask 3635 * offset + 6 (8 bit): data 3636 * 3637 * Read the register given by "I2C register" on the device addressed 3638 * by "I2C slave address" on the I2C bus given by "DCB I2C table 3639 * entry index". Compare the result AND "mask" to "data". 3640 * If they're not equal, skip subsequent opcodes until condition is 3641 * inverted (INIT_NOT), or we hit INIT_RESUME 3642 */ 3643 3644 uint8_t i2c_index = bios->data[offset + 1]; 3645 uint8_t i2c_address = bios->data[offset + 2] >> 1; 3646 uint8_t reglo = bios->data[offset + 3]; 3647 uint8_t reghi = bios->data[offset + 4]; 3648 uint8_t mask = bios->data[offset + 5]; 3649 uint8_t data = bios->data[offset + 6]; 3650 struct nouveau_i2c_chan *chan; 3651 uint8_t buf0[2] = { reghi, reglo }; 3652 uint8_t buf1[1]; 3653 struct i2c_msg msg[2] = { 3654 { i2c_address, 0, 1, buf0 }, 3655 { i2c_address, I2C_M_RD, 1, buf1 }, 3656 }; 3657 int ret; 3658 3659 /* no execute check by design */ 3660 3661 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n", 3662 offset, i2c_index, i2c_address); 3663 3664 chan = init_i2c_device_find(bios->dev, i2c_index); 3665 if (!chan) 3666 return -ENODEV; 3667 3668 3669 ret = i2c_transfer(&chan->adapter, msg, 2); 3670 if (ret < 0) { 3671 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: [no device], " 3672 "Mask: 0x%02X, Data: 0x%02X\n", 3673 offset, reghi, reglo, mask, data); 3674 iexec->execute = 0; 3675 return 7; 3676 } 3677 3678 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: 0x%02X, " 3679 "Mask: 0x%02X, Data: 0x%02X\n", 3680 offset, reghi, reglo, buf1[0], mask, data); 3681 3682 iexec->execute = ((buf1[0] & mask) == data); 3683 3684 return 7; 3685} 3686 3687static struct init_tbl_entry itbl_entry[] = { 3688 /* command name , id , length , offset , mult , command handler */ 3689 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */ 3690 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog }, 3691 { "INIT_REPEAT" , 0x33, init_repeat }, 3692 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll }, 3693 { "INIT_END_REPEAT" , 0x36, init_end_repeat }, 3694 { "INIT_COPY" , 0x37, init_copy }, 3695 { "INIT_NOT" , 0x38, init_not }, 3696 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition }, 3697 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition }, 3698 { "INIT_OP_3B" , 0x3B, init_op_3b }, 3699 { "INIT_OP_3C" , 0x3C, init_op_3c }, 3700 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched }, 3701 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 }, 3702 { "INIT_PLL2" , 0x4B, init_pll2 }, 3703 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte }, 3704 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte }, 3705 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c }, 3706 { "INIT_TMDS" , 0x4F, init_tmds }, 3707 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group }, 3708 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch }, 3709 { "INIT_CR" , 0x52, init_cr }, 3710 { "INIT_ZM_CR" , 0x53, init_zm_cr }, 3711 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group }, 3712 { "INIT_CONDITION_TIME" , 0x56, init_condition_time }, 3713 { "INIT_LTIME" , 0x57, init_ltime }, 3714 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence }, 3715 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */ 3716 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct }, 3717 { "INIT_JUMP" , 0x5C, init_jump }, 3718 { "INIT_I2C_IF" , 0x5E, init_i2c_if }, 3719 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg }, 3720 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io }, 3721 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem }, 3722 { "INIT_RESET" , 0x65, init_reset }, 3723 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem }, 3724 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk }, 3725 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit }, 3726 { "INIT_IO" , 0x69, init_io }, 3727 { "INIT_SUB" , 0x6B, init_sub }, 3728 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition }, 3729 { "INIT_NV_REG" , 0x6E, init_nv_reg }, 3730 { "INIT_MACRO" , 0x6F, init_macro }, 3731 { "INIT_DONE" , 0x71, init_done }, 3732 { "INIT_RESUME" , 0x72, init_resume }, 3733 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */ 3734 { "INIT_TIME" , 0x74, init_time }, 3735 { "INIT_CONDITION" , 0x75, init_condition }, 3736 { "INIT_IO_CONDITION" , 0x76, init_io_condition }, 3737 { "INIT_INDEX_IO" , 0x78, init_index_io }, 3738 { "INIT_PLL" , 0x79, init_pll }, 3739 { "INIT_ZM_REG" , 0x7A, init_zm_reg }, 3740 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll }, 3741 { "INIT_8C" , 0x8C, init_8c }, 3742 { "INIT_8D" , 0x8D, init_8d }, 3743 { "INIT_GPIO" , 0x8E, init_gpio }, 3744 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group }, 3745 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg }, 3746 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched }, 3747 { "INIT_RESERVED" , 0x92, init_reserved }, 3748 { "INIT_96" , 0x96, init_96 }, 3749 { "INIT_97" , 0x97, init_97 }, 3750 { "INIT_AUXCH" , 0x98, init_auxch }, 3751 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch }, 3752 { "INIT_I2C_LONG_IF" , 0x9A, init_i2c_long_if }, 3753 { NULL , 0 , NULL } 3754}; 3755 3756#define MAX_TABLE_OPS 1000 3757 3758static int 3759parse_init_table(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3760{ 3761 /* 3762 * Parses all commands in an init table. 3763 * 3764 * We start out executing all commands found in the init table. Some 3765 * opcodes may change the status of iexec->execute to SKIP, which will 3766 * cause the following opcodes to perform no operation until the value 3767 * is changed back to EXECUTE. 3768 */ 3769 3770 int count = 0, i, ret; 3771 uint8_t id; 3772 3773 /* catch NULL script pointers */ 3774 if (offset == 0) 3775 return 0; 3776 3777 /* 3778 * Loop until INIT_DONE causes us to break out of the loop 3779 * (or until offset > bios length just in case... ) 3780 * (and no more than MAX_TABLE_OPS iterations, just in case... ) 3781 */ 3782 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) { 3783 id = bios->data[offset]; 3784 3785 /* Find matching id in itbl_entry */ 3786 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++) 3787 ; 3788 3789 if (!itbl_entry[i].name) { 3790 NV_ERROR(bios->dev, 3791 "0x%04X: Init table command not found: " 3792 "0x%02X\n", offset, id); 3793 return -ENOENT; 3794 } 3795 3796 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset, 3797 itbl_entry[i].id, itbl_entry[i].name); 3798 3799 /* execute eventual command handler */ 3800 ret = (*itbl_entry[i].handler)(bios, offset, iexec); 3801 if (ret < 0) { 3802 NV_ERROR(bios->dev, "0x%04X: Failed parsing init " 3803 "table opcode: %s %d\n", offset, 3804 itbl_entry[i].name, ret); 3805 } 3806 3807 if (ret <= 0) 3808 break; 3809 3810 /* 3811 * Add the offset of the current command including all data 3812 * of that command. The offset will then be pointing on the 3813 * next op code. 3814 */ 3815 offset += ret; 3816 } 3817 3818 if (offset >= bios->length) 3819 NV_WARN(bios->dev, 3820 "Offset 0x%04X greater than known bios image length. " 3821 "Corrupt image?\n", offset); 3822 if (count >= MAX_TABLE_OPS) 3823 NV_WARN(bios->dev, 3824 "More than %d opcodes to a table is unlikely, " 3825 "is the bios image corrupt?\n", MAX_TABLE_OPS); 3826 3827 return 0; 3828} 3829 3830static void 3831parse_init_tables(struct nvbios *bios) 3832{ 3833 /* Loops and calls parse_init_table() for each present table. */ 3834 3835 int i = 0; 3836 uint16_t table; 3837 struct init_exec iexec = {true, false}; 3838 3839 if (bios->old_style_init) { 3840 if (bios->init_script_tbls_ptr) 3841 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec); 3842 if (bios->extra_init_script_tbl_ptr) 3843 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec); 3844 3845 return; 3846 } 3847 3848 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) { 3849 NV_INFO(bios->dev, 3850 "Parsing VBIOS init table %d at offset 0x%04X\n", 3851 i / 2, table); 3852 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table); 3853 3854 parse_init_table(bios, table, &iexec); 3855 i += 2; 3856 } 3857} 3858 3859static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk) 3860{ 3861 int compare_record_len, i = 0; 3862 uint16_t compareclk, scriptptr = 0; 3863 3864 if (bios->major_version < 5) /* pre BIT */ 3865 compare_record_len = 3; 3866 else 3867 compare_record_len = 4; 3868 3869 do { 3870 compareclk = ROM16(bios->data[clktable + compare_record_len * i]); 3871 if (pxclk >= compareclk * 10) { 3872 if (bios->major_version < 5) { 3873 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i]; 3874 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]); 3875 } else 3876 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]); 3877 break; 3878 } 3879 i++; 3880 } while (compareclk); 3881 3882 return scriptptr; 3883} 3884 3885static void 3886run_digital_op_script(struct drm_device *dev, uint16_t scriptptr, 3887 struct dcb_entry *dcbent, int head, bool dl) 3888{ 3889 struct drm_nouveau_private *dev_priv = dev->dev_private; 3890 struct nvbios *bios = &dev_priv->vbios; 3891 struct init_exec iexec = {true, false}; 3892 3893 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n", 3894 scriptptr); 3895 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44, 3896 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA); 3897 /* note: if dcb entries have been merged, index may be misleading */ 3898 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index); 3899 parse_init_table(bios, scriptptr, &iexec); 3900 3901 nv04_dfp_bind_head(dev, dcbent, head, dl); 3902} 3903 3904static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script) 3905{ 3906 struct drm_nouveau_private *dev_priv = dev->dev_private; 3907 struct nvbios *bios = &dev_priv->vbios; 3908 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0); 3909 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]); 3910 3911 if (!bios->fp.xlated_entry || !sub || !scriptofs) 3912 return -EINVAL; 3913 3914 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link); 3915 3916 if (script == LVDS_PANEL_OFF) { 3917 /* off-on delay in ms */ 3918 mdelay(ROM16(bios->data[bios->fp.xlated_entry + 7])); 3919 } 3920#ifdef __powerpc__ 3921 /* Powerbook specific quirks */ 3922 if (script == LVDS_RESET && 3923 (dev->pci_device == 0x0179 || dev->pci_device == 0x0189 || 3924 dev->pci_device == 0x0329)) 3925 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72); 3926#endif 3927 3928 return 0; 3929} 3930 3931static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk) 3932{ 3933 /* 3934 * The BIT LVDS table's header has the information to setup the 3935 * necessary registers. Following the standard 4 byte header are: 3936 * A bitmask byte and a dual-link transition pxclk value for use in 3937 * selecting the init script when not using straps; 4 script pointers 3938 * for panel power, selected by output and on/off; and 8 table pointers 3939 * for panel init, the needed one determined by output, and bits in the 3940 * conf byte. These tables are similar to the TMDS tables, consisting 3941 * of a list of pxclks and script pointers. 3942 */ 3943 struct drm_nouveau_private *dev_priv = dev->dev_private; 3944 struct nvbios *bios = &dev_priv->vbios; 3945 unsigned int outputset = (dcbent->or == 4) ? 1 : 0; 3946 uint16_t scriptptr = 0, clktable; 3947 3948 /* 3949 * For now we assume version 3.0 table - g80 support will need some 3950 * changes 3951 */ 3952 3953 switch (script) { 3954 case LVDS_INIT: 3955 return -ENOSYS; 3956 case LVDS_BACKLIGHT_ON: 3957 case LVDS_PANEL_ON: 3958 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]); 3959 break; 3960 case LVDS_BACKLIGHT_OFF: 3961 case LVDS_PANEL_OFF: 3962 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]); 3963 break; 3964 case LVDS_RESET: 3965 clktable = bios->fp.lvdsmanufacturerpointer + 15; 3966 if (dcbent->or == 4) 3967 clktable += 8; 3968 3969 if (dcbent->lvdsconf.use_straps_for_mode) { 3970 if (bios->fp.dual_link) 3971 clktable += 4; 3972 if (bios->fp.if_is_24bit) 3973 clktable += 2; 3974 } else { 3975 /* using EDID */ 3976 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1; 3977 3978 if (bios->fp.dual_link) { 3979 clktable += 4; 3980 cmpval_24bit <<= 1; 3981 } 3982 3983 if (bios->fp.strapless_is_24bit & cmpval_24bit) 3984 clktable += 2; 3985 } 3986 3987 clktable = ROM16(bios->data[clktable]); 3988 if (!clktable) { 3989 NV_ERROR(dev, "Pixel clock comparison table not found\n"); 3990 return -ENOENT; 3991 } 3992 scriptptr = clkcmptable(bios, clktable, pxclk); 3993 } 3994 3995 if (!scriptptr) { 3996 NV_ERROR(dev, "LVDS output init script not found\n"); 3997 return -ENOENT; 3998 } 3999 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link); 4000 4001 return 0; 4002} 4003 4004int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk) 4005{ 4006 /* 4007 * LVDS operations are multiplexed in an effort to present a single API 4008 * which works with two vastly differing underlying structures. 4009 * This acts as the demux 4010 */ 4011 4012 struct drm_nouveau_private *dev_priv = dev->dev_private; 4013 struct nvbios *bios = &dev_priv->vbios; 4014 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer]; 4015 uint32_t sel_clk_binding, sel_clk; 4016 int ret; 4017 4018 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver || 4019 (lvds_ver >= 0x30 && script == LVDS_INIT)) 4020 return 0; 4021 4022 if (!bios->fp.lvds_init_run) { 4023 bios->fp.lvds_init_run = true; 4024 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk); 4025 } 4026 4027 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change) 4028 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk); 4029 if (script == LVDS_RESET && bios->fp.power_off_for_reset) 4030 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk); 4031 4032 NV_TRACE(dev, "Calling LVDS script %d:\n", script); 4033 4034 /* don't let script change pll->head binding */ 4035 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000; 4036 4037 if (lvds_ver < 0x30) 4038 ret = call_lvds_manufacturer_script(dev, dcbent, head, script); 4039 else 4040 ret = run_lvds_table(dev, dcbent, head, script, pxclk); 4041 4042 bios->fp.last_script_invoc = (script << 1 | head); 4043 4044 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; 4045 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); 4046 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */ 4047 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0); 4048 4049 return ret; 4050} 4051 4052struct lvdstableheader { 4053 uint8_t lvds_ver, headerlen, recordlen; 4054}; 4055 4056static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth) 4057{ 4058 /* 4059 * BMP version (0xa) LVDS table has a simple header of version and 4060 * record length. The BIT LVDS table has the typical BIT table header: 4061 * version byte, header length byte, record length byte, and a byte for 4062 * the maximum number of records that can be held in the table. 4063 */ 4064 4065 uint8_t lvds_ver, headerlen, recordlen; 4066 4067 memset(lth, 0, sizeof(struct lvdstableheader)); 4068 4069 if (bios->fp.lvdsmanufacturerpointer == 0x0) { 4070 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n"); 4071 return -EINVAL; 4072 } 4073 4074 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer]; 4075 4076 switch (lvds_ver) { 4077 case 0x0a: /* pre NV40 */ 4078 headerlen = 2; 4079 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 4080 break; 4081 case 0x30: /* NV4x */ 4082 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 4083 if (headerlen < 0x1f) { 4084 NV_ERROR(dev, "LVDS table header not understood\n"); 4085 return -EINVAL; 4086 } 4087 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2]; 4088 break; 4089 case 0x40: /* G80/G90 */ 4090 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 4091 if (headerlen < 0x7) { 4092 NV_ERROR(dev, "LVDS table header not understood\n"); 4093 return -EINVAL; 4094 } 4095 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2]; 4096 break; 4097 default: 4098 NV_ERROR(dev, 4099 "LVDS table revision %d.%d not currently supported\n", 4100 lvds_ver >> 4, lvds_ver & 0xf); 4101 return -ENOSYS; 4102 } 4103 4104 lth->lvds_ver = lvds_ver; 4105 lth->headerlen = headerlen; 4106 lth->recordlen = recordlen; 4107 4108 return 0; 4109} 4110 4111static int 4112get_fp_strap(struct drm_device *dev, struct nvbios *bios) 4113{ 4114 struct drm_nouveau_private *dev_priv = dev->dev_private; 4115 4116 /* 4117 * The fp strap is normally dictated by the "User Strap" in 4118 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the 4119 * Internal_Flags struct at 0x48 is set, the user strap gets overriden 4120 * by the PCI subsystem ID during POST, but not before the previous user 4121 * strap has been committed to CR58 for CR57=0xf on head A, which may be 4122 * read and used instead 4123 */ 4124 4125 if (bios->major_version < 5 && bios->data[0x48] & 0x4) 4126 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf; 4127 4128 if (dev_priv->card_type >= NV_50) 4129 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf; 4130 else 4131 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf; 4132} 4133 4134static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios) 4135{ 4136 uint8_t *fptable; 4137 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex; 4138 int ret, ofs, fpstrapping; 4139 struct lvdstableheader lth; 4140 4141 if (bios->fp.fptablepointer == 0x0) { 4142 /* Apple cards don't have the fp table; the laptops use DDC */ 4143 /* The table is also missing on some x86 IGPs */ 4144#ifndef __powerpc__ 4145 NV_ERROR(dev, "Pointer to flat panel table invalid\n"); 4146#endif 4147 bios->digital_min_front_porch = 0x4b; 4148 return 0; 4149 } 4150 4151 fptable = &bios->data[bios->fp.fptablepointer]; 4152 fptable_ver = fptable[0]; 4153 4154 switch (fptable_ver) { 4155 /* 4156 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no 4157 * version field, and miss one of the spread spectrum/PWM bytes. 4158 * This could affect early GF2Go parts (not seen any appropriate ROMs 4159 * though). Here we assume that a version of 0x05 matches this case 4160 * (combining with a BMP version check would be better), as the 4161 * common case for the panel type field is 0x0005, and that is in 4162 * fact what we are reading the first byte of. 4163 */ 4164 case 0x05: /* some NV10, 11, 15, 16 */ 4165 recordlen = 42; 4166 ofs = -1; 4167 break; 4168 case 0x10: /* some NV15/16, and NV11+ */ 4169 recordlen = 44; 4170 ofs = 0; 4171 break; 4172 case 0x20: /* NV40+ */ 4173 headerlen = fptable[1]; 4174 recordlen = fptable[2]; 4175 fpentries = fptable[3]; 4176 /* 4177 * fptable[4] is the minimum 4178 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap 4179 */ 4180 bios->digital_min_front_porch = fptable[4]; 4181 ofs = -7; 4182 break; 4183 default: 4184 NV_ERROR(dev, 4185 "FP table revision %d.%d not currently supported\n", 4186 fptable_ver >> 4, fptable_ver & 0xf); 4187 return -ENOSYS; 4188 } 4189 4190 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */ 4191 return 0; 4192 4193 ret = parse_lvds_manufacturer_table_header(dev, bios, <h); 4194 if (ret) 4195 return ret; 4196 4197 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) { 4198 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer + 4199 lth.headerlen + 1; 4200 bios->fp.xlatwidth = lth.recordlen; 4201 } 4202 if (bios->fp.fpxlatetableptr == 0x0) { 4203 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n"); 4204 return -EINVAL; 4205 } 4206 4207 fpstrapping = get_fp_strap(dev, bios); 4208 4209 fpindex = bios->data[bios->fp.fpxlatetableptr + 4210 fpstrapping * bios->fp.xlatwidth]; 4211 4212 if (fpindex > fpentries) { 4213 NV_ERROR(dev, "Bad flat panel table index\n"); 4214 return -ENOENT; 4215 } 4216 4217 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */ 4218 if (lth.lvds_ver > 0x10) 4219 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf; 4220 4221 /* 4222 * If either the strap or xlated fpindex value are 0xf there is no 4223 * panel using a strap-derived bios mode present. this condition 4224 * includes, but is different from, the DDC panel indicator above 4225 */ 4226 if (fpstrapping == 0xf || fpindex == 0xf) 4227 return 0; 4228 4229 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen + 4230 recordlen * fpindex + ofs; 4231 4232 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n", 4233 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1, 4234 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1, 4235 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10); 4236 4237 return 0; 4238} 4239 4240bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode) 4241{ 4242 struct drm_nouveau_private *dev_priv = dev->dev_private; 4243 struct nvbios *bios = &dev_priv->vbios; 4244 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr]; 4245 4246 if (!mode) /* just checking whether we can produce a mode */ 4247 return bios->fp.mode_ptr; 4248 4249 memset(mode, 0, sizeof(struct drm_display_mode)); 4250 /* 4251 * For version 1.0 (version in byte 0): 4252 * bytes 1-2 are "panel type", including bits on whether Colour/mono, 4253 * single/dual link, and type (TFT etc.) 4254 * bytes 3-6 are bits per colour in RGBX 4255 */ 4256 mode->clock = ROM16(mode_entry[7]) * 10; 4257 /* bytes 9-10 is HActive */ 4258 mode->hdisplay = ROM16(mode_entry[11]) + 1; 4259 /* 4260 * bytes 13-14 is HValid Start 4261 * bytes 15-16 is HValid End 4262 */ 4263 mode->hsync_start = ROM16(mode_entry[17]) + 1; 4264 mode->hsync_end = ROM16(mode_entry[19]) + 1; 4265 mode->htotal = ROM16(mode_entry[21]) + 1; 4266 /* bytes 23-24, 27-30 similarly, but vertical */ 4267 mode->vdisplay = ROM16(mode_entry[25]) + 1; 4268 mode->vsync_start = ROM16(mode_entry[31]) + 1; 4269 mode->vsync_end = ROM16(mode_entry[33]) + 1; 4270 mode->vtotal = ROM16(mode_entry[35]) + 1; 4271 mode->flags |= (mode_entry[37] & 0x10) ? 4272 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4273 mode->flags |= (mode_entry[37] & 0x1) ? 4274 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4275 /* 4276 * bytes 38-39 relate to spread spectrum settings 4277 * bytes 40-43 are something to do with PWM 4278 */ 4279 4280 mode->status = MODE_OK; 4281 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; 4282 drm_mode_set_name(mode); 4283 return bios->fp.mode_ptr; 4284} 4285 4286int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit) 4287{ 4288 /* 4289 * The LVDS table header is (mostly) described in 4290 * parse_lvds_manufacturer_table_header(): the BIT header additionally 4291 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if 4292 * straps are not being used for the panel, this specifies the frequency 4293 * at which modes should be set up in the dual link style. 4294 * 4295 * Following the header, the BMP (ver 0xa) table has several records, 4296 * indexed by a separate xlat table, indexed in turn by the fp strap in 4297 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script 4298 * numbers for use by INIT_SUB which controlled panel init and power, 4299 * and finally a dword of ms to sleep between power off and on 4300 * operations. 4301 * 4302 * In the BIT versions, the table following the header serves as an 4303 * integrated config and xlat table: the records in the table are 4304 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has 4305 * two bytes - the first as a config byte, the second for indexing the 4306 * fp mode table pointed to by the BIT 'D' table 4307 * 4308 * DDC is not used until after card init, so selecting the correct table 4309 * entry and setting the dual link flag for EDID equipped panels, 4310 * requiring tests against the native-mode pixel clock, cannot be done 4311 * until later, when this function should be called with non-zero pxclk 4312 */ 4313 struct drm_nouveau_private *dev_priv = dev->dev_private; 4314 struct nvbios *bios = &dev_priv->vbios; 4315 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0; 4316 struct lvdstableheader lth; 4317 uint16_t lvdsofs; 4318 int ret, chip_version = bios->chip_version; 4319 4320 ret = parse_lvds_manufacturer_table_header(dev, bios, <h); 4321 if (ret) 4322 return ret; 4323 4324 switch (lth.lvds_ver) { 4325 case 0x0a: /* pre NV40 */ 4326 lvdsmanufacturerindex = bios->data[ 4327 bios->fp.fpxlatemanufacturertableptr + 4328 fpstrapping]; 4329 4330 /* we're done if this isn't the EDID panel case */ 4331 if (!pxclk) 4332 break; 4333 4334 if (chip_version < 0x25) { 4335 /* nv17 behaviour 4336 * 4337 * It seems the old style lvds script pointer is reused 4338 * to select 18/24 bit colour depth for EDID panels. 4339 */ 4340 lvdsmanufacturerindex = 4341 (bios->legacy.lvds_single_a_script_ptr & 1) ? 4342 2 : 0; 4343 if (pxclk >= bios->fp.duallink_transition_clk) 4344 lvdsmanufacturerindex++; 4345 } else if (chip_version < 0x30) { 4346 /* nv28 behaviour (off-chip encoder) 4347 * 4348 * nv28 does a complex dance of first using byte 121 of 4349 * the EDID to choose the lvdsmanufacturerindex, then 4350 * later attempting to match the EDID manufacturer and 4351 * product IDs in a table (signature 'pidt' (panel id 4352 * table?)), setting an lvdsmanufacturerindex of 0 and 4353 * an fp strap of the match index (or 0xf if none) 4354 */ 4355 lvdsmanufacturerindex = 0; 4356 } else { 4357 /* nv31, nv34 behaviour */ 4358 lvdsmanufacturerindex = 0; 4359 if (pxclk >= bios->fp.duallink_transition_clk) 4360 lvdsmanufacturerindex = 2; 4361 if (pxclk >= 140000) 4362 lvdsmanufacturerindex = 3; 4363 } 4364 4365 /* 4366 * nvidia set the high nibble of (cr57=f, cr58) to 4367 * lvdsmanufacturerindex in this case; we don't 4368 */ 4369 break; 4370 case 0x30: /* NV4x */ 4371 case 0x40: /* G80/G90 */ 4372 lvdsmanufacturerindex = fpstrapping; 4373 break; 4374 default: 4375 NV_ERROR(dev, "LVDS table revision not currently supported\n"); 4376 return -ENOSYS; 4377 } 4378 4379 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex; 4380 switch (lth.lvds_ver) { 4381 case 0x0a: 4382 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1; 4383 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2; 4384 bios->fp.dual_link = bios->data[lvdsofs] & 4; 4385 bios->fp.link_c_increment = bios->data[lvdsofs] & 8; 4386 *if_is_24bit = bios->data[lvdsofs] & 16; 4387 break; 4388 case 0x30: 4389 case 0x40: 4390 /* 4391 * No sign of the "power off for reset" or "reset for panel 4392 * on" bits, but it's safer to assume we should 4393 */ 4394 bios->fp.power_off_for_reset = true; 4395 bios->fp.reset_after_pclk_change = true; 4396 4397 /* 4398 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is 4399 * over-written, and if_is_24bit isn't used 4400 */ 4401 bios->fp.dual_link = bios->data[lvdsofs] & 1; 4402 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2; 4403 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4]; 4404 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10; 4405 break; 4406 } 4407 4408 /* Dell Latitude D620 reports a too-high value for the dual-link 4409 * transition freq, causing us to program the panel incorrectly. 4410 * 4411 * It doesn't appear the VBIOS actually uses its transition freq 4412 * (90000kHz), instead it uses the "Number of LVDS channels" field 4413 * out of the panel ID structure (http://www.spwg.org/). 4414 * 4415 * For the moment, a quirk will do :) 4416 */ 4417 if (nv_match_device(dev, 0x01d7, 0x1028, 0x01c2)) 4418 bios->fp.duallink_transition_clk = 80000; 4419 4420 /* set dual_link flag for EDID case */ 4421 if (pxclk && (chip_version < 0x25 || chip_version > 0x28)) 4422 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk); 4423 4424 *dl = bios->fp.dual_link; 4425 4426 return 0; 4427} 4428 4429static uint8_t * 4430bios_output_config_match(struct drm_device *dev, struct dcb_entry *dcbent, 4431 uint16_t record, int record_len, int record_nr, 4432 bool match_link) 4433{ 4434 struct drm_nouveau_private *dev_priv = dev->dev_private; 4435 struct nvbios *bios = &dev_priv->vbios; 4436 uint32_t entry; 4437 uint16_t table; 4438 int i, v; 4439 4440 switch (dcbent->type) { 4441 case OUTPUT_TMDS: 4442 case OUTPUT_LVDS: 4443 case OUTPUT_DP: 4444 break; 4445 default: 4446 match_link = false; 4447 break; 4448 } 4449 4450 for (i = 0; i < record_nr; i++, record += record_len) { 4451 table = ROM16(bios->data[record]); 4452 if (!table) 4453 continue; 4454 entry = ROM32(bios->data[table]); 4455 4456 if (match_link) { 4457 v = (entry & 0x00c00000) >> 22; 4458 if (!(v & dcbent->sorconf.link)) 4459 continue; 4460 } 4461 4462 v = (entry & 0x000f0000) >> 16; 4463 if (!(v & dcbent->or)) 4464 continue; 4465 4466 v = (entry & 0x000000f0) >> 4; 4467 if (v != dcbent->location) 4468 continue; 4469 4470 v = (entry & 0x0000000f); 4471 if (v != dcbent->type) 4472 continue; 4473 4474 return &bios->data[table]; 4475 } 4476 4477 return NULL; 4478} 4479 4480void * 4481nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent, 4482 uint8_t *headerlen) 4483{ 4484 struct drm_nouveau_private *dev_priv = dev->dev_private; 4485 struct nvbios *bios = &dev_priv->vbios; 4486 uint8_t *table; 4487 4488 if (!bios->display.dp_table_ptr) { 4489 NV_ERROR(dev, "No pointer to DisplayPort table\n"); 4490 return NULL; 4491 } 4492 table = &bios->data[bios->display.dp_table_ptr]; 4493 4494 if (table[0] != 0x20 && table[0] != 0x21) { 4495 NV_ERROR(dev, "DisplayPort table version 0x%02x unknown\n", 4496 table[0]); 4497 return NULL; 4498 } 4499 4500 *headerlen = table[4]; 4501 return bios_output_config_match(dev, dcbent, 4502 bios->display.dp_table_ptr + table[1], 4503 table[2], table[3], table[0] >= 0x21); 4504} 4505 4506int 4507nouveau_bios_run_display_table(struct drm_device *dev, u16 type, int pclk, 4508 struct dcb_entry *dcbent, int crtc) 4509{ 4510 /* 4511 * The display script table is located by the BIT 'U' table. 4512 * 4513 * It contains an array of pointers to various tables describing 4514 * a particular output type. The first 32-bits of the output 4515 * tables contains similar information to a DCB entry, and is 4516 * used to decide whether that particular table is suitable for 4517 * the output you want to access. 4518 * 4519 * The "record header length" field here seems to indicate the 4520 * offset of the first configuration entry in the output tables. 4521 * This is 10 on most cards I've seen, but 12 has been witnessed 4522 * on DP cards, and there's another script pointer within the 4523 * header. 4524 * 4525 * offset + 0 ( 8 bits): version 4526 * offset + 1 ( 8 bits): header length 4527 * offset + 2 ( 8 bits): record length 4528 * offset + 3 ( 8 bits): number of records 4529 * offset + 4 ( 8 bits): record header length 4530 * offset + 5 (16 bits): pointer to first output script table 4531 */ 4532 4533 struct drm_nouveau_private *dev_priv = dev->dev_private; 4534 struct nvbios *bios = &dev_priv->vbios; 4535 uint8_t *table = &bios->data[bios->display.script_table_ptr]; 4536 uint8_t *otable = NULL; 4537 uint16_t script; 4538 int i = 0; 4539 4540 if (!bios->display.script_table_ptr) { 4541 NV_ERROR(dev, "No pointer to output script table\n"); 4542 return 1; 4543 } 4544 4545 /* 4546 * Nothing useful has been in any of the pre-2.0 tables I've seen, 4547 * so until they are, we really don't need to care. 4548 */ 4549 if (table[0] < 0x20) 4550 return 1; 4551 4552 if (table[0] != 0x20 && table[0] != 0x21) { 4553 NV_ERROR(dev, "Output script table version 0x%02x unknown\n", 4554 table[0]); 4555 return 1; 4556 } 4557 4558 /* 4559 * The output script tables describing a particular output type 4560 * look as follows: 4561 * 4562 * offset + 0 (32 bits): output this table matches (hash of DCB) 4563 * offset + 4 ( 8 bits): unknown 4564 * offset + 5 ( 8 bits): number of configurations 4565 * offset + 6 (16 bits): pointer to some script 4566 * offset + 8 (16 bits): pointer to some script 4567 * 4568 * headerlen == 10 4569 * offset + 10 : configuration 0 4570 * 4571 * headerlen == 12 4572 * offset + 10 : pointer to some script 4573 * offset + 12 : configuration 0 4574 * 4575 * Each config entry is as follows: 4576 * 4577 * offset + 0 (16 bits): unknown, assumed to be a match value 4578 * offset + 2 (16 bits): pointer to script table (clock set?) 4579 * offset + 4 (16 bits): pointer to script table (reset?) 4580 * 4581 * There doesn't appear to be a count value to say how many 4582 * entries exist in each script table, instead, a 0 value in 4583 * the first 16-bit word seems to indicate both the end of the 4584 * list and the default entry. The second 16-bit word in the 4585 * script tables is a pointer to the script to execute. 4586 */ 4587 4588 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n", 4589 dcbent->type, dcbent->location, dcbent->or); 4590 otable = bios_output_config_match(dev, dcbent, table[1] + 4591 bios->display.script_table_ptr, 4592 table[2], table[3], table[0] >= 0x21); 4593 if (!otable) { 4594 NV_DEBUG_KMS(dev, "failed to match any output table\n"); 4595 return 1; 4596 } 4597 4598 if (pclk < -2 || pclk > 0) { 4599 /* Try to find matching script table entry */ 4600 for (i = 0; i < otable[5]; i++) { 4601 if (ROM16(otable[table[4] + i*6]) == type) 4602 break; 4603 } 4604 4605 if (i == otable[5]) { 4606 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, " 4607 "using first\n", 4608 type, dcbent->type, dcbent->or); 4609 i = 0; 4610 } 4611 } 4612 4613 if (pclk == 0) { 4614 script = ROM16(otable[6]); 4615 if (!script) { 4616 NV_DEBUG_KMS(dev, "output script 0 not found\n"); 4617 return 1; 4618 } 4619 4620 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 0\n", script); 4621 nouveau_bios_run_init_table(dev, script, dcbent, crtc); 4622 } else 4623 if (pclk == -1) { 4624 script = ROM16(otable[8]); 4625 if (!script) { 4626 NV_DEBUG_KMS(dev, "output script 1 not found\n"); 4627 return 1; 4628 } 4629 4630 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 1\n", script); 4631 nouveau_bios_run_init_table(dev, script, dcbent, crtc); 4632 } else 4633 if (pclk == -2) { 4634 if (table[4] >= 12) 4635 script = ROM16(otable[10]); 4636 else 4637 script = 0; 4638 if (!script) { 4639 NV_DEBUG_KMS(dev, "output script 2 not found\n"); 4640 return 1; 4641 } 4642 4643 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 2\n", script); 4644 nouveau_bios_run_init_table(dev, script, dcbent, crtc); 4645 } else 4646 if (pclk > 0) { 4647 script = ROM16(otable[table[4] + i*6 + 2]); 4648 if (script) 4649 script = clkcmptable(bios, script, pclk); 4650 if (!script) { 4651 NV_DEBUG_KMS(dev, "clock script 0 not found\n"); 4652 return 1; 4653 } 4654 4655 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 0\n", script); 4656 nouveau_bios_run_init_table(dev, script, dcbent, crtc); 4657 } else 4658 if (pclk < 0) { 4659 script = ROM16(otable[table[4] + i*6 + 4]); 4660 if (script) 4661 script = clkcmptable(bios, script, -pclk); 4662 if (!script) { 4663 NV_DEBUG_KMS(dev, "clock script 1 not found\n"); 4664 return 1; 4665 } 4666 4667 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 1\n", script); 4668 nouveau_bios_run_init_table(dev, script, dcbent, crtc); 4669 } 4670 4671 return 0; 4672} 4673 4674 4675int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk) 4676{ 4677 /* 4678 * the pxclk parameter is in kHz 4679 * 4680 * This runs the TMDS regs setting code found on BIT bios cards 4681 * 4682 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and 4683 * ffs(or) == 3, use the second. 4684 */ 4685 4686 struct drm_nouveau_private *dev_priv = dev->dev_private; 4687 struct nvbios *bios = &dev_priv->vbios; 4688 int cv = bios->chip_version; 4689 uint16_t clktable = 0, scriptptr; 4690 uint32_t sel_clk_binding, sel_clk; 4691 4692 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */ 4693 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 && 4694 dcbent->location != DCB_LOC_ON_CHIP) 4695 return 0; 4696 4697 switch (ffs(dcbent->or)) { 4698 case 1: 4699 clktable = bios->tmds.output0_script_ptr; 4700 break; 4701 case 2: 4702 case 3: 4703 clktable = bios->tmds.output1_script_ptr; 4704 break; 4705 } 4706 4707 if (!clktable) { 4708 NV_ERROR(dev, "Pixel clock comparison table not found\n"); 4709 return -EINVAL; 4710 } 4711 4712 scriptptr = clkcmptable(bios, clktable, pxclk); 4713 4714 if (!scriptptr) { 4715 NV_ERROR(dev, "TMDS output init script not found\n"); 4716 return -ENOENT; 4717 } 4718 4719 /* don't let script change pll->head binding */ 4720 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000; 4721 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000); 4722 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; 4723 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); 4724 4725 return 0; 4726} 4727 4728struct pll_mapping { 4729 u8 type; 4730 u32 reg; 4731}; 4732 4733static struct pll_mapping nv04_pll_mapping[] = { 4734 { PLL_CORE , NV_PRAMDAC_NVPLL_COEFF }, 4735 { PLL_MEMORY, NV_PRAMDAC_MPLL_COEFF }, 4736 { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF }, 4737 { PLL_VPLL1 , NV_RAMDAC_VPLL2 }, 4738 {} 4739}; 4740 4741static struct pll_mapping nv40_pll_mapping[] = { 4742 { PLL_CORE , 0x004000 }, 4743 { PLL_MEMORY, 0x004020 }, 4744 { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF }, 4745 { PLL_VPLL1 , NV_RAMDAC_VPLL2 }, 4746 {} 4747}; 4748 4749static struct pll_mapping nv50_pll_mapping[] = { 4750 { PLL_CORE , 0x004028 }, 4751 { PLL_SHADER, 0x004020 }, 4752 { PLL_UNK03 , 0x004000 }, 4753 { PLL_MEMORY, 0x004008 }, 4754 { PLL_UNK40 , 0x00e810 }, 4755 { PLL_UNK41 , 0x00e818 }, 4756 { PLL_UNK42 , 0x00e824 }, 4757 { PLL_VPLL0 , 0x614100 }, 4758 { PLL_VPLL1 , 0x614900 }, 4759 {} 4760}; 4761 4762static struct pll_mapping nv84_pll_mapping[] = { 4763 { PLL_CORE , 0x004028 }, 4764 { PLL_SHADER, 0x004020 }, 4765 { PLL_MEMORY, 0x004008 }, 4766 { PLL_UNK05 , 0x004030 }, 4767 { PLL_UNK41 , 0x00e818 }, 4768 { PLL_VPLL0 , 0x614100 }, 4769 { PLL_VPLL1 , 0x614900 }, 4770 {} 4771}; 4772 4773u32 4774get_pll_register(struct drm_device *dev, enum pll_types type) 4775{ 4776 struct drm_nouveau_private *dev_priv = dev->dev_private; 4777 struct nvbios *bios = &dev_priv->vbios; 4778 struct pll_mapping *map; 4779 int i; 4780 4781 if (dev_priv->card_type < NV_40) 4782 map = nv04_pll_mapping; 4783 else 4784 if (dev_priv->card_type < NV_50) 4785 map = nv40_pll_mapping; 4786 else { 4787 u8 *plim = &bios->data[bios->pll_limit_tbl_ptr]; 4788 4789 if (plim[0] >= 0x30) { 4790 u8 *entry = plim + plim[1]; 4791 for (i = 0; i < plim[3]; i++, entry += plim[2]) { 4792 if (entry[0] == type) 4793 return ROM32(entry[3]); 4794 } 4795 4796 return 0; 4797 } 4798 4799 if (dev_priv->chipset == 0x50) 4800 map = nv50_pll_mapping; 4801 else 4802 map = nv84_pll_mapping; 4803 } 4804 4805 while (map->reg) { 4806 if (map->type == type) 4807 return map->reg; 4808 map++; 4809 } 4810 4811 return 0; 4812} 4813 4814int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim) 4815{ 4816 /* 4817 * PLL limits table 4818 * 4819 * Version 0x10: NV30, NV31 4820 * One byte header (version), one record of 24 bytes 4821 * Version 0x11: NV36 - Not implemented 4822 * Seems to have same record style as 0x10, but 3 records rather than 1 4823 * Version 0x20: Found on Geforce 6 cards 4824 * Trivial 4 byte BIT header. 31 (0x1f) byte record length 4825 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards 4826 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record 4827 * length in general, some (integrated) have an extra configuration byte 4828 * Version 0x30: Found on Geforce 8, separates the register mapping 4829 * from the limits tables. 4830 */ 4831 4832 struct drm_nouveau_private *dev_priv = dev->dev_private; 4833 struct nvbios *bios = &dev_priv->vbios; 4834 int cv = bios->chip_version, pllindex = 0; 4835 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0; 4836 uint32_t crystal_strap_mask, crystal_straps; 4837 4838 if (!bios->pll_limit_tbl_ptr) { 4839 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 || 4840 cv >= 0x40) { 4841 NV_ERROR(dev, "Pointer to PLL limits table invalid\n"); 4842 return -EINVAL; 4843 } 4844 } else 4845 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr]; 4846 4847 crystal_strap_mask = 1 << 6; 4848 /* open coded dev->twoHeads test */ 4849 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20) 4850 crystal_strap_mask |= 1 << 22; 4851 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) & 4852 crystal_strap_mask; 4853 4854 switch (pll_lim_ver) { 4855 /* 4856 * We use version 0 to indicate a pre limit table bios (single stage 4857 * pll) and load the hard coded limits instead. 4858 */ 4859 case 0: 4860 break; 4861 case 0x10: 4862 case 0x11: 4863 /* 4864 * Strictly v0x11 has 3 entries, but the last two don't seem 4865 * to get used. 4866 */ 4867 headerlen = 1; 4868 recordlen = 0x18; 4869 entries = 1; 4870 pllindex = 0; 4871 break; 4872 case 0x20: 4873 case 0x21: 4874 case 0x30: 4875 case 0x40: 4876 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1]; 4877 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2]; 4878 entries = bios->data[bios->pll_limit_tbl_ptr + 3]; 4879 break; 4880 default: 4881 NV_ERROR(dev, "PLL limits table revision 0x%X not currently " 4882 "supported\n", pll_lim_ver); 4883 return -ENOSYS; 4884 } 4885 4886 /* initialize all members to zero */ 4887 memset(pll_lim, 0, sizeof(struct pll_lims)); 4888 4889 /* if we were passed a type rather than a register, figure 4890 * out the register and store it 4891 */ 4892 if (limit_match > PLL_MAX) 4893 pll_lim->reg = limit_match; 4894 else { 4895 pll_lim->reg = get_pll_register(dev, limit_match); 4896 if (!pll_lim->reg) 4897 return -ENOENT; 4898 } 4899 4900 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) { 4901 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex]; 4902 4903 pll_lim->vco1.minfreq = ROM32(pll_rec[0]); 4904 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]); 4905 pll_lim->vco2.minfreq = ROM32(pll_rec[8]); 4906 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]); 4907 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]); 4908 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]); 4909 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX; 4910 4911 /* these values taken from nv30/31/36 */ 4912 pll_lim->vco1.min_n = 0x1; 4913 if (cv == 0x36) 4914 pll_lim->vco1.min_n = 0x5; 4915 pll_lim->vco1.max_n = 0xff; 4916 pll_lim->vco1.min_m = 0x1; 4917 pll_lim->vco1.max_m = 0xd; 4918 pll_lim->vco2.min_n = 0x4; 4919 /* 4920 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this 4921 * table version (apart from nv35)), N2 is compared to 4922 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and 4923 * save a comparison 4924 */ 4925 pll_lim->vco2.max_n = 0x28; 4926 if (cv == 0x30 || cv == 0x35) 4927 /* only 5 bits available for N2 on nv30/35 */ 4928 pll_lim->vco2.max_n = 0x1f; 4929 pll_lim->vco2.min_m = 0x1; 4930 pll_lim->vco2.max_m = 0x4; 4931 pll_lim->max_log2p = 0x7; 4932 pll_lim->max_usable_log2p = 0x6; 4933 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) { 4934 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen; 4935 uint8_t *pll_rec; 4936 int i; 4937 4938 /* 4939 * First entry is default match, if nothing better. warn if 4940 * reg field nonzero 4941 */ 4942 if (ROM32(bios->data[plloffs])) 4943 NV_WARN(dev, "Default PLL limit entry has non-zero " 4944 "register field\n"); 4945 4946 for (i = 1; i < entries; i++) 4947 if (ROM32(bios->data[plloffs + recordlen * i]) == pll_lim->reg) { 4948 pllindex = i; 4949 break; 4950 } 4951 4952 if ((dev_priv->card_type >= NV_50) && (pllindex == 0)) { 4953 NV_ERROR(dev, "Register 0x%08x not found in PLL " 4954 "limits table", pll_lim->reg); 4955 return -ENOENT; 4956 } 4957 4958 pll_rec = &bios->data[plloffs + recordlen * pllindex]; 4959 4960 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n", 4961 pllindex ? pll_lim->reg : 0); 4962 4963 /* 4964 * Frequencies are stored in tables in MHz, kHz are more 4965 * useful, so we convert. 4966 */ 4967 4968 /* What output frequencies can each VCO generate? */ 4969 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000; 4970 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000; 4971 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000; 4972 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000; 4973 4974 /* What input frequencies they accept (past the m-divider)? */ 4975 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000; 4976 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000; 4977 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000; 4978 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000; 4979 4980 /* What values are accepted as multiplier and divider? */ 4981 pll_lim->vco1.min_n = pll_rec[20]; 4982 pll_lim->vco1.max_n = pll_rec[21]; 4983 pll_lim->vco1.min_m = pll_rec[22]; 4984 pll_lim->vco1.max_m = pll_rec[23]; 4985 pll_lim->vco2.min_n = pll_rec[24]; 4986 pll_lim->vco2.max_n = pll_rec[25]; 4987 pll_lim->vco2.min_m = pll_rec[26]; 4988 pll_lim->vco2.max_m = pll_rec[27]; 4989 4990 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29]; 4991 if (pll_lim->max_log2p > 0x7) 4992 /* pll decoding in nv_hw.c assumes never > 7 */ 4993 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n", 4994 pll_lim->max_log2p); 4995 if (cv < 0x60) 4996 pll_lim->max_usable_log2p = 0x6; 4997 pll_lim->log2p_bias = pll_rec[30]; 4998 4999 if (recordlen > 0x22) 5000 pll_lim->refclk = ROM32(pll_rec[31]); 5001 5002 if (recordlen > 0x23 && pll_rec[35]) 5003 NV_WARN(dev, 5004 "Bits set in PLL configuration byte (%x)\n", 5005 pll_rec[35]); 5006 5007 /* C51 special not seen elsewhere */ 5008 if (cv == 0x51 && !pll_lim->refclk) { 5009 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK); 5010 5011 if ((pll_lim->reg == NV_PRAMDAC_VPLL_COEFF && sel_clk & 0x20) || 5012 (pll_lim->reg == NV_RAMDAC_VPLL2 && sel_clk & 0x80)) { 5013 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3) 5014 pll_lim->refclk = 200000; 5015 else 5016 pll_lim->refclk = 25000; 5017 } 5018 } 5019 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */ 5020 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen]; 5021 uint8_t *record = NULL; 5022 int i; 5023 5024 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n", 5025 pll_lim->reg); 5026 5027 for (i = 0; i < entries; i++, entry += recordlen) { 5028 if (ROM32(entry[3]) == pll_lim->reg) { 5029 record = &bios->data[ROM16(entry[1])]; 5030 break; 5031 } 5032 } 5033 5034 if (!record) { 5035 NV_ERROR(dev, "Register 0x%08x not found in PLL " 5036 "limits table", pll_lim->reg); 5037 return -ENOENT; 5038 } 5039 5040 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000; 5041 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000; 5042 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000; 5043 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000; 5044 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000; 5045 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000; 5046 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000; 5047 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000; 5048 pll_lim->vco1.min_n = record[16]; 5049 pll_lim->vco1.max_n = record[17]; 5050 pll_lim->vco1.min_m = record[18]; 5051 pll_lim->vco1.max_m = record[19]; 5052 pll_lim->vco2.min_n = record[20]; 5053 pll_lim->vco2.max_n = record[21]; 5054 pll_lim->vco2.min_m = record[22]; 5055 pll_lim->vco2.max_m = record[23]; 5056 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25]; 5057 pll_lim->log2p_bias = record[27]; 5058 pll_lim->refclk = ROM32(record[28]); 5059 } else if (pll_lim_ver) { /* ver 0x40 */ 5060 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen]; 5061 uint8_t *record = NULL; 5062 int i; 5063 5064 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n", 5065 pll_lim->reg); 5066 5067 for (i = 0; i < entries; i++, entry += recordlen) { 5068 if (ROM32(entry[3]) == pll_lim->reg) { 5069 record = &bios->data[ROM16(entry[1])]; 5070 break; 5071 } 5072 } 5073 5074 if (!record) { 5075 NV_ERROR(dev, "Register 0x%08x not found in PLL " 5076 "limits table", pll_lim->reg); 5077 return -ENOENT; 5078 } 5079 5080 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000; 5081 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000; 5082 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000; 5083 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000; 5084 pll_lim->vco1.min_m = record[8]; 5085 pll_lim->vco1.max_m = record[9]; 5086 pll_lim->vco1.min_n = record[10]; 5087 pll_lim->vco1.max_n = record[11]; 5088 pll_lim->min_p = record[12]; 5089 pll_lim->max_p = record[13]; 5090 pll_lim->refclk = ROM16(entry[9]) * 1000; 5091 } 5092 5093 /* 5094 * By now any valid limit table ought to have set a max frequency for 5095 * vco1, so if it's zero it's either a pre limit table bios, or one 5096 * with an empty limit table (seen on nv18) 5097 */ 5098 if (!pll_lim->vco1.maxfreq) { 5099 pll_lim->vco1.minfreq = bios->fminvco; 5100 pll_lim->vco1.maxfreq = bios->fmaxvco; 5101 pll_lim->vco1.min_inputfreq = 0; 5102 pll_lim->vco1.max_inputfreq = INT_MAX; 5103 pll_lim->vco1.min_n = 0x1; 5104 pll_lim->vco1.max_n = 0xff; 5105 pll_lim->vco1.min_m = 0x1; 5106 if (crystal_straps == 0) { 5107 /* nv05 does this, nv11 doesn't, nv10 unknown */ 5108 if (cv < 0x11) 5109 pll_lim->vco1.min_m = 0x7; 5110 pll_lim->vco1.max_m = 0xd; 5111 } else { 5112 if (cv < 0x11) 5113 pll_lim->vco1.min_m = 0x8; 5114 pll_lim->vco1.max_m = 0xe; 5115 } 5116 if (cv < 0x17 || cv == 0x1a || cv == 0x20) 5117 pll_lim->max_log2p = 4; 5118 else 5119 pll_lim->max_log2p = 5; 5120 pll_lim->max_usable_log2p = pll_lim->max_log2p; 5121 } 5122 5123 if (!pll_lim->refclk) 5124 switch (crystal_straps) { 5125 case 0: 5126 pll_lim->refclk = 13500; 5127 break; 5128 case (1 << 6): 5129 pll_lim->refclk = 14318; 5130 break; 5131 case (1 << 22): 5132 pll_lim->refclk = 27000; 5133 break; 5134 case (1 << 22 | 1 << 6): 5135 pll_lim->refclk = 25000; 5136 break; 5137 } 5138 5139 NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq); 5140 NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq); 5141 NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq); 5142 NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq); 5143 NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n); 5144 NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n); 5145 NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m); 5146 NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m); 5147 if (pll_lim->vco2.maxfreq) { 5148 NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq); 5149 NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq); 5150 NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq); 5151 NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq); 5152 NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n); 5153 NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n); 5154 NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m); 5155 NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m); 5156 } 5157 if (!pll_lim->max_p) { 5158 NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p); 5159 NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias); 5160 } else { 5161 NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p); 5162 NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p); 5163 } 5164 NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk); 5165 5166 return 0; 5167} 5168 5169static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset) 5170{ 5171 /* 5172 * offset + 0 (8 bits): Micro version 5173 * offset + 1 (8 bits): Minor version 5174 * offset + 2 (8 bits): Chip version 5175 * offset + 3 (8 bits): Major version 5176 */ 5177 5178 bios->major_version = bios->data[offset + 3]; 5179 bios->chip_version = bios->data[offset + 2]; 5180 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n", 5181 bios->data[offset + 3], bios->data[offset + 2], 5182 bios->data[offset + 1], bios->data[offset]); 5183} 5184 5185static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset) 5186{ 5187 /* 5188 * Parses the init table segment for pointers used in script execution. 5189 * 5190 * offset + 0 (16 bits): init script tables pointer 5191 * offset + 2 (16 bits): macro index table pointer 5192 * offset + 4 (16 bits): macro table pointer 5193 * offset + 6 (16 bits): condition table pointer 5194 * offset + 8 (16 bits): io condition table pointer 5195 * offset + 10 (16 bits): io flag condition table pointer 5196 * offset + 12 (16 bits): init function table pointer 5197 */ 5198 5199 bios->init_script_tbls_ptr = ROM16(bios->data[offset]); 5200 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]); 5201 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]); 5202 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]); 5203 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]); 5204 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]); 5205 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]); 5206} 5207 5208static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5209{ 5210 /* 5211 * Parses the load detect values for g80 cards. 5212 * 5213 * offset + 0 (16 bits): loadval table pointer 5214 */ 5215 5216 uint16_t load_table_ptr; 5217 uint8_t version, headerlen, entrylen, num_entries; 5218 5219 if (bitentry->length != 3) { 5220 NV_ERROR(dev, "Do not understand BIT A table\n"); 5221 return -EINVAL; 5222 } 5223 5224 load_table_ptr = ROM16(bios->data[bitentry->offset]); 5225 5226 if (load_table_ptr == 0x0) { 5227 NV_DEBUG(dev, "Pointer to BIT loadval table invalid\n"); 5228 return -EINVAL; 5229 } 5230 5231 version = bios->data[load_table_ptr]; 5232 5233 if (version != 0x10) { 5234 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n", 5235 version >> 4, version & 0xF); 5236 return -ENOSYS; 5237 } 5238 5239 headerlen = bios->data[load_table_ptr + 1]; 5240 entrylen = bios->data[load_table_ptr + 2]; 5241 num_entries = bios->data[load_table_ptr + 3]; 5242 5243 if (headerlen != 4 || entrylen != 4 || num_entries != 2) { 5244 NV_ERROR(dev, "Do not understand BIT loadval table\n"); 5245 return -EINVAL; 5246 } 5247 5248 /* First entry is normal dac, 2nd tv-out perhaps? */ 5249 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff; 5250 5251 return 0; 5252} 5253 5254static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5255{ 5256 /* 5257 * offset + 8 (16 bits): PLL limits table pointer 5258 * 5259 * There's more in here, but that's unknown. 5260 */ 5261 5262 if (bitentry->length < 10) { 5263 NV_ERROR(dev, "Do not understand BIT C table\n"); 5264 return -EINVAL; 5265 } 5266 5267 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]); 5268 5269 return 0; 5270} 5271 5272static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5273{ 5274 /* 5275 * Parses the flat panel table segment that the bit entry points to. 5276 * Starting at bitentry->offset: 5277 * 5278 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte 5279 * records beginning with a freq. 5280 * offset + 2 (16 bits): mode table pointer 5281 */ 5282 5283 if (bitentry->length != 4) { 5284 NV_ERROR(dev, "Do not understand BIT display table\n"); 5285 return -EINVAL; 5286 } 5287 5288 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]); 5289 5290 return 0; 5291} 5292 5293static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5294{ 5295 /* 5296 * Parses the init table segment that the bit entry points to. 5297 * 5298 * See parse_script_table_pointers for layout 5299 */ 5300 5301 if (bitentry->length < 14) { 5302 NV_ERROR(dev, "Do not understand init table\n"); 5303 return -EINVAL; 5304 } 5305 5306 parse_script_table_pointers(bios, bitentry->offset); 5307 5308 if (bitentry->length >= 16) 5309 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]); 5310 if (bitentry->length >= 18) 5311 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]); 5312 5313 return 0; 5314} 5315 5316static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5317{ 5318 /* 5319 * BIT 'i' (info?) table 5320 * 5321 * offset + 0 (32 bits): BIOS version dword (as in B table) 5322 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?) 5323 * offset + 13 (16 bits): pointer to table containing DAC load 5324 * detection comparison values 5325 * 5326 * There's other things in the table, purpose unknown 5327 */ 5328 5329 uint16_t daccmpoffset; 5330 uint8_t dacver, dacheaderlen; 5331 5332 if (bitentry->length < 6) { 5333 NV_ERROR(dev, "BIT i table too short for needed information\n"); 5334 return -EINVAL; 5335 } 5336 5337 parse_bios_version(dev, bios, bitentry->offset); 5338 5339 /* 5340 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's 5341 * Quadro identity crisis), other bits possibly as for BMP feature byte 5342 */ 5343 bios->feature_byte = bios->data[bitentry->offset + 5]; 5344 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE; 5345 5346 if (bitentry->length < 15) { 5347 NV_WARN(dev, "BIT i table not long enough for DAC load " 5348 "detection comparison table\n"); 5349 return -EINVAL; 5350 } 5351 5352 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]); 5353 5354 /* doesn't exist on g80 */ 5355 if (!daccmpoffset) 5356 return 0; 5357 5358 /* 5359 * The first value in the table, following the header, is the 5360 * comparison value, the second entry is a comparison value for 5361 * TV load detection. 5362 */ 5363 5364 dacver = bios->data[daccmpoffset]; 5365 dacheaderlen = bios->data[daccmpoffset + 1]; 5366 5367 if (dacver != 0x00 && dacver != 0x10) { 5368 NV_WARN(dev, "DAC load detection comparison table version " 5369 "%d.%d not known\n", dacver >> 4, dacver & 0xf); 5370 return -ENOSYS; 5371 } 5372 5373 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]); 5374 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]); 5375 5376 return 0; 5377} 5378 5379static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5380{ 5381 /* 5382 * Parses the LVDS table segment that the bit entry points to. 5383 * Starting at bitentry->offset: 5384 * 5385 * offset + 0 (16 bits): LVDS strap xlate table pointer 5386 */ 5387 5388 if (bitentry->length != 2) { 5389 NV_ERROR(dev, "Do not understand BIT LVDS table\n"); 5390 return -EINVAL; 5391 } 5392 5393 /* 5394 * No idea if it's still called the LVDS manufacturer table, but 5395 * the concept's close enough. 5396 */ 5397 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]); 5398 5399 return 0; 5400} 5401 5402static int 5403parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios, 5404 struct bit_entry *bitentry) 5405{ 5406 /* 5407 * offset + 2 (8 bits): number of options in an 5408 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set 5409 * offset + 3 (16 bits): pointer to strap xlate table for RAM 5410 * restrict option selection 5411 * 5412 * There's a bunch of bits in this table other than the RAM restrict 5413 * stuff that we don't use - their use currently unknown 5414 */ 5415 5416 /* 5417 * Older bios versions don't have a sufficiently long table for 5418 * what we want 5419 */ 5420 if (bitentry->length < 0x5) 5421 return 0; 5422 5423 if (bitentry->version < 2) { 5424 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2]; 5425 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]); 5426 } else { 5427 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0]; 5428 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]); 5429 } 5430 5431 return 0; 5432} 5433 5434static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5435{ 5436 /* 5437 * Parses the pointer to the TMDS table 5438 * 5439 * Starting at bitentry->offset: 5440 * 5441 * offset + 0 (16 bits): TMDS table pointer 5442 * 5443 * The TMDS table is typically found just before the DCB table, with a 5444 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being 5445 * length?) 5446 * 5447 * At offset +7 is a pointer to a script, which I don't know how to 5448 * run yet. 5449 * At offset +9 is a pointer to another script, likewise 5450 * Offset +11 has a pointer to a table where the first word is a pxclk 5451 * frequency and the second word a pointer to a script, which should be 5452 * run if the comparison pxclk frequency is less than the pxclk desired. 5453 * This repeats for decreasing comparison frequencies 5454 * Offset +13 has a pointer to a similar table 5455 * The selection of table (and possibly +7/+9 script) is dictated by 5456 * "or" from the DCB. 5457 */ 5458 5459 uint16_t tmdstableptr, script1, script2; 5460 5461 if (bitentry->length != 2) { 5462 NV_ERROR(dev, "Do not understand BIT TMDS table\n"); 5463 return -EINVAL; 5464 } 5465 5466 tmdstableptr = ROM16(bios->data[bitentry->offset]); 5467 if (!tmdstableptr) { 5468 NV_ERROR(dev, "Pointer to TMDS table invalid\n"); 5469 return -EINVAL; 5470 } 5471 5472 NV_INFO(dev, "TMDS table version %d.%d\n", 5473 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf); 5474 5475 /* nv50+ has v2.0, but we don't parse it atm */ 5476 if (bios->data[tmdstableptr] != 0x11) 5477 return -ENOSYS; 5478 5479 /* 5480 * These two scripts are odd: they don't seem to get run even when 5481 * they are not stubbed. 5482 */ 5483 script1 = ROM16(bios->data[tmdstableptr + 7]); 5484 script2 = ROM16(bios->data[tmdstableptr + 9]); 5485 if (bios->data[script1] != 'q' || bios->data[script2] != 'q') 5486 NV_WARN(dev, "TMDS table script pointers not stubbed\n"); 5487 5488 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]); 5489 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]); 5490 5491 return 0; 5492} 5493 5494static int 5495parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios, 5496 struct bit_entry *bitentry) 5497{ 5498 /* 5499 * Parses the pointer to the G80 output script tables 5500 * 5501 * Starting at bitentry->offset: 5502 * 5503 * offset + 0 (16 bits): output script table pointer 5504 */ 5505 5506 uint16_t outputscripttableptr; 5507 5508 if (bitentry->length != 3) { 5509 NV_ERROR(dev, "Do not understand BIT U table\n"); 5510 return -EINVAL; 5511 } 5512 5513 outputscripttableptr = ROM16(bios->data[bitentry->offset]); 5514 bios->display.script_table_ptr = outputscripttableptr; 5515 return 0; 5516} 5517 5518static int 5519parse_bit_displayport_tbl_entry(struct drm_device *dev, struct nvbios *bios, 5520 struct bit_entry *bitentry) 5521{ 5522 bios->display.dp_table_ptr = ROM16(bios->data[bitentry->offset]); 5523 return 0; 5524} 5525 5526struct bit_table { 5527 const char id; 5528 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *); 5529}; 5530 5531#define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry }) 5532 5533int 5534bit_table(struct drm_device *dev, u8 id, struct bit_entry *bit) 5535{ 5536 struct drm_nouveau_private *dev_priv = dev->dev_private; 5537 struct nvbios *bios = &dev_priv->vbios; 5538 u8 entries, *entry; 5539 5540 entries = bios->data[bios->offset + 10]; 5541 entry = &bios->data[bios->offset + 12]; 5542 while (entries--) { 5543 if (entry[0] == id) { 5544 bit->id = entry[0]; 5545 bit->version = entry[1]; 5546 bit->length = ROM16(entry[2]); 5547 bit->offset = ROM16(entry[4]); 5548 bit->data = ROMPTR(bios, entry[4]); 5549 return 0; 5550 } 5551 5552 entry += bios->data[bios->offset + 9]; 5553 } 5554 5555 return -ENOENT; 5556} 5557 5558static int 5559parse_bit_table(struct nvbios *bios, const uint16_t bitoffset, 5560 struct bit_table *table) 5561{ 5562 struct drm_device *dev = bios->dev; 5563 struct bit_entry bitentry; 5564 5565 if (bit_table(dev, table->id, &bitentry) == 0) 5566 return table->parse_fn(dev, bios, &bitentry); 5567 5568 NV_INFO(dev, "BIT table '%c' not found\n", table->id); 5569 return -ENOSYS; 5570} 5571 5572static int 5573parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset) 5574{ 5575 int ret; 5576 5577 /* 5578 * The only restriction on parsing order currently is having 'i' first 5579 * for use of bios->*_version or bios->feature_byte while parsing; 5580 * functions shouldn't be actually *doing* anything apart from pulling 5581 * data from the image into the bios struct, thus no interdependencies 5582 */ 5583 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i)); 5584 if (ret) /* info? */ 5585 return ret; 5586 if (bios->major_version >= 0x60) /* g80+ */ 5587 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A)); 5588 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C)); 5589 if (ret) 5590 return ret; 5591 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display)); 5592 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init)); 5593 if (ret) 5594 return ret; 5595 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */ 5596 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds)); 5597 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds)); 5598 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U)); 5599 parse_bit_table(bios, bitoffset, &BIT_TABLE('d', displayport)); 5600 5601 return 0; 5602} 5603 5604static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset) 5605{ 5606 /* 5607 * Parses the BMP structure for useful things, but does not act on them 5608 * 5609 * offset + 5: BMP major version 5610 * offset + 6: BMP minor version 5611 * offset + 9: BMP feature byte 5612 * offset + 10: BCD encoded BIOS version 5613 * 5614 * offset + 18: init script table pointer (for bios versions < 5.10h) 5615 * offset + 20: extra init script table pointer (for bios 5616 * versions < 5.10h) 5617 * 5618 * offset + 24: memory init table pointer (used on early bios versions) 5619 * offset + 26: SDR memory sequencing setup data table 5620 * offset + 28: DDR memory sequencing setup data table 5621 * 5622 * offset + 54: index of I2C CRTC pair to use for CRT output 5623 * offset + 55: index of I2C CRTC pair to use for TV output 5624 * offset + 56: index of I2C CRTC pair to use for flat panel output 5625 * offset + 58: write CRTC index for I2C pair 0 5626 * offset + 59: read CRTC index for I2C pair 0 5627 * offset + 60: write CRTC index for I2C pair 1 5628 * offset + 61: read CRTC index for I2C pair 1 5629 * 5630 * offset + 67: maximum internal PLL frequency (single stage PLL) 5631 * offset + 71: minimum internal PLL frequency (single stage PLL) 5632 * 5633 * offset + 75: script table pointers, as described in 5634 * parse_script_table_pointers 5635 * 5636 * offset + 89: TMDS single link output A table pointer 5637 * offset + 91: TMDS single link output B table pointer 5638 * offset + 95: LVDS single link output A table pointer 5639 * offset + 105: flat panel timings table pointer 5640 * offset + 107: flat panel strapping translation table pointer 5641 * offset + 117: LVDS manufacturer panel config table pointer 5642 * offset + 119: LVDS manufacturer strapping translation table pointer 5643 * 5644 * offset + 142: PLL limits table pointer 5645 * 5646 * offset + 156: minimum pixel clock for LVDS dual link 5647 */ 5648 5649 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor; 5650 uint16_t bmplength; 5651 uint16_t legacy_scripts_offset, legacy_i2c_offset; 5652 5653 /* load needed defaults in case we can't parse this info */ 5654 bios->dcb.i2c[0].write = NV_CIO_CRE_DDC_WR__INDEX; 5655 bios->dcb.i2c[0].read = NV_CIO_CRE_DDC_STATUS__INDEX; 5656 bios->dcb.i2c[1].write = NV_CIO_CRE_DDC0_WR__INDEX; 5657 bios->dcb.i2c[1].read = NV_CIO_CRE_DDC0_STATUS__INDEX; 5658 bios->digital_min_front_porch = 0x4b; 5659 bios->fmaxvco = 256000; 5660 bios->fminvco = 128000; 5661 bios->fp.duallink_transition_clk = 90000; 5662 5663 bmp_version_major = bmp[5]; 5664 bmp_version_minor = bmp[6]; 5665 5666 NV_TRACE(dev, "BMP version %d.%d\n", 5667 bmp_version_major, bmp_version_minor); 5668 5669 /* 5670 * Make sure that 0x36 is blank and can't be mistaken for a DCB 5671 * pointer on early versions 5672 */ 5673 if (bmp_version_major < 5) 5674 *(uint16_t *)&bios->data[0x36] = 0; 5675 5676 /* 5677 * Seems that the minor version was 1 for all major versions prior 5678 * to 5. Version 6 could theoretically exist, but I suspect BIT 5679 * happened instead. 5680 */ 5681 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) { 5682 NV_ERROR(dev, "You have an unsupported BMP version. " 5683 "Please send in your bios\n"); 5684 return -ENOSYS; 5685 } 5686 5687 if (bmp_version_major == 0) 5688 /* nothing that's currently useful in this version */ 5689 return 0; 5690 else if (bmp_version_major == 1) 5691 bmplength = 44; /* exact for 1.01 */ 5692 else if (bmp_version_major == 2) 5693 bmplength = 48; /* exact for 2.01 */ 5694 else if (bmp_version_major == 3) 5695 bmplength = 54; 5696 /* guessed - mem init tables added in this version */ 5697 else if (bmp_version_major == 4 || bmp_version_minor < 0x1) 5698 /* don't know if 5.0 exists... */ 5699 bmplength = 62; 5700 /* guessed - BMP I2C indices added in version 4*/ 5701 else if (bmp_version_minor < 0x6) 5702 bmplength = 67; /* exact for 5.01 */ 5703 else if (bmp_version_minor < 0x10) 5704 bmplength = 75; /* exact for 5.06 */ 5705 else if (bmp_version_minor == 0x10) 5706 bmplength = 89; /* exact for 5.10h */ 5707 else if (bmp_version_minor < 0x14) 5708 bmplength = 118; /* exact for 5.11h */ 5709 else if (bmp_version_minor < 0x24) 5710 /* 5711 * Not sure of version where pll limits came in; 5712 * certainly exist by 0x24 though. 5713 */ 5714 /* length not exact: this is long enough to get lvds members */ 5715 bmplength = 123; 5716 else if (bmp_version_minor < 0x27) 5717 /* 5718 * Length not exact: this is long enough to get pll limit 5719 * member 5720 */ 5721 bmplength = 144; 5722 else 5723 /* 5724 * Length not exact: this is long enough to get dual link 5725 * transition clock. 5726 */ 5727 bmplength = 158; 5728 5729 /* checksum */ 5730 if (nv_cksum(bmp, 8)) { 5731 NV_ERROR(dev, "Bad BMP checksum\n"); 5732 return -EINVAL; 5733 } 5734 5735 /* 5736 * Bit 4 seems to indicate either a mobile bios or a quadro card -- 5737 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl 5738 * (not nv10gl), bit 5 that the flat panel tables are present, and 5739 * bit 6 a tv bios. 5740 */ 5741 bios->feature_byte = bmp[9]; 5742 5743 parse_bios_version(dev, bios, offset + 10); 5744 5745 if (bmp_version_major < 5 || bmp_version_minor < 0x10) 5746 bios->old_style_init = true; 5747 legacy_scripts_offset = 18; 5748 if (bmp_version_major < 2) 5749 legacy_scripts_offset -= 4; 5750 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]); 5751 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]); 5752 5753 if (bmp_version_major > 2) { /* appears in BMP 3 */ 5754 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]); 5755 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]); 5756 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]); 5757 } 5758 5759 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */ 5760 if (bmplength > 61) 5761 legacy_i2c_offset = offset + 54; 5762 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset]; 5763 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1]; 5764 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2]; 5765 if (bios->data[legacy_i2c_offset + 4]) 5766 bios->dcb.i2c[0].write = bios->data[legacy_i2c_offset + 4]; 5767 if (bios->data[legacy_i2c_offset + 5]) 5768 bios->dcb.i2c[0].read = bios->data[legacy_i2c_offset + 5]; 5769 if (bios->data[legacy_i2c_offset + 6]) 5770 bios->dcb.i2c[1].write = bios->data[legacy_i2c_offset + 6]; 5771 if (bios->data[legacy_i2c_offset + 7]) 5772 bios->dcb.i2c[1].read = bios->data[legacy_i2c_offset + 7]; 5773 5774 if (bmplength > 74) { 5775 bios->fmaxvco = ROM32(bmp[67]); 5776 bios->fminvco = ROM32(bmp[71]); 5777 } 5778 if (bmplength > 88) 5779 parse_script_table_pointers(bios, offset + 75); 5780 if (bmplength > 94) { 5781 bios->tmds.output0_script_ptr = ROM16(bmp[89]); 5782 bios->tmds.output1_script_ptr = ROM16(bmp[91]); 5783 /* 5784 * Never observed in use with lvds scripts, but is reused for 5785 * 18/24 bit panel interface default for EDID equipped panels 5786 * (if_is_24bit not set directly to avoid any oscillation). 5787 */ 5788 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]); 5789 } 5790 if (bmplength > 108) { 5791 bios->fp.fptablepointer = ROM16(bmp[105]); 5792 bios->fp.fpxlatetableptr = ROM16(bmp[107]); 5793 bios->fp.xlatwidth = 1; 5794 } 5795 if (bmplength > 120) { 5796 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]); 5797 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]); 5798 } 5799 if (bmplength > 143) 5800 bios->pll_limit_tbl_ptr = ROM16(bmp[142]); 5801 5802 if (bmplength > 157) 5803 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10; 5804 5805 return 0; 5806} 5807 5808static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len) 5809{ 5810 int i, j; 5811 5812 for (i = 0; i <= (n - len); i++) { 5813 for (j = 0; j < len; j++) 5814 if (data[i + j] != str[j]) 5815 break; 5816 if (j == len) 5817 return i; 5818 } 5819 5820 return 0; 5821} 5822 5823static struct dcb_gpio_entry * 5824new_gpio_entry(struct nvbios *bios) 5825{ 5826 struct drm_device *dev = bios->dev; 5827 struct dcb_gpio_table *gpio = &bios->dcb.gpio; 5828 5829 if (gpio->entries >= DCB_MAX_NUM_GPIO_ENTRIES) { 5830 NV_ERROR(dev, "exceeded maximum number of gpio entries!!\n"); 5831 return NULL; 5832 } 5833 5834 return &gpio->entry[gpio->entries++]; 5835} 5836 5837struct dcb_gpio_entry * 5838nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag) 5839{ 5840 struct drm_nouveau_private *dev_priv = dev->dev_private; 5841 struct nvbios *bios = &dev_priv->vbios; 5842 int i; 5843 5844 for (i = 0; i < bios->dcb.gpio.entries; i++) { 5845 if (bios->dcb.gpio.entry[i].tag != tag) 5846 continue; 5847 5848 return &bios->dcb.gpio.entry[i]; 5849 } 5850 5851 return NULL; 5852} 5853 5854static void 5855parse_dcb_gpio_table(struct nvbios *bios) 5856{ 5857 struct drm_device *dev = bios->dev; 5858 struct dcb_gpio_entry *e; 5859 u8 headerlen, entries, recordlen; 5860 u8 *dcb, *gpio = NULL, *entry; 5861 int i; 5862 5863 dcb = ROMPTR(bios, bios->data[0x36]); 5864 if (dcb[0] >= 0x30) { 5865 gpio = ROMPTR(bios, dcb[10]); 5866 if (!gpio) 5867 goto no_table; 5868 5869 headerlen = gpio[1]; 5870 entries = gpio[2]; 5871 recordlen = gpio[3]; 5872 } else 5873 if (dcb[0] >= 0x22 && dcb[-1] >= 0x13) { 5874 gpio = ROMPTR(bios, dcb[-15]); 5875 if (!gpio) 5876 goto no_table; 5877 5878 headerlen = 3; 5879 entries = gpio[2]; 5880 recordlen = gpio[1]; 5881 } else 5882 if (dcb[0] >= 0x22) { 5883 /* No GPIO table present, parse the TVDAC GPIO data. */ 5884 uint8_t *tvdac_gpio = &dcb[-5]; 5885 5886 if (tvdac_gpio[0] & 1) { 5887 e = new_gpio_entry(bios); 5888 e->tag = DCB_GPIO_TVDAC0; 5889 e->line = tvdac_gpio[1] >> 4; 5890 e->invert = tvdac_gpio[0] & 2; 5891 } 5892 5893 goto no_table; 5894 } else { 5895 NV_DEBUG(dev, "no/unknown gpio table on DCB 0x%02x\n", dcb[0]); 5896 goto no_table; 5897 } 5898 5899 entry = gpio + headerlen; 5900 for (i = 0; i < entries; i++, entry += recordlen) { 5901 e = new_gpio_entry(bios); 5902 if (!e) 5903 break; 5904 5905 if (gpio[0] < 0x40) { 5906 e->entry = ROM16(entry[0]); 5907 e->tag = (e->entry & 0x07e0) >> 5; 5908 if (e->tag == 0x3f) { 5909 bios->dcb.gpio.entries--; 5910 continue; 5911 } 5912 5913 e->line = (e->entry & 0x001f); 5914 e->invert = ((e->entry & 0xf800) >> 11) != 4; 5915 } else { 5916 e->entry = ROM32(entry[0]); 5917 e->tag = (e->entry & 0x0000ff00) >> 8; 5918 if (e->tag == 0xff) { 5919 bios->dcb.gpio.entries--; 5920 continue; 5921 } 5922 5923 e->line = (e->entry & 0x0000001f) >> 0; 5924 if (gpio[0] == 0x40) { 5925 e->state_default = (e->entry & 0x01000000) >> 24; 5926 e->state[0] = (e->entry & 0x18000000) >> 27; 5927 e->state[1] = (e->entry & 0x60000000) >> 29; 5928 } else { 5929 e->state_default = (e->entry & 0x00000080) >> 7; 5930 e->state[0] = (entry[4] >> 4) & 3; 5931 e->state[1] = (entry[4] >> 6) & 3; 5932 } 5933 } 5934 } 5935 5936no_table: 5937 /* Apple iMac G4 NV18 */ 5938 if (nv_match_device(dev, 0x0189, 0x10de, 0x0010)) { 5939 e = new_gpio_entry(bios); 5940 if (e) { 5941 e->tag = DCB_GPIO_TVDAC0; 5942 e->line = 4; 5943 } 5944 } 5945} 5946 5947struct dcb_connector_table_entry * 5948nouveau_bios_connector_entry(struct drm_device *dev, int index) 5949{ 5950 struct drm_nouveau_private *dev_priv = dev->dev_private; 5951 struct nvbios *bios = &dev_priv->vbios; 5952 struct dcb_connector_table_entry *cte; 5953 5954 if (index >= bios->dcb.connector.entries) 5955 return NULL; 5956 5957 cte = &bios->dcb.connector.entry[index]; 5958 if (cte->type == 0xff) 5959 return NULL; 5960 5961 return cte; 5962} 5963 5964static enum dcb_connector_type 5965divine_connector_type(struct nvbios *bios, int index) 5966{ 5967 struct dcb_table *dcb = &bios->dcb; 5968 unsigned encoders = 0, type = DCB_CONNECTOR_NONE; 5969 int i; 5970 5971 for (i = 0; i < dcb->entries; i++) { 5972 if (dcb->entry[i].connector == index) 5973 encoders |= (1 << dcb->entry[i].type); 5974 } 5975 5976 if (encoders & (1 << OUTPUT_DP)) { 5977 if (encoders & (1 << OUTPUT_TMDS)) 5978 type = DCB_CONNECTOR_DP; 5979 else 5980 type = DCB_CONNECTOR_eDP; 5981 } else 5982 if (encoders & (1 << OUTPUT_TMDS)) { 5983 if (encoders & (1 << OUTPUT_ANALOG)) 5984 type = DCB_CONNECTOR_DVI_I; 5985 else 5986 type = DCB_CONNECTOR_DVI_D; 5987 } else 5988 if (encoders & (1 << OUTPUT_ANALOG)) { 5989 type = DCB_CONNECTOR_VGA; 5990 } else 5991 if (encoders & (1 << OUTPUT_LVDS)) { 5992 type = DCB_CONNECTOR_LVDS; 5993 } else 5994 if (encoders & (1 << OUTPUT_TV)) { 5995 type = DCB_CONNECTOR_TV_0; 5996 } 5997 5998 return type; 5999} 6000 6001static void 6002apply_dcb_connector_quirks(struct nvbios *bios, int idx) 6003{ 6004 struct dcb_connector_table_entry *cte = &bios->dcb.connector.entry[idx]; 6005 struct drm_device *dev = bios->dev; 6006 6007 /* Gigabyte NX85T */ 6008 if (nv_match_device(dev, 0x0421, 0x1458, 0x344c)) { 6009 if (cte->type == DCB_CONNECTOR_HDMI_1) 6010 cte->type = DCB_CONNECTOR_DVI_I; 6011 } 6012 6013 /* Gigabyte GV-NX86T512H */ 6014 if (nv_match_device(dev, 0x0402, 0x1458, 0x3455)) { 6015 if (cte->type == DCB_CONNECTOR_HDMI_1) 6016 cte->type = DCB_CONNECTOR_DVI_I; 6017 } 6018} 6019 6020static const u8 hpd_gpio[16] = { 6021 0xff, 0x07, 0x08, 0xff, 0xff, 0x51, 0x52, 0xff, 6022 0xff, 0xff, 0xff, 0xff, 0xff, 0x5e, 0x5f, 0x60, 6023}; 6024 6025static void 6026parse_dcb_connector_table(struct nvbios *bios) 6027{ 6028 struct drm_device *dev = bios->dev; 6029 struct dcb_connector_table *ct = &bios->dcb.connector; 6030 struct dcb_connector_table_entry *cte; 6031 uint8_t *conntab = &bios->data[bios->dcb.connector_table_ptr]; 6032 uint8_t *entry; 6033 int i; 6034 6035 if (!bios->dcb.connector_table_ptr) { 6036 NV_DEBUG_KMS(dev, "No DCB connector table present\n"); 6037 return; 6038 } 6039 6040 NV_INFO(dev, "DCB connector table: VHER 0x%02x %d %d %d\n", 6041 conntab[0], conntab[1], conntab[2], conntab[3]); 6042 if ((conntab[0] != 0x30 && conntab[0] != 0x40) || 6043 (conntab[3] != 2 && conntab[3] != 4)) { 6044 NV_ERROR(dev, " Unknown! Please report.\n"); 6045 return; 6046 } 6047 6048 ct->entries = conntab[2]; 6049 6050 entry = conntab + conntab[1]; 6051 cte = &ct->entry[0]; 6052 for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) { 6053 cte->index = i; 6054 if (conntab[3] == 2) 6055 cte->entry = ROM16(entry[0]); 6056 else 6057 cte->entry = ROM32(entry[0]); 6058 6059 cte->type = (cte->entry & 0x000000ff) >> 0; 6060 cte->index2 = (cte->entry & 0x00000f00) >> 8; 6061 6062 cte->gpio_tag = ffs((cte->entry & 0x07033000) >> 12); 6063 cte->gpio_tag = hpd_gpio[cte->gpio_tag]; 6064 6065 if (cte->type == 0xff) 6066 continue; 6067 6068 apply_dcb_connector_quirks(bios, i); 6069 6070 NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n", 6071 i, cte->entry, cte->type, cte->index, cte->gpio_tag); 6072 6073 /* check for known types, fallback to guessing the type 6074 * from attached encoders if we hit an unknown. 6075 */ 6076 switch (cte->type) { 6077 case DCB_CONNECTOR_VGA: 6078 case DCB_CONNECTOR_TV_0: 6079 case DCB_CONNECTOR_TV_1: 6080 case DCB_CONNECTOR_TV_3: 6081 case DCB_CONNECTOR_DVI_I: 6082 case DCB_CONNECTOR_DVI_D: 6083 case DCB_CONNECTOR_LVDS: 6084 case DCB_CONNECTOR_LVDS_SPWG: 6085 case DCB_CONNECTOR_DP: 6086 case DCB_CONNECTOR_eDP: 6087 case DCB_CONNECTOR_HDMI_0: 6088 case DCB_CONNECTOR_HDMI_1: 6089 break; 6090 default: 6091 cte->type = divine_connector_type(bios, cte->index); 6092 NV_WARN(dev, "unknown type, using 0x%02x\n", cte->type); 6093 break; 6094 } 6095 6096 if (nouveau_override_conntype) { 6097 int type = divine_connector_type(bios, cte->index); 6098 if (type != cte->type) 6099 NV_WARN(dev, " -> type 0x%02x\n", cte->type); 6100 } 6101 6102 } 6103} 6104 6105static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb) 6106{ 6107 struct dcb_entry *entry = &dcb->entry[dcb->entries]; 6108 6109 memset(entry, 0, sizeof(struct dcb_entry)); 6110 entry->index = dcb->entries++; 6111 6112 return entry; 6113} 6114 6115static void fabricate_dcb_output(struct dcb_table *dcb, int type, int i2c, 6116 int heads, int or) 6117{ 6118 struct dcb_entry *entry = new_dcb_entry(dcb); 6119 6120 entry->type = type; 6121 entry->i2c_index = i2c; 6122 entry->heads = heads; 6123 if (type != OUTPUT_ANALOG) 6124 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */ 6125 entry->or = or; 6126} 6127 6128static bool 6129parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb, 6130 uint32_t conn, uint32_t conf, struct dcb_entry *entry) 6131{ 6132 entry->type = conn & 0xf; 6133 entry->i2c_index = (conn >> 4) & 0xf; 6134 entry->heads = (conn >> 8) & 0xf; 6135 if (dcb->version >= 0x40) 6136 entry->connector = (conn >> 12) & 0xf; 6137 entry->bus = (conn >> 16) & 0xf; 6138 entry->location = (conn >> 20) & 0x3; 6139 entry->or = (conn >> 24) & 0xf; 6140 6141 switch (entry->type) { 6142 case OUTPUT_ANALOG: 6143 /* 6144 * Although the rest of a CRT conf dword is usually 6145 * zeros, mac biosen have stuff there so we must mask 6146 */ 6147 entry->crtconf.maxfreq = (dcb->version < 0x30) ? 6148 (conf & 0xffff) * 10 : 6149 (conf & 0xff) * 10000; 6150 break; 6151 case OUTPUT_LVDS: 6152 { 6153 uint32_t mask; 6154 if (conf & 0x1) 6155 entry->lvdsconf.use_straps_for_mode = true; 6156 if (dcb->version < 0x22) { 6157 mask = ~0xd; 6158 /* 6159 * The laptop in bug 14567 lies and claims to not use 6160 * straps when it does, so assume all DCB 2.0 laptops 6161 * use straps, until a broken EDID using one is produced 6162 */ 6163 entry->lvdsconf.use_straps_for_mode = true; 6164 /* 6165 * Both 0x4 and 0x8 show up in v2.0 tables; assume they 6166 * mean the same thing (probably wrong, but might work) 6167 */ 6168 if (conf & 0x4 || conf & 0x8) 6169 entry->lvdsconf.use_power_scripts = true; 6170 } else { 6171 mask = ~0x7; 6172 if (conf & 0x2) 6173 entry->lvdsconf.use_acpi_for_edid = true; 6174 if (conf & 0x4) 6175 entry->lvdsconf.use_power_scripts = true; 6176 entry->lvdsconf.sor.link = (conf & 0x00000030) >> 4; 6177 } 6178 if (conf & mask) { 6179 /* 6180 * Until we even try to use these on G8x, it's 6181 * useless reporting unknown bits. They all are. 6182 */ 6183 if (dcb->version >= 0x40) 6184 break; 6185 6186 NV_ERROR(dev, "Unknown LVDS configuration bits, " 6187 "please report\n"); 6188 } 6189 break; 6190 } 6191 case OUTPUT_TV: 6192 { 6193 if (dcb->version >= 0x30) 6194 entry->tvconf.has_component_output = conf & (0x8 << 4); 6195 else 6196 entry->tvconf.has_component_output = false; 6197 6198 break; 6199 } 6200 case OUTPUT_DP: 6201 entry->dpconf.sor.link = (conf & 0x00000030) >> 4; 6202 switch ((conf & 0x00e00000) >> 21) { 6203 case 0: 6204 entry->dpconf.link_bw = 162000; 6205 break; 6206 default: 6207 entry->dpconf.link_bw = 270000; 6208 break; 6209 } 6210 switch ((conf & 0x0f000000) >> 24) { 6211 case 0xf: 6212 entry->dpconf.link_nr = 4; 6213 break; 6214 case 0x3: 6215 entry->dpconf.link_nr = 2; 6216 break; 6217 default: 6218 entry->dpconf.link_nr = 1; 6219 break; 6220 } 6221 break; 6222 case OUTPUT_TMDS: 6223 if (dcb->version >= 0x40) 6224 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4; 6225 else if (dcb->version >= 0x30) 6226 entry->tmdsconf.slave_addr = (conf & 0x00000700) >> 8; 6227 else if (dcb->version >= 0x22) 6228 entry->tmdsconf.slave_addr = (conf & 0x00000070) >> 4; 6229 6230 break; 6231 case OUTPUT_EOL: 6232 /* weird g80 mobile type that "nv" treats as a terminator */ 6233 dcb->entries--; 6234 return false; 6235 default: 6236 break; 6237 } 6238 6239 if (dcb->version < 0x40) { 6240 /* Normal entries consist of a single bit, but dual link has 6241 * the next most significant bit set too 6242 */ 6243 entry->duallink_possible = 6244 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or); 6245 } else { 6246 entry->duallink_possible = (entry->sorconf.link == 3); 6247 } 6248 6249 /* unsure what DCB version introduces this, 3.0? */ 6250 if (conf & 0x100000) 6251 entry->i2c_upper_default = true; 6252 6253 return true; 6254} 6255 6256static bool 6257parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb, 6258 uint32_t conn, uint32_t conf, struct dcb_entry *entry) 6259{ 6260 switch (conn & 0x0000000f) { 6261 case 0: 6262 entry->type = OUTPUT_ANALOG; 6263 break; 6264 case 1: 6265 entry->type = OUTPUT_TV; 6266 break; 6267 case 2: 6268 case 4: 6269 if (conn & 0x10) 6270 entry->type = OUTPUT_LVDS; 6271 else 6272 entry->type = OUTPUT_TMDS; 6273 break; 6274 case 3: 6275 entry->type = OUTPUT_LVDS; 6276 break; 6277 default: 6278 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f); 6279 return false; 6280 } 6281 6282 entry->i2c_index = (conn & 0x0003c000) >> 14; 6283 entry->heads = ((conn & 0x001c0000) >> 18) + 1; 6284 entry->or = entry->heads; /* same as heads, hopefully safe enough */ 6285 entry->location = (conn & 0x01e00000) >> 21; 6286 entry->bus = (conn & 0x0e000000) >> 25; 6287 entry->duallink_possible = false; 6288 6289 switch (entry->type) { 6290 case OUTPUT_ANALOG: 6291 entry->crtconf.maxfreq = (conf & 0xffff) * 10; 6292 break; 6293 case OUTPUT_TV: 6294 entry->tvconf.has_component_output = false; 6295 break; 6296 case OUTPUT_LVDS: 6297 if ((conn & 0x00003f00) >> 8 != 0x10) 6298 entry->lvdsconf.use_straps_for_mode = true; 6299 entry->lvdsconf.use_power_scripts = true; 6300 break; 6301 default: 6302 break; 6303 } 6304 6305 return true; 6306} 6307 6308static bool parse_dcb_entry(struct drm_device *dev, struct dcb_table *dcb, 6309 uint32_t conn, uint32_t conf) 6310{ 6311 struct dcb_entry *entry = new_dcb_entry(dcb); 6312 bool ret; 6313 6314 if (dcb->version >= 0x20) 6315 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry); 6316 else 6317 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry); 6318 if (!ret) 6319 return ret; 6320 6321 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table, 6322 entry->i2c_index, &dcb->i2c[entry->i2c_index]); 6323 6324 return true; 6325} 6326 6327static 6328void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb) 6329{ 6330 /* 6331 * DCB v2.0 lists each output combination separately. 6332 * Here we merge compatible entries to have fewer outputs, with 6333 * more options 6334 */ 6335 6336 int i, newentries = 0; 6337 6338 for (i = 0; i < dcb->entries; i++) { 6339 struct dcb_entry *ient = &dcb->entry[i]; 6340 int j; 6341 6342 for (j = i + 1; j < dcb->entries; j++) { 6343 struct dcb_entry *jent = &dcb->entry[j]; 6344 6345 if (jent->type == 100) /* already merged entry */ 6346 continue; 6347 6348 /* merge heads field when all other fields the same */ 6349 if (jent->i2c_index == ient->i2c_index && 6350 jent->type == ient->type && 6351 jent->location == ient->location && 6352 jent->or == ient->or) { 6353 NV_TRACE(dev, "Merging DCB entries %d and %d\n", 6354 i, j); 6355 ient->heads |= jent->heads; 6356 jent->type = 100; /* dummy value */ 6357 } 6358 } 6359 } 6360 6361 /* Compact entries merged into others out of dcb */ 6362 for (i = 0; i < dcb->entries; i++) { 6363 if (dcb->entry[i].type == 100) 6364 continue; 6365 6366 if (newentries != i) { 6367 dcb->entry[newentries] = dcb->entry[i]; 6368 dcb->entry[newentries].index = newentries; 6369 } 6370 newentries++; 6371 } 6372 6373 dcb->entries = newentries; 6374} 6375 6376static bool 6377apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf) 6378{ 6379 struct drm_nouveau_private *dev_priv = dev->dev_private; 6380 struct dcb_table *dcb = &dev_priv->vbios.dcb; 6381 6382 /* Dell Precision M6300 6383 * DCB entry 2: 02025312 00000010 6384 * DCB entry 3: 02026312 00000020 6385 * 6386 * Identical, except apparently a different connector on a 6387 * different SOR link. Not a clue how we're supposed to know 6388 * which one is in use if it even shares an i2c line... 6389 * 6390 * Ignore the connector on the second SOR link to prevent 6391 * nasty problems until this is sorted (assuming it's not a 6392 * VBIOS bug). 6393 */ 6394 if (nv_match_device(dev, 0x040d, 0x1028, 0x019b)) { 6395 if (*conn == 0x02026312 && *conf == 0x00000020) 6396 return false; 6397 } 6398 6399 /* GeForce3 Ti 200 6400 * 6401 * DCB reports an LVDS output that should be TMDS: 6402 * DCB entry 1: f2005014 ffffffff 6403 */ 6404 if (nv_match_device(dev, 0x0201, 0x1462, 0x8851)) { 6405 if (*conn == 0xf2005014 && *conf == 0xffffffff) { 6406 fabricate_dcb_output(dcb, OUTPUT_TMDS, 1, 1, 1); 6407 return false; 6408 } 6409 } 6410 6411 /* XFX GT-240X-YA 6412 * 6413 * So many things wrong here, replace the entire encoder table.. 6414 */ 6415 if (nv_match_device(dev, 0x0ca3, 0x1682, 0x3003)) { 6416 if (idx == 0) { 6417 *conn = 0x02001300; /* VGA, connector 1 */ 6418 *conf = 0x00000028; 6419 } else 6420 if (idx == 1) { 6421 *conn = 0x01010312; /* DVI, connector 0 */ 6422 *conf = 0x00020030; 6423 } else 6424 if (idx == 2) { 6425 *conn = 0x01010310; /* VGA, connector 0 */ 6426 *conf = 0x00000028; 6427 } else 6428 if (idx == 3) { 6429 *conn = 0x02022362; /* HDMI, connector 2 */ 6430 *conf = 0x00020010; 6431 } else { 6432 *conn = 0x0000000e; /* EOL */ 6433 *conf = 0x00000000; 6434 } 6435 } 6436 6437 /* Some other twisted XFX board (rhbz#694914) 6438 * 6439 * The DVI/VGA encoder combo that's supposed to represent the 6440 * DVI-I connector actually point at two different ones, and 6441 * the HDMI connector ends up paired with the VGA instead. 6442 * 6443 * Connector table is missing anything for VGA at all, pointing it 6444 * an invalid conntab entry 2 so we figure it out ourself. 6445 */ 6446 if (nv_match_device(dev, 0x0615, 0x1682, 0x2605)) { 6447 if (idx == 0) { 6448 *conn = 0x02002300; /* VGA, connector 2 */ 6449 *conf = 0x00000028; 6450 } else 6451 if (idx == 1) { 6452 *conn = 0x01010312; /* DVI, connector 0 */ 6453 *conf = 0x00020030; 6454 } else 6455 if (idx == 2) { 6456 *conn = 0x04020310; /* VGA, connector 0 */ 6457 *conf = 0x00000028; 6458 } else 6459 if (idx == 3) { 6460 *conn = 0x02021322; /* HDMI, connector 1 */ 6461 *conf = 0x00020010; 6462 } else { 6463 *conn = 0x0000000e; /* EOL */ 6464 *conf = 0x00000000; 6465 } 6466 } 6467 6468 return true; 6469} 6470 6471static void 6472fabricate_dcb_encoder_table(struct drm_device *dev, struct nvbios *bios) 6473{ 6474 struct dcb_table *dcb = &bios->dcb; 6475 int all_heads = (nv_two_heads(dev) ? 3 : 1); 6476 6477#ifdef __powerpc__ 6478 /* Apple iMac G4 NV17 */ 6479 if (of_machine_is_compatible("PowerMac4,5")) { 6480 fabricate_dcb_output(dcb, OUTPUT_TMDS, 0, all_heads, 1); 6481 fabricate_dcb_output(dcb, OUTPUT_ANALOG, 1, all_heads, 2); 6482 return; 6483 } 6484#endif 6485 6486 /* Make up some sane defaults */ 6487 fabricate_dcb_output(dcb, OUTPUT_ANALOG, LEGACY_I2C_CRT, 1, 1); 6488 6489 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0) 6490 fabricate_dcb_output(dcb, OUTPUT_TV, LEGACY_I2C_TV, 6491 all_heads, 0); 6492 6493 else if (bios->tmds.output0_script_ptr || 6494 bios->tmds.output1_script_ptr) 6495 fabricate_dcb_output(dcb, OUTPUT_TMDS, LEGACY_I2C_PANEL, 6496 all_heads, 1); 6497} 6498 6499static int 6500parse_dcb_table(struct drm_device *dev, struct nvbios *bios) 6501{ 6502 struct drm_nouveau_private *dev_priv = dev->dev_private; 6503 struct dcb_table *dcb = &bios->dcb; 6504 uint16_t dcbptr = 0, i2ctabptr = 0; 6505 uint8_t *dcbtable; 6506 uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES; 6507 bool configblock = true; 6508 int recordlength = 8, confofs = 4; 6509 int i; 6510 6511 /* get the offset from 0x36 */ 6512 if (dev_priv->card_type > NV_04) { 6513 dcbptr = ROM16(bios->data[0x36]); 6514 if (dcbptr == 0x0000) 6515 NV_WARN(dev, "No output data (DCB) found in BIOS\n"); 6516 } 6517 6518 /* this situation likely means a really old card, pre DCB */ 6519 if (dcbptr == 0x0) { 6520 fabricate_dcb_encoder_table(dev, bios); 6521 return 0; 6522 } 6523 6524 dcbtable = &bios->data[dcbptr]; 6525 6526 /* get DCB version */ 6527 dcb->version = dcbtable[0]; 6528 NV_TRACE(dev, "Found Display Configuration Block version %d.%d\n", 6529 dcb->version >> 4, dcb->version & 0xf); 6530 6531 if (dcb->version >= 0x20) { /* NV17+ */ 6532 uint32_t sig; 6533 6534 if (dcb->version >= 0x30) { /* NV40+ */ 6535 headerlen = dcbtable[1]; 6536 entries = dcbtable[2]; 6537 recordlength = dcbtable[3]; 6538 i2ctabptr = ROM16(dcbtable[4]); 6539 sig = ROM32(dcbtable[6]); 6540 dcb->gpio_table_ptr = ROM16(dcbtable[10]); 6541 dcb->connector_table_ptr = ROM16(dcbtable[20]); 6542 } else { 6543 i2ctabptr = ROM16(dcbtable[2]); 6544 sig = ROM32(dcbtable[4]); 6545 headerlen = 8; 6546 } 6547 6548 if (sig != 0x4edcbdcb) { 6549 NV_ERROR(dev, "Bad Display Configuration Block " 6550 "signature (%08X)\n", sig); 6551 return -EINVAL; 6552 } 6553 } else if (dcb->version >= 0x15) { /* some NV11 and NV20 */ 6554 char sig[8] = { 0 }; 6555 6556 strncpy(sig, (char *)&dcbtable[-7], 7); 6557 i2ctabptr = ROM16(dcbtable[2]); 6558 recordlength = 10; 6559 confofs = 6; 6560 6561 if (strcmp(sig, "DEV_REC")) { 6562 NV_ERROR(dev, "Bad Display Configuration Block " 6563 "signature (%s)\n", sig); 6564 return -EINVAL; 6565 } 6566 } else { 6567 /* 6568 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always 6569 * has the same single (crt) entry, even when tv-out present, so 6570 * the conclusion is this version cannot really be used. 6571 * v1.2 tables (some NV6/10, and NV15+) normally have the same 6572 * 5 entries, which are not specific to the card and so no use. 6573 * v1.2 does have an I2C table that read_dcb_i2c_table can 6574 * handle, but cards exist (nv11 in #14821) with a bad i2c table 6575 * pointer, so use the indices parsed in parse_bmp_structure. 6576 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful 6577 */ 6578 NV_TRACEWARN(dev, "No useful information in BIOS output table; " 6579 "adding all possible outputs\n"); 6580 fabricate_dcb_encoder_table(dev, bios); 6581 return 0; 6582 } 6583 6584 if (!i2ctabptr) 6585 NV_WARN(dev, "No pointer to DCB I2C port table\n"); 6586 else { 6587 dcb->i2c_table = &bios->data[i2ctabptr]; 6588 if (dcb->version >= 0x30) 6589 dcb->i2c_default_indices = dcb->i2c_table[4]; 6590 6591 /* 6592 * Parse the "management" I2C bus, used for hardware 6593 * monitoring and some external TMDS transmitters. 6594 */ 6595 if (dcb->version >= 0x22) { 6596 int idx = (dcb->version >= 0x40 ? 6597 dcb->i2c_default_indices & 0xf : 6598 2); 6599 6600 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table, 6601 idx, &dcb->i2c[idx]); 6602 } 6603 } 6604 6605 if (entries > DCB_MAX_NUM_ENTRIES) 6606 entries = DCB_MAX_NUM_ENTRIES; 6607 6608 for (i = 0; i < entries; i++) { 6609 uint32_t connection, config = 0; 6610 6611 connection = ROM32(dcbtable[headerlen + recordlength * i]); 6612 if (configblock) 6613 config = ROM32(dcbtable[headerlen + confofs + recordlength * i]); 6614 6615 /* seen on an NV11 with DCB v1.5 */ 6616 if (connection == 0x00000000) 6617 break; 6618 6619 /* seen on an NV17 with DCB v2.0 */ 6620 if (connection == 0xffffffff) 6621 break; 6622 6623 if ((connection & 0x0000000f) == 0x0000000f) 6624 continue; 6625 6626 if (!apply_dcb_encoder_quirks(dev, i, &connection, &config)) 6627 continue; 6628 6629 NV_TRACEWARN(dev, "Raw DCB entry %d: %08x %08x\n", 6630 dcb->entries, connection, config); 6631 6632 if (!parse_dcb_entry(dev, dcb, connection, config)) 6633 break; 6634 } 6635 6636 /* 6637 * apart for v2.1+ not being known for requiring merging, this 6638 * guarantees dcbent->index is the index of the entry in the rom image 6639 */ 6640 if (dcb->version < 0x21) 6641 merge_like_dcb_entries(dev, dcb); 6642 6643 if (!dcb->entries) 6644 return -ENXIO; 6645 6646 parse_dcb_gpio_table(bios); 6647 parse_dcb_connector_table(bios); 6648 return 0; 6649} 6650 6651static void 6652fixup_legacy_connector(struct nvbios *bios) 6653{ 6654 struct dcb_table *dcb = &bios->dcb; 6655 int i, i2c, i2c_conn[DCB_MAX_NUM_I2C_ENTRIES] = { }; 6656 6657 /* 6658 * DCB 3.0 also has the table in most cases, but there are some cards 6659 * where the table is filled with stub entries, and the DCB entriy 6660 * indices are all 0. We don't need the connector indices on pre-G80 6661 * chips (yet?) so limit the use to DCB 4.0 and above. 6662 */ 6663 if (dcb->version >= 0x40) 6664 return; 6665 6666 dcb->connector.entries = 0; 6667 6668 /* 6669 * No known connector info before v3.0, so make it up. the rule here 6670 * is: anything on the same i2c bus is considered to be on the same 6671 * connector. any output without an associated i2c bus is assigned 6672 * its own unique connector index. 6673 */ 6674 for (i = 0; i < dcb->entries; i++) { 6675 /* 6676 * Ignore the I2C index for on-chip TV-out, as there 6677 * are cards with bogus values (nv31m in bug 23212), 6678 * and it's otherwise useless. 6679 */ 6680 if (dcb->entry[i].type == OUTPUT_TV && 6681 dcb->entry[i].location == DCB_LOC_ON_CHIP) 6682 dcb->entry[i].i2c_index = 0xf; 6683 i2c = dcb->entry[i].i2c_index; 6684 6685 if (i2c_conn[i2c]) { 6686 dcb->entry[i].connector = i2c_conn[i2c] - 1; 6687 continue; 6688 } 6689 6690 dcb->entry[i].connector = dcb->connector.entries++; 6691 if (i2c != 0xf) 6692 i2c_conn[i2c] = dcb->connector.entries; 6693 } 6694 6695 /* Fake the connector table as well as just connector indices */ 6696 for (i = 0; i < dcb->connector.entries; i++) { 6697 dcb->connector.entry[i].index = i; 6698 dcb->connector.entry[i].type = divine_connector_type(bios, i); 6699 dcb->connector.entry[i].gpio_tag = 0xff; 6700 } 6701} 6702 6703static void 6704fixup_legacy_i2c(struct nvbios *bios) 6705{ 6706 struct dcb_table *dcb = &bios->dcb; 6707 int i; 6708 6709 for (i = 0; i < dcb->entries; i++) { 6710 if (dcb->entry[i].i2c_index == LEGACY_I2C_CRT) 6711 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.crt; 6712 if (dcb->entry[i].i2c_index == LEGACY_I2C_PANEL) 6713 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.panel; 6714 if (dcb->entry[i].i2c_index == LEGACY_I2C_TV) 6715 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.tv; 6716 } 6717} 6718 6719static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry) 6720{ 6721 /* 6722 * The header following the "HWSQ" signature has the number of entries, 6723 * and the entry size 6724 * 6725 * An entry consists of a dword to write to the sequencer control reg 6726 * (0x00001304), followed by the ucode bytes, written sequentially, 6727 * starting at reg 0x00001400 6728 */ 6729 6730 uint8_t bytes_to_write; 6731 uint16_t hwsq_entry_offset; 6732 int i; 6733 6734 if (bios->data[hwsq_offset] <= entry) { 6735 NV_ERROR(dev, "Too few entries in HW sequencer table for " 6736 "requested entry\n"); 6737 return -ENOENT; 6738 } 6739 6740 bytes_to_write = bios->data[hwsq_offset + 1]; 6741 6742 if (bytes_to_write != 36) { 6743 NV_ERROR(dev, "Unknown HW sequencer entry size\n"); 6744 return -EINVAL; 6745 } 6746 6747 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n"); 6748 6749 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write; 6750 6751 /* set sequencer control */ 6752 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset])); 6753 bytes_to_write -= 4; 6754 6755 /* write ucode */ 6756 for (i = 0; i < bytes_to_write; i += 4) 6757 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4])); 6758 6759 /* twiddle NV_PBUS_DEBUG_4 */ 6760 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18); 6761 6762 return 0; 6763} 6764 6765static int load_nv17_hw_sequencer_ucode(struct drm_device *dev, 6766 struct nvbios *bios) 6767{ 6768 /* 6769 * BMP based cards, from NV17, need a microcode loading to correctly 6770 * control the GPIO etc for LVDS panels 6771 * 6772 * BIT based cards seem to do this directly in the init scripts 6773 * 6774 * The microcode entries are found by the "HWSQ" signature. 6775 */ 6776 6777 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' }; 6778 const int sz = sizeof(hwsq_signature); 6779 int hwsq_offset; 6780 6781 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz); 6782 if (!hwsq_offset) 6783 return 0; 6784 6785 /* always use entry 0? */ 6786 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0); 6787} 6788 6789uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev) 6790{ 6791 struct drm_nouveau_private *dev_priv = dev->dev_private; 6792 struct nvbios *bios = &dev_priv->vbios; 6793 const uint8_t edid_sig[] = { 6794 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 }; 6795 uint16_t offset = 0; 6796 uint16_t newoffset; 6797 int searchlen = NV_PROM_SIZE; 6798 6799 if (bios->fp.edid) 6800 return bios->fp.edid; 6801 6802 while (searchlen) { 6803 newoffset = findstr(&bios->data[offset], searchlen, 6804 edid_sig, 8); 6805 if (!newoffset) 6806 return NULL; 6807 offset += newoffset; 6808 if (!nv_cksum(&bios->data[offset], EDID1_LEN)) 6809 break; 6810 6811 searchlen -= offset; 6812 offset++; 6813 } 6814 6815 NV_TRACE(dev, "Found EDID in BIOS\n"); 6816 6817 return bios->fp.edid = &bios->data[offset]; 6818} 6819 6820void 6821nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table, 6822 struct dcb_entry *dcbent, int crtc) 6823{ 6824 struct drm_nouveau_private *dev_priv = dev->dev_private; 6825 struct nvbios *bios = &dev_priv->vbios; 6826 struct init_exec iexec = { true, false }; 6827 6828 spin_lock_bh(&bios->lock); 6829 bios->display.output = dcbent; 6830 bios->display.crtc = crtc; 6831 parse_init_table(bios, table, &iexec); 6832 bios->display.output = NULL; 6833 spin_unlock_bh(&bios->lock); 6834} 6835 6836static bool NVInitVBIOS(struct drm_device *dev) 6837{ 6838 struct drm_nouveau_private *dev_priv = dev->dev_private; 6839 struct nvbios *bios = &dev_priv->vbios; 6840 6841 memset(bios, 0, sizeof(struct nvbios)); 6842 spin_lock_init(&bios->lock); 6843 bios->dev = dev; 6844 6845 if (!NVShadowVBIOS(dev, bios->data)) 6846 return false; 6847 6848 bios->length = NV_PROM_SIZE; 6849 return true; 6850} 6851 6852static int nouveau_parse_vbios_struct(struct drm_device *dev) 6853{ 6854 struct drm_nouveau_private *dev_priv = dev->dev_private; 6855 struct nvbios *bios = &dev_priv->vbios; 6856 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' }; 6857 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 }; 6858 int offset; 6859 6860 offset = findstr(bios->data, bios->length, 6861 bit_signature, sizeof(bit_signature)); 6862 if (offset) { 6863 NV_TRACE(dev, "BIT BIOS found\n"); 6864 bios->type = NVBIOS_BIT; 6865 bios->offset = offset; 6866 return parse_bit_structure(bios, offset + 6); 6867 } 6868 6869 offset = findstr(bios->data, bios->length, 6870 bmp_signature, sizeof(bmp_signature)); 6871 if (offset) { 6872 NV_TRACE(dev, "BMP BIOS found\n"); 6873 bios->type = NVBIOS_BMP; 6874 bios->offset = offset; 6875 return parse_bmp_structure(dev, bios, offset); 6876 } 6877 6878 NV_ERROR(dev, "No known BIOS signature found\n"); 6879 return -ENODEV; 6880} 6881 6882int 6883nouveau_run_vbios_init(struct drm_device *dev) 6884{ 6885 struct drm_nouveau_private *dev_priv = dev->dev_private; 6886 struct nvbios *bios = &dev_priv->vbios; 6887 int i, ret = 0; 6888 6889 /* Reset the BIOS head to 0. */ 6890 bios->state.crtchead = 0; 6891 6892 if (bios->major_version < 5) /* BMP only */ 6893 load_nv17_hw_sequencer_ucode(dev, bios); 6894 6895 if (bios->execute) { 6896 bios->fp.last_script_invoc = 0; 6897 bios->fp.lvds_init_run = false; 6898 } 6899 6900 parse_init_tables(bios); 6901 6902 /* 6903 * Runs some additional script seen on G8x VBIOSen. The VBIOS' 6904 * parser will run this right after the init tables, the binary 6905 * driver appears to run it at some point later. 6906 */ 6907 if (bios->some_script_ptr) { 6908 struct init_exec iexec = {true, false}; 6909 6910 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n", 6911 bios->some_script_ptr); 6912 parse_init_table(bios, bios->some_script_ptr, &iexec); 6913 } 6914 6915 if (dev_priv->card_type >= NV_50) { 6916 for (i = 0; i < bios->dcb.entries; i++) { 6917 nouveau_bios_run_display_table(dev, 0, 0, 6918 &bios->dcb.entry[i], -1); 6919 } 6920 } 6921 6922 return ret; 6923} 6924 6925static void 6926nouveau_bios_i2c_devices_takedown(struct drm_device *dev) 6927{ 6928 struct drm_nouveau_private *dev_priv = dev->dev_private; 6929 struct nvbios *bios = &dev_priv->vbios; 6930 struct dcb_i2c_entry *entry; 6931 int i; 6932 6933 entry = &bios->dcb.i2c[0]; 6934 for (i = 0; i < DCB_MAX_NUM_I2C_ENTRIES; i++, entry++) 6935 nouveau_i2c_fini(dev, entry); 6936} 6937 6938static bool 6939nouveau_bios_posted(struct drm_device *dev) 6940{ 6941 struct drm_nouveau_private *dev_priv = dev->dev_private; 6942 unsigned htotal; 6943 6944 if (dev_priv->card_type >= NV_50) { 6945 if (NVReadVgaCrtc(dev, 0, 0x00) == 0 && 6946 NVReadVgaCrtc(dev, 0, 0x1a) == 0) 6947 return false; 6948 return true; 6949 } 6950 6951 htotal = NVReadVgaCrtc(dev, 0, 0x06); 6952 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8; 6953 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4; 6954 htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10; 6955 htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11; 6956 6957 return (htotal != 0); 6958} 6959 6960int 6961nouveau_bios_init(struct drm_device *dev) 6962{ 6963 struct drm_nouveau_private *dev_priv = dev->dev_private; 6964 struct nvbios *bios = &dev_priv->vbios; 6965 int ret; 6966 6967 if (!NVInitVBIOS(dev)) 6968 return -ENODEV; 6969 6970 ret = nouveau_parse_vbios_struct(dev); 6971 if (ret) 6972 return ret; 6973 6974 ret = parse_dcb_table(dev, bios); 6975 if (ret) 6976 return ret; 6977 6978 fixup_legacy_i2c(bios); 6979 fixup_legacy_connector(bios); 6980 6981 if (!bios->major_version) /* we don't run version 0 bios */ 6982 return 0; 6983 6984 /* init script execution disabled */ 6985 bios->execute = false; 6986 6987 /* ... unless card isn't POSTed already */ 6988 if (!nouveau_bios_posted(dev)) { 6989 NV_INFO(dev, "Adaptor not initialised, " 6990 "running VBIOS init tables.\n"); 6991 bios->execute = true; 6992 } 6993 if (nouveau_force_post) 6994 bios->execute = true; 6995 6996 ret = nouveau_run_vbios_init(dev); 6997 if (ret) 6998 return ret; 6999 7000 /* feature_byte on BMP is poor, but init always sets CR4B */ 7001 if (bios->major_version < 5) 7002 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40; 7003 7004 /* all BIT systems need p_f_m_t for digital_min_front_porch */ 7005 if (bios->is_mobile || bios->major_version >= 5) 7006 ret = parse_fp_mode_table(dev, bios); 7007 7008 /* allow subsequent scripts to execute */ 7009 bios->execute = true; 7010 7011 return 0; 7012} 7013 7014void 7015nouveau_bios_takedown(struct drm_device *dev) 7016{ 7017 nouveau_bios_i2c_devices_takedown(dev); 7018} 7019