nouveau_bios.c revision ee2e013131dcf6427334663662dbe760ccdba735
1/* 2 * Copyright 2005-2006 Erik Waling 3 * Copyright 2006 Stephane Marchesin 4 * Copyright 2007-2009 Stuart Bennett 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 25#include "drmP.h" 26#define NV_DEBUG_NOTRACE 27#include "nouveau_drv.h" 28#include "nouveau_hw.h" 29#include "nouveau_encoder.h" 30 31#include <linux/io-mapping.h> 32 33/* these defines are made up */ 34#define NV_CIO_CRE_44_HEADA 0x0 35#define NV_CIO_CRE_44_HEADB 0x3 36#define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */ 37#define LEGACY_I2C_CRT 0x80 38#define LEGACY_I2C_PANEL 0x81 39#define LEGACY_I2C_TV 0x82 40 41#define EDID1_LEN 128 42 43#define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg) 44#define LOG_OLD_VALUE(x) 45 46#define ROM16(x) le16_to_cpu(*(uint16_t *)&(x)) 47#define ROM32(x) le32_to_cpu(*(uint32_t *)&(x)) 48 49struct init_exec { 50 bool execute; 51 bool repeat; 52}; 53 54static bool nv_cksum(const uint8_t *data, unsigned int length) 55{ 56 /* 57 * There's a few checksums in the BIOS, so here's a generic checking 58 * function. 59 */ 60 int i; 61 uint8_t sum = 0; 62 63 for (i = 0; i < length; i++) 64 sum += data[i]; 65 66 if (sum) 67 return true; 68 69 return false; 70} 71 72static int 73score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable) 74{ 75 if (!(data[0] == 0x55 && data[1] == 0xAA)) { 76 NV_TRACEWARN(dev, "... BIOS signature not found\n"); 77 return 0; 78 } 79 80 if (nv_cksum(data, data[2] * 512)) { 81 NV_TRACEWARN(dev, "... BIOS checksum invalid\n"); 82 /* if a ro image is somewhat bad, it's probably all rubbish */ 83 return writeable ? 2 : 1; 84 } else 85 NV_TRACE(dev, "... appears to be valid\n"); 86 87 return 3; 88} 89 90static void load_vbios_prom(struct drm_device *dev, uint8_t *data) 91{ 92 struct drm_nouveau_private *dev_priv = dev->dev_private; 93 uint32_t pci_nv_20, save_pci_nv_20; 94 int pcir_ptr; 95 int i; 96 97 if (dev_priv->card_type >= NV_50) 98 pci_nv_20 = 0x88050; 99 else 100 pci_nv_20 = NV_PBUS_PCI_NV_20; 101 102 /* enable ROM access */ 103 save_pci_nv_20 = nvReadMC(dev, pci_nv_20); 104 nvWriteMC(dev, pci_nv_20, 105 save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED); 106 107 /* bail if no rom signature */ 108 if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 || 109 nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa) 110 goto out; 111 112 /* additional check (see note below) - read PCI record header */ 113 pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) | 114 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8; 115 if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' || 116 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' || 117 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' || 118 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R') 119 goto out; 120 121 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a 122 * a good read may be obtained by waiting or re-reading (cargocult: 5x) 123 * each byte. we'll hope pramin has something usable instead 124 */ 125 for (i = 0; i < NV_PROM_SIZE; i++) 126 data[i] = nv_rd08(dev, NV_PROM_OFFSET + i); 127 128out: 129 /* disable ROM access */ 130 nvWriteMC(dev, pci_nv_20, 131 save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED); 132} 133 134static void load_vbios_pramin(struct drm_device *dev, uint8_t *data) 135{ 136 struct drm_nouveau_private *dev_priv = dev->dev_private; 137 uint32_t old_bar0_pramin = 0; 138 int i; 139 140 if (dev_priv->card_type >= NV_50) { 141 uint32_t vbios_vram = (nv_rd32(dev, 0x619f04) & ~0xff) << 8; 142 143 if (!vbios_vram) 144 vbios_vram = (nv_rd32(dev, 0x1700) << 16) + 0xf0000; 145 146 old_bar0_pramin = nv_rd32(dev, 0x1700); 147 nv_wr32(dev, 0x1700, vbios_vram >> 16); 148 } 149 150 /* bail if no rom signature */ 151 if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 || 152 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa) 153 goto out; 154 155 for (i = 0; i < NV_PROM_SIZE; i++) 156 data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i); 157 158out: 159 if (dev_priv->card_type >= NV_50) 160 nv_wr32(dev, 0x1700, old_bar0_pramin); 161} 162 163static void load_vbios_pci(struct drm_device *dev, uint8_t *data) 164{ 165 void __iomem *rom = NULL; 166 size_t rom_len; 167 int ret; 168 169 ret = pci_enable_rom(dev->pdev); 170 if (ret) 171 return; 172 173 rom = pci_map_rom(dev->pdev, &rom_len); 174 if (!rom) 175 goto out; 176 memcpy_fromio(data, rom, rom_len); 177 pci_unmap_rom(dev->pdev, rom); 178 179out: 180 pci_disable_rom(dev->pdev); 181} 182 183static void load_vbios_acpi(struct drm_device *dev, uint8_t *data) 184{ 185 int i; 186 int ret; 187 int size = 64 * 1024; 188 189 if (!nouveau_acpi_rom_supported(dev->pdev)) 190 return; 191 192 for (i = 0; i < (size / ROM_BIOS_PAGE); i++) { 193 ret = nouveau_acpi_get_bios_chunk(data, 194 (i * ROM_BIOS_PAGE), 195 ROM_BIOS_PAGE); 196 if (ret <= 0) 197 break; 198 } 199 return; 200} 201 202struct methods { 203 const char desc[8]; 204 void (*loadbios)(struct drm_device *, uint8_t *); 205 const bool rw; 206}; 207 208static struct methods shadow_methods[] = { 209 { "PRAMIN", load_vbios_pramin, true }, 210 { "PROM", load_vbios_prom, false }, 211 { "PCIROM", load_vbios_pci, true }, 212 { "ACPI", load_vbios_acpi, true }, 213}; 214#define NUM_SHADOW_METHODS ARRAY_SIZE(shadow_methods) 215 216static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data) 217{ 218 struct methods *methods = shadow_methods; 219 int testscore = 3; 220 int scores[NUM_SHADOW_METHODS], i; 221 222 if (nouveau_vbios) { 223 for (i = 0; i < NUM_SHADOW_METHODS; i++) 224 if (!strcasecmp(nouveau_vbios, methods[i].desc)) 225 break; 226 227 if (i < NUM_SHADOW_METHODS) { 228 NV_INFO(dev, "Attempting to use BIOS image from %s\n", 229 methods[i].desc); 230 231 methods[i].loadbios(dev, data); 232 if (score_vbios(dev, data, methods[i].rw)) 233 return true; 234 } 235 236 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios); 237 } 238 239 for (i = 0; i < NUM_SHADOW_METHODS; i++) { 240 NV_TRACE(dev, "Attempting to load BIOS image from %s\n", 241 methods[i].desc); 242 data[0] = data[1] = 0; /* avoid reuse of previous image */ 243 methods[i].loadbios(dev, data); 244 scores[i] = score_vbios(dev, data, methods[i].rw); 245 if (scores[i] == testscore) 246 return true; 247 } 248 249 while (--testscore > 0) { 250 for (i = 0; i < NUM_SHADOW_METHODS; i++) { 251 if (scores[i] == testscore) { 252 NV_TRACE(dev, "Using BIOS image from %s\n", 253 methods[i].desc); 254 methods[i].loadbios(dev, data); 255 return true; 256 } 257 } 258 } 259 260 NV_ERROR(dev, "No valid BIOS image found\n"); 261 return false; 262} 263 264struct init_tbl_entry { 265 char *name; 266 uint8_t id; 267 /* Return: 268 * > 0: success, length of opcode 269 * 0: success, but abort further parsing of table (INIT_DONE etc) 270 * < 0: failure, table parsing will be aborted 271 */ 272 int (*handler)(struct nvbios *, uint16_t, struct init_exec *); 273}; 274 275struct bit_entry { 276 uint8_t id[2]; 277 uint16_t length; 278 uint16_t offset; 279}; 280 281static int parse_init_table(struct nvbios *, unsigned int, struct init_exec *); 282 283#define MACRO_INDEX_SIZE 2 284#define MACRO_SIZE 8 285#define CONDITION_SIZE 12 286#define IO_FLAG_CONDITION_SIZE 9 287#define IO_CONDITION_SIZE 5 288#define MEM_INIT_SIZE 66 289 290static void still_alive(void) 291{ 292#if 0 293 sync(); 294 msleep(2); 295#endif 296} 297 298static uint32_t 299munge_reg(struct nvbios *bios, uint32_t reg) 300{ 301 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 302 struct dcb_entry *dcbent = bios->display.output; 303 304 if (dev_priv->card_type < NV_50) 305 return reg; 306 307 if (reg & 0x40000000) { 308 BUG_ON(!dcbent); 309 310 reg += (ffs(dcbent->or) - 1) * 0x800; 311 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1)) 312 reg += 0x00000080; 313 } 314 315 reg &= ~0x60000000; 316 return reg; 317} 318 319static int 320valid_reg(struct nvbios *bios, uint32_t reg) 321{ 322 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 323 struct drm_device *dev = bios->dev; 324 325 /* C51 has misaligned regs on purpose. Marvellous */ 326 if (reg & 0x2 || 327 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51)) 328 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg); 329 330 /* warn on C51 regs that haven't been verified accessible in tracing */ 331 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 && 332 reg != 0x130d && reg != 0x1311 && reg != 0x60081d) 333 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n", 334 reg); 335 336 if (reg >= (8*1024*1024)) { 337 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg); 338 return 0; 339 } 340 341 return 1; 342} 343 344static bool 345valid_idx_port(struct nvbios *bios, uint16_t port) 346{ 347 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 348 struct drm_device *dev = bios->dev; 349 350 /* 351 * If adding more ports here, the read/write functions below will need 352 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is 353 * used for the port in question 354 */ 355 if (dev_priv->card_type < NV_50) { 356 if (port == NV_CIO_CRX__COLOR) 357 return true; 358 if (port == NV_VIO_SRX) 359 return true; 360 } else { 361 if (port == NV_CIO_CRX__COLOR) 362 return true; 363 } 364 365 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n", 366 port); 367 368 return false; 369} 370 371static bool 372valid_port(struct nvbios *bios, uint16_t port) 373{ 374 struct drm_device *dev = bios->dev; 375 376 /* 377 * If adding more ports here, the read/write functions below will need 378 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is 379 * used for the port in question 380 */ 381 if (port == NV_VIO_VSE2) 382 return true; 383 384 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port); 385 386 return false; 387} 388 389static uint32_t 390bios_rd32(struct nvbios *bios, uint32_t reg) 391{ 392 uint32_t data; 393 394 reg = munge_reg(bios, reg); 395 if (!valid_reg(bios, reg)) 396 return 0; 397 398 /* 399 * C51 sometimes uses regs with bit0 set in the address. For these 400 * cases there should exist a translation in a BIOS table to an IO 401 * port address which the BIOS uses for accessing the reg 402 * 403 * These only seem to appear for the power control regs to a flat panel, 404 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs 405 * for 0x1308 and 0x1310 are used - hence the mask below. An S3 406 * suspend-resume mmio trace from a C51 will be required to see if this 407 * is true for the power microcode in 0x14.., or whether the direct IO 408 * port access method is needed 409 */ 410 if (reg & 0x1) 411 reg &= ~0x1; 412 413 data = nv_rd32(bios->dev, reg); 414 415 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data); 416 417 return data; 418} 419 420static void 421bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data) 422{ 423 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 424 425 reg = munge_reg(bios, reg); 426 if (!valid_reg(bios, reg)) 427 return; 428 429 /* see note in bios_rd32 */ 430 if (reg & 0x1) 431 reg &= 0xfffffffe; 432 433 LOG_OLD_VALUE(bios_rd32(bios, reg)); 434 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data); 435 436 if (dev_priv->vbios.execute) { 437 still_alive(); 438 nv_wr32(bios->dev, reg, data); 439 } 440} 441 442static uint8_t 443bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index) 444{ 445 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 446 struct drm_device *dev = bios->dev; 447 uint8_t data; 448 449 if (!valid_idx_port(bios, port)) 450 return 0; 451 452 if (dev_priv->card_type < NV_50) { 453 if (port == NV_VIO_SRX) 454 data = NVReadVgaSeq(dev, bios->state.crtchead, index); 455 else /* assume NV_CIO_CRX__COLOR */ 456 data = NVReadVgaCrtc(dev, bios->state.crtchead, index); 457 } else { 458 uint32_t data32; 459 460 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3)); 461 data = (data32 >> ((index & 3) << 3)) & 0xff; 462 } 463 464 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, " 465 "Head: 0x%02X, Data: 0x%02X\n", 466 port, index, bios->state.crtchead, data); 467 return data; 468} 469 470static void 471bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data) 472{ 473 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 474 struct drm_device *dev = bios->dev; 475 476 if (!valid_idx_port(bios, port)) 477 return; 478 479 /* 480 * The current head is maintained in the nvbios member state.crtchead. 481 * We trap changes to CR44 and update the head variable and hence the 482 * register set written. 483 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance 484 * of the write, and to head1 after the write 485 */ 486 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 && 487 data != NV_CIO_CRE_44_HEADB) 488 bios->state.crtchead = 0; 489 490 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index)); 491 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, " 492 "Head: 0x%02X, Data: 0x%02X\n", 493 port, index, bios->state.crtchead, data); 494 495 if (bios->execute && dev_priv->card_type < NV_50) { 496 still_alive(); 497 if (port == NV_VIO_SRX) 498 NVWriteVgaSeq(dev, bios->state.crtchead, index, data); 499 else /* assume NV_CIO_CRX__COLOR */ 500 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data); 501 } else 502 if (bios->execute) { 503 uint32_t data32, shift = (index & 3) << 3; 504 505 still_alive(); 506 507 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3)); 508 data32 &= ~(0xff << shift); 509 data32 |= (data << shift); 510 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32); 511 } 512 513 if (port == NV_CIO_CRX__COLOR && 514 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB) 515 bios->state.crtchead = 1; 516} 517 518static uint8_t 519bios_port_rd(struct nvbios *bios, uint16_t port) 520{ 521 uint8_t data, head = bios->state.crtchead; 522 523 if (!valid_port(bios, port)) 524 return 0; 525 526 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port); 527 528 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n", 529 port, head, data); 530 531 return data; 532} 533 534static void 535bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data) 536{ 537 int head = bios->state.crtchead; 538 539 if (!valid_port(bios, port)) 540 return; 541 542 LOG_OLD_VALUE(bios_port_rd(bios, port)); 543 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n", 544 port, head, data); 545 546 if (!bios->execute) 547 return; 548 549 still_alive(); 550 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data); 551} 552 553static bool 554io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 555{ 556 /* 557 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte 558 * for the CRTC index; 1 byte for the mask to apply to the value 559 * retrieved from the CRTC; 1 byte for the shift right to apply to the 560 * masked CRTC value; 2 bytes for the offset to the flag array, to 561 * which the shifted value is added; 1 byte for the mask applied to the 562 * value read from the flag array; and 1 byte for the value to compare 563 * against the masked byte from the flag table. 564 */ 565 566 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE; 567 uint16_t crtcport = ROM16(bios->data[condptr]); 568 uint8_t crtcindex = bios->data[condptr + 2]; 569 uint8_t mask = bios->data[condptr + 3]; 570 uint8_t shift = bios->data[condptr + 4]; 571 uint16_t flagarray = ROM16(bios->data[condptr + 5]); 572 uint8_t flagarraymask = bios->data[condptr + 7]; 573 uint8_t cmpval = bios->data[condptr + 8]; 574 uint8_t data; 575 576 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 577 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, " 578 "Cmpval: 0x%02X\n", 579 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval); 580 581 data = bios_idxprt_rd(bios, crtcport, crtcindex); 582 583 data = bios->data[flagarray + ((data & mask) >> shift)]; 584 data &= flagarraymask; 585 586 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n", 587 offset, data, cmpval); 588 589 return (data == cmpval); 590} 591 592static bool 593bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 594{ 595 /* 596 * The condition table entry has 4 bytes for the address of the 597 * register to check, 4 bytes for a mask to apply to the register and 598 * 4 for a test comparison value 599 */ 600 601 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE; 602 uint32_t reg = ROM32(bios->data[condptr]); 603 uint32_t mask = ROM32(bios->data[condptr + 4]); 604 uint32_t cmpval = ROM32(bios->data[condptr + 8]); 605 uint32_t data; 606 607 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n", 608 offset, cond, reg, mask); 609 610 data = bios_rd32(bios, reg) & mask; 611 612 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n", 613 offset, data, cmpval); 614 615 return (data == cmpval); 616} 617 618static bool 619io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 620{ 621 /* 622 * The IO condition entry has 2 bytes for the IO port address; 1 byte 623 * for the index to write to io_port; 1 byte for the mask to apply to 624 * the byte read from io_port+1; and 1 byte for the value to compare 625 * against the masked byte. 626 */ 627 628 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE; 629 uint16_t io_port = ROM16(bios->data[condptr]); 630 uint8_t port_index = bios->data[condptr + 2]; 631 uint8_t mask = bios->data[condptr + 3]; 632 uint8_t cmpval = bios->data[condptr + 4]; 633 634 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask; 635 636 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n", 637 offset, data, cmpval); 638 639 return (data == cmpval); 640} 641 642static int 643nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk) 644{ 645 struct drm_nouveau_private *dev_priv = dev->dev_private; 646 uint32_t reg0 = nv_rd32(dev, reg + 0); 647 uint32_t reg1 = nv_rd32(dev, reg + 4); 648 struct nouveau_pll_vals pll; 649 struct pll_lims pll_limits; 650 int ret; 651 652 ret = get_pll_limits(dev, reg, &pll_limits); 653 if (ret) 654 return ret; 655 656 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll); 657 if (!clk) 658 return -ERANGE; 659 660 reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16); 661 reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1; 662 663 if (dev_priv->vbios.execute) { 664 still_alive(); 665 nv_wr32(dev, reg + 4, reg1); 666 nv_wr32(dev, reg + 0, reg0); 667 } 668 669 return 0; 670} 671 672static int 673setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk) 674{ 675 struct drm_device *dev = bios->dev; 676 struct drm_nouveau_private *dev_priv = dev->dev_private; 677 /* clk in kHz */ 678 struct pll_lims pll_lim; 679 struct nouveau_pll_vals pllvals; 680 int ret; 681 682 if (dev_priv->card_type >= NV_50) 683 return nv50_pll_set(dev, reg, clk); 684 685 /* high regs (such as in the mac g5 table) are not -= 4 */ 686 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim); 687 if (ret) 688 return ret; 689 690 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals); 691 if (!clk) 692 return -ERANGE; 693 694 if (bios->execute) { 695 still_alive(); 696 nouveau_hw_setpll(dev, reg, &pllvals); 697 } 698 699 return 0; 700} 701 702static int dcb_entry_idx_from_crtchead(struct drm_device *dev) 703{ 704 struct drm_nouveau_private *dev_priv = dev->dev_private; 705 struct nvbios *bios = &dev_priv->vbios; 706 707 /* 708 * For the results of this function to be correct, CR44 must have been 709 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0, 710 * and the DCB table parsed, before the script calling the function is 711 * run. run_digital_op_script is example of how to do such setup 712 */ 713 714 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0); 715 716 if (dcb_entry > bios->dcb.entries) { 717 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently " 718 "(%02X)\n", dcb_entry); 719 dcb_entry = 0x7f; /* unused / invalid marker */ 720 } 721 722 return dcb_entry; 723} 724 725static int 726read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, int index, struct dcb_i2c_entry *i2c) 727{ 728 uint8_t dcb_i2c_ver = dcb_version, headerlen = 0, entry_len = 4; 729 int i2c_entries = DCB_MAX_NUM_I2C_ENTRIES; 730 int recordoffset = 0, rdofs = 1, wrofs = 0; 731 uint8_t port_type = 0; 732 733 if (!i2ctable) 734 return -EINVAL; 735 736 if (dcb_version >= 0x30) { 737 if (i2ctable[0] != dcb_version) /* necessary? */ 738 NV_WARN(dev, 739 "DCB I2C table version mismatch (%02X vs %02X)\n", 740 i2ctable[0], dcb_version); 741 dcb_i2c_ver = i2ctable[0]; 742 headerlen = i2ctable[1]; 743 if (i2ctable[2] <= DCB_MAX_NUM_I2C_ENTRIES) 744 i2c_entries = i2ctable[2]; 745 else 746 NV_WARN(dev, 747 "DCB I2C table has more entries than indexable " 748 "(%d entries, max %d)\n", i2ctable[2], 749 DCB_MAX_NUM_I2C_ENTRIES); 750 entry_len = i2ctable[3]; 751 /* [4] is i2c_default_indices, read in parse_dcb_table() */ 752 } 753 /* 754 * It's your own fault if you call this function on a DCB 1.1 BIOS -- 755 * the test below is for DCB 1.2 756 */ 757 if (dcb_version < 0x14) { 758 recordoffset = 2; 759 rdofs = 0; 760 wrofs = 1; 761 } 762 763 if (index == 0xf) 764 return 0; 765 if (index >= i2c_entries) { 766 NV_ERROR(dev, "DCB I2C index too big (%d >= %d)\n", 767 index, i2ctable[2]); 768 return -ENOENT; 769 } 770 if (i2ctable[headerlen + entry_len * index + 3] == 0xff) { 771 NV_ERROR(dev, "DCB I2C entry invalid\n"); 772 return -EINVAL; 773 } 774 775 if (dcb_i2c_ver >= 0x30) { 776 port_type = i2ctable[headerlen + recordoffset + 3 + entry_len * index]; 777 778 /* 779 * Fixup for chips using same address offset for read and 780 * write. 781 */ 782 if (port_type == 4) /* seen on C51 */ 783 rdofs = wrofs = 1; 784 if (port_type >= 5) /* G80+ */ 785 rdofs = wrofs = 0; 786 } 787 788 if (dcb_i2c_ver >= 0x40) { 789 if (port_type != 5 && port_type != 6) 790 NV_WARN(dev, "DCB I2C table has port type %d\n", port_type); 791 792 i2c->entry = ROM32(i2ctable[headerlen + recordoffset + entry_len * index]); 793 } 794 795 i2c->port_type = port_type; 796 i2c->read = i2ctable[headerlen + recordoffset + rdofs + entry_len * index]; 797 i2c->write = i2ctable[headerlen + recordoffset + wrofs + entry_len * index]; 798 799 return 0; 800} 801 802static struct nouveau_i2c_chan * 803init_i2c_device_find(struct drm_device *dev, int i2c_index) 804{ 805 struct drm_nouveau_private *dev_priv = dev->dev_private; 806 struct dcb_table *dcb = &dev_priv->vbios.dcb; 807 808 if (i2c_index == 0xff) { 809 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */ 810 int idx = dcb_entry_idx_from_crtchead(dev), shift = 0; 811 int default_indices = dcb->i2c_default_indices; 812 813 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default) 814 shift = 4; 815 816 i2c_index = (default_indices >> shift) & 0xf; 817 } 818 if (i2c_index == 0x80) /* g80+ */ 819 i2c_index = dcb->i2c_default_indices & 0xf; 820 else 821 if (i2c_index == 0x81) 822 i2c_index = (dcb->i2c_default_indices & 0xf0) >> 4; 823 824 if (i2c_index >= DCB_MAX_NUM_I2C_ENTRIES) { 825 NV_ERROR(dev, "invalid i2c_index 0x%x\n", i2c_index); 826 return NULL; 827 } 828 829 /* Make sure i2c table entry has been parsed, it may not 830 * have been if this is a bus not referenced by a DCB encoder 831 */ 832 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table, 833 i2c_index, &dcb->i2c[i2c_index]); 834 835 return nouveau_i2c_find(dev, i2c_index); 836} 837 838static uint32_t 839get_tmds_index_reg(struct drm_device *dev, uint8_t mlv) 840{ 841 /* 842 * For mlv < 0x80, it is an index into a table of TMDS base addresses. 843 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by 844 * CR58 for CR57 = 0 to index a table of offsets to the basic 845 * 0x6808b0 address. 846 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by 847 * CR58 for CR57 = 0 to index a table of offsets to the basic 848 * 0x6808b0 address, and then flip the offset by 8. 849 */ 850 851 struct drm_nouveau_private *dev_priv = dev->dev_private; 852 struct nvbios *bios = &dev_priv->vbios; 853 const int pramdac_offset[13] = { 854 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 }; 855 const uint32_t pramdac_table[4] = { 856 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 }; 857 858 if (mlv >= 0x80) { 859 int dcb_entry, dacoffset; 860 861 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */ 862 dcb_entry = dcb_entry_idx_from_crtchead(dev); 863 if (dcb_entry == 0x7f) 864 return 0; 865 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or]; 866 if (mlv == 0x81) 867 dacoffset ^= 8; 868 return 0x6808b0 + dacoffset; 869 } else { 870 if (mlv >= ARRAY_SIZE(pramdac_table)) { 871 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n", 872 mlv); 873 return 0; 874 } 875 return pramdac_table[mlv]; 876 } 877} 878 879static int 880init_io_restrict_prog(struct nvbios *bios, uint16_t offset, 881 struct init_exec *iexec) 882{ 883 /* 884 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2') 885 * 886 * offset (8 bit): opcode 887 * offset + 1 (16 bit): CRTC port 888 * offset + 3 (8 bit): CRTC index 889 * offset + 4 (8 bit): mask 890 * offset + 5 (8 bit): shift 891 * offset + 6 (8 bit): count 892 * offset + 7 (32 bit): register 893 * offset + 11 (32 bit): configuration 1 894 * ... 895 * 896 * Starting at offset + 11 there are "count" 32 bit values. 897 * To find out which value to use read index "CRTC index" on "CRTC 898 * port", AND this value with "mask" and then bit shift right "shift" 899 * bits. Read the appropriate value using this index and write to 900 * "register" 901 */ 902 903 uint16_t crtcport = ROM16(bios->data[offset + 1]); 904 uint8_t crtcindex = bios->data[offset + 3]; 905 uint8_t mask = bios->data[offset + 4]; 906 uint8_t shift = bios->data[offset + 5]; 907 uint8_t count = bios->data[offset + 6]; 908 uint32_t reg = ROM32(bios->data[offset + 7]); 909 uint8_t config; 910 uint32_t configval; 911 int len = 11 + count * 4; 912 913 if (!iexec->execute) 914 return len; 915 916 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 917 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n", 918 offset, crtcport, crtcindex, mask, shift, count, reg); 919 920 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 921 if (config > count) { 922 NV_ERROR(bios->dev, 923 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 924 offset, config, count); 925 return len; 926 } 927 928 configval = ROM32(bios->data[offset + 11 + config * 4]); 929 930 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config); 931 932 bios_wr32(bios, reg, configval); 933 934 return len; 935} 936 937static int 938init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 939{ 940 /* 941 * INIT_REPEAT opcode: 0x33 ('3') 942 * 943 * offset (8 bit): opcode 944 * offset + 1 (8 bit): count 945 * 946 * Execute script following this opcode up to INIT_REPEAT_END 947 * "count" times 948 */ 949 950 uint8_t count = bios->data[offset + 1]; 951 uint8_t i; 952 953 /* no iexec->execute check by design */ 954 955 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n", 956 offset, count); 957 958 iexec->repeat = true; 959 960 /* 961 * count - 1, as the script block will execute once when we leave this 962 * opcode -- this is compatible with bios behaviour as: 963 * a) the block is always executed at least once, even if count == 0 964 * b) the bios interpreter skips to the op following INIT_END_REPEAT, 965 * while we don't 966 */ 967 for (i = 0; i < count - 1; i++) 968 parse_init_table(bios, offset + 2, iexec); 969 970 iexec->repeat = false; 971 972 return 2; 973} 974 975static int 976init_io_restrict_pll(struct nvbios *bios, uint16_t offset, 977 struct init_exec *iexec) 978{ 979 /* 980 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4') 981 * 982 * offset (8 bit): opcode 983 * offset + 1 (16 bit): CRTC port 984 * offset + 3 (8 bit): CRTC index 985 * offset + 4 (8 bit): mask 986 * offset + 5 (8 bit): shift 987 * offset + 6 (8 bit): IO flag condition index 988 * offset + 7 (8 bit): count 989 * offset + 8 (32 bit): register 990 * offset + 12 (16 bit): frequency 1 991 * ... 992 * 993 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz). 994 * Set PLL register "register" to coefficients for frequency n, 995 * selected by reading index "CRTC index" of "CRTC port" ANDed with 996 * "mask" and shifted right by "shift". 997 * 998 * If "IO flag condition index" > 0, and condition met, double 999 * frequency before setting it. 1000 */ 1001 1002 uint16_t crtcport = ROM16(bios->data[offset + 1]); 1003 uint8_t crtcindex = bios->data[offset + 3]; 1004 uint8_t mask = bios->data[offset + 4]; 1005 uint8_t shift = bios->data[offset + 5]; 1006 int8_t io_flag_condition_idx = bios->data[offset + 6]; 1007 uint8_t count = bios->data[offset + 7]; 1008 uint32_t reg = ROM32(bios->data[offset + 8]); 1009 uint8_t config; 1010 uint16_t freq; 1011 int len = 12 + count * 2; 1012 1013 if (!iexec->execute) 1014 return len; 1015 1016 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 1017 "Shift: 0x%02X, IO Flag Condition: 0x%02X, " 1018 "Count: 0x%02X, Reg: 0x%08X\n", 1019 offset, crtcport, crtcindex, mask, shift, 1020 io_flag_condition_idx, count, reg); 1021 1022 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 1023 if (config > count) { 1024 NV_ERROR(bios->dev, 1025 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 1026 offset, config, count); 1027 return len; 1028 } 1029 1030 freq = ROM16(bios->data[offset + 12 + config * 2]); 1031 1032 if (io_flag_condition_idx > 0) { 1033 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) { 1034 BIOSLOG(bios, "0x%04X: Condition fulfilled -- " 1035 "frequency doubled\n", offset); 1036 freq *= 2; 1037 } else 1038 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- " 1039 "frequency unchanged\n", offset); 1040 } 1041 1042 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n", 1043 offset, reg, config, freq); 1044 1045 setPLL(bios, reg, freq * 10); 1046 1047 return len; 1048} 1049 1050static int 1051init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1052{ 1053 /* 1054 * INIT_END_REPEAT opcode: 0x36 ('6') 1055 * 1056 * offset (8 bit): opcode 1057 * 1058 * Marks the end of the block for INIT_REPEAT to repeat 1059 */ 1060 1061 /* no iexec->execute check by design */ 1062 1063 /* 1064 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when 1065 * we're not in repeat mode 1066 */ 1067 if (iexec->repeat) 1068 return 0; 1069 1070 return 1; 1071} 1072 1073static int 1074init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1075{ 1076 /* 1077 * INIT_COPY opcode: 0x37 ('7') 1078 * 1079 * offset (8 bit): opcode 1080 * offset + 1 (32 bit): register 1081 * offset + 5 (8 bit): shift 1082 * offset + 6 (8 bit): srcmask 1083 * offset + 7 (16 bit): CRTC port 1084 * offset + 9 (8 bit): CRTC index 1085 * offset + 10 (8 bit): mask 1086 * 1087 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with 1088 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC 1089 * port 1090 */ 1091 1092 uint32_t reg = ROM32(bios->data[offset + 1]); 1093 uint8_t shift = bios->data[offset + 5]; 1094 uint8_t srcmask = bios->data[offset + 6]; 1095 uint16_t crtcport = ROM16(bios->data[offset + 7]); 1096 uint8_t crtcindex = bios->data[offset + 9]; 1097 uint8_t mask = bios->data[offset + 10]; 1098 uint32_t data; 1099 uint8_t crtcdata; 1100 1101 if (!iexec->execute) 1102 return 11; 1103 1104 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, " 1105 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n", 1106 offset, reg, shift, srcmask, crtcport, crtcindex, mask); 1107 1108 data = bios_rd32(bios, reg); 1109 1110 if (shift < 0x80) 1111 data >>= shift; 1112 else 1113 data <<= (0x100 - shift); 1114 1115 data &= srcmask; 1116 1117 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask; 1118 crtcdata |= (uint8_t)data; 1119 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata); 1120 1121 return 11; 1122} 1123 1124static int 1125init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1126{ 1127 /* 1128 * INIT_NOT opcode: 0x38 ('8') 1129 * 1130 * offset (8 bit): opcode 1131 * 1132 * Invert the current execute / no-execute condition (i.e. "else") 1133 */ 1134 if (iexec->execute) 1135 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset); 1136 else 1137 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset); 1138 1139 iexec->execute = !iexec->execute; 1140 return 1; 1141} 1142 1143static int 1144init_io_flag_condition(struct nvbios *bios, uint16_t offset, 1145 struct init_exec *iexec) 1146{ 1147 /* 1148 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9') 1149 * 1150 * offset (8 bit): opcode 1151 * offset + 1 (8 bit): condition number 1152 * 1153 * Check condition "condition number" in the IO flag condition table. 1154 * If condition not met skip subsequent opcodes until condition is 1155 * inverted (INIT_NOT), or we hit INIT_RESUME 1156 */ 1157 1158 uint8_t cond = bios->data[offset + 1]; 1159 1160 if (!iexec->execute) 1161 return 2; 1162 1163 if (io_flag_condition_met(bios, offset, cond)) 1164 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 1165 else { 1166 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 1167 iexec->execute = false; 1168 } 1169 1170 return 2; 1171} 1172 1173static int 1174init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1175{ 1176 /* 1177 * INIT_DP_CONDITION opcode: 0x3A ('') 1178 * 1179 * offset (8 bit): opcode 1180 * offset + 1 (8 bit): "sub" opcode 1181 * offset + 2 (8 bit): unknown 1182 * 1183 */ 1184 1185 struct bit_displayport_encoder_table *dpe = NULL; 1186 struct dcb_entry *dcb = bios->display.output; 1187 struct drm_device *dev = bios->dev; 1188 uint8_t cond = bios->data[offset + 1]; 1189 int dummy; 1190 1191 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond); 1192 1193 if (!iexec->execute) 1194 return 3; 1195 1196 dpe = nouveau_bios_dp_table(dev, dcb, &dummy); 1197 if (!dpe) { 1198 NV_ERROR(dev, "0x%04X: INIT_3A: no encoder table!!\n", offset); 1199 return 3; 1200 } 1201 1202 switch (cond) { 1203 case 0: 1204 { 1205 struct dcb_connector_table_entry *ent = 1206 &bios->dcb.connector.entry[dcb->connector]; 1207 1208 if (ent->type != DCB_CONNECTOR_eDP) 1209 iexec->execute = false; 1210 } 1211 break; 1212 case 1: 1213 case 2: 1214 if (!(dpe->unknown & cond)) 1215 iexec->execute = false; 1216 break; 1217 case 5: 1218 { 1219 struct nouveau_i2c_chan *auxch; 1220 int ret; 1221 1222 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index); 1223 if (!auxch) { 1224 NV_ERROR(dev, "0x%04X: couldn't get auxch\n", offset); 1225 return 3; 1226 } 1227 1228 ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1); 1229 if (ret) { 1230 NV_ERROR(dev, "0x%04X: auxch rd fail: %d\n", offset, ret); 1231 return 3; 1232 } 1233 1234 if (cond & 1) 1235 iexec->execute = false; 1236 } 1237 break; 1238 default: 1239 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond); 1240 break; 1241 } 1242 1243 if (iexec->execute) 1244 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset); 1245 else 1246 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset); 1247 1248 return 3; 1249} 1250 1251static int 1252init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1253{ 1254 /* 1255 * INIT_3B opcode: 0x3B ('') 1256 * 1257 * offset (8 bit): opcode 1258 * offset + 1 (8 bit): crtc index 1259 * 1260 */ 1261 1262 uint8_t or = ffs(bios->display.output->or) - 1; 1263 uint8_t index = bios->data[offset + 1]; 1264 uint8_t data; 1265 1266 if (!iexec->execute) 1267 return 2; 1268 1269 data = bios_idxprt_rd(bios, 0x3d4, index); 1270 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or)); 1271 return 2; 1272} 1273 1274static int 1275init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1276{ 1277 /* 1278 * INIT_3C opcode: 0x3C ('') 1279 * 1280 * offset (8 bit): opcode 1281 * offset + 1 (8 bit): crtc index 1282 * 1283 */ 1284 1285 uint8_t or = ffs(bios->display.output->or) - 1; 1286 uint8_t index = bios->data[offset + 1]; 1287 uint8_t data; 1288 1289 if (!iexec->execute) 1290 return 2; 1291 1292 data = bios_idxprt_rd(bios, 0x3d4, index); 1293 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or)); 1294 return 2; 1295} 1296 1297static int 1298init_idx_addr_latched(struct nvbios *bios, uint16_t offset, 1299 struct init_exec *iexec) 1300{ 1301 /* 1302 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I') 1303 * 1304 * offset (8 bit): opcode 1305 * offset + 1 (32 bit): control register 1306 * offset + 5 (32 bit): data register 1307 * offset + 9 (32 bit): mask 1308 * offset + 13 (32 bit): data 1309 * offset + 17 (8 bit): count 1310 * offset + 18 (8 bit): address 1 1311 * offset + 19 (8 bit): data 1 1312 * ... 1313 * 1314 * For each of "count" address and data pairs, write "data n" to 1315 * "data register", read the current value of "control register", 1316 * and write it back once ANDed with "mask", ORed with "data", 1317 * and ORed with "address n" 1318 */ 1319 1320 uint32_t controlreg = ROM32(bios->data[offset + 1]); 1321 uint32_t datareg = ROM32(bios->data[offset + 5]); 1322 uint32_t mask = ROM32(bios->data[offset + 9]); 1323 uint32_t data = ROM32(bios->data[offset + 13]); 1324 uint8_t count = bios->data[offset + 17]; 1325 int len = 18 + count * 2; 1326 uint32_t value; 1327 int i; 1328 1329 if (!iexec->execute) 1330 return len; 1331 1332 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, " 1333 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n", 1334 offset, controlreg, datareg, mask, data, count); 1335 1336 for (i = 0; i < count; i++) { 1337 uint8_t instaddress = bios->data[offset + 18 + i * 2]; 1338 uint8_t instdata = bios->data[offset + 19 + i * 2]; 1339 1340 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n", 1341 offset, instaddress, instdata); 1342 1343 bios_wr32(bios, datareg, instdata); 1344 value = bios_rd32(bios, controlreg) & mask; 1345 value |= data; 1346 value |= instaddress; 1347 bios_wr32(bios, controlreg, value); 1348 } 1349 1350 return len; 1351} 1352 1353static int 1354init_io_restrict_pll2(struct nvbios *bios, uint16_t offset, 1355 struct init_exec *iexec) 1356{ 1357 /* 1358 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J') 1359 * 1360 * offset (8 bit): opcode 1361 * offset + 1 (16 bit): CRTC port 1362 * offset + 3 (8 bit): CRTC index 1363 * offset + 4 (8 bit): mask 1364 * offset + 5 (8 bit): shift 1365 * offset + 6 (8 bit): count 1366 * offset + 7 (32 bit): register 1367 * offset + 11 (32 bit): frequency 1 1368 * ... 1369 * 1370 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz). 1371 * Set PLL register "register" to coefficients for frequency n, 1372 * selected by reading index "CRTC index" of "CRTC port" ANDed with 1373 * "mask" and shifted right by "shift". 1374 */ 1375 1376 uint16_t crtcport = ROM16(bios->data[offset + 1]); 1377 uint8_t crtcindex = bios->data[offset + 3]; 1378 uint8_t mask = bios->data[offset + 4]; 1379 uint8_t shift = bios->data[offset + 5]; 1380 uint8_t count = bios->data[offset + 6]; 1381 uint32_t reg = ROM32(bios->data[offset + 7]); 1382 int len = 11 + count * 4; 1383 uint8_t config; 1384 uint32_t freq; 1385 1386 if (!iexec->execute) 1387 return len; 1388 1389 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 1390 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n", 1391 offset, crtcport, crtcindex, mask, shift, count, reg); 1392 1393 if (!reg) 1394 return len; 1395 1396 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 1397 if (config > count) { 1398 NV_ERROR(bios->dev, 1399 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 1400 offset, config, count); 1401 return len; 1402 } 1403 1404 freq = ROM32(bios->data[offset + 11 + config * 4]); 1405 1406 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n", 1407 offset, reg, config, freq); 1408 1409 setPLL(bios, reg, freq); 1410 1411 return len; 1412} 1413 1414static int 1415init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1416{ 1417 /* 1418 * INIT_PLL2 opcode: 0x4B ('K') 1419 * 1420 * offset (8 bit): opcode 1421 * offset + 1 (32 bit): register 1422 * offset + 5 (32 bit): freq 1423 * 1424 * Set PLL register "register" to coefficients for frequency "freq" 1425 */ 1426 1427 uint32_t reg = ROM32(bios->data[offset + 1]); 1428 uint32_t freq = ROM32(bios->data[offset + 5]); 1429 1430 if (!iexec->execute) 1431 return 9; 1432 1433 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n", 1434 offset, reg, freq); 1435 1436 setPLL(bios, reg, freq); 1437 return 9; 1438} 1439 1440static int 1441init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1442{ 1443 /* 1444 * INIT_I2C_BYTE opcode: 0x4C ('L') 1445 * 1446 * offset (8 bit): opcode 1447 * offset + 1 (8 bit): DCB I2C table entry index 1448 * offset + 2 (8 bit): I2C slave address 1449 * offset + 3 (8 bit): count 1450 * offset + 4 (8 bit): I2C register 1 1451 * offset + 5 (8 bit): mask 1 1452 * offset + 6 (8 bit): data 1 1453 * ... 1454 * 1455 * For each of "count" registers given by "I2C register n" on the device 1456 * addressed by "I2C slave address" on the I2C bus given by 1457 * "DCB I2C table entry index", read the register, AND the result with 1458 * "mask n" and OR it with "data n" before writing it back to the device 1459 */ 1460 1461 struct drm_device *dev = bios->dev; 1462 uint8_t i2c_index = bios->data[offset + 1]; 1463 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1464 uint8_t count = bios->data[offset + 3]; 1465 struct nouveau_i2c_chan *chan; 1466 int len = 4 + count * 3; 1467 int ret, i; 1468 1469 if (!iexec->execute) 1470 return len; 1471 1472 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1473 "Count: 0x%02X\n", 1474 offset, i2c_index, i2c_address, count); 1475 1476 chan = init_i2c_device_find(dev, i2c_index); 1477 if (!chan) { 1478 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset); 1479 return len; 1480 } 1481 1482 for (i = 0; i < count; i++) { 1483 uint8_t reg = bios->data[offset + 4 + i * 3]; 1484 uint8_t mask = bios->data[offset + 5 + i * 3]; 1485 uint8_t data = bios->data[offset + 6 + i * 3]; 1486 union i2c_smbus_data val; 1487 1488 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 1489 I2C_SMBUS_READ, reg, 1490 I2C_SMBUS_BYTE_DATA, &val); 1491 if (ret < 0) { 1492 NV_ERROR(dev, "0x%04X: i2c rd fail: %d\n", offset, ret); 1493 return len; 1494 } 1495 1496 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, " 1497 "Mask: 0x%02X, Data: 0x%02X\n", 1498 offset, reg, val.byte, mask, data); 1499 1500 if (!bios->execute) 1501 continue; 1502 1503 val.byte &= mask; 1504 val.byte |= data; 1505 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 1506 I2C_SMBUS_WRITE, reg, 1507 I2C_SMBUS_BYTE_DATA, &val); 1508 if (ret < 0) { 1509 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret); 1510 return len; 1511 } 1512 } 1513 1514 return len; 1515} 1516 1517static int 1518init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1519{ 1520 /* 1521 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M') 1522 * 1523 * offset (8 bit): opcode 1524 * offset + 1 (8 bit): DCB I2C table entry index 1525 * offset + 2 (8 bit): I2C slave address 1526 * offset + 3 (8 bit): count 1527 * offset + 4 (8 bit): I2C register 1 1528 * offset + 5 (8 bit): data 1 1529 * ... 1530 * 1531 * For each of "count" registers given by "I2C register n" on the device 1532 * addressed by "I2C slave address" on the I2C bus given by 1533 * "DCB I2C table entry index", set the register to "data n" 1534 */ 1535 1536 struct drm_device *dev = bios->dev; 1537 uint8_t i2c_index = bios->data[offset + 1]; 1538 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1539 uint8_t count = bios->data[offset + 3]; 1540 struct nouveau_i2c_chan *chan; 1541 int len = 4 + count * 2; 1542 int ret, i; 1543 1544 if (!iexec->execute) 1545 return len; 1546 1547 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1548 "Count: 0x%02X\n", 1549 offset, i2c_index, i2c_address, count); 1550 1551 chan = init_i2c_device_find(dev, i2c_index); 1552 if (!chan) { 1553 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset); 1554 return len; 1555 } 1556 1557 for (i = 0; i < count; i++) { 1558 uint8_t reg = bios->data[offset + 4 + i * 2]; 1559 union i2c_smbus_data val; 1560 1561 val.byte = bios->data[offset + 5 + i * 2]; 1562 1563 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n", 1564 offset, reg, val.byte); 1565 1566 if (!bios->execute) 1567 continue; 1568 1569 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 1570 I2C_SMBUS_WRITE, reg, 1571 I2C_SMBUS_BYTE_DATA, &val); 1572 if (ret < 0) { 1573 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret); 1574 return len; 1575 } 1576 } 1577 1578 return len; 1579} 1580 1581static int 1582init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1583{ 1584 /* 1585 * INIT_ZM_I2C opcode: 0x4E ('N') 1586 * 1587 * offset (8 bit): opcode 1588 * offset + 1 (8 bit): DCB I2C table entry index 1589 * offset + 2 (8 bit): I2C slave address 1590 * offset + 3 (8 bit): count 1591 * offset + 4 (8 bit): data 1 1592 * ... 1593 * 1594 * Send "count" bytes ("data n") to the device addressed by "I2C slave 1595 * address" on the I2C bus given by "DCB I2C table entry index" 1596 */ 1597 1598 struct drm_device *dev = bios->dev; 1599 uint8_t i2c_index = bios->data[offset + 1]; 1600 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1601 uint8_t count = bios->data[offset + 3]; 1602 int len = 4 + count; 1603 struct nouveau_i2c_chan *chan; 1604 struct i2c_msg msg; 1605 uint8_t data[256]; 1606 int ret, i; 1607 1608 if (!iexec->execute) 1609 return len; 1610 1611 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1612 "Count: 0x%02X\n", 1613 offset, i2c_index, i2c_address, count); 1614 1615 chan = init_i2c_device_find(dev, i2c_index); 1616 if (!chan) { 1617 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset); 1618 return len; 1619 } 1620 1621 for (i = 0; i < count; i++) { 1622 data[i] = bios->data[offset + 4 + i]; 1623 1624 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]); 1625 } 1626 1627 if (bios->execute) { 1628 msg.addr = i2c_address; 1629 msg.flags = 0; 1630 msg.len = count; 1631 msg.buf = data; 1632 ret = i2c_transfer(&chan->adapter, &msg, 1); 1633 if (ret != 1) { 1634 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret); 1635 return len; 1636 } 1637 } 1638 1639 return len; 1640} 1641 1642static int 1643init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1644{ 1645 /* 1646 * INIT_TMDS opcode: 0x4F ('O') (non-canon name) 1647 * 1648 * offset (8 bit): opcode 1649 * offset + 1 (8 bit): magic lookup value 1650 * offset + 2 (8 bit): TMDS address 1651 * offset + 3 (8 bit): mask 1652 * offset + 4 (8 bit): data 1653 * 1654 * Read the data reg for TMDS address "TMDS address", AND it with mask 1655 * and OR it with data, then write it back 1656 * "magic lookup value" determines which TMDS base address register is 1657 * used -- see get_tmds_index_reg() 1658 */ 1659 1660 struct drm_device *dev = bios->dev; 1661 uint8_t mlv = bios->data[offset + 1]; 1662 uint32_t tmdsaddr = bios->data[offset + 2]; 1663 uint8_t mask = bios->data[offset + 3]; 1664 uint8_t data = bios->data[offset + 4]; 1665 uint32_t reg, value; 1666 1667 if (!iexec->execute) 1668 return 5; 1669 1670 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, " 1671 "Mask: 0x%02X, Data: 0x%02X\n", 1672 offset, mlv, tmdsaddr, mask, data); 1673 1674 reg = get_tmds_index_reg(bios->dev, mlv); 1675 if (!reg) { 1676 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset); 1677 return 5; 1678 } 1679 1680 bios_wr32(bios, reg, 1681 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE); 1682 value = (bios_rd32(bios, reg + 4) & mask) | data; 1683 bios_wr32(bios, reg + 4, value); 1684 bios_wr32(bios, reg, tmdsaddr); 1685 1686 return 5; 1687} 1688 1689static int 1690init_zm_tmds_group(struct nvbios *bios, uint16_t offset, 1691 struct init_exec *iexec) 1692{ 1693 /* 1694 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name) 1695 * 1696 * offset (8 bit): opcode 1697 * offset + 1 (8 bit): magic lookup value 1698 * offset + 2 (8 bit): count 1699 * offset + 3 (8 bit): addr 1 1700 * offset + 4 (8 bit): data 1 1701 * ... 1702 * 1703 * For each of "count" TMDS address and data pairs write "data n" to 1704 * "addr n". "magic lookup value" determines which TMDS base address 1705 * register is used -- see get_tmds_index_reg() 1706 */ 1707 1708 struct drm_device *dev = bios->dev; 1709 uint8_t mlv = bios->data[offset + 1]; 1710 uint8_t count = bios->data[offset + 2]; 1711 int len = 3 + count * 2; 1712 uint32_t reg; 1713 int i; 1714 1715 if (!iexec->execute) 1716 return len; 1717 1718 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n", 1719 offset, mlv, count); 1720 1721 reg = get_tmds_index_reg(bios->dev, mlv); 1722 if (!reg) { 1723 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset); 1724 return len; 1725 } 1726 1727 for (i = 0; i < count; i++) { 1728 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2]; 1729 uint8_t tmdsdata = bios->data[offset + 4 + i * 2]; 1730 1731 bios_wr32(bios, reg + 4, tmdsdata); 1732 bios_wr32(bios, reg, tmdsaddr); 1733 } 1734 1735 return len; 1736} 1737 1738static int 1739init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset, 1740 struct init_exec *iexec) 1741{ 1742 /* 1743 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q') 1744 * 1745 * offset (8 bit): opcode 1746 * offset + 1 (8 bit): CRTC index1 1747 * offset + 2 (8 bit): CRTC index2 1748 * offset + 3 (8 bit): baseaddr 1749 * offset + 4 (8 bit): count 1750 * offset + 5 (8 bit): data 1 1751 * ... 1752 * 1753 * For each of "count" address and data pairs, write "baseaddr + n" to 1754 * "CRTC index1" and "data n" to "CRTC index2" 1755 * Once complete, restore initial value read from "CRTC index1" 1756 */ 1757 uint8_t crtcindex1 = bios->data[offset + 1]; 1758 uint8_t crtcindex2 = bios->data[offset + 2]; 1759 uint8_t baseaddr = bios->data[offset + 3]; 1760 uint8_t count = bios->data[offset + 4]; 1761 int len = 5 + count; 1762 uint8_t oldaddr, data; 1763 int i; 1764 1765 if (!iexec->execute) 1766 return len; 1767 1768 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, " 1769 "BaseAddr: 0x%02X, Count: 0x%02X\n", 1770 offset, crtcindex1, crtcindex2, baseaddr, count); 1771 1772 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1); 1773 1774 for (i = 0; i < count; i++) { 1775 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, 1776 baseaddr + i); 1777 data = bios->data[offset + 5 + i]; 1778 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data); 1779 } 1780 1781 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr); 1782 1783 return len; 1784} 1785 1786static int 1787init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1788{ 1789 /* 1790 * INIT_CR opcode: 0x52 ('R') 1791 * 1792 * offset (8 bit): opcode 1793 * offset + 1 (8 bit): CRTC index 1794 * offset + 2 (8 bit): mask 1795 * offset + 3 (8 bit): data 1796 * 1797 * Assign the value of at "CRTC index" ANDed with mask and ORed with 1798 * data back to "CRTC index" 1799 */ 1800 1801 uint8_t crtcindex = bios->data[offset + 1]; 1802 uint8_t mask = bios->data[offset + 2]; 1803 uint8_t data = bios->data[offset + 3]; 1804 uint8_t value; 1805 1806 if (!iexec->execute) 1807 return 4; 1808 1809 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n", 1810 offset, crtcindex, mask, data); 1811 1812 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask; 1813 value |= data; 1814 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value); 1815 1816 return 4; 1817} 1818 1819static int 1820init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1821{ 1822 /* 1823 * INIT_ZM_CR opcode: 0x53 ('S') 1824 * 1825 * offset (8 bit): opcode 1826 * offset + 1 (8 bit): CRTC index 1827 * offset + 2 (8 bit): value 1828 * 1829 * Assign "value" to CRTC register with index "CRTC index". 1830 */ 1831 1832 uint8_t crtcindex = ROM32(bios->data[offset + 1]); 1833 uint8_t data = bios->data[offset + 2]; 1834 1835 if (!iexec->execute) 1836 return 3; 1837 1838 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data); 1839 1840 return 3; 1841} 1842 1843static int 1844init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1845{ 1846 /* 1847 * INIT_ZM_CR_GROUP opcode: 0x54 ('T') 1848 * 1849 * offset (8 bit): opcode 1850 * offset + 1 (8 bit): count 1851 * offset + 2 (8 bit): CRTC index 1 1852 * offset + 3 (8 bit): value 1 1853 * ... 1854 * 1855 * For "count", assign "value n" to CRTC register with index 1856 * "CRTC index n". 1857 */ 1858 1859 uint8_t count = bios->data[offset + 1]; 1860 int len = 2 + count * 2; 1861 int i; 1862 1863 if (!iexec->execute) 1864 return len; 1865 1866 for (i = 0; i < count; i++) 1867 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec); 1868 1869 return len; 1870} 1871 1872static int 1873init_condition_time(struct nvbios *bios, uint16_t offset, 1874 struct init_exec *iexec) 1875{ 1876 /* 1877 * INIT_CONDITION_TIME opcode: 0x56 ('V') 1878 * 1879 * offset (8 bit): opcode 1880 * offset + 1 (8 bit): condition number 1881 * offset + 2 (8 bit): retries / 50 1882 * 1883 * Check condition "condition number" in the condition table. 1884 * Bios code then sleeps for 2ms if the condition is not met, and 1885 * repeats up to "retries" times, but on one C51 this has proved 1886 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do 1887 * this, and bail after "retries" times, or 2s, whichever is less. 1888 * If still not met after retries, clear execution flag for this table. 1889 */ 1890 1891 uint8_t cond = bios->data[offset + 1]; 1892 uint16_t retries = bios->data[offset + 2] * 50; 1893 unsigned cnt; 1894 1895 if (!iexec->execute) 1896 return 3; 1897 1898 if (retries > 100) 1899 retries = 100; 1900 1901 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n", 1902 offset, cond, retries); 1903 1904 if (!bios->execute) /* avoid 2s delays when "faking" execution */ 1905 retries = 1; 1906 1907 for (cnt = 0; cnt < retries; cnt++) { 1908 if (bios_condition_met(bios, offset, cond)) { 1909 BIOSLOG(bios, "0x%04X: Condition met, continuing\n", 1910 offset); 1911 break; 1912 } else { 1913 BIOSLOG(bios, "0x%04X: " 1914 "Condition not met, sleeping for 20ms\n", 1915 offset); 1916 msleep(20); 1917 } 1918 } 1919 1920 if (!bios_condition_met(bios, offset, cond)) { 1921 NV_WARN(bios->dev, 1922 "0x%04X: Condition still not met after %dms, " 1923 "skipping following opcodes\n", offset, 20 * retries); 1924 iexec->execute = false; 1925 } 1926 1927 return 3; 1928} 1929 1930static int 1931init_zm_reg_sequence(struct nvbios *bios, uint16_t offset, 1932 struct init_exec *iexec) 1933{ 1934 /* 1935 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X') 1936 * 1937 * offset (8 bit): opcode 1938 * offset + 1 (32 bit): base register 1939 * offset + 5 (8 bit): count 1940 * offset + 6 (32 bit): value 1 1941 * ... 1942 * 1943 * Starting at offset + 6 there are "count" 32 bit values. 1944 * For "count" iterations set "base register" + 4 * current_iteration 1945 * to "value current_iteration" 1946 */ 1947 1948 uint32_t basereg = ROM32(bios->data[offset + 1]); 1949 uint32_t count = bios->data[offset + 5]; 1950 int len = 6 + count * 4; 1951 int i; 1952 1953 if (!iexec->execute) 1954 return len; 1955 1956 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n", 1957 offset, basereg, count); 1958 1959 for (i = 0; i < count; i++) { 1960 uint32_t reg = basereg + i * 4; 1961 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]); 1962 1963 bios_wr32(bios, reg, data); 1964 } 1965 1966 return len; 1967} 1968 1969static int 1970init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1971{ 1972 /* 1973 * INIT_SUB_DIRECT opcode: 0x5B ('[') 1974 * 1975 * offset (8 bit): opcode 1976 * offset + 1 (16 bit): subroutine offset (in bios) 1977 * 1978 * Calls a subroutine that will execute commands until INIT_DONE 1979 * is found. 1980 */ 1981 1982 uint16_t sub_offset = ROM16(bios->data[offset + 1]); 1983 1984 if (!iexec->execute) 1985 return 3; 1986 1987 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n", 1988 offset, sub_offset); 1989 1990 parse_init_table(bios, sub_offset, iexec); 1991 1992 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset); 1993 1994 return 3; 1995} 1996 1997static int 1998init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1999{ 2000 /* 2001 * INIT_COPY_NV_REG opcode: 0x5F ('_') 2002 * 2003 * offset (8 bit): opcode 2004 * offset + 1 (32 bit): src reg 2005 * offset + 5 (8 bit): shift 2006 * offset + 6 (32 bit): src mask 2007 * offset + 10 (32 bit): xor 2008 * offset + 14 (32 bit): dst reg 2009 * offset + 18 (32 bit): dst mask 2010 * 2011 * Shift REGVAL("src reg") right by (signed) "shift", AND result with 2012 * "src mask", then XOR with "xor". Write this OR'd with 2013 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg" 2014 */ 2015 2016 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1])); 2017 uint8_t shift = bios->data[offset + 5]; 2018 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6])); 2019 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10])); 2020 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14])); 2021 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18])); 2022 uint32_t srcvalue, dstvalue; 2023 2024 if (!iexec->execute) 2025 return 22; 2026 2027 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, " 2028 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n", 2029 offset, srcreg, shift, srcmask, xor, dstreg, dstmask); 2030 2031 srcvalue = bios_rd32(bios, srcreg); 2032 2033 if (shift < 0x80) 2034 srcvalue >>= shift; 2035 else 2036 srcvalue <<= (0x100 - shift); 2037 2038 srcvalue = (srcvalue & srcmask) ^ xor; 2039 2040 dstvalue = bios_rd32(bios, dstreg) & dstmask; 2041 2042 bios_wr32(bios, dstreg, dstvalue | srcvalue); 2043 2044 return 22; 2045} 2046 2047static int 2048init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2049{ 2050 /* 2051 * INIT_ZM_INDEX_IO opcode: 0x62 ('b') 2052 * 2053 * offset (8 bit): opcode 2054 * offset + 1 (16 bit): CRTC port 2055 * offset + 3 (8 bit): CRTC index 2056 * offset + 4 (8 bit): data 2057 * 2058 * Write "data" to index "CRTC index" of "CRTC port" 2059 */ 2060 uint16_t crtcport = ROM16(bios->data[offset + 1]); 2061 uint8_t crtcindex = bios->data[offset + 3]; 2062 uint8_t data = bios->data[offset + 4]; 2063 2064 if (!iexec->execute) 2065 return 5; 2066 2067 bios_idxprt_wr(bios, crtcport, crtcindex, data); 2068 2069 return 5; 2070} 2071 2072static inline void 2073bios_md32(struct nvbios *bios, uint32_t reg, 2074 uint32_t mask, uint32_t val) 2075{ 2076 bios_wr32(bios, reg, (bios_rd32(bios, reg) & ~mask) | val); 2077} 2078 2079static uint32_t 2080peek_fb(struct drm_device *dev, struct io_mapping *fb, 2081 uint32_t off) 2082{ 2083 uint32_t val = 0; 2084 2085 if (off < pci_resource_len(dev->pdev, 1)) { 2086 uint32_t __iomem *p = io_mapping_map_atomic_wc(fb, off); 2087 2088 val = ioread32(p); 2089 2090 io_mapping_unmap_atomic(p); 2091 } 2092 2093 return val; 2094} 2095 2096static void 2097poke_fb(struct drm_device *dev, struct io_mapping *fb, 2098 uint32_t off, uint32_t val) 2099{ 2100 if (off < pci_resource_len(dev->pdev, 1)) { 2101 uint32_t __iomem *p = io_mapping_map_atomic_wc(fb, off); 2102 2103 iowrite32(val, p); 2104 wmb(); 2105 2106 io_mapping_unmap_atomic(p); 2107 } 2108} 2109 2110static inline bool 2111read_back_fb(struct drm_device *dev, struct io_mapping *fb, 2112 uint32_t off, uint32_t val) 2113{ 2114 poke_fb(dev, fb, off, val); 2115 return val == peek_fb(dev, fb, off); 2116} 2117 2118static int 2119nv04_init_compute_mem(struct nvbios *bios) 2120{ 2121 struct drm_device *dev = bios->dev; 2122 uint32_t patt = 0xdeadbeef; 2123 struct io_mapping *fb; 2124 int i; 2125 2126 /* Map the framebuffer aperture */ 2127 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1), 2128 pci_resource_len(dev->pdev, 1)); 2129 if (!fb) 2130 return -ENOMEM; 2131 2132 /* Sequencer and refresh off */ 2133 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20); 2134 bios_md32(bios, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF); 2135 2136 bios_md32(bios, NV04_PFB_BOOT_0, ~0, 2137 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB | 2138 NV04_PFB_BOOT_0_RAM_WIDTH_128 | 2139 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT); 2140 2141 for (i = 0; i < 4; i++) 2142 poke_fb(dev, fb, 4 * i, patt); 2143 2144 poke_fb(dev, fb, 0x400000, patt + 1); 2145 2146 if (peek_fb(dev, fb, 0) == patt + 1) { 2147 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE, 2148 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT); 2149 bios_md32(bios, NV04_PFB_DEBUG_0, 2150 NV04_PFB_DEBUG_0_REFRESH_OFF, 0); 2151 2152 for (i = 0; i < 4; i++) 2153 poke_fb(dev, fb, 4 * i, patt); 2154 2155 if ((peek_fb(dev, fb, 0xc) & 0xffff) != (patt & 0xffff)) 2156 bios_md32(bios, NV04_PFB_BOOT_0, 2157 NV04_PFB_BOOT_0_RAM_WIDTH_128 | 2158 NV04_PFB_BOOT_0_RAM_AMOUNT, 2159 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 2160 2161 } else if ((peek_fb(dev, fb, 0xc) & 0xffff0000) != 2162 (patt & 0xffff0000)) { 2163 bios_md32(bios, NV04_PFB_BOOT_0, 2164 NV04_PFB_BOOT_0_RAM_WIDTH_128 | 2165 NV04_PFB_BOOT_0_RAM_AMOUNT, 2166 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); 2167 2168 } else if (peek_fb(dev, fb, 0) == patt) { 2169 if (read_back_fb(dev, fb, 0x800000, patt)) 2170 bios_md32(bios, NV04_PFB_BOOT_0, 2171 NV04_PFB_BOOT_0_RAM_AMOUNT, 2172 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 2173 else 2174 bios_md32(bios, NV04_PFB_BOOT_0, 2175 NV04_PFB_BOOT_0_RAM_AMOUNT, 2176 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); 2177 2178 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE, 2179 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT); 2180 2181 } else if (!read_back_fb(dev, fb, 0x800000, patt)) { 2182 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, 2183 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 2184 2185 } 2186 2187 /* Refresh on, sequencer on */ 2188 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0); 2189 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20); 2190 2191 io_mapping_free(fb); 2192 return 0; 2193} 2194 2195static const uint8_t * 2196nv05_memory_config(struct nvbios *bios) 2197{ 2198 /* Defaults for BIOSes lacking a memory config table */ 2199 static const uint8_t default_config_tab[][2] = { 2200 { 0x24, 0x00 }, 2201 { 0x28, 0x00 }, 2202 { 0x24, 0x01 }, 2203 { 0x1f, 0x00 }, 2204 { 0x0f, 0x00 }, 2205 { 0x17, 0x00 }, 2206 { 0x06, 0x00 }, 2207 { 0x00, 0x00 } 2208 }; 2209 int i = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 2210 NV_PEXTDEV_BOOT_0_RAMCFG) >> 2; 2211 2212 if (bios->legacy.mem_init_tbl_ptr) 2213 return &bios->data[bios->legacy.mem_init_tbl_ptr + 2 * i]; 2214 else 2215 return default_config_tab[i]; 2216} 2217 2218static int 2219nv05_init_compute_mem(struct nvbios *bios) 2220{ 2221 struct drm_device *dev = bios->dev; 2222 const uint8_t *ramcfg = nv05_memory_config(bios); 2223 uint32_t patt = 0xdeadbeef; 2224 struct io_mapping *fb; 2225 int i, v; 2226 2227 /* Map the framebuffer aperture */ 2228 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1), 2229 pci_resource_len(dev->pdev, 1)); 2230 if (!fb) 2231 return -ENOMEM; 2232 2233 /* Sequencer off */ 2234 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20); 2235 2236 if (bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE) 2237 goto out; 2238 2239 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0); 2240 2241 /* If present load the hardcoded scrambling table */ 2242 if (bios->legacy.mem_init_tbl_ptr) { 2243 uint32_t *scramble_tab = (uint32_t *)&bios->data[ 2244 bios->legacy.mem_init_tbl_ptr + 0x10]; 2245 2246 for (i = 0; i < 8; i++) 2247 bios_wr32(bios, NV04_PFB_SCRAMBLE(i), 2248 ROM32(scramble_tab[i])); 2249 } 2250 2251 /* Set memory type/width/length defaults depending on the straps */ 2252 bios_md32(bios, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]); 2253 2254 if (ramcfg[1] & 0x80) 2255 bios_md32(bios, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE); 2256 2257 bios_md32(bios, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20); 2258 bios_md32(bios, NV04_PFB_CFG1, 0, 1); 2259 2260 /* Probe memory bus width */ 2261 for (i = 0; i < 4; i++) 2262 poke_fb(dev, fb, 4 * i, patt); 2263 2264 if (peek_fb(dev, fb, 0xc) != patt) 2265 bios_md32(bios, NV04_PFB_BOOT_0, 2266 NV04_PFB_BOOT_0_RAM_WIDTH_128, 0); 2267 2268 /* Probe memory length */ 2269 v = bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT; 2270 2271 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB && 2272 (!read_back_fb(dev, fb, 0x1000000, ++patt) || 2273 !read_back_fb(dev, fb, 0, ++patt))) 2274 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, 2275 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB); 2276 2277 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB && 2278 !read_back_fb(dev, fb, 0x800000, ++patt)) 2279 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, 2280 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 2281 2282 if (!read_back_fb(dev, fb, 0x400000, ++patt)) 2283 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, 2284 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); 2285 2286out: 2287 /* Sequencer on */ 2288 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20); 2289 2290 io_mapping_free(fb); 2291 return 0; 2292} 2293 2294static int 2295nv10_init_compute_mem(struct nvbios *bios) 2296{ 2297 struct drm_device *dev = bios->dev; 2298 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2299 const int mem_width[] = { 0x10, 0x00, 0x20 }; 2300 const int mem_width_count = (dev_priv->chipset >= 0x17 ? 3 : 2); 2301 uint32_t patt = 0xdeadbeef; 2302 struct io_mapping *fb; 2303 int i, j, k; 2304 2305 /* Map the framebuffer aperture */ 2306 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1), 2307 pci_resource_len(dev->pdev, 1)); 2308 if (!fb) 2309 return -ENOMEM; 2310 2311 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1); 2312 2313 /* Probe memory bus width */ 2314 for (i = 0; i < mem_width_count; i++) { 2315 bios_md32(bios, NV04_PFB_CFG0, 0x30, mem_width[i]); 2316 2317 for (j = 0; j < 4; j++) { 2318 for (k = 0; k < 4; k++) 2319 poke_fb(dev, fb, 0x1c, 0); 2320 2321 poke_fb(dev, fb, 0x1c, patt); 2322 poke_fb(dev, fb, 0x3c, 0); 2323 2324 if (peek_fb(dev, fb, 0x1c) == patt) 2325 goto mem_width_found; 2326 } 2327 } 2328 2329mem_width_found: 2330 patt <<= 1; 2331 2332 /* Probe amount of installed memory */ 2333 for (i = 0; i < 4; i++) { 2334 int off = bios_rd32(bios, NV04_PFB_FIFO_DATA) - 0x100000; 2335 2336 poke_fb(dev, fb, off, patt); 2337 poke_fb(dev, fb, 0, 0); 2338 2339 peek_fb(dev, fb, 0); 2340 peek_fb(dev, fb, 0); 2341 peek_fb(dev, fb, 0); 2342 peek_fb(dev, fb, 0); 2343 2344 if (peek_fb(dev, fb, off) == patt) 2345 goto amount_found; 2346 } 2347 2348 /* IC missing - disable the upper half memory space. */ 2349 bios_md32(bios, NV04_PFB_CFG0, 0x1000, 0); 2350 2351amount_found: 2352 io_mapping_free(fb); 2353 return 0; 2354} 2355 2356static int 2357nv20_init_compute_mem(struct nvbios *bios) 2358{ 2359 struct drm_device *dev = bios->dev; 2360 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2361 uint32_t mask = (dev_priv->chipset >= 0x25 ? 0x300 : 0x900); 2362 uint32_t amount, off; 2363 struct io_mapping *fb; 2364 2365 /* Map the framebuffer aperture */ 2366 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1), 2367 pci_resource_len(dev->pdev, 1)); 2368 if (!fb) 2369 return -ENOMEM; 2370 2371 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1); 2372 2373 /* Allow full addressing */ 2374 bios_md32(bios, NV04_PFB_CFG0, 0, mask); 2375 2376 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA); 2377 for (off = amount; off > 0x2000000; off -= 0x2000000) 2378 poke_fb(dev, fb, off - 4, off); 2379 2380 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA); 2381 if (amount != peek_fb(dev, fb, amount - 4)) 2382 /* IC missing - disable the upper half memory space. */ 2383 bios_md32(bios, NV04_PFB_CFG0, mask, 0); 2384 2385 io_mapping_free(fb); 2386 return 0; 2387} 2388 2389static int 2390init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2391{ 2392 /* 2393 * INIT_COMPUTE_MEM opcode: 0x63 ('c') 2394 * 2395 * offset (8 bit): opcode 2396 * 2397 * This opcode is meant to set the PFB memory config registers 2398 * appropriately so that we can correctly calculate how much VRAM it 2399 * has (on nv10 and better chipsets the amount of installed VRAM is 2400 * subsequently reported in NV_PFB_CSTATUS (0x10020C)). 2401 * 2402 * The implementation of this opcode in general consists of several 2403 * parts: 2404 * 2405 * 1) Determination of memory type and density. Only necessary for 2406 * really old chipsets, the memory type reported by the strap bits 2407 * (0x101000) is assumed to be accurate on nv05 and newer. 2408 * 2409 * 2) Determination of the memory bus width. Usually done by a cunning 2410 * combination of writes to offsets 0x1c and 0x3c in the fb, and 2411 * seeing whether the written values are read back correctly. 2412 * 2413 * Only necessary on nv0x-nv1x and nv34, on the other cards we can 2414 * trust the straps. 2415 * 2416 * 3) Determination of how many of the card's RAM pads have ICs 2417 * attached, usually done by a cunning combination of writes to an 2418 * offset slightly less than the maximum memory reported by 2419 * NV_PFB_CSTATUS, then seeing if the test pattern can be read back. 2420 * 2421 * This appears to be a NOP on IGPs and NV4x or newer chipsets, both io 2422 * logs of the VBIOS and kmmio traces of the binary driver POSTing the 2423 * card show nothing being done for this opcode. Why is it still listed 2424 * in the table?! 2425 */ 2426 2427 /* no iexec->execute check by design */ 2428 2429 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2430 int ret; 2431 2432 if (dev_priv->chipset >= 0x40 || 2433 dev_priv->chipset == 0x1a || 2434 dev_priv->chipset == 0x1f) 2435 ret = 0; 2436 else if (dev_priv->chipset >= 0x20 && 2437 dev_priv->chipset != 0x34) 2438 ret = nv20_init_compute_mem(bios); 2439 else if (dev_priv->chipset >= 0x10) 2440 ret = nv10_init_compute_mem(bios); 2441 else if (dev_priv->chipset >= 0x5) 2442 ret = nv05_init_compute_mem(bios); 2443 else 2444 ret = nv04_init_compute_mem(bios); 2445 2446 if (ret) 2447 return ret; 2448 2449 return 1; 2450} 2451 2452static int 2453init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2454{ 2455 /* 2456 * INIT_RESET opcode: 0x65 ('e') 2457 * 2458 * offset (8 bit): opcode 2459 * offset + 1 (32 bit): register 2460 * offset + 5 (32 bit): value1 2461 * offset + 9 (32 bit): value2 2462 * 2463 * Assign "value1" to "register", then assign "value2" to "register" 2464 */ 2465 2466 uint32_t reg = ROM32(bios->data[offset + 1]); 2467 uint32_t value1 = ROM32(bios->data[offset + 5]); 2468 uint32_t value2 = ROM32(bios->data[offset + 9]); 2469 uint32_t pci_nv_19, pci_nv_20; 2470 2471 /* no iexec->execute check by design */ 2472 2473 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19); 2474 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19 & ~0xf00); 2475 2476 bios_wr32(bios, reg, value1); 2477 2478 udelay(10); 2479 2480 bios_wr32(bios, reg, value2); 2481 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19); 2482 2483 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20); 2484 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */ 2485 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20); 2486 2487 return 13; 2488} 2489 2490static int 2491init_configure_mem(struct nvbios *bios, uint16_t offset, 2492 struct init_exec *iexec) 2493{ 2494 /* 2495 * INIT_CONFIGURE_MEM opcode: 0x66 ('f') 2496 * 2497 * offset (8 bit): opcode 2498 * 2499 * Equivalent to INIT_DONE on bios version 3 or greater. 2500 * For early bios versions, sets up the memory registers, using values 2501 * taken from the memory init table 2502 */ 2503 2504 /* no iexec->execute check by design */ 2505 2506 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4); 2507 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6; 2508 uint32_t reg, data; 2509 2510 if (bios->major_version > 2) 2511 return 0; 2512 2513 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd( 2514 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20); 2515 2516 if (bios->data[meminitoffs] & 1) 2517 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr; 2518 2519 for (reg = ROM32(bios->data[seqtbloffs]); 2520 reg != 0xffffffff; 2521 reg = ROM32(bios->data[seqtbloffs += 4])) { 2522 2523 switch (reg) { 2524 case NV04_PFB_PRE: 2525 data = NV04_PFB_PRE_CMD_PRECHARGE; 2526 break; 2527 case NV04_PFB_PAD: 2528 data = NV04_PFB_PAD_CKE_NORMAL; 2529 break; 2530 case NV04_PFB_REF: 2531 data = NV04_PFB_REF_CMD_REFRESH; 2532 break; 2533 default: 2534 data = ROM32(bios->data[meminitdata]); 2535 meminitdata += 4; 2536 if (data == 0xffffffff) 2537 continue; 2538 } 2539 2540 bios_wr32(bios, reg, data); 2541 } 2542 2543 return 1; 2544} 2545 2546static int 2547init_configure_clk(struct nvbios *bios, uint16_t offset, 2548 struct init_exec *iexec) 2549{ 2550 /* 2551 * INIT_CONFIGURE_CLK opcode: 0x67 ('g') 2552 * 2553 * offset (8 bit): opcode 2554 * 2555 * Equivalent to INIT_DONE on bios version 3 or greater. 2556 * For early bios versions, sets up the NVClk and MClk PLLs, using 2557 * values taken from the memory init table 2558 */ 2559 2560 /* no iexec->execute check by design */ 2561 2562 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4); 2563 int clock; 2564 2565 if (bios->major_version > 2) 2566 return 0; 2567 2568 clock = ROM16(bios->data[meminitoffs + 4]) * 10; 2569 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock); 2570 2571 clock = ROM16(bios->data[meminitoffs + 2]) * 10; 2572 if (bios->data[meminitoffs] & 1) /* DDR */ 2573 clock *= 2; 2574 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock); 2575 2576 return 1; 2577} 2578 2579static int 2580init_configure_preinit(struct nvbios *bios, uint16_t offset, 2581 struct init_exec *iexec) 2582{ 2583 /* 2584 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h') 2585 * 2586 * offset (8 bit): opcode 2587 * 2588 * Equivalent to INIT_DONE on bios version 3 or greater. 2589 * For early bios versions, does early init, loading ram and crystal 2590 * configuration from straps into CR3C 2591 */ 2592 2593 /* no iexec->execute check by design */ 2594 2595 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0); 2596 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & (1 << 6)); 2597 2598 if (bios->major_version > 2) 2599 return 0; 2600 2601 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, 2602 NV_CIO_CRE_SCRATCH4__INDEX, cr3c); 2603 2604 return 1; 2605} 2606 2607static int 2608init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2609{ 2610 /* 2611 * INIT_IO opcode: 0x69 ('i') 2612 * 2613 * offset (8 bit): opcode 2614 * offset + 1 (16 bit): CRTC port 2615 * offset + 3 (8 bit): mask 2616 * offset + 4 (8 bit): data 2617 * 2618 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port" 2619 */ 2620 2621 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2622 uint16_t crtcport = ROM16(bios->data[offset + 1]); 2623 uint8_t mask = bios->data[offset + 3]; 2624 uint8_t data = bios->data[offset + 4]; 2625 2626 if (!iexec->execute) 2627 return 5; 2628 2629 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n", 2630 offset, crtcport, mask, data); 2631 2632 /* 2633 * I have no idea what this does, but NVIDIA do this magic sequence 2634 * in the places where this INIT_IO happens.. 2635 */ 2636 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) { 2637 int i; 2638 2639 bios_wr32(bios, 0x614100, (bios_rd32( 2640 bios, 0x614100) & 0x0fffffff) | 0x00800000); 2641 2642 bios_wr32(bios, 0x00e18c, bios_rd32( 2643 bios, 0x00e18c) | 0x00020000); 2644 2645 bios_wr32(bios, 0x614900, (bios_rd32( 2646 bios, 0x614900) & 0x0fffffff) | 0x00800000); 2647 2648 bios_wr32(bios, 0x000200, bios_rd32( 2649 bios, 0x000200) & ~0x40000000); 2650 2651 mdelay(10); 2652 2653 bios_wr32(bios, 0x00e18c, bios_rd32( 2654 bios, 0x00e18c) & ~0x00020000); 2655 2656 bios_wr32(bios, 0x000200, bios_rd32( 2657 bios, 0x000200) | 0x40000000); 2658 2659 bios_wr32(bios, 0x614100, 0x00800018); 2660 bios_wr32(bios, 0x614900, 0x00800018); 2661 2662 mdelay(10); 2663 2664 bios_wr32(bios, 0x614100, 0x10000018); 2665 bios_wr32(bios, 0x614900, 0x10000018); 2666 2667 for (i = 0; i < 3; i++) 2668 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32( 2669 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0); 2670 2671 for (i = 0; i < 2; i++) 2672 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32( 2673 bios, 0x614300 + (i*0x800)) & 0xfffff0f0); 2674 2675 for (i = 0; i < 3; i++) 2676 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32( 2677 bios, 0x614380 + (i*0x800)) & 0xfffff0f0); 2678 2679 for (i = 0; i < 2; i++) 2680 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32( 2681 bios, 0x614200 + (i*0x800)) & 0xfffffff0); 2682 2683 for (i = 0; i < 2; i++) 2684 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32( 2685 bios, 0x614108 + (i*0x800)) & 0x0fffffff); 2686 return 5; 2687 } 2688 2689 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) | 2690 data); 2691 return 5; 2692} 2693 2694static int 2695init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2696{ 2697 /* 2698 * INIT_SUB opcode: 0x6B ('k') 2699 * 2700 * offset (8 bit): opcode 2701 * offset + 1 (8 bit): script number 2702 * 2703 * Execute script number "script number", as a subroutine 2704 */ 2705 2706 uint8_t sub = bios->data[offset + 1]; 2707 2708 if (!iexec->execute) 2709 return 2; 2710 2711 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub); 2712 2713 parse_init_table(bios, 2714 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]), 2715 iexec); 2716 2717 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub); 2718 2719 return 2; 2720} 2721 2722static int 2723init_ram_condition(struct nvbios *bios, uint16_t offset, 2724 struct init_exec *iexec) 2725{ 2726 /* 2727 * INIT_RAM_CONDITION opcode: 0x6D ('m') 2728 * 2729 * offset (8 bit): opcode 2730 * offset + 1 (8 bit): mask 2731 * offset + 2 (8 bit): cmpval 2732 * 2733 * Test if (NV04_PFB_BOOT_0 & "mask") equals "cmpval". 2734 * If condition not met skip subsequent opcodes until condition is 2735 * inverted (INIT_NOT), or we hit INIT_RESUME 2736 */ 2737 2738 uint8_t mask = bios->data[offset + 1]; 2739 uint8_t cmpval = bios->data[offset + 2]; 2740 uint8_t data; 2741 2742 if (!iexec->execute) 2743 return 3; 2744 2745 data = bios_rd32(bios, NV04_PFB_BOOT_0) & mask; 2746 2747 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n", 2748 offset, data, cmpval); 2749 2750 if (data == cmpval) 2751 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 2752 else { 2753 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 2754 iexec->execute = false; 2755 } 2756 2757 return 3; 2758} 2759 2760static int 2761init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2762{ 2763 /* 2764 * INIT_NV_REG opcode: 0x6E ('n') 2765 * 2766 * offset (8 bit): opcode 2767 * offset + 1 (32 bit): register 2768 * offset + 5 (32 bit): mask 2769 * offset + 9 (32 bit): data 2770 * 2771 * Assign ((REGVAL("register") & "mask") | "data") to "register" 2772 */ 2773 2774 uint32_t reg = ROM32(bios->data[offset + 1]); 2775 uint32_t mask = ROM32(bios->data[offset + 5]); 2776 uint32_t data = ROM32(bios->data[offset + 9]); 2777 2778 if (!iexec->execute) 2779 return 13; 2780 2781 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n", 2782 offset, reg, mask, data); 2783 2784 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data); 2785 2786 return 13; 2787} 2788 2789static int 2790init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2791{ 2792 /* 2793 * INIT_MACRO opcode: 0x6F ('o') 2794 * 2795 * offset (8 bit): opcode 2796 * offset + 1 (8 bit): macro number 2797 * 2798 * Look up macro index "macro number" in the macro index table. 2799 * The macro index table entry has 1 byte for the index in the macro 2800 * table, and 1 byte for the number of times to repeat the macro. 2801 * The macro table entry has 4 bytes for the register address and 2802 * 4 bytes for the value to write to that register 2803 */ 2804 2805 uint8_t macro_index_tbl_idx = bios->data[offset + 1]; 2806 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE); 2807 uint8_t macro_tbl_idx = bios->data[tmp]; 2808 uint8_t count = bios->data[tmp + 1]; 2809 uint32_t reg, data; 2810 int i; 2811 2812 if (!iexec->execute) 2813 return 2; 2814 2815 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, " 2816 "Count: 0x%02X\n", 2817 offset, macro_index_tbl_idx, macro_tbl_idx, count); 2818 2819 for (i = 0; i < count; i++) { 2820 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE; 2821 2822 reg = ROM32(bios->data[macroentryptr]); 2823 data = ROM32(bios->data[macroentryptr + 4]); 2824 2825 bios_wr32(bios, reg, data); 2826 } 2827 2828 return 2; 2829} 2830 2831static int 2832init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2833{ 2834 /* 2835 * INIT_DONE opcode: 0x71 ('q') 2836 * 2837 * offset (8 bit): opcode 2838 * 2839 * End the current script 2840 */ 2841 2842 /* mild retval abuse to stop parsing this table */ 2843 return 0; 2844} 2845 2846static int 2847init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2848{ 2849 /* 2850 * INIT_RESUME opcode: 0x72 ('r') 2851 * 2852 * offset (8 bit): opcode 2853 * 2854 * End the current execute / no-execute condition 2855 */ 2856 2857 if (iexec->execute) 2858 return 1; 2859 2860 iexec->execute = true; 2861 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset); 2862 2863 return 1; 2864} 2865 2866static int 2867init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2868{ 2869 /* 2870 * INIT_TIME opcode: 0x74 ('t') 2871 * 2872 * offset (8 bit): opcode 2873 * offset + 1 (16 bit): time 2874 * 2875 * Sleep for "time" microseconds. 2876 */ 2877 2878 unsigned time = ROM16(bios->data[offset + 1]); 2879 2880 if (!iexec->execute) 2881 return 3; 2882 2883 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n", 2884 offset, time); 2885 2886 if (time < 1000) 2887 udelay(time); 2888 else 2889 msleep((time + 900) / 1000); 2890 2891 return 3; 2892} 2893 2894static int 2895init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2896{ 2897 /* 2898 * INIT_CONDITION opcode: 0x75 ('u') 2899 * 2900 * offset (8 bit): opcode 2901 * offset + 1 (8 bit): condition number 2902 * 2903 * Check condition "condition number" in the condition table. 2904 * If condition not met skip subsequent opcodes until condition is 2905 * inverted (INIT_NOT), or we hit INIT_RESUME 2906 */ 2907 2908 uint8_t cond = bios->data[offset + 1]; 2909 2910 if (!iexec->execute) 2911 return 2; 2912 2913 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond); 2914 2915 if (bios_condition_met(bios, offset, cond)) 2916 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 2917 else { 2918 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 2919 iexec->execute = false; 2920 } 2921 2922 return 2; 2923} 2924 2925static int 2926init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2927{ 2928 /* 2929 * INIT_IO_CONDITION opcode: 0x76 2930 * 2931 * offset (8 bit): opcode 2932 * offset + 1 (8 bit): condition number 2933 * 2934 * Check condition "condition number" in the io condition table. 2935 * If condition not met skip subsequent opcodes until condition is 2936 * inverted (INIT_NOT), or we hit INIT_RESUME 2937 */ 2938 2939 uint8_t cond = bios->data[offset + 1]; 2940 2941 if (!iexec->execute) 2942 return 2; 2943 2944 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond); 2945 2946 if (io_condition_met(bios, offset, cond)) 2947 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 2948 else { 2949 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 2950 iexec->execute = false; 2951 } 2952 2953 return 2; 2954} 2955 2956static int 2957init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2958{ 2959 /* 2960 * INIT_INDEX_IO opcode: 0x78 ('x') 2961 * 2962 * offset (8 bit): opcode 2963 * offset + 1 (16 bit): CRTC port 2964 * offset + 3 (8 bit): CRTC index 2965 * offset + 4 (8 bit): mask 2966 * offset + 5 (8 bit): data 2967 * 2968 * Read value at index "CRTC index" on "CRTC port", AND with "mask", 2969 * OR with "data", write-back 2970 */ 2971 2972 uint16_t crtcport = ROM16(bios->data[offset + 1]); 2973 uint8_t crtcindex = bios->data[offset + 3]; 2974 uint8_t mask = bios->data[offset + 4]; 2975 uint8_t data = bios->data[offset + 5]; 2976 uint8_t value; 2977 2978 if (!iexec->execute) 2979 return 6; 2980 2981 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 2982 "Data: 0x%02X\n", 2983 offset, crtcport, crtcindex, mask, data); 2984 2985 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data; 2986 bios_idxprt_wr(bios, crtcport, crtcindex, value); 2987 2988 return 6; 2989} 2990 2991static int 2992init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2993{ 2994 /* 2995 * INIT_PLL opcode: 0x79 ('y') 2996 * 2997 * offset (8 bit): opcode 2998 * offset + 1 (32 bit): register 2999 * offset + 5 (16 bit): freq 3000 * 3001 * Set PLL register "register" to coefficients for frequency (10kHz) 3002 * "freq" 3003 */ 3004 3005 uint32_t reg = ROM32(bios->data[offset + 1]); 3006 uint16_t freq = ROM16(bios->data[offset + 5]); 3007 3008 if (!iexec->execute) 3009 return 7; 3010 3011 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq); 3012 3013 setPLL(bios, reg, freq * 10); 3014 3015 return 7; 3016} 3017 3018static int 3019init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3020{ 3021 /* 3022 * INIT_ZM_REG opcode: 0x7A ('z') 3023 * 3024 * offset (8 bit): opcode 3025 * offset + 1 (32 bit): register 3026 * offset + 5 (32 bit): value 3027 * 3028 * Assign "value" to "register" 3029 */ 3030 3031 uint32_t reg = ROM32(bios->data[offset + 1]); 3032 uint32_t value = ROM32(bios->data[offset + 5]); 3033 3034 if (!iexec->execute) 3035 return 9; 3036 3037 if (reg == 0x000200) 3038 value |= 1; 3039 3040 bios_wr32(bios, reg, value); 3041 3042 return 9; 3043} 3044 3045static int 3046init_ram_restrict_pll(struct nvbios *bios, uint16_t offset, 3047 struct init_exec *iexec) 3048{ 3049 /* 3050 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('') 3051 * 3052 * offset (8 bit): opcode 3053 * offset + 1 (8 bit): PLL type 3054 * offset + 2 (32 bit): frequency 0 3055 * 3056 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at 3057 * ram_restrict_table_ptr. The value read from there is used to select 3058 * a frequency from the table starting at 'frequency 0' to be 3059 * programmed into the PLL corresponding to 'type'. 3060 * 3061 * The PLL limits table on cards using this opcode has a mapping of 3062 * 'type' to the relevant registers. 3063 */ 3064 3065 struct drm_device *dev = bios->dev; 3066 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2; 3067 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap]; 3068 uint8_t type = bios->data[offset + 1]; 3069 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]); 3070 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry; 3071 int len = 2 + bios->ram_restrict_group_count * 4; 3072 int i; 3073 3074 if (!iexec->execute) 3075 return len; 3076 3077 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) { 3078 NV_ERROR(dev, "PLL limits table not version 3.x\n"); 3079 return len; /* deliberate, allow default clocks to remain */ 3080 } 3081 3082 entry = pll_limits + pll_limits[1]; 3083 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) { 3084 if (entry[0] == type) { 3085 uint32_t reg = ROM32(entry[3]); 3086 3087 BIOSLOG(bios, "0x%04X: " 3088 "Type %02x Reg 0x%08x Freq %dKHz\n", 3089 offset, type, reg, freq); 3090 3091 setPLL(bios, reg, freq); 3092 return len; 3093 } 3094 } 3095 3096 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type); 3097 return len; 3098} 3099 3100static int 3101init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3102{ 3103 /* 3104 * INIT_8C opcode: 0x8C ('') 3105 * 3106 * NOP so far.... 3107 * 3108 */ 3109 3110 return 1; 3111} 3112 3113static int 3114init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3115{ 3116 /* 3117 * INIT_8D opcode: 0x8D ('') 3118 * 3119 * NOP so far.... 3120 * 3121 */ 3122 3123 return 1; 3124} 3125 3126static int 3127init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3128{ 3129 /* 3130 * INIT_GPIO opcode: 0x8E ('') 3131 * 3132 * offset (8 bit): opcode 3133 * 3134 * Loop over all entries in the DCB GPIO table, and initialise 3135 * each GPIO according to various values listed in each entry 3136 */ 3137 3138 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 3139 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio; 3140 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c }; 3141 int i; 3142 3143 if (dev_priv->card_type != NV_50) { 3144 NV_ERROR(bios->dev, "INIT_GPIO on unsupported chipset\n"); 3145 return 1; 3146 } 3147 3148 if (!iexec->execute) 3149 return 1; 3150 3151 for (i = 0; i < bios->dcb.gpio.entries; i++) { 3152 struct dcb_gpio_entry *gpio = &bios->dcb.gpio.entry[i]; 3153 uint32_t r, s, v; 3154 3155 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, gpio->entry); 3156 3157 BIOSLOG(bios, "0x%04X: set gpio 0x%02x, state %d\n", 3158 offset, gpio->tag, gpio->state_default); 3159 if (bios->execute) 3160 pgpio->set(bios->dev, gpio->tag, gpio->state_default); 3161 3162 /* The NVIDIA binary driver doesn't appear to actually do 3163 * any of this, my VBIOS does however. 3164 */ 3165 /* Not a clue, needs de-magicing */ 3166 r = nv50_gpio_ctl[gpio->line >> 4]; 3167 s = (gpio->line & 0x0f); 3168 v = bios_rd32(bios, r) & ~(0x00010001 << s); 3169 switch ((gpio->entry & 0x06000000) >> 25) { 3170 case 1: 3171 v |= (0x00000001 << s); 3172 break; 3173 case 2: 3174 v |= (0x00010000 << s); 3175 break; 3176 default: 3177 break; 3178 } 3179 bios_wr32(bios, r, v); 3180 } 3181 3182 return 1; 3183} 3184 3185static int 3186init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset, 3187 struct init_exec *iexec) 3188{ 3189 /* 3190 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('') 3191 * 3192 * offset (8 bit): opcode 3193 * offset + 1 (32 bit): reg 3194 * offset + 5 (8 bit): regincrement 3195 * offset + 6 (8 bit): count 3196 * offset + 7 (32 bit): value 1,1 3197 * ... 3198 * 3199 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at 3200 * ram_restrict_table_ptr. The value read from here is 'n', and 3201 * "value 1,n" gets written to "reg". This repeats "count" times and on 3202 * each iteration 'm', "reg" increases by "regincrement" and 3203 * "value m,n" is used. The extent of n is limited by a number read 3204 * from the 'M' BIT table, herein called "blocklen" 3205 */ 3206 3207 uint32_t reg = ROM32(bios->data[offset + 1]); 3208 uint8_t regincrement = bios->data[offset + 5]; 3209 uint8_t count = bios->data[offset + 6]; 3210 uint32_t strap_ramcfg, data; 3211 /* previously set by 'M' BIT table */ 3212 uint16_t blocklen = bios->ram_restrict_group_count * 4; 3213 int len = 7 + count * blocklen; 3214 uint8_t index; 3215 int i; 3216 3217 /* critical! to know the length of the opcode */; 3218 if (!blocklen) { 3219 NV_ERROR(bios->dev, 3220 "0x%04X: Zero block length - has the M table " 3221 "been parsed?\n", offset); 3222 return -EINVAL; 3223 } 3224 3225 if (!iexec->execute) 3226 return len; 3227 3228 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf; 3229 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg]; 3230 3231 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, " 3232 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n", 3233 offset, reg, regincrement, count, strap_ramcfg, index); 3234 3235 for (i = 0; i < count; i++) { 3236 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]); 3237 3238 bios_wr32(bios, reg, data); 3239 3240 reg += regincrement; 3241 } 3242 3243 return len; 3244} 3245 3246static int 3247init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3248{ 3249 /* 3250 * INIT_COPY_ZM_REG opcode: 0x90 ('') 3251 * 3252 * offset (8 bit): opcode 3253 * offset + 1 (32 bit): src reg 3254 * offset + 5 (32 bit): dst reg 3255 * 3256 * Put contents of "src reg" into "dst reg" 3257 */ 3258 3259 uint32_t srcreg = ROM32(bios->data[offset + 1]); 3260 uint32_t dstreg = ROM32(bios->data[offset + 5]); 3261 3262 if (!iexec->execute) 3263 return 9; 3264 3265 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg)); 3266 3267 return 9; 3268} 3269 3270static int 3271init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset, 3272 struct init_exec *iexec) 3273{ 3274 /* 3275 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('') 3276 * 3277 * offset (8 bit): opcode 3278 * offset + 1 (32 bit): dst reg 3279 * offset + 5 (8 bit): count 3280 * offset + 6 (32 bit): data 1 3281 * ... 3282 * 3283 * For each of "count" values write "data n" to "dst reg" 3284 */ 3285 3286 uint32_t reg = ROM32(bios->data[offset + 1]); 3287 uint8_t count = bios->data[offset + 5]; 3288 int len = 6 + count * 4; 3289 int i; 3290 3291 if (!iexec->execute) 3292 return len; 3293 3294 for (i = 0; i < count; i++) { 3295 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]); 3296 bios_wr32(bios, reg, data); 3297 } 3298 3299 return len; 3300} 3301 3302static int 3303init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3304{ 3305 /* 3306 * INIT_RESERVED opcode: 0x92 ('') 3307 * 3308 * offset (8 bit): opcode 3309 * 3310 * Seemingly does nothing 3311 */ 3312 3313 return 1; 3314} 3315 3316static int 3317init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3318{ 3319 /* 3320 * INIT_96 opcode: 0x96 ('') 3321 * 3322 * offset (8 bit): opcode 3323 * offset + 1 (32 bit): sreg 3324 * offset + 5 (8 bit): sshift 3325 * offset + 6 (8 bit): smask 3326 * offset + 7 (8 bit): index 3327 * offset + 8 (32 bit): reg 3328 * offset + 12 (32 bit): mask 3329 * offset + 16 (8 bit): shift 3330 * 3331 */ 3332 3333 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2); 3334 uint32_t reg = ROM32(bios->data[offset + 8]); 3335 uint32_t mask = ROM32(bios->data[offset + 12]); 3336 uint32_t val; 3337 3338 val = bios_rd32(bios, ROM32(bios->data[offset + 1])); 3339 if (bios->data[offset + 5] < 0x80) 3340 val >>= bios->data[offset + 5]; 3341 else 3342 val <<= (0x100 - bios->data[offset + 5]); 3343 val &= bios->data[offset + 6]; 3344 3345 val = bios->data[ROM16(bios->data[xlatptr]) + val]; 3346 val <<= bios->data[offset + 16]; 3347 3348 if (!iexec->execute) 3349 return 17; 3350 3351 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val); 3352 return 17; 3353} 3354 3355static int 3356init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3357{ 3358 /* 3359 * INIT_97 opcode: 0x97 ('') 3360 * 3361 * offset (8 bit): opcode 3362 * offset + 1 (32 bit): register 3363 * offset + 5 (32 bit): mask 3364 * offset + 9 (32 bit): value 3365 * 3366 * Adds "value" to "register" preserving the fields specified 3367 * by "mask" 3368 */ 3369 3370 uint32_t reg = ROM32(bios->data[offset + 1]); 3371 uint32_t mask = ROM32(bios->data[offset + 5]); 3372 uint32_t add = ROM32(bios->data[offset + 9]); 3373 uint32_t val; 3374 3375 val = bios_rd32(bios, reg); 3376 val = (val & mask) | ((val + add) & ~mask); 3377 3378 if (!iexec->execute) 3379 return 13; 3380 3381 bios_wr32(bios, reg, val); 3382 return 13; 3383} 3384 3385static int 3386init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3387{ 3388 /* 3389 * INIT_AUXCH opcode: 0x98 ('') 3390 * 3391 * offset (8 bit): opcode 3392 * offset + 1 (32 bit): address 3393 * offset + 5 (8 bit): count 3394 * offset + 6 (8 bit): mask 0 3395 * offset + 7 (8 bit): data 0 3396 * ... 3397 * 3398 */ 3399 3400 struct drm_device *dev = bios->dev; 3401 struct nouveau_i2c_chan *auxch; 3402 uint32_t addr = ROM32(bios->data[offset + 1]); 3403 uint8_t count = bios->data[offset + 5]; 3404 int len = 6 + count * 2; 3405 int ret, i; 3406 3407 if (!bios->display.output) { 3408 NV_ERROR(dev, "INIT_AUXCH: no active output\n"); 3409 return len; 3410 } 3411 3412 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index); 3413 if (!auxch) { 3414 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n", 3415 bios->display.output->i2c_index); 3416 return len; 3417 } 3418 3419 if (!iexec->execute) 3420 return len; 3421 3422 offset += 6; 3423 for (i = 0; i < count; i++, offset += 2) { 3424 uint8_t data; 3425 3426 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1); 3427 if (ret) { 3428 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret); 3429 return len; 3430 } 3431 3432 data &= bios->data[offset + 0]; 3433 data |= bios->data[offset + 1]; 3434 3435 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1); 3436 if (ret) { 3437 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret); 3438 return len; 3439 } 3440 } 3441 3442 return len; 3443} 3444 3445static int 3446init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3447{ 3448 /* 3449 * INIT_ZM_AUXCH opcode: 0x99 ('') 3450 * 3451 * offset (8 bit): opcode 3452 * offset + 1 (32 bit): address 3453 * offset + 5 (8 bit): count 3454 * offset + 6 (8 bit): data 0 3455 * ... 3456 * 3457 */ 3458 3459 struct drm_device *dev = bios->dev; 3460 struct nouveau_i2c_chan *auxch; 3461 uint32_t addr = ROM32(bios->data[offset + 1]); 3462 uint8_t count = bios->data[offset + 5]; 3463 int len = 6 + count; 3464 int ret, i; 3465 3466 if (!bios->display.output) { 3467 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n"); 3468 return len; 3469 } 3470 3471 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index); 3472 if (!auxch) { 3473 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n", 3474 bios->display.output->i2c_index); 3475 return len; 3476 } 3477 3478 if (!iexec->execute) 3479 return len; 3480 3481 offset += 6; 3482 for (i = 0; i < count; i++, offset++) { 3483 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1); 3484 if (ret) { 3485 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret); 3486 return len; 3487 } 3488 } 3489 3490 return len; 3491} 3492 3493static struct init_tbl_entry itbl_entry[] = { 3494 /* command name , id , length , offset , mult , command handler */ 3495 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */ 3496 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog }, 3497 { "INIT_REPEAT" , 0x33, init_repeat }, 3498 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll }, 3499 { "INIT_END_REPEAT" , 0x36, init_end_repeat }, 3500 { "INIT_COPY" , 0x37, init_copy }, 3501 { "INIT_NOT" , 0x38, init_not }, 3502 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition }, 3503 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition }, 3504 { "INIT_OP_3B" , 0x3B, init_op_3b }, 3505 { "INIT_OP_3C" , 0x3C, init_op_3c }, 3506 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched }, 3507 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 }, 3508 { "INIT_PLL2" , 0x4B, init_pll2 }, 3509 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte }, 3510 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte }, 3511 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c }, 3512 { "INIT_TMDS" , 0x4F, init_tmds }, 3513 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group }, 3514 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch }, 3515 { "INIT_CR" , 0x52, init_cr }, 3516 { "INIT_ZM_CR" , 0x53, init_zm_cr }, 3517 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group }, 3518 { "INIT_CONDITION_TIME" , 0x56, init_condition_time }, 3519 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence }, 3520 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */ 3521 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct }, 3522 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg }, 3523 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io }, 3524 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem }, 3525 { "INIT_RESET" , 0x65, init_reset }, 3526 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem }, 3527 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk }, 3528 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit }, 3529 { "INIT_IO" , 0x69, init_io }, 3530 { "INIT_SUB" , 0x6B, init_sub }, 3531 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition }, 3532 { "INIT_NV_REG" , 0x6E, init_nv_reg }, 3533 { "INIT_MACRO" , 0x6F, init_macro }, 3534 { "INIT_DONE" , 0x71, init_done }, 3535 { "INIT_RESUME" , 0x72, init_resume }, 3536 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */ 3537 { "INIT_TIME" , 0x74, init_time }, 3538 { "INIT_CONDITION" , 0x75, init_condition }, 3539 { "INIT_IO_CONDITION" , 0x76, init_io_condition }, 3540 { "INIT_INDEX_IO" , 0x78, init_index_io }, 3541 { "INIT_PLL" , 0x79, init_pll }, 3542 { "INIT_ZM_REG" , 0x7A, init_zm_reg }, 3543 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll }, 3544 { "INIT_8C" , 0x8C, init_8c }, 3545 { "INIT_8D" , 0x8D, init_8d }, 3546 { "INIT_GPIO" , 0x8E, init_gpio }, 3547 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group }, 3548 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg }, 3549 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched }, 3550 { "INIT_RESERVED" , 0x92, init_reserved }, 3551 { "INIT_96" , 0x96, init_96 }, 3552 { "INIT_97" , 0x97, init_97 }, 3553 { "INIT_AUXCH" , 0x98, init_auxch }, 3554 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch }, 3555 { NULL , 0 , NULL } 3556}; 3557 3558#define MAX_TABLE_OPS 1000 3559 3560static int 3561parse_init_table(struct nvbios *bios, unsigned int offset, 3562 struct init_exec *iexec) 3563{ 3564 /* 3565 * Parses all commands in an init table. 3566 * 3567 * We start out executing all commands found in the init table. Some 3568 * opcodes may change the status of iexec->execute to SKIP, which will 3569 * cause the following opcodes to perform no operation until the value 3570 * is changed back to EXECUTE. 3571 */ 3572 3573 int count = 0, i, ret; 3574 uint8_t id; 3575 3576 /* 3577 * Loop until INIT_DONE causes us to break out of the loop 3578 * (or until offset > bios length just in case... ) 3579 * (and no more than MAX_TABLE_OPS iterations, just in case... ) 3580 */ 3581 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) { 3582 id = bios->data[offset]; 3583 3584 /* Find matching id in itbl_entry */ 3585 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++) 3586 ; 3587 3588 if (!itbl_entry[i].name) { 3589 NV_ERROR(bios->dev, 3590 "0x%04X: Init table command not found: " 3591 "0x%02X\n", offset, id); 3592 return -ENOENT; 3593 } 3594 3595 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset, 3596 itbl_entry[i].id, itbl_entry[i].name); 3597 3598 /* execute eventual command handler */ 3599 ret = (*itbl_entry[i].handler)(bios, offset, iexec); 3600 if (ret < 0) { 3601 NV_ERROR(bios->dev, "0x%04X: Failed parsing init " 3602 "table opcode: %s %d\n", offset, 3603 itbl_entry[i].name, ret); 3604 } 3605 3606 if (ret <= 0) 3607 break; 3608 3609 /* 3610 * Add the offset of the current command including all data 3611 * of that command. The offset will then be pointing on the 3612 * next op code. 3613 */ 3614 offset += ret; 3615 } 3616 3617 if (offset >= bios->length) 3618 NV_WARN(bios->dev, 3619 "Offset 0x%04X greater than known bios image length. " 3620 "Corrupt image?\n", offset); 3621 if (count >= MAX_TABLE_OPS) 3622 NV_WARN(bios->dev, 3623 "More than %d opcodes to a table is unlikely, " 3624 "is the bios image corrupt?\n", MAX_TABLE_OPS); 3625 3626 return 0; 3627} 3628 3629static void 3630parse_init_tables(struct nvbios *bios) 3631{ 3632 /* Loops and calls parse_init_table() for each present table. */ 3633 3634 int i = 0; 3635 uint16_t table; 3636 struct init_exec iexec = {true, false}; 3637 3638 if (bios->old_style_init) { 3639 if (bios->init_script_tbls_ptr) 3640 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec); 3641 if (bios->extra_init_script_tbl_ptr) 3642 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec); 3643 3644 return; 3645 } 3646 3647 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) { 3648 NV_INFO(bios->dev, 3649 "Parsing VBIOS init table %d at offset 0x%04X\n", 3650 i / 2, table); 3651 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table); 3652 3653 parse_init_table(bios, table, &iexec); 3654 i += 2; 3655 } 3656} 3657 3658static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk) 3659{ 3660 int compare_record_len, i = 0; 3661 uint16_t compareclk, scriptptr = 0; 3662 3663 if (bios->major_version < 5) /* pre BIT */ 3664 compare_record_len = 3; 3665 else 3666 compare_record_len = 4; 3667 3668 do { 3669 compareclk = ROM16(bios->data[clktable + compare_record_len * i]); 3670 if (pxclk >= compareclk * 10) { 3671 if (bios->major_version < 5) { 3672 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i]; 3673 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]); 3674 } else 3675 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]); 3676 break; 3677 } 3678 i++; 3679 } while (compareclk); 3680 3681 return scriptptr; 3682} 3683 3684static void 3685run_digital_op_script(struct drm_device *dev, uint16_t scriptptr, 3686 struct dcb_entry *dcbent, int head, bool dl) 3687{ 3688 struct drm_nouveau_private *dev_priv = dev->dev_private; 3689 struct nvbios *bios = &dev_priv->vbios; 3690 struct init_exec iexec = {true, false}; 3691 3692 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n", 3693 scriptptr); 3694 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44, 3695 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA); 3696 /* note: if dcb entries have been merged, index may be misleading */ 3697 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index); 3698 parse_init_table(bios, scriptptr, &iexec); 3699 3700 nv04_dfp_bind_head(dev, dcbent, head, dl); 3701} 3702 3703static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script) 3704{ 3705 struct drm_nouveau_private *dev_priv = dev->dev_private; 3706 struct nvbios *bios = &dev_priv->vbios; 3707 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0); 3708 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]); 3709 3710 if (!bios->fp.xlated_entry || !sub || !scriptofs) 3711 return -EINVAL; 3712 3713 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link); 3714 3715 if (script == LVDS_PANEL_OFF) { 3716 /* off-on delay in ms */ 3717 msleep(ROM16(bios->data[bios->fp.xlated_entry + 7])); 3718 } 3719#ifdef __powerpc__ 3720 /* Powerbook specific quirks */ 3721 if ((dev->pci_device & 0xffff) == 0x0179 || 3722 (dev->pci_device & 0xffff) == 0x0189 || 3723 (dev->pci_device & 0xffff) == 0x0329) { 3724 if (script == LVDS_RESET) { 3725 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72); 3726 3727 } else if (script == LVDS_PANEL_ON) { 3728 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL, 3729 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL) 3730 | (1 << 31)); 3731 bios_wr32(bios, NV_PCRTC_GPIO_EXT, 3732 bios_rd32(bios, NV_PCRTC_GPIO_EXT) | 1); 3733 3734 } else if (script == LVDS_PANEL_OFF) { 3735 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL, 3736 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL) 3737 & ~(1 << 31)); 3738 bios_wr32(bios, NV_PCRTC_GPIO_EXT, 3739 bios_rd32(bios, NV_PCRTC_GPIO_EXT) & ~3); 3740 } 3741 } 3742#endif 3743 3744 return 0; 3745} 3746 3747static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk) 3748{ 3749 /* 3750 * The BIT LVDS table's header has the information to setup the 3751 * necessary registers. Following the standard 4 byte header are: 3752 * A bitmask byte and a dual-link transition pxclk value for use in 3753 * selecting the init script when not using straps; 4 script pointers 3754 * for panel power, selected by output and on/off; and 8 table pointers 3755 * for panel init, the needed one determined by output, and bits in the 3756 * conf byte. These tables are similar to the TMDS tables, consisting 3757 * of a list of pxclks and script pointers. 3758 */ 3759 struct drm_nouveau_private *dev_priv = dev->dev_private; 3760 struct nvbios *bios = &dev_priv->vbios; 3761 unsigned int outputset = (dcbent->or == 4) ? 1 : 0; 3762 uint16_t scriptptr = 0, clktable; 3763 3764 /* 3765 * For now we assume version 3.0 table - g80 support will need some 3766 * changes 3767 */ 3768 3769 switch (script) { 3770 case LVDS_INIT: 3771 return -ENOSYS; 3772 case LVDS_BACKLIGHT_ON: 3773 case LVDS_PANEL_ON: 3774 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]); 3775 break; 3776 case LVDS_BACKLIGHT_OFF: 3777 case LVDS_PANEL_OFF: 3778 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]); 3779 break; 3780 case LVDS_RESET: 3781 clktable = bios->fp.lvdsmanufacturerpointer + 15; 3782 if (dcbent->or == 4) 3783 clktable += 8; 3784 3785 if (dcbent->lvdsconf.use_straps_for_mode) { 3786 if (bios->fp.dual_link) 3787 clktable += 4; 3788 if (bios->fp.if_is_24bit) 3789 clktable += 2; 3790 } else { 3791 /* using EDID */ 3792 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1; 3793 3794 if (bios->fp.dual_link) { 3795 clktable += 4; 3796 cmpval_24bit <<= 1; 3797 } 3798 3799 if (bios->fp.strapless_is_24bit & cmpval_24bit) 3800 clktable += 2; 3801 } 3802 3803 clktable = ROM16(bios->data[clktable]); 3804 if (!clktable) { 3805 NV_ERROR(dev, "Pixel clock comparison table not found\n"); 3806 return -ENOENT; 3807 } 3808 scriptptr = clkcmptable(bios, clktable, pxclk); 3809 } 3810 3811 if (!scriptptr) { 3812 NV_ERROR(dev, "LVDS output init script not found\n"); 3813 return -ENOENT; 3814 } 3815 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link); 3816 3817 return 0; 3818} 3819 3820int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk) 3821{ 3822 /* 3823 * LVDS operations are multiplexed in an effort to present a single API 3824 * which works with two vastly differing underlying structures. 3825 * This acts as the demux 3826 */ 3827 3828 struct drm_nouveau_private *dev_priv = dev->dev_private; 3829 struct nvbios *bios = &dev_priv->vbios; 3830 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer]; 3831 uint32_t sel_clk_binding, sel_clk; 3832 int ret; 3833 3834 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver || 3835 (lvds_ver >= 0x30 && script == LVDS_INIT)) 3836 return 0; 3837 3838 if (!bios->fp.lvds_init_run) { 3839 bios->fp.lvds_init_run = true; 3840 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk); 3841 } 3842 3843 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change) 3844 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk); 3845 if (script == LVDS_RESET && bios->fp.power_off_for_reset) 3846 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk); 3847 3848 NV_TRACE(dev, "Calling LVDS script %d:\n", script); 3849 3850 /* don't let script change pll->head binding */ 3851 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000; 3852 3853 if (lvds_ver < 0x30) 3854 ret = call_lvds_manufacturer_script(dev, dcbent, head, script); 3855 else 3856 ret = run_lvds_table(dev, dcbent, head, script, pxclk); 3857 3858 bios->fp.last_script_invoc = (script << 1 | head); 3859 3860 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; 3861 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); 3862 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */ 3863 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0); 3864 3865 return ret; 3866} 3867 3868struct lvdstableheader { 3869 uint8_t lvds_ver, headerlen, recordlen; 3870}; 3871 3872static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth) 3873{ 3874 /* 3875 * BMP version (0xa) LVDS table has a simple header of version and 3876 * record length. The BIT LVDS table has the typical BIT table header: 3877 * version byte, header length byte, record length byte, and a byte for 3878 * the maximum number of records that can be held in the table. 3879 */ 3880 3881 uint8_t lvds_ver, headerlen, recordlen; 3882 3883 memset(lth, 0, sizeof(struct lvdstableheader)); 3884 3885 if (bios->fp.lvdsmanufacturerpointer == 0x0) { 3886 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n"); 3887 return -EINVAL; 3888 } 3889 3890 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer]; 3891 3892 switch (lvds_ver) { 3893 case 0x0a: /* pre NV40 */ 3894 headerlen = 2; 3895 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 3896 break; 3897 case 0x30: /* NV4x */ 3898 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 3899 if (headerlen < 0x1f) { 3900 NV_ERROR(dev, "LVDS table header not understood\n"); 3901 return -EINVAL; 3902 } 3903 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2]; 3904 break; 3905 case 0x40: /* G80/G90 */ 3906 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 3907 if (headerlen < 0x7) { 3908 NV_ERROR(dev, "LVDS table header not understood\n"); 3909 return -EINVAL; 3910 } 3911 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2]; 3912 break; 3913 default: 3914 NV_ERROR(dev, 3915 "LVDS table revision %d.%d not currently supported\n", 3916 lvds_ver >> 4, lvds_ver & 0xf); 3917 return -ENOSYS; 3918 } 3919 3920 lth->lvds_ver = lvds_ver; 3921 lth->headerlen = headerlen; 3922 lth->recordlen = recordlen; 3923 3924 return 0; 3925} 3926 3927static int 3928get_fp_strap(struct drm_device *dev, struct nvbios *bios) 3929{ 3930 struct drm_nouveau_private *dev_priv = dev->dev_private; 3931 3932 /* 3933 * The fp strap is normally dictated by the "User Strap" in 3934 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the 3935 * Internal_Flags struct at 0x48 is set, the user strap gets overriden 3936 * by the PCI subsystem ID during POST, but not before the previous user 3937 * strap has been committed to CR58 for CR57=0xf on head A, which may be 3938 * read and used instead 3939 */ 3940 3941 if (bios->major_version < 5 && bios->data[0x48] & 0x4) 3942 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf; 3943 3944 if (dev_priv->card_type >= NV_50) 3945 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf; 3946 else 3947 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf; 3948} 3949 3950static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios) 3951{ 3952 uint8_t *fptable; 3953 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex; 3954 int ret, ofs, fpstrapping; 3955 struct lvdstableheader lth; 3956 3957 if (bios->fp.fptablepointer == 0x0) { 3958 /* Apple cards don't have the fp table; the laptops use DDC */ 3959 /* The table is also missing on some x86 IGPs */ 3960#ifndef __powerpc__ 3961 NV_ERROR(dev, "Pointer to flat panel table invalid\n"); 3962#endif 3963 bios->digital_min_front_porch = 0x4b; 3964 return 0; 3965 } 3966 3967 fptable = &bios->data[bios->fp.fptablepointer]; 3968 fptable_ver = fptable[0]; 3969 3970 switch (fptable_ver) { 3971 /* 3972 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no 3973 * version field, and miss one of the spread spectrum/PWM bytes. 3974 * This could affect early GF2Go parts (not seen any appropriate ROMs 3975 * though). Here we assume that a version of 0x05 matches this case 3976 * (combining with a BMP version check would be better), as the 3977 * common case for the panel type field is 0x0005, and that is in 3978 * fact what we are reading the first byte of. 3979 */ 3980 case 0x05: /* some NV10, 11, 15, 16 */ 3981 recordlen = 42; 3982 ofs = -1; 3983 break; 3984 case 0x10: /* some NV15/16, and NV11+ */ 3985 recordlen = 44; 3986 ofs = 0; 3987 break; 3988 case 0x20: /* NV40+ */ 3989 headerlen = fptable[1]; 3990 recordlen = fptable[2]; 3991 fpentries = fptable[3]; 3992 /* 3993 * fptable[4] is the minimum 3994 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap 3995 */ 3996 bios->digital_min_front_porch = fptable[4]; 3997 ofs = -7; 3998 break; 3999 default: 4000 NV_ERROR(dev, 4001 "FP table revision %d.%d not currently supported\n", 4002 fptable_ver >> 4, fptable_ver & 0xf); 4003 return -ENOSYS; 4004 } 4005 4006 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */ 4007 return 0; 4008 4009 ret = parse_lvds_manufacturer_table_header(dev, bios, <h); 4010 if (ret) 4011 return ret; 4012 4013 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) { 4014 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer + 4015 lth.headerlen + 1; 4016 bios->fp.xlatwidth = lth.recordlen; 4017 } 4018 if (bios->fp.fpxlatetableptr == 0x0) { 4019 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n"); 4020 return -EINVAL; 4021 } 4022 4023 fpstrapping = get_fp_strap(dev, bios); 4024 4025 fpindex = bios->data[bios->fp.fpxlatetableptr + 4026 fpstrapping * bios->fp.xlatwidth]; 4027 4028 if (fpindex > fpentries) { 4029 NV_ERROR(dev, "Bad flat panel table index\n"); 4030 return -ENOENT; 4031 } 4032 4033 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */ 4034 if (lth.lvds_ver > 0x10) 4035 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf; 4036 4037 /* 4038 * If either the strap or xlated fpindex value are 0xf there is no 4039 * panel using a strap-derived bios mode present. this condition 4040 * includes, but is different from, the DDC panel indicator above 4041 */ 4042 if (fpstrapping == 0xf || fpindex == 0xf) 4043 return 0; 4044 4045 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen + 4046 recordlen * fpindex + ofs; 4047 4048 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n", 4049 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1, 4050 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1, 4051 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10); 4052 4053 return 0; 4054} 4055 4056bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode) 4057{ 4058 struct drm_nouveau_private *dev_priv = dev->dev_private; 4059 struct nvbios *bios = &dev_priv->vbios; 4060 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr]; 4061 4062 if (!mode) /* just checking whether we can produce a mode */ 4063 return bios->fp.mode_ptr; 4064 4065 memset(mode, 0, sizeof(struct drm_display_mode)); 4066 /* 4067 * For version 1.0 (version in byte 0): 4068 * bytes 1-2 are "panel type", including bits on whether Colour/mono, 4069 * single/dual link, and type (TFT etc.) 4070 * bytes 3-6 are bits per colour in RGBX 4071 */ 4072 mode->clock = ROM16(mode_entry[7]) * 10; 4073 /* bytes 9-10 is HActive */ 4074 mode->hdisplay = ROM16(mode_entry[11]) + 1; 4075 /* 4076 * bytes 13-14 is HValid Start 4077 * bytes 15-16 is HValid End 4078 */ 4079 mode->hsync_start = ROM16(mode_entry[17]) + 1; 4080 mode->hsync_end = ROM16(mode_entry[19]) + 1; 4081 mode->htotal = ROM16(mode_entry[21]) + 1; 4082 /* bytes 23-24, 27-30 similarly, but vertical */ 4083 mode->vdisplay = ROM16(mode_entry[25]) + 1; 4084 mode->vsync_start = ROM16(mode_entry[31]) + 1; 4085 mode->vsync_end = ROM16(mode_entry[33]) + 1; 4086 mode->vtotal = ROM16(mode_entry[35]) + 1; 4087 mode->flags |= (mode_entry[37] & 0x10) ? 4088 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4089 mode->flags |= (mode_entry[37] & 0x1) ? 4090 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4091 /* 4092 * bytes 38-39 relate to spread spectrum settings 4093 * bytes 40-43 are something to do with PWM 4094 */ 4095 4096 mode->status = MODE_OK; 4097 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; 4098 drm_mode_set_name(mode); 4099 return bios->fp.mode_ptr; 4100} 4101 4102int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit) 4103{ 4104 /* 4105 * The LVDS table header is (mostly) described in 4106 * parse_lvds_manufacturer_table_header(): the BIT header additionally 4107 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if 4108 * straps are not being used for the panel, this specifies the frequency 4109 * at which modes should be set up in the dual link style. 4110 * 4111 * Following the header, the BMP (ver 0xa) table has several records, 4112 * indexed by a separate xlat table, indexed in turn by the fp strap in 4113 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script 4114 * numbers for use by INIT_SUB which controlled panel init and power, 4115 * and finally a dword of ms to sleep between power off and on 4116 * operations. 4117 * 4118 * In the BIT versions, the table following the header serves as an 4119 * integrated config and xlat table: the records in the table are 4120 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has 4121 * two bytes - the first as a config byte, the second for indexing the 4122 * fp mode table pointed to by the BIT 'D' table 4123 * 4124 * DDC is not used until after card init, so selecting the correct table 4125 * entry and setting the dual link flag for EDID equipped panels, 4126 * requiring tests against the native-mode pixel clock, cannot be done 4127 * until later, when this function should be called with non-zero pxclk 4128 */ 4129 struct drm_nouveau_private *dev_priv = dev->dev_private; 4130 struct nvbios *bios = &dev_priv->vbios; 4131 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0; 4132 struct lvdstableheader lth; 4133 uint16_t lvdsofs; 4134 int ret, chip_version = bios->chip_version; 4135 4136 ret = parse_lvds_manufacturer_table_header(dev, bios, <h); 4137 if (ret) 4138 return ret; 4139 4140 switch (lth.lvds_ver) { 4141 case 0x0a: /* pre NV40 */ 4142 lvdsmanufacturerindex = bios->data[ 4143 bios->fp.fpxlatemanufacturertableptr + 4144 fpstrapping]; 4145 4146 /* we're done if this isn't the EDID panel case */ 4147 if (!pxclk) 4148 break; 4149 4150 if (chip_version < 0x25) { 4151 /* nv17 behaviour 4152 * 4153 * It seems the old style lvds script pointer is reused 4154 * to select 18/24 bit colour depth for EDID panels. 4155 */ 4156 lvdsmanufacturerindex = 4157 (bios->legacy.lvds_single_a_script_ptr & 1) ? 4158 2 : 0; 4159 if (pxclk >= bios->fp.duallink_transition_clk) 4160 lvdsmanufacturerindex++; 4161 } else if (chip_version < 0x30) { 4162 /* nv28 behaviour (off-chip encoder) 4163 * 4164 * nv28 does a complex dance of first using byte 121 of 4165 * the EDID to choose the lvdsmanufacturerindex, then 4166 * later attempting to match the EDID manufacturer and 4167 * product IDs in a table (signature 'pidt' (panel id 4168 * table?)), setting an lvdsmanufacturerindex of 0 and 4169 * an fp strap of the match index (or 0xf if none) 4170 */ 4171 lvdsmanufacturerindex = 0; 4172 } else { 4173 /* nv31, nv34 behaviour */ 4174 lvdsmanufacturerindex = 0; 4175 if (pxclk >= bios->fp.duallink_transition_clk) 4176 lvdsmanufacturerindex = 2; 4177 if (pxclk >= 140000) 4178 lvdsmanufacturerindex = 3; 4179 } 4180 4181 /* 4182 * nvidia set the high nibble of (cr57=f, cr58) to 4183 * lvdsmanufacturerindex in this case; we don't 4184 */ 4185 break; 4186 case 0x30: /* NV4x */ 4187 case 0x40: /* G80/G90 */ 4188 lvdsmanufacturerindex = fpstrapping; 4189 break; 4190 default: 4191 NV_ERROR(dev, "LVDS table revision not currently supported\n"); 4192 return -ENOSYS; 4193 } 4194 4195 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex; 4196 switch (lth.lvds_ver) { 4197 case 0x0a: 4198 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1; 4199 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2; 4200 bios->fp.dual_link = bios->data[lvdsofs] & 4; 4201 bios->fp.link_c_increment = bios->data[lvdsofs] & 8; 4202 *if_is_24bit = bios->data[lvdsofs] & 16; 4203 break; 4204 case 0x30: 4205 case 0x40: 4206 /* 4207 * No sign of the "power off for reset" or "reset for panel 4208 * on" bits, but it's safer to assume we should 4209 */ 4210 bios->fp.power_off_for_reset = true; 4211 bios->fp.reset_after_pclk_change = true; 4212 4213 /* 4214 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is 4215 * over-written, and if_is_24bit isn't used 4216 */ 4217 bios->fp.dual_link = bios->data[lvdsofs] & 1; 4218 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2; 4219 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4]; 4220 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10; 4221 break; 4222 } 4223 4224 /* Dell Latitude D620 reports a too-high value for the dual-link 4225 * transition freq, causing us to program the panel incorrectly. 4226 * 4227 * It doesn't appear the VBIOS actually uses its transition freq 4228 * (90000kHz), instead it uses the "Number of LVDS channels" field 4229 * out of the panel ID structure (http://www.spwg.org/). 4230 * 4231 * For the moment, a quirk will do :) 4232 */ 4233 if ((dev->pdev->device == 0x01d7) && 4234 (dev->pdev->subsystem_vendor == 0x1028) && 4235 (dev->pdev->subsystem_device == 0x01c2)) { 4236 bios->fp.duallink_transition_clk = 80000; 4237 } 4238 4239 /* set dual_link flag for EDID case */ 4240 if (pxclk && (chip_version < 0x25 || chip_version > 0x28)) 4241 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk); 4242 4243 *dl = bios->fp.dual_link; 4244 4245 return 0; 4246} 4247 4248static uint8_t * 4249bios_output_config_match(struct drm_device *dev, struct dcb_entry *dcbent, 4250 uint16_t record, int record_len, int record_nr, 4251 bool match_link) 4252{ 4253 struct drm_nouveau_private *dev_priv = dev->dev_private; 4254 struct nvbios *bios = &dev_priv->vbios; 4255 uint32_t entry; 4256 uint16_t table; 4257 int i, v; 4258 4259 switch (dcbent->type) { 4260 case OUTPUT_TMDS: 4261 case OUTPUT_LVDS: 4262 case OUTPUT_DP: 4263 break; 4264 default: 4265 match_link = false; 4266 break; 4267 } 4268 4269 for (i = 0; i < record_nr; i++, record += record_len) { 4270 table = ROM16(bios->data[record]); 4271 if (!table) 4272 continue; 4273 entry = ROM32(bios->data[table]); 4274 4275 if (match_link) { 4276 v = (entry & 0x00c00000) >> 22; 4277 if (!(v & dcbent->sorconf.link)) 4278 continue; 4279 } 4280 4281 v = (entry & 0x000f0000) >> 16; 4282 if (!(v & dcbent->or)) 4283 continue; 4284 4285 v = (entry & 0x000000f0) >> 4; 4286 if (v != dcbent->location) 4287 continue; 4288 4289 v = (entry & 0x0000000f); 4290 if (v != dcbent->type) 4291 continue; 4292 4293 return &bios->data[table]; 4294 } 4295 4296 return NULL; 4297} 4298 4299void * 4300nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent, 4301 int *length) 4302{ 4303 struct drm_nouveau_private *dev_priv = dev->dev_private; 4304 struct nvbios *bios = &dev_priv->vbios; 4305 uint8_t *table; 4306 4307 if (!bios->display.dp_table_ptr) { 4308 NV_ERROR(dev, "No pointer to DisplayPort table\n"); 4309 return NULL; 4310 } 4311 table = &bios->data[bios->display.dp_table_ptr]; 4312 4313 if (table[0] != 0x20 && table[0] != 0x21) { 4314 NV_ERROR(dev, "DisplayPort table version 0x%02x unknown\n", 4315 table[0]); 4316 return NULL; 4317 } 4318 4319 *length = table[4]; 4320 return bios_output_config_match(dev, dcbent, 4321 bios->display.dp_table_ptr + table[1], 4322 table[2], table[3], table[0] >= 0x21); 4323} 4324 4325int 4326nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent, 4327 uint32_t sub, int pxclk) 4328{ 4329 /* 4330 * The display script table is located by the BIT 'U' table. 4331 * 4332 * It contains an array of pointers to various tables describing 4333 * a particular output type. The first 32-bits of the output 4334 * tables contains similar information to a DCB entry, and is 4335 * used to decide whether that particular table is suitable for 4336 * the output you want to access. 4337 * 4338 * The "record header length" field here seems to indicate the 4339 * offset of the first configuration entry in the output tables. 4340 * This is 10 on most cards I've seen, but 12 has been witnessed 4341 * on DP cards, and there's another script pointer within the 4342 * header. 4343 * 4344 * offset + 0 ( 8 bits): version 4345 * offset + 1 ( 8 bits): header length 4346 * offset + 2 ( 8 bits): record length 4347 * offset + 3 ( 8 bits): number of records 4348 * offset + 4 ( 8 bits): record header length 4349 * offset + 5 (16 bits): pointer to first output script table 4350 */ 4351 4352 struct drm_nouveau_private *dev_priv = dev->dev_private; 4353 struct nvbios *bios = &dev_priv->vbios; 4354 uint8_t *table = &bios->data[bios->display.script_table_ptr]; 4355 uint8_t *otable = NULL; 4356 uint16_t script; 4357 int i = 0; 4358 4359 if (!bios->display.script_table_ptr) { 4360 NV_ERROR(dev, "No pointer to output script table\n"); 4361 return 1; 4362 } 4363 4364 /* 4365 * Nothing useful has been in any of the pre-2.0 tables I've seen, 4366 * so until they are, we really don't need to care. 4367 */ 4368 if (table[0] < 0x20) 4369 return 1; 4370 4371 if (table[0] != 0x20 && table[0] != 0x21) { 4372 NV_ERROR(dev, "Output script table version 0x%02x unknown\n", 4373 table[0]); 4374 return 1; 4375 } 4376 4377 /* 4378 * The output script tables describing a particular output type 4379 * look as follows: 4380 * 4381 * offset + 0 (32 bits): output this table matches (hash of DCB) 4382 * offset + 4 ( 8 bits): unknown 4383 * offset + 5 ( 8 bits): number of configurations 4384 * offset + 6 (16 bits): pointer to some script 4385 * offset + 8 (16 bits): pointer to some script 4386 * 4387 * headerlen == 10 4388 * offset + 10 : configuration 0 4389 * 4390 * headerlen == 12 4391 * offset + 10 : pointer to some script 4392 * offset + 12 : configuration 0 4393 * 4394 * Each config entry is as follows: 4395 * 4396 * offset + 0 (16 bits): unknown, assumed to be a match value 4397 * offset + 2 (16 bits): pointer to script table (clock set?) 4398 * offset + 4 (16 bits): pointer to script table (reset?) 4399 * 4400 * There doesn't appear to be a count value to say how many 4401 * entries exist in each script table, instead, a 0 value in 4402 * the first 16-bit word seems to indicate both the end of the 4403 * list and the default entry. The second 16-bit word in the 4404 * script tables is a pointer to the script to execute. 4405 */ 4406 4407 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n", 4408 dcbent->type, dcbent->location, dcbent->or); 4409 otable = bios_output_config_match(dev, dcbent, table[1] + 4410 bios->display.script_table_ptr, 4411 table[2], table[3], table[0] >= 0x21); 4412 if (!otable) { 4413 NV_ERROR(dev, "Couldn't find matching output script table\n"); 4414 return 1; 4415 } 4416 4417 if (pxclk < -2 || pxclk > 0) { 4418 /* Try to find matching script table entry */ 4419 for (i = 0; i < otable[5]; i++) { 4420 if (ROM16(otable[table[4] + i*6]) == sub) 4421 break; 4422 } 4423 4424 if (i == otable[5]) { 4425 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, " 4426 "using first\n", 4427 sub, dcbent->type, dcbent->or); 4428 i = 0; 4429 } 4430 } 4431 4432 if (pxclk == 0) { 4433 script = ROM16(otable[6]); 4434 if (!script) { 4435 NV_DEBUG_KMS(dev, "output script 0 not found\n"); 4436 return 1; 4437 } 4438 4439 NV_TRACE(dev, "0x%04X: parsing output script 0\n", script); 4440 nouveau_bios_run_init_table(dev, script, dcbent); 4441 } else 4442 if (pxclk == -1) { 4443 script = ROM16(otable[8]); 4444 if (!script) { 4445 NV_DEBUG_KMS(dev, "output script 1 not found\n"); 4446 return 1; 4447 } 4448 4449 NV_TRACE(dev, "0x%04X: parsing output script 1\n", script); 4450 nouveau_bios_run_init_table(dev, script, dcbent); 4451 } else 4452 if (pxclk == -2) { 4453 if (table[4] >= 12) 4454 script = ROM16(otable[10]); 4455 else 4456 script = 0; 4457 if (!script) { 4458 NV_DEBUG_KMS(dev, "output script 2 not found\n"); 4459 return 1; 4460 } 4461 4462 NV_TRACE(dev, "0x%04X: parsing output script 2\n", script); 4463 nouveau_bios_run_init_table(dev, script, dcbent); 4464 } else 4465 if (pxclk > 0) { 4466 script = ROM16(otable[table[4] + i*6 + 2]); 4467 if (script) 4468 script = clkcmptable(bios, script, pxclk); 4469 if (!script) { 4470 NV_ERROR(dev, "clock script 0 not found\n"); 4471 return 1; 4472 } 4473 4474 NV_TRACE(dev, "0x%04X: parsing clock script 0\n", script); 4475 nouveau_bios_run_init_table(dev, script, dcbent); 4476 } else 4477 if (pxclk < 0) { 4478 script = ROM16(otable[table[4] + i*6 + 4]); 4479 if (script) 4480 script = clkcmptable(bios, script, -pxclk); 4481 if (!script) { 4482 NV_DEBUG_KMS(dev, "clock script 1 not found\n"); 4483 return 1; 4484 } 4485 4486 NV_TRACE(dev, "0x%04X: parsing clock script 1\n", script); 4487 nouveau_bios_run_init_table(dev, script, dcbent); 4488 } 4489 4490 return 0; 4491} 4492 4493 4494int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk) 4495{ 4496 /* 4497 * the pxclk parameter is in kHz 4498 * 4499 * This runs the TMDS regs setting code found on BIT bios cards 4500 * 4501 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and 4502 * ffs(or) == 3, use the second. 4503 */ 4504 4505 struct drm_nouveau_private *dev_priv = dev->dev_private; 4506 struct nvbios *bios = &dev_priv->vbios; 4507 int cv = bios->chip_version; 4508 uint16_t clktable = 0, scriptptr; 4509 uint32_t sel_clk_binding, sel_clk; 4510 4511 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */ 4512 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 && 4513 dcbent->location != DCB_LOC_ON_CHIP) 4514 return 0; 4515 4516 switch (ffs(dcbent->or)) { 4517 case 1: 4518 clktable = bios->tmds.output0_script_ptr; 4519 break; 4520 case 2: 4521 case 3: 4522 clktable = bios->tmds.output1_script_ptr; 4523 break; 4524 } 4525 4526 if (!clktable) { 4527 NV_ERROR(dev, "Pixel clock comparison table not found\n"); 4528 return -EINVAL; 4529 } 4530 4531 scriptptr = clkcmptable(bios, clktable, pxclk); 4532 4533 if (!scriptptr) { 4534 NV_ERROR(dev, "TMDS output init script not found\n"); 4535 return -ENOENT; 4536 } 4537 4538 /* don't let script change pll->head binding */ 4539 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000; 4540 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000); 4541 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; 4542 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); 4543 4544 return 0; 4545} 4546 4547int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim) 4548{ 4549 /* 4550 * PLL limits table 4551 * 4552 * Version 0x10: NV30, NV31 4553 * One byte header (version), one record of 24 bytes 4554 * Version 0x11: NV36 - Not implemented 4555 * Seems to have same record style as 0x10, but 3 records rather than 1 4556 * Version 0x20: Found on Geforce 6 cards 4557 * Trivial 4 byte BIT header. 31 (0x1f) byte record length 4558 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards 4559 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record 4560 * length in general, some (integrated) have an extra configuration byte 4561 * Version 0x30: Found on Geforce 8, separates the register mapping 4562 * from the limits tables. 4563 */ 4564 4565 struct drm_nouveau_private *dev_priv = dev->dev_private; 4566 struct nvbios *bios = &dev_priv->vbios; 4567 int cv = bios->chip_version, pllindex = 0; 4568 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0; 4569 uint32_t crystal_strap_mask, crystal_straps; 4570 4571 if (!bios->pll_limit_tbl_ptr) { 4572 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 || 4573 cv >= 0x40) { 4574 NV_ERROR(dev, "Pointer to PLL limits table invalid\n"); 4575 return -EINVAL; 4576 } 4577 } else 4578 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr]; 4579 4580 crystal_strap_mask = 1 << 6; 4581 /* open coded dev->twoHeads test */ 4582 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20) 4583 crystal_strap_mask |= 1 << 22; 4584 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) & 4585 crystal_strap_mask; 4586 4587 switch (pll_lim_ver) { 4588 /* 4589 * We use version 0 to indicate a pre limit table bios (single stage 4590 * pll) and load the hard coded limits instead. 4591 */ 4592 case 0: 4593 break; 4594 case 0x10: 4595 case 0x11: 4596 /* 4597 * Strictly v0x11 has 3 entries, but the last two don't seem 4598 * to get used. 4599 */ 4600 headerlen = 1; 4601 recordlen = 0x18; 4602 entries = 1; 4603 pllindex = 0; 4604 break; 4605 case 0x20: 4606 case 0x21: 4607 case 0x30: 4608 case 0x40: 4609 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1]; 4610 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2]; 4611 entries = bios->data[bios->pll_limit_tbl_ptr + 3]; 4612 break; 4613 default: 4614 NV_ERROR(dev, "PLL limits table revision 0x%X not currently " 4615 "supported\n", pll_lim_ver); 4616 return -ENOSYS; 4617 } 4618 4619 /* initialize all members to zero */ 4620 memset(pll_lim, 0, sizeof(struct pll_lims)); 4621 4622 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) { 4623 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex]; 4624 4625 pll_lim->vco1.minfreq = ROM32(pll_rec[0]); 4626 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]); 4627 pll_lim->vco2.minfreq = ROM32(pll_rec[8]); 4628 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]); 4629 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]); 4630 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]); 4631 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX; 4632 4633 /* these values taken from nv30/31/36 */ 4634 pll_lim->vco1.min_n = 0x1; 4635 if (cv == 0x36) 4636 pll_lim->vco1.min_n = 0x5; 4637 pll_lim->vco1.max_n = 0xff; 4638 pll_lim->vco1.min_m = 0x1; 4639 pll_lim->vco1.max_m = 0xd; 4640 pll_lim->vco2.min_n = 0x4; 4641 /* 4642 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this 4643 * table version (apart from nv35)), N2 is compared to 4644 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and 4645 * save a comparison 4646 */ 4647 pll_lim->vco2.max_n = 0x28; 4648 if (cv == 0x30 || cv == 0x35) 4649 /* only 5 bits available for N2 on nv30/35 */ 4650 pll_lim->vco2.max_n = 0x1f; 4651 pll_lim->vco2.min_m = 0x1; 4652 pll_lim->vco2.max_m = 0x4; 4653 pll_lim->max_log2p = 0x7; 4654 pll_lim->max_usable_log2p = 0x6; 4655 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) { 4656 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen; 4657 uint32_t reg = 0; /* default match */ 4658 uint8_t *pll_rec; 4659 int i; 4660 4661 /* 4662 * First entry is default match, if nothing better. warn if 4663 * reg field nonzero 4664 */ 4665 if (ROM32(bios->data[plloffs])) 4666 NV_WARN(dev, "Default PLL limit entry has non-zero " 4667 "register field\n"); 4668 4669 if (limit_match > MAX_PLL_TYPES) 4670 /* we've been passed a reg as the match */ 4671 reg = limit_match; 4672 else /* limit match is a pll type */ 4673 for (i = 1; i < entries && !reg; i++) { 4674 uint32_t cmpreg = ROM32(bios->data[plloffs + recordlen * i]); 4675 4676 if (limit_match == NVPLL && 4677 (cmpreg == NV_PRAMDAC_NVPLL_COEFF || cmpreg == 0x4000)) 4678 reg = cmpreg; 4679 if (limit_match == MPLL && 4680 (cmpreg == NV_PRAMDAC_MPLL_COEFF || cmpreg == 0x4020)) 4681 reg = cmpreg; 4682 if (limit_match == VPLL1 && 4683 (cmpreg == NV_PRAMDAC_VPLL_COEFF || cmpreg == 0x4010)) 4684 reg = cmpreg; 4685 if (limit_match == VPLL2 && 4686 (cmpreg == NV_RAMDAC_VPLL2 || cmpreg == 0x4018)) 4687 reg = cmpreg; 4688 } 4689 4690 for (i = 1; i < entries; i++) 4691 if (ROM32(bios->data[plloffs + recordlen * i]) == reg) { 4692 pllindex = i; 4693 break; 4694 } 4695 4696 pll_rec = &bios->data[plloffs + recordlen * pllindex]; 4697 4698 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n", 4699 pllindex ? reg : 0); 4700 4701 /* 4702 * Frequencies are stored in tables in MHz, kHz are more 4703 * useful, so we convert. 4704 */ 4705 4706 /* What output frequencies can each VCO generate? */ 4707 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000; 4708 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000; 4709 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000; 4710 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000; 4711 4712 /* What input frequencies they accept (past the m-divider)? */ 4713 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000; 4714 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000; 4715 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000; 4716 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000; 4717 4718 /* What values are accepted as multiplier and divider? */ 4719 pll_lim->vco1.min_n = pll_rec[20]; 4720 pll_lim->vco1.max_n = pll_rec[21]; 4721 pll_lim->vco1.min_m = pll_rec[22]; 4722 pll_lim->vco1.max_m = pll_rec[23]; 4723 pll_lim->vco2.min_n = pll_rec[24]; 4724 pll_lim->vco2.max_n = pll_rec[25]; 4725 pll_lim->vco2.min_m = pll_rec[26]; 4726 pll_lim->vco2.max_m = pll_rec[27]; 4727 4728 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29]; 4729 if (pll_lim->max_log2p > 0x7) 4730 /* pll decoding in nv_hw.c assumes never > 7 */ 4731 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n", 4732 pll_lim->max_log2p); 4733 if (cv < 0x60) 4734 pll_lim->max_usable_log2p = 0x6; 4735 pll_lim->log2p_bias = pll_rec[30]; 4736 4737 if (recordlen > 0x22) 4738 pll_lim->refclk = ROM32(pll_rec[31]); 4739 4740 if (recordlen > 0x23 && pll_rec[35]) 4741 NV_WARN(dev, 4742 "Bits set in PLL configuration byte (%x)\n", 4743 pll_rec[35]); 4744 4745 /* C51 special not seen elsewhere */ 4746 if (cv == 0x51 && !pll_lim->refclk) { 4747 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK); 4748 4749 if (((limit_match == NV_PRAMDAC_VPLL_COEFF || limit_match == VPLL1) && sel_clk & 0x20) || 4750 ((limit_match == NV_RAMDAC_VPLL2 || limit_match == VPLL2) && sel_clk & 0x80)) { 4751 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3) 4752 pll_lim->refclk = 200000; 4753 else 4754 pll_lim->refclk = 25000; 4755 } 4756 } 4757 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */ 4758 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen]; 4759 uint8_t *record = NULL; 4760 int i; 4761 4762 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n", 4763 limit_match); 4764 4765 for (i = 0; i < entries; i++, entry += recordlen) { 4766 if (ROM32(entry[3]) == limit_match) { 4767 record = &bios->data[ROM16(entry[1])]; 4768 break; 4769 } 4770 } 4771 4772 if (!record) { 4773 NV_ERROR(dev, "Register 0x%08x not found in PLL " 4774 "limits table", limit_match); 4775 return -ENOENT; 4776 } 4777 4778 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000; 4779 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000; 4780 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000; 4781 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000; 4782 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000; 4783 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000; 4784 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000; 4785 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000; 4786 pll_lim->vco1.min_n = record[16]; 4787 pll_lim->vco1.max_n = record[17]; 4788 pll_lim->vco1.min_m = record[18]; 4789 pll_lim->vco1.max_m = record[19]; 4790 pll_lim->vco2.min_n = record[20]; 4791 pll_lim->vco2.max_n = record[21]; 4792 pll_lim->vco2.min_m = record[22]; 4793 pll_lim->vco2.max_m = record[23]; 4794 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25]; 4795 pll_lim->log2p_bias = record[27]; 4796 pll_lim->refclk = ROM32(record[28]); 4797 } else if (pll_lim_ver) { /* ver 0x40 */ 4798 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen]; 4799 uint8_t *record = NULL; 4800 int i; 4801 4802 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n", 4803 limit_match); 4804 4805 for (i = 0; i < entries; i++, entry += recordlen) { 4806 if (ROM32(entry[3]) == limit_match) { 4807 record = &bios->data[ROM16(entry[1])]; 4808 break; 4809 } 4810 } 4811 4812 if (!record) { 4813 NV_ERROR(dev, "Register 0x%08x not found in PLL " 4814 "limits table", limit_match); 4815 return -ENOENT; 4816 } 4817 4818 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000; 4819 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000; 4820 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000; 4821 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000; 4822 pll_lim->vco1.min_m = record[8]; 4823 pll_lim->vco1.max_m = record[9]; 4824 pll_lim->vco1.min_n = record[10]; 4825 pll_lim->vco1.max_n = record[11]; 4826 pll_lim->min_p = record[12]; 4827 pll_lim->max_p = record[13]; 4828 /* where did this go to?? */ 4829 if (limit_match == 0x00614100 || limit_match == 0x00614900) 4830 pll_lim->refclk = 27000; 4831 else 4832 pll_lim->refclk = 100000; 4833 } 4834 4835 /* 4836 * By now any valid limit table ought to have set a max frequency for 4837 * vco1, so if it's zero it's either a pre limit table bios, or one 4838 * with an empty limit table (seen on nv18) 4839 */ 4840 if (!pll_lim->vco1.maxfreq) { 4841 pll_lim->vco1.minfreq = bios->fminvco; 4842 pll_lim->vco1.maxfreq = bios->fmaxvco; 4843 pll_lim->vco1.min_inputfreq = 0; 4844 pll_lim->vco1.max_inputfreq = INT_MAX; 4845 pll_lim->vco1.min_n = 0x1; 4846 pll_lim->vco1.max_n = 0xff; 4847 pll_lim->vco1.min_m = 0x1; 4848 if (crystal_straps == 0) { 4849 /* nv05 does this, nv11 doesn't, nv10 unknown */ 4850 if (cv < 0x11) 4851 pll_lim->vco1.min_m = 0x7; 4852 pll_lim->vco1.max_m = 0xd; 4853 } else { 4854 if (cv < 0x11) 4855 pll_lim->vco1.min_m = 0x8; 4856 pll_lim->vco1.max_m = 0xe; 4857 } 4858 if (cv < 0x17 || cv == 0x1a || cv == 0x20) 4859 pll_lim->max_log2p = 4; 4860 else 4861 pll_lim->max_log2p = 5; 4862 pll_lim->max_usable_log2p = pll_lim->max_log2p; 4863 } 4864 4865 if (!pll_lim->refclk) 4866 switch (crystal_straps) { 4867 case 0: 4868 pll_lim->refclk = 13500; 4869 break; 4870 case (1 << 6): 4871 pll_lim->refclk = 14318; 4872 break; 4873 case (1 << 22): 4874 pll_lim->refclk = 27000; 4875 break; 4876 case (1 << 22 | 1 << 6): 4877 pll_lim->refclk = 25000; 4878 break; 4879 } 4880 4881 NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq); 4882 NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq); 4883 NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq); 4884 NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq); 4885 NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n); 4886 NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n); 4887 NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m); 4888 NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m); 4889 if (pll_lim->vco2.maxfreq) { 4890 NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq); 4891 NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq); 4892 NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq); 4893 NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq); 4894 NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n); 4895 NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n); 4896 NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m); 4897 NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m); 4898 } 4899 if (!pll_lim->max_p) { 4900 NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p); 4901 NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias); 4902 } else { 4903 NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p); 4904 NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p); 4905 } 4906 NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk); 4907 4908 return 0; 4909} 4910 4911static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset) 4912{ 4913 /* 4914 * offset + 0 (8 bits): Micro version 4915 * offset + 1 (8 bits): Minor version 4916 * offset + 2 (8 bits): Chip version 4917 * offset + 3 (8 bits): Major version 4918 */ 4919 4920 bios->major_version = bios->data[offset + 3]; 4921 bios->chip_version = bios->data[offset + 2]; 4922 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n", 4923 bios->data[offset + 3], bios->data[offset + 2], 4924 bios->data[offset + 1], bios->data[offset]); 4925} 4926 4927static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset) 4928{ 4929 /* 4930 * Parses the init table segment for pointers used in script execution. 4931 * 4932 * offset + 0 (16 bits): init script tables pointer 4933 * offset + 2 (16 bits): macro index table pointer 4934 * offset + 4 (16 bits): macro table pointer 4935 * offset + 6 (16 bits): condition table pointer 4936 * offset + 8 (16 bits): io condition table pointer 4937 * offset + 10 (16 bits): io flag condition table pointer 4938 * offset + 12 (16 bits): init function table pointer 4939 */ 4940 4941 bios->init_script_tbls_ptr = ROM16(bios->data[offset]); 4942 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]); 4943 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]); 4944 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]); 4945 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]); 4946 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]); 4947 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]); 4948} 4949 4950static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4951{ 4952 /* 4953 * Parses the load detect values for g80 cards. 4954 * 4955 * offset + 0 (16 bits): loadval table pointer 4956 */ 4957 4958 uint16_t load_table_ptr; 4959 uint8_t version, headerlen, entrylen, num_entries; 4960 4961 if (bitentry->length != 3) { 4962 NV_ERROR(dev, "Do not understand BIT A table\n"); 4963 return -EINVAL; 4964 } 4965 4966 load_table_ptr = ROM16(bios->data[bitentry->offset]); 4967 4968 if (load_table_ptr == 0x0) { 4969 NV_ERROR(dev, "Pointer to BIT loadval table invalid\n"); 4970 return -EINVAL; 4971 } 4972 4973 version = bios->data[load_table_ptr]; 4974 4975 if (version != 0x10) { 4976 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n", 4977 version >> 4, version & 0xF); 4978 return -ENOSYS; 4979 } 4980 4981 headerlen = bios->data[load_table_ptr + 1]; 4982 entrylen = bios->data[load_table_ptr + 2]; 4983 num_entries = bios->data[load_table_ptr + 3]; 4984 4985 if (headerlen != 4 || entrylen != 4 || num_entries != 2) { 4986 NV_ERROR(dev, "Do not understand BIT loadval table\n"); 4987 return -EINVAL; 4988 } 4989 4990 /* First entry is normal dac, 2nd tv-out perhaps? */ 4991 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff; 4992 4993 return 0; 4994} 4995 4996static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4997{ 4998 /* 4999 * offset + 8 (16 bits): PLL limits table pointer 5000 * 5001 * There's more in here, but that's unknown. 5002 */ 5003 5004 if (bitentry->length < 10) { 5005 NV_ERROR(dev, "Do not understand BIT C table\n"); 5006 return -EINVAL; 5007 } 5008 5009 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]); 5010 5011 return 0; 5012} 5013 5014static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5015{ 5016 /* 5017 * Parses the flat panel table segment that the bit entry points to. 5018 * Starting at bitentry->offset: 5019 * 5020 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte 5021 * records beginning with a freq. 5022 * offset + 2 (16 bits): mode table pointer 5023 */ 5024 5025 if (bitentry->length != 4) { 5026 NV_ERROR(dev, "Do not understand BIT display table\n"); 5027 return -EINVAL; 5028 } 5029 5030 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]); 5031 5032 return 0; 5033} 5034 5035static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5036{ 5037 /* 5038 * Parses the init table segment that the bit entry points to. 5039 * 5040 * See parse_script_table_pointers for layout 5041 */ 5042 5043 if (bitentry->length < 14) { 5044 NV_ERROR(dev, "Do not understand init table\n"); 5045 return -EINVAL; 5046 } 5047 5048 parse_script_table_pointers(bios, bitentry->offset); 5049 5050 if (bitentry->length >= 16) 5051 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]); 5052 if (bitentry->length >= 18) 5053 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]); 5054 5055 return 0; 5056} 5057 5058static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5059{ 5060 /* 5061 * BIT 'i' (info?) table 5062 * 5063 * offset + 0 (32 bits): BIOS version dword (as in B table) 5064 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?) 5065 * offset + 13 (16 bits): pointer to table containing DAC load 5066 * detection comparison values 5067 * 5068 * There's other things in the table, purpose unknown 5069 */ 5070 5071 uint16_t daccmpoffset; 5072 uint8_t dacver, dacheaderlen; 5073 5074 if (bitentry->length < 6) { 5075 NV_ERROR(dev, "BIT i table too short for needed information\n"); 5076 return -EINVAL; 5077 } 5078 5079 parse_bios_version(dev, bios, bitentry->offset); 5080 5081 /* 5082 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's 5083 * Quadro identity crisis), other bits possibly as for BMP feature byte 5084 */ 5085 bios->feature_byte = bios->data[bitentry->offset + 5]; 5086 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE; 5087 5088 if (bitentry->length < 15) { 5089 NV_WARN(dev, "BIT i table not long enough for DAC load " 5090 "detection comparison table\n"); 5091 return -EINVAL; 5092 } 5093 5094 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]); 5095 5096 /* doesn't exist on g80 */ 5097 if (!daccmpoffset) 5098 return 0; 5099 5100 /* 5101 * The first value in the table, following the header, is the 5102 * comparison value, the second entry is a comparison value for 5103 * TV load detection. 5104 */ 5105 5106 dacver = bios->data[daccmpoffset]; 5107 dacheaderlen = bios->data[daccmpoffset + 1]; 5108 5109 if (dacver != 0x00 && dacver != 0x10) { 5110 NV_WARN(dev, "DAC load detection comparison table version " 5111 "%d.%d not known\n", dacver >> 4, dacver & 0xf); 5112 return -ENOSYS; 5113 } 5114 5115 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]); 5116 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]); 5117 5118 return 0; 5119} 5120 5121static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5122{ 5123 /* 5124 * Parses the LVDS table segment that the bit entry points to. 5125 * Starting at bitentry->offset: 5126 * 5127 * offset + 0 (16 bits): LVDS strap xlate table pointer 5128 */ 5129 5130 if (bitentry->length != 2) { 5131 NV_ERROR(dev, "Do not understand BIT LVDS table\n"); 5132 return -EINVAL; 5133 } 5134 5135 /* 5136 * No idea if it's still called the LVDS manufacturer table, but 5137 * the concept's close enough. 5138 */ 5139 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]); 5140 5141 return 0; 5142} 5143 5144static int 5145parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios, 5146 struct bit_entry *bitentry) 5147{ 5148 /* 5149 * offset + 2 (8 bits): number of options in an 5150 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set 5151 * offset + 3 (16 bits): pointer to strap xlate table for RAM 5152 * restrict option selection 5153 * 5154 * There's a bunch of bits in this table other than the RAM restrict 5155 * stuff that we don't use - their use currently unknown 5156 */ 5157 5158 /* 5159 * Older bios versions don't have a sufficiently long table for 5160 * what we want 5161 */ 5162 if (bitentry->length < 0x5) 5163 return 0; 5164 5165 if (bitentry->id[1] < 2) { 5166 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2]; 5167 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]); 5168 } else { 5169 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0]; 5170 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]); 5171 } 5172 5173 return 0; 5174} 5175 5176static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5177{ 5178 /* 5179 * Parses the pointer to the TMDS table 5180 * 5181 * Starting at bitentry->offset: 5182 * 5183 * offset + 0 (16 bits): TMDS table pointer 5184 * 5185 * The TMDS table is typically found just before the DCB table, with a 5186 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being 5187 * length?) 5188 * 5189 * At offset +7 is a pointer to a script, which I don't know how to 5190 * run yet. 5191 * At offset +9 is a pointer to another script, likewise 5192 * Offset +11 has a pointer to a table where the first word is a pxclk 5193 * frequency and the second word a pointer to a script, which should be 5194 * run if the comparison pxclk frequency is less than the pxclk desired. 5195 * This repeats for decreasing comparison frequencies 5196 * Offset +13 has a pointer to a similar table 5197 * The selection of table (and possibly +7/+9 script) is dictated by 5198 * "or" from the DCB. 5199 */ 5200 5201 uint16_t tmdstableptr, script1, script2; 5202 5203 if (bitentry->length != 2) { 5204 NV_ERROR(dev, "Do not understand BIT TMDS table\n"); 5205 return -EINVAL; 5206 } 5207 5208 tmdstableptr = ROM16(bios->data[bitentry->offset]); 5209 5210 if (tmdstableptr == 0x0) { 5211 NV_ERROR(dev, "Pointer to TMDS table invalid\n"); 5212 return -EINVAL; 5213 } 5214 5215 /* nv50+ has v2.0, but we don't parse it atm */ 5216 if (bios->data[tmdstableptr] != 0x11) { 5217 NV_WARN(dev, 5218 "TMDS table revision %d.%d not currently supported\n", 5219 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf); 5220 return -ENOSYS; 5221 } 5222 5223 /* 5224 * These two scripts are odd: they don't seem to get run even when 5225 * they are not stubbed. 5226 */ 5227 script1 = ROM16(bios->data[tmdstableptr + 7]); 5228 script2 = ROM16(bios->data[tmdstableptr + 9]); 5229 if (bios->data[script1] != 'q' || bios->data[script2] != 'q') 5230 NV_WARN(dev, "TMDS table script pointers not stubbed\n"); 5231 5232 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]); 5233 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]); 5234 5235 return 0; 5236} 5237 5238static int 5239parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios, 5240 struct bit_entry *bitentry) 5241{ 5242 /* 5243 * Parses the pointer to the G80 output script tables 5244 * 5245 * Starting at bitentry->offset: 5246 * 5247 * offset + 0 (16 bits): output script table pointer 5248 */ 5249 5250 uint16_t outputscripttableptr; 5251 5252 if (bitentry->length != 3) { 5253 NV_ERROR(dev, "Do not understand BIT U table\n"); 5254 return -EINVAL; 5255 } 5256 5257 outputscripttableptr = ROM16(bios->data[bitentry->offset]); 5258 bios->display.script_table_ptr = outputscripttableptr; 5259 return 0; 5260} 5261 5262static int 5263parse_bit_displayport_tbl_entry(struct drm_device *dev, struct nvbios *bios, 5264 struct bit_entry *bitentry) 5265{ 5266 bios->display.dp_table_ptr = ROM16(bios->data[bitentry->offset]); 5267 return 0; 5268} 5269 5270struct bit_table { 5271 const char id; 5272 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *); 5273}; 5274 5275#define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry }) 5276 5277static int 5278parse_bit_table(struct nvbios *bios, const uint16_t bitoffset, 5279 struct bit_table *table) 5280{ 5281 struct drm_device *dev = bios->dev; 5282 uint8_t maxentries = bios->data[bitoffset + 4]; 5283 int i, offset; 5284 struct bit_entry bitentry; 5285 5286 for (i = 0, offset = bitoffset + 6; i < maxentries; i++, offset += 6) { 5287 bitentry.id[0] = bios->data[offset]; 5288 5289 if (bitentry.id[0] != table->id) 5290 continue; 5291 5292 bitentry.id[1] = bios->data[offset + 1]; 5293 bitentry.length = ROM16(bios->data[offset + 2]); 5294 bitentry.offset = ROM16(bios->data[offset + 4]); 5295 5296 return table->parse_fn(dev, bios, &bitentry); 5297 } 5298 5299 NV_INFO(dev, "BIT table '%c' not found\n", table->id); 5300 return -ENOSYS; 5301} 5302 5303static int 5304parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset) 5305{ 5306 int ret; 5307 5308 /* 5309 * The only restriction on parsing order currently is having 'i' first 5310 * for use of bios->*_version or bios->feature_byte while parsing; 5311 * functions shouldn't be actually *doing* anything apart from pulling 5312 * data from the image into the bios struct, thus no interdependencies 5313 */ 5314 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i)); 5315 if (ret) /* info? */ 5316 return ret; 5317 if (bios->major_version >= 0x60) /* g80+ */ 5318 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A)); 5319 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C)); 5320 if (ret) 5321 return ret; 5322 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display)); 5323 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init)); 5324 if (ret) 5325 return ret; 5326 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */ 5327 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds)); 5328 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds)); 5329 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U)); 5330 parse_bit_table(bios, bitoffset, &BIT_TABLE('d', displayport)); 5331 5332 return 0; 5333} 5334 5335static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset) 5336{ 5337 /* 5338 * Parses the BMP structure for useful things, but does not act on them 5339 * 5340 * offset + 5: BMP major version 5341 * offset + 6: BMP minor version 5342 * offset + 9: BMP feature byte 5343 * offset + 10: BCD encoded BIOS version 5344 * 5345 * offset + 18: init script table pointer (for bios versions < 5.10h) 5346 * offset + 20: extra init script table pointer (for bios 5347 * versions < 5.10h) 5348 * 5349 * offset + 24: memory init table pointer (used on early bios versions) 5350 * offset + 26: SDR memory sequencing setup data table 5351 * offset + 28: DDR memory sequencing setup data table 5352 * 5353 * offset + 54: index of I2C CRTC pair to use for CRT output 5354 * offset + 55: index of I2C CRTC pair to use for TV output 5355 * offset + 56: index of I2C CRTC pair to use for flat panel output 5356 * offset + 58: write CRTC index for I2C pair 0 5357 * offset + 59: read CRTC index for I2C pair 0 5358 * offset + 60: write CRTC index for I2C pair 1 5359 * offset + 61: read CRTC index for I2C pair 1 5360 * 5361 * offset + 67: maximum internal PLL frequency (single stage PLL) 5362 * offset + 71: minimum internal PLL frequency (single stage PLL) 5363 * 5364 * offset + 75: script table pointers, as described in 5365 * parse_script_table_pointers 5366 * 5367 * offset + 89: TMDS single link output A table pointer 5368 * offset + 91: TMDS single link output B table pointer 5369 * offset + 95: LVDS single link output A table pointer 5370 * offset + 105: flat panel timings table pointer 5371 * offset + 107: flat panel strapping translation table pointer 5372 * offset + 117: LVDS manufacturer panel config table pointer 5373 * offset + 119: LVDS manufacturer strapping translation table pointer 5374 * 5375 * offset + 142: PLL limits table pointer 5376 * 5377 * offset + 156: minimum pixel clock for LVDS dual link 5378 */ 5379 5380 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor; 5381 uint16_t bmplength; 5382 uint16_t legacy_scripts_offset, legacy_i2c_offset; 5383 5384 /* load needed defaults in case we can't parse this info */ 5385 bios->dcb.i2c[0].write = NV_CIO_CRE_DDC_WR__INDEX; 5386 bios->dcb.i2c[0].read = NV_CIO_CRE_DDC_STATUS__INDEX; 5387 bios->dcb.i2c[1].write = NV_CIO_CRE_DDC0_WR__INDEX; 5388 bios->dcb.i2c[1].read = NV_CIO_CRE_DDC0_STATUS__INDEX; 5389 bios->digital_min_front_porch = 0x4b; 5390 bios->fmaxvco = 256000; 5391 bios->fminvco = 128000; 5392 bios->fp.duallink_transition_clk = 90000; 5393 5394 bmp_version_major = bmp[5]; 5395 bmp_version_minor = bmp[6]; 5396 5397 NV_TRACE(dev, "BMP version %d.%d\n", 5398 bmp_version_major, bmp_version_minor); 5399 5400 /* 5401 * Make sure that 0x36 is blank and can't be mistaken for a DCB 5402 * pointer on early versions 5403 */ 5404 if (bmp_version_major < 5) 5405 *(uint16_t *)&bios->data[0x36] = 0; 5406 5407 /* 5408 * Seems that the minor version was 1 for all major versions prior 5409 * to 5. Version 6 could theoretically exist, but I suspect BIT 5410 * happened instead. 5411 */ 5412 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) { 5413 NV_ERROR(dev, "You have an unsupported BMP version. " 5414 "Please send in your bios\n"); 5415 return -ENOSYS; 5416 } 5417 5418 if (bmp_version_major == 0) 5419 /* nothing that's currently useful in this version */ 5420 return 0; 5421 else if (bmp_version_major == 1) 5422 bmplength = 44; /* exact for 1.01 */ 5423 else if (bmp_version_major == 2) 5424 bmplength = 48; /* exact for 2.01 */ 5425 else if (bmp_version_major == 3) 5426 bmplength = 54; 5427 /* guessed - mem init tables added in this version */ 5428 else if (bmp_version_major == 4 || bmp_version_minor < 0x1) 5429 /* don't know if 5.0 exists... */ 5430 bmplength = 62; 5431 /* guessed - BMP I2C indices added in version 4*/ 5432 else if (bmp_version_minor < 0x6) 5433 bmplength = 67; /* exact for 5.01 */ 5434 else if (bmp_version_minor < 0x10) 5435 bmplength = 75; /* exact for 5.06 */ 5436 else if (bmp_version_minor == 0x10) 5437 bmplength = 89; /* exact for 5.10h */ 5438 else if (bmp_version_minor < 0x14) 5439 bmplength = 118; /* exact for 5.11h */ 5440 else if (bmp_version_minor < 0x24) 5441 /* 5442 * Not sure of version where pll limits came in; 5443 * certainly exist by 0x24 though. 5444 */ 5445 /* length not exact: this is long enough to get lvds members */ 5446 bmplength = 123; 5447 else if (bmp_version_minor < 0x27) 5448 /* 5449 * Length not exact: this is long enough to get pll limit 5450 * member 5451 */ 5452 bmplength = 144; 5453 else 5454 /* 5455 * Length not exact: this is long enough to get dual link 5456 * transition clock. 5457 */ 5458 bmplength = 158; 5459 5460 /* checksum */ 5461 if (nv_cksum(bmp, 8)) { 5462 NV_ERROR(dev, "Bad BMP checksum\n"); 5463 return -EINVAL; 5464 } 5465 5466 /* 5467 * Bit 4 seems to indicate either a mobile bios or a quadro card -- 5468 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl 5469 * (not nv10gl), bit 5 that the flat panel tables are present, and 5470 * bit 6 a tv bios. 5471 */ 5472 bios->feature_byte = bmp[9]; 5473 5474 parse_bios_version(dev, bios, offset + 10); 5475 5476 if (bmp_version_major < 5 || bmp_version_minor < 0x10) 5477 bios->old_style_init = true; 5478 legacy_scripts_offset = 18; 5479 if (bmp_version_major < 2) 5480 legacy_scripts_offset -= 4; 5481 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]); 5482 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]); 5483 5484 if (bmp_version_major > 2) { /* appears in BMP 3 */ 5485 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]); 5486 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]); 5487 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]); 5488 } 5489 5490 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */ 5491 if (bmplength > 61) 5492 legacy_i2c_offset = offset + 54; 5493 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset]; 5494 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1]; 5495 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2]; 5496 if (bios->data[legacy_i2c_offset + 4]) 5497 bios->dcb.i2c[0].write = bios->data[legacy_i2c_offset + 4]; 5498 if (bios->data[legacy_i2c_offset + 5]) 5499 bios->dcb.i2c[0].read = bios->data[legacy_i2c_offset + 5]; 5500 if (bios->data[legacy_i2c_offset + 6]) 5501 bios->dcb.i2c[1].write = bios->data[legacy_i2c_offset + 6]; 5502 if (bios->data[legacy_i2c_offset + 7]) 5503 bios->dcb.i2c[1].read = bios->data[legacy_i2c_offset + 7]; 5504 5505 if (bmplength > 74) { 5506 bios->fmaxvco = ROM32(bmp[67]); 5507 bios->fminvco = ROM32(bmp[71]); 5508 } 5509 if (bmplength > 88) 5510 parse_script_table_pointers(bios, offset + 75); 5511 if (bmplength > 94) { 5512 bios->tmds.output0_script_ptr = ROM16(bmp[89]); 5513 bios->tmds.output1_script_ptr = ROM16(bmp[91]); 5514 /* 5515 * Never observed in use with lvds scripts, but is reused for 5516 * 18/24 bit panel interface default for EDID equipped panels 5517 * (if_is_24bit not set directly to avoid any oscillation). 5518 */ 5519 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]); 5520 } 5521 if (bmplength > 108) { 5522 bios->fp.fptablepointer = ROM16(bmp[105]); 5523 bios->fp.fpxlatetableptr = ROM16(bmp[107]); 5524 bios->fp.xlatwidth = 1; 5525 } 5526 if (bmplength > 120) { 5527 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]); 5528 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]); 5529 } 5530 if (bmplength > 143) 5531 bios->pll_limit_tbl_ptr = ROM16(bmp[142]); 5532 5533 if (bmplength > 157) 5534 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10; 5535 5536 return 0; 5537} 5538 5539static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len) 5540{ 5541 int i, j; 5542 5543 for (i = 0; i <= (n - len); i++) { 5544 for (j = 0; j < len; j++) 5545 if (data[i + j] != str[j]) 5546 break; 5547 if (j == len) 5548 return i; 5549 } 5550 5551 return 0; 5552} 5553 5554static struct dcb_gpio_entry * 5555new_gpio_entry(struct nvbios *bios) 5556{ 5557 struct dcb_gpio_table *gpio = &bios->dcb.gpio; 5558 5559 return &gpio->entry[gpio->entries++]; 5560} 5561 5562struct dcb_gpio_entry * 5563nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag) 5564{ 5565 struct drm_nouveau_private *dev_priv = dev->dev_private; 5566 struct nvbios *bios = &dev_priv->vbios; 5567 int i; 5568 5569 for (i = 0; i < bios->dcb.gpio.entries; i++) { 5570 if (bios->dcb.gpio.entry[i].tag != tag) 5571 continue; 5572 5573 return &bios->dcb.gpio.entry[i]; 5574 } 5575 5576 return NULL; 5577} 5578 5579static void 5580parse_dcb30_gpio_entry(struct nvbios *bios, uint16_t offset) 5581{ 5582 struct dcb_gpio_entry *gpio; 5583 uint16_t ent = ROM16(bios->data[offset]); 5584 uint8_t line = ent & 0x1f, 5585 tag = ent >> 5 & 0x3f, 5586 flags = ent >> 11 & 0x1f; 5587 5588 if (tag == 0x3f) 5589 return; 5590 5591 gpio = new_gpio_entry(bios); 5592 5593 gpio->tag = tag; 5594 gpio->line = line; 5595 gpio->invert = flags != 4; 5596 gpio->entry = ent; 5597} 5598 5599static void 5600parse_dcb40_gpio_entry(struct nvbios *bios, uint16_t offset) 5601{ 5602 uint32_t entry = ROM32(bios->data[offset]); 5603 struct dcb_gpio_entry *gpio; 5604 5605 if ((entry & 0x0000ff00) == 0x0000ff00) 5606 return; 5607 5608 gpio = new_gpio_entry(bios); 5609 gpio->tag = (entry & 0x0000ff00) >> 8; 5610 gpio->line = (entry & 0x0000001f) >> 0; 5611 gpio->state_default = (entry & 0x01000000) >> 24; 5612 gpio->state[0] = (entry & 0x18000000) >> 27; 5613 gpio->state[1] = (entry & 0x60000000) >> 29; 5614 gpio->entry = entry; 5615} 5616 5617static void 5618parse_dcb_gpio_table(struct nvbios *bios) 5619{ 5620 struct drm_device *dev = bios->dev; 5621 uint16_t gpio_table_ptr = bios->dcb.gpio_table_ptr; 5622 uint8_t *gpio_table = &bios->data[gpio_table_ptr]; 5623 int header_len = gpio_table[1], 5624 entries = gpio_table[2], 5625 entry_len = gpio_table[3]; 5626 void (*parse_entry)(struct nvbios *, uint16_t) = NULL; 5627 int i; 5628 5629 if (bios->dcb.version >= 0x40) { 5630 if (gpio_table_ptr && entry_len != 4) { 5631 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n"); 5632 return; 5633 } 5634 5635 parse_entry = parse_dcb40_gpio_entry; 5636 5637 } else if (bios->dcb.version >= 0x30) { 5638 if (gpio_table_ptr && entry_len != 2) { 5639 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n"); 5640 return; 5641 } 5642 5643 parse_entry = parse_dcb30_gpio_entry; 5644 5645 } else if (bios->dcb.version >= 0x22) { 5646 /* 5647 * DCBs older than v3.0 don't really have a GPIO 5648 * table, instead they keep some GPIO info at fixed 5649 * locations. 5650 */ 5651 uint16_t dcbptr = ROM16(bios->data[0x36]); 5652 uint8_t *tvdac_gpio = &bios->data[dcbptr - 5]; 5653 5654 if (tvdac_gpio[0] & 1) { 5655 struct dcb_gpio_entry *gpio = new_gpio_entry(bios); 5656 5657 gpio->tag = DCB_GPIO_TVDAC0; 5658 gpio->line = tvdac_gpio[1] >> 4; 5659 gpio->invert = tvdac_gpio[0] & 2; 5660 } 5661 } 5662 5663 if (!gpio_table_ptr) 5664 return; 5665 5666 if (entries > DCB_MAX_NUM_GPIO_ENTRIES) { 5667 NV_WARN(dev, "Too many entries in the DCB GPIO table.\n"); 5668 entries = DCB_MAX_NUM_GPIO_ENTRIES; 5669 } 5670 5671 for (i = 0; i < entries; i++) 5672 parse_entry(bios, gpio_table_ptr + header_len + entry_len * i); 5673} 5674 5675struct dcb_connector_table_entry * 5676nouveau_bios_connector_entry(struct drm_device *dev, int index) 5677{ 5678 struct drm_nouveau_private *dev_priv = dev->dev_private; 5679 struct nvbios *bios = &dev_priv->vbios; 5680 struct dcb_connector_table_entry *cte; 5681 5682 if (index >= bios->dcb.connector.entries) 5683 return NULL; 5684 5685 cte = &bios->dcb.connector.entry[index]; 5686 if (cte->type == 0xff) 5687 return NULL; 5688 5689 return cte; 5690} 5691 5692static enum dcb_connector_type 5693divine_connector_type(struct nvbios *bios, int index) 5694{ 5695 struct dcb_table *dcb = &bios->dcb; 5696 unsigned encoders = 0, type = DCB_CONNECTOR_NONE; 5697 int i; 5698 5699 for (i = 0; i < dcb->entries; i++) { 5700 if (dcb->entry[i].connector == index) 5701 encoders |= (1 << dcb->entry[i].type); 5702 } 5703 5704 if (encoders & (1 << OUTPUT_DP)) { 5705 if (encoders & (1 << OUTPUT_TMDS)) 5706 type = DCB_CONNECTOR_DP; 5707 else 5708 type = DCB_CONNECTOR_eDP; 5709 } else 5710 if (encoders & (1 << OUTPUT_TMDS)) { 5711 if (encoders & (1 << OUTPUT_ANALOG)) 5712 type = DCB_CONNECTOR_DVI_I; 5713 else 5714 type = DCB_CONNECTOR_DVI_D; 5715 } else 5716 if (encoders & (1 << OUTPUT_ANALOG)) { 5717 type = DCB_CONNECTOR_VGA; 5718 } else 5719 if (encoders & (1 << OUTPUT_LVDS)) { 5720 type = DCB_CONNECTOR_LVDS; 5721 } else 5722 if (encoders & (1 << OUTPUT_TV)) { 5723 type = DCB_CONNECTOR_TV_0; 5724 } 5725 5726 return type; 5727} 5728 5729static void 5730apply_dcb_connector_quirks(struct nvbios *bios, int idx) 5731{ 5732 struct dcb_connector_table_entry *cte = &bios->dcb.connector.entry[idx]; 5733 struct drm_device *dev = bios->dev; 5734 5735 /* Gigabyte NX85T */ 5736 if ((dev->pdev->device == 0x0421) && 5737 (dev->pdev->subsystem_vendor == 0x1458) && 5738 (dev->pdev->subsystem_device == 0x344c)) { 5739 if (cte->type == DCB_CONNECTOR_HDMI_1) 5740 cte->type = DCB_CONNECTOR_DVI_I; 5741 } 5742} 5743 5744static void 5745parse_dcb_connector_table(struct nvbios *bios) 5746{ 5747 struct drm_device *dev = bios->dev; 5748 struct dcb_connector_table *ct = &bios->dcb.connector; 5749 struct dcb_connector_table_entry *cte; 5750 uint8_t *conntab = &bios->data[bios->dcb.connector_table_ptr]; 5751 uint8_t *entry; 5752 int i; 5753 5754 if (!bios->dcb.connector_table_ptr) { 5755 NV_DEBUG_KMS(dev, "No DCB connector table present\n"); 5756 return; 5757 } 5758 5759 NV_INFO(dev, "DCB connector table: VHER 0x%02x %d %d %d\n", 5760 conntab[0], conntab[1], conntab[2], conntab[3]); 5761 if ((conntab[0] != 0x30 && conntab[0] != 0x40) || 5762 (conntab[3] != 2 && conntab[3] != 4)) { 5763 NV_ERROR(dev, " Unknown! Please report.\n"); 5764 return; 5765 } 5766 5767 ct->entries = conntab[2]; 5768 5769 entry = conntab + conntab[1]; 5770 cte = &ct->entry[0]; 5771 for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) { 5772 cte->index = i; 5773 if (conntab[3] == 2) 5774 cte->entry = ROM16(entry[0]); 5775 else 5776 cte->entry = ROM32(entry[0]); 5777 5778 cte->type = (cte->entry & 0x000000ff) >> 0; 5779 cte->index2 = (cte->entry & 0x00000f00) >> 8; 5780 switch (cte->entry & 0x00033000) { 5781 case 0x00001000: 5782 cte->gpio_tag = 0x07; 5783 break; 5784 case 0x00002000: 5785 cte->gpio_tag = 0x08; 5786 break; 5787 case 0x00010000: 5788 cte->gpio_tag = 0x51; 5789 break; 5790 case 0x00020000: 5791 cte->gpio_tag = 0x52; 5792 break; 5793 default: 5794 cte->gpio_tag = 0xff; 5795 break; 5796 } 5797 5798 if (cte->type == 0xff) 5799 continue; 5800 5801 apply_dcb_connector_quirks(bios, i); 5802 5803 NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n", 5804 i, cte->entry, cte->type, cte->index, cte->gpio_tag); 5805 5806 /* check for known types, fallback to guessing the type 5807 * from attached encoders if we hit an unknown. 5808 */ 5809 switch (cte->type) { 5810 case DCB_CONNECTOR_VGA: 5811 case DCB_CONNECTOR_TV_0: 5812 case DCB_CONNECTOR_TV_1: 5813 case DCB_CONNECTOR_TV_3: 5814 case DCB_CONNECTOR_DVI_I: 5815 case DCB_CONNECTOR_DVI_D: 5816 case DCB_CONNECTOR_LVDS: 5817 case DCB_CONNECTOR_DP: 5818 case DCB_CONNECTOR_eDP: 5819 case DCB_CONNECTOR_HDMI_0: 5820 case DCB_CONNECTOR_HDMI_1: 5821 break; 5822 default: 5823 cte->type = divine_connector_type(bios, cte->index); 5824 NV_WARN(dev, "unknown type, using 0x%02x\n", cte->type); 5825 break; 5826 } 5827 5828 if (nouveau_override_conntype) { 5829 int type = divine_connector_type(bios, cte->index); 5830 if (type != cte->type) 5831 NV_WARN(dev, " -> type 0x%02x\n", cte->type); 5832 } 5833 5834 } 5835} 5836 5837static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb) 5838{ 5839 struct dcb_entry *entry = &dcb->entry[dcb->entries]; 5840 5841 memset(entry, 0, sizeof(struct dcb_entry)); 5842 entry->index = dcb->entries++; 5843 5844 return entry; 5845} 5846 5847static void fabricate_vga_output(struct dcb_table *dcb, int i2c, int heads) 5848{ 5849 struct dcb_entry *entry = new_dcb_entry(dcb); 5850 5851 entry->type = 0; 5852 entry->i2c_index = i2c; 5853 entry->heads = heads; 5854 entry->location = DCB_LOC_ON_CHIP; 5855 /* "or" mostly unused in early gen crt modesetting, 0 is fine */ 5856} 5857 5858static void fabricate_dvi_i_output(struct dcb_table *dcb, bool twoHeads) 5859{ 5860 struct dcb_entry *entry = new_dcb_entry(dcb); 5861 5862 entry->type = 2; 5863 entry->i2c_index = LEGACY_I2C_PANEL; 5864 entry->heads = twoHeads ? 3 : 1; 5865 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */ 5866 entry->or = 1; /* means |0x10 gets set on CRE_LCD__INDEX */ 5867 entry->duallink_possible = false; /* SiI164 and co. are single link */ 5868 5869#if 0 5870 /* 5871 * For dvi-a either crtc probably works, but my card appears to only 5872 * support dvi-d. "nvidia" still attempts to program it for dvi-a, 5873 * doing the full fp output setup (program 0x6808.. fp dimension regs, 5874 * setting 0x680848 to 0x10000111 to enable, maybe setting 0x680880); 5875 * the monitor picks up the mode res ok and lights up, but no pixel 5876 * data appears, so the board manufacturer probably connected up the 5877 * sync lines, but missed the video traces / components 5878 * 5879 * with this introduction, dvi-a left as an exercise for the reader. 5880 */ 5881 fabricate_vga_output(dcb, LEGACY_I2C_PANEL, entry->heads); 5882#endif 5883} 5884 5885static void fabricate_tv_output(struct dcb_table *dcb, bool twoHeads) 5886{ 5887 struct dcb_entry *entry = new_dcb_entry(dcb); 5888 5889 entry->type = 1; 5890 entry->i2c_index = LEGACY_I2C_TV; 5891 entry->heads = twoHeads ? 3 : 1; 5892 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */ 5893} 5894 5895static bool 5896parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb, 5897 uint32_t conn, uint32_t conf, struct dcb_entry *entry) 5898{ 5899 entry->type = conn & 0xf; 5900 entry->i2c_index = (conn >> 4) & 0xf; 5901 entry->heads = (conn >> 8) & 0xf; 5902 if (dcb->version >= 0x40) 5903 entry->connector = (conn >> 12) & 0xf; 5904 entry->bus = (conn >> 16) & 0xf; 5905 entry->location = (conn >> 20) & 0x3; 5906 entry->or = (conn >> 24) & 0xf; 5907 5908 switch (entry->type) { 5909 case OUTPUT_ANALOG: 5910 /* 5911 * Although the rest of a CRT conf dword is usually 5912 * zeros, mac biosen have stuff there so we must mask 5913 */ 5914 entry->crtconf.maxfreq = (dcb->version < 0x30) ? 5915 (conf & 0xffff) * 10 : 5916 (conf & 0xff) * 10000; 5917 break; 5918 case OUTPUT_LVDS: 5919 { 5920 uint32_t mask; 5921 if (conf & 0x1) 5922 entry->lvdsconf.use_straps_for_mode = true; 5923 if (dcb->version < 0x22) { 5924 mask = ~0xd; 5925 /* 5926 * The laptop in bug 14567 lies and claims to not use 5927 * straps when it does, so assume all DCB 2.0 laptops 5928 * use straps, until a broken EDID using one is produced 5929 */ 5930 entry->lvdsconf.use_straps_for_mode = true; 5931 /* 5932 * Both 0x4 and 0x8 show up in v2.0 tables; assume they 5933 * mean the same thing (probably wrong, but might work) 5934 */ 5935 if (conf & 0x4 || conf & 0x8) 5936 entry->lvdsconf.use_power_scripts = true; 5937 } else { 5938 mask = ~0x7; 5939 if (conf & 0x2) 5940 entry->lvdsconf.use_acpi_for_edid = true; 5941 if (conf & 0x4) 5942 entry->lvdsconf.use_power_scripts = true; 5943 entry->lvdsconf.sor.link = (conf & 0x00000030) >> 4; 5944 } 5945 if (conf & mask) { 5946 /* 5947 * Until we even try to use these on G8x, it's 5948 * useless reporting unknown bits. They all are. 5949 */ 5950 if (dcb->version >= 0x40) 5951 break; 5952 5953 NV_ERROR(dev, "Unknown LVDS configuration bits, " 5954 "please report\n"); 5955 } 5956 break; 5957 } 5958 case OUTPUT_TV: 5959 { 5960 if (dcb->version >= 0x30) 5961 entry->tvconf.has_component_output = conf & (0x8 << 4); 5962 else 5963 entry->tvconf.has_component_output = false; 5964 5965 break; 5966 } 5967 case OUTPUT_DP: 5968 entry->dpconf.sor.link = (conf & 0x00000030) >> 4; 5969 entry->dpconf.link_bw = (conf & 0x00e00000) >> 21; 5970 switch ((conf & 0x0f000000) >> 24) { 5971 case 0xf: 5972 entry->dpconf.link_nr = 4; 5973 break; 5974 case 0x3: 5975 entry->dpconf.link_nr = 2; 5976 break; 5977 default: 5978 entry->dpconf.link_nr = 1; 5979 break; 5980 } 5981 break; 5982 case OUTPUT_TMDS: 5983 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4; 5984 break; 5985 case 0xe: 5986 /* weird g80 mobile type that "nv" treats as a terminator */ 5987 dcb->entries--; 5988 return false; 5989 default: 5990 break; 5991 } 5992 5993 if (dcb->version < 0x40) { 5994 /* Normal entries consist of a single bit, but dual link has 5995 * the next most significant bit set too 5996 */ 5997 entry->duallink_possible = 5998 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or); 5999 } else { 6000 entry->duallink_possible = (entry->sorconf.link == 3); 6001 } 6002 6003 /* unsure what DCB version introduces this, 3.0? */ 6004 if (conf & 0x100000) 6005 entry->i2c_upper_default = true; 6006 6007 return true; 6008} 6009 6010static bool 6011parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb, 6012 uint32_t conn, uint32_t conf, struct dcb_entry *entry) 6013{ 6014 switch (conn & 0x0000000f) { 6015 case 0: 6016 entry->type = OUTPUT_ANALOG; 6017 break; 6018 case 1: 6019 entry->type = OUTPUT_TV; 6020 break; 6021 case 2: 6022 case 3: 6023 entry->type = OUTPUT_LVDS; 6024 break; 6025 case 4: 6026 switch ((conn & 0x000000f0) >> 4) { 6027 case 0: 6028 entry->type = OUTPUT_TMDS; 6029 break; 6030 case 1: 6031 entry->type = OUTPUT_LVDS; 6032 break; 6033 default: 6034 NV_ERROR(dev, "Unknown DCB subtype 4/%d\n", 6035 (conn & 0x000000f0) >> 4); 6036 return false; 6037 } 6038 break; 6039 default: 6040 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f); 6041 return false; 6042 } 6043 6044 entry->i2c_index = (conn & 0x0003c000) >> 14; 6045 entry->heads = ((conn & 0x001c0000) >> 18) + 1; 6046 entry->or = entry->heads; /* same as heads, hopefully safe enough */ 6047 entry->location = (conn & 0x01e00000) >> 21; 6048 entry->bus = (conn & 0x0e000000) >> 25; 6049 entry->duallink_possible = false; 6050 6051 switch (entry->type) { 6052 case OUTPUT_ANALOG: 6053 entry->crtconf.maxfreq = (conf & 0xffff) * 10; 6054 break; 6055 case OUTPUT_TV: 6056 entry->tvconf.has_component_output = false; 6057 break; 6058 case OUTPUT_LVDS: 6059 if ((conn & 0x00003f00) != 0x10) 6060 entry->lvdsconf.use_straps_for_mode = true; 6061 entry->lvdsconf.use_power_scripts = true; 6062 break; 6063 default: 6064 break; 6065 } 6066 6067 return true; 6068} 6069 6070static bool parse_dcb_entry(struct drm_device *dev, struct dcb_table *dcb, 6071 uint32_t conn, uint32_t conf) 6072{ 6073 struct dcb_entry *entry = new_dcb_entry(dcb); 6074 bool ret; 6075 6076 if (dcb->version >= 0x20) 6077 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry); 6078 else 6079 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry); 6080 if (!ret) 6081 return ret; 6082 6083 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table, 6084 entry->i2c_index, &dcb->i2c[entry->i2c_index]); 6085 6086 return true; 6087} 6088 6089static 6090void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb) 6091{ 6092 /* 6093 * DCB v2.0 lists each output combination separately. 6094 * Here we merge compatible entries to have fewer outputs, with 6095 * more options 6096 */ 6097 6098 int i, newentries = 0; 6099 6100 for (i = 0; i < dcb->entries; i++) { 6101 struct dcb_entry *ient = &dcb->entry[i]; 6102 int j; 6103 6104 for (j = i + 1; j < dcb->entries; j++) { 6105 struct dcb_entry *jent = &dcb->entry[j]; 6106 6107 if (jent->type == 100) /* already merged entry */ 6108 continue; 6109 6110 /* merge heads field when all other fields the same */ 6111 if (jent->i2c_index == ient->i2c_index && 6112 jent->type == ient->type && 6113 jent->location == ient->location && 6114 jent->or == ient->or) { 6115 NV_TRACE(dev, "Merging DCB entries %d and %d\n", 6116 i, j); 6117 ient->heads |= jent->heads; 6118 jent->type = 100; /* dummy value */ 6119 } 6120 } 6121 } 6122 6123 /* Compact entries merged into others out of dcb */ 6124 for (i = 0; i < dcb->entries; i++) { 6125 if (dcb->entry[i].type == 100) 6126 continue; 6127 6128 if (newentries != i) { 6129 dcb->entry[newentries] = dcb->entry[i]; 6130 dcb->entry[newentries].index = newentries; 6131 } 6132 newentries++; 6133 } 6134 6135 dcb->entries = newentries; 6136} 6137 6138static bool 6139apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf) 6140{ 6141 /* Dell Precision M6300 6142 * DCB entry 2: 02025312 00000010 6143 * DCB entry 3: 02026312 00000020 6144 * 6145 * Identical, except apparently a different connector on a 6146 * different SOR link. Not a clue how we're supposed to know 6147 * which one is in use if it even shares an i2c line... 6148 * 6149 * Ignore the connector on the second SOR link to prevent 6150 * nasty problems until this is sorted (assuming it's not a 6151 * VBIOS bug). 6152 */ 6153 if ((dev->pdev->device == 0x040d) && 6154 (dev->pdev->subsystem_vendor == 0x1028) && 6155 (dev->pdev->subsystem_device == 0x019b)) { 6156 if (*conn == 0x02026312 && *conf == 0x00000020) 6157 return false; 6158 } 6159 6160 return true; 6161} 6162 6163static int 6164parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads) 6165{ 6166 struct drm_nouveau_private *dev_priv = dev->dev_private; 6167 struct dcb_table *dcb = &bios->dcb; 6168 uint16_t dcbptr = 0, i2ctabptr = 0; 6169 uint8_t *dcbtable; 6170 uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES; 6171 bool configblock = true; 6172 int recordlength = 8, confofs = 4; 6173 int i; 6174 6175 /* get the offset from 0x36 */ 6176 if (dev_priv->card_type > NV_04) { 6177 dcbptr = ROM16(bios->data[0x36]); 6178 if (dcbptr == 0x0000) 6179 NV_WARN(dev, "No output data (DCB) found in BIOS\n"); 6180 } 6181 6182 /* this situation likely means a really old card, pre DCB */ 6183 if (dcbptr == 0x0) { 6184 NV_INFO(dev, "Assuming a CRT output exists\n"); 6185 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1); 6186 6187 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0) 6188 fabricate_tv_output(dcb, twoHeads); 6189 6190 return 0; 6191 } 6192 6193 dcbtable = &bios->data[dcbptr]; 6194 6195 /* get DCB version */ 6196 dcb->version = dcbtable[0]; 6197 NV_TRACE(dev, "Found Display Configuration Block version %d.%d\n", 6198 dcb->version >> 4, dcb->version & 0xf); 6199 6200 if (dcb->version >= 0x20) { /* NV17+ */ 6201 uint32_t sig; 6202 6203 if (dcb->version >= 0x30) { /* NV40+ */ 6204 headerlen = dcbtable[1]; 6205 entries = dcbtable[2]; 6206 recordlength = dcbtable[3]; 6207 i2ctabptr = ROM16(dcbtable[4]); 6208 sig = ROM32(dcbtable[6]); 6209 dcb->gpio_table_ptr = ROM16(dcbtable[10]); 6210 dcb->connector_table_ptr = ROM16(dcbtable[20]); 6211 } else { 6212 i2ctabptr = ROM16(dcbtable[2]); 6213 sig = ROM32(dcbtable[4]); 6214 headerlen = 8; 6215 } 6216 6217 if (sig != 0x4edcbdcb) { 6218 NV_ERROR(dev, "Bad Display Configuration Block " 6219 "signature (%08X)\n", sig); 6220 return -EINVAL; 6221 } 6222 } else if (dcb->version >= 0x15) { /* some NV11 and NV20 */ 6223 char sig[8] = { 0 }; 6224 6225 strncpy(sig, (char *)&dcbtable[-7], 7); 6226 i2ctabptr = ROM16(dcbtable[2]); 6227 recordlength = 10; 6228 confofs = 6; 6229 6230 if (strcmp(sig, "DEV_REC")) { 6231 NV_ERROR(dev, "Bad Display Configuration Block " 6232 "signature (%s)\n", sig); 6233 return -EINVAL; 6234 } 6235 } else { 6236 /* 6237 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always 6238 * has the same single (crt) entry, even when tv-out present, so 6239 * the conclusion is this version cannot really be used. 6240 * v1.2 tables (some NV6/10, and NV15+) normally have the same 6241 * 5 entries, which are not specific to the card and so no use. 6242 * v1.2 does have an I2C table that read_dcb_i2c_table can 6243 * handle, but cards exist (nv11 in #14821) with a bad i2c table 6244 * pointer, so use the indices parsed in parse_bmp_structure. 6245 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful 6246 */ 6247 NV_TRACEWARN(dev, "No useful information in BIOS output table; " 6248 "adding all possible outputs\n"); 6249 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1); 6250 6251 /* 6252 * Attempt to detect TV before DVI because the test 6253 * for the former is more accurate and it rules the 6254 * latter out. 6255 */ 6256 if (nv04_tv_identify(dev, 6257 bios->legacy.i2c_indices.tv) >= 0) 6258 fabricate_tv_output(dcb, twoHeads); 6259 6260 else if (bios->tmds.output0_script_ptr || 6261 bios->tmds.output1_script_ptr) 6262 fabricate_dvi_i_output(dcb, twoHeads); 6263 6264 return 0; 6265 } 6266 6267 if (!i2ctabptr) 6268 NV_WARN(dev, "No pointer to DCB I2C port table\n"); 6269 else { 6270 dcb->i2c_table = &bios->data[i2ctabptr]; 6271 if (dcb->version >= 0x30) 6272 dcb->i2c_default_indices = dcb->i2c_table[4]; 6273 } 6274 6275 if (entries > DCB_MAX_NUM_ENTRIES) 6276 entries = DCB_MAX_NUM_ENTRIES; 6277 6278 for (i = 0; i < entries; i++) { 6279 uint32_t connection, config = 0; 6280 6281 connection = ROM32(dcbtable[headerlen + recordlength * i]); 6282 if (configblock) 6283 config = ROM32(dcbtable[headerlen + confofs + recordlength * i]); 6284 6285 /* seen on an NV11 with DCB v1.5 */ 6286 if (connection == 0x00000000) 6287 break; 6288 6289 /* seen on an NV17 with DCB v2.0 */ 6290 if (connection == 0xffffffff) 6291 break; 6292 6293 if ((connection & 0x0000000f) == 0x0000000f) 6294 continue; 6295 6296 if (!apply_dcb_encoder_quirks(dev, i, &connection, &config)) 6297 continue; 6298 6299 NV_TRACEWARN(dev, "Raw DCB entry %d: %08x %08x\n", 6300 dcb->entries, connection, config); 6301 6302 if (!parse_dcb_entry(dev, dcb, connection, config)) 6303 break; 6304 } 6305 6306 /* 6307 * apart for v2.1+ not being known for requiring merging, this 6308 * guarantees dcbent->index is the index of the entry in the rom image 6309 */ 6310 if (dcb->version < 0x21) 6311 merge_like_dcb_entries(dev, dcb); 6312 6313 if (!dcb->entries) 6314 return -ENXIO; 6315 6316 parse_dcb_gpio_table(bios); 6317 parse_dcb_connector_table(bios); 6318 return 0; 6319} 6320 6321static void 6322fixup_legacy_connector(struct nvbios *bios) 6323{ 6324 struct dcb_table *dcb = &bios->dcb; 6325 int i, i2c, i2c_conn[DCB_MAX_NUM_I2C_ENTRIES] = { }; 6326 6327 /* 6328 * DCB 3.0 also has the table in most cases, but there are some cards 6329 * where the table is filled with stub entries, and the DCB entriy 6330 * indices are all 0. We don't need the connector indices on pre-G80 6331 * chips (yet?) so limit the use to DCB 4.0 and above. 6332 */ 6333 if (dcb->version >= 0x40) 6334 return; 6335 6336 dcb->connector.entries = 0; 6337 6338 /* 6339 * No known connector info before v3.0, so make it up. the rule here 6340 * is: anything on the same i2c bus is considered to be on the same 6341 * connector. any output without an associated i2c bus is assigned 6342 * its own unique connector index. 6343 */ 6344 for (i = 0; i < dcb->entries; i++) { 6345 /* 6346 * Ignore the I2C index for on-chip TV-out, as there 6347 * are cards with bogus values (nv31m in bug 23212), 6348 * and it's otherwise useless. 6349 */ 6350 if (dcb->entry[i].type == OUTPUT_TV && 6351 dcb->entry[i].location == DCB_LOC_ON_CHIP) 6352 dcb->entry[i].i2c_index = 0xf; 6353 i2c = dcb->entry[i].i2c_index; 6354 6355 if (i2c_conn[i2c]) { 6356 dcb->entry[i].connector = i2c_conn[i2c] - 1; 6357 continue; 6358 } 6359 6360 dcb->entry[i].connector = dcb->connector.entries++; 6361 if (i2c != 0xf) 6362 i2c_conn[i2c] = dcb->connector.entries; 6363 } 6364 6365 /* Fake the connector table as well as just connector indices */ 6366 for (i = 0; i < dcb->connector.entries; i++) { 6367 dcb->connector.entry[i].index = i; 6368 dcb->connector.entry[i].type = divine_connector_type(bios, i); 6369 dcb->connector.entry[i].gpio_tag = 0xff; 6370 } 6371} 6372 6373static void 6374fixup_legacy_i2c(struct nvbios *bios) 6375{ 6376 struct dcb_table *dcb = &bios->dcb; 6377 int i; 6378 6379 for (i = 0; i < dcb->entries; i++) { 6380 if (dcb->entry[i].i2c_index == LEGACY_I2C_CRT) 6381 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.crt; 6382 if (dcb->entry[i].i2c_index == LEGACY_I2C_PANEL) 6383 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.panel; 6384 if (dcb->entry[i].i2c_index == LEGACY_I2C_TV) 6385 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.tv; 6386 } 6387} 6388 6389static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry) 6390{ 6391 /* 6392 * The header following the "HWSQ" signature has the number of entries, 6393 * and the entry size 6394 * 6395 * An entry consists of a dword to write to the sequencer control reg 6396 * (0x00001304), followed by the ucode bytes, written sequentially, 6397 * starting at reg 0x00001400 6398 */ 6399 6400 uint8_t bytes_to_write; 6401 uint16_t hwsq_entry_offset; 6402 int i; 6403 6404 if (bios->data[hwsq_offset] <= entry) { 6405 NV_ERROR(dev, "Too few entries in HW sequencer table for " 6406 "requested entry\n"); 6407 return -ENOENT; 6408 } 6409 6410 bytes_to_write = bios->data[hwsq_offset + 1]; 6411 6412 if (bytes_to_write != 36) { 6413 NV_ERROR(dev, "Unknown HW sequencer entry size\n"); 6414 return -EINVAL; 6415 } 6416 6417 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n"); 6418 6419 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write; 6420 6421 /* set sequencer control */ 6422 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset])); 6423 bytes_to_write -= 4; 6424 6425 /* write ucode */ 6426 for (i = 0; i < bytes_to_write; i += 4) 6427 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4])); 6428 6429 /* twiddle NV_PBUS_DEBUG_4 */ 6430 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18); 6431 6432 return 0; 6433} 6434 6435static int load_nv17_hw_sequencer_ucode(struct drm_device *dev, 6436 struct nvbios *bios) 6437{ 6438 /* 6439 * BMP based cards, from NV17, need a microcode loading to correctly 6440 * control the GPIO etc for LVDS panels 6441 * 6442 * BIT based cards seem to do this directly in the init scripts 6443 * 6444 * The microcode entries are found by the "HWSQ" signature. 6445 */ 6446 6447 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' }; 6448 const int sz = sizeof(hwsq_signature); 6449 int hwsq_offset; 6450 6451 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz); 6452 if (!hwsq_offset) 6453 return 0; 6454 6455 /* always use entry 0? */ 6456 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0); 6457} 6458 6459uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev) 6460{ 6461 struct drm_nouveau_private *dev_priv = dev->dev_private; 6462 struct nvbios *bios = &dev_priv->vbios; 6463 const uint8_t edid_sig[] = { 6464 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 }; 6465 uint16_t offset = 0; 6466 uint16_t newoffset; 6467 int searchlen = NV_PROM_SIZE; 6468 6469 if (bios->fp.edid) 6470 return bios->fp.edid; 6471 6472 while (searchlen) { 6473 newoffset = findstr(&bios->data[offset], searchlen, 6474 edid_sig, 8); 6475 if (!newoffset) 6476 return NULL; 6477 offset += newoffset; 6478 if (!nv_cksum(&bios->data[offset], EDID1_LEN)) 6479 break; 6480 6481 searchlen -= offset; 6482 offset++; 6483 } 6484 6485 NV_TRACE(dev, "Found EDID in BIOS\n"); 6486 6487 return bios->fp.edid = &bios->data[offset]; 6488} 6489 6490void 6491nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table, 6492 struct dcb_entry *dcbent) 6493{ 6494 struct drm_nouveau_private *dev_priv = dev->dev_private; 6495 struct nvbios *bios = &dev_priv->vbios; 6496 struct init_exec iexec = { true, false }; 6497 6498 mutex_lock(&bios->lock); 6499 bios->display.output = dcbent; 6500 parse_init_table(bios, table, &iexec); 6501 bios->display.output = NULL; 6502 mutex_unlock(&bios->lock); 6503} 6504 6505static bool NVInitVBIOS(struct drm_device *dev) 6506{ 6507 struct drm_nouveau_private *dev_priv = dev->dev_private; 6508 struct nvbios *bios = &dev_priv->vbios; 6509 6510 memset(bios, 0, sizeof(struct nvbios)); 6511 mutex_init(&bios->lock); 6512 bios->dev = dev; 6513 6514 if (!NVShadowVBIOS(dev, bios->data)) 6515 return false; 6516 6517 bios->length = NV_PROM_SIZE; 6518 return true; 6519} 6520 6521static int nouveau_parse_vbios_struct(struct drm_device *dev) 6522{ 6523 struct drm_nouveau_private *dev_priv = dev->dev_private; 6524 struct nvbios *bios = &dev_priv->vbios; 6525 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' }; 6526 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 }; 6527 int offset; 6528 6529 offset = findstr(bios->data, bios->length, 6530 bit_signature, sizeof(bit_signature)); 6531 if (offset) { 6532 NV_TRACE(dev, "BIT BIOS found\n"); 6533 return parse_bit_structure(bios, offset + 6); 6534 } 6535 6536 offset = findstr(bios->data, bios->length, 6537 bmp_signature, sizeof(bmp_signature)); 6538 if (offset) { 6539 NV_TRACE(dev, "BMP BIOS found\n"); 6540 return parse_bmp_structure(dev, bios, offset); 6541 } 6542 6543 NV_ERROR(dev, "No known BIOS signature found\n"); 6544 return -ENODEV; 6545} 6546 6547int 6548nouveau_run_vbios_init(struct drm_device *dev) 6549{ 6550 struct drm_nouveau_private *dev_priv = dev->dev_private; 6551 struct nvbios *bios = &dev_priv->vbios; 6552 int i, ret = 0; 6553 6554 /* Reset the BIOS head to 0. */ 6555 bios->state.crtchead = 0; 6556 6557 if (bios->major_version < 5) /* BMP only */ 6558 load_nv17_hw_sequencer_ucode(dev, bios); 6559 6560 if (bios->execute) { 6561 bios->fp.last_script_invoc = 0; 6562 bios->fp.lvds_init_run = false; 6563 } 6564 6565 parse_init_tables(bios); 6566 6567 /* 6568 * Runs some additional script seen on G8x VBIOSen. The VBIOS' 6569 * parser will run this right after the init tables, the binary 6570 * driver appears to run it at some point later. 6571 */ 6572 if (bios->some_script_ptr) { 6573 struct init_exec iexec = {true, false}; 6574 6575 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n", 6576 bios->some_script_ptr); 6577 parse_init_table(bios, bios->some_script_ptr, &iexec); 6578 } 6579 6580 if (dev_priv->card_type >= NV_50) { 6581 for (i = 0; i < bios->dcb.entries; i++) { 6582 nouveau_bios_run_display_table(dev, 6583 &bios->dcb.entry[i], 6584 0, 0); 6585 } 6586 } 6587 6588 return ret; 6589} 6590 6591static void 6592nouveau_bios_i2c_devices_takedown(struct drm_device *dev) 6593{ 6594 struct drm_nouveau_private *dev_priv = dev->dev_private; 6595 struct nvbios *bios = &dev_priv->vbios; 6596 struct dcb_i2c_entry *entry; 6597 int i; 6598 6599 entry = &bios->dcb.i2c[0]; 6600 for (i = 0; i < DCB_MAX_NUM_I2C_ENTRIES; i++, entry++) 6601 nouveau_i2c_fini(dev, entry); 6602} 6603 6604static bool 6605nouveau_bios_posted(struct drm_device *dev) 6606{ 6607 struct drm_nouveau_private *dev_priv = dev->dev_private; 6608 unsigned htotal; 6609 6610 if (dev_priv->chipset >= NV_50) { 6611 if (NVReadVgaCrtc(dev, 0, 0x00) == 0 && 6612 NVReadVgaCrtc(dev, 0, 0x1a) == 0) 6613 return false; 6614 return true; 6615 } 6616 6617 htotal = NVReadVgaCrtc(dev, 0, 0x06); 6618 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8; 6619 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4; 6620 htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10; 6621 htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11; 6622 6623 return (htotal != 0); 6624} 6625 6626int 6627nouveau_bios_init(struct drm_device *dev) 6628{ 6629 struct drm_nouveau_private *dev_priv = dev->dev_private; 6630 struct nvbios *bios = &dev_priv->vbios; 6631 int ret; 6632 6633 if (!NVInitVBIOS(dev)) 6634 return -ENODEV; 6635 6636 ret = nouveau_parse_vbios_struct(dev); 6637 if (ret) 6638 return ret; 6639 6640 ret = parse_dcb_table(dev, bios, nv_two_heads(dev)); 6641 if (ret) 6642 return ret; 6643 6644 fixup_legacy_i2c(bios); 6645 fixup_legacy_connector(bios); 6646 6647 if (!bios->major_version) /* we don't run version 0 bios */ 6648 return 0; 6649 6650 /* init script execution disabled */ 6651 bios->execute = false; 6652 6653 /* ... unless card isn't POSTed already */ 6654 if (!nouveau_bios_posted(dev)) { 6655 NV_INFO(dev, "Adaptor not initialised, " 6656 "running VBIOS init tables.\n"); 6657 bios->execute = true; 6658 } 6659 6660 ret = nouveau_run_vbios_init(dev); 6661 if (ret) 6662 return ret; 6663 6664 /* feature_byte on BMP is poor, but init always sets CR4B */ 6665 if (bios->major_version < 5) 6666 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40; 6667 6668 /* all BIT systems need p_f_m_t for digital_min_front_porch */ 6669 if (bios->is_mobile || bios->major_version >= 5) 6670 ret = parse_fp_mode_table(dev, bios); 6671 6672 /* allow subsequent scripts to execute */ 6673 bios->execute = true; 6674 6675 return 0; 6676} 6677 6678void 6679nouveau_bios_takedown(struct drm_device *dev) 6680{ 6681 nouveau_bios_i2c_devices_takedown(dev); 6682} 6683