nouveau_bios.c revision f3bbb9ccbf2a0362363ce6d7e4e57dbf34a5cef1
1/* 2 * Copyright 2005-2006 Erik Waling 3 * Copyright 2006 Stephane Marchesin 4 * Copyright 2007-2009 Stuart Bennett 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 25#include "drmP.h" 26#define NV_DEBUG_NOTRACE 27#include "nouveau_drv.h" 28#include "nouveau_hw.h" 29 30/* these defines are made up */ 31#define NV_CIO_CRE_44_HEADA 0x0 32#define NV_CIO_CRE_44_HEADB 0x3 33#define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */ 34#define LEGACY_I2C_CRT 0x80 35#define LEGACY_I2C_PANEL 0x81 36#define LEGACY_I2C_TV 0x82 37 38#define EDID1_LEN 128 39 40#define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg) 41#define LOG_OLD_VALUE(x) 42 43#define ROM16(x) le16_to_cpu(*(uint16_t *)&(x)) 44#define ROM32(x) le32_to_cpu(*(uint32_t *)&(x)) 45 46struct init_exec { 47 bool execute; 48 bool repeat; 49}; 50 51static bool nv_cksum(const uint8_t *data, unsigned int length) 52{ 53 /* 54 * There's a few checksums in the BIOS, so here's a generic checking 55 * function. 56 */ 57 int i; 58 uint8_t sum = 0; 59 60 for (i = 0; i < length; i++) 61 sum += data[i]; 62 63 if (sum) 64 return true; 65 66 return false; 67} 68 69static int 70score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable) 71{ 72 if (!(data[0] == 0x55 && data[1] == 0xAA)) { 73 NV_TRACEWARN(dev, "... BIOS signature not found\n"); 74 return 0; 75 } 76 77 if (nv_cksum(data, data[2] * 512)) { 78 NV_TRACEWARN(dev, "... BIOS checksum invalid\n"); 79 /* if a ro image is somewhat bad, it's probably all rubbish */ 80 return writeable ? 2 : 1; 81 } else 82 NV_TRACE(dev, "... appears to be valid\n"); 83 84 return 3; 85} 86 87static void load_vbios_prom(struct drm_device *dev, uint8_t *data) 88{ 89 struct drm_nouveau_private *dev_priv = dev->dev_private; 90 uint32_t pci_nv_20, save_pci_nv_20; 91 int pcir_ptr; 92 int i; 93 94 if (dev_priv->card_type >= NV_50) 95 pci_nv_20 = 0x88050; 96 else 97 pci_nv_20 = NV_PBUS_PCI_NV_20; 98 99 /* enable ROM access */ 100 save_pci_nv_20 = nvReadMC(dev, pci_nv_20); 101 nvWriteMC(dev, pci_nv_20, 102 save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED); 103 104 /* bail if no rom signature */ 105 if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 || 106 nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa) 107 goto out; 108 109 /* additional check (see note below) - read PCI record header */ 110 pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) | 111 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8; 112 if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' || 113 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' || 114 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' || 115 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R') 116 goto out; 117 118 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a 119 * a good read may be obtained by waiting or re-reading (cargocult: 5x) 120 * each byte. we'll hope pramin has something usable instead 121 */ 122 for (i = 0; i < NV_PROM_SIZE; i++) 123 data[i] = nv_rd08(dev, NV_PROM_OFFSET + i); 124 125out: 126 /* disable ROM access */ 127 nvWriteMC(dev, pci_nv_20, 128 save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED); 129} 130 131static void load_vbios_pramin(struct drm_device *dev, uint8_t *data) 132{ 133 struct drm_nouveau_private *dev_priv = dev->dev_private; 134 uint32_t old_bar0_pramin = 0; 135 int i; 136 137 if (dev_priv->card_type >= NV_50) { 138 uint32_t vbios_vram = (nv_rd32(dev, 0x619f04) & ~0xff) << 8; 139 140 if (!vbios_vram) 141 vbios_vram = (nv_rd32(dev, 0x1700) << 16) + 0xf0000; 142 143 old_bar0_pramin = nv_rd32(dev, 0x1700); 144 nv_wr32(dev, 0x1700, vbios_vram >> 16); 145 } 146 147 /* bail if no rom signature */ 148 if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 || 149 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa) 150 goto out; 151 152 for (i = 0; i < NV_PROM_SIZE; i++) 153 data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i); 154 155out: 156 if (dev_priv->card_type >= NV_50) 157 nv_wr32(dev, 0x1700, old_bar0_pramin); 158} 159 160static void load_vbios_pci(struct drm_device *dev, uint8_t *data) 161{ 162 void __iomem *rom = NULL; 163 size_t rom_len; 164 int ret; 165 166 ret = pci_enable_rom(dev->pdev); 167 if (ret) 168 return; 169 170 rom = pci_map_rom(dev->pdev, &rom_len); 171 if (!rom) 172 goto out; 173 memcpy_fromio(data, rom, rom_len); 174 pci_unmap_rom(dev->pdev, rom); 175 176out: 177 pci_disable_rom(dev->pdev); 178} 179 180struct methods { 181 const char desc[8]; 182 void (*loadbios)(struct drm_device *, uint8_t *); 183 const bool rw; 184}; 185 186static struct methods nv04_methods[] = { 187 { "PROM", load_vbios_prom, false }, 188 { "PRAMIN", load_vbios_pramin, true }, 189 { "PCIROM", load_vbios_pci, true }, 190}; 191 192static struct methods nv50_methods[] = { 193 { "PRAMIN", load_vbios_pramin, true }, 194 { "PROM", load_vbios_prom, false }, 195 { "PCIROM", load_vbios_pci, true }, 196}; 197 198#define METHODCNT 3 199 200static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data) 201{ 202 struct drm_nouveau_private *dev_priv = dev->dev_private; 203 struct methods *methods; 204 int i; 205 int testscore = 3; 206 int scores[METHODCNT]; 207 208 if (nouveau_vbios) { 209 methods = nv04_methods; 210 for (i = 0; i < METHODCNT; i++) 211 if (!strcasecmp(nouveau_vbios, methods[i].desc)) 212 break; 213 214 if (i < METHODCNT) { 215 NV_INFO(dev, "Attempting to use BIOS image from %s\n", 216 methods[i].desc); 217 218 methods[i].loadbios(dev, data); 219 if (score_vbios(dev, data, methods[i].rw)) 220 return true; 221 } 222 223 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios); 224 } 225 226 if (dev_priv->card_type < NV_50) 227 methods = nv04_methods; 228 else 229 methods = nv50_methods; 230 231 for (i = 0; i < METHODCNT; i++) { 232 NV_TRACE(dev, "Attempting to load BIOS image from %s\n", 233 methods[i].desc); 234 data[0] = data[1] = 0; /* avoid reuse of previous image */ 235 methods[i].loadbios(dev, data); 236 scores[i] = score_vbios(dev, data, methods[i].rw); 237 if (scores[i] == testscore) 238 return true; 239 } 240 241 while (--testscore > 0) { 242 for (i = 0; i < METHODCNT; i++) { 243 if (scores[i] == testscore) { 244 NV_TRACE(dev, "Using BIOS image from %s\n", 245 methods[i].desc); 246 methods[i].loadbios(dev, data); 247 return true; 248 } 249 } 250 } 251 252 NV_ERROR(dev, "No valid BIOS image found\n"); 253 return false; 254} 255 256struct init_tbl_entry { 257 char *name; 258 uint8_t id; 259 int (*handler)(struct nvbios *, uint16_t, struct init_exec *); 260}; 261 262struct bit_entry { 263 uint8_t id[2]; 264 uint16_t length; 265 uint16_t offset; 266}; 267 268static int parse_init_table(struct nvbios *, unsigned int, struct init_exec *); 269 270#define MACRO_INDEX_SIZE 2 271#define MACRO_SIZE 8 272#define CONDITION_SIZE 12 273#define IO_FLAG_CONDITION_SIZE 9 274#define IO_CONDITION_SIZE 5 275#define MEM_INIT_SIZE 66 276 277static void still_alive(void) 278{ 279#if 0 280 sync(); 281 msleep(2); 282#endif 283} 284 285static uint32_t 286munge_reg(struct nvbios *bios, uint32_t reg) 287{ 288 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 289 struct dcb_entry *dcbent = bios->display.output; 290 291 if (dev_priv->card_type < NV_50) 292 return reg; 293 294 if (reg & 0x40000000) { 295 BUG_ON(!dcbent); 296 297 reg += (ffs(dcbent->or) - 1) * 0x800; 298 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1)) 299 reg += 0x00000080; 300 } 301 302 reg &= ~0x60000000; 303 return reg; 304} 305 306static int 307valid_reg(struct nvbios *bios, uint32_t reg) 308{ 309 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 310 struct drm_device *dev = bios->dev; 311 312 /* C51 has misaligned regs on purpose. Marvellous */ 313 if (reg & 0x2 || 314 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51)) 315 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg); 316 317 /* warn on C51 regs that haven't been verified accessible in tracing */ 318 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 && 319 reg != 0x130d && reg != 0x1311 && reg != 0x60081d) 320 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n", 321 reg); 322 323 if (reg >= (8*1024*1024)) { 324 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg); 325 return 0; 326 } 327 328 return 1; 329} 330 331static bool 332valid_idx_port(struct nvbios *bios, uint16_t port) 333{ 334 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 335 struct drm_device *dev = bios->dev; 336 337 /* 338 * If adding more ports here, the read/write functions below will need 339 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is 340 * used for the port in question 341 */ 342 if (dev_priv->card_type < NV_50) { 343 if (port == NV_CIO_CRX__COLOR) 344 return true; 345 if (port == NV_VIO_SRX) 346 return true; 347 } else { 348 if (port == NV_CIO_CRX__COLOR) 349 return true; 350 } 351 352 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n", 353 port); 354 355 return false; 356} 357 358static bool 359valid_port(struct nvbios *bios, uint16_t port) 360{ 361 struct drm_device *dev = bios->dev; 362 363 /* 364 * If adding more ports here, the read/write functions below will need 365 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is 366 * used for the port in question 367 */ 368 if (port == NV_VIO_VSE2) 369 return true; 370 371 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port); 372 373 return false; 374} 375 376static uint32_t 377bios_rd32(struct nvbios *bios, uint32_t reg) 378{ 379 uint32_t data; 380 381 reg = munge_reg(bios, reg); 382 if (!valid_reg(bios, reg)) 383 return 0; 384 385 /* 386 * C51 sometimes uses regs with bit0 set in the address. For these 387 * cases there should exist a translation in a BIOS table to an IO 388 * port address which the BIOS uses for accessing the reg 389 * 390 * These only seem to appear for the power control regs to a flat panel, 391 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs 392 * for 0x1308 and 0x1310 are used - hence the mask below. An S3 393 * suspend-resume mmio trace from a C51 will be required to see if this 394 * is true for the power microcode in 0x14.., or whether the direct IO 395 * port access method is needed 396 */ 397 if (reg & 0x1) 398 reg &= ~0x1; 399 400 data = nv_rd32(bios->dev, reg); 401 402 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data); 403 404 return data; 405} 406 407static void 408bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data) 409{ 410 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 411 412 reg = munge_reg(bios, reg); 413 if (!valid_reg(bios, reg)) 414 return; 415 416 /* see note in bios_rd32 */ 417 if (reg & 0x1) 418 reg &= 0xfffffffe; 419 420 LOG_OLD_VALUE(bios_rd32(bios, reg)); 421 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data); 422 423 if (dev_priv->vbios.execute) { 424 still_alive(); 425 nv_wr32(bios->dev, reg, data); 426 } 427} 428 429static uint8_t 430bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index) 431{ 432 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 433 struct drm_device *dev = bios->dev; 434 uint8_t data; 435 436 if (!valid_idx_port(bios, port)) 437 return 0; 438 439 if (dev_priv->card_type < NV_50) { 440 if (port == NV_VIO_SRX) 441 data = NVReadVgaSeq(dev, bios->state.crtchead, index); 442 else /* assume NV_CIO_CRX__COLOR */ 443 data = NVReadVgaCrtc(dev, bios->state.crtchead, index); 444 } else { 445 uint32_t data32; 446 447 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3)); 448 data = (data32 >> ((index & 3) << 3)) & 0xff; 449 } 450 451 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, " 452 "Head: 0x%02X, Data: 0x%02X\n", 453 port, index, bios->state.crtchead, data); 454 return data; 455} 456 457static void 458bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data) 459{ 460 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 461 struct drm_device *dev = bios->dev; 462 463 if (!valid_idx_port(bios, port)) 464 return; 465 466 /* 467 * The current head is maintained in the nvbios member state.crtchead. 468 * We trap changes to CR44 and update the head variable and hence the 469 * register set written. 470 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance 471 * of the write, and to head1 after the write 472 */ 473 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 && 474 data != NV_CIO_CRE_44_HEADB) 475 bios->state.crtchead = 0; 476 477 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index)); 478 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, " 479 "Head: 0x%02X, Data: 0x%02X\n", 480 port, index, bios->state.crtchead, data); 481 482 if (bios->execute && dev_priv->card_type < NV_50) { 483 still_alive(); 484 if (port == NV_VIO_SRX) 485 NVWriteVgaSeq(dev, bios->state.crtchead, index, data); 486 else /* assume NV_CIO_CRX__COLOR */ 487 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data); 488 } else 489 if (bios->execute) { 490 uint32_t data32, shift = (index & 3) << 3; 491 492 still_alive(); 493 494 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3)); 495 data32 &= ~(0xff << shift); 496 data32 |= (data << shift); 497 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32); 498 } 499 500 if (port == NV_CIO_CRX__COLOR && 501 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB) 502 bios->state.crtchead = 1; 503} 504 505static uint8_t 506bios_port_rd(struct nvbios *bios, uint16_t port) 507{ 508 uint8_t data, head = bios->state.crtchead; 509 510 if (!valid_port(bios, port)) 511 return 0; 512 513 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port); 514 515 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n", 516 port, head, data); 517 518 return data; 519} 520 521static void 522bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data) 523{ 524 int head = bios->state.crtchead; 525 526 if (!valid_port(bios, port)) 527 return; 528 529 LOG_OLD_VALUE(bios_port_rd(bios, port)); 530 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n", 531 port, head, data); 532 533 if (!bios->execute) 534 return; 535 536 still_alive(); 537 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data); 538} 539 540static bool 541io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 542{ 543 /* 544 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte 545 * for the CRTC index; 1 byte for the mask to apply to the value 546 * retrieved from the CRTC; 1 byte for the shift right to apply to the 547 * masked CRTC value; 2 bytes for the offset to the flag array, to 548 * which the shifted value is added; 1 byte for the mask applied to the 549 * value read from the flag array; and 1 byte for the value to compare 550 * against the masked byte from the flag table. 551 */ 552 553 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE; 554 uint16_t crtcport = ROM16(bios->data[condptr]); 555 uint8_t crtcindex = bios->data[condptr + 2]; 556 uint8_t mask = bios->data[condptr + 3]; 557 uint8_t shift = bios->data[condptr + 4]; 558 uint16_t flagarray = ROM16(bios->data[condptr + 5]); 559 uint8_t flagarraymask = bios->data[condptr + 7]; 560 uint8_t cmpval = bios->data[condptr + 8]; 561 uint8_t data; 562 563 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 564 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, " 565 "Cmpval: 0x%02X\n", 566 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval); 567 568 data = bios_idxprt_rd(bios, crtcport, crtcindex); 569 570 data = bios->data[flagarray + ((data & mask) >> shift)]; 571 data &= flagarraymask; 572 573 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n", 574 offset, data, cmpval); 575 576 return (data == cmpval); 577} 578 579static bool 580bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 581{ 582 /* 583 * The condition table entry has 4 bytes for the address of the 584 * register to check, 4 bytes for a mask to apply to the register and 585 * 4 for a test comparison value 586 */ 587 588 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE; 589 uint32_t reg = ROM32(bios->data[condptr]); 590 uint32_t mask = ROM32(bios->data[condptr + 4]); 591 uint32_t cmpval = ROM32(bios->data[condptr + 8]); 592 uint32_t data; 593 594 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n", 595 offset, cond, reg, mask); 596 597 data = bios_rd32(bios, reg) & mask; 598 599 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n", 600 offset, data, cmpval); 601 602 return (data == cmpval); 603} 604 605static bool 606io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 607{ 608 /* 609 * The IO condition entry has 2 bytes for the IO port address; 1 byte 610 * for the index to write to io_port; 1 byte for the mask to apply to 611 * the byte read from io_port+1; and 1 byte for the value to compare 612 * against the masked byte. 613 */ 614 615 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE; 616 uint16_t io_port = ROM16(bios->data[condptr]); 617 uint8_t port_index = bios->data[condptr + 2]; 618 uint8_t mask = bios->data[condptr + 3]; 619 uint8_t cmpval = bios->data[condptr + 4]; 620 621 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask; 622 623 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n", 624 offset, data, cmpval); 625 626 return (data == cmpval); 627} 628 629static int 630nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk) 631{ 632 struct drm_nouveau_private *dev_priv = dev->dev_private; 633 uint32_t reg0 = nv_rd32(dev, reg + 0); 634 uint32_t reg1 = nv_rd32(dev, reg + 4); 635 struct nouveau_pll_vals pll; 636 struct pll_lims pll_limits; 637 int ret; 638 639 ret = get_pll_limits(dev, reg, &pll_limits); 640 if (ret) 641 return ret; 642 643 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll); 644 if (!clk) 645 return -ERANGE; 646 647 reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16); 648 reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1; 649 650 if (dev_priv->vbios.execute) { 651 still_alive(); 652 nv_wr32(dev, reg + 4, reg1); 653 nv_wr32(dev, reg + 0, reg0); 654 } 655 656 return 0; 657} 658 659static int 660setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk) 661{ 662 struct drm_device *dev = bios->dev; 663 struct drm_nouveau_private *dev_priv = dev->dev_private; 664 /* clk in kHz */ 665 struct pll_lims pll_lim; 666 struct nouveau_pll_vals pllvals; 667 int ret; 668 669 if (dev_priv->card_type >= NV_50) 670 return nv50_pll_set(dev, reg, clk); 671 672 /* high regs (such as in the mac g5 table) are not -= 4 */ 673 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim); 674 if (ret) 675 return ret; 676 677 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals); 678 if (!clk) 679 return -ERANGE; 680 681 if (bios->execute) { 682 still_alive(); 683 nouveau_hw_setpll(dev, reg, &pllvals); 684 } 685 686 return 0; 687} 688 689static int dcb_entry_idx_from_crtchead(struct drm_device *dev) 690{ 691 struct drm_nouveau_private *dev_priv = dev->dev_private; 692 struct nvbios *bios = &dev_priv->vbios; 693 694 /* 695 * For the results of this function to be correct, CR44 must have been 696 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0, 697 * and the DCB table parsed, before the script calling the function is 698 * run. run_digital_op_script is example of how to do such setup 699 */ 700 701 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0); 702 703 if (dcb_entry > bios->dcb.entries) { 704 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently " 705 "(%02X)\n", dcb_entry); 706 dcb_entry = 0x7f; /* unused / invalid marker */ 707 } 708 709 return dcb_entry; 710} 711 712static struct nouveau_i2c_chan * 713init_i2c_device_find(struct drm_device *dev, int i2c_index) 714{ 715 struct drm_nouveau_private *dev_priv = dev->dev_private; 716 struct dcb_table *dcb = &dev_priv->vbios.dcb; 717 718 if (i2c_index == 0xff) { 719 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */ 720 int idx = dcb_entry_idx_from_crtchead(dev), shift = 0; 721 int default_indices = dcb->i2c_default_indices; 722 723 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default) 724 shift = 4; 725 726 i2c_index = (default_indices >> shift) & 0xf; 727 } 728 if (i2c_index == 0x80) /* g80+ */ 729 i2c_index = dcb->i2c_default_indices & 0xf; 730 731 return nouveau_i2c_find(dev, i2c_index); 732} 733 734static uint32_t 735get_tmds_index_reg(struct drm_device *dev, uint8_t mlv) 736{ 737 /* 738 * For mlv < 0x80, it is an index into a table of TMDS base addresses. 739 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by 740 * CR58 for CR57 = 0 to index a table of offsets to the basic 741 * 0x6808b0 address. 742 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by 743 * CR58 for CR57 = 0 to index a table of offsets to the basic 744 * 0x6808b0 address, and then flip the offset by 8. 745 */ 746 747 struct drm_nouveau_private *dev_priv = dev->dev_private; 748 struct nvbios *bios = &dev_priv->vbios; 749 const int pramdac_offset[13] = { 750 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 }; 751 const uint32_t pramdac_table[4] = { 752 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 }; 753 754 if (mlv >= 0x80) { 755 int dcb_entry, dacoffset; 756 757 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */ 758 dcb_entry = dcb_entry_idx_from_crtchead(dev); 759 if (dcb_entry == 0x7f) 760 return 0; 761 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or]; 762 if (mlv == 0x81) 763 dacoffset ^= 8; 764 return 0x6808b0 + dacoffset; 765 } else { 766 if (mlv >= ARRAY_SIZE(pramdac_table)) { 767 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n", 768 mlv); 769 return 0; 770 } 771 return pramdac_table[mlv]; 772 } 773} 774 775static int 776init_io_restrict_prog(struct nvbios *bios, uint16_t offset, 777 struct init_exec *iexec) 778{ 779 /* 780 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2') 781 * 782 * offset (8 bit): opcode 783 * offset + 1 (16 bit): CRTC port 784 * offset + 3 (8 bit): CRTC index 785 * offset + 4 (8 bit): mask 786 * offset + 5 (8 bit): shift 787 * offset + 6 (8 bit): count 788 * offset + 7 (32 bit): register 789 * offset + 11 (32 bit): configuration 1 790 * ... 791 * 792 * Starting at offset + 11 there are "count" 32 bit values. 793 * To find out which value to use read index "CRTC index" on "CRTC 794 * port", AND this value with "mask" and then bit shift right "shift" 795 * bits. Read the appropriate value using this index and write to 796 * "register" 797 */ 798 799 uint16_t crtcport = ROM16(bios->data[offset + 1]); 800 uint8_t crtcindex = bios->data[offset + 3]; 801 uint8_t mask = bios->data[offset + 4]; 802 uint8_t shift = bios->data[offset + 5]; 803 uint8_t count = bios->data[offset + 6]; 804 uint32_t reg = ROM32(bios->data[offset + 7]); 805 uint8_t config; 806 uint32_t configval; 807 int len = 11 + count * 4; 808 809 if (!iexec->execute) 810 return len; 811 812 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 813 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n", 814 offset, crtcport, crtcindex, mask, shift, count, reg); 815 816 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 817 if (config > count) { 818 NV_ERROR(bios->dev, 819 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 820 offset, config, count); 821 return 0; 822 } 823 824 configval = ROM32(bios->data[offset + 11 + config * 4]); 825 826 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config); 827 828 bios_wr32(bios, reg, configval); 829 830 return len; 831} 832 833static int 834init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 835{ 836 /* 837 * INIT_REPEAT opcode: 0x33 ('3') 838 * 839 * offset (8 bit): opcode 840 * offset + 1 (8 bit): count 841 * 842 * Execute script following this opcode up to INIT_REPEAT_END 843 * "count" times 844 */ 845 846 uint8_t count = bios->data[offset + 1]; 847 uint8_t i; 848 849 /* no iexec->execute check by design */ 850 851 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n", 852 offset, count); 853 854 iexec->repeat = true; 855 856 /* 857 * count - 1, as the script block will execute once when we leave this 858 * opcode -- this is compatible with bios behaviour as: 859 * a) the block is always executed at least once, even if count == 0 860 * b) the bios interpreter skips to the op following INIT_END_REPEAT, 861 * while we don't 862 */ 863 for (i = 0; i < count - 1; i++) 864 parse_init_table(bios, offset + 2, iexec); 865 866 iexec->repeat = false; 867 868 return 2; 869} 870 871static int 872init_io_restrict_pll(struct nvbios *bios, uint16_t offset, 873 struct init_exec *iexec) 874{ 875 /* 876 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4') 877 * 878 * offset (8 bit): opcode 879 * offset + 1 (16 bit): CRTC port 880 * offset + 3 (8 bit): CRTC index 881 * offset + 4 (8 bit): mask 882 * offset + 5 (8 bit): shift 883 * offset + 6 (8 bit): IO flag condition index 884 * offset + 7 (8 bit): count 885 * offset + 8 (32 bit): register 886 * offset + 12 (16 bit): frequency 1 887 * ... 888 * 889 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz). 890 * Set PLL register "register" to coefficients for frequency n, 891 * selected by reading index "CRTC index" of "CRTC port" ANDed with 892 * "mask" and shifted right by "shift". 893 * 894 * If "IO flag condition index" > 0, and condition met, double 895 * frequency before setting it. 896 */ 897 898 uint16_t crtcport = ROM16(bios->data[offset + 1]); 899 uint8_t crtcindex = bios->data[offset + 3]; 900 uint8_t mask = bios->data[offset + 4]; 901 uint8_t shift = bios->data[offset + 5]; 902 int8_t io_flag_condition_idx = bios->data[offset + 6]; 903 uint8_t count = bios->data[offset + 7]; 904 uint32_t reg = ROM32(bios->data[offset + 8]); 905 uint8_t config; 906 uint16_t freq; 907 int len = 12 + count * 2; 908 909 if (!iexec->execute) 910 return len; 911 912 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 913 "Shift: 0x%02X, IO Flag Condition: 0x%02X, " 914 "Count: 0x%02X, Reg: 0x%08X\n", 915 offset, crtcport, crtcindex, mask, shift, 916 io_flag_condition_idx, count, reg); 917 918 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 919 if (config > count) { 920 NV_ERROR(bios->dev, 921 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 922 offset, config, count); 923 return 0; 924 } 925 926 freq = ROM16(bios->data[offset + 12 + config * 2]); 927 928 if (io_flag_condition_idx > 0) { 929 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) { 930 BIOSLOG(bios, "0x%04X: Condition fulfilled -- " 931 "frequency doubled\n", offset); 932 freq *= 2; 933 } else 934 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- " 935 "frequency unchanged\n", offset); 936 } 937 938 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n", 939 offset, reg, config, freq); 940 941 setPLL(bios, reg, freq * 10); 942 943 return len; 944} 945 946static int 947init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 948{ 949 /* 950 * INIT_END_REPEAT opcode: 0x36 ('6') 951 * 952 * offset (8 bit): opcode 953 * 954 * Marks the end of the block for INIT_REPEAT to repeat 955 */ 956 957 /* no iexec->execute check by design */ 958 959 /* 960 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when 961 * we're not in repeat mode 962 */ 963 if (iexec->repeat) 964 return 0; 965 966 return 1; 967} 968 969static int 970init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 971{ 972 /* 973 * INIT_COPY opcode: 0x37 ('7') 974 * 975 * offset (8 bit): opcode 976 * offset + 1 (32 bit): register 977 * offset + 5 (8 bit): shift 978 * offset + 6 (8 bit): srcmask 979 * offset + 7 (16 bit): CRTC port 980 * offset + 9 (8 bit): CRTC index 981 * offset + 10 (8 bit): mask 982 * 983 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with 984 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC 985 * port 986 */ 987 988 uint32_t reg = ROM32(bios->data[offset + 1]); 989 uint8_t shift = bios->data[offset + 5]; 990 uint8_t srcmask = bios->data[offset + 6]; 991 uint16_t crtcport = ROM16(bios->data[offset + 7]); 992 uint8_t crtcindex = bios->data[offset + 9]; 993 uint8_t mask = bios->data[offset + 10]; 994 uint32_t data; 995 uint8_t crtcdata; 996 997 if (!iexec->execute) 998 return 11; 999 1000 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, " 1001 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n", 1002 offset, reg, shift, srcmask, crtcport, crtcindex, mask); 1003 1004 data = bios_rd32(bios, reg); 1005 1006 if (shift < 0x80) 1007 data >>= shift; 1008 else 1009 data <<= (0x100 - shift); 1010 1011 data &= srcmask; 1012 1013 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask; 1014 crtcdata |= (uint8_t)data; 1015 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata); 1016 1017 return 11; 1018} 1019 1020static int 1021init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1022{ 1023 /* 1024 * INIT_NOT opcode: 0x38 ('8') 1025 * 1026 * offset (8 bit): opcode 1027 * 1028 * Invert the current execute / no-execute condition (i.e. "else") 1029 */ 1030 if (iexec->execute) 1031 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset); 1032 else 1033 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset); 1034 1035 iexec->execute = !iexec->execute; 1036 return 1; 1037} 1038 1039static int 1040init_io_flag_condition(struct nvbios *bios, uint16_t offset, 1041 struct init_exec *iexec) 1042{ 1043 /* 1044 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9') 1045 * 1046 * offset (8 bit): opcode 1047 * offset + 1 (8 bit): condition number 1048 * 1049 * Check condition "condition number" in the IO flag condition table. 1050 * If condition not met skip subsequent opcodes until condition is 1051 * inverted (INIT_NOT), or we hit INIT_RESUME 1052 */ 1053 1054 uint8_t cond = bios->data[offset + 1]; 1055 1056 if (!iexec->execute) 1057 return 2; 1058 1059 if (io_flag_condition_met(bios, offset, cond)) 1060 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 1061 else { 1062 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 1063 iexec->execute = false; 1064 } 1065 1066 return 2; 1067} 1068 1069static int 1070init_idx_addr_latched(struct nvbios *bios, uint16_t offset, 1071 struct init_exec *iexec) 1072{ 1073 /* 1074 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I') 1075 * 1076 * offset (8 bit): opcode 1077 * offset + 1 (32 bit): control register 1078 * offset + 5 (32 bit): data register 1079 * offset + 9 (32 bit): mask 1080 * offset + 13 (32 bit): data 1081 * offset + 17 (8 bit): count 1082 * offset + 18 (8 bit): address 1 1083 * offset + 19 (8 bit): data 1 1084 * ... 1085 * 1086 * For each of "count" address and data pairs, write "data n" to 1087 * "data register", read the current value of "control register", 1088 * and write it back once ANDed with "mask", ORed with "data", 1089 * and ORed with "address n" 1090 */ 1091 1092 uint32_t controlreg = ROM32(bios->data[offset + 1]); 1093 uint32_t datareg = ROM32(bios->data[offset + 5]); 1094 uint32_t mask = ROM32(bios->data[offset + 9]); 1095 uint32_t data = ROM32(bios->data[offset + 13]); 1096 uint8_t count = bios->data[offset + 17]; 1097 int len = 18 + count * 2; 1098 uint32_t value; 1099 int i; 1100 1101 if (!iexec->execute) 1102 return len; 1103 1104 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, " 1105 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n", 1106 offset, controlreg, datareg, mask, data, count); 1107 1108 for (i = 0; i < count; i++) { 1109 uint8_t instaddress = bios->data[offset + 18 + i * 2]; 1110 uint8_t instdata = bios->data[offset + 19 + i * 2]; 1111 1112 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n", 1113 offset, instaddress, instdata); 1114 1115 bios_wr32(bios, datareg, instdata); 1116 value = bios_rd32(bios, controlreg) & mask; 1117 value |= data; 1118 value |= instaddress; 1119 bios_wr32(bios, controlreg, value); 1120 } 1121 1122 return len; 1123} 1124 1125static int 1126init_io_restrict_pll2(struct nvbios *bios, uint16_t offset, 1127 struct init_exec *iexec) 1128{ 1129 /* 1130 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J') 1131 * 1132 * offset (8 bit): opcode 1133 * offset + 1 (16 bit): CRTC port 1134 * offset + 3 (8 bit): CRTC index 1135 * offset + 4 (8 bit): mask 1136 * offset + 5 (8 bit): shift 1137 * offset + 6 (8 bit): count 1138 * offset + 7 (32 bit): register 1139 * offset + 11 (32 bit): frequency 1 1140 * ... 1141 * 1142 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz). 1143 * Set PLL register "register" to coefficients for frequency n, 1144 * selected by reading index "CRTC index" of "CRTC port" ANDed with 1145 * "mask" and shifted right by "shift". 1146 */ 1147 1148 uint16_t crtcport = ROM16(bios->data[offset + 1]); 1149 uint8_t crtcindex = bios->data[offset + 3]; 1150 uint8_t mask = bios->data[offset + 4]; 1151 uint8_t shift = bios->data[offset + 5]; 1152 uint8_t count = bios->data[offset + 6]; 1153 uint32_t reg = ROM32(bios->data[offset + 7]); 1154 int len = 11 + count * 4; 1155 uint8_t config; 1156 uint32_t freq; 1157 1158 if (!iexec->execute) 1159 return len; 1160 1161 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 1162 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n", 1163 offset, crtcport, crtcindex, mask, shift, count, reg); 1164 1165 if (!reg) 1166 return len; 1167 1168 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 1169 if (config > count) { 1170 NV_ERROR(bios->dev, 1171 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 1172 offset, config, count); 1173 return 0; 1174 } 1175 1176 freq = ROM32(bios->data[offset + 11 + config * 4]); 1177 1178 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n", 1179 offset, reg, config, freq); 1180 1181 setPLL(bios, reg, freq); 1182 1183 return len; 1184} 1185 1186static int 1187init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1188{ 1189 /* 1190 * INIT_PLL2 opcode: 0x4B ('K') 1191 * 1192 * offset (8 bit): opcode 1193 * offset + 1 (32 bit): register 1194 * offset + 5 (32 bit): freq 1195 * 1196 * Set PLL register "register" to coefficients for frequency "freq" 1197 */ 1198 1199 uint32_t reg = ROM32(bios->data[offset + 1]); 1200 uint32_t freq = ROM32(bios->data[offset + 5]); 1201 1202 if (!iexec->execute) 1203 return 9; 1204 1205 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n", 1206 offset, reg, freq); 1207 1208 setPLL(bios, reg, freq); 1209 return 9; 1210} 1211 1212static int 1213init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1214{ 1215 /* 1216 * INIT_I2C_BYTE opcode: 0x4C ('L') 1217 * 1218 * offset (8 bit): opcode 1219 * offset + 1 (8 bit): DCB I2C table entry index 1220 * offset + 2 (8 bit): I2C slave address 1221 * offset + 3 (8 bit): count 1222 * offset + 4 (8 bit): I2C register 1 1223 * offset + 5 (8 bit): mask 1 1224 * offset + 6 (8 bit): data 1 1225 * ... 1226 * 1227 * For each of "count" registers given by "I2C register n" on the device 1228 * addressed by "I2C slave address" on the I2C bus given by 1229 * "DCB I2C table entry index", read the register, AND the result with 1230 * "mask n" and OR it with "data n" before writing it back to the device 1231 */ 1232 1233 uint8_t i2c_index = bios->data[offset + 1]; 1234 uint8_t i2c_address = bios->data[offset + 2]; 1235 uint8_t count = bios->data[offset + 3]; 1236 int len = 4 + count * 3; 1237 struct nouveau_i2c_chan *chan; 1238 struct i2c_msg msg; 1239 int i; 1240 1241 if (!iexec->execute) 1242 return len; 1243 1244 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1245 "Count: 0x%02X\n", 1246 offset, i2c_index, i2c_address, count); 1247 1248 chan = init_i2c_device_find(bios->dev, i2c_index); 1249 if (!chan) 1250 return 0; 1251 1252 for (i = 0; i < count; i++) { 1253 uint8_t i2c_reg = bios->data[offset + 4 + i * 3]; 1254 uint8_t mask = bios->data[offset + 5 + i * 3]; 1255 uint8_t data = bios->data[offset + 6 + i * 3]; 1256 uint8_t value; 1257 1258 msg.addr = i2c_address; 1259 msg.flags = I2C_M_RD; 1260 msg.len = 1; 1261 msg.buf = &value; 1262 if (i2c_transfer(&chan->adapter, &msg, 1) != 1) 1263 return 0; 1264 1265 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, " 1266 "Mask: 0x%02X, Data: 0x%02X\n", 1267 offset, i2c_reg, value, mask, data); 1268 1269 value = (value & mask) | data; 1270 1271 if (bios->execute) { 1272 msg.addr = i2c_address; 1273 msg.flags = 0; 1274 msg.len = 1; 1275 msg.buf = &value; 1276 if (i2c_transfer(&chan->adapter, &msg, 1) != 1) 1277 return 0; 1278 } 1279 } 1280 1281 return len; 1282} 1283 1284static int 1285init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1286{ 1287 /* 1288 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M') 1289 * 1290 * offset (8 bit): opcode 1291 * offset + 1 (8 bit): DCB I2C table entry index 1292 * offset + 2 (8 bit): I2C slave address 1293 * offset + 3 (8 bit): count 1294 * offset + 4 (8 bit): I2C register 1 1295 * offset + 5 (8 bit): data 1 1296 * ... 1297 * 1298 * For each of "count" registers given by "I2C register n" on the device 1299 * addressed by "I2C slave address" on the I2C bus given by 1300 * "DCB I2C table entry index", set the register to "data n" 1301 */ 1302 1303 uint8_t i2c_index = bios->data[offset + 1]; 1304 uint8_t i2c_address = bios->data[offset + 2]; 1305 uint8_t count = bios->data[offset + 3]; 1306 int len = 4 + count * 2; 1307 struct nouveau_i2c_chan *chan; 1308 struct i2c_msg msg; 1309 int i; 1310 1311 if (!iexec->execute) 1312 return len; 1313 1314 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1315 "Count: 0x%02X\n", 1316 offset, i2c_index, i2c_address, count); 1317 1318 chan = init_i2c_device_find(bios->dev, i2c_index); 1319 if (!chan) 1320 return 0; 1321 1322 for (i = 0; i < count; i++) { 1323 uint8_t i2c_reg = bios->data[offset + 4 + i * 2]; 1324 uint8_t data = bios->data[offset + 5 + i * 2]; 1325 1326 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n", 1327 offset, i2c_reg, data); 1328 1329 if (bios->execute) { 1330 msg.addr = i2c_address; 1331 msg.flags = 0; 1332 msg.len = 1; 1333 msg.buf = &data; 1334 if (i2c_transfer(&chan->adapter, &msg, 1) != 1) 1335 return 0; 1336 } 1337 } 1338 1339 return len; 1340} 1341 1342static int 1343init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1344{ 1345 /* 1346 * INIT_ZM_I2C opcode: 0x4E ('N') 1347 * 1348 * offset (8 bit): opcode 1349 * offset + 1 (8 bit): DCB I2C table entry index 1350 * offset + 2 (8 bit): I2C slave address 1351 * offset + 3 (8 bit): count 1352 * offset + 4 (8 bit): data 1 1353 * ... 1354 * 1355 * Send "count" bytes ("data n") to the device addressed by "I2C slave 1356 * address" on the I2C bus given by "DCB I2C table entry index" 1357 */ 1358 1359 uint8_t i2c_index = bios->data[offset + 1]; 1360 uint8_t i2c_address = bios->data[offset + 2]; 1361 uint8_t count = bios->data[offset + 3]; 1362 int len = 4 + count; 1363 struct nouveau_i2c_chan *chan; 1364 struct i2c_msg msg; 1365 uint8_t data[256]; 1366 int i; 1367 1368 if (!iexec->execute) 1369 return len; 1370 1371 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1372 "Count: 0x%02X\n", 1373 offset, i2c_index, i2c_address, count); 1374 1375 chan = init_i2c_device_find(bios->dev, i2c_index); 1376 if (!chan) 1377 return 0; 1378 1379 for (i = 0; i < count; i++) { 1380 data[i] = bios->data[offset + 4 + i]; 1381 1382 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]); 1383 } 1384 1385 if (bios->execute) { 1386 msg.addr = i2c_address; 1387 msg.flags = 0; 1388 msg.len = count; 1389 msg.buf = data; 1390 if (i2c_transfer(&chan->adapter, &msg, 1) != 1) 1391 return 0; 1392 } 1393 1394 return len; 1395} 1396 1397static int 1398init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1399{ 1400 /* 1401 * INIT_TMDS opcode: 0x4F ('O') (non-canon name) 1402 * 1403 * offset (8 bit): opcode 1404 * offset + 1 (8 bit): magic lookup value 1405 * offset + 2 (8 bit): TMDS address 1406 * offset + 3 (8 bit): mask 1407 * offset + 4 (8 bit): data 1408 * 1409 * Read the data reg for TMDS address "TMDS address", AND it with mask 1410 * and OR it with data, then write it back 1411 * "magic lookup value" determines which TMDS base address register is 1412 * used -- see get_tmds_index_reg() 1413 */ 1414 1415 uint8_t mlv = bios->data[offset + 1]; 1416 uint32_t tmdsaddr = bios->data[offset + 2]; 1417 uint8_t mask = bios->data[offset + 3]; 1418 uint8_t data = bios->data[offset + 4]; 1419 uint32_t reg, value; 1420 1421 if (!iexec->execute) 1422 return 5; 1423 1424 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, " 1425 "Mask: 0x%02X, Data: 0x%02X\n", 1426 offset, mlv, tmdsaddr, mask, data); 1427 1428 reg = get_tmds_index_reg(bios->dev, mlv); 1429 if (!reg) 1430 return 0; 1431 1432 bios_wr32(bios, reg, 1433 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE); 1434 value = (bios_rd32(bios, reg + 4) & mask) | data; 1435 bios_wr32(bios, reg + 4, value); 1436 bios_wr32(bios, reg, tmdsaddr); 1437 1438 return 5; 1439} 1440 1441static int 1442init_zm_tmds_group(struct nvbios *bios, uint16_t offset, 1443 struct init_exec *iexec) 1444{ 1445 /* 1446 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name) 1447 * 1448 * offset (8 bit): opcode 1449 * offset + 1 (8 bit): magic lookup value 1450 * offset + 2 (8 bit): count 1451 * offset + 3 (8 bit): addr 1 1452 * offset + 4 (8 bit): data 1 1453 * ... 1454 * 1455 * For each of "count" TMDS address and data pairs write "data n" to 1456 * "addr n". "magic lookup value" determines which TMDS base address 1457 * register is used -- see get_tmds_index_reg() 1458 */ 1459 1460 uint8_t mlv = bios->data[offset + 1]; 1461 uint8_t count = bios->data[offset + 2]; 1462 int len = 3 + count * 2; 1463 uint32_t reg; 1464 int i; 1465 1466 if (!iexec->execute) 1467 return len; 1468 1469 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n", 1470 offset, mlv, count); 1471 1472 reg = get_tmds_index_reg(bios->dev, mlv); 1473 if (!reg) 1474 return 0; 1475 1476 for (i = 0; i < count; i++) { 1477 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2]; 1478 uint8_t tmdsdata = bios->data[offset + 4 + i * 2]; 1479 1480 bios_wr32(bios, reg + 4, tmdsdata); 1481 bios_wr32(bios, reg, tmdsaddr); 1482 } 1483 1484 return len; 1485} 1486 1487static int 1488init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset, 1489 struct init_exec *iexec) 1490{ 1491 /* 1492 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q') 1493 * 1494 * offset (8 bit): opcode 1495 * offset + 1 (8 bit): CRTC index1 1496 * offset + 2 (8 bit): CRTC index2 1497 * offset + 3 (8 bit): baseaddr 1498 * offset + 4 (8 bit): count 1499 * offset + 5 (8 bit): data 1 1500 * ... 1501 * 1502 * For each of "count" address and data pairs, write "baseaddr + n" to 1503 * "CRTC index1" and "data n" to "CRTC index2" 1504 * Once complete, restore initial value read from "CRTC index1" 1505 */ 1506 uint8_t crtcindex1 = bios->data[offset + 1]; 1507 uint8_t crtcindex2 = bios->data[offset + 2]; 1508 uint8_t baseaddr = bios->data[offset + 3]; 1509 uint8_t count = bios->data[offset + 4]; 1510 int len = 5 + count; 1511 uint8_t oldaddr, data; 1512 int i; 1513 1514 if (!iexec->execute) 1515 return len; 1516 1517 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, " 1518 "BaseAddr: 0x%02X, Count: 0x%02X\n", 1519 offset, crtcindex1, crtcindex2, baseaddr, count); 1520 1521 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1); 1522 1523 for (i = 0; i < count; i++) { 1524 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, 1525 baseaddr + i); 1526 data = bios->data[offset + 5 + i]; 1527 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data); 1528 } 1529 1530 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr); 1531 1532 return len; 1533} 1534 1535static int 1536init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1537{ 1538 /* 1539 * INIT_CR opcode: 0x52 ('R') 1540 * 1541 * offset (8 bit): opcode 1542 * offset + 1 (8 bit): CRTC index 1543 * offset + 2 (8 bit): mask 1544 * offset + 3 (8 bit): data 1545 * 1546 * Assign the value of at "CRTC index" ANDed with mask and ORed with 1547 * data back to "CRTC index" 1548 */ 1549 1550 uint8_t crtcindex = bios->data[offset + 1]; 1551 uint8_t mask = bios->data[offset + 2]; 1552 uint8_t data = bios->data[offset + 3]; 1553 uint8_t value; 1554 1555 if (!iexec->execute) 1556 return 4; 1557 1558 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n", 1559 offset, crtcindex, mask, data); 1560 1561 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask; 1562 value |= data; 1563 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value); 1564 1565 return 4; 1566} 1567 1568static int 1569init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1570{ 1571 /* 1572 * INIT_ZM_CR opcode: 0x53 ('S') 1573 * 1574 * offset (8 bit): opcode 1575 * offset + 1 (8 bit): CRTC index 1576 * offset + 2 (8 bit): value 1577 * 1578 * Assign "value" to CRTC register with index "CRTC index". 1579 */ 1580 1581 uint8_t crtcindex = ROM32(bios->data[offset + 1]); 1582 uint8_t data = bios->data[offset + 2]; 1583 1584 if (!iexec->execute) 1585 return 3; 1586 1587 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data); 1588 1589 return 3; 1590} 1591 1592static int 1593init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1594{ 1595 /* 1596 * INIT_ZM_CR_GROUP opcode: 0x54 ('T') 1597 * 1598 * offset (8 bit): opcode 1599 * offset + 1 (8 bit): count 1600 * offset + 2 (8 bit): CRTC index 1 1601 * offset + 3 (8 bit): value 1 1602 * ... 1603 * 1604 * For "count", assign "value n" to CRTC register with index 1605 * "CRTC index n". 1606 */ 1607 1608 uint8_t count = bios->data[offset + 1]; 1609 int len = 2 + count * 2; 1610 int i; 1611 1612 if (!iexec->execute) 1613 return len; 1614 1615 for (i = 0; i < count; i++) 1616 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec); 1617 1618 return len; 1619} 1620 1621static int 1622init_condition_time(struct nvbios *bios, uint16_t offset, 1623 struct init_exec *iexec) 1624{ 1625 /* 1626 * INIT_CONDITION_TIME opcode: 0x56 ('V') 1627 * 1628 * offset (8 bit): opcode 1629 * offset + 1 (8 bit): condition number 1630 * offset + 2 (8 bit): retries / 50 1631 * 1632 * Check condition "condition number" in the condition table. 1633 * Bios code then sleeps for 2ms if the condition is not met, and 1634 * repeats up to "retries" times, but on one C51 this has proved 1635 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do 1636 * this, and bail after "retries" times, or 2s, whichever is less. 1637 * If still not met after retries, clear execution flag for this table. 1638 */ 1639 1640 uint8_t cond = bios->data[offset + 1]; 1641 uint16_t retries = bios->data[offset + 2] * 50; 1642 unsigned cnt; 1643 1644 if (!iexec->execute) 1645 return 3; 1646 1647 if (retries > 100) 1648 retries = 100; 1649 1650 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n", 1651 offset, cond, retries); 1652 1653 if (!bios->execute) /* avoid 2s delays when "faking" execution */ 1654 retries = 1; 1655 1656 for (cnt = 0; cnt < retries; cnt++) { 1657 if (bios_condition_met(bios, offset, cond)) { 1658 BIOSLOG(bios, "0x%04X: Condition met, continuing\n", 1659 offset); 1660 break; 1661 } else { 1662 BIOSLOG(bios, "0x%04X: " 1663 "Condition not met, sleeping for 20ms\n", 1664 offset); 1665 msleep(20); 1666 } 1667 } 1668 1669 if (!bios_condition_met(bios, offset, cond)) { 1670 NV_WARN(bios->dev, 1671 "0x%04X: Condition still not met after %dms, " 1672 "skipping following opcodes\n", offset, 20 * retries); 1673 iexec->execute = false; 1674 } 1675 1676 return 3; 1677} 1678 1679static int 1680init_zm_reg_sequence(struct nvbios *bios, uint16_t offset, 1681 struct init_exec *iexec) 1682{ 1683 /* 1684 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X') 1685 * 1686 * offset (8 bit): opcode 1687 * offset + 1 (32 bit): base register 1688 * offset + 5 (8 bit): count 1689 * offset + 6 (32 bit): value 1 1690 * ... 1691 * 1692 * Starting at offset + 6 there are "count" 32 bit values. 1693 * For "count" iterations set "base register" + 4 * current_iteration 1694 * to "value current_iteration" 1695 */ 1696 1697 uint32_t basereg = ROM32(bios->data[offset + 1]); 1698 uint32_t count = bios->data[offset + 5]; 1699 int len = 6 + count * 4; 1700 int i; 1701 1702 if (!iexec->execute) 1703 return len; 1704 1705 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n", 1706 offset, basereg, count); 1707 1708 for (i = 0; i < count; i++) { 1709 uint32_t reg = basereg + i * 4; 1710 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]); 1711 1712 bios_wr32(bios, reg, data); 1713 } 1714 1715 return len; 1716} 1717 1718static int 1719init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1720{ 1721 /* 1722 * INIT_SUB_DIRECT opcode: 0x5B ('[') 1723 * 1724 * offset (8 bit): opcode 1725 * offset + 1 (16 bit): subroutine offset (in bios) 1726 * 1727 * Calls a subroutine that will execute commands until INIT_DONE 1728 * is found. 1729 */ 1730 1731 uint16_t sub_offset = ROM16(bios->data[offset + 1]); 1732 1733 if (!iexec->execute) 1734 return 3; 1735 1736 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n", 1737 offset, sub_offset); 1738 1739 parse_init_table(bios, sub_offset, iexec); 1740 1741 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset); 1742 1743 return 3; 1744} 1745 1746static int 1747init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1748{ 1749 /* 1750 * INIT_COPY_NV_REG opcode: 0x5F ('_') 1751 * 1752 * offset (8 bit): opcode 1753 * offset + 1 (32 bit): src reg 1754 * offset + 5 (8 bit): shift 1755 * offset + 6 (32 bit): src mask 1756 * offset + 10 (32 bit): xor 1757 * offset + 14 (32 bit): dst reg 1758 * offset + 18 (32 bit): dst mask 1759 * 1760 * Shift REGVAL("src reg") right by (signed) "shift", AND result with 1761 * "src mask", then XOR with "xor". Write this OR'd with 1762 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg" 1763 */ 1764 1765 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1])); 1766 uint8_t shift = bios->data[offset + 5]; 1767 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6])); 1768 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10])); 1769 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14])); 1770 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18])); 1771 uint32_t srcvalue, dstvalue; 1772 1773 if (!iexec->execute) 1774 return 22; 1775 1776 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, " 1777 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n", 1778 offset, srcreg, shift, srcmask, xor, dstreg, dstmask); 1779 1780 srcvalue = bios_rd32(bios, srcreg); 1781 1782 if (shift < 0x80) 1783 srcvalue >>= shift; 1784 else 1785 srcvalue <<= (0x100 - shift); 1786 1787 srcvalue = (srcvalue & srcmask) ^ xor; 1788 1789 dstvalue = bios_rd32(bios, dstreg) & dstmask; 1790 1791 bios_wr32(bios, dstreg, dstvalue | srcvalue); 1792 1793 return 22; 1794} 1795 1796static int 1797init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1798{ 1799 /* 1800 * INIT_ZM_INDEX_IO opcode: 0x62 ('b') 1801 * 1802 * offset (8 bit): opcode 1803 * offset + 1 (16 bit): CRTC port 1804 * offset + 3 (8 bit): CRTC index 1805 * offset + 4 (8 bit): data 1806 * 1807 * Write "data" to index "CRTC index" of "CRTC port" 1808 */ 1809 uint16_t crtcport = ROM16(bios->data[offset + 1]); 1810 uint8_t crtcindex = bios->data[offset + 3]; 1811 uint8_t data = bios->data[offset + 4]; 1812 1813 if (!iexec->execute) 1814 return 5; 1815 1816 bios_idxprt_wr(bios, crtcport, crtcindex, data); 1817 1818 return 5; 1819} 1820 1821static int 1822init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1823{ 1824 /* 1825 * INIT_COMPUTE_MEM opcode: 0x63 ('c') 1826 * 1827 * offset (8 bit): opcode 1828 * 1829 * This opcode is meant to set NV_PFB_CFG0 (0x100200) appropriately so 1830 * that the hardware can correctly calculate how much VRAM it has 1831 * (and subsequently report that value in NV_PFB_CSTATUS (0x10020C)) 1832 * 1833 * The implementation of this opcode in general consists of two parts: 1834 * 1) determination of the memory bus width 1835 * 2) determination of how many of the card's RAM pads have ICs attached 1836 * 1837 * 1) is done by a cunning combination of writes to offsets 0x1c and 1838 * 0x3c in the framebuffer, and seeing whether the written values are 1839 * read back correctly. This then affects bits 4-7 of NV_PFB_CFG0 1840 * 1841 * 2) is done by a cunning combination of writes to an offset slightly 1842 * less than the maximum memory reported by NV_PFB_CSTATUS, then seeing 1843 * if the test pattern can be read back. This then affects bits 12-15 of 1844 * NV_PFB_CFG0 1845 * 1846 * In this context a "cunning combination" may include multiple reads 1847 * and writes to varying locations, often alternating the test pattern 1848 * and 0, doubtless to make sure buffers are filled, residual charges 1849 * on tracks are removed etc. 1850 * 1851 * Unfortunately, the "cunning combination"s mentioned above, and the 1852 * changes to the bits in NV_PFB_CFG0 differ with nearly every bios 1853 * trace I have. 1854 * 1855 * Therefore, we cheat and assume the value of NV_PFB_CFG0 with which 1856 * we started was correct, and use that instead 1857 */ 1858 1859 /* no iexec->execute check by design */ 1860 1861 /* 1862 * This appears to be a NOP on G8x chipsets, both io logs of the VBIOS 1863 * and kmmio traces of the binary driver POSTing the card show nothing 1864 * being done for this opcode. why is it still listed in the table?! 1865 */ 1866 1867 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 1868 1869 if (dev_priv->card_type >= NV_40) 1870 return 1; 1871 1872 /* 1873 * On every card I've seen, this step gets done for us earlier in 1874 * the init scripts 1875 uint8_t crdata = bios_idxprt_rd(dev, NV_VIO_SRX, 0x01); 1876 bios_idxprt_wr(dev, NV_VIO_SRX, 0x01, crdata | 0x20); 1877 */ 1878 1879 /* 1880 * This also has probably been done in the scripts, but an mmio trace of 1881 * s3 resume shows nvidia doing it anyway (unlike the NV_VIO_SRX write) 1882 */ 1883 bios_wr32(bios, NV_PFB_REFCTRL, NV_PFB_REFCTRL_VALID_1); 1884 1885 /* write back the saved configuration value */ 1886 bios_wr32(bios, NV_PFB_CFG0, bios->state.saved_nv_pfb_cfg0); 1887 1888 return 1; 1889} 1890 1891static int 1892init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1893{ 1894 /* 1895 * INIT_RESET opcode: 0x65 ('e') 1896 * 1897 * offset (8 bit): opcode 1898 * offset + 1 (32 bit): register 1899 * offset + 5 (32 bit): value1 1900 * offset + 9 (32 bit): value2 1901 * 1902 * Assign "value1" to "register", then assign "value2" to "register" 1903 */ 1904 1905 uint32_t reg = ROM32(bios->data[offset + 1]); 1906 uint32_t value1 = ROM32(bios->data[offset + 5]); 1907 uint32_t value2 = ROM32(bios->data[offset + 9]); 1908 uint32_t pci_nv_19, pci_nv_20; 1909 1910 /* no iexec->execute check by design */ 1911 1912 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19); 1913 bios_wr32(bios, NV_PBUS_PCI_NV_19, 0); 1914 bios_wr32(bios, reg, value1); 1915 1916 udelay(10); 1917 1918 bios_wr32(bios, reg, value2); 1919 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19); 1920 1921 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20); 1922 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */ 1923 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20); 1924 1925 return 13; 1926} 1927 1928static int 1929init_configure_mem(struct nvbios *bios, uint16_t offset, 1930 struct init_exec *iexec) 1931{ 1932 /* 1933 * INIT_CONFIGURE_MEM opcode: 0x66 ('f') 1934 * 1935 * offset (8 bit): opcode 1936 * 1937 * Equivalent to INIT_DONE on bios version 3 or greater. 1938 * For early bios versions, sets up the memory registers, using values 1939 * taken from the memory init table 1940 */ 1941 1942 /* no iexec->execute check by design */ 1943 1944 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4); 1945 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6; 1946 uint32_t reg, data; 1947 1948 if (bios->major_version > 2) 1949 return 0; 1950 1951 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd( 1952 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20); 1953 1954 if (bios->data[meminitoffs] & 1) 1955 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr; 1956 1957 for (reg = ROM32(bios->data[seqtbloffs]); 1958 reg != 0xffffffff; 1959 reg = ROM32(bios->data[seqtbloffs += 4])) { 1960 1961 switch (reg) { 1962 case NV_PFB_PRE: 1963 data = NV_PFB_PRE_CMD_PRECHARGE; 1964 break; 1965 case NV_PFB_PAD: 1966 data = NV_PFB_PAD_CKE_NORMAL; 1967 break; 1968 case NV_PFB_REF: 1969 data = NV_PFB_REF_CMD_REFRESH; 1970 break; 1971 default: 1972 data = ROM32(bios->data[meminitdata]); 1973 meminitdata += 4; 1974 if (data == 0xffffffff) 1975 continue; 1976 } 1977 1978 bios_wr32(bios, reg, data); 1979 } 1980 1981 return 1; 1982} 1983 1984static int 1985init_configure_clk(struct nvbios *bios, uint16_t offset, 1986 struct init_exec *iexec) 1987{ 1988 /* 1989 * INIT_CONFIGURE_CLK opcode: 0x67 ('g') 1990 * 1991 * offset (8 bit): opcode 1992 * 1993 * Equivalent to INIT_DONE on bios version 3 or greater. 1994 * For early bios versions, sets up the NVClk and MClk PLLs, using 1995 * values taken from the memory init table 1996 */ 1997 1998 /* no iexec->execute check by design */ 1999 2000 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4); 2001 int clock; 2002 2003 if (bios->major_version > 2) 2004 return 0; 2005 2006 clock = ROM16(bios->data[meminitoffs + 4]) * 10; 2007 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock); 2008 2009 clock = ROM16(bios->data[meminitoffs + 2]) * 10; 2010 if (bios->data[meminitoffs] & 1) /* DDR */ 2011 clock *= 2; 2012 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock); 2013 2014 return 1; 2015} 2016 2017static int 2018init_configure_preinit(struct nvbios *bios, uint16_t offset, 2019 struct init_exec *iexec) 2020{ 2021 /* 2022 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h') 2023 * 2024 * offset (8 bit): opcode 2025 * 2026 * Equivalent to INIT_DONE on bios version 3 or greater. 2027 * For early bios versions, does early init, loading ram and crystal 2028 * configuration from straps into CR3C 2029 */ 2030 2031 /* no iexec->execute check by design */ 2032 2033 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0); 2034 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & (1 << 6)); 2035 2036 if (bios->major_version > 2) 2037 return 0; 2038 2039 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, 2040 NV_CIO_CRE_SCRATCH4__INDEX, cr3c); 2041 2042 return 1; 2043} 2044 2045static int 2046init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2047{ 2048 /* 2049 * INIT_IO opcode: 0x69 ('i') 2050 * 2051 * offset (8 bit): opcode 2052 * offset + 1 (16 bit): CRTC port 2053 * offset + 3 (8 bit): mask 2054 * offset + 4 (8 bit): data 2055 * 2056 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port" 2057 */ 2058 2059 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2060 uint16_t crtcport = ROM16(bios->data[offset + 1]); 2061 uint8_t mask = bios->data[offset + 3]; 2062 uint8_t data = bios->data[offset + 4]; 2063 2064 if (!iexec->execute) 2065 return 5; 2066 2067 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n", 2068 offset, crtcport, mask, data); 2069 2070 /* 2071 * I have no idea what this does, but NVIDIA do this magic sequence 2072 * in the places where this INIT_IO happens.. 2073 */ 2074 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) { 2075 int i; 2076 2077 bios_wr32(bios, 0x614100, (bios_rd32( 2078 bios, 0x614100) & 0x0fffffff) | 0x00800000); 2079 2080 bios_wr32(bios, 0x00e18c, bios_rd32( 2081 bios, 0x00e18c) | 0x00020000); 2082 2083 bios_wr32(bios, 0x614900, (bios_rd32( 2084 bios, 0x614900) & 0x0fffffff) | 0x00800000); 2085 2086 bios_wr32(bios, 0x000200, bios_rd32( 2087 bios, 0x000200) & ~0x40000000); 2088 2089 mdelay(10); 2090 2091 bios_wr32(bios, 0x00e18c, bios_rd32( 2092 bios, 0x00e18c) & ~0x00020000); 2093 2094 bios_wr32(bios, 0x000200, bios_rd32( 2095 bios, 0x000200) | 0x40000000); 2096 2097 bios_wr32(bios, 0x614100, 0x00800018); 2098 bios_wr32(bios, 0x614900, 0x00800018); 2099 2100 mdelay(10); 2101 2102 bios_wr32(bios, 0x614100, 0x10000018); 2103 bios_wr32(bios, 0x614900, 0x10000018); 2104 2105 for (i = 0; i < 3; i++) 2106 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32( 2107 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0); 2108 2109 for (i = 0; i < 2; i++) 2110 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32( 2111 bios, 0x614300 + (i*0x800)) & 0xfffff0f0); 2112 2113 for (i = 0; i < 3; i++) 2114 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32( 2115 bios, 0x614380 + (i*0x800)) & 0xfffff0f0); 2116 2117 for (i = 0; i < 2; i++) 2118 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32( 2119 bios, 0x614200 + (i*0x800)) & 0xfffffff0); 2120 2121 for (i = 0; i < 2; i++) 2122 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32( 2123 bios, 0x614108 + (i*0x800)) & 0x0fffffff); 2124 return 5; 2125 } 2126 2127 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) | 2128 data); 2129 return 5; 2130} 2131 2132static int 2133init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2134{ 2135 /* 2136 * INIT_SUB opcode: 0x6B ('k') 2137 * 2138 * offset (8 bit): opcode 2139 * offset + 1 (8 bit): script number 2140 * 2141 * Execute script number "script number", as a subroutine 2142 */ 2143 2144 uint8_t sub = bios->data[offset + 1]; 2145 2146 if (!iexec->execute) 2147 return 2; 2148 2149 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub); 2150 2151 parse_init_table(bios, 2152 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]), 2153 iexec); 2154 2155 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub); 2156 2157 return 2; 2158} 2159 2160static int 2161init_ram_condition(struct nvbios *bios, uint16_t offset, 2162 struct init_exec *iexec) 2163{ 2164 /* 2165 * INIT_RAM_CONDITION opcode: 0x6D ('m') 2166 * 2167 * offset (8 bit): opcode 2168 * offset + 1 (8 bit): mask 2169 * offset + 2 (8 bit): cmpval 2170 * 2171 * Test if (NV_PFB_BOOT_0 & "mask") equals "cmpval". 2172 * If condition not met skip subsequent opcodes until condition is 2173 * inverted (INIT_NOT), or we hit INIT_RESUME 2174 */ 2175 2176 uint8_t mask = bios->data[offset + 1]; 2177 uint8_t cmpval = bios->data[offset + 2]; 2178 uint8_t data; 2179 2180 if (!iexec->execute) 2181 return 3; 2182 2183 data = bios_rd32(bios, NV_PFB_BOOT_0) & mask; 2184 2185 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n", 2186 offset, data, cmpval); 2187 2188 if (data == cmpval) 2189 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 2190 else { 2191 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 2192 iexec->execute = false; 2193 } 2194 2195 return 3; 2196} 2197 2198static int 2199init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2200{ 2201 /* 2202 * INIT_NV_REG opcode: 0x6E ('n') 2203 * 2204 * offset (8 bit): opcode 2205 * offset + 1 (32 bit): register 2206 * offset + 5 (32 bit): mask 2207 * offset + 9 (32 bit): data 2208 * 2209 * Assign ((REGVAL("register") & "mask") | "data") to "register" 2210 */ 2211 2212 uint32_t reg = ROM32(bios->data[offset + 1]); 2213 uint32_t mask = ROM32(bios->data[offset + 5]); 2214 uint32_t data = ROM32(bios->data[offset + 9]); 2215 2216 if (!iexec->execute) 2217 return 13; 2218 2219 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n", 2220 offset, reg, mask, data); 2221 2222 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data); 2223 2224 return 13; 2225} 2226 2227static int 2228init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2229{ 2230 /* 2231 * INIT_MACRO opcode: 0x6F ('o') 2232 * 2233 * offset (8 bit): opcode 2234 * offset + 1 (8 bit): macro number 2235 * 2236 * Look up macro index "macro number" in the macro index table. 2237 * The macro index table entry has 1 byte for the index in the macro 2238 * table, and 1 byte for the number of times to repeat the macro. 2239 * The macro table entry has 4 bytes for the register address and 2240 * 4 bytes for the value to write to that register 2241 */ 2242 2243 uint8_t macro_index_tbl_idx = bios->data[offset + 1]; 2244 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE); 2245 uint8_t macro_tbl_idx = bios->data[tmp]; 2246 uint8_t count = bios->data[tmp + 1]; 2247 uint32_t reg, data; 2248 int i; 2249 2250 if (!iexec->execute) 2251 return 2; 2252 2253 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, " 2254 "Count: 0x%02X\n", 2255 offset, macro_index_tbl_idx, macro_tbl_idx, count); 2256 2257 for (i = 0; i < count; i++) { 2258 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE; 2259 2260 reg = ROM32(bios->data[macroentryptr]); 2261 data = ROM32(bios->data[macroentryptr + 4]); 2262 2263 bios_wr32(bios, reg, data); 2264 } 2265 2266 return 2; 2267} 2268 2269static int 2270init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2271{ 2272 /* 2273 * INIT_DONE opcode: 0x71 ('q') 2274 * 2275 * offset (8 bit): opcode 2276 * 2277 * End the current script 2278 */ 2279 2280 /* mild retval abuse to stop parsing this table */ 2281 return 0; 2282} 2283 2284static int 2285init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2286{ 2287 /* 2288 * INIT_RESUME opcode: 0x72 ('r') 2289 * 2290 * offset (8 bit): opcode 2291 * 2292 * End the current execute / no-execute condition 2293 */ 2294 2295 if (iexec->execute) 2296 return 1; 2297 2298 iexec->execute = true; 2299 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset); 2300 2301 return 1; 2302} 2303 2304static int 2305init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2306{ 2307 /* 2308 * INIT_TIME opcode: 0x74 ('t') 2309 * 2310 * offset (8 bit): opcode 2311 * offset + 1 (16 bit): time 2312 * 2313 * Sleep for "time" microseconds. 2314 */ 2315 2316 unsigned time = ROM16(bios->data[offset + 1]); 2317 2318 if (!iexec->execute) 2319 return 3; 2320 2321 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n", 2322 offset, time); 2323 2324 if (time < 1000) 2325 udelay(time); 2326 else 2327 msleep((time + 900) / 1000); 2328 2329 return 3; 2330} 2331 2332static int 2333init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2334{ 2335 /* 2336 * INIT_CONDITION opcode: 0x75 ('u') 2337 * 2338 * offset (8 bit): opcode 2339 * offset + 1 (8 bit): condition number 2340 * 2341 * Check condition "condition number" in the condition table. 2342 * If condition not met skip subsequent opcodes until condition is 2343 * inverted (INIT_NOT), or we hit INIT_RESUME 2344 */ 2345 2346 uint8_t cond = bios->data[offset + 1]; 2347 2348 if (!iexec->execute) 2349 return 2; 2350 2351 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond); 2352 2353 if (bios_condition_met(bios, offset, cond)) 2354 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 2355 else { 2356 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 2357 iexec->execute = false; 2358 } 2359 2360 return 2; 2361} 2362 2363static int 2364init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2365{ 2366 /* 2367 * INIT_IO_CONDITION opcode: 0x76 2368 * 2369 * offset (8 bit): opcode 2370 * offset + 1 (8 bit): condition number 2371 * 2372 * Check condition "condition number" in the io condition table. 2373 * If condition not met skip subsequent opcodes until condition is 2374 * inverted (INIT_NOT), or we hit INIT_RESUME 2375 */ 2376 2377 uint8_t cond = bios->data[offset + 1]; 2378 2379 if (!iexec->execute) 2380 return 2; 2381 2382 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond); 2383 2384 if (io_condition_met(bios, offset, cond)) 2385 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 2386 else { 2387 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 2388 iexec->execute = false; 2389 } 2390 2391 return 2; 2392} 2393 2394static int 2395init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2396{ 2397 /* 2398 * INIT_INDEX_IO opcode: 0x78 ('x') 2399 * 2400 * offset (8 bit): opcode 2401 * offset + 1 (16 bit): CRTC port 2402 * offset + 3 (8 bit): CRTC index 2403 * offset + 4 (8 bit): mask 2404 * offset + 5 (8 bit): data 2405 * 2406 * Read value at index "CRTC index" on "CRTC port", AND with "mask", 2407 * OR with "data", write-back 2408 */ 2409 2410 uint16_t crtcport = ROM16(bios->data[offset + 1]); 2411 uint8_t crtcindex = bios->data[offset + 3]; 2412 uint8_t mask = bios->data[offset + 4]; 2413 uint8_t data = bios->data[offset + 5]; 2414 uint8_t value; 2415 2416 if (!iexec->execute) 2417 return 6; 2418 2419 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 2420 "Data: 0x%02X\n", 2421 offset, crtcport, crtcindex, mask, data); 2422 2423 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data; 2424 bios_idxprt_wr(bios, crtcport, crtcindex, value); 2425 2426 return 6; 2427} 2428 2429static int 2430init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2431{ 2432 /* 2433 * INIT_PLL opcode: 0x79 ('y') 2434 * 2435 * offset (8 bit): opcode 2436 * offset + 1 (32 bit): register 2437 * offset + 5 (16 bit): freq 2438 * 2439 * Set PLL register "register" to coefficients for frequency (10kHz) 2440 * "freq" 2441 */ 2442 2443 uint32_t reg = ROM32(bios->data[offset + 1]); 2444 uint16_t freq = ROM16(bios->data[offset + 5]); 2445 2446 if (!iexec->execute) 2447 return 7; 2448 2449 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq); 2450 2451 setPLL(bios, reg, freq * 10); 2452 2453 return 7; 2454} 2455 2456static int 2457init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2458{ 2459 /* 2460 * INIT_ZM_REG opcode: 0x7A ('z') 2461 * 2462 * offset (8 bit): opcode 2463 * offset + 1 (32 bit): register 2464 * offset + 5 (32 bit): value 2465 * 2466 * Assign "value" to "register" 2467 */ 2468 2469 uint32_t reg = ROM32(bios->data[offset + 1]); 2470 uint32_t value = ROM32(bios->data[offset + 5]); 2471 2472 if (!iexec->execute) 2473 return 9; 2474 2475 if (reg == 0x000200) 2476 value |= 1; 2477 2478 bios_wr32(bios, reg, value); 2479 2480 return 9; 2481} 2482 2483static int 2484init_ram_restrict_pll(struct nvbios *bios, uint16_t offset, 2485 struct init_exec *iexec) 2486{ 2487 /* 2488 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('') 2489 * 2490 * offset (8 bit): opcode 2491 * offset + 1 (8 bit): PLL type 2492 * offset + 2 (32 bit): frequency 0 2493 * 2494 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at 2495 * ram_restrict_table_ptr. The value read from there is used to select 2496 * a frequency from the table starting at 'frequency 0' to be 2497 * programmed into the PLL corresponding to 'type'. 2498 * 2499 * The PLL limits table on cards using this opcode has a mapping of 2500 * 'type' to the relevant registers. 2501 */ 2502 2503 struct drm_device *dev = bios->dev; 2504 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2; 2505 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap]; 2506 uint8_t type = bios->data[offset + 1]; 2507 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]); 2508 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry; 2509 int len = 2 + bios->ram_restrict_group_count * 4; 2510 int i; 2511 2512 if (!iexec->execute) 2513 return len; 2514 2515 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) { 2516 NV_ERROR(dev, "PLL limits table not version 3.x\n"); 2517 return len; /* deliberate, allow default clocks to remain */ 2518 } 2519 2520 entry = pll_limits + pll_limits[1]; 2521 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) { 2522 if (entry[0] == type) { 2523 uint32_t reg = ROM32(entry[3]); 2524 2525 BIOSLOG(bios, "0x%04X: " 2526 "Type %02x Reg 0x%08x Freq %dKHz\n", 2527 offset, type, reg, freq); 2528 2529 setPLL(bios, reg, freq); 2530 return len; 2531 } 2532 } 2533 2534 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type); 2535 return len; 2536} 2537 2538static int 2539init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2540{ 2541 /* 2542 * INIT_8C opcode: 0x8C ('') 2543 * 2544 * NOP so far.... 2545 * 2546 */ 2547 2548 return 1; 2549} 2550 2551static int 2552init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2553{ 2554 /* 2555 * INIT_8D opcode: 0x8D ('') 2556 * 2557 * NOP so far.... 2558 * 2559 */ 2560 2561 return 1; 2562} 2563 2564static int 2565init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2566{ 2567 /* 2568 * INIT_GPIO opcode: 0x8E ('') 2569 * 2570 * offset (8 bit): opcode 2571 * 2572 * Loop over all entries in the DCB GPIO table, and initialise 2573 * each GPIO according to various values listed in each entry 2574 */ 2575 2576 const uint32_t nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 }; 2577 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c }; 2578 const uint8_t *gpio_table = &bios->data[bios->dcb.gpio_table_ptr]; 2579 const uint8_t *gpio_entry; 2580 int i; 2581 2582 if (!iexec->execute) 2583 return 1; 2584 2585 if (bios->dcb.version != 0x40) { 2586 NV_ERROR(bios->dev, "DCB table not version 4.0\n"); 2587 return 0; 2588 } 2589 2590 if (!bios->dcb.gpio_table_ptr) { 2591 NV_WARN(bios->dev, "Invalid pointer to INIT_8E table\n"); 2592 return 0; 2593 } 2594 2595 gpio_entry = gpio_table + gpio_table[1]; 2596 for (i = 0; i < gpio_table[2]; i++, gpio_entry += gpio_table[3]) { 2597 uint32_t entry = ROM32(gpio_entry[0]), r, s, v; 2598 int line = (entry & 0x0000001f); 2599 2600 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, entry); 2601 2602 if ((entry & 0x0000ff00) == 0x0000ff00) 2603 continue; 2604 2605 r = nv50_gpio_reg[line >> 3]; 2606 s = (line & 0x07) << 2; 2607 v = bios_rd32(bios, r) & ~(0x00000003 << s); 2608 if (entry & 0x01000000) 2609 v |= (((entry & 0x60000000) >> 29) ^ 2) << s; 2610 else 2611 v |= (((entry & 0x18000000) >> 27) ^ 2) << s; 2612 bios_wr32(bios, r, v); 2613 2614 r = nv50_gpio_ctl[line >> 4]; 2615 s = (line & 0x0f); 2616 v = bios_rd32(bios, r) & ~(0x00010001 << s); 2617 switch ((entry & 0x06000000) >> 25) { 2618 case 1: 2619 v |= (0x00000001 << s); 2620 break; 2621 case 2: 2622 v |= (0x00010000 << s); 2623 break; 2624 default: 2625 break; 2626 } 2627 bios_wr32(bios, r, v); 2628 } 2629 2630 return 1; 2631} 2632 2633static int 2634init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset, 2635 struct init_exec *iexec) 2636{ 2637 /* 2638 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('') 2639 * 2640 * offset (8 bit): opcode 2641 * offset + 1 (32 bit): reg 2642 * offset + 5 (8 bit): regincrement 2643 * offset + 6 (8 bit): count 2644 * offset + 7 (32 bit): value 1,1 2645 * ... 2646 * 2647 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at 2648 * ram_restrict_table_ptr. The value read from here is 'n', and 2649 * "value 1,n" gets written to "reg". This repeats "count" times and on 2650 * each iteration 'm', "reg" increases by "regincrement" and 2651 * "value m,n" is used. The extent of n is limited by a number read 2652 * from the 'M' BIT table, herein called "blocklen" 2653 */ 2654 2655 uint32_t reg = ROM32(bios->data[offset + 1]); 2656 uint8_t regincrement = bios->data[offset + 5]; 2657 uint8_t count = bios->data[offset + 6]; 2658 uint32_t strap_ramcfg, data; 2659 /* previously set by 'M' BIT table */ 2660 uint16_t blocklen = bios->ram_restrict_group_count * 4; 2661 int len = 7 + count * blocklen; 2662 uint8_t index; 2663 int i; 2664 2665 2666 if (!iexec->execute) 2667 return len; 2668 2669 if (!blocklen) { 2670 NV_ERROR(bios->dev, 2671 "0x%04X: Zero block length - has the M table " 2672 "been parsed?\n", offset); 2673 return 0; 2674 } 2675 2676 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf; 2677 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg]; 2678 2679 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, " 2680 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n", 2681 offset, reg, regincrement, count, strap_ramcfg, index); 2682 2683 for (i = 0; i < count; i++) { 2684 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]); 2685 2686 bios_wr32(bios, reg, data); 2687 2688 reg += regincrement; 2689 } 2690 2691 return len; 2692} 2693 2694static int 2695init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2696{ 2697 /* 2698 * INIT_COPY_ZM_REG opcode: 0x90 ('') 2699 * 2700 * offset (8 bit): opcode 2701 * offset + 1 (32 bit): src reg 2702 * offset + 5 (32 bit): dst reg 2703 * 2704 * Put contents of "src reg" into "dst reg" 2705 */ 2706 2707 uint32_t srcreg = ROM32(bios->data[offset + 1]); 2708 uint32_t dstreg = ROM32(bios->data[offset + 5]); 2709 2710 if (!iexec->execute) 2711 return 9; 2712 2713 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg)); 2714 2715 return 9; 2716} 2717 2718static int 2719init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset, 2720 struct init_exec *iexec) 2721{ 2722 /* 2723 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('') 2724 * 2725 * offset (8 bit): opcode 2726 * offset + 1 (32 bit): dst reg 2727 * offset + 5 (8 bit): count 2728 * offset + 6 (32 bit): data 1 2729 * ... 2730 * 2731 * For each of "count" values write "data n" to "dst reg" 2732 */ 2733 2734 uint32_t reg = ROM32(bios->data[offset + 1]); 2735 uint8_t count = bios->data[offset + 5]; 2736 int len = 6 + count * 4; 2737 int i; 2738 2739 if (!iexec->execute) 2740 return len; 2741 2742 for (i = 0; i < count; i++) { 2743 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]); 2744 bios_wr32(bios, reg, data); 2745 } 2746 2747 return len; 2748} 2749 2750static int 2751init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2752{ 2753 /* 2754 * INIT_RESERVED opcode: 0x92 ('') 2755 * 2756 * offset (8 bit): opcode 2757 * 2758 * Seemingly does nothing 2759 */ 2760 2761 return 1; 2762} 2763 2764static int 2765init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2766{ 2767 /* 2768 * INIT_96 opcode: 0x96 ('') 2769 * 2770 * offset (8 bit): opcode 2771 * offset + 1 (32 bit): sreg 2772 * offset + 5 (8 bit): sshift 2773 * offset + 6 (8 bit): smask 2774 * offset + 7 (8 bit): index 2775 * offset + 8 (32 bit): reg 2776 * offset + 12 (32 bit): mask 2777 * offset + 16 (8 bit): shift 2778 * 2779 */ 2780 2781 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2); 2782 uint32_t reg = ROM32(bios->data[offset + 8]); 2783 uint32_t mask = ROM32(bios->data[offset + 12]); 2784 uint32_t val; 2785 2786 val = bios_rd32(bios, ROM32(bios->data[offset + 1])); 2787 if (bios->data[offset + 5] < 0x80) 2788 val >>= bios->data[offset + 5]; 2789 else 2790 val <<= (0x100 - bios->data[offset + 5]); 2791 val &= bios->data[offset + 6]; 2792 2793 val = bios->data[ROM16(bios->data[xlatptr]) + val]; 2794 val <<= bios->data[offset + 16]; 2795 2796 if (!iexec->execute) 2797 return 17; 2798 2799 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val); 2800 return 17; 2801} 2802 2803static int 2804init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2805{ 2806 /* 2807 * INIT_97 opcode: 0x97 ('') 2808 * 2809 * offset (8 bit): opcode 2810 * offset + 1 (32 bit): register 2811 * offset + 5 (32 bit): mask 2812 * offset + 9 (32 bit): value 2813 * 2814 * Adds "value" to "register" preserving the fields specified 2815 * by "mask" 2816 */ 2817 2818 uint32_t reg = ROM32(bios->data[offset + 1]); 2819 uint32_t mask = ROM32(bios->data[offset + 5]); 2820 uint32_t add = ROM32(bios->data[offset + 9]); 2821 uint32_t val; 2822 2823 val = bios_rd32(bios, reg); 2824 val = (val & mask) | ((val + add) & ~mask); 2825 2826 if (!iexec->execute) 2827 return 13; 2828 2829 bios_wr32(bios, reg, val); 2830 return 13; 2831} 2832 2833static int 2834init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2835{ 2836 /* 2837 * INIT_AUXCH opcode: 0x98 ('') 2838 * 2839 * offset (8 bit): opcode 2840 * offset + 1 (32 bit): address 2841 * offset + 5 (8 bit): count 2842 * offset + 6 (8 bit): mask 0 2843 * offset + 7 (8 bit): data 0 2844 * ... 2845 * 2846 */ 2847 2848 struct drm_device *dev = bios->dev; 2849 struct nouveau_i2c_chan *auxch; 2850 uint32_t addr = ROM32(bios->data[offset + 1]); 2851 uint8_t count = bios->data[offset + 5]; 2852 int len = 6 + count * 2; 2853 int ret, i; 2854 2855 if (!bios->display.output) { 2856 NV_ERROR(dev, "INIT_AUXCH: no active output\n"); 2857 return 0; 2858 } 2859 2860 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index); 2861 if (!auxch) { 2862 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n", 2863 bios->display.output->i2c_index); 2864 return 0; 2865 } 2866 2867 if (!iexec->execute) 2868 return len; 2869 2870 offset += 6; 2871 for (i = 0; i < count; i++, offset += 2) { 2872 uint8_t data; 2873 2874 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1); 2875 if (ret) { 2876 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret); 2877 return 0; 2878 } 2879 2880 data &= bios->data[offset + 0]; 2881 data |= bios->data[offset + 1]; 2882 2883 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1); 2884 if (ret) { 2885 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret); 2886 return 0; 2887 } 2888 } 2889 2890 return len; 2891} 2892 2893static int 2894init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2895{ 2896 /* 2897 * INIT_ZM_AUXCH opcode: 0x99 ('') 2898 * 2899 * offset (8 bit): opcode 2900 * offset + 1 (32 bit): address 2901 * offset + 5 (8 bit): count 2902 * offset + 6 (8 bit): data 0 2903 * ... 2904 * 2905 */ 2906 2907 struct drm_device *dev = bios->dev; 2908 struct nouveau_i2c_chan *auxch; 2909 uint32_t addr = ROM32(bios->data[offset + 1]); 2910 uint8_t count = bios->data[offset + 5]; 2911 int len = 6 + count; 2912 int ret, i; 2913 2914 if (!bios->display.output) { 2915 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n"); 2916 return 0; 2917 } 2918 2919 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index); 2920 if (!auxch) { 2921 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n", 2922 bios->display.output->i2c_index); 2923 return 0; 2924 } 2925 2926 if (!iexec->execute) 2927 return len; 2928 2929 offset += 6; 2930 for (i = 0; i < count; i++, offset++) { 2931 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1); 2932 if (ret) { 2933 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret); 2934 return 0; 2935 } 2936 } 2937 2938 return len; 2939} 2940 2941static struct init_tbl_entry itbl_entry[] = { 2942 /* command name , id , length , offset , mult , command handler */ 2943 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */ 2944 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog }, 2945 { "INIT_REPEAT" , 0x33, init_repeat }, 2946 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll }, 2947 { "INIT_END_REPEAT" , 0x36, init_end_repeat }, 2948 { "INIT_COPY" , 0x37, init_copy }, 2949 { "INIT_NOT" , 0x38, init_not }, 2950 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition }, 2951 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched }, 2952 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 }, 2953 { "INIT_PLL2" , 0x4B, init_pll2 }, 2954 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte }, 2955 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte }, 2956 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c }, 2957 { "INIT_TMDS" , 0x4F, init_tmds }, 2958 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group }, 2959 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch }, 2960 { "INIT_CR" , 0x52, init_cr }, 2961 { "INIT_ZM_CR" , 0x53, init_zm_cr }, 2962 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group }, 2963 { "INIT_CONDITION_TIME" , 0x56, init_condition_time }, 2964 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence }, 2965 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */ 2966 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct }, 2967 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg }, 2968 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io }, 2969 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem }, 2970 { "INIT_RESET" , 0x65, init_reset }, 2971 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem }, 2972 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk }, 2973 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit }, 2974 { "INIT_IO" , 0x69, init_io }, 2975 { "INIT_SUB" , 0x6B, init_sub }, 2976 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition }, 2977 { "INIT_NV_REG" , 0x6E, init_nv_reg }, 2978 { "INIT_MACRO" , 0x6F, init_macro }, 2979 { "INIT_DONE" , 0x71, init_done }, 2980 { "INIT_RESUME" , 0x72, init_resume }, 2981 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */ 2982 { "INIT_TIME" , 0x74, init_time }, 2983 { "INIT_CONDITION" , 0x75, init_condition }, 2984 { "INIT_IO_CONDITION" , 0x76, init_io_condition }, 2985 { "INIT_INDEX_IO" , 0x78, init_index_io }, 2986 { "INIT_PLL" , 0x79, init_pll }, 2987 { "INIT_ZM_REG" , 0x7A, init_zm_reg }, 2988 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll }, 2989 { "INIT_8C" , 0x8C, init_8c }, 2990 { "INIT_8D" , 0x8D, init_8d }, 2991 { "INIT_GPIO" , 0x8E, init_gpio }, 2992 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group }, 2993 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg }, 2994 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched }, 2995 { "INIT_RESERVED" , 0x92, init_reserved }, 2996 { "INIT_96" , 0x96, init_96 }, 2997 { "INIT_97" , 0x97, init_97 }, 2998 { "INIT_AUXCH" , 0x98, init_auxch }, 2999 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch }, 3000 { NULL , 0 , NULL } 3001}; 3002 3003#define MAX_TABLE_OPS 1000 3004 3005static int 3006parse_init_table(struct nvbios *bios, unsigned int offset, 3007 struct init_exec *iexec) 3008{ 3009 /* 3010 * Parses all commands in an init table. 3011 * 3012 * We start out executing all commands found in the init table. Some 3013 * opcodes may change the status of iexec->execute to SKIP, which will 3014 * cause the following opcodes to perform no operation until the value 3015 * is changed back to EXECUTE. 3016 */ 3017 3018 int count = 0, i, res; 3019 uint8_t id; 3020 3021 /* 3022 * Loop until INIT_DONE causes us to break out of the loop 3023 * (or until offset > bios length just in case... ) 3024 * (and no more than MAX_TABLE_OPS iterations, just in case... ) 3025 */ 3026 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) { 3027 id = bios->data[offset]; 3028 3029 /* Find matching id in itbl_entry */ 3030 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++) 3031 ; 3032 3033 if (itbl_entry[i].name) { 3034 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", 3035 offset, itbl_entry[i].id, itbl_entry[i].name); 3036 3037 /* execute eventual command handler */ 3038 res = (*itbl_entry[i].handler)(bios, offset, iexec); 3039 if (!res) 3040 break; 3041 /* 3042 * Add the offset of the current command including all data 3043 * of that command. The offset will then be pointing on the 3044 * next op code. 3045 */ 3046 offset += res; 3047 } else { 3048 NV_ERROR(bios->dev, 3049 "0x%04X: Init table command not found: " 3050 "0x%02X\n", offset, id); 3051 return -ENOENT; 3052 } 3053 } 3054 3055 if (offset >= bios->length) 3056 NV_WARN(bios->dev, 3057 "Offset 0x%04X greater than known bios image length. " 3058 "Corrupt image?\n", offset); 3059 if (count >= MAX_TABLE_OPS) 3060 NV_WARN(bios->dev, 3061 "More than %d opcodes to a table is unlikely, " 3062 "is the bios image corrupt?\n", MAX_TABLE_OPS); 3063 3064 return 0; 3065} 3066 3067static void 3068parse_init_tables(struct nvbios *bios) 3069{ 3070 /* Loops and calls parse_init_table() for each present table. */ 3071 3072 int i = 0; 3073 uint16_t table; 3074 struct init_exec iexec = {true, false}; 3075 3076 if (bios->old_style_init) { 3077 if (bios->init_script_tbls_ptr) 3078 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec); 3079 if (bios->extra_init_script_tbl_ptr) 3080 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec); 3081 3082 return; 3083 } 3084 3085 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) { 3086 NV_INFO(bios->dev, 3087 "Parsing VBIOS init table %d at offset 0x%04X\n", 3088 i / 2, table); 3089 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table); 3090 3091 parse_init_table(bios, table, &iexec); 3092 i += 2; 3093 } 3094} 3095 3096static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk) 3097{ 3098 int compare_record_len, i = 0; 3099 uint16_t compareclk, scriptptr = 0; 3100 3101 if (bios->major_version < 5) /* pre BIT */ 3102 compare_record_len = 3; 3103 else 3104 compare_record_len = 4; 3105 3106 do { 3107 compareclk = ROM16(bios->data[clktable + compare_record_len * i]); 3108 if (pxclk >= compareclk * 10) { 3109 if (bios->major_version < 5) { 3110 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i]; 3111 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]); 3112 } else 3113 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]); 3114 break; 3115 } 3116 i++; 3117 } while (compareclk); 3118 3119 return scriptptr; 3120} 3121 3122static void 3123run_digital_op_script(struct drm_device *dev, uint16_t scriptptr, 3124 struct dcb_entry *dcbent, int head, bool dl) 3125{ 3126 struct drm_nouveau_private *dev_priv = dev->dev_private; 3127 struct nvbios *bios = &dev_priv->vbios; 3128 struct init_exec iexec = {true, false}; 3129 3130 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n", 3131 scriptptr); 3132 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44, 3133 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA); 3134 /* note: if dcb entries have been merged, index may be misleading */ 3135 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index); 3136 parse_init_table(bios, scriptptr, &iexec); 3137 3138 nv04_dfp_bind_head(dev, dcbent, head, dl); 3139} 3140 3141static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script) 3142{ 3143 struct drm_nouveau_private *dev_priv = dev->dev_private; 3144 struct nvbios *bios = &dev_priv->vbios; 3145 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0); 3146 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]); 3147 3148 if (!bios->fp.xlated_entry || !sub || !scriptofs) 3149 return -EINVAL; 3150 3151 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link); 3152 3153 if (script == LVDS_PANEL_OFF) { 3154 /* off-on delay in ms */ 3155 msleep(ROM16(bios->data[bios->fp.xlated_entry + 7])); 3156 } 3157#ifdef __powerpc__ 3158 /* Powerbook specific quirks */ 3159 if ((dev->pci_device & 0xffff) == 0x0179 || 3160 (dev->pci_device & 0xffff) == 0x0189 || 3161 (dev->pci_device & 0xffff) == 0x0329) { 3162 if (script == LVDS_RESET) { 3163 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72); 3164 3165 } else if (script == LVDS_PANEL_ON) { 3166 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL, 3167 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL) 3168 | (1 << 31)); 3169 bios_wr32(bios, NV_PCRTC_GPIO_EXT, 3170 bios_rd32(bios, NV_PCRTC_GPIO_EXT) | 1); 3171 3172 } else if (script == LVDS_PANEL_OFF) { 3173 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL, 3174 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL) 3175 & ~(1 << 31)); 3176 bios_wr32(bios, NV_PCRTC_GPIO_EXT, 3177 bios_rd32(bios, NV_PCRTC_GPIO_EXT) & ~3); 3178 } 3179 } 3180#endif 3181 3182 return 0; 3183} 3184 3185static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk) 3186{ 3187 /* 3188 * The BIT LVDS table's header has the information to setup the 3189 * necessary registers. Following the standard 4 byte header are: 3190 * A bitmask byte and a dual-link transition pxclk value for use in 3191 * selecting the init script when not using straps; 4 script pointers 3192 * for panel power, selected by output and on/off; and 8 table pointers 3193 * for panel init, the needed one determined by output, and bits in the 3194 * conf byte. These tables are similar to the TMDS tables, consisting 3195 * of a list of pxclks and script pointers. 3196 */ 3197 struct drm_nouveau_private *dev_priv = dev->dev_private; 3198 struct nvbios *bios = &dev_priv->vbios; 3199 unsigned int outputset = (dcbent->or == 4) ? 1 : 0; 3200 uint16_t scriptptr = 0, clktable; 3201 3202 /* 3203 * For now we assume version 3.0 table - g80 support will need some 3204 * changes 3205 */ 3206 3207 switch (script) { 3208 case LVDS_INIT: 3209 return -ENOSYS; 3210 case LVDS_BACKLIGHT_ON: 3211 case LVDS_PANEL_ON: 3212 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]); 3213 break; 3214 case LVDS_BACKLIGHT_OFF: 3215 case LVDS_PANEL_OFF: 3216 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]); 3217 break; 3218 case LVDS_RESET: 3219 clktable = bios->fp.lvdsmanufacturerpointer + 15; 3220 if (dcbent->or == 4) 3221 clktable += 8; 3222 3223 if (dcbent->lvdsconf.use_straps_for_mode) { 3224 if (bios->fp.dual_link) 3225 clktable += 4; 3226 if (bios->fp.if_is_24bit) 3227 clktable += 2; 3228 } else { 3229 /* using EDID */ 3230 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1; 3231 3232 if (bios->fp.dual_link) { 3233 clktable += 4; 3234 cmpval_24bit <<= 1; 3235 } 3236 3237 if (bios->fp.strapless_is_24bit & cmpval_24bit) 3238 clktable += 2; 3239 } 3240 3241 clktable = ROM16(bios->data[clktable]); 3242 if (!clktable) { 3243 NV_ERROR(dev, "Pixel clock comparison table not found\n"); 3244 return -ENOENT; 3245 } 3246 scriptptr = clkcmptable(bios, clktable, pxclk); 3247 } 3248 3249 if (!scriptptr) { 3250 NV_ERROR(dev, "LVDS output init script not found\n"); 3251 return -ENOENT; 3252 } 3253 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link); 3254 3255 return 0; 3256} 3257 3258int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk) 3259{ 3260 /* 3261 * LVDS operations are multiplexed in an effort to present a single API 3262 * which works with two vastly differing underlying structures. 3263 * This acts as the demux 3264 */ 3265 3266 struct drm_nouveau_private *dev_priv = dev->dev_private; 3267 struct nvbios *bios = &dev_priv->vbios; 3268 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer]; 3269 uint32_t sel_clk_binding, sel_clk; 3270 int ret; 3271 3272 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver || 3273 (lvds_ver >= 0x30 && script == LVDS_INIT)) 3274 return 0; 3275 3276 if (!bios->fp.lvds_init_run) { 3277 bios->fp.lvds_init_run = true; 3278 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk); 3279 } 3280 3281 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change) 3282 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk); 3283 if (script == LVDS_RESET && bios->fp.power_off_for_reset) 3284 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk); 3285 3286 NV_TRACE(dev, "Calling LVDS script %d:\n", script); 3287 3288 /* don't let script change pll->head binding */ 3289 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000; 3290 3291 if (lvds_ver < 0x30) 3292 ret = call_lvds_manufacturer_script(dev, dcbent, head, script); 3293 else 3294 ret = run_lvds_table(dev, dcbent, head, script, pxclk); 3295 3296 bios->fp.last_script_invoc = (script << 1 | head); 3297 3298 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; 3299 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); 3300 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */ 3301 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0); 3302 3303 return ret; 3304} 3305 3306struct lvdstableheader { 3307 uint8_t lvds_ver, headerlen, recordlen; 3308}; 3309 3310static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth) 3311{ 3312 /* 3313 * BMP version (0xa) LVDS table has a simple header of version and 3314 * record length. The BIT LVDS table has the typical BIT table header: 3315 * version byte, header length byte, record length byte, and a byte for 3316 * the maximum number of records that can be held in the table. 3317 */ 3318 3319 uint8_t lvds_ver, headerlen, recordlen; 3320 3321 memset(lth, 0, sizeof(struct lvdstableheader)); 3322 3323 if (bios->fp.lvdsmanufacturerpointer == 0x0) { 3324 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n"); 3325 return -EINVAL; 3326 } 3327 3328 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer]; 3329 3330 switch (lvds_ver) { 3331 case 0x0a: /* pre NV40 */ 3332 headerlen = 2; 3333 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 3334 break; 3335 case 0x30: /* NV4x */ 3336 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 3337 if (headerlen < 0x1f) { 3338 NV_ERROR(dev, "LVDS table header not understood\n"); 3339 return -EINVAL; 3340 } 3341 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2]; 3342 break; 3343 case 0x40: /* G80/G90 */ 3344 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 3345 if (headerlen < 0x7) { 3346 NV_ERROR(dev, "LVDS table header not understood\n"); 3347 return -EINVAL; 3348 } 3349 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2]; 3350 break; 3351 default: 3352 NV_ERROR(dev, 3353 "LVDS table revision %d.%d not currently supported\n", 3354 lvds_ver >> 4, lvds_ver & 0xf); 3355 return -ENOSYS; 3356 } 3357 3358 lth->lvds_ver = lvds_ver; 3359 lth->headerlen = headerlen; 3360 lth->recordlen = recordlen; 3361 3362 return 0; 3363} 3364 3365static int 3366get_fp_strap(struct drm_device *dev, struct nvbios *bios) 3367{ 3368 struct drm_nouveau_private *dev_priv = dev->dev_private; 3369 3370 /* 3371 * The fp strap is normally dictated by the "User Strap" in 3372 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the 3373 * Internal_Flags struct at 0x48 is set, the user strap gets overriden 3374 * by the PCI subsystem ID during POST, but not before the previous user 3375 * strap has been committed to CR58 for CR57=0xf on head A, which may be 3376 * read and used instead 3377 */ 3378 3379 if (bios->major_version < 5 && bios->data[0x48] & 0x4) 3380 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf; 3381 3382 if (dev_priv->card_type >= NV_50) 3383 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf; 3384 else 3385 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf; 3386} 3387 3388static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios) 3389{ 3390 uint8_t *fptable; 3391 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex; 3392 int ret, ofs, fpstrapping; 3393 struct lvdstableheader lth; 3394 3395 if (bios->fp.fptablepointer == 0x0) { 3396 /* Apple cards don't have the fp table; the laptops use DDC */ 3397 /* The table is also missing on some x86 IGPs */ 3398#ifndef __powerpc__ 3399 NV_ERROR(dev, "Pointer to flat panel table invalid\n"); 3400#endif 3401 bios->digital_min_front_porch = 0x4b; 3402 return 0; 3403 } 3404 3405 fptable = &bios->data[bios->fp.fptablepointer]; 3406 fptable_ver = fptable[0]; 3407 3408 switch (fptable_ver) { 3409 /* 3410 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no 3411 * version field, and miss one of the spread spectrum/PWM bytes. 3412 * This could affect early GF2Go parts (not seen any appropriate ROMs 3413 * though). Here we assume that a version of 0x05 matches this case 3414 * (combining with a BMP version check would be better), as the 3415 * common case for the panel type field is 0x0005, and that is in 3416 * fact what we are reading the first byte of. 3417 */ 3418 case 0x05: /* some NV10, 11, 15, 16 */ 3419 recordlen = 42; 3420 ofs = -1; 3421 break; 3422 case 0x10: /* some NV15/16, and NV11+ */ 3423 recordlen = 44; 3424 ofs = 0; 3425 break; 3426 case 0x20: /* NV40+ */ 3427 headerlen = fptable[1]; 3428 recordlen = fptable[2]; 3429 fpentries = fptable[3]; 3430 /* 3431 * fptable[4] is the minimum 3432 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap 3433 */ 3434 bios->digital_min_front_porch = fptable[4]; 3435 ofs = -7; 3436 break; 3437 default: 3438 NV_ERROR(dev, 3439 "FP table revision %d.%d not currently supported\n", 3440 fptable_ver >> 4, fptable_ver & 0xf); 3441 return -ENOSYS; 3442 } 3443 3444 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */ 3445 return 0; 3446 3447 ret = parse_lvds_manufacturer_table_header(dev, bios, <h); 3448 if (ret) 3449 return ret; 3450 3451 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) { 3452 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer + 3453 lth.headerlen + 1; 3454 bios->fp.xlatwidth = lth.recordlen; 3455 } 3456 if (bios->fp.fpxlatetableptr == 0x0) { 3457 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n"); 3458 return -EINVAL; 3459 } 3460 3461 fpstrapping = get_fp_strap(dev, bios); 3462 3463 fpindex = bios->data[bios->fp.fpxlatetableptr + 3464 fpstrapping * bios->fp.xlatwidth]; 3465 3466 if (fpindex > fpentries) { 3467 NV_ERROR(dev, "Bad flat panel table index\n"); 3468 return -ENOENT; 3469 } 3470 3471 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */ 3472 if (lth.lvds_ver > 0x10) 3473 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf; 3474 3475 /* 3476 * If either the strap or xlated fpindex value are 0xf there is no 3477 * panel using a strap-derived bios mode present. this condition 3478 * includes, but is different from, the DDC panel indicator above 3479 */ 3480 if (fpstrapping == 0xf || fpindex == 0xf) 3481 return 0; 3482 3483 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen + 3484 recordlen * fpindex + ofs; 3485 3486 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n", 3487 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1, 3488 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1, 3489 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10); 3490 3491 return 0; 3492} 3493 3494bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode) 3495{ 3496 struct drm_nouveau_private *dev_priv = dev->dev_private; 3497 struct nvbios *bios = &dev_priv->vbios; 3498 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr]; 3499 3500 if (!mode) /* just checking whether we can produce a mode */ 3501 return bios->fp.mode_ptr; 3502 3503 memset(mode, 0, sizeof(struct drm_display_mode)); 3504 /* 3505 * For version 1.0 (version in byte 0): 3506 * bytes 1-2 are "panel type", including bits on whether Colour/mono, 3507 * single/dual link, and type (TFT etc.) 3508 * bytes 3-6 are bits per colour in RGBX 3509 */ 3510 mode->clock = ROM16(mode_entry[7]) * 10; 3511 /* bytes 9-10 is HActive */ 3512 mode->hdisplay = ROM16(mode_entry[11]) + 1; 3513 /* 3514 * bytes 13-14 is HValid Start 3515 * bytes 15-16 is HValid End 3516 */ 3517 mode->hsync_start = ROM16(mode_entry[17]) + 1; 3518 mode->hsync_end = ROM16(mode_entry[19]) + 1; 3519 mode->htotal = ROM16(mode_entry[21]) + 1; 3520 /* bytes 23-24, 27-30 similarly, but vertical */ 3521 mode->vdisplay = ROM16(mode_entry[25]) + 1; 3522 mode->vsync_start = ROM16(mode_entry[31]) + 1; 3523 mode->vsync_end = ROM16(mode_entry[33]) + 1; 3524 mode->vtotal = ROM16(mode_entry[35]) + 1; 3525 mode->flags |= (mode_entry[37] & 0x10) ? 3526 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3527 mode->flags |= (mode_entry[37] & 0x1) ? 3528 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3529 /* 3530 * bytes 38-39 relate to spread spectrum settings 3531 * bytes 40-43 are something to do with PWM 3532 */ 3533 3534 mode->status = MODE_OK; 3535 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; 3536 drm_mode_set_name(mode); 3537 return bios->fp.mode_ptr; 3538} 3539 3540int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit) 3541{ 3542 /* 3543 * The LVDS table header is (mostly) described in 3544 * parse_lvds_manufacturer_table_header(): the BIT header additionally 3545 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if 3546 * straps are not being used for the panel, this specifies the frequency 3547 * at which modes should be set up in the dual link style. 3548 * 3549 * Following the header, the BMP (ver 0xa) table has several records, 3550 * indexed by a separate xlat table, indexed in turn by the fp strap in 3551 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script 3552 * numbers for use by INIT_SUB which controlled panel init and power, 3553 * and finally a dword of ms to sleep between power off and on 3554 * operations. 3555 * 3556 * In the BIT versions, the table following the header serves as an 3557 * integrated config and xlat table: the records in the table are 3558 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has 3559 * two bytes - the first as a config byte, the second for indexing the 3560 * fp mode table pointed to by the BIT 'D' table 3561 * 3562 * DDC is not used until after card init, so selecting the correct table 3563 * entry and setting the dual link flag for EDID equipped panels, 3564 * requiring tests against the native-mode pixel clock, cannot be done 3565 * until later, when this function should be called with non-zero pxclk 3566 */ 3567 struct drm_nouveau_private *dev_priv = dev->dev_private; 3568 struct nvbios *bios = &dev_priv->vbios; 3569 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0; 3570 struct lvdstableheader lth; 3571 uint16_t lvdsofs; 3572 int ret, chip_version = bios->chip_version; 3573 3574 ret = parse_lvds_manufacturer_table_header(dev, bios, <h); 3575 if (ret) 3576 return ret; 3577 3578 switch (lth.lvds_ver) { 3579 case 0x0a: /* pre NV40 */ 3580 lvdsmanufacturerindex = bios->data[ 3581 bios->fp.fpxlatemanufacturertableptr + 3582 fpstrapping]; 3583 3584 /* we're done if this isn't the EDID panel case */ 3585 if (!pxclk) 3586 break; 3587 3588 if (chip_version < 0x25) { 3589 /* nv17 behaviour 3590 * 3591 * It seems the old style lvds script pointer is reused 3592 * to select 18/24 bit colour depth for EDID panels. 3593 */ 3594 lvdsmanufacturerindex = 3595 (bios->legacy.lvds_single_a_script_ptr & 1) ? 3596 2 : 0; 3597 if (pxclk >= bios->fp.duallink_transition_clk) 3598 lvdsmanufacturerindex++; 3599 } else if (chip_version < 0x30) { 3600 /* nv28 behaviour (off-chip encoder) 3601 * 3602 * nv28 does a complex dance of first using byte 121 of 3603 * the EDID to choose the lvdsmanufacturerindex, then 3604 * later attempting to match the EDID manufacturer and 3605 * product IDs in a table (signature 'pidt' (panel id 3606 * table?)), setting an lvdsmanufacturerindex of 0 and 3607 * an fp strap of the match index (or 0xf if none) 3608 */ 3609 lvdsmanufacturerindex = 0; 3610 } else { 3611 /* nv31, nv34 behaviour */ 3612 lvdsmanufacturerindex = 0; 3613 if (pxclk >= bios->fp.duallink_transition_clk) 3614 lvdsmanufacturerindex = 2; 3615 if (pxclk >= 140000) 3616 lvdsmanufacturerindex = 3; 3617 } 3618 3619 /* 3620 * nvidia set the high nibble of (cr57=f, cr58) to 3621 * lvdsmanufacturerindex in this case; we don't 3622 */ 3623 break; 3624 case 0x30: /* NV4x */ 3625 case 0x40: /* G80/G90 */ 3626 lvdsmanufacturerindex = fpstrapping; 3627 break; 3628 default: 3629 NV_ERROR(dev, "LVDS table revision not currently supported\n"); 3630 return -ENOSYS; 3631 } 3632 3633 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex; 3634 switch (lth.lvds_ver) { 3635 case 0x0a: 3636 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1; 3637 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2; 3638 bios->fp.dual_link = bios->data[lvdsofs] & 4; 3639 bios->fp.link_c_increment = bios->data[lvdsofs] & 8; 3640 *if_is_24bit = bios->data[lvdsofs] & 16; 3641 break; 3642 case 0x30: 3643 case 0x40: 3644 /* 3645 * No sign of the "power off for reset" or "reset for panel 3646 * on" bits, but it's safer to assume we should 3647 */ 3648 bios->fp.power_off_for_reset = true; 3649 bios->fp.reset_after_pclk_change = true; 3650 3651 /* 3652 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is 3653 * over-written, and if_is_24bit isn't used 3654 */ 3655 bios->fp.dual_link = bios->data[lvdsofs] & 1; 3656 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2; 3657 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4]; 3658 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10; 3659 break; 3660 } 3661 3662 /* set dual_link flag for EDID case */ 3663 if (pxclk && (chip_version < 0x25 || chip_version > 0x28)) 3664 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk); 3665 3666 *dl = bios->fp.dual_link; 3667 3668 return 0; 3669} 3670 3671static uint8_t * 3672bios_output_config_match(struct drm_device *dev, struct dcb_entry *dcbent, 3673 uint16_t record, int record_len, int record_nr) 3674{ 3675 struct drm_nouveau_private *dev_priv = dev->dev_private; 3676 struct nvbios *bios = &dev_priv->vbios; 3677 uint32_t entry; 3678 uint16_t table; 3679 int i, v; 3680 3681 for (i = 0; i < record_nr; i++, record += record_len) { 3682 table = ROM16(bios->data[record]); 3683 if (!table) 3684 continue; 3685 entry = ROM32(bios->data[table]); 3686 3687 v = (entry & 0x000f0000) >> 16; 3688 if (!(v & dcbent->or)) 3689 continue; 3690 3691 v = (entry & 0x000000f0) >> 4; 3692 if (v != dcbent->location) 3693 continue; 3694 3695 v = (entry & 0x0000000f); 3696 if (v != dcbent->type) 3697 continue; 3698 3699 return &bios->data[table]; 3700 } 3701 3702 return NULL; 3703} 3704 3705void * 3706nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent, 3707 int *length) 3708{ 3709 struct drm_nouveau_private *dev_priv = dev->dev_private; 3710 struct nvbios *bios = &dev_priv->vbios; 3711 uint8_t *table; 3712 3713 if (!bios->display.dp_table_ptr) { 3714 NV_ERROR(dev, "No pointer to DisplayPort table\n"); 3715 return NULL; 3716 } 3717 table = &bios->data[bios->display.dp_table_ptr]; 3718 3719 if (table[0] != 0x20 && table[0] != 0x21) { 3720 NV_ERROR(dev, "DisplayPort table version 0x%02x unknown\n", 3721 table[0]); 3722 return NULL; 3723 } 3724 3725 *length = table[4]; 3726 return bios_output_config_match(dev, dcbent, 3727 bios->display.dp_table_ptr + table[1], 3728 table[2], table[3]); 3729} 3730 3731int 3732nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent, 3733 uint32_t sub, int pxclk) 3734{ 3735 /* 3736 * The display script table is located by the BIT 'U' table. 3737 * 3738 * It contains an array of pointers to various tables describing 3739 * a particular output type. The first 32-bits of the output 3740 * tables contains similar information to a DCB entry, and is 3741 * used to decide whether that particular table is suitable for 3742 * the output you want to access. 3743 * 3744 * The "record header length" field here seems to indicate the 3745 * offset of the first configuration entry in the output tables. 3746 * This is 10 on most cards I've seen, but 12 has been witnessed 3747 * on DP cards, and there's another script pointer within the 3748 * header. 3749 * 3750 * offset + 0 ( 8 bits): version 3751 * offset + 1 ( 8 bits): header length 3752 * offset + 2 ( 8 bits): record length 3753 * offset + 3 ( 8 bits): number of records 3754 * offset + 4 ( 8 bits): record header length 3755 * offset + 5 (16 bits): pointer to first output script table 3756 */ 3757 3758 struct drm_nouveau_private *dev_priv = dev->dev_private; 3759 struct nvbios *bios = &dev_priv->vbios; 3760 uint8_t *table = &bios->data[bios->display.script_table_ptr]; 3761 uint8_t *otable = NULL; 3762 uint16_t script; 3763 int i = 0; 3764 3765 if (!bios->display.script_table_ptr) { 3766 NV_ERROR(dev, "No pointer to output script table\n"); 3767 return 1; 3768 } 3769 3770 /* 3771 * Nothing useful has been in any of the pre-2.0 tables I've seen, 3772 * so until they are, we really don't need to care. 3773 */ 3774 if (table[0] < 0x20) 3775 return 1; 3776 3777 if (table[0] != 0x20 && table[0] != 0x21) { 3778 NV_ERROR(dev, "Output script table version 0x%02x unknown\n", 3779 table[0]); 3780 return 1; 3781 } 3782 3783 /* 3784 * The output script tables describing a particular output type 3785 * look as follows: 3786 * 3787 * offset + 0 (32 bits): output this table matches (hash of DCB) 3788 * offset + 4 ( 8 bits): unknown 3789 * offset + 5 ( 8 bits): number of configurations 3790 * offset + 6 (16 bits): pointer to some script 3791 * offset + 8 (16 bits): pointer to some script 3792 * 3793 * headerlen == 10 3794 * offset + 10 : configuration 0 3795 * 3796 * headerlen == 12 3797 * offset + 10 : pointer to some script 3798 * offset + 12 : configuration 0 3799 * 3800 * Each config entry is as follows: 3801 * 3802 * offset + 0 (16 bits): unknown, assumed to be a match value 3803 * offset + 2 (16 bits): pointer to script table (clock set?) 3804 * offset + 4 (16 bits): pointer to script table (reset?) 3805 * 3806 * There doesn't appear to be a count value to say how many 3807 * entries exist in each script table, instead, a 0 value in 3808 * the first 16-bit word seems to indicate both the end of the 3809 * list and the default entry. The second 16-bit word in the 3810 * script tables is a pointer to the script to execute. 3811 */ 3812 3813 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n", 3814 dcbent->type, dcbent->location, dcbent->or); 3815 otable = bios_output_config_match(dev, dcbent, table[1] + 3816 bios->display.script_table_ptr, 3817 table[2], table[3]); 3818 if (!otable) { 3819 NV_ERROR(dev, "Couldn't find matching output script table\n"); 3820 return 1; 3821 } 3822 3823 if (pxclk < -2 || pxclk > 0) { 3824 /* Try to find matching script table entry */ 3825 for (i = 0; i < otable[5]; i++) { 3826 if (ROM16(otable[table[4] + i*6]) == sub) 3827 break; 3828 } 3829 3830 if (i == otable[5]) { 3831 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, " 3832 "using first\n", 3833 sub, dcbent->type, dcbent->or); 3834 i = 0; 3835 } 3836 } 3837 3838 if (pxclk == 0) { 3839 script = ROM16(otable[6]); 3840 if (!script) { 3841 NV_DEBUG_KMS(dev, "output script 0 not found\n"); 3842 return 1; 3843 } 3844 3845 NV_TRACE(dev, "0x%04X: parsing output script 0\n", script); 3846 nouveau_bios_run_init_table(dev, script, dcbent); 3847 } else 3848 if (pxclk == -1) { 3849 script = ROM16(otable[8]); 3850 if (!script) { 3851 NV_DEBUG_KMS(dev, "output script 1 not found\n"); 3852 return 1; 3853 } 3854 3855 NV_TRACE(dev, "0x%04X: parsing output script 1\n", script); 3856 nouveau_bios_run_init_table(dev, script, dcbent); 3857 } else 3858 if (pxclk == -2) { 3859 if (table[4] >= 12) 3860 script = ROM16(otable[10]); 3861 else 3862 script = 0; 3863 if (!script) { 3864 NV_DEBUG_KMS(dev, "output script 2 not found\n"); 3865 return 1; 3866 } 3867 3868 NV_TRACE(dev, "0x%04X: parsing output script 2\n", script); 3869 nouveau_bios_run_init_table(dev, script, dcbent); 3870 } else 3871 if (pxclk > 0) { 3872 script = ROM16(otable[table[4] + i*6 + 2]); 3873 if (script) 3874 script = clkcmptable(bios, script, pxclk); 3875 if (!script) { 3876 NV_ERROR(dev, "clock script 0 not found\n"); 3877 return 1; 3878 } 3879 3880 NV_TRACE(dev, "0x%04X: parsing clock script 0\n", script); 3881 nouveau_bios_run_init_table(dev, script, dcbent); 3882 } else 3883 if (pxclk < 0) { 3884 script = ROM16(otable[table[4] + i*6 + 4]); 3885 if (script) 3886 script = clkcmptable(bios, script, -pxclk); 3887 if (!script) { 3888 NV_DEBUG_KMS(dev, "clock script 1 not found\n"); 3889 return 1; 3890 } 3891 3892 NV_TRACE(dev, "0x%04X: parsing clock script 1\n", script); 3893 nouveau_bios_run_init_table(dev, script, dcbent); 3894 } 3895 3896 return 0; 3897} 3898 3899 3900int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk) 3901{ 3902 /* 3903 * the pxclk parameter is in kHz 3904 * 3905 * This runs the TMDS regs setting code found on BIT bios cards 3906 * 3907 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and 3908 * ffs(or) == 3, use the second. 3909 */ 3910 3911 struct drm_nouveau_private *dev_priv = dev->dev_private; 3912 struct nvbios *bios = &dev_priv->vbios; 3913 int cv = bios->chip_version; 3914 uint16_t clktable = 0, scriptptr; 3915 uint32_t sel_clk_binding, sel_clk; 3916 3917 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */ 3918 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 && 3919 dcbent->location != DCB_LOC_ON_CHIP) 3920 return 0; 3921 3922 switch (ffs(dcbent->or)) { 3923 case 1: 3924 clktable = bios->tmds.output0_script_ptr; 3925 break; 3926 case 2: 3927 case 3: 3928 clktable = bios->tmds.output1_script_ptr; 3929 break; 3930 } 3931 3932 if (!clktable) { 3933 NV_ERROR(dev, "Pixel clock comparison table not found\n"); 3934 return -EINVAL; 3935 } 3936 3937 scriptptr = clkcmptable(bios, clktable, pxclk); 3938 3939 if (!scriptptr) { 3940 NV_ERROR(dev, "TMDS output init script not found\n"); 3941 return -ENOENT; 3942 } 3943 3944 /* don't let script change pll->head binding */ 3945 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000; 3946 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000); 3947 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; 3948 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); 3949 3950 return 0; 3951} 3952 3953int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim) 3954{ 3955 /* 3956 * PLL limits table 3957 * 3958 * Version 0x10: NV30, NV31 3959 * One byte header (version), one record of 24 bytes 3960 * Version 0x11: NV36 - Not implemented 3961 * Seems to have same record style as 0x10, but 3 records rather than 1 3962 * Version 0x20: Found on Geforce 6 cards 3963 * Trivial 4 byte BIT header. 31 (0x1f) byte record length 3964 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards 3965 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record 3966 * length in general, some (integrated) have an extra configuration byte 3967 * Version 0x30: Found on Geforce 8, separates the register mapping 3968 * from the limits tables. 3969 */ 3970 3971 struct drm_nouveau_private *dev_priv = dev->dev_private; 3972 struct nvbios *bios = &dev_priv->vbios; 3973 int cv = bios->chip_version, pllindex = 0; 3974 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0; 3975 uint32_t crystal_strap_mask, crystal_straps; 3976 3977 if (!bios->pll_limit_tbl_ptr) { 3978 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 || 3979 cv >= 0x40) { 3980 NV_ERROR(dev, "Pointer to PLL limits table invalid\n"); 3981 return -EINVAL; 3982 } 3983 } else 3984 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr]; 3985 3986 crystal_strap_mask = 1 << 6; 3987 /* open coded dev->twoHeads test */ 3988 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20) 3989 crystal_strap_mask |= 1 << 22; 3990 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) & 3991 crystal_strap_mask; 3992 3993 switch (pll_lim_ver) { 3994 /* 3995 * We use version 0 to indicate a pre limit table bios (single stage 3996 * pll) and load the hard coded limits instead. 3997 */ 3998 case 0: 3999 break; 4000 case 0x10: 4001 case 0x11: 4002 /* 4003 * Strictly v0x11 has 3 entries, but the last two don't seem 4004 * to get used. 4005 */ 4006 headerlen = 1; 4007 recordlen = 0x18; 4008 entries = 1; 4009 pllindex = 0; 4010 break; 4011 case 0x20: 4012 case 0x21: 4013 case 0x30: 4014 case 0x40: 4015 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1]; 4016 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2]; 4017 entries = bios->data[bios->pll_limit_tbl_ptr + 3]; 4018 break; 4019 default: 4020 NV_ERROR(dev, "PLL limits table revision 0x%X not currently " 4021 "supported\n", pll_lim_ver); 4022 return -ENOSYS; 4023 } 4024 4025 /* initialize all members to zero */ 4026 memset(pll_lim, 0, sizeof(struct pll_lims)); 4027 4028 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) { 4029 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex]; 4030 4031 pll_lim->vco1.minfreq = ROM32(pll_rec[0]); 4032 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]); 4033 pll_lim->vco2.minfreq = ROM32(pll_rec[8]); 4034 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]); 4035 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]); 4036 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]); 4037 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX; 4038 4039 /* these values taken from nv30/31/36 */ 4040 pll_lim->vco1.min_n = 0x1; 4041 if (cv == 0x36) 4042 pll_lim->vco1.min_n = 0x5; 4043 pll_lim->vco1.max_n = 0xff; 4044 pll_lim->vco1.min_m = 0x1; 4045 pll_lim->vco1.max_m = 0xd; 4046 pll_lim->vco2.min_n = 0x4; 4047 /* 4048 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this 4049 * table version (apart from nv35)), N2 is compared to 4050 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and 4051 * save a comparison 4052 */ 4053 pll_lim->vco2.max_n = 0x28; 4054 if (cv == 0x30 || cv == 0x35) 4055 /* only 5 bits available for N2 on nv30/35 */ 4056 pll_lim->vco2.max_n = 0x1f; 4057 pll_lim->vco2.min_m = 0x1; 4058 pll_lim->vco2.max_m = 0x4; 4059 pll_lim->max_log2p = 0x7; 4060 pll_lim->max_usable_log2p = 0x6; 4061 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) { 4062 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen; 4063 uint32_t reg = 0; /* default match */ 4064 uint8_t *pll_rec; 4065 int i; 4066 4067 /* 4068 * First entry is default match, if nothing better. warn if 4069 * reg field nonzero 4070 */ 4071 if (ROM32(bios->data[plloffs])) 4072 NV_WARN(dev, "Default PLL limit entry has non-zero " 4073 "register field\n"); 4074 4075 if (limit_match > MAX_PLL_TYPES) 4076 /* we've been passed a reg as the match */ 4077 reg = limit_match; 4078 else /* limit match is a pll type */ 4079 for (i = 1; i < entries && !reg; i++) { 4080 uint32_t cmpreg = ROM32(bios->data[plloffs + recordlen * i]); 4081 4082 if (limit_match == NVPLL && 4083 (cmpreg == NV_PRAMDAC_NVPLL_COEFF || cmpreg == 0x4000)) 4084 reg = cmpreg; 4085 if (limit_match == MPLL && 4086 (cmpreg == NV_PRAMDAC_MPLL_COEFF || cmpreg == 0x4020)) 4087 reg = cmpreg; 4088 if (limit_match == VPLL1 && 4089 (cmpreg == NV_PRAMDAC_VPLL_COEFF || cmpreg == 0x4010)) 4090 reg = cmpreg; 4091 if (limit_match == VPLL2 && 4092 (cmpreg == NV_RAMDAC_VPLL2 || cmpreg == 0x4018)) 4093 reg = cmpreg; 4094 } 4095 4096 for (i = 1; i < entries; i++) 4097 if (ROM32(bios->data[plloffs + recordlen * i]) == reg) { 4098 pllindex = i; 4099 break; 4100 } 4101 4102 pll_rec = &bios->data[plloffs + recordlen * pllindex]; 4103 4104 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n", 4105 pllindex ? reg : 0); 4106 4107 /* 4108 * Frequencies are stored in tables in MHz, kHz are more 4109 * useful, so we convert. 4110 */ 4111 4112 /* What output frequencies can each VCO generate? */ 4113 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000; 4114 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000; 4115 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000; 4116 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000; 4117 4118 /* What input frequencies they accept (past the m-divider)? */ 4119 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000; 4120 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000; 4121 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000; 4122 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000; 4123 4124 /* What values are accepted as multiplier and divider? */ 4125 pll_lim->vco1.min_n = pll_rec[20]; 4126 pll_lim->vco1.max_n = pll_rec[21]; 4127 pll_lim->vco1.min_m = pll_rec[22]; 4128 pll_lim->vco1.max_m = pll_rec[23]; 4129 pll_lim->vco2.min_n = pll_rec[24]; 4130 pll_lim->vco2.max_n = pll_rec[25]; 4131 pll_lim->vco2.min_m = pll_rec[26]; 4132 pll_lim->vco2.max_m = pll_rec[27]; 4133 4134 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29]; 4135 if (pll_lim->max_log2p > 0x7) 4136 /* pll decoding in nv_hw.c assumes never > 7 */ 4137 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n", 4138 pll_lim->max_log2p); 4139 if (cv < 0x60) 4140 pll_lim->max_usable_log2p = 0x6; 4141 pll_lim->log2p_bias = pll_rec[30]; 4142 4143 if (recordlen > 0x22) 4144 pll_lim->refclk = ROM32(pll_rec[31]); 4145 4146 if (recordlen > 0x23 && pll_rec[35]) 4147 NV_WARN(dev, 4148 "Bits set in PLL configuration byte (%x)\n", 4149 pll_rec[35]); 4150 4151 /* C51 special not seen elsewhere */ 4152 if (cv == 0x51 && !pll_lim->refclk) { 4153 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK); 4154 4155 if (((limit_match == NV_PRAMDAC_VPLL_COEFF || limit_match == VPLL1) && sel_clk & 0x20) || 4156 ((limit_match == NV_RAMDAC_VPLL2 || limit_match == VPLL2) && sel_clk & 0x80)) { 4157 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3) 4158 pll_lim->refclk = 200000; 4159 else 4160 pll_lim->refclk = 25000; 4161 } 4162 } 4163 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */ 4164 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen]; 4165 uint8_t *record = NULL; 4166 int i; 4167 4168 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n", 4169 limit_match); 4170 4171 for (i = 0; i < entries; i++, entry += recordlen) { 4172 if (ROM32(entry[3]) == limit_match) { 4173 record = &bios->data[ROM16(entry[1])]; 4174 break; 4175 } 4176 } 4177 4178 if (!record) { 4179 NV_ERROR(dev, "Register 0x%08x not found in PLL " 4180 "limits table", limit_match); 4181 return -ENOENT; 4182 } 4183 4184 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000; 4185 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000; 4186 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000; 4187 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000; 4188 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000; 4189 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000; 4190 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000; 4191 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000; 4192 pll_lim->vco1.min_n = record[16]; 4193 pll_lim->vco1.max_n = record[17]; 4194 pll_lim->vco1.min_m = record[18]; 4195 pll_lim->vco1.max_m = record[19]; 4196 pll_lim->vco2.min_n = record[20]; 4197 pll_lim->vco2.max_n = record[21]; 4198 pll_lim->vco2.min_m = record[22]; 4199 pll_lim->vco2.max_m = record[23]; 4200 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25]; 4201 pll_lim->log2p_bias = record[27]; 4202 pll_lim->refclk = ROM32(record[28]); 4203 } else if (pll_lim_ver) { /* ver 0x40 */ 4204 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen]; 4205 uint8_t *record = NULL; 4206 int i; 4207 4208 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n", 4209 limit_match); 4210 4211 for (i = 0; i < entries; i++, entry += recordlen) { 4212 if (ROM32(entry[3]) == limit_match) { 4213 record = &bios->data[ROM16(entry[1])]; 4214 break; 4215 } 4216 } 4217 4218 if (!record) { 4219 NV_ERROR(dev, "Register 0x%08x not found in PLL " 4220 "limits table", limit_match); 4221 return -ENOENT; 4222 } 4223 4224 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000; 4225 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000; 4226 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000; 4227 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000; 4228 pll_lim->vco1.min_m = record[8]; 4229 pll_lim->vco1.max_m = record[9]; 4230 pll_lim->vco1.min_n = record[10]; 4231 pll_lim->vco1.max_n = record[11]; 4232 pll_lim->min_p = record[12]; 4233 pll_lim->max_p = record[13]; 4234 /* where did this go to?? */ 4235 if (limit_match == 0x00614100 || limit_match == 0x00614900) 4236 pll_lim->refclk = 27000; 4237 else 4238 pll_lim->refclk = 100000; 4239 } 4240 4241 /* 4242 * By now any valid limit table ought to have set a max frequency for 4243 * vco1, so if it's zero it's either a pre limit table bios, or one 4244 * with an empty limit table (seen on nv18) 4245 */ 4246 if (!pll_lim->vco1.maxfreq) { 4247 pll_lim->vco1.minfreq = bios->fminvco; 4248 pll_lim->vco1.maxfreq = bios->fmaxvco; 4249 pll_lim->vco1.min_inputfreq = 0; 4250 pll_lim->vco1.max_inputfreq = INT_MAX; 4251 pll_lim->vco1.min_n = 0x1; 4252 pll_lim->vco1.max_n = 0xff; 4253 pll_lim->vco1.min_m = 0x1; 4254 if (crystal_straps == 0) { 4255 /* nv05 does this, nv11 doesn't, nv10 unknown */ 4256 if (cv < 0x11) 4257 pll_lim->vco1.min_m = 0x7; 4258 pll_lim->vco1.max_m = 0xd; 4259 } else { 4260 if (cv < 0x11) 4261 pll_lim->vco1.min_m = 0x8; 4262 pll_lim->vco1.max_m = 0xe; 4263 } 4264 if (cv < 0x17 || cv == 0x1a || cv == 0x20) 4265 pll_lim->max_log2p = 4; 4266 else 4267 pll_lim->max_log2p = 5; 4268 pll_lim->max_usable_log2p = pll_lim->max_log2p; 4269 } 4270 4271 if (!pll_lim->refclk) 4272 switch (crystal_straps) { 4273 case 0: 4274 pll_lim->refclk = 13500; 4275 break; 4276 case (1 << 6): 4277 pll_lim->refclk = 14318; 4278 break; 4279 case (1 << 22): 4280 pll_lim->refclk = 27000; 4281 break; 4282 case (1 << 22 | 1 << 6): 4283 pll_lim->refclk = 25000; 4284 break; 4285 } 4286 4287#if 0 /* for easy debugging */ 4288 ErrorF("pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq); 4289 ErrorF("pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq); 4290 ErrorF("pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq); 4291 ErrorF("pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq); 4292 4293 ErrorF("pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq); 4294 ErrorF("pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq); 4295 ErrorF("pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq); 4296 ErrorF("pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq); 4297 4298 ErrorF("pll.vco1.min_n: %d\n", pll_lim->vco1.min_n); 4299 ErrorF("pll.vco1.max_n: %d\n", pll_lim->vco1.max_n); 4300 ErrorF("pll.vco1.min_m: %d\n", pll_lim->vco1.min_m); 4301 ErrorF("pll.vco1.max_m: %d\n", pll_lim->vco1.max_m); 4302 ErrorF("pll.vco2.min_n: %d\n", pll_lim->vco2.min_n); 4303 ErrorF("pll.vco2.max_n: %d\n", pll_lim->vco2.max_n); 4304 ErrorF("pll.vco2.min_m: %d\n", pll_lim->vco2.min_m); 4305 ErrorF("pll.vco2.max_m: %d\n", pll_lim->vco2.max_m); 4306 4307 ErrorF("pll.max_log2p: %d\n", pll_lim->max_log2p); 4308 ErrorF("pll.log2p_bias: %d\n", pll_lim->log2p_bias); 4309 4310 ErrorF("pll.refclk: %d\n", pll_lim->refclk); 4311#endif 4312 4313 return 0; 4314} 4315 4316static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset) 4317{ 4318 /* 4319 * offset + 0 (8 bits): Micro version 4320 * offset + 1 (8 bits): Minor version 4321 * offset + 2 (8 bits): Chip version 4322 * offset + 3 (8 bits): Major version 4323 */ 4324 4325 bios->major_version = bios->data[offset + 3]; 4326 bios->chip_version = bios->data[offset + 2]; 4327 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n", 4328 bios->data[offset + 3], bios->data[offset + 2], 4329 bios->data[offset + 1], bios->data[offset]); 4330} 4331 4332static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset) 4333{ 4334 /* 4335 * Parses the init table segment for pointers used in script execution. 4336 * 4337 * offset + 0 (16 bits): init script tables pointer 4338 * offset + 2 (16 bits): macro index table pointer 4339 * offset + 4 (16 bits): macro table pointer 4340 * offset + 6 (16 bits): condition table pointer 4341 * offset + 8 (16 bits): io condition table pointer 4342 * offset + 10 (16 bits): io flag condition table pointer 4343 * offset + 12 (16 bits): init function table pointer 4344 */ 4345 4346 bios->init_script_tbls_ptr = ROM16(bios->data[offset]); 4347 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]); 4348 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]); 4349 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]); 4350 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]); 4351 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]); 4352 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]); 4353} 4354 4355static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4356{ 4357 /* 4358 * Parses the load detect values for g80 cards. 4359 * 4360 * offset + 0 (16 bits): loadval table pointer 4361 */ 4362 4363 uint16_t load_table_ptr; 4364 uint8_t version, headerlen, entrylen, num_entries; 4365 4366 if (bitentry->length != 3) { 4367 NV_ERROR(dev, "Do not understand BIT A table\n"); 4368 return -EINVAL; 4369 } 4370 4371 load_table_ptr = ROM16(bios->data[bitentry->offset]); 4372 4373 if (load_table_ptr == 0x0) { 4374 NV_ERROR(dev, "Pointer to BIT loadval table invalid\n"); 4375 return -EINVAL; 4376 } 4377 4378 version = bios->data[load_table_ptr]; 4379 4380 if (version != 0x10) { 4381 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n", 4382 version >> 4, version & 0xF); 4383 return -ENOSYS; 4384 } 4385 4386 headerlen = bios->data[load_table_ptr + 1]; 4387 entrylen = bios->data[load_table_ptr + 2]; 4388 num_entries = bios->data[load_table_ptr + 3]; 4389 4390 if (headerlen != 4 || entrylen != 4 || num_entries != 2) { 4391 NV_ERROR(dev, "Do not understand BIT loadval table\n"); 4392 return -EINVAL; 4393 } 4394 4395 /* First entry is normal dac, 2nd tv-out perhaps? */ 4396 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff; 4397 4398 return 0; 4399} 4400 4401static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4402{ 4403 /* 4404 * offset + 8 (16 bits): PLL limits table pointer 4405 * 4406 * There's more in here, but that's unknown. 4407 */ 4408 4409 if (bitentry->length < 10) { 4410 NV_ERROR(dev, "Do not understand BIT C table\n"); 4411 return -EINVAL; 4412 } 4413 4414 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]); 4415 4416 return 0; 4417} 4418 4419static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4420{ 4421 /* 4422 * Parses the flat panel table segment that the bit entry points to. 4423 * Starting at bitentry->offset: 4424 * 4425 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte 4426 * records beginning with a freq. 4427 * offset + 2 (16 bits): mode table pointer 4428 */ 4429 4430 if (bitentry->length != 4) { 4431 NV_ERROR(dev, "Do not understand BIT display table\n"); 4432 return -EINVAL; 4433 } 4434 4435 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]); 4436 4437 return 0; 4438} 4439 4440static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4441{ 4442 /* 4443 * Parses the init table segment that the bit entry points to. 4444 * 4445 * See parse_script_table_pointers for layout 4446 */ 4447 4448 if (bitentry->length < 14) { 4449 NV_ERROR(dev, "Do not understand init table\n"); 4450 return -EINVAL; 4451 } 4452 4453 parse_script_table_pointers(bios, bitentry->offset); 4454 4455 if (bitentry->length >= 16) 4456 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]); 4457 if (bitentry->length >= 18) 4458 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]); 4459 4460 return 0; 4461} 4462 4463static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4464{ 4465 /* 4466 * BIT 'i' (info?) table 4467 * 4468 * offset + 0 (32 bits): BIOS version dword (as in B table) 4469 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?) 4470 * offset + 13 (16 bits): pointer to table containing DAC load 4471 * detection comparison values 4472 * 4473 * There's other things in the table, purpose unknown 4474 */ 4475 4476 uint16_t daccmpoffset; 4477 uint8_t dacver, dacheaderlen; 4478 4479 if (bitentry->length < 6) { 4480 NV_ERROR(dev, "BIT i table too short for needed information\n"); 4481 return -EINVAL; 4482 } 4483 4484 parse_bios_version(dev, bios, bitentry->offset); 4485 4486 /* 4487 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's 4488 * Quadro identity crisis), other bits possibly as for BMP feature byte 4489 */ 4490 bios->feature_byte = bios->data[bitentry->offset + 5]; 4491 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE; 4492 4493 if (bitentry->length < 15) { 4494 NV_WARN(dev, "BIT i table not long enough for DAC load " 4495 "detection comparison table\n"); 4496 return -EINVAL; 4497 } 4498 4499 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]); 4500 4501 /* doesn't exist on g80 */ 4502 if (!daccmpoffset) 4503 return 0; 4504 4505 /* 4506 * The first value in the table, following the header, is the 4507 * comparison value, the second entry is a comparison value for 4508 * TV load detection. 4509 */ 4510 4511 dacver = bios->data[daccmpoffset]; 4512 dacheaderlen = bios->data[daccmpoffset + 1]; 4513 4514 if (dacver != 0x00 && dacver != 0x10) { 4515 NV_WARN(dev, "DAC load detection comparison table version " 4516 "%d.%d not known\n", dacver >> 4, dacver & 0xf); 4517 return -ENOSYS; 4518 } 4519 4520 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]); 4521 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]); 4522 4523 return 0; 4524} 4525 4526static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4527{ 4528 /* 4529 * Parses the LVDS table segment that the bit entry points to. 4530 * Starting at bitentry->offset: 4531 * 4532 * offset + 0 (16 bits): LVDS strap xlate table pointer 4533 */ 4534 4535 if (bitentry->length != 2) { 4536 NV_ERROR(dev, "Do not understand BIT LVDS table\n"); 4537 return -EINVAL; 4538 } 4539 4540 /* 4541 * No idea if it's still called the LVDS manufacturer table, but 4542 * the concept's close enough. 4543 */ 4544 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]); 4545 4546 return 0; 4547} 4548 4549static int 4550parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios, 4551 struct bit_entry *bitentry) 4552{ 4553 /* 4554 * offset + 2 (8 bits): number of options in an 4555 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set 4556 * offset + 3 (16 bits): pointer to strap xlate table for RAM 4557 * restrict option selection 4558 * 4559 * There's a bunch of bits in this table other than the RAM restrict 4560 * stuff that we don't use - their use currently unknown 4561 */ 4562 4563 /* 4564 * Older bios versions don't have a sufficiently long table for 4565 * what we want 4566 */ 4567 if (bitentry->length < 0x5) 4568 return 0; 4569 4570 if (bitentry->id[1] < 2) { 4571 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2]; 4572 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]); 4573 } else { 4574 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0]; 4575 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]); 4576 } 4577 4578 return 0; 4579} 4580 4581static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4582{ 4583 /* 4584 * Parses the pointer to the TMDS table 4585 * 4586 * Starting at bitentry->offset: 4587 * 4588 * offset + 0 (16 bits): TMDS table pointer 4589 * 4590 * The TMDS table is typically found just before the DCB table, with a 4591 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being 4592 * length?) 4593 * 4594 * At offset +7 is a pointer to a script, which I don't know how to 4595 * run yet. 4596 * At offset +9 is a pointer to another script, likewise 4597 * Offset +11 has a pointer to a table where the first word is a pxclk 4598 * frequency and the second word a pointer to a script, which should be 4599 * run if the comparison pxclk frequency is less than the pxclk desired. 4600 * This repeats for decreasing comparison frequencies 4601 * Offset +13 has a pointer to a similar table 4602 * The selection of table (and possibly +7/+9 script) is dictated by 4603 * "or" from the DCB. 4604 */ 4605 4606 uint16_t tmdstableptr, script1, script2; 4607 4608 if (bitentry->length != 2) { 4609 NV_ERROR(dev, "Do not understand BIT TMDS table\n"); 4610 return -EINVAL; 4611 } 4612 4613 tmdstableptr = ROM16(bios->data[bitentry->offset]); 4614 4615 if (tmdstableptr == 0x0) { 4616 NV_ERROR(dev, "Pointer to TMDS table invalid\n"); 4617 return -EINVAL; 4618 } 4619 4620 /* nv50+ has v2.0, but we don't parse it atm */ 4621 if (bios->data[tmdstableptr] != 0x11) { 4622 NV_WARN(dev, 4623 "TMDS table revision %d.%d not currently supported\n", 4624 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf); 4625 return -ENOSYS; 4626 } 4627 4628 /* 4629 * These two scripts are odd: they don't seem to get run even when 4630 * they are not stubbed. 4631 */ 4632 script1 = ROM16(bios->data[tmdstableptr + 7]); 4633 script2 = ROM16(bios->data[tmdstableptr + 9]); 4634 if (bios->data[script1] != 'q' || bios->data[script2] != 'q') 4635 NV_WARN(dev, "TMDS table script pointers not stubbed\n"); 4636 4637 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]); 4638 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]); 4639 4640 return 0; 4641} 4642 4643static int 4644parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios, 4645 struct bit_entry *bitentry) 4646{ 4647 /* 4648 * Parses the pointer to the G80 output script tables 4649 * 4650 * Starting at bitentry->offset: 4651 * 4652 * offset + 0 (16 bits): output script table pointer 4653 */ 4654 4655 uint16_t outputscripttableptr; 4656 4657 if (bitentry->length != 3) { 4658 NV_ERROR(dev, "Do not understand BIT U table\n"); 4659 return -EINVAL; 4660 } 4661 4662 outputscripttableptr = ROM16(bios->data[bitentry->offset]); 4663 bios->display.script_table_ptr = outputscripttableptr; 4664 return 0; 4665} 4666 4667static int 4668parse_bit_displayport_tbl_entry(struct drm_device *dev, struct nvbios *bios, 4669 struct bit_entry *bitentry) 4670{ 4671 bios->display.dp_table_ptr = ROM16(bios->data[bitentry->offset]); 4672 return 0; 4673} 4674 4675struct bit_table { 4676 const char id; 4677 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *); 4678}; 4679 4680#define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry }) 4681 4682static int 4683parse_bit_table(struct nvbios *bios, const uint16_t bitoffset, 4684 struct bit_table *table) 4685{ 4686 struct drm_device *dev = bios->dev; 4687 uint8_t maxentries = bios->data[bitoffset + 4]; 4688 int i, offset; 4689 struct bit_entry bitentry; 4690 4691 for (i = 0, offset = bitoffset + 6; i < maxentries; i++, offset += 6) { 4692 bitentry.id[0] = bios->data[offset]; 4693 4694 if (bitentry.id[0] != table->id) 4695 continue; 4696 4697 bitentry.id[1] = bios->data[offset + 1]; 4698 bitentry.length = ROM16(bios->data[offset + 2]); 4699 bitentry.offset = ROM16(bios->data[offset + 4]); 4700 4701 return table->parse_fn(dev, bios, &bitentry); 4702 } 4703 4704 NV_INFO(dev, "BIT table '%c' not found\n", table->id); 4705 return -ENOSYS; 4706} 4707 4708static int 4709parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset) 4710{ 4711 int ret; 4712 4713 /* 4714 * The only restriction on parsing order currently is having 'i' first 4715 * for use of bios->*_version or bios->feature_byte while parsing; 4716 * functions shouldn't be actually *doing* anything apart from pulling 4717 * data from the image into the bios struct, thus no interdependencies 4718 */ 4719 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i)); 4720 if (ret) /* info? */ 4721 return ret; 4722 if (bios->major_version >= 0x60) /* g80+ */ 4723 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A)); 4724 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C)); 4725 if (ret) 4726 return ret; 4727 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display)); 4728 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init)); 4729 if (ret) 4730 return ret; 4731 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */ 4732 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds)); 4733 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds)); 4734 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U)); 4735 parse_bit_table(bios, bitoffset, &BIT_TABLE('d', displayport)); 4736 4737 return 0; 4738} 4739 4740static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset) 4741{ 4742 /* 4743 * Parses the BMP structure for useful things, but does not act on them 4744 * 4745 * offset + 5: BMP major version 4746 * offset + 6: BMP minor version 4747 * offset + 9: BMP feature byte 4748 * offset + 10: BCD encoded BIOS version 4749 * 4750 * offset + 18: init script table pointer (for bios versions < 5.10h) 4751 * offset + 20: extra init script table pointer (for bios 4752 * versions < 5.10h) 4753 * 4754 * offset + 24: memory init table pointer (used on early bios versions) 4755 * offset + 26: SDR memory sequencing setup data table 4756 * offset + 28: DDR memory sequencing setup data table 4757 * 4758 * offset + 54: index of I2C CRTC pair to use for CRT output 4759 * offset + 55: index of I2C CRTC pair to use for TV output 4760 * offset + 56: index of I2C CRTC pair to use for flat panel output 4761 * offset + 58: write CRTC index for I2C pair 0 4762 * offset + 59: read CRTC index for I2C pair 0 4763 * offset + 60: write CRTC index for I2C pair 1 4764 * offset + 61: read CRTC index for I2C pair 1 4765 * 4766 * offset + 67: maximum internal PLL frequency (single stage PLL) 4767 * offset + 71: minimum internal PLL frequency (single stage PLL) 4768 * 4769 * offset + 75: script table pointers, as described in 4770 * parse_script_table_pointers 4771 * 4772 * offset + 89: TMDS single link output A table pointer 4773 * offset + 91: TMDS single link output B table pointer 4774 * offset + 95: LVDS single link output A table pointer 4775 * offset + 105: flat panel timings table pointer 4776 * offset + 107: flat panel strapping translation table pointer 4777 * offset + 117: LVDS manufacturer panel config table pointer 4778 * offset + 119: LVDS manufacturer strapping translation table pointer 4779 * 4780 * offset + 142: PLL limits table pointer 4781 * 4782 * offset + 156: minimum pixel clock for LVDS dual link 4783 */ 4784 4785 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor; 4786 uint16_t bmplength; 4787 uint16_t legacy_scripts_offset, legacy_i2c_offset; 4788 4789 /* load needed defaults in case we can't parse this info */ 4790 bios->dcb.i2c[0].write = NV_CIO_CRE_DDC_WR__INDEX; 4791 bios->dcb.i2c[0].read = NV_CIO_CRE_DDC_STATUS__INDEX; 4792 bios->dcb.i2c[1].write = NV_CIO_CRE_DDC0_WR__INDEX; 4793 bios->dcb.i2c[1].read = NV_CIO_CRE_DDC0_STATUS__INDEX; 4794 bios->digital_min_front_porch = 0x4b; 4795 bios->fmaxvco = 256000; 4796 bios->fminvco = 128000; 4797 bios->fp.duallink_transition_clk = 90000; 4798 4799 bmp_version_major = bmp[5]; 4800 bmp_version_minor = bmp[6]; 4801 4802 NV_TRACE(dev, "BMP version %d.%d\n", 4803 bmp_version_major, bmp_version_minor); 4804 4805 /* 4806 * Make sure that 0x36 is blank and can't be mistaken for a DCB 4807 * pointer on early versions 4808 */ 4809 if (bmp_version_major < 5) 4810 *(uint16_t *)&bios->data[0x36] = 0; 4811 4812 /* 4813 * Seems that the minor version was 1 for all major versions prior 4814 * to 5. Version 6 could theoretically exist, but I suspect BIT 4815 * happened instead. 4816 */ 4817 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) { 4818 NV_ERROR(dev, "You have an unsupported BMP version. " 4819 "Please send in your bios\n"); 4820 return -ENOSYS; 4821 } 4822 4823 if (bmp_version_major == 0) 4824 /* nothing that's currently useful in this version */ 4825 return 0; 4826 else if (bmp_version_major == 1) 4827 bmplength = 44; /* exact for 1.01 */ 4828 else if (bmp_version_major == 2) 4829 bmplength = 48; /* exact for 2.01 */ 4830 else if (bmp_version_major == 3) 4831 bmplength = 54; 4832 /* guessed - mem init tables added in this version */ 4833 else if (bmp_version_major == 4 || bmp_version_minor < 0x1) 4834 /* don't know if 5.0 exists... */ 4835 bmplength = 62; 4836 /* guessed - BMP I2C indices added in version 4*/ 4837 else if (bmp_version_minor < 0x6) 4838 bmplength = 67; /* exact for 5.01 */ 4839 else if (bmp_version_minor < 0x10) 4840 bmplength = 75; /* exact for 5.06 */ 4841 else if (bmp_version_minor == 0x10) 4842 bmplength = 89; /* exact for 5.10h */ 4843 else if (bmp_version_minor < 0x14) 4844 bmplength = 118; /* exact for 5.11h */ 4845 else if (bmp_version_minor < 0x24) 4846 /* 4847 * Not sure of version where pll limits came in; 4848 * certainly exist by 0x24 though. 4849 */ 4850 /* length not exact: this is long enough to get lvds members */ 4851 bmplength = 123; 4852 else if (bmp_version_minor < 0x27) 4853 /* 4854 * Length not exact: this is long enough to get pll limit 4855 * member 4856 */ 4857 bmplength = 144; 4858 else 4859 /* 4860 * Length not exact: this is long enough to get dual link 4861 * transition clock. 4862 */ 4863 bmplength = 158; 4864 4865 /* checksum */ 4866 if (nv_cksum(bmp, 8)) { 4867 NV_ERROR(dev, "Bad BMP checksum\n"); 4868 return -EINVAL; 4869 } 4870 4871 /* 4872 * Bit 4 seems to indicate either a mobile bios or a quadro card -- 4873 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl 4874 * (not nv10gl), bit 5 that the flat panel tables are present, and 4875 * bit 6 a tv bios. 4876 */ 4877 bios->feature_byte = bmp[9]; 4878 4879 parse_bios_version(dev, bios, offset + 10); 4880 4881 if (bmp_version_major < 5 || bmp_version_minor < 0x10) 4882 bios->old_style_init = true; 4883 legacy_scripts_offset = 18; 4884 if (bmp_version_major < 2) 4885 legacy_scripts_offset -= 4; 4886 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]); 4887 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]); 4888 4889 if (bmp_version_major > 2) { /* appears in BMP 3 */ 4890 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]); 4891 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]); 4892 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]); 4893 } 4894 4895 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */ 4896 if (bmplength > 61) 4897 legacy_i2c_offset = offset + 54; 4898 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset]; 4899 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1]; 4900 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2]; 4901 bios->dcb.i2c[0].write = bios->data[legacy_i2c_offset + 4]; 4902 bios->dcb.i2c[0].read = bios->data[legacy_i2c_offset + 5]; 4903 bios->dcb.i2c[1].write = bios->data[legacy_i2c_offset + 6]; 4904 bios->dcb.i2c[1].read = bios->data[legacy_i2c_offset + 7]; 4905 4906 if (bmplength > 74) { 4907 bios->fmaxvco = ROM32(bmp[67]); 4908 bios->fminvco = ROM32(bmp[71]); 4909 } 4910 if (bmplength > 88) 4911 parse_script_table_pointers(bios, offset + 75); 4912 if (bmplength > 94) { 4913 bios->tmds.output0_script_ptr = ROM16(bmp[89]); 4914 bios->tmds.output1_script_ptr = ROM16(bmp[91]); 4915 /* 4916 * Never observed in use with lvds scripts, but is reused for 4917 * 18/24 bit panel interface default for EDID equipped panels 4918 * (if_is_24bit not set directly to avoid any oscillation). 4919 */ 4920 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]); 4921 } 4922 if (bmplength > 108) { 4923 bios->fp.fptablepointer = ROM16(bmp[105]); 4924 bios->fp.fpxlatetableptr = ROM16(bmp[107]); 4925 bios->fp.xlatwidth = 1; 4926 } 4927 if (bmplength > 120) { 4928 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]); 4929 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]); 4930 } 4931 if (bmplength > 143) 4932 bios->pll_limit_tbl_ptr = ROM16(bmp[142]); 4933 4934 if (bmplength > 157) 4935 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10; 4936 4937 return 0; 4938} 4939 4940static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len) 4941{ 4942 int i, j; 4943 4944 for (i = 0; i <= (n - len); i++) { 4945 for (j = 0; j < len; j++) 4946 if (data[i + j] != str[j]) 4947 break; 4948 if (j == len) 4949 return i; 4950 } 4951 4952 return 0; 4953} 4954 4955static int 4956read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, int index, struct dcb_i2c_entry *i2c) 4957{ 4958 uint8_t dcb_i2c_ver = dcb_version, headerlen = 0, entry_len = 4; 4959 int i2c_entries = DCB_MAX_NUM_I2C_ENTRIES; 4960 int recordoffset = 0, rdofs = 1, wrofs = 0; 4961 uint8_t port_type = 0; 4962 4963 if (!i2ctable) 4964 return -EINVAL; 4965 4966 if (dcb_version >= 0x30) { 4967 if (i2ctable[0] != dcb_version) /* necessary? */ 4968 NV_WARN(dev, 4969 "DCB I2C table version mismatch (%02X vs %02X)\n", 4970 i2ctable[0], dcb_version); 4971 dcb_i2c_ver = i2ctable[0]; 4972 headerlen = i2ctable[1]; 4973 if (i2ctable[2] <= DCB_MAX_NUM_I2C_ENTRIES) 4974 i2c_entries = i2ctable[2]; 4975 else 4976 NV_WARN(dev, 4977 "DCB I2C table has more entries than indexable " 4978 "(%d entries, max %d)\n", i2ctable[2], 4979 DCB_MAX_NUM_I2C_ENTRIES); 4980 entry_len = i2ctable[3]; 4981 /* [4] is i2c_default_indices, read in parse_dcb_table() */ 4982 } 4983 /* 4984 * It's your own fault if you call this function on a DCB 1.1 BIOS -- 4985 * the test below is for DCB 1.2 4986 */ 4987 if (dcb_version < 0x14) { 4988 recordoffset = 2; 4989 rdofs = 0; 4990 wrofs = 1; 4991 } 4992 4993 if (index == 0xf) 4994 return 0; 4995 if (index >= i2c_entries) { 4996 NV_ERROR(dev, "DCB I2C index too big (%d >= %d)\n", 4997 index, i2ctable[2]); 4998 return -ENOENT; 4999 } 5000 if (i2ctable[headerlen + entry_len * index + 3] == 0xff) { 5001 NV_ERROR(dev, "DCB I2C entry invalid\n"); 5002 return -EINVAL; 5003 } 5004 5005 if (dcb_i2c_ver >= 0x30) { 5006 port_type = i2ctable[headerlen + recordoffset + 3 + entry_len * index]; 5007 5008 /* 5009 * Fixup for chips using same address offset for read and 5010 * write. 5011 */ 5012 if (port_type == 4) /* seen on C51 */ 5013 rdofs = wrofs = 1; 5014 if (port_type >= 5) /* G80+ */ 5015 rdofs = wrofs = 0; 5016 } 5017 5018 if (dcb_i2c_ver >= 0x40 && port_type != 5 && port_type != 6) 5019 NV_WARN(dev, "DCB I2C table has port type %d\n", port_type); 5020 5021 i2c->port_type = port_type; 5022 i2c->read = i2ctable[headerlen + recordoffset + rdofs + entry_len * index]; 5023 i2c->write = i2ctable[headerlen + recordoffset + wrofs + entry_len * index]; 5024 5025 return 0; 5026} 5027 5028static struct dcb_gpio_entry * 5029new_gpio_entry(struct nvbios *bios) 5030{ 5031 struct dcb_gpio_table *gpio = &bios->dcb.gpio; 5032 5033 return &gpio->entry[gpio->entries++]; 5034} 5035 5036struct dcb_gpio_entry * 5037nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag) 5038{ 5039 struct drm_nouveau_private *dev_priv = dev->dev_private; 5040 struct nvbios *bios = &dev_priv->vbios; 5041 int i; 5042 5043 for (i = 0; i < bios->dcb.gpio.entries; i++) { 5044 if (bios->dcb.gpio.entry[i].tag != tag) 5045 continue; 5046 5047 return &bios->dcb.gpio.entry[i]; 5048 } 5049 5050 return NULL; 5051} 5052 5053static void 5054parse_dcb30_gpio_entry(struct nvbios *bios, uint16_t offset) 5055{ 5056 struct dcb_gpio_entry *gpio; 5057 uint16_t ent = ROM16(bios->data[offset]); 5058 uint8_t line = ent & 0x1f, 5059 tag = ent >> 5 & 0x3f, 5060 flags = ent >> 11 & 0x1f; 5061 5062 if (tag == 0x3f) 5063 return; 5064 5065 gpio = new_gpio_entry(bios); 5066 5067 gpio->tag = tag; 5068 gpio->line = line; 5069 gpio->invert = flags != 4; 5070} 5071 5072static void 5073parse_dcb40_gpio_entry(struct nvbios *bios, uint16_t offset) 5074{ 5075 struct dcb_gpio_entry *gpio; 5076 uint32_t ent = ROM32(bios->data[offset]); 5077 uint8_t line = ent & 0x1f, 5078 tag = ent >> 8 & 0xff; 5079 5080 if (tag == 0xff) 5081 return; 5082 5083 gpio = new_gpio_entry(bios); 5084 5085 /* Currently unused, we may need more fields parsed at some 5086 * point. */ 5087 gpio->tag = tag; 5088 gpio->line = line; 5089} 5090 5091static void 5092parse_dcb_gpio_table(struct nvbios *bios) 5093{ 5094 struct drm_device *dev = bios->dev; 5095 uint16_t gpio_table_ptr = bios->dcb.gpio_table_ptr; 5096 uint8_t *gpio_table = &bios->data[gpio_table_ptr]; 5097 int header_len = gpio_table[1], 5098 entries = gpio_table[2], 5099 entry_len = gpio_table[3]; 5100 void (*parse_entry)(struct nvbios *, uint16_t) = NULL; 5101 int i; 5102 5103 if (bios->dcb.version >= 0x40) { 5104 if (gpio_table_ptr && entry_len != 4) { 5105 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n"); 5106 return; 5107 } 5108 5109 parse_entry = parse_dcb40_gpio_entry; 5110 5111 } else if (bios->dcb.version >= 0x30) { 5112 if (gpio_table_ptr && entry_len != 2) { 5113 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n"); 5114 return; 5115 } 5116 5117 parse_entry = parse_dcb30_gpio_entry; 5118 5119 } else if (bios->dcb.version >= 0x22) { 5120 /* 5121 * DCBs older than v3.0 don't really have a GPIO 5122 * table, instead they keep some GPIO info at fixed 5123 * locations. 5124 */ 5125 uint16_t dcbptr = ROM16(bios->data[0x36]); 5126 uint8_t *tvdac_gpio = &bios->data[dcbptr - 5]; 5127 5128 if (tvdac_gpio[0] & 1) { 5129 struct dcb_gpio_entry *gpio = new_gpio_entry(bios); 5130 5131 gpio->tag = DCB_GPIO_TVDAC0; 5132 gpio->line = tvdac_gpio[1] >> 4; 5133 gpio->invert = tvdac_gpio[0] & 2; 5134 } 5135 } 5136 5137 if (!gpio_table_ptr) 5138 return; 5139 5140 if (entries > DCB_MAX_NUM_GPIO_ENTRIES) { 5141 NV_WARN(dev, "Too many entries in the DCB GPIO table.\n"); 5142 entries = DCB_MAX_NUM_GPIO_ENTRIES; 5143 } 5144 5145 for (i = 0; i < entries; i++) 5146 parse_entry(bios, gpio_table_ptr + header_len + entry_len * i); 5147} 5148 5149struct dcb_connector_table_entry * 5150nouveau_bios_connector_entry(struct drm_device *dev, int index) 5151{ 5152 struct drm_nouveau_private *dev_priv = dev->dev_private; 5153 struct nvbios *bios = &dev_priv->vbios; 5154 struct dcb_connector_table_entry *cte; 5155 5156 if (index >= bios->dcb.connector.entries) 5157 return NULL; 5158 5159 cte = &bios->dcb.connector.entry[index]; 5160 if (cte->type == 0xff) 5161 return NULL; 5162 5163 return cte; 5164} 5165 5166static enum dcb_connector_type 5167divine_connector_type(struct nvbios *bios, int index) 5168{ 5169 struct dcb_table *dcb = &bios->dcb; 5170 unsigned encoders = 0, type = DCB_CONNECTOR_NONE; 5171 int i; 5172 5173 for (i = 0; i < dcb->entries; i++) { 5174 if (dcb->entry[i].connector == index) 5175 encoders |= (1 << dcb->entry[i].type); 5176 } 5177 5178 if (encoders & (1 << OUTPUT_DP)) { 5179 if (encoders & (1 << OUTPUT_TMDS)) 5180 type = DCB_CONNECTOR_DP; 5181 else 5182 type = DCB_CONNECTOR_eDP; 5183 } else 5184 if (encoders & (1 << OUTPUT_TMDS)) { 5185 if (encoders & (1 << OUTPUT_ANALOG)) 5186 type = DCB_CONNECTOR_DVI_I; 5187 else 5188 type = DCB_CONNECTOR_DVI_D; 5189 } else 5190 if (encoders & (1 << OUTPUT_ANALOG)) { 5191 type = DCB_CONNECTOR_VGA; 5192 } else 5193 if (encoders & (1 << OUTPUT_LVDS)) { 5194 type = DCB_CONNECTOR_LVDS; 5195 } else 5196 if (encoders & (1 << OUTPUT_TV)) { 5197 type = DCB_CONNECTOR_TV_0; 5198 } 5199 5200 return type; 5201} 5202 5203static void 5204apply_dcb_connector_quirks(struct nvbios *bios, int idx) 5205{ 5206 struct dcb_connector_table_entry *cte = &bios->dcb.connector.entry[idx]; 5207 struct drm_device *dev = bios->dev; 5208 5209 /* Gigabyte NX85T */ 5210 if ((dev->pdev->device == 0x0421) && 5211 (dev->pdev->subsystem_vendor == 0x1458) && 5212 (dev->pdev->subsystem_device == 0x344c)) { 5213 if (cte->type == DCB_CONNECTOR_HDMI_1) 5214 cte->type = DCB_CONNECTOR_DVI_I; 5215 } 5216} 5217 5218static void 5219parse_dcb_connector_table(struct nvbios *bios) 5220{ 5221 struct drm_device *dev = bios->dev; 5222 struct dcb_connector_table *ct = &bios->dcb.connector; 5223 struct dcb_connector_table_entry *cte; 5224 uint8_t *conntab = &bios->data[bios->dcb.connector_table_ptr]; 5225 uint8_t *entry; 5226 int i; 5227 5228 if (!bios->dcb.connector_table_ptr) { 5229 NV_DEBUG_KMS(dev, "No DCB connector table present\n"); 5230 return; 5231 } 5232 5233 NV_INFO(dev, "DCB connector table: VHER 0x%02x %d %d %d\n", 5234 conntab[0], conntab[1], conntab[2], conntab[3]); 5235 if ((conntab[0] != 0x30 && conntab[0] != 0x40) || 5236 (conntab[3] != 2 && conntab[3] != 4)) { 5237 NV_ERROR(dev, " Unknown! Please report.\n"); 5238 return; 5239 } 5240 5241 ct->entries = conntab[2]; 5242 5243 entry = conntab + conntab[1]; 5244 cte = &ct->entry[0]; 5245 for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) { 5246 cte->index = i; 5247 if (conntab[3] == 2) 5248 cte->entry = ROM16(entry[0]); 5249 else 5250 cte->entry = ROM32(entry[0]); 5251 5252 cte->type = (cte->entry & 0x000000ff) >> 0; 5253 cte->index2 = (cte->entry & 0x00000f00) >> 8; 5254 switch (cte->entry & 0x00033000) { 5255 case 0x00001000: 5256 cte->gpio_tag = 0x07; 5257 break; 5258 case 0x00002000: 5259 cte->gpio_tag = 0x08; 5260 break; 5261 case 0x00010000: 5262 cte->gpio_tag = 0x51; 5263 break; 5264 case 0x00020000: 5265 cte->gpio_tag = 0x52; 5266 break; 5267 default: 5268 cte->gpio_tag = 0xff; 5269 break; 5270 } 5271 5272 if (cte->type == 0xff) 5273 continue; 5274 5275 apply_dcb_connector_quirks(bios, i); 5276 5277 NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n", 5278 i, cte->entry, cte->type, cte->index, cte->gpio_tag); 5279 5280 /* check for known types, fallback to guessing the type 5281 * from attached encoders if we hit an unknown. 5282 */ 5283 switch (cte->type) { 5284 case DCB_CONNECTOR_VGA: 5285 case DCB_CONNECTOR_TV_0: 5286 case DCB_CONNECTOR_TV_1: 5287 case DCB_CONNECTOR_TV_3: 5288 case DCB_CONNECTOR_DVI_I: 5289 case DCB_CONNECTOR_DVI_D: 5290 case DCB_CONNECTOR_LVDS: 5291 case DCB_CONNECTOR_DP: 5292 case DCB_CONNECTOR_eDP: 5293 case DCB_CONNECTOR_HDMI_0: 5294 case DCB_CONNECTOR_HDMI_1: 5295 break; 5296 default: 5297 cte->type = divine_connector_type(bios, cte->index); 5298 NV_WARN(dev, "unknown type, using 0x%02x\n", cte->type); 5299 break; 5300 } 5301 5302 if (nouveau_override_conntype) { 5303 int type = divine_connector_type(bios, cte->index); 5304 if (type != cte->type) 5305 NV_WARN(dev, " -> type 0x%02x\n", cte->type); 5306 } 5307 5308 } 5309} 5310 5311static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb) 5312{ 5313 struct dcb_entry *entry = &dcb->entry[dcb->entries]; 5314 5315 memset(entry, 0, sizeof(struct dcb_entry)); 5316 entry->index = dcb->entries++; 5317 5318 return entry; 5319} 5320 5321static void fabricate_vga_output(struct dcb_table *dcb, int i2c, int heads) 5322{ 5323 struct dcb_entry *entry = new_dcb_entry(dcb); 5324 5325 entry->type = 0; 5326 entry->i2c_index = i2c; 5327 entry->heads = heads; 5328 entry->location = DCB_LOC_ON_CHIP; 5329 /* "or" mostly unused in early gen crt modesetting, 0 is fine */ 5330} 5331 5332static void fabricate_dvi_i_output(struct dcb_table *dcb, bool twoHeads) 5333{ 5334 struct dcb_entry *entry = new_dcb_entry(dcb); 5335 5336 entry->type = 2; 5337 entry->i2c_index = LEGACY_I2C_PANEL; 5338 entry->heads = twoHeads ? 3 : 1; 5339 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */ 5340 entry->or = 1; /* means |0x10 gets set on CRE_LCD__INDEX */ 5341 entry->duallink_possible = false; /* SiI164 and co. are single link */ 5342 5343#if 0 5344 /* 5345 * For dvi-a either crtc probably works, but my card appears to only 5346 * support dvi-d. "nvidia" still attempts to program it for dvi-a, 5347 * doing the full fp output setup (program 0x6808.. fp dimension regs, 5348 * setting 0x680848 to 0x10000111 to enable, maybe setting 0x680880); 5349 * the monitor picks up the mode res ok and lights up, but no pixel 5350 * data appears, so the board manufacturer probably connected up the 5351 * sync lines, but missed the video traces / components 5352 * 5353 * with this introduction, dvi-a left as an exercise for the reader. 5354 */ 5355 fabricate_vga_output(dcb, LEGACY_I2C_PANEL, entry->heads); 5356#endif 5357} 5358 5359static void fabricate_tv_output(struct dcb_table *dcb, bool twoHeads) 5360{ 5361 struct dcb_entry *entry = new_dcb_entry(dcb); 5362 5363 entry->type = 1; 5364 entry->i2c_index = LEGACY_I2C_TV; 5365 entry->heads = twoHeads ? 3 : 1; 5366 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */ 5367} 5368 5369static bool 5370parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb, 5371 uint32_t conn, uint32_t conf, struct dcb_entry *entry) 5372{ 5373 entry->type = conn & 0xf; 5374 entry->i2c_index = (conn >> 4) & 0xf; 5375 entry->heads = (conn >> 8) & 0xf; 5376 if (dcb->version >= 0x40) 5377 entry->connector = (conn >> 12) & 0xf; 5378 entry->bus = (conn >> 16) & 0xf; 5379 entry->location = (conn >> 20) & 0x3; 5380 entry->or = (conn >> 24) & 0xf; 5381 /* 5382 * Normal entries consist of a single bit, but dual link has the 5383 * next most significant bit set too 5384 */ 5385 entry->duallink_possible = 5386 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or); 5387 5388 switch (entry->type) { 5389 case OUTPUT_ANALOG: 5390 /* 5391 * Although the rest of a CRT conf dword is usually 5392 * zeros, mac biosen have stuff there so we must mask 5393 */ 5394 entry->crtconf.maxfreq = (dcb->version < 0x30) ? 5395 (conf & 0xffff) * 10 : 5396 (conf & 0xff) * 10000; 5397 break; 5398 case OUTPUT_LVDS: 5399 { 5400 uint32_t mask; 5401 if (conf & 0x1) 5402 entry->lvdsconf.use_straps_for_mode = true; 5403 if (dcb->version < 0x22) { 5404 mask = ~0xd; 5405 /* 5406 * The laptop in bug 14567 lies and claims to not use 5407 * straps when it does, so assume all DCB 2.0 laptops 5408 * use straps, until a broken EDID using one is produced 5409 */ 5410 entry->lvdsconf.use_straps_for_mode = true; 5411 /* 5412 * Both 0x4 and 0x8 show up in v2.0 tables; assume they 5413 * mean the same thing (probably wrong, but might work) 5414 */ 5415 if (conf & 0x4 || conf & 0x8) 5416 entry->lvdsconf.use_power_scripts = true; 5417 } else { 5418 mask = ~0x5; 5419 if (conf & 0x4) 5420 entry->lvdsconf.use_power_scripts = true; 5421 } 5422 if (conf & mask) { 5423 /* 5424 * Until we even try to use these on G8x, it's 5425 * useless reporting unknown bits. They all are. 5426 */ 5427 if (dcb->version >= 0x40) 5428 break; 5429 5430 NV_ERROR(dev, "Unknown LVDS configuration bits, " 5431 "please report\n"); 5432 } 5433 break; 5434 } 5435 case OUTPUT_TV: 5436 { 5437 if (dcb->version >= 0x30) 5438 entry->tvconf.has_component_output = conf & (0x8 << 4); 5439 else 5440 entry->tvconf.has_component_output = false; 5441 5442 break; 5443 } 5444 case OUTPUT_DP: 5445 entry->dpconf.sor.link = (conf & 0x00000030) >> 4; 5446 entry->dpconf.link_bw = (conf & 0x00e00000) >> 21; 5447 switch ((conf & 0x0f000000) >> 24) { 5448 case 0xf: 5449 entry->dpconf.link_nr = 4; 5450 break; 5451 case 0x3: 5452 entry->dpconf.link_nr = 2; 5453 break; 5454 default: 5455 entry->dpconf.link_nr = 1; 5456 break; 5457 } 5458 break; 5459 case OUTPUT_TMDS: 5460 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4; 5461 break; 5462 case 0xe: 5463 /* weird g80 mobile type that "nv" treats as a terminator */ 5464 dcb->entries--; 5465 return false; 5466 default: 5467 break; 5468 } 5469 5470 /* unsure what DCB version introduces this, 3.0? */ 5471 if (conf & 0x100000) 5472 entry->i2c_upper_default = true; 5473 5474 return true; 5475} 5476 5477static bool 5478parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb, 5479 uint32_t conn, uint32_t conf, struct dcb_entry *entry) 5480{ 5481 switch (conn & 0x0000000f) { 5482 case 0: 5483 entry->type = OUTPUT_ANALOG; 5484 break; 5485 case 1: 5486 entry->type = OUTPUT_TV; 5487 break; 5488 case 2: 5489 case 3: 5490 entry->type = OUTPUT_LVDS; 5491 break; 5492 case 4: 5493 switch ((conn & 0x000000f0) >> 4) { 5494 case 0: 5495 entry->type = OUTPUT_TMDS; 5496 break; 5497 case 1: 5498 entry->type = OUTPUT_LVDS; 5499 break; 5500 default: 5501 NV_ERROR(dev, "Unknown DCB subtype 4/%d\n", 5502 (conn & 0x000000f0) >> 4); 5503 return false; 5504 } 5505 break; 5506 default: 5507 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f); 5508 return false; 5509 } 5510 5511 entry->i2c_index = (conn & 0x0003c000) >> 14; 5512 entry->heads = ((conn & 0x001c0000) >> 18) + 1; 5513 entry->or = entry->heads; /* same as heads, hopefully safe enough */ 5514 entry->location = (conn & 0x01e00000) >> 21; 5515 entry->bus = (conn & 0x0e000000) >> 25; 5516 entry->duallink_possible = false; 5517 5518 switch (entry->type) { 5519 case OUTPUT_ANALOG: 5520 entry->crtconf.maxfreq = (conf & 0xffff) * 10; 5521 break; 5522 case OUTPUT_TV: 5523 entry->tvconf.has_component_output = false; 5524 break; 5525 case OUTPUT_TMDS: 5526 /* 5527 * Invent a DVI-A output, by copying the fields of the DVI-D 5528 * output; reported to work by math_b on an NV20(!). 5529 */ 5530 fabricate_vga_output(dcb, entry->i2c_index, entry->heads); 5531 break; 5532 case OUTPUT_LVDS: 5533 if ((conn & 0x00003f00) != 0x10) 5534 entry->lvdsconf.use_straps_for_mode = true; 5535 entry->lvdsconf.use_power_scripts = true; 5536 break; 5537 default: 5538 break; 5539 } 5540 5541 return true; 5542} 5543 5544static bool parse_dcb_entry(struct drm_device *dev, struct dcb_table *dcb, 5545 uint32_t conn, uint32_t conf) 5546{ 5547 struct dcb_entry *entry = new_dcb_entry(dcb); 5548 bool ret; 5549 5550 if (dcb->version >= 0x20) 5551 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry); 5552 else 5553 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry); 5554 if (!ret) 5555 return ret; 5556 5557 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table, 5558 entry->i2c_index, &dcb->i2c[entry->i2c_index]); 5559 5560 return true; 5561} 5562 5563static 5564void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb) 5565{ 5566 /* 5567 * DCB v2.0 lists each output combination separately. 5568 * Here we merge compatible entries to have fewer outputs, with 5569 * more options 5570 */ 5571 5572 int i, newentries = 0; 5573 5574 for (i = 0; i < dcb->entries; i++) { 5575 struct dcb_entry *ient = &dcb->entry[i]; 5576 int j; 5577 5578 for (j = i + 1; j < dcb->entries; j++) { 5579 struct dcb_entry *jent = &dcb->entry[j]; 5580 5581 if (jent->type == 100) /* already merged entry */ 5582 continue; 5583 5584 /* merge heads field when all other fields the same */ 5585 if (jent->i2c_index == ient->i2c_index && 5586 jent->type == ient->type && 5587 jent->location == ient->location && 5588 jent->or == ient->or) { 5589 NV_TRACE(dev, "Merging DCB entries %d and %d\n", 5590 i, j); 5591 ient->heads |= jent->heads; 5592 jent->type = 100; /* dummy value */ 5593 } 5594 } 5595 } 5596 5597 /* Compact entries merged into others out of dcb */ 5598 for (i = 0; i < dcb->entries; i++) { 5599 if (dcb->entry[i].type == 100) 5600 continue; 5601 5602 if (newentries != i) { 5603 dcb->entry[newentries] = dcb->entry[i]; 5604 dcb->entry[newentries].index = newentries; 5605 } 5606 newentries++; 5607 } 5608 5609 dcb->entries = newentries; 5610} 5611 5612static int 5613parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads) 5614{ 5615 struct drm_nouveau_private *dev_priv = dev->dev_private; 5616 struct dcb_table *dcb = &bios->dcb; 5617 uint16_t dcbptr = 0, i2ctabptr = 0; 5618 uint8_t *dcbtable; 5619 uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES; 5620 bool configblock = true; 5621 int recordlength = 8, confofs = 4; 5622 int i; 5623 5624 /* get the offset from 0x36 */ 5625 if (dev_priv->card_type > NV_04) { 5626 dcbptr = ROM16(bios->data[0x36]); 5627 if (dcbptr == 0x0000) 5628 NV_WARN(dev, "No output data (DCB) found in BIOS\n"); 5629 } 5630 5631 /* this situation likely means a really old card, pre DCB */ 5632 if (dcbptr == 0x0) { 5633 NV_INFO(dev, "Assuming a CRT output exists\n"); 5634 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1); 5635 5636 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0) 5637 fabricate_tv_output(dcb, twoHeads); 5638 5639 return 0; 5640 } 5641 5642 dcbtable = &bios->data[dcbptr]; 5643 5644 /* get DCB version */ 5645 dcb->version = dcbtable[0]; 5646 NV_TRACE(dev, "Found Display Configuration Block version %d.%d\n", 5647 dcb->version >> 4, dcb->version & 0xf); 5648 5649 if (dcb->version >= 0x20) { /* NV17+ */ 5650 uint32_t sig; 5651 5652 if (dcb->version >= 0x30) { /* NV40+ */ 5653 headerlen = dcbtable[1]; 5654 entries = dcbtable[2]; 5655 recordlength = dcbtable[3]; 5656 i2ctabptr = ROM16(dcbtable[4]); 5657 sig = ROM32(dcbtable[6]); 5658 dcb->gpio_table_ptr = ROM16(dcbtable[10]); 5659 dcb->connector_table_ptr = ROM16(dcbtable[20]); 5660 } else { 5661 i2ctabptr = ROM16(dcbtable[2]); 5662 sig = ROM32(dcbtable[4]); 5663 headerlen = 8; 5664 } 5665 5666 if (sig != 0x4edcbdcb) { 5667 NV_ERROR(dev, "Bad Display Configuration Block " 5668 "signature (%08X)\n", sig); 5669 return -EINVAL; 5670 } 5671 } else if (dcb->version >= 0x15) { /* some NV11 and NV20 */ 5672 char sig[8] = { 0 }; 5673 5674 strncpy(sig, (char *)&dcbtable[-7], 7); 5675 i2ctabptr = ROM16(dcbtable[2]); 5676 recordlength = 10; 5677 confofs = 6; 5678 5679 if (strcmp(sig, "DEV_REC")) { 5680 NV_ERROR(dev, "Bad Display Configuration Block " 5681 "signature (%s)\n", sig); 5682 return -EINVAL; 5683 } 5684 } else { 5685 /* 5686 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always 5687 * has the same single (crt) entry, even when tv-out present, so 5688 * the conclusion is this version cannot really be used. 5689 * v1.2 tables (some NV6/10, and NV15+) normally have the same 5690 * 5 entries, which are not specific to the card and so no use. 5691 * v1.2 does have an I2C table that read_dcb_i2c_table can 5692 * handle, but cards exist (nv11 in #14821) with a bad i2c table 5693 * pointer, so use the indices parsed in parse_bmp_structure. 5694 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful 5695 */ 5696 NV_TRACEWARN(dev, "No useful information in BIOS output table; " 5697 "adding all possible outputs\n"); 5698 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1); 5699 5700 /* 5701 * Attempt to detect TV before DVI because the test 5702 * for the former is more accurate and it rules the 5703 * latter out. 5704 */ 5705 if (nv04_tv_identify(dev, 5706 bios->legacy.i2c_indices.tv) >= 0) 5707 fabricate_tv_output(dcb, twoHeads); 5708 5709 else if (bios->tmds.output0_script_ptr || 5710 bios->tmds.output1_script_ptr) 5711 fabricate_dvi_i_output(dcb, twoHeads); 5712 5713 return 0; 5714 } 5715 5716 if (!i2ctabptr) 5717 NV_WARN(dev, "No pointer to DCB I2C port table\n"); 5718 else { 5719 dcb->i2c_table = &bios->data[i2ctabptr]; 5720 if (dcb->version >= 0x30) 5721 dcb->i2c_default_indices = dcb->i2c_table[4]; 5722 } 5723 5724 if (entries > DCB_MAX_NUM_ENTRIES) 5725 entries = DCB_MAX_NUM_ENTRIES; 5726 5727 for (i = 0; i < entries; i++) { 5728 uint32_t connection, config = 0; 5729 5730 connection = ROM32(dcbtable[headerlen + recordlength * i]); 5731 if (configblock) 5732 config = ROM32(dcbtable[headerlen + confofs + recordlength * i]); 5733 5734 /* seen on an NV11 with DCB v1.5 */ 5735 if (connection == 0x00000000) 5736 break; 5737 5738 /* seen on an NV17 with DCB v2.0 */ 5739 if (connection == 0xffffffff) 5740 break; 5741 5742 if ((connection & 0x0000000f) == 0x0000000f) 5743 continue; 5744 5745 NV_TRACEWARN(dev, "Raw DCB entry %d: %08x %08x\n", 5746 dcb->entries, connection, config); 5747 5748 if (!parse_dcb_entry(dev, dcb, connection, config)) 5749 break; 5750 } 5751 5752 /* 5753 * apart for v2.1+ not being known for requiring merging, this 5754 * guarantees dcbent->index is the index of the entry in the rom image 5755 */ 5756 if (dcb->version < 0x21) 5757 merge_like_dcb_entries(dev, dcb); 5758 5759 if (!dcb->entries) 5760 return -ENXIO; 5761 5762 parse_dcb_gpio_table(bios); 5763 parse_dcb_connector_table(bios); 5764 return 0; 5765} 5766 5767static void 5768fixup_legacy_connector(struct nvbios *bios) 5769{ 5770 struct dcb_table *dcb = &bios->dcb; 5771 int i, i2c, i2c_conn[DCB_MAX_NUM_I2C_ENTRIES] = { }; 5772 5773 /* 5774 * DCB 3.0 also has the table in most cases, but there are some cards 5775 * where the table is filled with stub entries, and the DCB entriy 5776 * indices are all 0. We don't need the connector indices on pre-G80 5777 * chips (yet?) so limit the use to DCB 4.0 and above. 5778 */ 5779 if (dcb->version >= 0x40) 5780 return; 5781 5782 dcb->connector.entries = 0; 5783 5784 /* 5785 * No known connector info before v3.0, so make it up. the rule here 5786 * is: anything on the same i2c bus is considered to be on the same 5787 * connector. any output without an associated i2c bus is assigned 5788 * its own unique connector index. 5789 */ 5790 for (i = 0; i < dcb->entries; i++) { 5791 /* 5792 * Ignore the I2C index for on-chip TV-out, as there 5793 * are cards with bogus values (nv31m in bug 23212), 5794 * and it's otherwise useless. 5795 */ 5796 if (dcb->entry[i].type == OUTPUT_TV && 5797 dcb->entry[i].location == DCB_LOC_ON_CHIP) 5798 dcb->entry[i].i2c_index = 0xf; 5799 i2c = dcb->entry[i].i2c_index; 5800 5801 if (i2c_conn[i2c]) { 5802 dcb->entry[i].connector = i2c_conn[i2c] - 1; 5803 continue; 5804 } 5805 5806 dcb->entry[i].connector = dcb->connector.entries++; 5807 if (i2c != 0xf) 5808 i2c_conn[i2c] = dcb->connector.entries; 5809 } 5810 5811 /* Fake the connector table as well as just connector indices */ 5812 for (i = 0; i < dcb->connector.entries; i++) { 5813 dcb->connector.entry[i].index = i; 5814 dcb->connector.entry[i].type = divine_connector_type(bios, i); 5815 dcb->connector.entry[i].gpio_tag = 0xff; 5816 } 5817} 5818 5819static void 5820fixup_legacy_i2c(struct nvbios *bios) 5821{ 5822 struct dcb_table *dcb = &bios->dcb; 5823 int i; 5824 5825 for (i = 0; i < dcb->entries; i++) { 5826 if (dcb->entry[i].i2c_index == LEGACY_I2C_CRT) 5827 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.crt; 5828 if (dcb->entry[i].i2c_index == LEGACY_I2C_PANEL) 5829 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.panel; 5830 if (dcb->entry[i].i2c_index == LEGACY_I2C_TV) 5831 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.tv; 5832 } 5833} 5834 5835static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry) 5836{ 5837 /* 5838 * The header following the "HWSQ" signature has the number of entries, 5839 * and the entry size 5840 * 5841 * An entry consists of a dword to write to the sequencer control reg 5842 * (0x00001304), followed by the ucode bytes, written sequentially, 5843 * starting at reg 0x00001400 5844 */ 5845 5846 uint8_t bytes_to_write; 5847 uint16_t hwsq_entry_offset; 5848 int i; 5849 5850 if (bios->data[hwsq_offset] <= entry) { 5851 NV_ERROR(dev, "Too few entries in HW sequencer table for " 5852 "requested entry\n"); 5853 return -ENOENT; 5854 } 5855 5856 bytes_to_write = bios->data[hwsq_offset + 1]; 5857 5858 if (bytes_to_write != 36) { 5859 NV_ERROR(dev, "Unknown HW sequencer entry size\n"); 5860 return -EINVAL; 5861 } 5862 5863 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n"); 5864 5865 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write; 5866 5867 /* set sequencer control */ 5868 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset])); 5869 bytes_to_write -= 4; 5870 5871 /* write ucode */ 5872 for (i = 0; i < bytes_to_write; i += 4) 5873 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4])); 5874 5875 /* twiddle NV_PBUS_DEBUG_4 */ 5876 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18); 5877 5878 return 0; 5879} 5880 5881static int load_nv17_hw_sequencer_ucode(struct drm_device *dev, 5882 struct nvbios *bios) 5883{ 5884 /* 5885 * BMP based cards, from NV17, need a microcode loading to correctly 5886 * control the GPIO etc for LVDS panels 5887 * 5888 * BIT based cards seem to do this directly in the init scripts 5889 * 5890 * The microcode entries are found by the "HWSQ" signature. 5891 */ 5892 5893 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' }; 5894 const int sz = sizeof(hwsq_signature); 5895 int hwsq_offset; 5896 5897 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz); 5898 if (!hwsq_offset) 5899 return 0; 5900 5901 /* always use entry 0? */ 5902 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0); 5903} 5904 5905uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev) 5906{ 5907 struct drm_nouveau_private *dev_priv = dev->dev_private; 5908 struct nvbios *bios = &dev_priv->vbios; 5909 const uint8_t edid_sig[] = { 5910 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 }; 5911 uint16_t offset = 0; 5912 uint16_t newoffset; 5913 int searchlen = NV_PROM_SIZE; 5914 5915 if (bios->fp.edid) 5916 return bios->fp.edid; 5917 5918 while (searchlen) { 5919 newoffset = findstr(&bios->data[offset], searchlen, 5920 edid_sig, 8); 5921 if (!newoffset) 5922 return NULL; 5923 offset += newoffset; 5924 if (!nv_cksum(&bios->data[offset], EDID1_LEN)) 5925 break; 5926 5927 searchlen -= offset; 5928 offset++; 5929 } 5930 5931 NV_TRACE(dev, "Found EDID in BIOS\n"); 5932 5933 return bios->fp.edid = &bios->data[offset]; 5934} 5935 5936void 5937nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table, 5938 struct dcb_entry *dcbent) 5939{ 5940 struct drm_nouveau_private *dev_priv = dev->dev_private; 5941 struct nvbios *bios = &dev_priv->vbios; 5942 struct init_exec iexec = { true, false }; 5943 5944 mutex_lock(&bios->lock); 5945 bios->display.output = dcbent; 5946 parse_init_table(bios, table, &iexec); 5947 bios->display.output = NULL; 5948 mutex_unlock(&bios->lock); 5949} 5950 5951static bool NVInitVBIOS(struct drm_device *dev) 5952{ 5953 struct drm_nouveau_private *dev_priv = dev->dev_private; 5954 struct nvbios *bios = &dev_priv->vbios; 5955 5956 memset(bios, 0, sizeof(struct nvbios)); 5957 mutex_init(&bios->lock); 5958 bios->dev = dev; 5959 5960 if (!NVShadowVBIOS(dev, bios->data)) 5961 return false; 5962 5963 bios->length = NV_PROM_SIZE; 5964 return true; 5965} 5966 5967static int nouveau_parse_vbios_struct(struct drm_device *dev) 5968{ 5969 struct drm_nouveau_private *dev_priv = dev->dev_private; 5970 struct nvbios *bios = &dev_priv->vbios; 5971 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' }; 5972 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 }; 5973 int offset; 5974 5975 offset = findstr(bios->data, bios->length, 5976 bit_signature, sizeof(bit_signature)); 5977 if (offset) { 5978 NV_TRACE(dev, "BIT BIOS found\n"); 5979 return parse_bit_structure(bios, offset + 6); 5980 } 5981 5982 offset = findstr(bios->data, bios->length, 5983 bmp_signature, sizeof(bmp_signature)); 5984 if (offset) { 5985 NV_TRACE(dev, "BMP BIOS found\n"); 5986 return parse_bmp_structure(dev, bios, offset); 5987 } 5988 5989 NV_ERROR(dev, "No known BIOS signature found\n"); 5990 return -ENODEV; 5991} 5992 5993int 5994nouveau_run_vbios_init(struct drm_device *dev) 5995{ 5996 struct drm_nouveau_private *dev_priv = dev->dev_private; 5997 struct nvbios *bios = &dev_priv->vbios; 5998 int i, ret = 0; 5999 6000 NVLockVgaCrtcs(dev, false); 6001 if (nv_two_heads(dev)) 6002 NVSetOwner(dev, bios->state.crtchead); 6003 6004 if (bios->major_version < 5) /* BMP only */ 6005 load_nv17_hw_sequencer_ucode(dev, bios); 6006 6007 if (bios->execute) { 6008 bios->fp.last_script_invoc = 0; 6009 bios->fp.lvds_init_run = false; 6010 } 6011 6012 parse_init_tables(bios); 6013 6014 /* 6015 * Runs some additional script seen on G8x VBIOSen. The VBIOS' 6016 * parser will run this right after the init tables, the binary 6017 * driver appears to run it at some point later. 6018 */ 6019 if (bios->some_script_ptr) { 6020 struct init_exec iexec = {true, false}; 6021 6022 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n", 6023 bios->some_script_ptr); 6024 parse_init_table(bios, bios->some_script_ptr, &iexec); 6025 } 6026 6027 if (dev_priv->card_type >= NV_50) { 6028 for (i = 0; i < bios->dcb.entries; i++) { 6029 nouveau_bios_run_display_table(dev, 6030 &bios->dcb.entry[i], 6031 0, 0); 6032 } 6033 } 6034 6035 NVLockVgaCrtcs(dev, true); 6036 6037 return ret; 6038} 6039 6040static void 6041nouveau_bios_i2c_devices_takedown(struct drm_device *dev) 6042{ 6043 struct drm_nouveau_private *dev_priv = dev->dev_private; 6044 struct nvbios *bios = &dev_priv->vbios; 6045 struct dcb_i2c_entry *entry; 6046 int i; 6047 6048 entry = &bios->dcb.i2c[0]; 6049 for (i = 0; i < DCB_MAX_NUM_I2C_ENTRIES; i++, entry++) 6050 nouveau_i2c_fini(dev, entry); 6051} 6052 6053int 6054nouveau_bios_init(struct drm_device *dev) 6055{ 6056 struct drm_nouveau_private *dev_priv = dev->dev_private; 6057 struct nvbios *bios = &dev_priv->vbios; 6058 uint32_t saved_nv_pextdev_boot_0; 6059 bool was_locked; 6060 int ret; 6061 6062 if (!NVInitVBIOS(dev)) 6063 return -ENODEV; 6064 6065 ret = nouveau_parse_vbios_struct(dev); 6066 if (ret) 6067 return ret; 6068 6069 ret = parse_dcb_table(dev, bios, nv_two_heads(dev)); 6070 if (ret) 6071 return ret; 6072 6073 fixup_legacy_i2c(bios); 6074 fixup_legacy_connector(bios); 6075 6076 if (!bios->major_version) /* we don't run version 0 bios */ 6077 return 0; 6078 6079 /* these will need remembering across a suspend */ 6080 saved_nv_pextdev_boot_0 = bios_rd32(bios, NV_PEXTDEV_BOOT_0); 6081 bios->state.saved_nv_pfb_cfg0 = bios_rd32(bios, NV_PFB_CFG0); 6082 6083 /* init script execution disabled */ 6084 bios->execute = false; 6085 6086 /* ... unless card isn't POSTed already */ 6087 if (dev_priv->card_type >= NV_10 && 6088 NVReadVgaCrtc(dev, 0, 0x00) == 0 && 6089 NVReadVgaCrtc(dev, 0, 0x1a) == 0) { 6090 NV_INFO(dev, "Adaptor not initialised\n"); 6091 if (dev_priv->card_type < NV_50) { 6092 NV_ERROR(dev, "Unable to POST this chipset\n"); 6093 return -ENODEV; 6094 } 6095 6096 NV_INFO(dev, "Running VBIOS init tables\n"); 6097 bios->execute = true; 6098 } 6099 6100 bios_wr32(bios, NV_PEXTDEV_BOOT_0, saved_nv_pextdev_boot_0); 6101 6102 ret = nouveau_run_vbios_init(dev); 6103 if (ret) 6104 return ret; 6105 6106 /* feature_byte on BMP is poor, but init always sets CR4B */ 6107 was_locked = NVLockVgaCrtcs(dev, false); 6108 if (bios->major_version < 5) 6109 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40; 6110 6111 /* all BIT systems need p_f_m_t for digital_min_front_porch */ 6112 if (bios->is_mobile || bios->major_version >= 5) 6113 ret = parse_fp_mode_table(dev, bios); 6114 NVLockVgaCrtcs(dev, was_locked); 6115 6116 /* allow subsequent scripts to execute */ 6117 bios->execute = true; 6118 6119 return 0; 6120} 6121 6122void 6123nouveau_bios_takedown(struct drm_device *dev) 6124{ 6125 nouveau_bios_i2c_devices_takedown(dev); 6126} 6127