nouveau_bios.c revision f50c0b91e7718e7deda46475cfd0ea1413daed04
1/* 2 * Copyright 2005-2006 Erik Waling 3 * Copyright 2006 Stephane Marchesin 4 * Copyright 2007-2009 Stuart Bennett 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 25#include "drmP.h" 26#define NV_DEBUG_NOTRACE 27#include "nouveau_drv.h" 28#include "nouveau_hw.h" 29#include "nouveau_encoder.h" 30 31/* these defines are made up */ 32#define NV_CIO_CRE_44_HEADA 0x0 33#define NV_CIO_CRE_44_HEADB 0x3 34#define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */ 35#define LEGACY_I2C_CRT 0x80 36#define LEGACY_I2C_PANEL 0x81 37#define LEGACY_I2C_TV 0x82 38 39#define EDID1_LEN 128 40 41#define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg) 42#define LOG_OLD_VALUE(x) 43 44#define ROM16(x) le16_to_cpu(*(uint16_t *)&(x)) 45#define ROM32(x) le32_to_cpu(*(uint32_t *)&(x)) 46 47struct init_exec { 48 bool execute; 49 bool repeat; 50}; 51 52static bool nv_cksum(const uint8_t *data, unsigned int length) 53{ 54 /* 55 * There's a few checksums in the BIOS, so here's a generic checking 56 * function. 57 */ 58 int i; 59 uint8_t sum = 0; 60 61 for (i = 0; i < length; i++) 62 sum += data[i]; 63 64 if (sum) 65 return true; 66 67 return false; 68} 69 70static int 71score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable) 72{ 73 if (!(data[0] == 0x55 && data[1] == 0xAA)) { 74 NV_TRACEWARN(dev, "... BIOS signature not found\n"); 75 return 0; 76 } 77 78 if (nv_cksum(data, data[2] * 512)) { 79 NV_TRACEWARN(dev, "... BIOS checksum invalid\n"); 80 /* if a ro image is somewhat bad, it's probably all rubbish */ 81 return writeable ? 2 : 1; 82 } else 83 NV_TRACE(dev, "... appears to be valid\n"); 84 85 return 3; 86} 87 88static void load_vbios_prom(struct drm_device *dev, uint8_t *data) 89{ 90 struct drm_nouveau_private *dev_priv = dev->dev_private; 91 uint32_t pci_nv_20, save_pci_nv_20; 92 int pcir_ptr; 93 int i; 94 95 if (dev_priv->card_type >= NV_50) 96 pci_nv_20 = 0x88050; 97 else 98 pci_nv_20 = NV_PBUS_PCI_NV_20; 99 100 /* enable ROM access */ 101 save_pci_nv_20 = nvReadMC(dev, pci_nv_20); 102 nvWriteMC(dev, pci_nv_20, 103 save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED); 104 105 /* bail if no rom signature */ 106 if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 || 107 nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa) 108 goto out; 109 110 /* additional check (see note below) - read PCI record header */ 111 pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) | 112 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8; 113 if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' || 114 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' || 115 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' || 116 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R') 117 goto out; 118 119 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a 120 * a good read may be obtained by waiting or re-reading (cargocult: 5x) 121 * each byte. we'll hope pramin has something usable instead 122 */ 123 for (i = 0; i < NV_PROM_SIZE; i++) 124 data[i] = nv_rd08(dev, NV_PROM_OFFSET + i); 125 126out: 127 /* disable ROM access */ 128 nvWriteMC(dev, pci_nv_20, 129 save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED); 130} 131 132static void load_vbios_pramin(struct drm_device *dev, uint8_t *data) 133{ 134 struct drm_nouveau_private *dev_priv = dev->dev_private; 135 uint32_t old_bar0_pramin = 0; 136 int i; 137 138 if (dev_priv->card_type >= NV_50) { 139 uint32_t vbios_vram = (nv_rd32(dev, 0x619f04) & ~0xff) << 8; 140 141 if (!vbios_vram) 142 vbios_vram = (nv_rd32(dev, 0x1700) << 16) + 0xf0000; 143 144 old_bar0_pramin = nv_rd32(dev, 0x1700); 145 nv_wr32(dev, 0x1700, vbios_vram >> 16); 146 } 147 148 /* bail if no rom signature */ 149 if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 || 150 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa) 151 goto out; 152 153 for (i = 0; i < NV_PROM_SIZE; i++) 154 data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i); 155 156out: 157 if (dev_priv->card_type >= NV_50) 158 nv_wr32(dev, 0x1700, old_bar0_pramin); 159} 160 161static void load_vbios_pci(struct drm_device *dev, uint8_t *data) 162{ 163 void __iomem *rom = NULL; 164 size_t rom_len; 165 int ret; 166 167 ret = pci_enable_rom(dev->pdev); 168 if (ret) 169 return; 170 171 rom = pci_map_rom(dev->pdev, &rom_len); 172 if (!rom) 173 goto out; 174 memcpy_fromio(data, rom, rom_len); 175 pci_unmap_rom(dev->pdev, rom); 176 177out: 178 pci_disable_rom(dev->pdev); 179} 180 181struct methods { 182 const char desc[8]; 183 void (*loadbios)(struct drm_device *, uint8_t *); 184 const bool rw; 185}; 186 187static struct methods nv04_methods[] = { 188 { "PROM", load_vbios_prom, false }, 189 { "PRAMIN", load_vbios_pramin, true }, 190 { "PCIROM", load_vbios_pci, true }, 191}; 192 193static struct methods nv50_methods[] = { 194 { "PRAMIN", load_vbios_pramin, true }, 195 { "PROM", load_vbios_prom, false }, 196 { "PCIROM", load_vbios_pci, true }, 197}; 198 199#define METHODCNT 3 200 201static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data) 202{ 203 struct drm_nouveau_private *dev_priv = dev->dev_private; 204 struct methods *methods; 205 int i; 206 int testscore = 3; 207 int scores[METHODCNT]; 208 209 if (nouveau_vbios) { 210 methods = nv04_methods; 211 for (i = 0; i < METHODCNT; i++) 212 if (!strcasecmp(nouveau_vbios, methods[i].desc)) 213 break; 214 215 if (i < METHODCNT) { 216 NV_INFO(dev, "Attempting to use BIOS image from %s\n", 217 methods[i].desc); 218 219 methods[i].loadbios(dev, data); 220 if (score_vbios(dev, data, methods[i].rw)) 221 return true; 222 } 223 224 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios); 225 } 226 227 if (dev_priv->card_type < NV_50) 228 methods = nv04_methods; 229 else 230 methods = nv50_methods; 231 232 for (i = 0; i < METHODCNT; i++) { 233 NV_TRACE(dev, "Attempting to load BIOS image from %s\n", 234 methods[i].desc); 235 data[0] = data[1] = 0; /* avoid reuse of previous image */ 236 methods[i].loadbios(dev, data); 237 scores[i] = score_vbios(dev, data, methods[i].rw); 238 if (scores[i] == testscore) 239 return true; 240 } 241 242 while (--testscore > 0) { 243 for (i = 0; i < METHODCNT; i++) { 244 if (scores[i] == testscore) { 245 NV_TRACE(dev, "Using BIOS image from %s\n", 246 methods[i].desc); 247 methods[i].loadbios(dev, data); 248 return true; 249 } 250 } 251 } 252 253 NV_ERROR(dev, "No valid BIOS image found\n"); 254 return false; 255} 256 257struct init_tbl_entry { 258 char *name; 259 uint8_t id; 260 /* Return: 261 * > 0: success, length of opcode 262 * 0: success, but abort further parsing of table (INIT_DONE etc) 263 * < 0: failure, table parsing will be aborted 264 */ 265 int (*handler)(struct nvbios *, uint16_t, struct init_exec *); 266}; 267 268struct bit_entry { 269 uint8_t id[2]; 270 uint16_t length; 271 uint16_t offset; 272}; 273 274static int parse_init_table(struct nvbios *, unsigned int, struct init_exec *); 275 276#define MACRO_INDEX_SIZE 2 277#define MACRO_SIZE 8 278#define CONDITION_SIZE 12 279#define IO_FLAG_CONDITION_SIZE 9 280#define IO_CONDITION_SIZE 5 281#define MEM_INIT_SIZE 66 282 283static void still_alive(void) 284{ 285#if 0 286 sync(); 287 msleep(2); 288#endif 289} 290 291static uint32_t 292munge_reg(struct nvbios *bios, uint32_t reg) 293{ 294 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 295 struct dcb_entry *dcbent = bios->display.output; 296 297 if (dev_priv->card_type < NV_50) 298 return reg; 299 300 if (reg & 0x40000000) { 301 BUG_ON(!dcbent); 302 303 reg += (ffs(dcbent->or) - 1) * 0x800; 304 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1)) 305 reg += 0x00000080; 306 } 307 308 reg &= ~0x60000000; 309 return reg; 310} 311 312static int 313valid_reg(struct nvbios *bios, uint32_t reg) 314{ 315 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 316 struct drm_device *dev = bios->dev; 317 318 /* C51 has misaligned regs on purpose. Marvellous */ 319 if (reg & 0x2 || 320 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51)) 321 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg); 322 323 /* warn on C51 regs that haven't been verified accessible in tracing */ 324 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 && 325 reg != 0x130d && reg != 0x1311 && reg != 0x60081d) 326 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n", 327 reg); 328 329 if (reg >= (8*1024*1024)) { 330 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg); 331 return 0; 332 } 333 334 return 1; 335} 336 337static bool 338valid_idx_port(struct nvbios *bios, uint16_t port) 339{ 340 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 341 struct drm_device *dev = bios->dev; 342 343 /* 344 * If adding more ports here, the read/write functions below will need 345 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is 346 * used for the port in question 347 */ 348 if (dev_priv->card_type < NV_50) { 349 if (port == NV_CIO_CRX__COLOR) 350 return true; 351 if (port == NV_VIO_SRX) 352 return true; 353 } else { 354 if (port == NV_CIO_CRX__COLOR) 355 return true; 356 } 357 358 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n", 359 port); 360 361 return false; 362} 363 364static bool 365valid_port(struct nvbios *bios, uint16_t port) 366{ 367 struct drm_device *dev = bios->dev; 368 369 /* 370 * If adding more ports here, the read/write functions below will need 371 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is 372 * used for the port in question 373 */ 374 if (port == NV_VIO_VSE2) 375 return true; 376 377 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port); 378 379 return false; 380} 381 382static uint32_t 383bios_rd32(struct nvbios *bios, uint32_t reg) 384{ 385 uint32_t data; 386 387 reg = munge_reg(bios, reg); 388 if (!valid_reg(bios, reg)) 389 return 0; 390 391 /* 392 * C51 sometimes uses regs with bit0 set in the address. For these 393 * cases there should exist a translation in a BIOS table to an IO 394 * port address which the BIOS uses for accessing the reg 395 * 396 * These only seem to appear for the power control regs to a flat panel, 397 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs 398 * for 0x1308 and 0x1310 are used - hence the mask below. An S3 399 * suspend-resume mmio trace from a C51 will be required to see if this 400 * is true for the power microcode in 0x14.., or whether the direct IO 401 * port access method is needed 402 */ 403 if (reg & 0x1) 404 reg &= ~0x1; 405 406 data = nv_rd32(bios->dev, reg); 407 408 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data); 409 410 return data; 411} 412 413static void 414bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data) 415{ 416 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 417 418 reg = munge_reg(bios, reg); 419 if (!valid_reg(bios, reg)) 420 return; 421 422 /* see note in bios_rd32 */ 423 if (reg & 0x1) 424 reg &= 0xfffffffe; 425 426 LOG_OLD_VALUE(bios_rd32(bios, reg)); 427 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data); 428 429 if (dev_priv->vbios.execute) { 430 still_alive(); 431 nv_wr32(bios->dev, reg, data); 432 } 433} 434 435static uint8_t 436bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index) 437{ 438 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 439 struct drm_device *dev = bios->dev; 440 uint8_t data; 441 442 if (!valid_idx_port(bios, port)) 443 return 0; 444 445 if (dev_priv->card_type < NV_50) { 446 if (port == NV_VIO_SRX) 447 data = NVReadVgaSeq(dev, bios->state.crtchead, index); 448 else /* assume NV_CIO_CRX__COLOR */ 449 data = NVReadVgaCrtc(dev, bios->state.crtchead, index); 450 } else { 451 uint32_t data32; 452 453 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3)); 454 data = (data32 >> ((index & 3) << 3)) & 0xff; 455 } 456 457 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, " 458 "Head: 0x%02X, Data: 0x%02X\n", 459 port, index, bios->state.crtchead, data); 460 return data; 461} 462 463static void 464bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data) 465{ 466 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 467 struct drm_device *dev = bios->dev; 468 469 if (!valid_idx_port(bios, port)) 470 return; 471 472 /* 473 * The current head is maintained in the nvbios member state.crtchead. 474 * We trap changes to CR44 and update the head variable and hence the 475 * register set written. 476 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance 477 * of the write, and to head1 after the write 478 */ 479 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 && 480 data != NV_CIO_CRE_44_HEADB) 481 bios->state.crtchead = 0; 482 483 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index)); 484 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, " 485 "Head: 0x%02X, Data: 0x%02X\n", 486 port, index, bios->state.crtchead, data); 487 488 if (bios->execute && dev_priv->card_type < NV_50) { 489 still_alive(); 490 if (port == NV_VIO_SRX) 491 NVWriteVgaSeq(dev, bios->state.crtchead, index, data); 492 else /* assume NV_CIO_CRX__COLOR */ 493 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data); 494 } else 495 if (bios->execute) { 496 uint32_t data32, shift = (index & 3) << 3; 497 498 still_alive(); 499 500 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3)); 501 data32 &= ~(0xff << shift); 502 data32 |= (data << shift); 503 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32); 504 } 505 506 if (port == NV_CIO_CRX__COLOR && 507 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB) 508 bios->state.crtchead = 1; 509} 510 511static uint8_t 512bios_port_rd(struct nvbios *bios, uint16_t port) 513{ 514 uint8_t data, head = bios->state.crtchead; 515 516 if (!valid_port(bios, port)) 517 return 0; 518 519 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port); 520 521 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n", 522 port, head, data); 523 524 return data; 525} 526 527static void 528bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data) 529{ 530 int head = bios->state.crtchead; 531 532 if (!valid_port(bios, port)) 533 return; 534 535 LOG_OLD_VALUE(bios_port_rd(bios, port)); 536 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n", 537 port, head, data); 538 539 if (!bios->execute) 540 return; 541 542 still_alive(); 543 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data); 544} 545 546static bool 547io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 548{ 549 /* 550 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte 551 * for the CRTC index; 1 byte for the mask to apply to the value 552 * retrieved from the CRTC; 1 byte for the shift right to apply to the 553 * masked CRTC value; 2 bytes for the offset to the flag array, to 554 * which the shifted value is added; 1 byte for the mask applied to the 555 * value read from the flag array; and 1 byte for the value to compare 556 * against the masked byte from the flag table. 557 */ 558 559 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE; 560 uint16_t crtcport = ROM16(bios->data[condptr]); 561 uint8_t crtcindex = bios->data[condptr + 2]; 562 uint8_t mask = bios->data[condptr + 3]; 563 uint8_t shift = bios->data[condptr + 4]; 564 uint16_t flagarray = ROM16(bios->data[condptr + 5]); 565 uint8_t flagarraymask = bios->data[condptr + 7]; 566 uint8_t cmpval = bios->data[condptr + 8]; 567 uint8_t data; 568 569 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 570 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, " 571 "Cmpval: 0x%02X\n", 572 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval); 573 574 data = bios_idxprt_rd(bios, crtcport, crtcindex); 575 576 data = bios->data[flagarray + ((data & mask) >> shift)]; 577 data &= flagarraymask; 578 579 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n", 580 offset, data, cmpval); 581 582 return (data == cmpval); 583} 584 585static bool 586bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 587{ 588 /* 589 * The condition table entry has 4 bytes for the address of the 590 * register to check, 4 bytes for a mask to apply to the register and 591 * 4 for a test comparison value 592 */ 593 594 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE; 595 uint32_t reg = ROM32(bios->data[condptr]); 596 uint32_t mask = ROM32(bios->data[condptr + 4]); 597 uint32_t cmpval = ROM32(bios->data[condptr + 8]); 598 uint32_t data; 599 600 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n", 601 offset, cond, reg, mask); 602 603 data = bios_rd32(bios, reg) & mask; 604 605 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n", 606 offset, data, cmpval); 607 608 return (data == cmpval); 609} 610 611static bool 612io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 613{ 614 /* 615 * The IO condition entry has 2 bytes for the IO port address; 1 byte 616 * for the index to write to io_port; 1 byte for the mask to apply to 617 * the byte read from io_port+1; and 1 byte for the value to compare 618 * against the masked byte. 619 */ 620 621 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE; 622 uint16_t io_port = ROM16(bios->data[condptr]); 623 uint8_t port_index = bios->data[condptr + 2]; 624 uint8_t mask = bios->data[condptr + 3]; 625 uint8_t cmpval = bios->data[condptr + 4]; 626 627 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask; 628 629 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n", 630 offset, data, cmpval); 631 632 return (data == cmpval); 633} 634 635static int 636nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk) 637{ 638 struct drm_nouveau_private *dev_priv = dev->dev_private; 639 uint32_t reg0 = nv_rd32(dev, reg + 0); 640 uint32_t reg1 = nv_rd32(dev, reg + 4); 641 struct nouveau_pll_vals pll; 642 struct pll_lims pll_limits; 643 int ret; 644 645 ret = get_pll_limits(dev, reg, &pll_limits); 646 if (ret) 647 return ret; 648 649 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll); 650 if (!clk) 651 return -ERANGE; 652 653 reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16); 654 reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1; 655 656 if (dev_priv->vbios.execute) { 657 still_alive(); 658 nv_wr32(dev, reg + 4, reg1); 659 nv_wr32(dev, reg + 0, reg0); 660 } 661 662 return 0; 663} 664 665static int 666setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk) 667{ 668 struct drm_device *dev = bios->dev; 669 struct drm_nouveau_private *dev_priv = dev->dev_private; 670 /* clk in kHz */ 671 struct pll_lims pll_lim; 672 struct nouveau_pll_vals pllvals; 673 int ret; 674 675 if (dev_priv->card_type >= NV_50) 676 return nv50_pll_set(dev, reg, clk); 677 678 /* high regs (such as in the mac g5 table) are not -= 4 */ 679 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim); 680 if (ret) 681 return ret; 682 683 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals); 684 if (!clk) 685 return -ERANGE; 686 687 if (bios->execute) { 688 still_alive(); 689 nouveau_hw_setpll(dev, reg, &pllvals); 690 } 691 692 return 0; 693} 694 695static int dcb_entry_idx_from_crtchead(struct drm_device *dev) 696{ 697 struct drm_nouveau_private *dev_priv = dev->dev_private; 698 struct nvbios *bios = &dev_priv->vbios; 699 700 /* 701 * For the results of this function to be correct, CR44 must have been 702 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0, 703 * and the DCB table parsed, before the script calling the function is 704 * run. run_digital_op_script is example of how to do such setup 705 */ 706 707 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0); 708 709 if (dcb_entry > bios->dcb.entries) { 710 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently " 711 "(%02X)\n", dcb_entry); 712 dcb_entry = 0x7f; /* unused / invalid marker */ 713 } 714 715 return dcb_entry; 716} 717 718static int 719read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, int index, struct dcb_i2c_entry *i2c) 720{ 721 uint8_t dcb_i2c_ver = dcb_version, headerlen = 0, entry_len = 4; 722 int i2c_entries = DCB_MAX_NUM_I2C_ENTRIES; 723 int recordoffset = 0, rdofs = 1, wrofs = 0; 724 uint8_t port_type = 0; 725 726 if (!i2ctable) 727 return -EINVAL; 728 729 if (dcb_version >= 0x30) { 730 if (i2ctable[0] != dcb_version) /* necessary? */ 731 NV_WARN(dev, 732 "DCB I2C table version mismatch (%02X vs %02X)\n", 733 i2ctable[0], dcb_version); 734 dcb_i2c_ver = i2ctable[0]; 735 headerlen = i2ctable[1]; 736 if (i2ctable[2] <= DCB_MAX_NUM_I2C_ENTRIES) 737 i2c_entries = i2ctable[2]; 738 else 739 NV_WARN(dev, 740 "DCB I2C table has more entries than indexable " 741 "(%d entries, max %d)\n", i2ctable[2], 742 DCB_MAX_NUM_I2C_ENTRIES); 743 entry_len = i2ctable[3]; 744 /* [4] is i2c_default_indices, read in parse_dcb_table() */ 745 } 746 /* 747 * It's your own fault if you call this function on a DCB 1.1 BIOS -- 748 * the test below is for DCB 1.2 749 */ 750 if (dcb_version < 0x14) { 751 recordoffset = 2; 752 rdofs = 0; 753 wrofs = 1; 754 } 755 756 if (index == 0xf) 757 return 0; 758 if (index >= i2c_entries) { 759 NV_ERROR(dev, "DCB I2C index too big (%d >= %d)\n", 760 index, i2ctable[2]); 761 return -ENOENT; 762 } 763 if (i2ctable[headerlen + entry_len * index + 3] == 0xff) { 764 NV_ERROR(dev, "DCB I2C entry invalid\n"); 765 return -EINVAL; 766 } 767 768 if (dcb_i2c_ver >= 0x30) { 769 port_type = i2ctable[headerlen + recordoffset + 3 + entry_len * index]; 770 771 /* 772 * Fixup for chips using same address offset for read and 773 * write. 774 */ 775 if (port_type == 4) /* seen on C51 */ 776 rdofs = wrofs = 1; 777 if (port_type >= 5) /* G80+ */ 778 rdofs = wrofs = 0; 779 } 780 781 if (dcb_i2c_ver >= 0x40) { 782 if (port_type != 5 && port_type != 6) 783 NV_WARN(dev, "DCB I2C table has port type %d\n", port_type); 784 785 i2c->entry = ROM32(i2ctable[headerlen + recordoffset + entry_len * index]); 786 } 787 788 i2c->port_type = port_type; 789 i2c->read = i2ctable[headerlen + recordoffset + rdofs + entry_len * index]; 790 i2c->write = i2ctable[headerlen + recordoffset + wrofs + entry_len * index]; 791 792 return 0; 793} 794 795static struct nouveau_i2c_chan * 796init_i2c_device_find(struct drm_device *dev, int i2c_index) 797{ 798 struct drm_nouveau_private *dev_priv = dev->dev_private; 799 struct dcb_table *dcb = &dev_priv->vbios.dcb; 800 801 if (i2c_index == 0xff) { 802 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */ 803 int idx = dcb_entry_idx_from_crtchead(dev), shift = 0; 804 int default_indices = dcb->i2c_default_indices; 805 806 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default) 807 shift = 4; 808 809 i2c_index = (default_indices >> shift) & 0xf; 810 } 811 if (i2c_index == 0x80) /* g80+ */ 812 i2c_index = dcb->i2c_default_indices & 0xf; 813 else 814 if (i2c_index == 0x81) 815 i2c_index = (dcb->i2c_default_indices & 0xf0) >> 4; 816 817 if (i2c_index > DCB_MAX_NUM_I2C_ENTRIES) { 818 NV_ERROR(dev, "invalid i2c_index 0x%x\n", i2c_index); 819 return NULL; 820 } 821 822 /* Make sure i2c table entry has been parsed, it may not 823 * have been if this is a bus not referenced by a DCB encoder 824 */ 825 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table, 826 i2c_index, &dcb->i2c[i2c_index]); 827 828 return nouveau_i2c_find(dev, i2c_index); 829} 830 831static uint32_t 832get_tmds_index_reg(struct drm_device *dev, uint8_t mlv) 833{ 834 /* 835 * For mlv < 0x80, it is an index into a table of TMDS base addresses. 836 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by 837 * CR58 for CR57 = 0 to index a table of offsets to the basic 838 * 0x6808b0 address. 839 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by 840 * CR58 for CR57 = 0 to index a table of offsets to the basic 841 * 0x6808b0 address, and then flip the offset by 8. 842 */ 843 844 struct drm_nouveau_private *dev_priv = dev->dev_private; 845 struct nvbios *bios = &dev_priv->vbios; 846 const int pramdac_offset[13] = { 847 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 }; 848 const uint32_t pramdac_table[4] = { 849 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 }; 850 851 if (mlv >= 0x80) { 852 int dcb_entry, dacoffset; 853 854 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */ 855 dcb_entry = dcb_entry_idx_from_crtchead(dev); 856 if (dcb_entry == 0x7f) 857 return 0; 858 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or]; 859 if (mlv == 0x81) 860 dacoffset ^= 8; 861 return 0x6808b0 + dacoffset; 862 } else { 863 if (mlv >= ARRAY_SIZE(pramdac_table)) { 864 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n", 865 mlv); 866 return 0; 867 } 868 return pramdac_table[mlv]; 869 } 870} 871 872static int 873init_io_restrict_prog(struct nvbios *bios, uint16_t offset, 874 struct init_exec *iexec) 875{ 876 /* 877 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2') 878 * 879 * offset (8 bit): opcode 880 * offset + 1 (16 bit): CRTC port 881 * offset + 3 (8 bit): CRTC index 882 * offset + 4 (8 bit): mask 883 * offset + 5 (8 bit): shift 884 * offset + 6 (8 bit): count 885 * offset + 7 (32 bit): register 886 * offset + 11 (32 bit): configuration 1 887 * ... 888 * 889 * Starting at offset + 11 there are "count" 32 bit values. 890 * To find out which value to use read index "CRTC index" on "CRTC 891 * port", AND this value with "mask" and then bit shift right "shift" 892 * bits. Read the appropriate value using this index and write to 893 * "register" 894 */ 895 896 uint16_t crtcport = ROM16(bios->data[offset + 1]); 897 uint8_t crtcindex = bios->data[offset + 3]; 898 uint8_t mask = bios->data[offset + 4]; 899 uint8_t shift = bios->data[offset + 5]; 900 uint8_t count = bios->data[offset + 6]; 901 uint32_t reg = ROM32(bios->data[offset + 7]); 902 uint8_t config; 903 uint32_t configval; 904 int len = 11 + count * 4; 905 906 if (!iexec->execute) 907 return len; 908 909 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 910 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n", 911 offset, crtcport, crtcindex, mask, shift, count, reg); 912 913 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 914 if (config > count) { 915 NV_ERROR(bios->dev, 916 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 917 offset, config, count); 918 return -EINVAL; 919 } 920 921 configval = ROM32(bios->data[offset + 11 + config * 4]); 922 923 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config); 924 925 bios_wr32(bios, reg, configval); 926 927 return len; 928} 929 930static int 931init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 932{ 933 /* 934 * INIT_REPEAT opcode: 0x33 ('3') 935 * 936 * offset (8 bit): opcode 937 * offset + 1 (8 bit): count 938 * 939 * Execute script following this opcode up to INIT_REPEAT_END 940 * "count" times 941 */ 942 943 uint8_t count = bios->data[offset + 1]; 944 uint8_t i; 945 946 /* no iexec->execute check by design */ 947 948 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n", 949 offset, count); 950 951 iexec->repeat = true; 952 953 /* 954 * count - 1, as the script block will execute once when we leave this 955 * opcode -- this is compatible with bios behaviour as: 956 * a) the block is always executed at least once, even if count == 0 957 * b) the bios interpreter skips to the op following INIT_END_REPEAT, 958 * while we don't 959 */ 960 for (i = 0; i < count - 1; i++) 961 parse_init_table(bios, offset + 2, iexec); 962 963 iexec->repeat = false; 964 965 return 2; 966} 967 968static int 969init_io_restrict_pll(struct nvbios *bios, uint16_t offset, 970 struct init_exec *iexec) 971{ 972 /* 973 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4') 974 * 975 * offset (8 bit): opcode 976 * offset + 1 (16 bit): CRTC port 977 * offset + 3 (8 bit): CRTC index 978 * offset + 4 (8 bit): mask 979 * offset + 5 (8 bit): shift 980 * offset + 6 (8 bit): IO flag condition index 981 * offset + 7 (8 bit): count 982 * offset + 8 (32 bit): register 983 * offset + 12 (16 bit): frequency 1 984 * ... 985 * 986 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz). 987 * Set PLL register "register" to coefficients for frequency n, 988 * selected by reading index "CRTC index" of "CRTC port" ANDed with 989 * "mask" and shifted right by "shift". 990 * 991 * If "IO flag condition index" > 0, and condition met, double 992 * frequency before setting it. 993 */ 994 995 uint16_t crtcport = ROM16(bios->data[offset + 1]); 996 uint8_t crtcindex = bios->data[offset + 3]; 997 uint8_t mask = bios->data[offset + 4]; 998 uint8_t shift = bios->data[offset + 5]; 999 int8_t io_flag_condition_idx = bios->data[offset + 6]; 1000 uint8_t count = bios->data[offset + 7]; 1001 uint32_t reg = ROM32(bios->data[offset + 8]); 1002 uint8_t config; 1003 uint16_t freq; 1004 int len = 12 + count * 2; 1005 1006 if (!iexec->execute) 1007 return len; 1008 1009 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 1010 "Shift: 0x%02X, IO Flag Condition: 0x%02X, " 1011 "Count: 0x%02X, Reg: 0x%08X\n", 1012 offset, crtcport, crtcindex, mask, shift, 1013 io_flag_condition_idx, count, reg); 1014 1015 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 1016 if (config > count) { 1017 NV_ERROR(bios->dev, 1018 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 1019 offset, config, count); 1020 return -EINVAL; 1021 } 1022 1023 freq = ROM16(bios->data[offset + 12 + config * 2]); 1024 1025 if (io_flag_condition_idx > 0) { 1026 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) { 1027 BIOSLOG(bios, "0x%04X: Condition fulfilled -- " 1028 "frequency doubled\n", offset); 1029 freq *= 2; 1030 } else 1031 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- " 1032 "frequency unchanged\n", offset); 1033 } 1034 1035 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n", 1036 offset, reg, config, freq); 1037 1038 setPLL(bios, reg, freq * 10); 1039 1040 return len; 1041} 1042 1043static int 1044init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1045{ 1046 /* 1047 * INIT_END_REPEAT opcode: 0x36 ('6') 1048 * 1049 * offset (8 bit): opcode 1050 * 1051 * Marks the end of the block for INIT_REPEAT to repeat 1052 */ 1053 1054 /* no iexec->execute check by design */ 1055 1056 /* 1057 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when 1058 * we're not in repeat mode 1059 */ 1060 if (iexec->repeat) 1061 return 0; 1062 1063 return 1; 1064} 1065 1066static int 1067init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1068{ 1069 /* 1070 * INIT_COPY opcode: 0x37 ('7') 1071 * 1072 * offset (8 bit): opcode 1073 * offset + 1 (32 bit): register 1074 * offset + 5 (8 bit): shift 1075 * offset + 6 (8 bit): srcmask 1076 * offset + 7 (16 bit): CRTC port 1077 * offset + 9 (8 bit): CRTC index 1078 * offset + 10 (8 bit): mask 1079 * 1080 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with 1081 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC 1082 * port 1083 */ 1084 1085 uint32_t reg = ROM32(bios->data[offset + 1]); 1086 uint8_t shift = bios->data[offset + 5]; 1087 uint8_t srcmask = bios->data[offset + 6]; 1088 uint16_t crtcport = ROM16(bios->data[offset + 7]); 1089 uint8_t crtcindex = bios->data[offset + 9]; 1090 uint8_t mask = bios->data[offset + 10]; 1091 uint32_t data; 1092 uint8_t crtcdata; 1093 1094 if (!iexec->execute) 1095 return 11; 1096 1097 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, " 1098 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n", 1099 offset, reg, shift, srcmask, crtcport, crtcindex, mask); 1100 1101 data = bios_rd32(bios, reg); 1102 1103 if (shift < 0x80) 1104 data >>= shift; 1105 else 1106 data <<= (0x100 - shift); 1107 1108 data &= srcmask; 1109 1110 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask; 1111 crtcdata |= (uint8_t)data; 1112 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata); 1113 1114 return 11; 1115} 1116 1117static int 1118init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1119{ 1120 /* 1121 * INIT_NOT opcode: 0x38 ('8') 1122 * 1123 * offset (8 bit): opcode 1124 * 1125 * Invert the current execute / no-execute condition (i.e. "else") 1126 */ 1127 if (iexec->execute) 1128 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset); 1129 else 1130 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset); 1131 1132 iexec->execute = !iexec->execute; 1133 return 1; 1134} 1135 1136static int 1137init_io_flag_condition(struct nvbios *bios, uint16_t offset, 1138 struct init_exec *iexec) 1139{ 1140 /* 1141 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9') 1142 * 1143 * offset (8 bit): opcode 1144 * offset + 1 (8 bit): condition number 1145 * 1146 * Check condition "condition number" in the IO flag condition table. 1147 * If condition not met skip subsequent opcodes until condition is 1148 * inverted (INIT_NOT), or we hit INIT_RESUME 1149 */ 1150 1151 uint8_t cond = bios->data[offset + 1]; 1152 1153 if (!iexec->execute) 1154 return 2; 1155 1156 if (io_flag_condition_met(bios, offset, cond)) 1157 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 1158 else { 1159 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 1160 iexec->execute = false; 1161 } 1162 1163 return 2; 1164} 1165 1166static int 1167init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1168{ 1169 /* 1170 * INIT_DP_CONDITION opcode: 0x3A ('') 1171 * 1172 * offset (8 bit): opcode 1173 * offset + 1 (8 bit): "sub" opcode 1174 * offset + 2 (8 bit): unknown 1175 * 1176 */ 1177 1178 struct bit_displayport_encoder_table *dpe = NULL; 1179 struct dcb_entry *dcb = bios->display.output; 1180 struct drm_device *dev = bios->dev; 1181 uint8_t cond = bios->data[offset + 1]; 1182 int dummy; 1183 1184 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond); 1185 1186 if (!iexec->execute) 1187 return 3; 1188 1189 dpe = nouveau_bios_dp_table(dev, dcb, &dummy); 1190 if (!dpe) { 1191 NV_ERROR(dev, "0x%04X: INIT_3A: no encoder table!!\n", offset); 1192 return -EINVAL; 1193 } 1194 1195 switch (cond) { 1196 case 0: 1197 { 1198 struct dcb_connector_table_entry *ent = 1199 &bios->dcb.connector.entry[dcb->connector]; 1200 1201 if (ent->type != DCB_CONNECTOR_eDP) 1202 iexec->execute = false; 1203 } 1204 break; 1205 case 1: 1206 case 2: 1207 if (!(dpe->unknown & cond)) 1208 iexec->execute = false; 1209 break; 1210 case 5: 1211 { 1212 struct nouveau_i2c_chan *auxch; 1213 int ret; 1214 1215 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index); 1216 if (!auxch) 1217 return -ENODEV; 1218 1219 ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1); 1220 if (ret) 1221 return ret; 1222 1223 if (cond & 1) 1224 iexec->execute = false; 1225 } 1226 break; 1227 default: 1228 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond); 1229 break; 1230 } 1231 1232 if (iexec->execute) 1233 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset); 1234 else 1235 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset); 1236 1237 return 3; 1238} 1239 1240static int 1241init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1242{ 1243 /* 1244 * INIT_3B opcode: 0x3B ('') 1245 * 1246 * offset (8 bit): opcode 1247 * offset + 1 (8 bit): crtc index 1248 * 1249 */ 1250 1251 uint8_t or = ffs(bios->display.output->or) - 1; 1252 uint8_t index = bios->data[offset + 1]; 1253 uint8_t data; 1254 1255 if (!iexec->execute) 1256 return 2; 1257 1258 data = bios_idxprt_rd(bios, 0x3d4, index); 1259 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or)); 1260 return 2; 1261} 1262 1263static int 1264init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1265{ 1266 /* 1267 * INIT_3C opcode: 0x3C ('') 1268 * 1269 * offset (8 bit): opcode 1270 * offset + 1 (8 bit): crtc index 1271 * 1272 */ 1273 1274 uint8_t or = ffs(bios->display.output->or) - 1; 1275 uint8_t index = bios->data[offset + 1]; 1276 uint8_t data; 1277 1278 if (!iexec->execute) 1279 return 2; 1280 1281 data = bios_idxprt_rd(bios, 0x3d4, index); 1282 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or)); 1283 return 2; 1284} 1285 1286static int 1287init_idx_addr_latched(struct nvbios *bios, uint16_t offset, 1288 struct init_exec *iexec) 1289{ 1290 /* 1291 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I') 1292 * 1293 * offset (8 bit): opcode 1294 * offset + 1 (32 bit): control register 1295 * offset + 5 (32 bit): data register 1296 * offset + 9 (32 bit): mask 1297 * offset + 13 (32 bit): data 1298 * offset + 17 (8 bit): count 1299 * offset + 18 (8 bit): address 1 1300 * offset + 19 (8 bit): data 1 1301 * ... 1302 * 1303 * For each of "count" address and data pairs, write "data n" to 1304 * "data register", read the current value of "control register", 1305 * and write it back once ANDed with "mask", ORed with "data", 1306 * and ORed with "address n" 1307 */ 1308 1309 uint32_t controlreg = ROM32(bios->data[offset + 1]); 1310 uint32_t datareg = ROM32(bios->data[offset + 5]); 1311 uint32_t mask = ROM32(bios->data[offset + 9]); 1312 uint32_t data = ROM32(bios->data[offset + 13]); 1313 uint8_t count = bios->data[offset + 17]; 1314 int len = 18 + count * 2; 1315 uint32_t value; 1316 int i; 1317 1318 if (!iexec->execute) 1319 return len; 1320 1321 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, " 1322 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n", 1323 offset, controlreg, datareg, mask, data, count); 1324 1325 for (i = 0; i < count; i++) { 1326 uint8_t instaddress = bios->data[offset + 18 + i * 2]; 1327 uint8_t instdata = bios->data[offset + 19 + i * 2]; 1328 1329 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n", 1330 offset, instaddress, instdata); 1331 1332 bios_wr32(bios, datareg, instdata); 1333 value = bios_rd32(bios, controlreg) & mask; 1334 value |= data; 1335 value |= instaddress; 1336 bios_wr32(bios, controlreg, value); 1337 } 1338 1339 return len; 1340} 1341 1342static int 1343init_io_restrict_pll2(struct nvbios *bios, uint16_t offset, 1344 struct init_exec *iexec) 1345{ 1346 /* 1347 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J') 1348 * 1349 * offset (8 bit): opcode 1350 * offset + 1 (16 bit): CRTC port 1351 * offset + 3 (8 bit): CRTC index 1352 * offset + 4 (8 bit): mask 1353 * offset + 5 (8 bit): shift 1354 * offset + 6 (8 bit): count 1355 * offset + 7 (32 bit): register 1356 * offset + 11 (32 bit): frequency 1 1357 * ... 1358 * 1359 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz). 1360 * Set PLL register "register" to coefficients for frequency n, 1361 * selected by reading index "CRTC index" of "CRTC port" ANDed with 1362 * "mask" and shifted right by "shift". 1363 */ 1364 1365 uint16_t crtcport = ROM16(bios->data[offset + 1]); 1366 uint8_t crtcindex = bios->data[offset + 3]; 1367 uint8_t mask = bios->data[offset + 4]; 1368 uint8_t shift = bios->data[offset + 5]; 1369 uint8_t count = bios->data[offset + 6]; 1370 uint32_t reg = ROM32(bios->data[offset + 7]); 1371 int len = 11 + count * 4; 1372 uint8_t config; 1373 uint32_t freq; 1374 1375 if (!iexec->execute) 1376 return len; 1377 1378 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 1379 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n", 1380 offset, crtcport, crtcindex, mask, shift, count, reg); 1381 1382 if (!reg) 1383 return len; 1384 1385 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 1386 if (config > count) { 1387 NV_ERROR(bios->dev, 1388 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 1389 offset, config, count); 1390 return -EINVAL; 1391 } 1392 1393 freq = ROM32(bios->data[offset + 11 + config * 4]); 1394 1395 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n", 1396 offset, reg, config, freq); 1397 1398 setPLL(bios, reg, freq); 1399 1400 return len; 1401} 1402 1403static int 1404init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1405{ 1406 /* 1407 * INIT_PLL2 opcode: 0x4B ('K') 1408 * 1409 * offset (8 bit): opcode 1410 * offset + 1 (32 bit): register 1411 * offset + 5 (32 bit): freq 1412 * 1413 * Set PLL register "register" to coefficients for frequency "freq" 1414 */ 1415 1416 uint32_t reg = ROM32(bios->data[offset + 1]); 1417 uint32_t freq = ROM32(bios->data[offset + 5]); 1418 1419 if (!iexec->execute) 1420 return 9; 1421 1422 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n", 1423 offset, reg, freq); 1424 1425 setPLL(bios, reg, freq); 1426 return 9; 1427} 1428 1429static int 1430init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1431{ 1432 /* 1433 * INIT_I2C_BYTE opcode: 0x4C ('L') 1434 * 1435 * offset (8 bit): opcode 1436 * offset + 1 (8 bit): DCB I2C table entry index 1437 * offset + 2 (8 bit): I2C slave address 1438 * offset + 3 (8 bit): count 1439 * offset + 4 (8 bit): I2C register 1 1440 * offset + 5 (8 bit): mask 1 1441 * offset + 6 (8 bit): data 1 1442 * ... 1443 * 1444 * For each of "count" registers given by "I2C register n" on the device 1445 * addressed by "I2C slave address" on the I2C bus given by 1446 * "DCB I2C table entry index", read the register, AND the result with 1447 * "mask n" and OR it with "data n" before writing it back to the device 1448 */ 1449 1450 uint8_t i2c_index = bios->data[offset + 1]; 1451 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1452 uint8_t count = bios->data[offset + 3]; 1453 struct nouveau_i2c_chan *chan; 1454 int len = 4 + count * 3; 1455 int ret, i; 1456 1457 if (!iexec->execute) 1458 return len; 1459 1460 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1461 "Count: 0x%02X\n", 1462 offset, i2c_index, i2c_address, count); 1463 1464 chan = init_i2c_device_find(bios->dev, i2c_index); 1465 if (!chan) 1466 return -ENODEV; 1467 1468 for (i = 0; i < count; i++) { 1469 uint8_t reg = bios->data[offset + 4 + i * 3]; 1470 uint8_t mask = bios->data[offset + 5 + i * 3]; 1471 uint8_t data = bios->data[offset + 6 + i * 3]; 1472 union i2c_smbus_data val; 1473 1474 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 1475 I2C_SMBUS_READ, reg, 1476 I2C_SMBUS_BYTE_DATA, &val); 1477 if (ret < 0) 1478 return ret; 1479 1480 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, " 1481 "Mask: 0x%02X, Data: 0x%02X\n", 1482 offset, reg, val.byte, mask, data); 1483 1484 if (!bios->execute) 1485 continue; 1486 1487 val.byte &= mask; 1488 val.byte |= data; 1489 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 1490 I2C_SMBUS_WRITE, reg, 1491 I2C_SMBUS_BYTE_DATA, &val); 1492 if (ret < 0) 1493 return ret; 1494 } 1495 1496 return len; 1497} 1498 1499static int 1500init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1501{ 1502 /* 1503 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M') 1504 * 1505 * offset (8 bit): opcode 1506 * offset + 1 (8 bit): DCB I2C table entry index 1507 * offset + 2 (8 bit): I2C slave address 1508 * offset + 3 (8 bit): count 1509 * offset + 4 (8 bit): I2C register 1 1510 * offset + 5 (8 bit): data 1 1511 * ... 1512 * 1513 * For each of "count" registers given by "I2C register n" on the device 1514 * addressed by "I2C slave address" on the I2C bus given by 1515 * "DCB I2C table entry index", set the register to "data n" 1516 */ 1517 1518 uint8_t i2c_index = bios->data[offset + 1]; 1519 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1520 uint8_t count = bios->data[offset + 3]; 1521 struct nouveau_i2c_chan *chan; 1522 int len = 4 + count * 2; 1523 int ret, i; 1524 1525 if (!iexec->execute) 1526 return len; 1527 1528 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1529 "Count: 0x%02X\n", 1530 offset, i2c_index, i2c_address, count); 1531 1532 chan = init_i2c_device_find(bios->dev, i2c_index); 1533 if (!chan) 1534 return -ENODEV; 1535 1536 for (i = 0; i < count; i++) { 1537 uint8_t reg = bios->data[offset + 4 + i * 2]; 1538 union i2c_smbus_data val; 1539 1540 val.byte = bios->data[offset + 5 + i * 2]; 1541 1542 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n", 1543 offset, reg, val.byte); 1544 1545 if (!bios->execute) 1546 continue; 1547 1548 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 1549 I2C_SMBUS_WRITE, reg, 1550 I2C_SMBUS_BYTE_DATA, &val); 1551 if (ret < 0) 1552 return ret; 1553 } 1554 1555 return len; 1556} 1557 1558static int 1559init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1560{ 1561 /* 1562 * INIT_ZM_I2C opcode: 0x4E ('N') 1563 * 1564 * offset (8 bit): opcode 1565 * offset + 1 (8 bit): DCB I2C table entry index 1566 * offset + 2 (8 bit): I2C slave address 1567 * offset + 3 (8 bit): count 1568 * offset + 4 (8 bit): data 1 1569 * ... 1570 * 1571 * Send "count" bytes ("data n") to the device addressed by "I2C slave 1572 * address" on the I2C bus given by "DCB I2C table entry index" 1573 */ 1574 1575 uint8_t i2c_index = bios->data[offset + 1]; 1576 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1577 uint8_t count = bios->data[offset + 3]; 1578 int len = 4 + count; 1579 struct nouveau_i2c_chan *chan; 1580 struct i2c_msg msg; 1581 uint8_t data[256]; 1582 int i; 1583 1584 if (!iexec->execute) 1585 return len; 1586 1587 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1588 "Count: 0x%02X\n", 1589 offset, i2c_index, i2c_address, count); 1590 1591 chan = init_i2c_device_find(bios->dev, i2c_index); 1592 if (!chan) 1593 return -ENODEV; 1594 1595 for (i = 0; i < count; i++) { 1596 data[i] = bios->data[offset + 4 + i]; 1597 1598 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]); 1599 } 1600 1601 if (bios->execute) { 1602 msg.addr = i2c_address; 1603 msg.flags = 0; 1604 msg.len = count; 1605 msg.buf = data; 1606 if (i2c_transfer(&chan->adapter, &msg, 1) != 1) 1607 return -EIO; 1608 } 1609 1610 return len; 1611} 1612 1613static int 1614init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1615{ 1616 /* 1617 * INIT_TMDS opcode: 0x4F ('O') (non-canon name) 1618 * 1619 * offset (8 bit): opcode 1620 * offset + 1 (8 bit): magic lookup value 1621 * offset + 2 (8 bit): TMDS address 1622 * offset + 3 (8 bit): mask 1623 * offset + 4 (8 bit): data 1624 * 1625 * Read the data reg for TMDS address "TMDS address", AND it with mask 1626 * and OR it with data, then write it back 1627 * "magic lookup value" determines which TMDS base address register is 1628 * used -- see get_tmds_index_reg() 1629 */ 1630 1631 uint8_t mlv = bios->data[offset + 1]; 1632 uint32_t tmdsaddr = bios->data[offset + 2]; 1633 uint8_t mask = bios->data[offset + 3]; 1634 uint8_t data = bios->data[offset + 4]; 1635 uint32_t reg, value; 1636 1637 if (!iexec->execute) 1638 return 5; 1639 1640 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, " 1641 "Mask: 0x%02X, Data: 0x%02X\n", 1642 offset, mlv, tmdsaddr, mask, data); 1643 1644 reg = get_tmds_index_reg(bios->dev, mlv); 1645 if (!reg) 1646 return -EINVAL; 1647 1648 bios_wr32(bios, reg, 1649 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE); 1650 value = (bios_rd32(bios, reg + 4) & mask) | data; 1651 bios_wr32(bios, reg + 4, value); 1652 bios_wr32(bios, reg, tmdsaddr); 1653 1654 return 5; 1655} 1656 1657static int 1658init_zm_tmds_group(struct nvbios *bios, uint16_t offset, 1659 struct init_exec *iexec) 1660{ 1661 /* 1662 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name) 1663 * 1664 * offset (8 bit): opcode 1665 * offset + 1 (8 bit): magic lookup value 1666 * offset + 2 (8 bit): count 1667 * offset + 3 (8 bit): addr 1 1668 * offset + 4 (8 bit): data 1 1669 * ... 1670 * 1671 * For each of "count" TMDS address and data pairs write "data n" to 1672 * "addr n". "magic lookup value" determines which TMDS base address 1673 * register is used -- see get_tmds_index_reg() 1674 */ 1675 1676 uint8_t mlv = bios->data[offset + 1]; 1677 uint8_t count = bios->data[offset + 2]; 1678 int len = 3 + count * 2; 1679 uint32_t reg; 1680 int i; 1681 1682 if (!iexec->execute) 1683 return len; 1684 1685 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n", 1686 offset, mlv, count); 1687 1688 reg = get_tmds_index_reg(bios->dev, mlv); 1689 if (!reg) 1690 return -EINVAL; 1691 1692 for (i = 0; i < count; i++) { 1693 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2]; 1694 uint8_t tmdsdata = bios->data[offset + 4 + i * 2]; 1695 1696 bios_wr32(bios, reg + 4, tmdsdata); 1697 bios_wr32(bios, reg, tmdsaddr); 1698 } 1699 1700 return len; 1701} 1702 1703static int 1704init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset, 1705 struct init_exec *iexec) 1706{ 1707 /* 1708 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q') 1709 * 1710 * offset (8 bit): opcode 1711 * offset + 1 (8 bit): CRTC index1 1712 * offset + 2 (8 bit): CRTC index2 1713 * offset + 3 (8 bit): baseaddr 1714 * offset + 4 (8 bit): count 1715 * offset + 5 (8 bit): data 1 1716 * ... 1717 * 1718 * For each of "count" address and data pairs, write "baseaddr + n" to 1719 * "CRTC index1" and "data n" to "CRTC index2" 1720 * Once complete, restore initial value read from "CRTC index1" 1721 */ 1722 uint8_t crtcindex1 = bios->data[offset + 1]; 1723 uint8_t crtcindex2 = bios->data[offset + 2]; 1724 uint8_t baseaddr = bios->data[offset + 3]; 1725 uint8_t count = bios->data[offset + 4]; 1726 int len = 5 + count; 1727 uint8_t oldaddr, data; 1728 int i; 1729 1730 if (!iexec->execute) 1731 return len; 1732 1733 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, " 1734 "BaseAddr: 0x%02X, Count: 0x%02X\n", 1735 offset, crtcindex1, crtcindex2, baseaddr, count); 1736 1737 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1); 1738 1739 for (i = 0; i < count; i++) { 1740 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, 1741 baseaddr + i); 1742 data = bios->data[offset + 5 + i]; 1743 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data); 1744 } 1745 1746 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr); 1747 1748 return len; 1749} 1750 1751static int 1752init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1753{ 1754 /* 1755 * INIT_CR opcode: 0x52 ('R') 1756 * 1757 * offset (8 bit): opcode 1758 * offset + 1 (8 bit): CRTC index 1759 * offset + 2 (8 bit): mask 1760 * offset + 3 (8 bit): data 1761 * 1762 * Assign the value of at "CRTC index" ANDed with mask and ORed with 1763 * data back to "CRTC index" 1764 */ 1765 1766 uint8_t crtcindex = bios->data[offset + 1]; 1767 uint8_t mask = bios->data[offset + 2]; 1768 uint8_t data = bios->data[offset + 3]; 1769 uint8_t value; 1770 1771 if (!iexec->execute) 1772 return 4; 1773 1774 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n", 1775 offset, crtcindex, mask, data); 1776 1777 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask; 1778 value |= data; 1779 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value); 1780 1781 return 4; 1782} 1783 1784static int 1785init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1786{ 1787 /* 1788 * INIT_ZM_CR opcode: 0x53 ('S') 1789 * 1790 * offset (8 bit): opcode 1791 * offset + 1 (8 bit): CRTC index 1792 * offset + 2 (8 bit): value 1793 * 1794 * Assign "value" to CRTC register with index "CRTC index". 1795 */ 1796 1797 uint8_t crtcindex = ROM32(bios->data[offset + 1]); 1798 uint8_t data = bios->data[offset + 2]; 1799 1800 if (!iexec->execute) 1801 return 3; 1802 1803 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data); 1804 1805 return 3; 1806} 1807 1808static int 1809init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1810{ 1811 /* 1812 * INIT_ZM_CR_GROUP opcode: 0x54 ('T') 1813 * 1814 * offset (8 bit): opcode 1815 * offset + 1 (8 bit): count 1816 * offset + 2 (8 bit): CRTC index 1 1817 * offset + 3 (8 bit): value 1 1818 * ... 1819 * 1820 * For "count", assign "value n" to CRTC register with index 1821 * "CRTC index n". 1822 */ 1823 1824 uint8_t count = bios->data[offset + 1]; 1825 int len = 2 + count * 2; 1826 int i; 1827 1828 if (!iexec->execute) 1829 return len; 1830 1831 for (i = 0; i < count; i++) 1832 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec); 1833 1834 return len; 1835} 1836 1837static int 1838init_condition_time(struct nvbios *bios, uint16_t offset, 1839 struct init_exec *iexec) 1840{ 1841 /* 1842 * INIT_CONDITION_TIME opcode: 0x56 ('V') 1843 * 1844 * offset (8 bit): opcode 1845 * offset + 1 (8 bit): condition number 1846 * offset + 2 (8 bit): retries / 50 1847 * 1848 * Check condition "condition number" in the condition table. 1849 * Bios code then sleeps for 2ms if the condition is not met, and 1850 * repeats up to "retries" times, but on one C51 this has proved 1851 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do 1852 * this, and bail after "retries" times, or 2s, whichever is less. 1853 * If still not met after retries, clear execution flag for this table. 1854 */ 1855 1856 uint8_t cond = bios->data[offset + 1]; 1857 uint16_t retries = bios->data[offset + 2] * 50; 1858 unsigned cnt; 1859 1860 if (!iexec->execute) 1861 return 3; 1862 1863 if (retries > 100) 1864 retries = 100; 1865 1866 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n", 1867 offset, cond, retries); 1868 1869 if (!bios->execute) /* avoid 2s delays when "faking" execution */ 1870 retries = 1; 1871 1872 for (cnt = 0; cnt < retries; cnt++) { 1873 if (bios_condition_met(bios, offset, cond)) { 1874 BIOSLOG(bios, "0x%04X: Condition met, continuing\n", 1875 offset); 1876 break; 1877 } else { 1878 BIOSLOG(bios, "0x%04X: " 1879 "Condition not met, sleeping for 20ms\n", 1880 offset); 1881 msleep(20); 1882 } 1883 } 1884 1885 if (!bios_condition_met(bios, offset, cond)) { 1886 NV_WARN(bios->dev, 1887 "0x%04X: Condition still not met after %dms, " 1888 "skipping following opcodes\n", offset, 20 * retries); 1889 iexec->execute = false; 1890 } 1891 1892 return 3; 1893} 1894 1895static int 1896init_zm_reg_sequence(struct nvbios *bios, uint16_t offset, 1897 struct init_exec *iexec) 1898{ 1899 /* 1900 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X') 1901 * 1902 * offset (8 bit): opcode 1903 * offset + 1 (32 bit): base register 1904 * offset + 5 (8 bit): count 1905 * offset + 6 (32 bit): value 1 1906 * ... 1907 * 1908 * Starting at offset + 6 there are "count" 32 bit values. 1909 * For "count" iterations set "base register" + 4 * current_iteration 1910 * to "value current_iteration" 1911 */ 1912 1913 uint32_t basereg = ROM32(bios->data[offset + 1]); 1914 uint32_t count = bios->data[offset + 5]; 1915 int len = 6 + count * 4; 1916 int i; 1917 1918 if (!iexec->execute) 1919 return len; 1920 1921 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n", 1922 offset, basereg, count); 1923 1924 for (i = 0; i < count; i++) { 1925 uint32_t reg = basereg + i * 4; 1926 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]); 1927 1928 bios_wr32(bios, reg, data); 1929 } 1930 1931 return len; 1932} 1933 1934static int 1935init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1936{ 1937 /* 1938 * INIT_SUB_DIRECT opcode: 0x5B ('[') 1939 * 1940 * offset (8 bit): opcode 1941 * offset + 1 (16 bit): subroutine offset (in bios) 1942 * 1943 * Calls a subroutine that will execute commands until INIT_DONE 1944 * is found. 1945 */ 1946 1947 uint16_t sub_offset = ROM16(bios->data[offset + 1]); 1948 1949 if (!iexec->execute) 1950 return 3; 1951 1952 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n", 1953 offset, sub_offset); 1954 1955 parse_init_table(bios, sub_offset, iexec); 1956 1957 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset); 1958 1959 return 3; 1960} 1961 1962static int 1963init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1964{ 1965 /* 1966 * INIT_COPY_NV_REG opcode: 0x5F ('_') 1967 * 1968 * offset (8 bit): opcode 1969 * offset + 1 (32 bit): src reg 1970 * offset + 5 (8 bit): shift 1971 * offset + 6 (32 bit): src mask 1972 * offset + 10 (32 bit): xor 1973 * offset + 14 (32 bit): dst reg 1974 * offset + 18 (32 bit): dst mask 1975 * 1976 * Shift REGVAL("src reg") right by (signed) "shift", AND result with 1977 * "src mask", then XOR with "xor". Write this OR'd with 1978 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg" 1979 */ 1980 1981 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1])); 1982 uint8_t shift = bios->data[offset + 5]; 1983 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6])); 1984 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10])); 1985 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14])); 1986 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18])); 1987 uint32_t srcvalue, dstvalue; 1988 1989 if (!iexec->execute) 1990 return 22; 1991 1992 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, " 1993 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n", 1994 offset, srcreg, shift, srcmask, xor, dstreg, dstmask); 1995 1996 srcvalue = bios_rd32(bios, srcreg); 1997 1998 if (shift < 0x80) 1999 srcvalue >>= shift; 2000 else 2001 srcvalue <<= (0x100 - shift); 2002 2003 srcvalue = (srcvalue & srcmask) ^ xor; 2004 2005 dstvalue = bios_rd32(bios, dstreg) & dstmask; 2006 2007 bios_wr32(bios, dstreg, dstvalue | srcvalue); 2008 2009 return 22; 2010} 2011 2012static int 2013init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2014{ 2015 /* 2016 * INIT_ZM_INDEX_IO opcode: 0x62 ('b') 2017 * 2018 * offset (8 bit): opcode 2019 * offset + 1 (16 bit): CRTC port 2020 * offset + 3 (8 bit): CRTC index 2021 * offset + 4 (8 bit): data 2022 * 2023 * Write "data" to index "CRTC index" of "CRTC port" 2024 */ 2025 uint16_t crtcport = ROM16(bios->data[offset + 1]); 2026 uint8_t crtcindex = bios->data[offset + 3]; 2027 uint8_t data = bios->data[offset + 4]; 2028 2029 if (!iexec->execute) 2030 return 5; 2031 2032 bios_idxprt_wr(bios, crtcport, crtcindex, data); 2033 2034 return 5; 2035} 2036 2037static int 2038init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2039{ 2040 /* 2041 * INIT_COMPUTE_MEM opcode: 0x63 ('c') 2042 * 2043 * offset (8 bit): opcode 2044 * 2045 * This opcode is meant to set NV_PFB_CFG0 (0x100200) appropriately so 2046 * that the hardware can correctly calculate how much VRAM it has 2047 * (and subsequently report that value in NV_PFB_CSTATUS (0x10020C)) 2048 * 2049 * The implementation of this opcode in general consists of two parts: 2050 * 1) determination of the memory bus width 2051 * 2) determination of how many of the card's RAM pads have ICs attached 2052 * 2053 * 1) is done by a cunning combination of writes to offsets 0x1c and 2054 * 0x3c in the framebuffer, and seeing whether the written values are 2055 * read back correctly. This then affects bits 4-7 of NV_PFB_CFG0 2056 * 2057 * 2) is done by a cunning combination of writes to an offset slightly 2058 * less than the maximum memory reported by NV_PFB_CSTATUS, then seeing 2059 * if the test pattern can be read back. This then affects bits 12-15 of 2060 * NV_PFB_CFG0 2061 * 2062 * In this context a "cunning combination" may include multiple reads 2063 * and writes to varying locations, often alternating the test pattern 2064 * and 0, doubtless to make sure buffers are filled, residual charges 2065 * on tracks are removed etc. 2066 * 2067 * Unfortunately, the "cunning combination"s mentioned above, and the 2068 * changes to the bits in NV_PFB_CFG0 differ with nearly every bios 2069 * trace I have. 2070 * 2071 * Therefore, we cheat and assume the value of NV_PFB_CFG0 with which 2072 * we started was correct, and use that instead 2073 */ 2074 2075 /* no iexec->execute check by design */ 2076 2077 /* 2078 * This appears to be a NOP on G8x chipsets, both io logs of the VBIOS 2079 * and kmmio traces of the binary driver POSTing the card show nothing 2080 * being done for this opcode. why is it still listed in the table?! 2081 */ 2082 2083 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2084 2085 if (dev_priv->card_type >= NV_40) 2086 return 1; 2087 2088 /* 2089 * On every card I've seen, this step gets done for us earlier in 2090 * the init scripts 2091 uint8_t crdata = bios_idxprt_rd(dev, NV_VIO_SRX, 0x01); 2092 bios_idxprt_wr(dev, NV_VIO_SRX, 0x01, crdata | 0x20); 2093 */ 2094 2095 /* 2096 * This also has probably been done in the scripts, but an mmio trace of 2097 * s3 resume shows nvidia doing it anyway (unlike the NV_VIO_SRX write) 2098 */ 2099 bios_wr32(bios, NV_PFB_REFCTRL, NV_PFB_REFCTRL_VALID_1); 2100 2101 /* write back the saved configuration value */ 2102 bios_wr32(bios, NV_PFB_CFG0, bios->state.saved_nv_pfb_cfg0); 2103 2104 return 1; 2105} 2106 2107static int 2108init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2109{ 2110 /* 2111 * INIT_RESET opcode: 0x65 ('e') 2112 * 2113 * offset (8 bit): opcode 2114 * offset + 1 (32 bit): register 2115 * offset + 5 (32 bit): value1 2116 * offset + 9 (32 bit): value2 2117 * 2118 * Assign "value1" to "register", then assign "value2" to "register" 2119 */ 2120 2121 uint32_t reg = ROM32(bios->data[offset + 1]); 2122 uint32_t value1 = ROM32(bios->data[offset + 5]); 2123 uint32_t value2 = ROM32(bios->data[offset + 9]); 2124 uint32_t pci_nv_19, pci_nv_20; 2125 2126 /* no iexec->execute check by design */ 2127 2128 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19); 2129 bios_wr32(bios, NV_PBUS_PCI_NV_19, 0); 2130 bios_wr32(bios, reg, value1); 2131 2132 udelay(10); 2133 2134 bios_wr32(bios, reg, value2); 2135 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19); 2136 2137 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20); 2138 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */ 2139 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20); 2140 2141 return 13; 2142} 2143 2144static int 2145init_configure_mem(struct nvbios *bios, uint16_t offset, 2146 struct init_exec *iexec) 2147{ 2148 /* 2149 * INIT_CONFIGURE_MEM opcode: 0x66 ('f') 2150 * 2151 * offset (8 bit): opcode 2152 * 2153 * Equivalent to INIT_DONE on bios version 3 or greater. 2154 * For early bios versions, sets up the memory registers, using values 2155 * taken from the memory init table 2156 */ 2157 2158 /* no iexec->execute check by design */ 2159 2160 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4); 2161 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6; 2162 uint32_t reg, data; 2163 2164 if (bios->major_version > 2) 2165 return -ENODEV; 2166 2167 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd( 2168 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20); 2169 2170 if (bios->data[meminitoffs] & 1) 2171 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr; 2172 2173 for (reg = ROM32(bios->data[seqtbloffs]); 2174 reg != 0xffffffff; 2175 reg = ROM32(bios->data[seqtbloffs += 4])) { 2176 2177 switch (reg) { 2178 case NV_PFB_PRE: 2179 data = NV_PFB_PRE_CMD_PRECHARGE; 2180 break; 2181 case NV_PFB_PAD: 2182 data = NV_PFB_PAD_CKE_NORMAL; 2183 break; 2184 case NV_PFB_REF: 2185 data = NV_PFB_REF_CMD_REFRESH; 2186 break; 2187 default: 2188 data = ROM32(bios->data[meminitdata]); 2189 meminitdata += 4; 2190 if (data == 0xffffffff) 2191 continue; 2192 } 2193 2194 bios_wr32(bios, reg, data); 2195 } 2196 2197 return 1; 2198} 2199 2200static int 2201init_configure_clk(struct nvbios *bios, uint16_t offset, 2202 struct init_exec *iexec) 2203{ 2204 /* 2205 * INIT_CONFIGURE_CLK opcode: 0x67 ('g') 2206 * 2207 * offset (8 bit): opcode 2208 * 2209 * Equivalent to INIT_DONE on bios version 3 or greater. 2210 * For early bios versions, sets up the NVClk and MClk PLLs, using 2211 * values taken from the memory init table 2212 */ 2213 2214 /* no iexec->execute check by design */ 2215 2216 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4); 2217 int clock; 2218 2219 if (bios->major_version > 2) 2220 return -ENODEV; 2221 2222 clock = ROM16(bios->data[meminitoffs + 4]) * 10; 2223 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock); 2224 2225 clock = ROM16(bios->data[meminitoffs + 2]) * 10; 2226 if (bios->data[meminitoffs] & 1) /* DDR */ 2227 clock *= 2; 2228 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock); 2229 2230 return 1; 2231} 2232 2233static int 2234init_configure_preinit(struct nvbios *bios, uint16_t offset, 2235 struct init_exec *iexec) 2236{ 2237 /* 2238 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h') 2239 * 2240 * offset (8 bit): opcode 2241 * 2242 * Equivalent to INIT_DONE on bios version 3 or greater. 2243 * For early bios versions, does early init, loading ram and crystal 2244 * configuration from straps into CR3C 2245 */ 2246 2247 /* no iexec->execute check by design */ 2248 2249 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0); 2250 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & (1 << 6)); 2251 2252 if (bios->major_version > 2) 2253 return -ENODEV; 2254 2255 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, 2256 NV_CIO_CRE_SCRATCH4__INDEX, cr3c); 2257 2258 return 1; 2259} 2260 2261static int 2262init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2263{ 2264 /* 2265 * INIT_IO opcode: 0x69 ('i') 2266 * 2267 * offset (8 bit): opcode 2268 * offset + 1 (16 bit): CRTC port 2269 * offset + 3 (8 bit): mask 2270 * offset + 4 (8 bit): data 2271 * 2272 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port" 2273 */ 2274 2275 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2276 uint16_t crtcport = ROM16(bios->data[offset + 1]); 2277 uint8_t mask = bios->data[offset + 3]; 2278 uint8_t data = bios->data[offset + 4]; 2279 2280 if (!iexec->execute) 2281 return 5; 2282 2283 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n", 2284 offset, crtcport, mask, data); 2285 2286 /* 2287 * I have no idea what this does, but NVIDIA do this magic sequence 2288 * in the places where this INIT_IO happens.. 2289 */ 2290 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) { 2291 int i; 2292 2293 bios_wr32(bios, 0x614100, (bios_rd32( 2294 bios, 0x614100) & 0x0fffffff) | 0x00800000); 2295 2296 bios_wr32(bios, 0x00e18c, bios_rd32( 2297 bios, 0x00e18c) | 0x00020000); 2298 2299 bios_wr32(bios, 0x614900, (bios_rd32( 2300 bios, 0x614900) & 0x0fffffff) | 0x00800000); 2301 2302 bios_wr32(bios, 0x000200, bios_rd32( 2303 bios, 0x000200) & ~0x40000000); 2304 2305 mdelay(10); 2306 2307 bios_wr32(bios, 0x00e18c, bios_rd32( 2308 bios, 0x00e18c) & ~0x00020000); 2309 2310 bios_wr32(bios, 0x000200, bios_rd32( 2311 bios, 0x000200) | 0x40000000); 2312 2313 bios_wr32(bios, 0x614100, 0x00800018); 2314 bios_wr32(bios, 0x614900, 0x00800018); 2315 2316 mdelay(10); 2317 2318 bios_wr32(bios, 0x614100, 0x10000018); 2319 bios_wr32(bios, 0x614900, 0x10000018); 2320 2321 for (i = 0; i < 3; i++) 2322 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32( 2323 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0); 2324 2325 for (i = 0; i < 2; i++) 2326 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32( 2327 bios, 0x614300 + (i*0x800)) & 0xfffff0f0); 2328 2329 for (i = 0; i < 3; i++) 2330 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32( 2331 bios, 0x614380 + (i*0x800)) & 0xfffff0f0); 2332 2333 for (i = 0; i < 2; i++) 2334 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32( 2335 bios, 0x614200 + (i*0x800)) & 0xfffffff0); 2336 2337 for (i = 0; i < 2; i++) 2338 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32( 2339 bios, 0x614108 + (i*0x800)) & 0x0fffffff); 2340 return 5; 2341 } 2342 2343 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) | 2344 data); 2345 return 5; 2346} 2347 2348static int 2349init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2350{ 2351 /* 2352 * INIT_SUB opcode: 0x6B ('k') 2353 * 2354 * offset (8 bit): opcode 2355 * offset + 1 (8 bit): script number 2356 * 2357 * Execute script number "script number", as a subroutine 2358 */ 2359 2360 uint8_t sub = bios->data[offset + 1]; 2361 2362 if (!iexec->execute) 2363 return 2; 2364 2365 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub); 2366 2367 parse_init_table(bios, 2368 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]), 2369 iexec); 2370 2371 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub); 2372 2373 return 2; 2374} 2375 2376static int 2377init_ram_condition(struct nvbios *bios, uint16_t offset, 2378 struct init_exec *iexec) 2379{ 2380 /* 2381 * INIT_RAM_CONDITION opcode: 0x6D ('m') 2382 * 2383 * offset (8 bit): opcode 2384 * offset + 1 (8 bit): mask 2385 * offset + 2 (8 bit): cmpval 2386 * 2387 * Test if (NV_PFB_BOOT_0 & "mask") equals "cmpval". 2388 * If condition not met skip subsequent opcodes until condition is 2389 * inverted (INIT_NOT), or we hit INIT_RESUME 2390 */ 2391 2392 uint8_t mask = bios->data[offset + 1]; 2393 uint8_t cmpval = bios->data[offset + 2]; 2394 uint8_t data; 2395 2396 if (!iexec->execute) 2397 return 3; 2398 2399 data = bios_rd32(bios, NV_PFB_BOOT_0) & mask; 2400 2401 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n", 2402 offset, data, cmpval); 2403 2404 if (data == cmpval) 2405 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 2406 else { 2407 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 2408 iexec->execute = false; 2409 } 2410 2411 return 3; 2412} 2413 2414static int 2415init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2416{ 2417 /* 2418 * INIT_NV_REG opcode: 0x6E ('n') 2419 * 2420 * offset (8 bit): opcode 2421 * offset + 1 (32 bit): register 2422 * offset + 5 (32 bit): mask 2423 * offset + 9 (32 bit): data 2424 * 2425 * Assign ((REGVAL("register") & "mask") | "data") to "register" 2426 */ 2427 2428 uint32_t reg = ROM32(bios->data[offset + 1]); 2429 uint32_t mask = ROM32(bios->data[offset + 5]); 2430 uint32_t data = ROM32(bios->data[offset + 9]); 2431 2432 if (!iexec->execute) 2433 return 13; 2434 2435 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n", 2436 offset, reg, mask, data); 2437 2438 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data); 2439 2440 return 13; 2441} 2442 2443static int 2444init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2445{ 2446 /* 2447 * INIT_MACRO opcode: 0x6F ('o') 2448 * 2449 * offset (8 bit): opcode 2450 * offset + 1 (8 bit): macro number 2451 * 2452 * Look up macro index "macro number" in the macro index table. 2453 * The macro index table entry has 1 byte for the index in the macro 2454 * table, and 1 byte for the number of times to repeat the macro. 2455 * The macro table entry has 4 bytes for the register address and 2456 * 4 bytes for the value to write to that register 2457 */ 2458 2459 uint8_t macro_index_tbl_idx = bios->data[offset + 1]; 2460 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE); 2461 uint8_t macro_tbl_idx = bios->data[tmp]; 2462 uint8_t count = bios->data[tmp + 1]; 2463 uint32_t reg, data; 2464 int i; 2465 2466 if (!iexec->execute) 2467 return 2; 2468 2469 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, " 2470 "Count: 0x%02X\n", 2471 offset, macro_index_tbl_idx, macro_tbl_idx, count); 2472 2473 for (i = 0; i < count; i++) { 2474 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE; 2475 2476 reg = ROM32(bios->data[macroentryptr]); 2477 data = ROM32(bios->data[macroentryptr + 4]); 2478 2479 bios_wr32(bios, reg, data); 2480 } 2481 2482 return 2; 2483} 2484 2485static int 2486init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2487{ 2488 /* 2489 * INIT_DONE opcode: 0x71 ('q') 2490 * 2491 * offset (8 bit): opcode 2492 * 2493 * End the current script 2494 */ 2495 2496 /* mild retval abuse to stop parsing this table */ 2497 return 0; 2498} 2499 2500static int 2501init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2502{ 2503 /* 2504 * INIT_RESUME opcode: 0x72 ('r') 2505 * 2506 * offset (8 bit): opcode 2507 * 2508 * End the current execute / no-execute condition 2509 */ 2510 2511 if (iexec->execute) 2512 return 1; 2513 2514 iexec->execute = true; 2515 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset); 2516 2517 return 1; 2518} 2519 2520static int 2521init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2522{ 2523 /* 2524 * INIT_TIME opcode: 0x74 ('t') 2525 * 2526 * offset (8 bit): opcode 2527 * offset + 1 (16 bit): time 2528 * 2529 * Sleep for "time" microseconds. 2530 */ 2531 2532 unsigned time = ROM16(bios->data[offset + 1]); 2533 2534 if (!iexec->execute) 2535 return 3; 2536 2537 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n", 2538 offset, time); 2539 2540 if (time < 1000) 2541 udelay(time); 2542 else 2543 msleep((time + 900) / 1000); 2544 2545 return 3; 2546} 2547 2548static int 2549init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2550{ 2551 /* 2552 * INIT_CONDITION opcode: 0x75 ('u') 2553 * 2554 * offset (8 bit): opcode 2555 * offset + 1 (8 bit): condition number 2556 * 2557 * Check condition "condition number" in the condition table. 2558 * If condition not met skip subsequent opcodes until condition is 2559 * inverted (INIT_NOT), or we hit INIT_RESUME 2560 */ 2561 2562 uint8_t cond = bios->data[offset + 1]; 2563 2564 if (!iexec->execute) 2565 return 2; 2566 2567 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond); 2568 2569 if (bios_condition_met(bios, offset, cond)) 2570 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 2571 else { 2572 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 2573 iexec->execute = false; 2574 } 2575 2576 return 2; 2577} 2578 2579static int 2580init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2581{ 2582 /* 2583 * INIT_IO_CONDITION opcode: 0x76 2584 * 2585 * offset (8 bit): opcode 2586 * offset + 1 (8 bit): condition number 2587 * 2588 * Check condition "condition number" in the io condition table. 2589 * If condition not met skip subsequent opcodes until condition is 2590 * inverted (INIT_NOT), or we hit INIT_RESUME 2591 */ 2592 2593 uint8_t cond = bios->data[offset + 1]; 2594 2595 if (!iexec->execute) 2596 return 2; 2597 2598 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond); 2599 2600 if (io_condition_met(bios, offset, cond)) 2601 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 2602 else { 2603 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 2604 iexec->execute = false; 2605 } 2606 2607 return 2; 2608} 2609 2610static int 2611init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2612{ 2613 /* 2614 * INIT_INDEX_IO opcode: 0x78 ('x') 2615 * 2616 * offset (8 bit): opcode 2617 * offset + 1 (16 bit): CRTC port 2618 * offset + 3 (8 bit): CRTC index 2619 * offset + 4 (8 bit): mask 2620 * offset + 5 (8 bit): data 2621 * 2622 * Read value at index "CRTC index" on "CRTC port", AND with "mask", 2623 * OR with "data", write-back 2624 */ 2625 2626 uint16_t crtcport = ROM16(bios->data[offset + 1]); 2627 uint8_t crtcindex = bios->data[offset + 3]; 2628 uint8_t mask = bios->data[offset + 4]; 2629 uint8_t data = bios->data[offset + 5]; 2630 uint8_t value; 2631 2632 if (!iexec->execute) 2633 return 6; 2634 2635 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 2636 "Data: 0x%02X\n", 2637 offset, crtcport, crtcindex, mask, data); 2638 2639 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data; 2640 bios_idxprt_wr(bios, crtcport, crtcindex, value); 2641 2642 return 6; 2643} 2644 2645static int 2646init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2647{ 2648 /* 2649 * INIT_PLL opcode: 0x79 ('y') 2650 * 2651 * offset (8 bit): opcode 2652 * offset + 1 (32 bit): register 2653 * offset + 5 (16 bit): freq 2654 * 2655 * Set PLL register "register" to coefficients for frequency (10kHz) 2656 * "freq" 2657 */ 2658 2659 uint32_t reg = ROM32(bios->data[offset + 1]); 2660 uint16_t freq = ROM16(bios->data[offset + 5]); 2661 2662 if (!iexec->execute) 2663 return 7; 2664 2665 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq); 2666 2667 setPLL(bios, reg, freq * 10); 2668 2669 return 7; 2670} 2671 2672static int 2673init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2674{ 2675 /* 2676 * INIT_ZM_REG opcode: 0x7A ('z') 2677 * 2678 * offset (8 bit): opcode 2679 * offset + 1 (32 bit): register 2680 * offset + 5 (32 bit): value 2681 * 2682 * Assign "value" to "register" 2683 */ 2684 2685 uint32_t reg = ROM32(bios->data[offset + 1]); 2686 uint32_t value = ROM32(bios->data[offset + 5]); 2687 2688 if (!iexec->execute) 2689 return 9; 2690 2691 if (reg == 0x000200) 2692 value |= 1; 2693 2694 bios_wr32(bios, reg, value); 2695 2696 return 9; 2697} 2698 2699static int 2700init_ram_restrict_pll(struct nvbios *bios, uint16_t offset, 2701 struct init_exec *iexec) 2702{ 2703 /* 2704 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('') 2705 * 2706 * offset (8 bit): opcode 2707 * offset + 1 (8 bit): PLL type 2708 * offset + 2 (32 bit): frequency 0 2709 * 2710 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at 2711 * ram_restrict_table_ptr. The value read from there is used to select 2712 * a frequency from the table starting at 'frequency 0' to be 2713 * programmed into the PLL corresponding to 'type'. 2714 * 2715 * The PLL limits table on cards using this opcode has a mapping of 2716 * 'type' to the relevant registers. 2717 */ 2718 2719 struct drm_device *dev = bios->dev; 2720 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2; 2721 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap]; 2722 uint8_t type = bios->data[offset + 1]; 2723 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]); 2724 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry; 2725 int len = 2 + bios->ram_restrict_group_count * 4; 2726 int i; 2727 2728 if (!iexec->execute) 2729 return len; 2730 2731 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) { 2732 NV_ERROR(dev, "PLL limits table not version 3.x\n"); 2733 return len; /* deliberate, allow default clocks to remain */ 2734 } 2735 2736 entry = pll_limits + pll_limits[1]; 2737 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) { 2738 if (entry[0] == type) { 2739 uint32_t reg = ROM32(entry[3]); 2740 2741 BIOSLOG(bios, "0x%04X: " 2742 "Type %02x Reg 0x%08x Freq %dKHz\n", 2743 offset, type, reg, freq); 2744 2745 setPLL(bios, reg, freq); 2746 return len; 2747 } 2748 } 2749 2750 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type); 2751 return len; 2752} 2753 2754static int 2755init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2756{ 2757 /* 2758 * INIT_8C opcode: 0x8C ('') 2759 * 2760 * NOP so far.... 2761 * 2762 */ 2763 2764 return 1; 2765} 2766 2767static int 2768init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2769{ 2770 /* 2771 * INIT_8D opcode: 0x8D ('') 2772 * 2773 * NOP so far.... 2774 * 2775 */ 2776 2777 return 1; 2778} 2779 2780static int 2781init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2782{ 2783 /* 2784 * INIT_GPIO opcode: 0x8E ('') 2785 * 2786 * offset (8 bit): opcode 2787 * 2788 * Loop over all entries in the DCB GPIO table, and initialise 2789 * each GPIO according to various values listed in each entry 2790 */ 2791 2792 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2793 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c }; 2794 int i; 2795 2796 if (dev_priv->card_type != NV_50) { 2797 NV_ERROR(bios->dev, "INIT_GPIO on unsupported chipset\n"); 2798 return -ENODEV; 2799 } 2800 2801 if (!iexec->execute) 2802 return 1; 2803 2804 for (i = 0; i < bios->dcb.gpio.entries; i++) { 2805 struct dcb_gpio_entry *gpio = &bios->dcb.gpio.entry[i]; 2806 uint32_t r, s, v; 2807 2808 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, gpio->entry); 2809 2810 nv50_gpio_set(bios->dev, gpio->tag, gpio->state_default); 2811 2812 /* The NVIDIA binary driver doesn't appear to actually do 2813 * any of this, my VBIOS does however. 2814 */ 2815 /* Not a clue, needs de-magicing */ 2816 r = nv50_gpio_ctl[gpio->line >> 4]; 2817 s = (gpio->line & 0x0f); 2818 v = bios_rd32(bios, r) & ~(0x00010001 << s); 2819 switch ((gpio->entry & 0x06000000) >> 25) { 2820 case 1: 2821 v |= (0x00000001 << s); 2822 break; 2823 case 2: 2824 v |= (0x00010000 << s); 2825 break; 2826 default: 2827 break; 2828 } 2829 bios_wr32(bios, r, v); 2830 } 2831 2832 return 1; 2833} 2834 2835static int 2836init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset, 2837 struct init_exec *iexec) 2838{ 2839 /* 2840 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('') 2841 * 2842 * offset (8 bit): opcode 2843 * offset + 1 (32 bit): reg 2844 * offset + 5 (8 bit): regincrement 2845 * offset + 6 (8 bit): count 2846 * offset + 7 (32 bit): value 1,1 2847 * ... 2848 * 2849 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at 2850 * ram_restrict_table_ptr. The value read from here is 'n', and 2851 * "value 1,n" gets written to "reg". This repeats "count" times and on 2852 * each iteration 'm', "reg" increases by "regincrement" and 2853 * "value m,n" is used. The extent of n is limited by a number read 2854 * from the 'M' BIT table, herein called "blocklen" 2855 */ 2856 2857 uint32_t reg = ROM32(bios->data[offset + 1]); 2858 uint8_t regincrement = bios->data[offset + 5]; 2859 uint8_t count = bios->data[offset + 6]; 2860 uint32_t strap_ramcfg, data; 2861 /* previously set by 'M' BIT table */ 2862 uint16_t blocklen = bios->ram_restrict_group_count * 4; 2863 int len = 7 + count * blocklen; 2864 uint8_t index; 2865 int i; 2866 2867 2868 if (!iexec->execute) 2869 return len; 2870 2871 if (!blocklen) { 2872 NV_ERROR(bios->dev, 2873 "0x%04X: Zero block length - has the M table " 2874 "been parsed?\n", offset); 2875 return -EINVAL; 2876 } 2877 2878 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf; 2879 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg]; 2880 2881 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, " 2882 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n", 2883 offset, reg, regincrement, count, strap_ramcfg, index); 2884 2885 for (i = 0; i < count; i++) { 2886 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]); 2887 2888 bios_wr32(bios, reg, data); 2889 2890 reg += regincrement; 2891 } 2892 2893 return len; 2894} 2895 2896static int 2897init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2898{ 2899 /* 2900 * INIT_COPY_ZM_REG opcode: 0x90 ('') 2901 * 2902 * offset (8 bit): opcode 2903 * offset + 1 (32 bit): src reg 2904 * offset + 5 (32 bit): dst reg 2905 * 2906 * Put contents of "src reg" into "dst reg" 2907 */ 2908 2909 uint32_t srcreg = ROM32(bios->data[offset + 1]); 2910 uint32_t dstreg = ROM32(bios->data[offset + 5]); 2911 2912 if (!iexec->execute) 2913 return 9; 2914 2915 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg)); 2916 2917 return 9; 2918} 2919 2920static int 2921init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset, 2922 struct init_exec *iexec) 2923{ 2924 /* 2925 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('') 2926 * 2927 * offset (8 bit): opcode 2928 * offset + 1 (32 bit): dst reg 2929 * offset + 5 (8 bit): count 2930 * offset + 6 (32 bit): data 1 2931 * ... 2932 * 2933 * For each of "count" values write "data n" to "dst reg" 2934 */ 2935 2936 uint32_t reg = ROM32(bios->data[offset + 1]); 2937 uint8_t count = bios->data[offset + 5]; 2938 int len = 6 + count * 4; 2939 int i; 2940 2941 if (!iexec->execute) 2942 return len; 2943 2944 for (i = 0; i < count; i++) { 2945 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]); 2946 bios_wr32(bios, reg, data); 2947 } 2948 2949 return len; 2950} 2951 2952static int 2953init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2954{ 2955 /* 2956 * INIT_RESERVED opcode: 0x92 ('') 2957 * 2958 * offset (8 bit): opcode 2959 * 2960 * Seemingly does nothing 2961 */ 2962 2963 return 1; 2964} 2965 2966static int 2967init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2968{ 2969 /* 2970 * INIT_96 opcode: 0x96 ('') 2971 * 2972 * offset (8 bit): opcode 2973 * offset + 1 (32 bit): sreg 2974 * offset + 5 (8 bit): sshift 2975 * offset + 6 (8 bit): smask 2976 * offset + 7 (8 bit): index 2977 * offset + 8 (32 bit): reg 2978 * offset + 12 (32 bit): mask 2979 * offset + 16 (8 bit): shift 2980 * 2981 */ 2982 2983 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2); 2984 uint32_t reg = ROM32(bios->data[offset + 8]); 2985 uint32_t mask = ROM32(bios->data[offset + 12]); 2986 uint32_t val; 2987 2988 val = bios_rd32(bios, ROM32(bios->data[offset + 1])); 2989 if (bios->data[offset + 5] < 0x80) 2990 val >>= bios->data[offset + 5]; 2991 else 2992 val <<= (0x100 - bios->data[offset + 5]); 2993 val &= bios->data[offset + 6]; 2994 2995 val = bios->data[ROM16(bios->data[xlatptr]) + val]; 2996 val <<= bios->data[offset + 16]; 2997 2998 if (!iexec->execute) 2999 return 17; 3000 3001 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val); 3002 return 17; 3003} 3004 3005static int 3006init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3007{ 3008 /* 3009 * INIT_97 opcode: 0x97 ('') 3010 * 3011 * offset (8 bit): opcode 3012 * offset + 1 (32 bit): register 3013 * offset + 5 (32 bit): mask 3014 * offset + 9 (32 bit): value 3015 * 3016 * Adds "value" to "register" preserving the fields specified 3017 * by "mask" 3018 */ 3019 3020 uint32_t reg = ROM32(bios->data[offset + 1]); 3021 uint32_t mask = ROM32(bios->data[offset + 5]); 3022 uint32_t add = ROM32(bios->data[offset + 9]); 3023 uint32_t val; 3024 3025 val = bios_rd32(bios, reg); 3026 val = (val & mask) | ((val + add) & ~mask); 3027 3028 if (!iexec->execute) 3029 return 13; 3030 3031 bios_wr32(bios, reg, val); 3032 return 13; 3033} 3034 3035static int 3036init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3037{ 3038 /* 3039 * INIT_AUXCH opcode: 0x98 ('') 3040 * 3041 * offset (8 bit): opcode 3042 * offset + 1 (32 bit): address 3043 * offset + 5 (8 bit): count 3044 * offset + 6 (8 bit): mask 0 3045 * offset + 7 (8 bit): data 0 3046 * ... 3047 * 3048 */ 3049 3050 struct drm_device *dev = bios->dev; 3051 struct nouveau_i2c_chan *auxch; 3052 uint32_t addr = ROM32(bios->data[offset + 1]); 3053 uint8_t count = bios->data[offset + 5]; 3054 int len = 6 + count * 2; 3055 int ret, i; 3056 3057 if (!bios->display.output) { 3058 NV_ERROR(dev, "INIT_AUXCH: no active output\n"); 3059 return -EINVAL; 3060 } 3061 3062 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index); 3063 if (!auxch) { 3064 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n", 3065 bios->display.output->i2c_index); 3066 return -ENODEV; 3067 } 3068 3069 if (!iexec->execute) 3070 return len; 3071 3072 offset += 6; 3073 for (i = 0; i < count; i++, offset += 2) { 3074 uint8_t data; 3075 3076 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1); 3077 if (ret) { 3078 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret); 3079 return ret; 3080 } 3081 3082 data &= bios->data[offset + 0]; 3083 data |= bios->data[offset + 1]; 3084 3085 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1); 3086 if (ret) { 3087 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret); 3088 return ret; 3089 } 3090 } 3091 3092 return len; 3093} 3094 3095static int 3096init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3097{ 3098 /* 3099 * INIT_ZM_AUXCH opcode: 0x99 ('') 3100 * 3101 * offset (8 bit): opcode 3102 * offset + 1 (32 bit): address 3103 * offset + 5 (8 bit): count 3104 * offset + 6 (8 bit): data 0 3105 * ... 3106 * 3107 */ 3108 3109 struct drm_device *dev = bios->dev; 3110 struct nouveau_i2c_chan *auxch; 3111 uint32_t addr = ROM32(bios->data[offset + 1]); 3112 uint8_t count = bios->data[offset + 5]; 3113 int len = 6 + count; 3114 int ret, i; 3115 3116 if (!bios->display.output) { 3117 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n"); 3118 return -EINVAL; 3119 } 3120 3121 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index); 3122 if (!auxch) { 3123 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n", 3124 bios->display.output->i2c_index); 3125 return -ENODEV; 3126 } 3127 3128 if (!iexec->execute) 3129 return len; 3130 3131 offset += 6; 3132 for (i = 0; i < count; i++, offset++) { 3133 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1); 3134 if (ret) { 3135 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret); 3136 return ret; 3137 } 3138 } 3139 3140 return len; 3141} 3142 3143static struct init_tbl_entry itbl_entry[] = { 3144 /* command name , id , length , offset , mult , command handler */ 3145 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */ 3146 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog }, 3147 { "INIT_REPEAT" , 0x33, init_repeat }, 3148 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll }, 3149 { "INIT_END_REPEAT" , 0x36, init_end_repeat }, 3150 { "INIT_COPY" , 0x37, init_copy }, 3151 { "INIT_NOT" , 0x38, init_not }, 3152 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition }, 3153 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition }, 3154 { "INIT_OP_3B" , 0x3B, init_op_3b }, 3155 { "INIT_OP_3C" , 0x3C, init_op_3c }, 3156 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched }, 3157 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 }, 3158 { "INIT_PLL2" , 0x4B, init_pll2 }, 3159 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte }, 3160 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte }, 3161 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c }, 3162 { "INIT_TMDS" , 0x4F, init_tmds }, 3163 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group }, 3164 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch }, 3165 { "INIT_CR" , 0x52, init_cr }, 3166 { "INIT_ZM_CR" , 0x53, init_zm_cr }, 3167 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group }, 3168 { "INIT_CONDITION_TIME" , 0x56, init_condition_time }, 3169 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence }, 3170 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */ 3171 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct }, 3172 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg }, 3173 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io }, 3174 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem }, 3175 { "INIT_RESET" , 0x65, init_reset }, 3176 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem }, 3177 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk }, 3178 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit }, 3179 { "INIT_IO" , 0x69, init_io }, 3180 { "INIT_SUB" , 0x6B, init_sub }, 3181 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition }, 3182 { "INIT_NV_REG" , 0x6E, init_nv_reg }, 3183 { "INIT_MACRO" , 0x6F, init_macro }, 3184 { "INIT_DONE" , 0x71, init_done }, 3185 { "INIT_RESUME" , 0x72, init_resume }, 3186 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */ 3187 { "INIT_TIME" , 0x74, init_time }, 3188 { "INIT_CONDITION" , 0x75, init_condition }, 3189 { "INIT_IO_CONDITION" , 0x76, init_io_condition }, 3190 { "INIT_INDEX_IO" , 0x78, init_index_io }, 3191 { "INIT_PLL" , 0x79, init_pll }, 3192 { "INIT_ZM_REG" , 0x7A, init_zm_reg }, 3193 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll }, 3194 { "INIT_8C" , 0x8C, init_8c }, 3195 { "INIT_8D" , 0x8D, init_8d }, 3196 { "INIT_GPIO" , 0x8E, init_gpio }, 3197 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group }, 3198 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg }, 3199 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched }, 3200 { "INIT_RESERVED" , 0x92, init_reserved }, 3201 { "INIT_96" , 0x96, init_96 }, 3202 { "INIT_97" , 0x97, init_97 }, 3203 { "INIT_AUXCH" , 0x98, init_auxch }, 3204 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch }, 3205 { NULL , 0 , NULL } 3206}; 3207 3208#define MAX_TABLE_OPS 1000 3209 3210static int 3211parse_init_table(struct nvbios *bios, unsigned int offset, 3212 struct init_exec *iexec) 3213{ 3214 /* 3215 * Parses all commands in an init table. 3216 * 3217 * We start out executing all commands found in the init table. Some 3218 * opcodes may change the status of iexec->execute to SKIP, which will 3219 * cause the following opcodes to perform no operation until the value 3220 * is changed back to EXECUTE. 3221 */ 3222 3223 int count = 0, i, ret; 3224 uint8_t id; 3225 3226 /* 3227 * Loop until INIT_DONE causes us to break out of the loop 3228 * (or until offset > bios length just in case... ) 3229 * (and no more than MAX_TABLE_OPS iterations, just in case... ) 3230 */ 3231 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) { 3232 id = bios->data[offset]; 3233 3234 /* Find matching id in itbl_entry */ 3235 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++) 3236 ; 3237 3238 if (!itbl_entry[i].name) { 3239 NV_ERROR(bios->dev, 3240 "0x%04X: Init table command not found: " 3241 "0x%02X\n", offset, id); 3242 return -ENOENT; 3243 } 3244 3245 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset, 3246 itbl_entry[i].id, itbl_entry[i].name); 3247 3248 /* execute eventual command handler */ 3249 ret = (*itbl_entry[i].handler)(bios, offset, iexec); 3250 if (ret < 0) { 3251 NV_ERROR(bios->dev, "0x%04X: Failed parsing init " 3252 "table opcode: %s %d\n", offset, 3253 itbl_entry[i].name, ret); 3254 } 3255 3256 if (ret <= 0) 3257 break; 3258 3259 /* 3260 * Add the offset of the current command including all data 3261 * of that command. The offset will then be pointing on the 3262 * next op code. 3263 */ 3264 offset += ret; 3265 } 3266 3267 if (offset >= bios->length) 3268 NV_WARN(bios->dev, 3269 "Offset 0x%04X greater than known bios image length. " 3270 "Corrupt image?\n", offset); 3271 if (count >= MAX_TABLE_OPS) 3272 NV_WARN(bios->dev, 3273 "More than %d opcodes to a table is unlikely, " 3274 "is the bios image corrupt?\n", MAX_TABLE_OPS); 3275 3276 return 0; 3277} 3278 3279static void 3280parse_init_tables(struct nvbios *bios) 3281{ 3282 /* Loops and calls parse_init_table() for each present table. */ 3283 3284 int i = 0; 3285 uint16_t table; 3286 struct init_exec iexec = {true, false}; 3287 3288 if (bios->old_style_init) { 3289 if (bios->init_script_tbls_ptr) 3290 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec); 3291 if (bios->extra_init_script_tbl_ptr) 3292 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec); 3293 3294 return; 3295 } 3296 3297 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) { 3298 NV_INFO(bios->dev, 3299 "Parsing VBIOS init table %d at offset 0x%04X\n", 3300 i / 2, table); 3301 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table); 3302 3303 parse_init_table(bios, table, &iexec); 3304 i += 2; 3305 } 3306} 3307 3308static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk) 3309{ 3310 int compare_record_len, i = 0; 3311 uint16_t compareclk, scriptptr = 0; 3312 3313 if (bios->major_version < 5) /* pre BIT */ 3314 compare_record_len = 3; 3315 else 3316 compare_record_len = 4; 3317 3318 do { 3319 compareclk = ROM16(bios->data[clktable + compare_record_len * i]); 3320 if (pxclk >= compareclk * 10) { 3321 if (bios->major_version < 5) { 3322 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i]; 3323 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]); 3324 } else 3325 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]); 3326 break; 3327 } 3328 i++; 3329 } while (compareclk); 3330 3331 return scriptptr; 3332} 3333 3334static void 3335run_digital_op_script(struct drm_device *dev, uint16_t scriptptr, 3336 struct dcb_entry *dcbent, int head, bool dl) 3337{ 3338 struct drm_nouveau_private *dev_priv = dev->dev_private; 3339 struct nvbios *bios = &dev_priv->vbios; 3340 struct init_exec iexec = {true, false}; 3341 3342 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n", 3343 scriptptr); 3344 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44, 3345 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA); 3346 /* note: if dcb entries have been merged, index may be misleading */ 3347 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index); 3348 parse_init_table(bios, scriptptr, &iexec); 3349 3350 nv04_dfp_bind_head(dev, dcbent, head, dl); 3351} 3352 3353static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script) 3354{ 3355 struct drm_nouveau_private *dev_priv = dev->dev_private; 3356 struct nvbios *bios = &dev_priv->vbios; 3357 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0); 3358 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]); 3359 3360 if (!bios->fp.xlated_entry || !sub || !scriptofs) 3361 return -EINVAL; 3362 3363 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link); 3364 3365 if (script == LVDS_PANEL_OFF) { 3366 /* off-on delay in ms */ 3367 msleep(ROM16(bios->data[bios->fp.xlated_entry + 7])); 3368 } 3369#ifdef __powerpc__ 3370 /* Powerbook specific quirks */ 3371 if ((dev->pci_device & 0xffff) == 0x0179 || 3372 (dev->pci_device & 0xffff) == 0x0189 || 3373 (dev->pci_device & 0xffff) == 0x0329) { 3374 if (script == LVDS_RESET) { 3375 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72); 3376 3377 } else if (script == LVDS_PANEL_ON) { 3378 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL, 3379 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL) 3380 | (1 << 31)); 3381 bios_wr32(bios, NV_PCRTC_GPIO_EXT, 3382 bios_rd32(bios, NV_PCRTC_GPIO_EXT) | 1); 3383 3384 } else if (script == LVDS_PANEL_OFF) { 3385 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL, 3386 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL) 3387 & ~(1 << 31)); 3388 bios_wr32(bios, NV_PCRTC_GPIO_EXT, 3389 bios_rd32(bios, NV_PCRTC_GPIO_EXT) & ~3); 3390 } 3391 } 3392#endif 3393 3394 return 0; 3395} 3396 3397static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk) 3398{ 3399 /* 3400 * The BIT LVDS table's header has the information to setup the 3401 * necessary registers. Following the standard 4 byte header are: 3402 * A bitmask byte and a dual-link transition pxclk value for use in 3403 * selecting the init script when not using straps; 4 script pointers 3404 * for panel power, selected by output and on/off; and 8 table pointers 3405 * for panel init, the needed one determined by output, and bits in the 3406 * conf byte. These tables are similar to the TMDS tables, consisting 3407 * of a list of pxclks and script pointers. 3408 */ 3409 struct drm_nouveau_private *dev_priv = dev->dev_private; 3410 struct nvbios *bios = &dev_priv->vbios; 3411 unsigned int outputset = (dcbent->or == 4) ? 1 : 0; 3412 uint16_t scriptptr = 0, clktable; 3413 3414 /* 3415 * For now we assume version 3.0 table - g80 support will need some 3416 * changes 3417 */ 3418 3419 switch (script) { 3420 case LVDS_INIT: 3421 return -ENOSYS; 3422 case LVDS_BACKLIGHT_ON: 3423 case LVDS_PANEL_ON: 3424 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]); 3425 break; 3426 case LVDS_BACKLIGHT_OFF: 3427 case LVDS_PANEL_OFF: 3428 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]); 3429 break; 3430 case LVDS_RESET: 3431 clktable = bios->fp.lvdsmanufacturerpointer + 15; 3432 if (dcbent->or == 4) 3433 clktable += 8; 3434 3435 if (dcbent->lvdsconf.use_straps_for_mode) { 3436 if (bios->fp.dual_link) 3437 clktable += 4; 3438 if (bios->fp.if_is_24bit) 3439 clktable += 2; 3440 } else { 3441 /* using EDID */ 3442 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1; 3443 3444 if (bios->fp.dual_link) { 3445 clktable += 4; 3446 cmpval_24bit <<= 1; 3447 } 3448 3449 if (bios->fp.strapless_is_24bit & cmpval_24bit) 3450 clktable += 2; 3451 } 3452 3453 clktable = ROM16(bios->data[clktable]); 3454 if (!clktable) { 3455 NV_ERROR(dev, "Pixel clock comparison table not found\n"); 3456 return -ENOENT; 3457 } 3458 scriptptr = clkcmptable(bios, clktable, pxclk); 3459 } 3460 3461 if (!scriptptr) { 3462 NV_ERROR(dev, "LVDS output init script not found\n"); 3463 return -ENOENT; 3464 } 3465 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link); 3466 3467 return 0; 3468} 3469 3470int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk) 3471{ 3472 /* 3473 * LVDS operations are multiplexed in an effort to present a single API 3474 * which works with two vastly differing underlying structures. 3475 * This acts as the demux 3476 */ 3477 3478 struct drm_nouveau_private *dev_priv = dev->dev_private; 3479 struct nvbios *bios = &dev_priv->vbios; 3480 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer]; 3481 uint32_t sel_clk_binding, sel_clk; 3482 int ret; 3483 3484 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver || 3485 (lvds_ver >= 0x30 && script == LVDS_INIT)) 3486 return 0; 3487 3488 if (!bios->fp.lvds_init_run) { 3489 bios->fp.lvds_init_run = true; 3490 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk); 3491 } 3492 3493 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change) 3494 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk); 3495 if (script == LVDS_RESET && bios->fp.power_off_for_reset) 3496 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk); 3497 3498 NV_TRACE(dev, "Calling LVDS script %d:\n", script); 3499 3500 /* don't let script change pll->head binding */ 3501 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000; 3502 3503 if (lvds_ver < 0x30) 3504 ret = call_lvds_manufacturer_script(dev, dcbent, head, script); 3505 else 3506 ret = run_lvds_table(dev, dcbent, head, script, pxclk); 3507 3508 bios->fp.last_script_invoc = (script << 1 | head); 3509 3510 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; 3511 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); 3512 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */ 3513 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0); 3514 3515 return ret; 3516} 3517 3518struct lvdstableheader { 3519 uint8_t lvds_ver, headerlen, recordlen; 3520}; 3521 3522static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth) 3523{ 3524 /* 3525 * BMP version (0xa) LVDS table has a simple header of version and 3526 * record length. The BIT LVDS table has the typical BIT table header: 3527 * version byte, header length byte, record length byte, and a byte for 3528 * the maximum number of records that can be held in the table. 3529 */ 3530 3531 uint8_t lvds_ver, headerlen, recordlen; 3532 3533 memset(lth, 0, sizeof(struct lvdstableheader)); 3534 3535 if (bios->fp.lvdsmanufacturerpointer == 0x0) { 3536 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n"); 3537 return -EINVAL; 3538 } 3539 3540 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer]; 3541 3542 switch (lvds_ver) { 3543 case 0x0a: /* pre NV40 */ 3544 headerlen = 2; 3545 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 3546 break; 3547 case 0x30: /* NV4x */ 3548 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 3549 if (headerlen < 0x1f) { 3550 NV_ERROR(dev, "LVDS table header not understood\n"); 3551 return -EINVAL; 3552 } 3553 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2]; 3554 break; 3555 case 0x40: /* G80/G90 */ 3556 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 3557 if (headerlen < 0x7) { 3558 NV_ERROR(dev, "LVDS table header not understood\n"); 3559 return -EINVAL; 3560 } 3561 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2]; 3562 break; 3563 default: 3564 NV_ERROR(dev, 3565 "LVDS table revision %d.%d not currently supported\n", 3566 lvds_ver >> 4, lvds_ver & 0xf); 3567 return -ENOSYS; 3568 } 3569 3570 lth->lvds_ver = lvds_ver; 3571 lth->headerlen = headerlen; 3572 lth->recordlen = recordlen; 3573 3574 return 0; 3575} 3576 3577static int 3578get_fp_strap(struct drm_device *dev, struct nvbios *bios) 3579{ 3580 struct drm_nouveau_private *dev_priv = dev->dev_private; 3581 3582 /* 3583 * The fp strap is normally dictated by the "User Strap" in 3584 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the 3585 * Internal_Flags struct at 0x48 is set, the user strap gets overriden 3586 * by the PCI subsystem ID during POST, but not before the previous user 3587 * strap has been committed to CR58 for CR57=0xf on head A, which may be 3588 * read and used instead 3589 */ 3590 3591 if (bios->major_version < 5 && bios->data[0x48] & 0x4) 3592 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf; 3593 3594 if (dev_priv->card_type >= NV_50) 3595 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf; 3596 else 3597 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf; 3598} 3599 3600static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios) 3601{ 3602 uint8_t *fptable; 3603 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex; 3604 int ret, ofs, fpstrapping; 3605 struct lvdstableheader lth; 3606 3607 if (bios->fp.fptablepointer == 0x0) { 3608 /* Apple cards don't have the fp table; the laptops use DDC */ 3609 /* The table is also missing on some x86 IGPs */ 3610#ifndef __powerpc__ 3611 NV_ERROR(dev, "Pointer to flat panel table invalid\n"); 3612#endif 3613 bios->digital_min_front_porch = 0x4b; 3614 return 0; 3615 } 3616 3617 fptable = &bios->data[bios->fp.fptablepointer]; 3618 fptable_ver = fptable[0]; 3619 3620 switch (fptable_ver) { 3621 /* 3622 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no 3623 * version field, and miss one of the spread spectrum/PWM bytes. 3624 * This could affect early GF2Go parts (not seen any appropriate ROMs 3625 * though). Here we assume that a version of 0x05 matches this case 3626 * (combining with a BMP version check would be better), as the 3627 * common case for the panel type field is 0x0005, and that is in 3628 * fact what we are reading the first byte of. 3629 */ 3630 case 0x05: /* some NV10, 11, 15, 16 */ 3631 recordlen = 42; 3632 ofs = -1; 3633 break; 3634 case 0x10: /* some NV15/16, and NV11+ */ 3635 recordlen = 44; 3636 ofs = 0; 3637 break; 3638 case 0x20: /* NV40+ */ 3639 headerlen = fptable[1]; 3640 recordlen = fptable[2]; 3641 fpentries = fptable[3]; 3642 /* 3643 * fptable[4] is the minimum 3644 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap 3645 */ 3646 bios->digital_min_front_porch = fptable[4]; 3647 ofs = -7; 3648 break; 3649 default: 3650 NV_ERROR(dev, 3651 "FP table revision %d.%d not currently supported\n", 3652 fptable_ver >> 4, fptable_ver & 0xf); 3653 return -ENOSYS; 3654 } 3655 3656 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */ 3657 return 0; 3658 3659 ret = parse_lvds_manufacturer_table_header(dev, bios, <h); 3660 if (ret) 3661 return ret; 3662 3663 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) { 3664 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer + 3665 lth.headerlen + 1; 3666 bios->fp.xlatwidth = lth.recordlen; 3667 } 3668 if (bios->fp.fpxlatetableptr == 0x0) { 3669 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n"); 3670 return -EINVAL; 3671 } 3672 3673 fpstrapping = get_fp_strap(dev, bios); 3674 3675 fpindex = bios->data[bios->fp.fpxlatetableptr + 3676 fpstrapping * bios->fp.xlatwidth]; 3677 3678 if (fpindex > fpentries) { 3679 NV_ERROR(dev, "Bad flat panel table index\n"); 3680 return -ENOENT; 3681 } 3682 3683 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */ 3684 if (lth.lvds_ver > 0x10) 3685 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf; 3686 3687 /* 3688 * If either the strap or xlated fpindex value are 0xf there is no 3689 * panel using a strap-derived bios mode present. this condition 3690 * includes, but is different from, the DDC panel indicator above 3691 */ 3692 if (fpstrapping == 0xf || fpindex == 0xf) 3693 return 0; 3694 3695 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen + 3696 recordlen * fpindex + ofs; 3697 3698 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n", 3699 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1, 3700 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1, 3701 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10); 3702 3703 return 0; 3704} 3705 3706bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode) 3707{ 3708 struct drm_nouveau_private *dev_priv = dev->dev_private; 3709 struct nvbios *bios = &dev_priv->vbios; 3710 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr]; 3711 3712 if (!mode) /* just checking whether we can produce a mode */ 3713 return bios->fp.mode_ptr; 3714 3715 memset(mode, 0, sizeof(struct drm_display_mode)); 3716 /* 3717 * For version 1.0 (version in byte 0): 3718 * bytes 1-2 are "panel type", including bits on whether Colour/mono, 3719 * single/dual link, and type (TFT etc.) 3720 * bytes 3-6 are bits per colour in RGBX 3721 */ 3722 mode->clock = ROM16(mode_entry[7]) * 10; 3723 /* bytes 9-10 is HActive */ 3724 mode->hdisplay = ROM16(mode_entry[11]) + 1; 3725 /* 3726 * bytes 13-14 is HValid Start 3727 * bytes 15-16 is HValid End 3728 */ 3729 mode->hsync_start = ROM16(mode_entry[17]) + 1; 3730 mode->hsync_end = ROM16(mode_entry[19]) + 1; 3731 mode->htotal = ROM16(mode_entry[21]) + 1; 3732 /* bytes 23-24, 27-30 similarly, but vertical */ 3733 mode->vdisplay = ROM16(mode_entry[25]) + 1; 3734 mode->vsync_start = ROM16(mode_entry[31]) + 1; 3735 mode->vsync_end = ROM16(mode_entry[33]) + 1; 3736 mode->vtotal = ROM16(mode_entry[35]) + 1; 3737 mode->flags |= (mode_entry[37] & 0x10) ? 3738 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3739 mode->flags |= (mode_entry[37] & 0x1) ? 3740 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3741 /* 3742 * bytes 38-39 relate to spread spectrum settings 3743 * bytes 40-43 are something to do with PWM 3744 */ 3745 3746 mode->status = MODE_OK; 3747 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; 3748 drm_mode_set_name(mode); 3749 return bios->fp.mode_ptr; 3750} 3751 3752int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit) 3753{ 3754 /* 3755 * The LVDS table header is (mostly) described in 3756 * parse_lvds_manufacturer_table_header(): the BIT header additionally 3757 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if 3758 * straps are not being used for the panel, this specifies the frequency 3759 * at which modes should be set up in the dual link style. 3760 * 3761 * Following the header, the BMP (ver 0xa) table has several records, 3762 * indexed by a separate xlat table, indexed in turn by the fp strap in 3763 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script 3764 * numbers for use by INIT_SUB which controlled panel init and power, 3765 * and finally a dword of ms to sleep between power off and on 3766 * operations. 3767 * 3768 * In the BIT versions, the table following the header serves as an 3769 * integrated config and xlat table: the records in the table are 3770 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has 3771 * two bytes - the first as a config byte, the second for indexing the 3772 * fp mode table pointed to by the BIT 'D' table 3773 * 3774 * DDC is not used until after card init, so selecting the correct table 3775 * entry and setting the dual link flag for EDID equipped panels, 3776 * requiring tests against the native-mode pixel clock, cannot be done 3777 * until later, when this function should be called with non-zero pxclk 3778 */ 3779 struct drm_nouveau_private *dev_priv = dev->dev_private; 3780 struct nvbios *bios = &dev_priv->vbios; 3781 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0; 3782 struct lvdstableheader lth; 3783 uint16_t lvdsofs; 3784 int ret, chip_version = bios->chip_version; 3785 3786 ret = parse_lvds_manufacturer_table_header(dev, bios, <h); 3787 if (ret) 3788 return ret; 3789 3790 switch (lth.lvds_ver) { 3791 case 0x0a: /* pre NV40 */ 3792 lvdsmanufacturerindex = bios->data[ 3793 bios->fp.fpxlatemanufacturertableptr + 3794 fpstrapping]; 3795 3796 /* we're done if this isn't the EDID panel case */ 3797 if (!pxclk) 3798 break; 3799 3800 if (chip_version < 0x25) { 3801 /* nv17 behaviour 3802 * 3803 * It seems the old style lvds script pointer is reused 3804 * to select 18/24 bit colour depth for EDID panels. 3805 */ 3806 lvdsmanufacturerindex = 3807 (bios->legacy.lvds_single_a_script_ptr & 1) ? 3808 2 : 0; 3809 if (pxclk >= bios->fp.duallink_transition_clk) 3810 lvdsmanufacturerindex++; 3811 } else if (chip_version < 0x30) { 3812 /* nv28 behaviour (off-chip encoder) 3813 * 3814 * nv28 does a complex dance of first using byte 121 of 3815 * the EDID to choose the lvdsmanufacturerindex, then 3816 * later attempting to match the EDID manufacturer and 3817 * product IDs in a table (signature 'pidt' (panel id 3818 * table?)), setting an lvdsmanufacturerindex of 0 and 3819 * an fp strap of the match index (or 0xf if none) 3820 */ 3821 lvdsmanufacturerindex = 0; 3822 } else { 3823 /* nv31, nv34 behaviour */ 3824 lvdsmanufacturerindex = 0; 3825 if (pxclk >= bios->fp.duallink_transition_clk) 3826 lvdsmanufacturerindex = 2; 3827 if (pxclk >= 140000) 3828 lvdsmanufacturerindex = 3; 3829 } 3830 3831 /* 3832 * nvidia set the high nibble of (cr57=f, cr58) to 3833 * lvdsmanufacturerindex in this case; we don't 3834 */ 3835 break; 3836 case 0x30: /* NV4x */ 3837 case 0x40: /* G80/G90 */ 3838 lvdsmanufacturerindex = fpstrapping; 3839 break; 3840 default: 3841 NV_ERROR(dev, "LVDS table revision not currently supported\n"); 3842 return -ENOSYS; 3843 } 3844 3845 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex; 3846 switch (lth.lvds_ver) { 3847 case 0x0a: 3848 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1; 3849 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2; 3850 bios->fp.dual_link = bios->data[lvdsofs] & 4; 3851 bios->fp.link_c_increment = bios->data[lvdsofs] & 8; 3852 *if_is_24bit = bios->data[lvdsofs] & 16; 3853 break; 3854 case 0x30: 3855 case 0x40: 3856 /* 3857 * No sign of the "power off for reset" or "reset for panel 3858 * on" bits, but it's safer to assume we should 3859 */ 3860 bios->fp.power_off_for_reset = true; 3861 bios->fp.reset_after_pclk_change = true; 3862 3863 /* 3864 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is 3865 * over-written, and if_is_24bit isn't used 3866 */ 3867 bios->fp.dual_link = bios->data[lvdsofs] & 1; 3868 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2; 3869 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4]; 3870 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10; 3871 break; 3872 } 3873 3874 /* Dell Latitude D620 reports a too-high value for the dual-link 3875 * transition freq, causing us to program the panel incorrectly. 3876 * 3877 * It doesn't appear the VBIOS actually uses its transition freq 3878 * (90000kHz), instead it uses the "Number of LVDS channels" field 3879 * out of the panel ID structure (http://www.spwg.org/). 3880 * 3881 * For the moment, a quirk will do :) 3882 */ 3883 if ((dev->pdev->device == 0x01d7) && 3884 (dev->pdev->subsystem_vendor == 0x1028) && 3885 (dev->pdev->subsystem_device == 0x01c2)) { 3886 bios->fp.duallink_transition_clk = 80000; 3887 } 3888 3889 /* set dual_link flag for EDID case */ 3890 if (pxclk && (chip_version < 0x25 || chip_version > 0x28)) 3891 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk); 3892 3893 *dl = bios->fp.dual_link; 3894 3895 return 0; 3896} 3897 3898static uint8_t * 3899bios_output_config_match(struct drm_device *dev, struct dcb_entry *dcbent, 3900 uint16_t record, int record_len, int record_nr) 3901{ 3902 struct drm_nouveau_private *dev_priv = dev->dev_private; 3903 struct nvbios *bios = &dev_priv->vbios; 3904 uint32_t entry; 3905 uint16_t table; 3906 int i, v; 3907 3908 for (i = 0; i < record_nr; i++, record += record_len) { 3909 table = ROM16(bios->data[record]); 3910 if (!table) 3911 continue; 3912 entry = ROM32(bios->data[table]); 3913 3914 v = (entry & 0x000f0000) >> 16; 3915 if (!(v & dcbent->or)) 3916 continue; 3917 3918 v = (entry & 0x000000f0) >> 4; 3919 if (v != dcbent->location) 3920 continue; 3921 3922 v = (entry & 0x0000000f); 3923 if (v != dcbent->type) 3924 continue; 3925 3926 return &bios->data[table]; 3927 } 3928 3929 return NULL; 3930} 3931 3932void * 3933nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent, 3934 int *length) 3935{ 3936 struct drm_nouveau_private *dev_priv = dev->dev_private; 3937 struct nvbios *bios = &dev_priv->vbios; 3938 uint8_t *table; 3939 3940 if (!bios->display.dp_table_ptr) { 3941 NV_ERROR(dev, "No pointer to DisplayPort table\n"); 3942 return NULL; 3943 } 3944 table = &bios->data[bios->display.dp_table_ptr]; 3945 3946 if (table[0] != 0x20 && table[0] != 0x21) { 3947 NV_ERROR(dev, "DisplayPort table version 0x%02x unknown\n", 3948 table[0]); 3949 return NULL; 3950 } 3951 3952 *length = table[4]; 3953 return bios_output_config_match(dev, dcbent, 3954 bios->display.dp_table_ptr + table[1], 3955 table[2], table[3]); 3956} 3957 3958int 3959nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent, 3960 uint32_t sub, int pxclk) 3961{ 3962 /* 3963 * The display script table is located by the BIT 'U' table. 3964 * 3965 * It contains an array of pointers to various tables describing 3966 * a particular output type. The first 32-bits of the output 3967 * tables contains similar information to a DCB entry, and is 3968 * used to decide whether that particular table is suitable for 3969 * the output you want to access. 3970 * 3971 * The "record header length" field here seems to indicate the 3972 * offset of the first configuration entry in the output tables. 3973 * This is 10 on most cards I've seen, but 12 has been witnessed 3974 * on DP cards, and there's another script pointer within the 3975 * header. 3976 * 3977 * offset + 0 ( 8 bits): version 3978 * offset + 1 ( 8 bits): header length 3979 * offset + 2 ( 8 bits): record length 3980 * offset + 3 ( 8 bits): number of records 3981 * offset + 4 ( 8 bits): record header length 3982 * offset + 5 (16 bits): pointer to first output script table 3983 */ 3984 3985 struct drm_nouveau_private *dev_priv = dev->dev_private; 3986 struct nvbios *bios = &dev_priv->vbios; 3987 uint8_t *table = &bios->data[bios->display.script_table_ptr]; 3988 uint8_t *otable = NULL; 3989 uint16_t script; 3990 int i = 0; 3991 3992 if (!bios->display.script_table_ptr) { 3993 NV_ERROR(dev, "No pointer to output script table\n"); 3994 return 1; 3995 } 3996 3997 /* 3998 * Nothing useful has been in any of the pre-2.0 tables I've seen, 3999 * so until they are, we really don't need to care. 4000 */ 4001 if (table[0] < 0x20) 4002 return 1; 4003 4004 if (table[0] != 0x20 && table[0] != 0x21) { 4005 NV_ERROR(dev, "Output script table version 0x%02x unknown\n", 4006 table[0]); 4007 return 1; 4008 } 4009 4010 /* 4011 * The output script tables describing a particular output type 4012 * look as follows: 4013 * 4014 * offset + 0 (32 bits): output this table matches (hash of DCB) 4015 * offset + 4 ( 8 bits): unknown 4016 * offset + 5 ( 8 bits): number of configurations 4017 * offset + 6 (16 bits): pointer to some script 4018 * offset + 8 (16 bits): pointer to some script 4019 * 4020 * headerlen == 10 4021 * offset + 10 : configuration 0 4022 * 4023 * headerlen == 12 4024 * offset + 10 : pointer to some script 4025 * offset + 12 : configuration 0 4026 * 4027 * Each config entry is as follows: 4028 * 4029 * offset + 0 (16 bits): unknown, assumed to be a match value 4030 * offset + 2 (16 bits): pointer to script table (clock set?) 4031 * offset + 4 (16 bits): pointer to script table (reset?) 4032 * 4033 * There doesn't appear to be a count value to say how many 4034 * entries exist in each script table, instead, a 0 value in 4035 * the first 16-bit word seems to indicate both the end of the 4036 * list and the default entry. The second 16-bit word in the 4037 * script tables is a pointer to the script to execute. 4038 */ 4039 4040 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n", 4041 dcbent->type, dcbent->location, dcbent->or); 4042 otable = bios_output_config_match(dev, dcbent, table[1] + 4043 bios->display.script_table_ptr, 4044 table[2], table[3]); 4045 if (!otable) { 4046 NV_ERROR(dev, "Couldn't find matching output script table\n"); 4047 return 1; 4048 } 4049 4050 if (pxclk < -2 || pxclk > 0) { 4051 /* Try to find matching script table entry */ 4052 for (i = 0; i < otable[5]; i++) { 4053 if (ROM16(otable[table[4] + i*6]) == sub) 4054 break; 4055 } 4056 4057 if (i == otable[5]) { 4058 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, " 4059 "using first\n", 4060 sub, dcbent->type, dcbent->or); 4061 i = 0; 4062 } 4063 } 4064 4065 if (pxclk == 0) { 4066 script = ROM16(otable[6]); 4067 if (!script) { 4068 NV_DEBUG_KMS(dev, "output script 0 not found\n"); 4069 return 1; 4070 } 4071 4072 NV_TRACE(dev, "0x%04X: parsing output script 0\n", script); 4073 nouveau_bios_run_init_table(dev, script, dcbent); 4074 } else 4075 if (pxclk == -1) { 4076 script = ROM16(otable[8]); 4077 if (!script) { 4078 NV_DEBUG_KMS(dev, "output script 1 not found\n"); 4079 return 1; 4080 } 4081 4082 NV_TRACE(dev, "0x%04X: parsing output script 1\n", script); 4083 nouveau_bios_run_init_table(dev, script, dcbent); 4084 } else 4085 if (pxclk == -2) { 4086 if (table[4] >= 12) 4087 script = ROM16(otable[10]); 4088 else 4089 script = 0; 4090 if (!script) { 4091 NV_DEBUG_KMS(dev, "output script 2 not found\n"); 4092 return 1; 4093 } 4094 4095 NV_TRACE(dev, "0x%04X: parsing output script 2\n", script); 4096 nouveau_bios_run_init_table(dev, script, dcbent); 4097 } else 4098 if (pxclk > 0) { 4099 script = ROM16(otable[table[4] + i*6 + 2]); 4100 if (script) 4101 script = clkcmptable(bios, script, pxclk); 4102 if (!script) { 4103 NV_ERROR(dev, "clock script 0 not found\n"); 4104 return 1; 4105 } 4106 4107 NV_TRACE(dev, "0x%04X: parsing clock script 0\n", script); 4108 nouveau_bios_run_init_table(dev, script, dcbent); 4109 } else 4110 if (pxclk < 0) { 4111 script = ROM16(otable[table[4] + i*6 + 4]); 4112 if (script) 4113 script = clkcmptable(bios, script, -pxclk); 4114 if (!script) { 4115 NV_DEBUG_KMS(dev, "clock script 1 not found\n"); 4116 return 1; 4117 } 4118 4119 NV_TRACE(dev, "0x%04X: parsing clock script 1\n", script); 4120 nouveau_bios_run_init_table(dev, script, dcbent); 4121 } 4122 4123 return 0; 4124} 4125 4126 4127int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk) 4128{ 4129 /* 4130 * the pxclk parameter is in kHz 4131 * 4132 * This runs the TMDS regs setting code found on BIT bios cards 4133 * 4134 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and 4135 * ffs(or) == 3, use the second. 4136 */ 4137 4138 struct drm_nouveau_private *dev_priv = dev->dev_private; 4139 struct nvbios *bios = &dev_priv->vbios; 4140 int cv = bios->chip_version; 4141 uint16_t clktable = 0, scriptptr; 4142 uint32_t sel_clk_binding, sel_clk; 4143 4144 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */ 4145 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 && 4146 dcbent->location != DCB_LOC_ON_CHIP) 4147 return 0; 4148 4149 switch (ffs(dcbent->or)) { 4150 case 1: 4151 clktable = bios->tmds.output0_script_ptr; 4152 break; 4153 case 2: 4154 case 3: 4155 clktable = bios->tmds.output1_script_ptr; 4156 break; 4157 } 4158 4159 if (!clktable) { 4160 NV_ERROR(dev, "Pixel clock comparison table not found\n"); 4161 return -EINVAL; 4162 } 4163 4164 scriptptr = clkcmptable(bios, clktable, pxclk); 4165 4166 if (!scriptptr) { 4167 NV_ERROR(dev, "TMDS output init script not found\n"); 4168 return -ENOENT; 4169 } 4170 4171 /* don't let script change pll->head binding */ 4172 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000; 4173 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000); 4174 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; 4175 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); 4176 4177 return 0; 4178} 4179 4180int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim) 4181{ 4182 /* 4183 * PLL limits table 4184 * 4185 * Version 0x10: NV30, NV31 4186 * One byte header (version), one record of 24 bytes 4187 * Version 0x11: NV36 - Not implemented 4188 * Seems to have same record style as 0x10, but 3 records rather than 1 4189 * Version 0x20: Found on Geforce 6 cards 4190 * Trivial 4 byte BIT header. 31 (0x1f) byte record length 4191 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards 4192 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record 4193 * length in general, some (integrated) have an extra configuration byte 4194 * Version 0x30: Found on Geforce 8, separates the register mapping 4195 * from the limits tables. 4196 */ 4197 4198 struct drm_nouveau_private *dev_priv = dev->dev_private; 4199 struct nvbios *bios = &dev_priv->vbios; 4200 int cv = bios->chip_version, pllindex = 0; 4201 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0; 4202 uint32_t crystal_strap_mask, crystal_straps; 4203 4204 if (!bios->pll_limit_tbl_ptr) { 4205 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 || 4206 cv >= 0x40) { 4207 NV_ERROR(dev, "Pointer to PLL limits table invalid\n"); 4208 return -EINVAL; 4209 } 4210 } else 4211 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr]; 4212 4213 crystal_strap_mask = 1 << 6; 4214 /* open coded dev->twoHeads test */ 4215 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20) 4216 crystal_strap_mask |= 1 << 22; 4217 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) & 4218 crystal_strap_mask; 4219 4220 switch (pll_lim_ver) { 4221 /* 4222 * We use version 0 to indicate a pre limit table bios (single stage 4223 * pll) and load the hard coded limits instead. 4224 */ 4225 case 0: 4226 break; 4227 case 0x10: 4228 case 0x11: 4229 /* 4230 * Strictly v0x11 has 3 entries, but the last two don't seem 4231 * to get used. 4232 */ 4233 headerlen = 1; 4234 recordlen = 0x18; 4235 entries = 1; 4236 pllindex = 0; 4237 break; 4238 case 0x20: 4239 case 0x21: 4240 case 0x30: 4241 case 0x40: 4242 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1]; 4243 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2]; 4244 entries = bios->data[bios->pll_limit_tbl_ptr + 3]; 4245 break; 4246 default: 4247 NV_ERROR(dev, "PLL limits table revision 0x%X not currently " 4248 "supported\n", pll_lim_ver); 4249 return -ENOSYS; 4250 } 4251 4252 /* initialize all members to zero */ 4253 memset(pll_lim, 0, sizeof(struct pll_lims)); 4254 4255 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) { 4256 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex]; 4257 4258 pll_lim->vco1.minfreq = ROM32(pll_rec[0]); 4259 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]); 4260 pll_lim->vco2.minfreq = ROM32(pll_rec[8]); 4261 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]); 4262 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]); 4263 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]); 4264 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX; 4265 4266 /* these values taken from nv30/31/36 */ 4267 pll_lim->vco1.min_n = 0x1; 4268 if (cv == 0x36) 4269 pll_lim->vco1.min_n = 0x5; 4270 pll_lim->vco1.max_n = 0xff; 4271 pll_lim->vco1.min_m = 0x1; 4272 pll_lim->vco1.max_m = 0xd; 4273 pll_lim->vco2.min_n = 0x4; 4274 /* 4275 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this 4276 * table version (apart from nv35)), N2 is compared to 4277 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and 4278 * save a comparison 4279 */ 4280 pll_lim->vco2.max_n = 0x28; 4281 if (cv == 0x30 || cv == 0x35) 4282 /* only 5 bits available for N2 on nv30/35 */ 4283 pll_lim->vco2.max_n = 0x1f; 4284 pll_lim->vco2.min_m = 0x1; 4285 pll_lim->vco2.max_m = 0x4; 4286 pll_lim->max_log2p = 0x7; 4287 pll_lim->max_usable_log2p = 0x6; 4288 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) { 4289 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen; 4290 uint32_t reg = 0; /* default match */ 4291 uint8_t *pll_rec; 4292 int i; 4293 4294 /* 4295 * First entry is default match, if nothing better. warn if 4296 * reg field nonzero 4297 */ 4298 if (ROM32(bios->data[plloffs])) 4299 NV_WARN(dev, "Default PLL limit entry has non-zero " 4300 "register field\n"); 4301 4302 if (limit_match > MAX_PLL_TYPES) 4303 /* we've been passed a reg as the match */ 4304 reg = limit_match; 4305 else /* limit match is a pll type */ 4306 for (i = 1; i < entries && !reg; i++) { 4307 uint32_t cmpreg = ROM32(bios->data[plloffs + recordlen * i]); 4308 4309 if (limit_match == NVPLL && 4310 (cmpreg == NV_PRAMDAC_NVPLL_COEFF || cmpreg == 0x4000)) 4311 reg = cmpreg; 4312 if (limit_match == MPLL && 4313 (cmpreg == NV_PRAMDAC_MPLL_COEFF || cmpreg == 0x4020)) 4314 reg = cmpreg; 4315 if (limit_match == VPLL1 && 4316 (cmpreg == NV_PRAMDAC_VPLL_COEFF || cmpreg == 0x4010)) 4317 reg = cmpreg; 4318 if (limit_match == VPLL2 && 4319 (cmpreg == NV_RAMDAC_VPLL2 || cmpreg == 0x4018)) 4320 reg = cmpreg; 4321 } 4322 4323 for (i = 1; i < entries; i++) 4324 if (ROM32(bios->data[plloffs + recordlen * i]) == reg) { 4325 pllindex = i; 4326 break; 4327 } 4328 4329 pll_rec = &bios->data[plloffs + recordlen * pllindex]; 4330 4331 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n", 4332 pllindex ? reg : 0); 4333 4334 /* 4335 * Frequencies are stored in tables in MHz, kHz are more 4336 * useful, so we convert. 4337 */ 4338 4339 /* What output frequencies can each VCO generate? */ 4340 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000; 4341 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000; 4342 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000; 4343 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000; 4344 4345 /* What input frequencies they accept (past the m-divider)? */ 4346 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000; 4347 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000; 4348 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000; 4349 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000; 4350 4351 /* What values are accepted as multiplier and divider? */ 4352 pll_lim->vco1.min_n = pll_rec[20]; 4353 pll_lim->vco1.max_n = pll_rec[21]; 4354 pll_lim->vco1.min_m = pll_rec[22]; 4355 pll_lim->vco1.max_m = pll_rec[23]; 4356 pll_lim->vco2.min_n = pll_rec[24]; 4357 pll_lim->vco2.max_n = pll_rec[25]; 4358 pll_lim->vco2.min_m = pll_rec[26]; 4359 pll_lim->vco2.max_m = pll_rec[27]; 4360 4361 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29]; 4362 if (pll_lim->max_log2p > 0x7) 4363 /* pll decoding in nv_hw.c assumes never > 7 */ 4364 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n", 4365 pll_lim->max_log2p); 4366 if (cv < 0x60) 4367 pll_lim->max_usable_log2p = 0x6; 4368 pll_lim->log2p_bias = pll_rec[30]; 4369 4370 if (recordlen > 0x22) 4371 pll_lim->refclk = ROM32(pll_rec[31]); 4372 4373 if (recordlen > 0x23 && pll_rec[35]) 4374 NV_WARN(dev, 4375 "Bits set in PLL configuration byte (%x)\n", 4376 pll_rec[35]); 4377 4378 /* C51 special not seen elsewhere */ 4379 if (cv == 0x51 && !pll_lim->refclk) { 4380 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK); 4381 4382 if (((limit_match == NV_PRAMDAC_VPLL_COEFF || limit_match == VPLL1) && sel_clk & 0x20) || 4383 ((limit_match == NV_RAMDAC_VPLL2 || limit_match == VPLL2) && sel_clk & 0x80)) { 4384 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3) 4385 pll_lim->refclk = 200000; 4386 else 4387 pll_lim->refclk = 25000; 4388 } 4389 } 4390 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */ 4391 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen]; 4392 uint8_t *record = NULL; 4393 int i; 4394 4395 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n", 4396 limit_match); 4397 4398 for (i = 0; i < entries; i++, entry += recordlen) { 4399 if (ROM32(entry[3]) == limit_match) { 4400 record = &bios->data[ROM16(entry[1])]; 4401 break; 4402 } 4403 } 4404 4405 if (!record) { 4406 NV_ERROR(dev, "Register 0x%08x not found in PLL " 4407 "limits table", limit_match); 4408 return -ENOENT; 4409 } 4410 4411 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000; 4412 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000; 4413 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000; 4414 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000; 4415 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000; 4416 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000; 4417 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000; 4418 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000; 4419 pll_lim->vco1.min_n = record[16]; 4420 pll_lim->vco1.max_n = record[17]; 4421 pll_lim->vco1.min_m = record[18]; 4422 pll_lim->vco1.max_m = record[19]; 4423 pll_lim->vco2.min_n = record[20]; 4424 pll_lim->vco2.max_n = record[21]; 4425 pll_lim->vco2.min_m = record[22]; 4426 pll_lim->vco2.max_m = record[23]; 4427 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25]; 4428 pll_lim->log2p_bias = record[27]; 4429 pll_lim->refclk = ROM32(record[28]); 4430 } else if (pll_lim_ver) { /* ver 0x40 */ 4431 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen]; 4432 uint8_t *record = NULL; 4433 int i; 4434 4435 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n", 4436 limit_match); 4437 4438 for (i = 0; i < entries; i++, entry += recordlen) { 4439 if (ROM32(entry[3]) == limit_match) { 4440 record = &bios->data[ROM16(entry[1])]; 4441 break; 4442 } 4443 } 4444 4445 if (!record) { 4446 NV_ERROR(dev, "Register 0x%08x not found in PLL " 4447 "limits table", limit_match); 4448 return -ENOENT; 4449 } 4450 4451 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000; 4452 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000; 4453 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000; 4454 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000; 4455 pll_lim->vco1.min_m = record[8]; 4456 pll_lim->vco1.max_m = record[9]; 4457 pll_lim->vco1.min_n = record[10]; 4458 pll_lim->vco1.max_n = record[11]; 4459 pll_lim->min_p = record[12]; 4460 pll_lim->max_p = record[13]; 4461 /* where did this go to?? */ 4462 if (limit_match == 0x00614100 || limit_match == 0x00614900) 4463 pll_lim->refclk = 27000; 4464 else 4465 pll_lim->refclk = 100000; 4466 } 4467 4468 /* 4469 * By now any valid limit table ought to have set a max frequency for 4470 * vco1, so if it's zero it's either a pre limit table bios, or one 4471 * with an empty limit table (seen on nv18) 4472 */ 4473 if (!pll_lim->vco1.maxfreq) { 4474 pll_lim->vco1.minfreq = bios->fminvco; 4475 pll_lim->vco1.maxfreq = bios->fmaxvco; 4476 pll_lim->vco1.min_inputfreq = 0; 4477 pll_lim->vco1.max_inputfreq = INT_MAX; 4478 pll_lim->vco1.min_n = 0x1; 4479 pll_lim->vco1.max_n = 0xff; 4480 pll_lim->vco1.min_m = 0x1; 4481 if (crystal_straps == 0) { 4482 /* nv05 does this, nv11 doesn't, nv10 unknown */ 4483 if (cv < 0x11) 4484 pll_lim->vco1.min_m = 0x7; 4485 pll_lim->vco1.max_m = 0xd; 4486 } else { 4487 if (cv < 0x11) 4488 pll_lim->vco1.min_m = 0x8; 4489 pll_lim->vco1.max_m = 0xe; 4490 } 4491 if (cv < 0x17 || cv == 0x1a || cv == 0x20) 4492 pll_lim->max_log2p = 4; 4493 else 4494 pll_lim->max_log2p = 5; 4495 pll_lim->max_usable_log2p = pll_lim->max_log2p; 4496 } 4497 4498 if (!pll_lim->refclk) 4499 switch (crystal_straps) { 4500 case 0: 4501 pll_lim->refclk = 13500; 4502 break; 4503 case (1 << 6): 4504 pll_lim->refclk = 14318; 4505 break; 4506 case (1 << 22): 4507 pll_lim->refclk = 27000; 4508 break; 4509 case (1 << 22 | 1 << 6): 4510 pll_lim->refclk = 25000; 4511 break; 4512 } 4513 4514 NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq); 4515 NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq); 4516 NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq); 4517 NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq); 4518 NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n); 4519 NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n); 4520 NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m); 4521 NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m); 4522 if (pll_lim->vco2.maxfreq) { 4523 NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq); 4524 NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq); 4525 NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq); 4526 NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq); 4527 NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n); 4528 NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n); 4529 NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m); 4530 NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m); 4531 } 4532 if (!pll_lim->max_p) { 4533 NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p); 4534 NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias); 4535 } else { 4536 NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p); 4537 NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p); 4538 } 4539 NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk); 4540 4541 return 0; 4542} 4543 4544static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset) 4545{ 4546 /* 4547 * offset + 0 (8 bits): Micro version 4548 * offset + 1 (8 bits): Minor version 4549 * offset + 2 (8 bits): Chip version 4550 * offset + 3 (8 bits): Major version 4551 */ 4552 4553 bios->major_version = bios->data[offset + 3]; 4554 bios->chip_version = bios->data[offset + 2]; 4555 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n", 4556 bios->data[offset + 3], bios->data[offset + 2], 4557 bios->data[offset + 1], bios->data[offset]); 4558} 4559 4560static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset) 4561{ 4562 /* 4563 * Parses the init table segment for pointers used in script execution. 4564 * 4565 * offset + 0 (16 bits): init script tables pointer 4566 * offset + 2 (16 bits): macro index table pointer 4567 * offset + 4 (16 bits): macro table pointer 4568 * offset + 6 (16 bits): condition table pointer 4569 * offset + 8 (16 bits): io condition table pointer 4570 * offset + 10 (16 bits): io flag condition table pointer 4571 * offset + 12 (16 bits): init function table pointer 4572 */ 4573 4574 bios->init_script_tbls_ptr = ROM16(bios->data[offset]); 4575 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]); 4576 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]); 4577 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]); 4578 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]); 4579 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]); 4580 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]); 4581} 4582 4583static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4584{ 4585 /* 4586 * Parses the load detect values for g80 cards. 4587 * 4588 * offset + 0 (16 bits): loadval table pointer 4589 */ 4590 4591 uint16_t load_table_ptr; 4592 uint8_t version, headerlen, entrylen, num_entries; 4593 4594 if (bitentry->length != 3) { 4595 NV_ERROR(dev, "Do not understand BIT A table\n"); 4596 return -EINVAL; 4597 } 4598 4599 load_table_ptr = ROM16(bios->data[bitentry->offset]); 4600 4601 if (load_table_ptr == 0x0) { 4602 NV_ERROR(dev, "Pointer to BIT loadval table invalid\n"); 4603 return -EINVAL; 4604 } 4605 4606 version = bios->data[load_table_ptr]; 4607 4608 if (version != 0x10) { 4609 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n", 4610 version >> 4, version & 0xF); 4611 return -ENOSYS; 4612 } 4613 4614 headerlen = bios->data[load_table_ptr + 1]; 4615 entrylen = bios->data[load_table_ptr + 2]; 4616 num_entries = bios->data[load_table_ptr + 3]; 4617 4618 if (headerlen != 4 || entrylen != 4 || num_entries != 2) { 4619 NV_ERROR(dev, "Do not understand BIT loadval table\n"); 4620 return -EINVAL; 4621 } 4622 4623 /* First entry is normal dac, 2nd tv-out perhaps? */ 4624 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff; 4625 4626 return 0; 4627} 4628 4629static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4630{ 4631 /* 4632 * offset + 8 (16 bits): PLL limits table pointer 4633 * 4634 * There's more in here, but that's unknown. 4635 */ 4636 4637 if (bitentry->length < 10) { 4638 NV_ERROR(dev, "Do not understand BIT C table\n"); 4639 return -EINVAL; 4640 } 4641 4642 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]); 4643 4644 return 0; 4645} 4646 4647static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4648{ 4649 /* 4650 * Parses the flat panel table segment that the bit entry points to. 4651 * Starting at bitentry->offset: 4652 * 4653 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte 4654 * records beginning with a freq. 4655 * offset + 2 (16 bits): mode table pointer 4656 */ 4657 4658 if (bitentry->length != 4) { 4659 NV_ERROR(dev, "Do not understand BIT display table\n"); 4660 return -EINVAL; 4661 } 4662 4663 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]); 4664 4665 return 0; 4666} 4667 4668static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4669{ 4670 /* 4671 * Parses the init table segment that the bit entry points to. 4672 * 4673 * See parse_script_table_pointers for layout 4674 */ 4675 4676 if (bitentry->length < 14) { 4677 NV_ERROR(dev, "Do not understand init table\n"); 4678 return -EINVAL; 4679 } 4680 4681 parse_script_table_pointers(bios, bitentry->offset); 4682 4683 if (bitentry->length >= 16) 4684 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]); 4685 if (bitentry->length >= 18) 4686 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]); 4687 4688 return 0; 4689} 4690 4691static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4692{ 4693 /* 4694 * BIT 'i' (info?) table 4695 * 4696 * offset + 0 (32 bits): BIOS version dword (as in B table) 4697 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?) 4698 * offset + 13 (16 bits): pointer to table containing DAC load 4699 * detection comparison values 4700 * 4701 * There's other things in the table, purpose unknown 4702 */ 4703 4704 uint16_t daccmpoffset; 4705 uint8_t dacver, dacheaderlen; 4706 4707 if (bitentry->length < 6) { 4708 NV_ERROR(dev, "BIT i table too short for needed information\n"); 4709 return -EINVAL; 4710 } 4711 4712 parse_bios_version(dev, bios, bitentry->offset); 4713 4714 /* 4715 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's 4716 * Quadro identity crisis), other bits possibly as for BMP feature byte 4717 */ 4718 bios->feature_byte = bios->data[bitentry->offset + 5]; 4719 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE; 4720 4721 if (bitentry->length < 15) { 4722 NV_WARN(dev, "BIT i table not long enough for DAC load " 4723 "detection comparison table\n"); 4724 return -EINVAL; 4725 } 4726 4727 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]); 4728 4729 /* doesn't exist on g80 */ 4730 if (!daccmpoffset) 4731 return 0; 4732 4733 /* 4734 * The first value in the table, following the header, is the 4735 * comparison value, the second entry is a comparison value for 4736 * TV load detection. 4737 */ 4738 4739 dacver = bios->data[daccmpoffset]; 4740 dacheaderlen = bios->data[daccmpoffset + 1]; 4741 4742 if (dacver != 0x00 && dacver != 0x10) { 4743 NV_WARN(dev, "DAC load detection comparison table version " 4744 "%d.%d not known\n", dacver >> 4, dacver & 0xf); 4745 return -ENOSYS; 4746 } 4747 4748 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]); 4749 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]); 4750 4751 return 0; 4752} 4753 4754static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4755{ 4756 /* 4757 * Parses the LVDS table segment that the bit entry points to. 4758 * Starting at bitentry->offset: 4759 * 4760 * offset + 0 (16 bits): LVDS strap xlate table pointer 4761 */ 4762 4763 if (bitentry->length != 2) { 4764 NV_ERROR(dev, "Do not understand BIT LVDS table\n"); 4765 return -EINVAL; 4766 } 4767 4768 /* 4769 * No idea if it's still called the LVDS manufacturer table, but 4770 * the concept's close enough. 4771 */ 4772 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]); 4773 4774 return 0; 4775} 4776 4777static int 4778parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios, 4779 struct bit_entry *bitentry) 4780{ 4781 /* 4782 * offset + 2 (8 bits): number of options in an 4783 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set 4784 * offset + 3 (16 bits): pointer to strap xlate table for RAM 4785 * restrict option selection 4786 * 4787 * There's a bunch of bits in this table other than the RAM restrict 4788 * stuff that we don't use - their use currently unknown 4789 */ 4790 4791 /* 4792 * Older bios versions don't have a sufficiently long table for 4793 * what we want 4794 */ 4795 if (bitentry->length < 0x5) 4796 return 0; 4797 4798 if (bitentry->id[1] < 2) { 4799 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2]; 4800 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]); 4801 } else { 4802 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0]; 4803 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]); 4804 } 4805 4806 return 0; 4807} 4808 4809static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 4810{ 4811 /* 4812 * Parses the pointer to the TMDS table 4813 * 4814 * Starting at bitentry->offset: 4815 * 4816 * offset + 0 (16 bits): TMDS table pointer 4817 * 4818 * The TMDS table is typically found just before the DCB table, with a 4819 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being 4820 * length?) 4821 * 4822 * At offset +7 is a pointer to a script, which I don't know how to 4823 * run yet. 4824 * At offset +9 is a pointer to another script, likewise 4825 * Offset +11 has a pointer to a table where the first word is a pxclk 4826 * frequency and the second word a pointer to a script, which should be 4827 * run if the comparison pxclk frequency is less than the pxclk desired. 4828 * This repeats for decreasing comparison frequencies 4829 * Offset +13 has a pointer to a similar table 4830 * The selection of table (and possibly +7/+9 script) is dictated by 4831 * "or" from the DCB. 4832 */ 4833 4834 uint16_t tmdstableptr, script1, script2; 4835 4836 if (bitentry->length != 2) { 4837 NV_ERROR(dev, "Do not understand BIT TMDS table\n"); 4838 return -EINVAL; 4839 } 4840 4841 tmdstableptr = ROM16(bios->data[bitentry->offset]); 4842 4843 if (tmdstableptr == 0x0) { 4844 NV_ERROR(dev, "Pointer to TMDS table invalid\n"); 4845 return -EINVAL; 4846 } 4847 4848 /* nv50+ has v2.0, but we don't parse it atm */ 4849 if (bios->data[tmdstableptr] != 0x11) { 4850 NV_WARN(dev, 4851 "TMDS table revision %d.%d not currently supported\n", 4852 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf); 4853 return -ENOSYS; 4854 } 4855 4856 /* 4857 * These two scripts are odd: they don't seem to get run even when 4858 * they are not stubbed. 4859 */ 4860 script1 = ROM16(bios->data[tmdstableptr + 7]); 4861 script2 = ROM16(bios->data[tmdstableptr + 9]); 4862 if (bios->data[script1] != 'q' || bios->data[script2] != 'q') 4863 NV_WARN(dev, "TMDS table script pointers not stubbed\n"); 4864 4865 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]); 4866 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]); 4867 4868 return 0; 4869} 4870 4871static int 4872parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios, 4873 struct bit_entry *bitentry) 4874{ 4875 /* 4876 * Parses the pointer to the G80 output script tables 4877 * 4878 * Starting at bitentry->offset: 4879 * 4880 * offset + 0 (16 bits): output script table pointer 4881 */ 4882 4883 uint16_t outputscripttableptr; 4884 4885 if (bitentry->length != 3) { 4886 NV_ERROR(dev, "Do not understand BIT U table\n"); 4887 return -EINVAL; 4888 } 4889 4890 outputscripttableptr = ROM16(bios->data[bitentry->offset]); 4891 bios->display.script_table_ptr = outputscripttableptr; 4892 return 0; 4893} 4894 4895static int 4896parse_bit_displayport_tbl_entry(struct drm_device *dev, struct nvbios *bios, 4897 struct bit_entry *bitentry) 4898{ 4899 bios->display.dp_table_ptr = ROM16(bios->data[bitentry->offset]); 4900 return 0; 4901} 4902 4903struct bit_table { 4904 const char id; 4905 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *); 4906}; 4907 4908#define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry }) 4909 4910static int 4911parse_bit_table(struct nvbios *bios, const uint16_t bitoffset, 4912 struct bit_table *table) 4913{ 4914 struct drm_device *dev = bios->dev; 4915 uint8_t maxentries = bios->data[bitoffset + 4]; 4916 int i, offset; 4917 struct bit_entry bitentry; 4918 4919 for (i = 0, offset = bitoffset + 6; i < maxentries; i++, offset += 6) { 4920 bitentry.id[0] = bios->data[offset]; 4921 4922 if (bitentry.id[0] != table->id) 4923 continue; 4924 4925 bitentry.id[1] = bios->data[offset + 1]; 4926 bitentry.length = ROM16(bios->data[offset + 2]); 4927 bitentry.offset = ROM16(bios->data[offset + 4]); 4928 4929 return table->parse_fn(dev, bios, &bitentry); 4930 } 4931 4932 NV_INFO(dev, "BIT table '%c' not found\n", table->id); 4933 return -ENOSYS; 4934} 4935 4936static int 4937parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset) 4938{ 4939 int ret; 4940 4941 /* 4942 * The only restriction on parsing order currently is having 'i' first 4943 * for use of bios->*_version or bios->feature_byte while parsing; 4944 * functions shouldn't be actually *doing* anything apart from pulling 4945 * data from the image into the bios struct, thus no interdependencies 4946 */ 4947 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i)); 4948 if (ret) /* info? */ 4949 return ret; 4950 if (bios->major_version >= 0x60) /* g80+ */ 4951 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A)); 4952 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C)); 4953 if (ret) 4954 return ret; 4955 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display)); 4956 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init)); 4957 if (ret) 4958 return ret; 4959 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */ 4960 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds)); 4961 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds)); 4962 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U)); 4963 parse_bit_table(bios, bitoffset, &BIT_TABLE('d', displayport)); 4964 4965 return 0; 4966} 4967 4968static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset) 4969{ 4970 /* 4971 * Parses the BMP structure for useful things, but does not act on them 4972 * 4973 * offset + 5: BMP major version 4974 * offset + 6: BMP minor version 4975 * offset + 9: BMP feature byte 4976 * offset + 10: BCD encoded BIOS version 4977 * 4978 * offset + 18: init script table pointer (for bios versions < 5.10h) 4979 * offset + 20: extra init script table pointer (for bios 4980 * versions < 5.10h) 4981 * 4982 * offset + 24: memory init table pointer (used on early bios versions) 4983 * offset + 26: SDR memory sequencing setup data table 4984 * offset + 28: DDR memory sequencing setup data table 4985 * 4986 * offset + 54: index of I2C CRTC pair to use for CRT output 4987 * offset + 55: index of I2C CRTC pair to use for TV output 4988 * offset + 56: index of I2C CRTC pair to use for flat panel output 4989 * offset + 58: write CRTC index for I2C pair 0 4990 * offset + 59: read CRTC index for I2C pair 0 4991 * offset + 60: write CRTC index for I2C pair 1 4992 * offset + 61: read CRTC index for I2C pair 1 4993 * 4994 * offset + 67: maximum internal PLL frequency (single stage PLL) 4995 * offset + 71: minimum internal PLL frequency (single stage PLL) 4996 * 4997 * offset + 75: script table pointers, as described in 4998 * parse_script_table_pointers 4999 * 5000 * offset + 89: TMDS single link output A table pointer 5001 * offset + 91: TMDS single link output B table pointer 5002 * offset + 95: LVDS single link output A table pointer 5003 * offset + 105: flat panel timings table pointer 5004 * offset + 107: flat panel strapping translation table pointer 5005 * offset + 117: LVDS manufacturer panel config table pointer 5006 * offset + 119: LVDS manufacturer strapping translation table pointer 5007 * 5008 * offset + 142: PLL limits table pointer 5009 * 5010 * offset + 156: minimum pixel clock for LVDS dual link 5011 */ 5012 5013 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor; 5014 uint16_t bmplength; 5015 uint16_t legacy_scripts_offset, legacy_i2c_offset; 5016 5017 /* load needed defaults in case we can't parse this info */ 5018 bios->dcb.i2c[0].write = NV_CIO_CRE_DDC_WR__INDEX; 5019 bios->dcb.i2c[0].read = NV_CIO_CRE_DDC_STATUS__INDEX; 5020 bios->dcb.i2c[1].write = NV_CIO_CRE_DDC0_WR__INDEX; 5021 bios->dcb.i2c[1].read = NV_CIO_CRE_DDC0_STATUS__INDEX; 5022 bios->digital_min_front_porch = 0x4b; 5023 bios->fmaxvco = 256000; 5024 bios->fminvco = 128000; 5025 bios->fp.duallink_transition_clk = 90000; 5026 5027 bmp_version_major = bmp[5]; 5028 bmp_version_minor = bmp[6]; 5029 5030 NV_TRACE(dev, "BMP version %d.%d\n", 5031 bmp_version_major, bmp_version_minor); 5032 5033 /* 5034 * Make sure that 0x36 is blank and can't be mistaken for a DCB 5035 * pointer on early versions 5036 */ 5037 if (bmp_version_major < 5) 5038 *(uint16_t *)&bios->data[0x36] = 0; 5039 5040 /* 5041 * Seems that the minor version was 1 for all major versions prior 5042 * to 5. Version 6 could theoretically exist, but I suspect BIT 5043 * happened instead. 5044 */ 5045 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) { 5046 NV_ERROR(dev, "You have an unsupported BMP version. " 5047 "Please send in your bios\n"); 5048 return -ENOSYS; 5049 } 5050 5051 if (bmp_version_major == 0) 5052 /* nothing that's currently useful in this version */ 5053 return 0; 5054 else if (bmp_version_major == 1) 5055 bmplength = 44; /* exact for 1.01 */ 5056 else if (bmp_version_major == 2) 5057 bmplength = 48; /* exact for 2.01 */ 5058 else if (bmp_version_major == 3) 5059 bmplength = 54; 5060 /* guessed - mem init tables added in this version */ 5061 else if (bmp_version_major == 4 || bmp_version_minor < 0x1) 5062 /* don't know if 5.0 exists... */ 5063 bmplength = 62; 5064 /* guessed - BMP I2C indices added in version 4*/ 5065 else if (bmp_version_minor < 0x6) 5066 bmplength = 67; /* exact for 5.01 */ 5067 else if (bmp_version_minor < 0x10) 5068 bmplength = 75; /* exact for 5.06 */ 5069 else if (bmp_version_minor == 0x10) 5070 bmplength = 89; /* exact for 5.10h */ 5071 else if (bmp_version_minor < 0x14) 5072 bmplength = 118; /* exact for 5.11h */ 5073 else if (bmp_version_minor < 0x24) 5074 /* 5075 * Not sure of version where pll limits came in; 5076 * certainly exist by 0x24 though. 5077 */ 5078 /* length not exact: this is long enough to get lvds members */ 5079 bmplength = 123; 5080 else if (bmp_version_minor < 0x27) 5081 /* 5082 * Length not exact: this is long enough to get pll limit 5083 * member 5084 */ 5085 bmplength = 144; 5086 else 5087 /* 5088 * Length not exact: this is long enough to get dual link 5089 * transition clock. 5090 */ 5091 bmplength = 158; 5092 5093 /* checksum */ 5094 if (nv_cksum(bmp, 8)) { 5095 NV_ERROR(dev, "Bad BMP checksum\n"); 5096 return -EINVAL; 5097 } 5098 5099 /* 5100 * Bit 4 seems to indicate either a mobile bios or a quadro card -- 5101 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl 5102 * (not nv10gl), bit 5 that the flat panel tables are present, and 5103 * bit 6 a tv bios. 5104 */ 5105 bios->feature_byte = bmp[9]; 5106 5107 parse_bios_version(dev, bios, offset + 10); 5108 5109 if (bmp_version_major < 5 || bmp_version_minor < 0x10) 5110 bios->old_style_init = true; 5111 legacy_scripts_offset = 18; 5112 if (bmp_version_major < 2) 5113 legacy_scripts_offset -= 4; 5114 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]); 5115 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]); 5116 5117 if (bmp_version_major > 2) { /* appears in BMP 3 */ 5118 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]); 5119 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]); 5120 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]); 5121 } 5122 5123 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */ 5124 if (bmplength > 61) 5125 legacy_i2c_offset = offset + 54; 5126 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset]; 5127 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1]; 5128 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2]; 5129 bios->dcb.i2c[0].write = bios->data[legacy_i2c_offset + 4]; 5130 bios->dcb.i2c[0].read = bios->data[legacy_i2c_offset + 5]; 5131 bios->dcb.i2c[1].write = bios->data[legacy_i2c_offset + 6]; 5132 bios->dcb.i2c[1].read = bios->data[legacy_i2c_offset + 7]; 5133 5134 if (bmplength > 74) { 5135 bios->fmaxvco = ROM32(bmp[67]); 5136 bios->fminvco = ROM32(bmp[71]); 5137 } 5138 if (bmplength > 88) 5139 parse_script_table_pointers(bios, offset + 75); 5140 if (bmplength > 94) { 5141 bios->tmds.output0_script_ptr = ROM16(bmp[89]); 5142 bios->tmds.output1_script_ptr = ROM16(bmp[91]); 5143 /* 5144 * Never observed in use with lvds scripts, but is reused for 5145 * 18/24 bit panel interface default for EDID equipped panels 5146 * (if_is_24bit not set directly to avoid any oscillation). 5147 */ 5148 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]); 5149 } 5150 if (bmplength > 108) { 5151 bios->fp.fptablepointer = ROM16(bmp[105]); 5152 bios->fp.fpxlatetableptr = ROM16(bmp[107]); 5153 bios->fp.xlatwidth = 1; 5154 } 5155 if (bmplength > 120) { 5156 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]); 5157 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]); 5158 } 5159 if (bmplength > 143) 5160 bios->pll_limit_tbl_ptr = ROM16(bmp[142]); 5161 5162 if (bmplength > 157) 5163 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10; 5164 5165 return 0; 5166} 5167 5168static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len) 5169{ 5170 int i, j; 5171 5172 for (i = 0; i <= (n - len); i++) { 5173 for (j = 0; j < len; j++) 5174 if (data[i + j] != str[j]) 5175 break; 5176 if (j == len) 5177 return i; 5178 } 5179 5180 return 0; 5181} 5182 5183static struct dcb_gpio_entry * 5184new_gpio_entry(struct nvbios *bios) 5185{ 5186 struct dcb_gpio_table *gpio = &bios->dcb.gpio; 5187 5188 return &gpio->entry[gpio->entries++]; 5189} 5190 5191struct dcb_gpio_entry * 5192nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag) 5193{ 5194 struct drm_nouveau_private *dev_priv = dev->dev_private; 5195 struct nvbios *bios = &dev_priv->vbios; 5196 int i; 5197 5198 for (i = 0; i < bios->dcb.gpio.entries; i++) { 5199 if (bios->dcb.gpio.entry[i].tag != tag) 5200 continue; 5201 5202 return &bios->dcb.gpio.entry[i]; 5203 } 5204 5205 return NULL; 5206} 5207 5208static void 5209parse_dcb30_gpio_entry(struct nvbios *bios, uint16_t offset) 5210{ 5211 struct dcb_gpio_entry *gpio; 5212 uint16_t ent = ROM16(bios->data[offset]); 5213 uint8_t line = ent & 0x1f, 5214 tag = ent >> 5 & 0x3f, 5215 flags = ent >> 11 & 0x1f; 5216 5217 if (tag == 0x3f) 5218 return; 5219 5220 gpio = new_gpio_entry(bios); 5221 5222 gpio->tag = tag; 5223 gpio->line = line; 5224 gpio->invert = flags != 4; 5225 gpio->entry = ent; 5226} 5227 5228static void 5229parse_dcb40_gpio_entry(struct nvbios *bios, uint16_t offset) 5230{ 5231 uint32_t entry = ROM32(bios->data[offset]); 5232 struct dcb_gpio_entry *gpio; 5233 5234 if ((entry & 0x0000ff00) == 0x0000ff00) 5235 return; 5236 5237 gpio = new_gpio_entry(bios); 5238 gpio->tag = (entry & 0x0000ff00) >> 8; 5239 gpio->line = (entry & 0x0000001f) >> 0; 5240 gpio->state_default = (entry & 0x01000000) >> 24; 5241 gpio->state[0] = (entry & 0x18000000) >> 27; 5242 gpio->state[1] = (entry & 0x60000000) >> 29; 5243 gpio->entry = entry; 5244} 5245 5246static void 5247parse_dcb_gpio_table(struct nvbios *bios) 5248{ 5249 struct drm_device *dev = bios->dev; 5250 uint16_t gpio_table_ptr = bios->dcb.gpio_table_ptr; 5251 uint8_t *gpio_table = &bios->data[gpio_table_ptr]; 5252 int header_len = gpio_table[1], 5253 entries = gpio_table[2], 5254 entry_len = gpio_table[3]; 5255 void (*parse_entry)(struct nvbios *, uint16_t) = NULL; 5256 int i; 5257 5258 if (bios->dcb.version >= 0x40) { 5259 if (gpio_table_ptr && entry_len != 4) { 5260 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n"); 5261 return; 5262 } 5263 5264 parse_entry = parse_dcb40_gpio_entry; 5265 5266 } else if (bios->dcb.version >= 0x30) { 5267 if (gpio_table_ptr && entry_len != 2) { 5268 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n"); 5269 return; 5270 } 5271 5272 parse_entry = parse_dcb30_gpio_entry; 5273 5274 } else if (bios->dcb.version >= 0x22) { 5275 /* 5276 * DCBs older than v3.0 don't really have a GPIO 5277 * table, instead they keep some GPIO info at fixed 5278 * locations. 5279 */ 5280 uint16_t dcbptr = ROM16(bios->data[0x36]); 5281 uint8_t *tvdac_gpio = &bios->data[dcbptr - 5]; 5282 5283 if (tvdac_gpio[0] & 1) { 5284 struct dcb_gpio_entry *gpio = new_gpio_entry(bios); 5285 5286 gpio->tag = DCB_GPIO_TVDAC0; 5287 gpio->line = tvdac_gpio[1] >> 4; 5288 gpio->invert = tvdac_gpio[0] & 2; 5289 } 5290 } 5291 5292 if (!gpio_table_ptr) 5293 return; 5294 5295 if (entries > DCB_MAX_NUM_GPIO_ENTRIES) { 5296 NV_WARN(dev, "Too many entries in the DCB GPIO table.\n"); 5297 entries = DCB_MAX_NUM_GPIO_ENTRIES; 5298 } 5299 5300 for (i = 0; i < entries; i++) 5301 parse_entry(bios, gpio_table_ptr + header_len + entry_len * i); 5302} 5303 5304struct dcb_connector_table_entry * 5305nouveau_bios_connector_entry(struct drm_device *dev, int index) 5306{ 5307 struct drm_nouveau_private *dev_priv = dev->dev_private; 5308 struct nvbios *bios = &dev_priv->vbios; 5309 struct dcb_connector_table_entry *cte; 5310 5311 if (index >= bios->dcb.connector.entries) 5312 return NULL; 5313 5314 cte = &bios->dcb.connector.entry[index]; 5315 if (cte->type == 0xff) 5316 return NULL; 5317 5318 return cte; 5319} 5320 5321static enum dcb_connector_type 5322divine_connector_type(struct nvbios *bios, int index) 5323{ 5324 struct dcb_table *dcb = &bios->dcb; 5325 unsigned encoders = 0, type = DCB_CONNECTOR_NONE; 5326 int i; 5327 5328 for (i = 0; i < dcb->entries; i++) { 5329 if (dcb->entry[i].connector == index) 5330 encoders |= (1 << dcb->entry[i].type); 5331 } 5332 5333 if (encoders & (1 << OUTPUT_DP)) { 5334 if (encoders & (1 << OUTPUT_TMDS)) 5335 type = DCB_CONNECTOR_DP; 5336 else 5337 type = DCB_CONNECTOR_eDP; 5338 } else 5339 if (encoders & (1 << OUTPUT_TMDS)) { 5340 if (encoders & (1 << OUTPUT_ANALOG)) 5341 type = DCB_CONNECTOR_DVI_I; 5342 else 5343 type = DCB_CONNECTOR_DVI_D; 5344 } else 5345 if (encoders & (1 << OUTPUT_ANALOG)) { 5346 type = DCB_CONNECTOR_VGA; 5347 } else 5348 if (encoders & (1 << OUTPUT_LVDS)) { 5349 type = DCB_CONNECTOR_LVDS; 5350 } else 5351 if (encoders & (1 << OUTPUT_TV)) { 5352 type = DCB_CONNECTOR_TV_0; 5353 } 5354 5355 return type; 5356} 5357 5358static void 5359apply_dcb_connector_quirks(struct nvbios *bios, int idx) 5360{ 5361 struct dcb_connector_table_entry *cte = &bios->dcb.connector.entry[idx]; 5362 struct drm_device *dev = bios->dev; 5363 5364 /* Gigabyte NX85T */ 5365 if ((dev->pdev->device == 0x0421) && 5366 (dev->pdev->subsystem_vendor == 0x1458) && 5367 (dev->pdev->subsystem_device == 0x344c)) { 5368 if (cte->type == DCB_CONNECTOR_HDMI_1) 5369 cte->type = DCB_CONNECTOR_DVI_I; 5370 } 5371} 5372 5373static void 5374parse_dcb_connector_table(struct nvbios *bios) 5375{ 5376 struct drm_device *dev = bios->dev; 5377 struct dcb_connector_table *ct = &bios->dcb.connector; 5378 struct dcb_connector_table_entry *cte; 5379 uint8_t *conntab = &bios->data[bios->dcb.connector_table_ptr]; 5380 uint8_t *entry; 5381 int i; 5382 5383 if (!bios->dcb.connector_table_ptr) { 5384 NV_DEBUG_KMS(dev, "No DCB connector table present\n"); 5385 return; 5386 } 5387 5388 NV_INFO(dev, "DCB connector table: VHER 0x%02x %d %d %d\n", 5389 conntab[0], conntab[1], conntab[2], conntab[3]); 5390 if ((conntab[0] != 0x30 && conntab[0] != 0x40) || 5391 (conntab[3] != 2 && conntab[3] != 4)) { 5392 NV_ERROR(dev, " Unknown! Please report.\n"); 5393 return; 5394 } 5395 5396 ct->entries = conntab[2]; 5397 5398 entry = conntab + conntab[1]; 5399 cte = &ct->entry[0]; 5400 for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) { 5401 cte->index = i; 5402 if (conntab[3] == 2) 5403 cte->entry = ROM16(entry[0]); 5404 else 5405 cte->entry = ROM32(entry[0]); 5406 5407 cte->type = (cte->entry & 0x000000ff) >> 0; 5408 cte->index2 = (cte->entry & 0x00000f00) >> 8; 5409 switch (cte->entry & 0x00033000) { 5410 case 0x00001000: 5411 cte->gpio_tag = 0x07; 5412 break; 5413 case 0x00002000: 5414 cte->gpio_tag = 0x08; 5415 break; 5416 case 0x00010000: 5417 cte->gpio_tag = 0x51; 5418 break; 5419 case 0x00020000: 5420 cte->gpio_tag = 0x52; 5421 break; 5422 default: 5423 cte->gpio_tag = 0xff; 5424 break; 5425 } 5426 5427 if (cte->type == 0xff) 5428 continue; 5429 5430 apply_dcb_connector_quirks(bios, i); 5431 5432 NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n", 5433 i, cte->entry, cte->type, cte->index, cte->gpio_tag); 5434 5435 /* check for known types, fallback to guessing the type 5436 * from attached encoders if we hit an unknown. 5437 */ 5438 switch (cte->type) { 5439 case DCB_CONNECTOR_VGA: 5440 case DCB_CONNECTOR_TV_0: 5441 case DCB_CONNECTOR_TV_1: 5442 case DCB_CONNECTOR_TV_3: 5443 case DCB_CONNECTOR_DVI_I: 5444 case DCB_CONNECTOR_DVI_D: 5445 case DCB_CONNECTOR_LVDS: 5446 case DCB_CONNECTOR_DP: 5447 case DCB_CONNECTOR_eDP: 5448 case DCB_CONNECTOR_HDMI_0: 5449 case DCB_CONNECTOR_HDMI_1: 5450 break; 5451 default: 5452 cte->type = divine_connector_type(bios, cte->index); 5453 NV_WARN(dev, "unknown type, using 0x%02x\n", cte->type); 5454 break; 5455 } 5456 5457 if (nouveau_override_conntype) { 5458 int type = divine_connector_type(bios, cte->index); 5459 if (type != cte->type) 5460 NV_WARN(dev, " -> type 0x%02x\n", cte->type); 5461 } 5462 5463 } 5464} 5465 5466static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb) 5467{ 5468 struct dcb_entry *entry = &dcb->entry[dcb->entries]; 5469 5470 memset(entry, 0, sizeof(struct dcb_entry)); 5471 entry->index = dcb->entries++; 5472 5473 return entry; 5474} 5475 5476static void fabricate_vga_output(struct dcb_table *dcb, int i2c, int heads) 5477{ 5478 struct dcb_entry *entry = new_dcb_entry(dcb); 5479 5480 entry->type = 0; 5481 entry->i2c_index = i2c; 5482 entry->heads = heads; 5483 entry->location = DCB_LOC_ON_CHIP; 5484 /* "or" mostly unused in early gen crt modesetting, 0 is fine */ 5485} 5486 5487static void fabricate_dvi_i_output(struct dcb_table *dcb, bool twoHeads) 5488{ 5489 struct dcb_entry *entry = new_dcb_entry(dcb); 5490 5491 entry->type = 2; 5492 entry->i2c_index = LEGACY_I2C_PANEL; 5493 entry->heads = twoHeads ? 3 : 1; 5494 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */ 5495 entry->or = 1; /* means |0x10 gets set on CRE_LCD__INDEX */ 5496 entry->duallink_possible = false; /* SiI164 and co. are single link */ 5497 5498#if 0 5499 /* 5500 * For dvi-a either crtc probably works, but my card appears to only 5501 * support dvi-d. "nvidia" still attempts to program it for dvi-a, 5502 * doing the full fp output setup (program 0x6808.. fp dimension regs, 5503 * setting 0x680848 to 0x10000111 to enable, maybe setting 0x680880); 5504 * the monitor picks up the mode res ok and lights up, but no pixel 5505 * data appears, so the board manufacturer probably connected up the 5506 * sync lines, but missed the video traces / components 5507 * 5508 * with this introduction, dvi-a left as an exercise for the reader. 5509 */ 5510 fabricate_vga_output(dcb, LEGACY_I2C_PANEL, entry->heads); 5511#endif 5512} 5513 5514static void fabricate_tv_output(struct dcb_table *dcb, bool twoHeads) 5515{ 5516 struct dcb_entry *entry = new_dcb_entry(dcb); 5517 5518 entry->type = 1; 5519 entry->i2c_index = LEGACY_I2C_TV; 5520 entry->heads = twoHeads ? 3 : 1; 5521 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */ 5522} 5523 5524static bool 5525parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb, 5526 uint32_t conn, uint32_t conf, struct dcb_entry *entry) 5527{ 5528 entry->type = conn & 0xf; 5529 entry->i2c_index = (conn >> 4) & 0xf; 5530 entry->heads = (conn >> 8) & 0xf; 5531 if (dcb->version >= 0x40) 5532 entry->connector = (conn >> 12) & 0xf; 5533 entry->bus = (conn >> 16) & 0xf; 5534 entry->location = (conn >> 20) & 0x3; 5535 entry->or = (conn >> 24) & 0xf; 5536 /* 5537 * Normal entries consist of a single bit, but dual link has the 5538 * next most significant bit set too 5539 */ 5540 entry->duallink_possible = 5541 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or); 5542 5543 switch (entry->type) { 5544 case OUTPUT_ANALOG: 5545 /* 5546 * Although the rest of a CRT conf dword is usually 5547 * zeros, mac biosen have stuff there so we must mask 5548 */ 5549 entry->crtconf.maxfreq = (dcb->version < 0x30) ? 5550 (conf & 0xffff) * 10 : 5551 (conf & 0xff) * 10000; 5552 break; 5553 case OUTPUT_LVDS: 5554 { 5555 uint32_t mask; 5556 if (conf & 0x1) 5557 entry->lvdsconf.use_straps_for_mode = true; 5558 if (dcb->version < 0x22) { 5559 mask = ~0xd; 5560 /* 5561 * The laptop in bug 14567 lies and claims to not use 5562 * straps when it does, so assume all DCB 2.0 laptops 5563 * use straps, until a broken EDID using one is produced 5564 */ 5565 entry->lvdsconf.use_straps_for_mode = true; 5566 /* 5567 * Both 0x4 and 0x8 show up in v2.0 tables; assume they 5568 * mean the same thing (probably wrong, but might work) 5569 */ 5570 if (conf & 0x4 || conf & 0x8) 5571 entry->lvdsconf.use_power_scripts = true; 5572 } else { 5573 mask = ~0x5; 5574 if (conf & 0x4) 5575 entry->lvdsconf.use_power_scripts = true; 5576 } 5577 if (conf & mask) { 5578 /* 5579 * Until we even try to use these on G8x, it's 5580 * useless reporting unknown bits. They all are. 5581 */ 5582 if (dcb->version >= 0x40) 5583 break; 5584 5585 NV_ERROR(dev, "Unknown LVDS configuration bits, " 5586 "please report\n"); 5587 } 5588 break; 5589 } 5590 case OUTPUT_TV: 5591 { 5592 if (dcb->version >= 0x30) 5593 entry->tvconf.has_component_output = conf & (0x8 << 4); 5594 else 5595 entry->tvconf.has_component_output = false; 5596 5597 break; 5598 } 5599 case OUTPUT_DP: 5600 entry->dpconf.sor.link = (conf & 0x00000030) >> 4; 5601 entry->dpconf.link_bw = (conf & 0x00e00000) >> 21; 5602 switch ((conf & 0x0f000000) >> 24) { 5603 case 0xf: 5604 entry->dpconf.link_nr = 4; 5605 break; 5606 case 0x3: 5607 entry->dpconf.link_nr = 2; 5608 break; 5609 default: 5610 entry->dpconf.link_nr = 1; 5611 break; 5612 } 5613 break; 5614 case OUTPUT_TMDS: 5615 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4; 5616 break; 5617 case 0xe: 5618 /* weird g80 mobile type that "nv" treats as a terminator */ 5619 dcb->entries--; 5620 return false; 5621 default: 5622 break; 5623 } 5624 5625 /* unsure what DCB version introduces this, 3.0? */ 5626 if (conf & 0x100000) 5627 entry->i2c_upper_default = true; 5628 5629 return true; 5630} 5631 5632static bool 5633parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb, 5634 uint32_t conn, uint32_t conf, struct dcb_entry *entry) 5635{ 5636 switch (conn & 0x0000000f) { 5637 case 0: 5638 entry->type = OUTPUT_ANALOG; 5639 break; 5640 case 1: 5641 entry->type = OUTPUT_TV; 5642 break; 5643 case 2: 5644 case 3: 5645 entry->type = OUTPUT_LVDS; 5646 break; 5647 case 4: 5648 switch ((conn & 0x000000f0) >> 4) { 5649 case 0: 5650 entry->type = OUTPUT_TMDS; 5651 break; 5652 case 1: 5653 entry->type = OUTPUT_LVDS; 5654 break; 5655 default: 5656 NV_ERROR(dev, "Unknown DCB subtype 4/%d\n", 5657 (conn & 0x000000f0) >> 4); 5658 return false; 5659 } 5660 break; 5661 default: 5662 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f); 5663 return false; 5664 } 5665 5666 entry->i2c_index = (conn & 0x0003c000) >> 14; 5667 entry->heads = ((conn & 0x001c0000) >> 18) + 1; 5668 entry->or = entry->heads; /* same as heads, hopefully safe enough */ 5669 entry->location = (conn & 0x01e00000) >> 21; 5670 entry->bus = (conn & 0x0e000000) >> 25; 5671 entry->duallink_possible = false; 5672 5673 switch (entry->type) { 5674 case OUTPUT_ANALOG: 5675 entry->crtconf.maxfreq = (conf & 0xffff) * 10; 5676 break; 5677 case OUTPUT_TV: 5678 entry->tvconf.has_component_output = false; 5679 break; 5680 case OUTPUT_TMDS: 5681 /* 5682 * Invent a DVI-A output, by copying the fields of the DVI-D 5683 * output; reported to work by math_b on an NV20(!). 5684 */ 5685 fabricate_vga_output(dcb, entry->i2c_index, entry->heads); 5686 break; 5687 case OUTPUT_LVDS: 5688 if ((conn & 0x00003f00) != 0x10) 5689 entry->lvdsconf.use_straps_for_mode = true; 5690 entry->lvdsconf.use_power_scripts = true; 5691 break; 5692 default: 5693 break; 5694 } 5695 5696 return true; 5697} 5698 5699static bool parse_dcb_entry(struct drm_device *dev, struct dcb_table *dcb, 5700 uint32_t conn, uint32_t conf) 5701{ 5702 struct dcb_entry *entry = new_dcb_entry(dcb); 5703 bool ret; 5704 5705 if (dcb->version >= 0x20) 5706 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry); 5707 else 5708 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry); 5709 if (!ret) 5710 return ret; 5711 5712 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table, 5713 entry->i2c_index, &dcb->i2c[entry->i2c_index]); 5714 5715 return true; 5716} 5717 5718static 5719void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb) 5720{ 5721 /* 5722 * DCB v2.0 lists each output combination separately. 5723 * Here we merge compatible entries to have fewer outputs, with 5724 * more options 5725 */ 5726 5727 int i, newentries = 0; 5728 5729 for (i = 0; i < dcb->entries; i++) { 5730 struct dcb_entry *ient = &dcb->entry[i]; 5731 int j; 5732 5733 for (j = i + 1; j < dcb->entries; j++) { 5734 struct dcb_entry *jent = &dcb->entry[j]; 5735 5736 if (jent->type == 100) /* already merged entry */ 5737 continue; 5738 5739 /* merge heads field when all other fields the same */ 5740 if (jent->i2c_index == ient->i2c_index && 5741 jent->type == ient->type && 5742 jent->location == ient->location && 5743 jent->or == ient->or) { 5744 NV_TRACE(dev, "Merging DCB entries %d and %d\n", 5745 i, j); 5746 ient->heads |= jent->heads; 5747 jent->type = 100; /* dummy value */ 5748 } 5749 } 5750 } 5751 5752 /* Compact entries merged into others out of dcb */ 5753 for (i = 0; i < dcb->entries; i++) { 5754 if (dcb->entry[i].type == 100) 5755 continue; 5756 5757 if (newentries != i) { 5758 dcb->entry[newentries] = dcb->entry[i]; 5759 dcb->entry[newentries].index = newentries; 5760 } 5761 newentries++; 5762 } 5763 5764 dcb->entries = newentries; 5765} 5766 5767static int 5768parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads) 5769{ 5770 struct drm_nouveau_private *dev_priv = dev->dev_private; 5771 struct dcb_table *dcb = &bios->dcb; 5772 uint16_t dcbptr = 0, i2ctabptr = 0; 5773 uint8_t *dcbtable; 5774 uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES; 5775 bool configblock = true; 5776 int recordlength = 8, confofs = 4; 5777 int i; 5778 5779 /* get the offset from 0x36 */ 5780 if (dev_priv->card_type > NV_04) { 5781 dcbptr = ROM16(bios->data[0x36]); 5782 if (dcbptr == 0x0000) 5783 NV_WARN(dev, "No output data (DCB) found in BIOS\n"); 5784 } 5785 5786 /* this situation likely means a really old card, pre DCB */ 5787 if (dcbptr == 0x0) { 5788 NV_INFO(dev, "Assuming a CRT output exists\n"); 5789 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1); 5790 5791 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0) 5792 fabricate_tv_output(dcb, twoHeads); 5793 5794 return 0; 5795 } 5796 5797 dcbtable = &bios->data[dcbptr]; 5798 5799 /* get DCB version */ 5800 dcb->version = dcbtable[0]; 5801 NV_TRACE(dev, "Found Display Configuration Block version %d.%d\n", 5802 dcb->version >> 4, dcb->version & 0xf); 5803 5804 if (dcb->version >= 0x20) { /* NV17+ */ 5805 uint32_t sig; 5806 5807 if (dcb->version >= 0x30) { /* NV40+ */ 5808 headerlen = dcbtable[1]; 5809 entries = dcbtable[2]; 5810 recordlength = dcbtable[3]; 5811 i2ctabptr = ROM16(dcbtable[4]); 5812 sig = ROM32(dcbtable[6]); 5813 dcb->gpio_table_ptr = ROM16(dcbtable[10]); 5814 dcb->connector_table_ptr = ROM16(dcbtable[20]); 5815 } else { 5816 i2ctabptr = ROM16(dcbtable[2]); 5817 sig = ROM32(dcbtable[4]); 5818 headerlen = 8; 5819 } 5820 5821 if (sig != 0x4edcbdcb) { 5822 NV_ERROR(dev, "Bad Display Configuration Block " 5823 "signature (%08X)\n", sig); 5824 return -EINVAL; 5825 } 5826 } else if (dcb->version >= 0x15) { /* some NV11 and NV20 */ 5827 char sig[8] = { 0 }; 5828 5829 strncpy(sig, (char *)&dcbtable[-7], 7); 5830 i2ctabptr = ROM16(dcbtable[2]); 5831 recordlength = 10; 5832 confofs = 6; 5833 5834 if (strcmp(sig, "DEV_REC")) { 5835 NV_ERROR(dev, "Bad Display Configuration Block " 5836 "signature (%s)\n", sig); 5837 return -EINVAL; 5838 } 5839 } else { 5840 /* 5841 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always 5842 * has the same single (crt) entry, even when tv-out present, so 5843 * the conclusion is this version cannot really be used. 5844 * v1.2 tables (some NV6/10, and NV15+) normally have the same 5845 * 5 entries, which are not specific to the card and so no use. 5846 * v1.2 does have an I2C table that read_dcb_i2c_table can 5847 * handle, but cards exist (nv11 in #14821) with a bad i2c table 5848 * pointer, so use the indices parsed in parse_bmp_structure. 5849 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful 5850 */ 5851 NV_TRACEWARN(dev, "No useful information in BIOS output table; " 5852 "adding all possible outputs\n"); 5853 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1); 5854 5855 /* 5856 * Attempt to detect TV before DVI because the test 5857 * for the former is more accurate and it rules the 5858 * latter out. 5859 */ 5860 if (nv04_tv_identify(dev, 5861 bios->legacy.i2c_indices.tv) >= 0) 5862 fabricate_tv_output(dcb, twoHeads); 5863 5864 else if (bios->tmds.output0_script_ptr || 5865 bios->tmds.output1_script_ptr) 5866 fabricate_dvi_i_output(dcb, twoHeads); 5867 5868 return 0; 5869 } 5870 5871 if (!i2ctabptr) 5872 NV_WARN(dev, "No pointer to DCB I2C port table\n"); 5873 else { 5874 dcb->i2c_table = &bios->data[i2ctabptr]; 5875 if (dcb->version >= 0x30) 5876 dcb->i2c_default_indices = dcb->i2c_table[4]; 5877 } 5878 5879 if (entries > DCB_MAX_NUM_ENTRIES) 5880 entries = DCB_MAX_NUM_ENTRIES; 5881 5882 for (i = 0; i < entries; i++) { 5883 uint32_t connection, config = 0; 5884 5885 connection = ROM32(dcbtable[headerlen + recordlength * i]); 5886 if (configblock) 5887 config = ROM32(dcbtable[headerlen + confofs + recordlength * i]); 5888 5889 /* seen on an NV11 with DCB v1.5 */ 5890 if (connection == 0x00000000) 5891 break; 5892 5893 /* seen on an NV17 with DCB v2.0 */ 5894 if (connection == 0xffffffff) 5895 break; 5896 5897 if ((connection & 0x0000000f) == 0x0000000f) 5898 continue; 5899 5900 NV_TRACEWARN(dev, "Raw DCB entry %d: %08x %08x\n", 5901 dcb->entries, connection, config); 5902 5903 if (!parse_dcb_entry(dev, dcb, connection, config)) 5904 break; 5905 } 5906 5907 /* 5908 * apart for v2.1+ not being known for requiring merging, this 5909 * guarantees dcbent->index is the index of the entry in the rom image 5910 */ 5911 if (dcb->version < 0x21) 5912 merge_like_dcb_entries(dev, dcb); 5913 5914 if (!dcb->entries) 5915 return -ENXIO; 5916 5917 parse_dcb_gpio_table(bios); 5918 parse_dcb_connector_table(bios); 5919 return 0; 5920} 5921 5922static void 5923fixup_legacy_connector(struct nvbios *bios) 5924{ 5925 struct dcb_table *dcb = &bios->dcb; 5926 int i, i2c, i2c_conn[DCB_MAX_NUM_I2C_ENTRIES] = { }; 5927 5928 /* 5929 * DCB 3.0 also has the table in most cases, but there are some cards 5930 * where the table is filled with stub entries, and the DCB entriy 5931 * indices are all 0. We don't need the connector indices on pre-G80 5932 * chips (yet?) so limit the use to DCB 4.0 and above. 5933 */ 5934 if (dcb->version >= 0x40) 5935 return; 5936 5937 dcb->connector.entries = 0; 5938 5939 /* 5940 * No known connector info before v3.0, so make it up. the rule here 5941 * is: anything on the same i2c bus is considered to be on the same 5942 * connector. any output without an associated i2c bus is assigned 5943 * its own unique connector index. 5944 */ 5945 for (i = 0; i < dcb->entries; i++) { 5946 /* 5947 * Ignore the I2C index for on-chip TV-out, as there 5948 * are cards with bogus values (nv31m in bug 23212), 5949 * and it's otherwise useless. 5950 */ 5951 if (dcb->entry[i].type == OUTPUT_TV && 5952 dcb->entry[i].location == DCB_LOC_ON_CHIP) 5953 dcb->entry[i].i2c_index = 0xf; 5954 i2c = dcb->entry[i].i2c_index; 5955 5956 if (i2c_conn[i2c]) { 5957 dcb->entry[i].connector = i2c_conn[i2c] - 1; 5958 continue; 5959 } 5960 5961 dcb->entry[i].connector = dcb->connector.entries++; 5962 if (i2c != 0xf) 5963 i2c_conn[i2c] = dcb->connector.entries; 5964 } 5965 5966 /* Fake the connector table as well as just connector indices */ 5967 for (i = 0; i < dcb->connector.entries; i++) { 5968 dcb->connector.entry[i].index = i; 5969 dcb->connector.entry[i].type = divine_connector_type(bios, i); 5970 dcb->connector.entry[i].gpio_tag = 0xff; 5971 } 5972} 5973 5974static void 5975fixup_legacy_i2c(struct nvbios *bios) 5976{ 5977 struct dcb_table *dcb = &bios->dcb; 5978 int i; 5979 5980 for (i = 0; i < dcb->entries; i++) { 5981 if (dcb->entry[i].i2c_index == LEGACY_I2C_CRT) 5982 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.crt; 5983 if (dcb->entry[i].i2c_index == LEGACY_I2C_PANEL) 5984 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.panel; 5985 if (dcb->entry[i].i2c_index == LEGACY_I2C_TV) 5986 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.tv; 5987 } 5988} 5989 5990static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry) 5991{ 5992 /* 5993 * The header following the "HWSQ" signature has the number of entries, 5994 * and the entry size 5995 * 5996 * An entry consists of a dword to write to the sequencer control reg 5997 * (0x00001304), followed by the ucode bytes, written sequentially, 5998 * starting at reg 0x00001400 5999 */ 6000 6001 uint8_t bytes_to_write; 6002 uint16_t hwsq_entry_offset; 6003 int i; 6004 6005 if (bios->data[hwsq_offset] <= entry) { 6006 NV_ERROR(dev, "Too few entries in HW sequencer table for " 6007 "requested entry\n"); 6008 return -ENOENT; 6009 } 6010 6011 bytes_to_write = bios->data[hwsq_offset + 1]; 6012 6013 if (bytes_to_write != 36) { 6014 NV_ERROR(dev, "Unknown HW sequencer entry size\n"); 6015 return -EINVAL; 6016 } 6017 6018 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n"); 6019 6020 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write; 6021 6022 /* set sequencer control */ 6023 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset])); 6024 bytes_to_write -= 4; 6025 6026 /* write ucode */ 6027 for (i = 0; i < bytes_to_write; i += 4) 6028 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4])); 6029 6030 /* twiddle NV_PBUS_DEBUG_4 */ 6031 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18); 6032 6033 return 0; 6034} 6035 6036static int load_nv17_hw_sequencer_ucode(struct drm_device *dev, 6037 struct nvbios *bios) 6038{ 6039 /* 6040 * BMP based cards, from NV17, need a microcode loading to correctly 6041 * control the GPIO etc for LVDS panels 6042 * 6043 * BIT based cards seem to do this directly in the init scripts 6044 * 6045 * The microcode entries are found by the "HWSQ" signature. 6046 */ 6047 6048 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' }; 6049 const int sz = sizeof(hwsq_signature); 6050 int hwsq_offset; 6051 6052 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz); 6053 if (!hwsq_offset) 6054 return 0; 6055 6056 /* always use entry 0? */ 6057 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0); 6058} 6059 6060uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev) 6061{ 6062 struct drm_nouveau_private *dev_priv = dev->dev_private; 6063 struct nvbios *bios = &dev_priv->vbios; 6064 const uint8_t edid_sig[] = { 6065 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 }; 6066 uint16_t offset = 0; 6067 uint16_t newoffset; 6068 int searchlen = NV_PROM_SIZE; 6069 6070 if (bios->fp.edid) 6071 return bios->fp.edid; 6072 6073 while (searchlen) { 6074 newoffset = findstr(&bios->data[offset], searchlen, 6075 edid_sig, 8); 6076 if (!newoffset) 6077 return NULL; 6078 offset += newoffset; 6079 if (!nv_cksum(&bios->data[offset], EDID1_LEN)) 6080 break; 6081 6082 searchlen -= offset; 6083 offset++; 6084 } 6085 6086 NV_TRACE(dev, "Found EDID in BIOS\n"); 6087 6088 return bios->fp.edid = &bios->data[offset]; 6089} 6090 6091void 6092nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table, 6093 struct dcb_entry *dcbent) 6094{ 6095 struct drm_nouveau_private *dev_priv = dev->dev_private; 6096 struct nvbios *bios = &dev_priv->vbios; 6097 struct init_exec iexec = { true, false }; 6098 6099 mutex_lock(&bios->lock); 6100 bios->display.output = dcbent; 6101 parse_init_table(bios, table, &iexec); 6102 bios->display.output = NULL; 6103 mutex_unlock(&bios->lock); 6104} 6105 6106static bool NVInitVBIOS(struct drm_device *dev) 6107{ 6108 struct drm_nouveau_private *dev_priv = dev->dev_private; 6109 struct nvbios *bios = &dev_priv->vbios; 6110 6111 memset(bios, 0, sizeof(struct nvbios)); 6112 mutex_init(&bios->lock); 6113 bios->dev = dev; 6114 6115 if (!NVShadowVBIOS(dev, bios->data)) 6116 return false; 6117 6118 bios->length = NV_PROM_SIZE; 6119 return true; 6120} 6121 6122static int nouveau_parse_vbios_struct(struct drm_device *dev) 6123{ 6124 struct drm_nouveau_private *dev_priv = dev->dev_private; 6125 struct nvbios *bios = &dev_priv->vbios; 6126 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' }; 6127 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 }; 6128 int offset; 6129 6130 offset = findstr(bios->data, bios->length, 6131 bit_signature, sizeof(bit_signature)); 6132 if (offset) { 6133 NV_TRACE(dev, "BIT BIOS found\n"); 6134 return parse_bit_structure(bios, offset + 6); 6135 } 6136 6137 offset = findstr(bios->data, bios->length, 6138 bmp_signature, sizeof(bmp_signature)); 6139 if (offset) { 6140 NV_TRACE(dev, "BMP BIOS found\n"); 6141 return parse_bmp_structure(dev, bios, offset); 6142 } 6143 6144 NV_ERROR(dev, "No known BIOS signature found\n"); 6145 return -ENODEV; 6146} 6147 6148int 6149nouveau_run_vbios_init(struct drm_device *dev) 6150{ 6151 struct drm_nouveau_private *dev_priv = dev->dev_private; 6152 struct nvbios *bios = &dev_priv->vbios; 6153 int i, ret = 0; 6154 6155 NVLockVgaCrtcs(dev, false); 6156 if (nv_two_heads(dev)) 6157 NVSetOwner(dev, bios->state.crtchead); 6158 6159 if (bios->major_version < 5) /* BMP only */ 6160 load_nv17_hw_sequencer_ucode(dev, bios); 6161 6162 if (bios->execute) { 6163 bios->fp.last_script_invoc = 0; 6164 bios->fp.lvds_init_run = false; 6165 } 6166 6167 parse_init_tables(bios); 6168 6169 /* 6170 * Runs some additional script seen on G8x VBIOSen. The VBIOS' 6171 * parser will run this right after the init tables, the binary 6172 * driver appears to run it at some point later. 6173 */ 6174 if (bios->some_script_ptr) { 6175 struct init_exec iexec = {true, false}; 6176 6177 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n", 6178 bios->some_script_ptr); 6179 parse_init_table(bios, bios->some_script_ptr, &iexec); 6180 } 6181 6182 if (dev_priv->card_type >= NV_50) { 6183 for (i = 0; i < bios->dcb.entries; i++) { 6184 nouveau_bios_run_display_table(dev, 6185 &bios->dcb.entry[i], 6186 0, 0); 6187 } 6188 } 6189 6190 NVLockVgaCrtcs(dev, true); 6191 6192 return ret; 6193} 6194 6195static void 6196nouveau_bios_i2c_devices_takedown(struct drm_device *dev) 6197{ 6198 struct drm_nouveau_private *dev_priv = dev->dev_private; 6199 struct nvbios *bios = &dev_priv->vbios; 6200 struct dcb_i2c_entry *entry; 6201 int i; 6202 6203 entry = &bios->dcb.i2c[0]; 6204 for (i = 0; i < DCB_MAX_NUM_I2C_ENTRIES; i++, entry++) 6205 nouveau_i2c_fini(dev, entry); 6206} 6207 6208static bool 6209nouveau_bios_posted(struct drm_device *dev) 6210{ 6211 struct drm_nouveau_private *dev_priv = dev->dev_private; 6212 bool was_locked; 6213 unsigned htotal; 6214 6215 if (dev_priv->chipset >= NV_50) { 6216 if (NVReadVgaCrtc(dev, 0, 0x00) == 0 && 6217 NVReadVgaCrtc(dev, 0, 0x1a) == 0) 6218 return false; 6219 return true; 6220 } 6221 6222 was_locked = NVLockVgaCrtcs(dev, false); 6223 htotal = NVReadVgaCrtc(dev, 0, 0x06); 6224 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8; 6225 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4; 6226 htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10; 6227 htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11; 6228 NVLockVgaCrtcs(dev, was_locked); 6229 return (htotal != 0); 6230} 6231 6232int 6233nouveau_bios_init(struct drm_device *dev) 6234{ 6235 struct drm_nouveau_private *dev_priv = dev->dev_private; 6236 struct nvbios *bios = &dev_priv->vbios; 6237 uint32_t saved_nv_pextdev_boot_0; 6238 bool was_locked; 6239 int ret; 6240 6241 if (!NVInitVBIOS(dev)) 6242 return -ENODEV; 6243 6244 ret = nouveau_parse_vbios_struct(dev); 6245 if (ret) 6246 return ret; 6247 6248 ret = parse_dcb_table(dev, bios, nv_two_heads(dev)); 6249 if (ret) 6250 return ret; 6251 6252 fixup_legacy_i2c(bios); 6253 fixup_legacy_connector(bios); 6254 6255 if (!bios->major_version) /* we don't run version 0 bios */ 6256 return 0; 6257 6258 /* these will need remembering across a suspend */ 6259 saved_nv_pextdev_boot_0 = bios_rd32(bios, NV_PEXTDEV_BOOT_0); 6260 bios->state.saved_nv_pfb_cfg0 = bios_rd32(bios, NV_PFB_CFG0); 6261 6262 /* init script execution disabled */ 6263 bios->execute = false; 6264 6265 /* ... unless card isn't POSTed already */ 6266 if (!nouveau_bios_posted(dev)) { 6267 NV_INFO(dev, "Adaptor not initialised\n"); 6268 if (dev_priv->card_type < NV_40) { 6269 NV_ERROR(dev, "Unable to POST this chipset\n"); 6270 return -ENODEV; 6271 } 6272 6273 NV_INFO(dev, "Running VBIOS init tables\n"); 6274 bios->execute = true; 6275 } 6276 6277 bios_wr32(bios, NV_PEXTDEV_BOOT_0, saved_nv_pextdev_boot_0); 6278 6279 ret = nouveau_run_vbios_init(dev); 6280 if (ret) 6281 return ret; 6282 6283 /* feature_byte on BMP is poor, but init always sets CR4B */ 6284 was_locked = NVLockVgaCrtcs(dev, false); 6285 if (bios->major_version < 5) 6286 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40; 6287 6288 /* all BIT systems need p_f_m_t for digital_min_front_porch */ 6289 if (bios->is_mobile || bios->major_version >= 5) 6290 ret = parse_fp_mode_table(dev, bios); 6291 NVLockVgaCrtcs(dev, was_locked); 6292 6293 /* allow subsequent scripts to execute */ 6294 bios->execute = true; 6295 6296 return 0; 6297} 6298 6299void 6300nouveau_bios_takedown(struct drm_device *dev) 6301{ 6302 nouveau_bios_i2c_devices_takedown(dev); 6303} 6304