nv50_display.c revision 106ddad5aa8e8e03503cea05f9a64611f849952f
1/* 2 * Copyright (C) 2008 Maarten Maathuis. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sublicense, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial 15 * portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27#include "nv50_display.h" 28#include "nouveau_crtc.h" 29#include "nouveau_encoder.h" 30#include "nouveau_connector.h" 31#include "nouveau_fb.h" 32#include "nouveau_fbcon.h" 33#include "nouveau_ramht.h" 34#include "drm_crtc_helper.h" 35 36static inline int 37nv50_sor_nr(struct drm_device *dev) 38{ 39 struct drm_nouveau_private *dev_priv = dev->dev_private; 40 41 if (dev_priv->chipset < 0x90 || 42 dev_priv->chipset == 0x92 || 43 dev_priv->chipset == 0xa0) 44 return 2; 45 46 return 4; 47} 48 49static void 50nv50_evo_channel_del(struct nouveau_channel **pchan) 51{ 52 struct nouveau_channel *chan = *pchan; 53 54 if (!chan) 55 return; 56 *pchan = NULL; 57 58 nouveau_gpuobj_channel_takedown(chan); 59 nouveau_bo_unmap(chan->pushbuf_bo); 60 nouveau_bo_ref(NULL, &chan->pushbuf_bo); 61 62 if (chan->user) 63 iounmap(chan->user); 64 65 kfree(chan); 66} 67 68static int 69nv50_evo_dmaobj_new(struct nouveau_channel *evo, uint32_t class, uint32_t name, 70 uint32_t tile_flags, uint32_t magic_flags, 71 uint32_t offset, uint32_t limit) 72{ 73 struct drm_nouveau_private *dev_priv = evo->dev->dev_private; 74 struct drm_device *dev = evo->dev; 75 struct nouveau_gpuobj *obj = NULL; 76 int ret; 77 78 ret = nouveau_gpuobj_new(dev, evo, 6*4, 32, 0, &obj); 79 if (ret) 80 return ret; 81 obj->engine = NVOBJ_ENGINE_DISPLAY; 82 83 nv_wo32(obj, 0, (tile_flags << 22) | (magic_flags << 16) | class); 84 nv_wo32(obj, 4, limit); 85 nv_wo32(obj, 8, offset); 86 nv_wo32(obj, 12, 0x00000000); 87 nv_wo32(obj, 16, 0x00000000); 88 if (dev_priv->card_type < NV_C0) 89 nv_wo32(obj, 20, 0x00010000); 90 else 91 nv_wo32(obj, 20, 0x00020000); 92 dev_priv->engine.instmem.flush(dev); 93 94 ret = nouveau_ramht_insert(evo, name, obj); 95 nouveau_gpuobj_ref(NULL, &obj); 96 if (ret) { 97 return ret; 98 } 99 100 return 0; 101} 102 103static int 104nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pchan) 105{ 106 struct drm_nouveau_private *dev_priv = dev->dev_private; 107 struct nouveau_gpuobj *ramht = NULL; 108 struct nouveau_channel *chan; 109 int ret; 110 111 chan = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL); 112 if (!chan) 113 return -ENOMEM; 114 *pchan = chan; 115 116 chan->id = -1; 117 chan->dev = dev; 118 chan->user_get = 4; 119 chan->user_put = 0; 120 121 ret = nouveau_gpuobj_new(dev, NULL, 32768, 0x1000, 122 NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin); 123 if (ret) { 124 NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret); 125 nv50_evo_channel_del(pchan); 126 return ret; 127 } 128 129 ret = drm_mm_init(&chan->ramin_heap, 0, 32768); 130 if (ret) { 131 NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret); 132 nv50_evo_channel_del(pchan); 133 return ret; 134 } 135 136 ret = nouveau_gpuobj_new(dev, chan, 4096, 16, 0, &ramht); 137 if (ret) { 138 NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret); 139 nv50_evo_channel_del(pchan); 140 return ret; 141 } 142 143 ret = nouveau_ramht_new(dev, ramht, &chan->ramht); 144 nouveau_gpuobj_ref(NULL, &ramht); 145 if (ret) { 146 nv50_evo_channel_del(pchan); 147 return ret; 148 } 149 150 if (dev_priv->chipset != 0x50) { 151 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB16, 0x70, 0x19, 152 0, 0xffffffff); 153 if (ret) { 154 nv50_evo_channel_del(pchan); 155 return ret; 156 } 157 158 159 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB32, 0x7a, 0x19, 160 0, 0xffffffff); 161 if (ret) { 162 nv50_evo_channel_del(pchan); 163 return ret; 164 } 165 } 166 167 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoVRAM, 0, 0x19, 168 0, dev_priv->vram_size); 169 if (ret) { 170 nv50_evo_channel_del(pchan); 171 return ret; 172 } 173 174 ret = nouveau_bo_new(dev, NULL, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0, 175 false, true, &chan->pushbuf_bo); 176 if (ret == 0) 177 ret = nouveau_bo_pin(chan->pushbuf_bo, TTM_PL_FLAG_VRAM); 178 if (ret) { 179 NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret); 180 nv50_evo_channel_del(pchan); 181 return ret; 182 } 183 184 ret = nouveau_bo_map(chan->pushbuf_bo); 185 if (ret) { 186 NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret); 187 nv50_evo_channel_del(pchan); 188 return ret; 189 } 190 191 chan->user = ioremap(pci_resource_start(dev->pdev, 0) + 192 NV50_PDISPLAY_USER(0), PAGE_SIZE); 193 if (!chan->user) { 194 NV_ERROR(dev, "Error mapping EVO control regs.\n"); 195 nv50_evo_channel_del(pchan); 196 return -ENOMEM; 197 } 198 199 return 0; 200} 201 202int 203nv50_display_early_init(struct drm_device *dev) 204{ 205 return 0; 206} 207 208void 209nv50_display_late_takedown(struct drm_device *dev) 210{ 211} 212 213int 214nv50_display_init(struct drm_device *dev) 215{ 216 struct drm_nouveau_private *dev_priv = dev->dev_private; 217 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer; 218 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio; 219 struct nouveau_channel *evo = dev_priv->evo; 220 struct drm_connector *connector; 221 int ret, i; 222 u64 start; 223 u32 val; 224 225 NV_DEBUG_KMS(dev, "\n"); 226 227 nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004)); 228 229 /* 230 * I think the 0x006101XX range is some kind of main control area 231 * that enables things. 232 */ 233 /* CRTC? */ 234 for (i = 0; i < 2; i++) { 235 val = nv_rd32(dev, 0x00616100 + (i * 0x800)); 236 nv_wr32(dev, 0x00610190 + (i * 0x10), val); 237 val = nv_rd32(dev, 0x00616104 + (i * 0x800)); 238 nv_wr32(dev, 0x00610194 + (i * 0x10), val); 239 val = nv_rd32(dev, 0x00616108 + (i * 0x800)); 240 nv_wr32(dev, 0x00610198 + (i * 0x10), val); 241 val = nv_rd32(dev, 0x0061610c + (i * 0x800)); 242 nv_wr32(dev, 0x0061019c + (i * 0x10), val); 243 } 244 245 /* DAC */ 246 for (i = 0; i < 3; i++) { 247 val = nv_rd32(dev, 0x0061a000 + (i * 0x800)); 248 nv_wr32(dev, 0x006101d0 + (i * 0x04), val); 249 } 250 251 /* SOR */ 252 for (i = 0; i < nv50_sor_nr(dev); i++) { 253 val = nv_rd32(dev, 0x0061c000 + (i * 0x800)); 254 nv_wr32(dev, 0x006101e0 + (i * 0x04), val); 255 } 256 257 /* EXT */ 258 for (i = 0; i < 3; i++) { 259 val = nv_rd32(dev, 0x0061e000 + (i * 0x800)); 260 nv_wr32(dev, 0x006101f0 + (i * 0x04), val); 261 } 262 263 for (i = 0; i < 3; i++) { 264 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 | 265 NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING); 266 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001); 267 } 268 269 /* The precise purpose is unknown, i suspect it has something to do 270 * with text mode. 271 */ 272 if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) { 273 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100); 274 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1); 275 if (!nv_wait(dev, 0x006194e8, 2, 0)) { 276 NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n"); 277 NV_ERROR(dev, "0x6194e8 = 0x%08x\n", 278 nv_rd32(dev, 0x6194e8)); 279 return -EBUSY; 280 } 281 } 282 283 for (i = 0; i < 2; i++) { 284 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000); 285 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 286 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) { 287 NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n"); 288 NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n", 289 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i))); 290 return -EBUSY; 291 } 292 293 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 294 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON); 295 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 296 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 297 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) { 298 NV_ERROR(dev, "timeout: " 299 "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i); 300 NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i, 301 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i))); 302 return -EBUSY; 303 } 304 } 305 306 nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->vinst >> 8) | 9); 307 nv_wr32(dev, NV50_PDISPLAY_PIO_CTRL, 0x00000000); 308 nv_wr32(dev, 0x610028, 0x00000000); 309 nv_mask(dev, NV50_PDISPLAY_INTR_0, 0x00000000, 0x00000000); 310 nv_mask(dev, NV50_PDISPLAY_INTR_1, 0x00000000, 0x00000000); 311 nv_wr32(dev, NV50_PDISPLAY_INTR_EN, 312 NV50_PDISPLAY_INTR_EN_CLK_UNK10 | 313 NV50_PDISPLAY_INTR_EN_CLK_UNK20 | 314 NV50_PDISPLAY_INTR_EN_CLK_UNK40); 315 316 /* enable hotplug interrupts */ 317 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 318 struct nouveau_connector *conn = nouveau_connector(connector); 319 320 if (conn->dcb->gpio_tag == 0xff) 321 continue; 322 323 pgpio->irq_enable(dev, conn->dcb->gpio_tag, true); 324 } 325 326 /* taken from nv bug #12637, attempts to un-wedge the hw if it's 327 * stuck in some unspecified state 328 */ 329 start = ptimer->read(dev); 330 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x2b00); 331 while ((val = nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0))) & 0x1e0000) { 332 if ((val & 0x9f0000) == 0x20000) 333 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 334 val | 0x800000); 335 336 if ((val & 0x3f0000) == 0x30000) 337 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 338 val | 0x200000); 339 340 if (ptimer->read(dev) - start > 1000000000ULL) { 341 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) != 0\n"); 342 NV_ERROR(dev, "0x610200 = 0x%08x\n", val); 343 return -EBUSY; 344 } 345 } 346 347 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x1000b03); 348 if (!nv_wait(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 349 0x40000000, 0x40000000)) { 350 NV_ERROR(dev, "timeout: (0x610200 & 0x40000000) == 0x40000000\n"); 351 NV_ERROR(dev, "0x610200 = 0x%08x\n", 352 nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0))); 353 return -EBUSY; 354 } 355 356 /* initialise fifo */ 357 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_DMA_CB(0), 358 ((evo->pushbuf_bo->bo.mem.start << PAGE_SHIFT) >> 8) | 359 NV50_PDISPLAY_CHANNEL_DMA_CB_LOCATION_VRAM | 360 NV50_PDISPLAY_CHANNEL_DMA_CB_VALID); 361 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK2(0), 0x00010000); 362 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK3(0), 0x00000002); 363 if (!nv_wait(dev, 0x610200, 0x80000000, 0x00000000)) { 364 NV_ERROR(dev, "timeout: (0x610200 & 0x80000000) == 0\n"); 365 NV_ERROR(dev, "0x610200 = 0x%08x\n", nv_rd32(dev, 0x610200)); 366 return -EBUSY; 367 } 368 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 369 (nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)) & ~0x00000003) | 370 NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED); 371 nv_wr32(dev, NV50_PDISPLAY_USER_PUT(0), 0); 372 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x01000003 | 373 NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED); 374 375 /* enable error reporting on the channel */ 376 nv_mask(dev, 0x610028, 0x00000000, 0x00010001 << 0); 377 378 evo->dma.max = (4096/4) - 2; 379 evo->dma.put = 0; 380 evo->dma.cur = evo->dma.put; 381 evo->dma.free = evo->dma.max - evo->dma.cur; 382 383 ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS); 384 if (ret) 385 return ret; 386 387 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++) 388 OUT_RING(evo, 0); 389 390 ret = RING_SPACE(evo, 11); 391 if (ret) 392 return ret; 393 BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2); 394 OUT_RING(evo, NV50_EVO_UNK84_NOTIFY_DISABLED); 395 OUT_RING(evo, NV50_EVO_DMA_NOTIFY_HANDLE_NONE); 396 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, FB_DMA), 1); 397 OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE); 398 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK0800), 1); 399 OUT_RING(evo, 0); 400 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, DISPLAY_START), 1); 401 OUT_RING(evo, 0); 402 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK082C), 1); 403 OUT_RING(evo, 0); 404 FIRE_RING(evo); 405 if (!nv_wait(dev, 0x640004, 0xffffffff, evo->dma.put << 2)) 406 NV_ERROR(dev, "evo pushbuf stalled\n"); 407 408 409 return 0; 410} 411 412static int nv50_display_disable(struct drm_device *dev) 413{ 414 struct drm_nouveau_private *dev_priv = dev->dev_private; 415 struct drm_crtc *drm_crtc; 416 int ret, i; 417 418 NV_DEBUG_KMS(dev, "\n"); 419 420 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) { 421 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc); 422 423 nv50_crtc_blank(crtc, true); 424 } 425 426 ret = RING_SPACE(dev_priv->evo, 2); 427 if (ret == 0) { 428 BEGIN_RING(dev_priv->evo, 0, NV50_EVO_UPDATE, 1); 429 OUT_RING(dev_priv->evo, 0); 430 } 431 FIRE_RING(dev_priv->evo); 432 433 /* Almost like ack'ing a vblank interrupt, maybe in the spirit of 434 * cleaning up? 435 */ 436 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) { 437 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc); 438 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index); 439 440 if (!crtc->base.enabled) 441 continue; 442 443 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask); 444 if (!nv_wait(dev, NV50_PDISPLAY_INTR_1, mask, mask)) { 445 NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == " 446 "0x%08x\n", mask, mask); 447 NV_ERROR(dev, "0x610024 = 0x%08x\n", 448 nv_rd32(dev, NV50_PDISPLAY_INTR_1)); 449 } 450 } 451 452 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0); 453 if (!nv_wait(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x1e0000, 0)) { 454 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) == 0\n"); 455 NV_ERROR(dev, "0x610200 = 0x%08x\n", 456 nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0))); 457 } 458 459 for (i = 0; i < 3; i++) { 460 if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i), 461 NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) { 462 NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i); 463 NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i, 464 nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i))); 465 } 466 } 467 468 /* disable interrupts. */ 469 nv_wr32(dev, NV50_PDISPLAY_INTR_EN, 0x00000000); 470 471 /* disable hotplug interrupts */ 472 nv_wr32(dev, 0xe054, 0xffffffff); 473 nv_wr32(dev, 0xe050, 0x00000000); 474 if (dev_priv->chipset >= 0x90) { 475 nv_wr32(dev, 0xe074, 0xffffffff); 476 nv_wr32(dev, 0xe070, 0x00000000); 477 } 478 return 0; 479} 480 481int nv50_display_create(struct drm_device *dev) 482{ 483 struct drm_nouveau_private *dev_priv = dev->dev_private; 484 struct dcb_table *dcb = &dev_priv->vbios.dcb; 485 struct drm_connector *connector, *ct; 486 int ret, i; 487 488 NV_DEBUG_KMS(dev, "\n"); 489 490 /* init basic kernel modesetting */ 491 drm_mode_config_init(dev); 492 493 /* Initialise some optional connector properties. */ 494 drm_mode_create_scaling_mode_property(dev); 495 drm_mode_create_dithering_property(dev); 496 497 dev->mode_config.min_width = 0; 498 dev->mode_config.min_height = 0; 499 500 dev->mode_config.funcs = (void *)&nouveau_mode_config_funcs; 501 502 dev->mode_config.max_width = 8192; 503 dev->mode_config.max_height = 8192; 504 505 dev->mode_config.fb_base = dev_priv->fb_phys; 506 507 /* Create EVO channel */ 508 ret = nv50_evo_channel_new(dev, &dev_priv->evo); 509 if (ret) { 510 NV_ERROR(dev, "Error creating EVO channel: %d\n", ret); 511 return ret; 512 } 513 514 /* Create CRTC objects */ 515 for (i = 0; i < 2; i++) 516 nv50_crtc_create(dev, i); 517 518 /* We setup the encoders from the BIOS table */ 519 for (i = 0 ; i < dcb->entries; i++) { 520 struct dcb_entry *entry = &dcb->entry[i]; 521 522 if (entry->location != DCB_LOC_ON_CHIP) { 523 NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n", 524 entry->type, ffs(entry->or) - 1); 525 continue; 526 } 527 528 connector = nouveau_connector_create(dev, entry->connector); 529 if (IS_ERR(connector)) 530 continue; 531 532 switch (entry->type) { 533 case OUTPUT_TMDS: 534 case OUTPUT_LVDS: 535 case OUTPUT_DP: 536 nv50_sor_create(connector, entry); 537 break; 538 case OUTPUT_ANALOG: 539 nv50_dac_create(connector, entry); 540 break; 541 default: 542 NV_WARN(dev, "DCB encoder %d unknown\n", entry->type); 543 continue; 544 } 545 } 546 547 list_for_each_entry_safe(connector, ct, 548 &dev->mode_config.connector_list, head) { 549 if (!connector->encoder_ids[0]) { 550 NV_WARN(dev, "%s has no encoders, removing\n", 551 drm_get_connector_name(connector)); 552 connector->funcs->destroy(connector); 553 } 554 } 555 556 ret = nv50_display_init(dev); 557 if (ret) { 558 nv50_display_destroy(dev); 559 return ret; 560 } 561 562 return 0; 563} 564 565void 566nv50_display_destroy(struct drm_device *dev) 567{ 568 struct drm_nouveau_private *dev_priv = dev->dev_private; 569 570 NV_DEBUG_KMS(dev, "\n"); 571 572 drm_mode_config_cleanup(dev); 573 574 nv50_display_disable(dev); 575 nv50_evo_channel_del(&dev_priv->evo); 576} 577 578static u16 579nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb, 580 u32 mc, int pxclk) 581{ 582 struct drm_nouveau_private *dev_priv = dev->dev_private; 583 struct nouveau_connector *nv_connector = NULL; 584 struct drm_encoder *encoder; 585 struct nvbios *bios = &dev_priv->vbios; 586 u32 script = 0, or; 587 588 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 589 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 590 591 if (nv_encoder->dcb != dcb) 592 continue; 593 594 nv_connector = nouveau_encoder_connector_get(nv_encoder); 595 break; 596 } 597 598 or = ffs(dcb->or) - 1; 599 switch (dcb->type) { 600 case OUTPUT_LVDS: 601 script = (mc >> 8) & 0xf; 602 if (bios->fp_no_ddc) { 603 if (bios->fp.dual_link) 604 script |= 0x0100; 605 if (bios->fp.if_is_24bit) 606 script |= 0x0200; 607 } else { 608 if (pxclk >= bios->fp.duallink_transition_clk) { 609 script |= 0x0100; 610 if (bios->fp.strapless_is_24bit & 2) 611 script |= 0x0200; 612 } else 613 if (bios->fp.strapless_is_24bit & 1) 614 script |= 0x0200; 615 616 if (nv_connector && nv_connector->edid && 617 (nv_connector->edid->revision >= 4) && 618 (nv_connector->edid->input & 0x70) >= 0x20) 619 script |= 0x0200; 620 } 621 622 if (nouveau_uscript_lvds >= 0) { 623 NV_INFO(dev, "override script 0x%04x with 0x%04x " 624 "for output LVDS-%d\n", script, 625 nouveau_uscript_lvds, or); 626 script = nouveau_uscript_lvds; 627 } 628 break; 629 case OUTPUT_TMDS: 630 script = (mc >> 8) & 0xf; 631 if (pxclk >= 165000) 632 script |= 0x0100; 633 634 if (nouveau_uscript_tmds >= 0) { 635 NV_INFO(dev, "override script 0x%04x with 0x%04x " 636 "for output TMDS-%d\n", script, 637 nouveau_uscript_tmds, or); 638 script = nouveau_uscript_tmds; 639 } 640 break; 641 case OUTPUT_DP: 642 script = (mc >> 8) & 0xf; 643 break; 644 case OUTPUT_ANALOG: 645 script = 0xff; 646 break; 647 default: 648 NV_ERROR(dev, "modeset on unsupported output type!\n"); 649 break; 650 } 651 652 return script; 653} 654 655static void 656nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc) 657{ 658 struct drm_nouveau_private *dev_priv = dev->dev_private; 659 struct nouveau_channel *chan; 660 struct list_head *entry, *tmp; 661 662 list_for_each_safe(entry, tmp, &dev_priv->vbl_waiting) { 663 chan = list_entry(entry, struct nouveau_channel, nvsw.vbl_wait); 664 665 nouveau_bo_wr32(chan->notifier_bo, chan->nvsw.vblsem_offset, 666 chan->nvsw.vblsem_rval); 667 list_del(&chan->nvsw.vbl_wait); 668 } 669} 670 671static void 672nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr) 673{ 674 intr &= NV50_PDISPLAY_INTR_1_VBLANK_CRTC; 675 676 if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0) 677 nv50_display_vblank_crtc_handler(dev, 0); 678 679 if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1) 680 nv50_display_vblank_crtc_handler(dev, 1); 681 682 nv_wr32(dev, NV50_PDISPLAY_INTR_EN, nv_rd32(dev, 683 NV50_PDISPLAY_INTR_EN) & ~intr); 684 nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr); 685} 686 687static void 688nv50_display_unk10_handler(struct drm_device *dev) 689{ 690 struct drm_nouveau_private *dev_priv = dev->dev_private; 691 u32 unk30 = nv_rd32(dev, 0x610030), mc; 692 int i, crtc, or, type = OUTPUT_ANY; 693 694 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30); 695 dev_priv->evo_irq.dcb = NULL; 696 697 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8); 698 699 /* Determine which CRTC we're dealing with, only 1 ever will be 700 * signalled at the same time with the current nouveau code. 701 */ 702 crtc = ffs((unk30 & 0x00000060) >> 5) - 1; 703 if (crtc < 0) 704 goto ack; 705 706 /* Nothing needs to be done for the encoder */ 707 crtc = ffs((unk30 & 0x00000180) >> 7) - 1; 708 if (crtc < 0) 709 goto ack; 710 711 /* Find which encoder was connected to the CRTC */ 712 for (i = 0; type == OUTPUT_ANY && i < 3; i++) { 713 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i)); 714 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc); 715 if (!(mc & (1 << crtc))) 716 continue; 717 718 switch ((mc & 0x00000f00) >> 8) { 719 case 0: type = OUTPUT_ANALOG; break; 720 case 1: type = OUTPUT_TV; break; 721 default: 722 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc); 723 goto ack; 724 } 725 726 or = i; 727 } 728 729 for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) { 730 if (dev_priv->chipset < 0x90 || 731 dev_priv->chipset == 0x92 || 732 dev_priv->chipset == 0xa0) 733 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i)); 734 else 735 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i)); 736 737 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc); 738 if (!(mc & (1 << crtc))) 739 continue; 740 741 switch ((mc & 0x00000f00) >> 8) { 742 case 0: type = OUTPUT_LVDS; break; 743 case 1: type = OUTPUT_TMDS; break; 744 case 2: type = OUTPUT_TMDS; break; 745 case 5: type = OUTPUT_TMDS; break; 746 case 8: type = OUTPUT_DP; break; 747 case 9: type = OUTPUT_DP; break; 748 default: 749 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc); 750 goto ack; 751 } 752 753 or = i; 754 } 755 756 /* There was no encoder to disable */ 757 if (type == OUTPUT_ANY) 758 goto ack; 759 760 /* Disable the encoder */ 761 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) { 762 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i]; 763 764 if (dcb->type == type && (dcb->or & (1 << or))) { 765 nouveau_bios_run_display_table(dev, dcb, 0, -1); 766 dev_priv->evo_irq.dcb = dcb; 767 goto ack; 768 } 769 } 770 771 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc); 772ack: 773 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10); 774 nv_wr32(dev, 0x610030, 0x80000000); 775} 776 777static void 778nv50_display_unk20_dp_hack(struct drm_device *dev, struct dcb_entry *dcb) 779{ 780 int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1); 781 struct drm_encoder *encoder; 782 uint32_t tmp, unk0 = 0, unk1 = 0; 783 784 if (dcb->type != OUTPUT_DP) 785 return; 786 787 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 788 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 789 790 if (nv_encoder->dcb == dcb) { 791 unk0 = nv_encoder->dp.unk0; 792 unk1 = nv_encoder->dp.unk1; 793 break; 794 } 795 } 796 797 if (unk0 || unk1) { 798 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link)); 799 tmp &= 0xfffffe03; 800 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp | unk0); 801 802 tmp = nv_rd32(dev, NV50_SOR_DP_UNK128(or, link)); 803 tmp &= 0xfef080c0; 804 nv_wr32(dev, NV50_SOR_DP_UNK128(or, link), tmp | unk1); 805 } 806} 807 808static void 809nv50_display_unk20_handler(struct drm_device *dev) 810{ 811 struct drm_nouveau_private *dev_priv = dev->dev_private; 812 u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc; 813 struct dcb_entry *dcb; 814 int i, crtc, or, type = OUTPUT_ANY; 815 816 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30); 817 dcb = dev_priv->evo_irq.dcb; 818 if (dcb) { 819 nouveau_bios_run_display_table(dev, dcb, 0, -2); 820 dev_priv->evo_irq.dcb = NULL; 821 } 822 823 /* CRTC clock change requested? */ 824 crtc = ffs((unk30 & 0x00000600) >> 9) - 1; 825 if (crtc >= 0) { 826 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)); 827 pclk &= 0x003fffff; 828 829 nv50_crtc_set_clock(dev, crtc, pclk); 830 831 tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc)); 832 tmp &= ~0x000000f; 833 nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp); 834 } 835 836 /* Nothing needs to be done for the encoder */ 837 crtc = ffs((unk30 & 0x00000180) >> 7) - 1; 838 if (crtc < 0) 839 goto ack; 840 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff; 841 842 /* Find which encoder is connected to the CRTC */ 843 for (i = 0; type == OUTPUT_ANY && i < 3; i++) { 844 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i)); 845 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc); 846 if (!(mc & (1 << crtc))) 847 continue; 848 849 switch ((mc & 0x00000f00) >> 8) { 850 case 0: type = OUTPUT_ANALOG; break; 851 case 1: type = OUTPUT_TV; break; 852 default: 853 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc); 854 goto ack; 855 } 856 857 or = i; 858 } 859 860 for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) { 861 if (dev_priv->chipset < 0x90 || 862 dev_priv->chipset == 0x92 || 863 dev_priv->chipset == 0xa0) 864 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(i)); 865 else 866 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(i)); 867 868 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc); 869 if (!(mc & (1 << crtc))) 870 continue; 871 872 switch ((mc & 0x00000f00) >> 8) { 873 case 0: type = OUTPUT_LVDS; break; 874 case 1: type = OUTPUT_TMDS; break; 875 case 2: type = OUTPUT_TMDS; break; 876 case 5: type = OUTPUT_TMDS; break; 877 case 8: type = OUTPUT_DP; break; 878 case 9: type = OUTPUT_DP; break; 879 default: 880 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc); 881 goto ack; 882 } 883 884 or = i; 885 } 886 887 if (type == OUTPUT_ANY) 888 goto ack; 889 890 /* Enable the encoder */ 891 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) { 892 dcb = &dev_priv->vbios.dcb.entry[i]; 893 if (dcb->type == type && (dcb->or & (1 << or))) 894 break; 895 } 896 897 if (i == dev_priv->vbios.dcb.entries) { 898 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc); 899 goto ack; 900 } 901 902 script = nv50_display_script_select(dev, dcb, mc, pclk); 903 nouveau_bios_run_display_table(dev, dcb, script, pclk); 904 905 nv50_display_unk20_dp_hack(dev, dcb); 906 907 if (dcb->type != OUTPUT_ANALOG) { 908 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or)); 909 tmp &= ~0x00000f0f; 910 if (script & 0x0100) 911 tmp |= 0x00000101; 912 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp); 913 } else { 914 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0); 915 } 916 917 dev_priv->evo_irq.dcb = dcb; 918 dev_priv->evo_irq.pclk = pclk; 919 dev_priv->evo_irq.script = script; 920 921ack: 922 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20); 923 nv_wr32(dev, 0x610030, 0x80000000); 924} 925 926/* If programming a TMDS output on a SOR that can also be configured for 927 * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off. 928 * 929 * It looks like the VBIOS TMDS scripts make an attempt at this, however, 930 * the VBIOS scripts on at least one board I have only switch it off on 931 * link 0, causing a blank display if the output has previously been 932 * programmed for DisplayPort. 933 */ 934static void 935nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_entry *dcb) 936{ 937 int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1); 938 struct drm_encoder *encoder; 939 u32 tmp; 940 941 if (dcb->type != OUTPUT_TMDS) 942 return; 943 944 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 945 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 946 947 if (nv_encoder->dcb->type == OUTPUT_DP && 948 nv_encoder->dcb->or & (1 << or)) { 949 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link)); 950 tmp &= ~NV50_SOR_DP_CTRL_ENABLED; 951 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp); 952 break; 953 } 954 } 955} 956 957static void 958nv50_display_unk40_handler(struct drm_device *dev) 959{ 960 struct drm_nouveau_private *dev_priv = dev->dev_private; 961 struct dcb_entry *dcb = dev_priv->evo_irq.dcb; 962 u16 script = dev_priv->evo_irq.script; 963 u32 unk30 = nv_rd32(dev, 0x610030), pclk = dev_priv->evo_irq.pclk; 964 965 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30); 966 dev_priv->evo_irq.dcb = NULL; 967 if (!dcb) 968 goto ack; 969 970 nouveau_bios_run_display_table(dev, dcb, script, -pclk); 971 nv50_display_unk40_dp_set_tmds(dev, dcb); 972 973ack: 974 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40); 975 nv_wr32(dev, 0x610030, 0x80000000); 976 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8); 977} 978 979void 980nv50_display_irq_handler_bh(struct work_struct *work) 981{ 982 struct drm_nouveau_private *dev_priv = 983 container_of(work, struct drm_nouveau_private, irq_work); 984 struct drm_device *dev = dev_priv->dev; 985 986 for (;;) { 987 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0); 988 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1); 989 990 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1); 991 992 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10) 993 nv50_display_unk10_handler(dev); 994 else 995 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20) 996 nv50_display_unk20_handler(dev); 997 else 998 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40) 999 nv50_display_unk40_handler(dev); 1000 else 1001 break; 1002 } 1003 1004 nv_wr32(dev, NV03_PMC_INTR_EN_0, 1); 1005} 1006 1007static void 1008nv50_display_error_handler(struct drm_device *dev) 1009{ 1010 uint32_t addr, data; 1011 1012 nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000); 1013 addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR); 1014 data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA); 1015 1016 NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x (0x%04x 0x%02x)\n", 1017 0, addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf); 1018 1019 nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR, 0x90000000); 1020} 1021 1022void 1023nv50_display_irq_hotplug_bh(struct work_struct *work) 1024{ 1025 struct drm_nouveau_private *dev_priv = 1026 container_of(work, struct drm_nouveau_private, hpd_work); 1027 struct drm_device *dev = dev_priv->dev; 1028 struct drm_connector *connector; 1029 const uint32_t gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 }; 1030 uint32_t unplug_mask, plug_mask, change_mask; 1031 uint32_t hpd0, hpd1; 1032 1033 spin_lock_irq(&dev_priv->hpd_state.lock); 1034 hpd0 = dev_priv->hpd_state.hpd0_bits; 1035 dev_priv->hpd_state.hpd0_bits = 0; 1036 hpd1 = dev_priv->hpd_state.hpd1_bits; 1037 dev_priv->hpd_state.hpd1_bits = 0; 1038 spin_unlock_irq(&dev_priv->hpd_state.lock); 1039 1040 hpd0 &= nv_rd32(dev, 0xe050); 1041 if (dev_priv->chipset >= 0x90) 1042 hpd1 &= nv_rd32(dev, 0xe070); 1043 1044 plug_mask = (hpd0 & 0x0000ffff) | (hpd1 << 16); 1045 unplug_mask = (hpd0 >> 16) | (hpd1 & 0xffff0000); 1046 change_mask = plug_mask | unplug_mask; 1047 1048 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1049 struct drm_encoder_helper_funcs *helper; 1050 struct nouveau_connector *nv_connector = 1051 nouveau_connector(connector); 1052 struct nouveau_encoder *nv_encoder; 1053 struct dcb_gpio_entry *gpio; 1054 uint32_t reg; 1055 bool plugged; 1056 1057 if (!nv_connector->dcb) 1058 continue; 1059 1060 gpio = nouveau_bios_gpio_entry(dev, nv_connector->dcb->gpio_tag); 1061 if (!gpio || !(change_mask & (1 << gpio->line))) 1062 continue; 1063 1064 reg = nv_rd32(dev, gpio_reg[gpio->line >> 3]); 1065 plugged = !!(reg & (4 << ((gpio->line & 7) << 2))); 1066 NV_INFO(dev, "%splugged %s\n", plugged ? "" : "un", 1067 drm_get_connector_name(connector)) ; 1068 1069 if (!connector->encoder || !connector->encoder->crtc || 1070 !connector->encoder->crtc->enabled) 1071 continue; 1072 nv_encoder = nouveau_encoder(connector->encoder); 1073 helper = connector->encoder->helper_private; 1074 1075 if (nv_encoder->dcb->type != OUTPUT_DP) 1076 continue; 1077 1078 if (plugged) 1079 helper->dpms(connector->encoder, DRM_MODE_DPMS_ON); 1080 else 1081 helper->dpms(connector->encoder, DRM_MODE_DPMS_OFF); 1082 } 1083 1084 drm_helper_hpd_irq_event(dev); 1085} 1086 1087void 1088nv50_display_irq_handler(struct drm_device *dev) 1089{ 1090 struct drm_nouveau_private *dev_priv = dev->dev_private; 1091 uint32_t delayed = 0; 1092 1093 if (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_HOTPLUG) { 1094 uint32_t hpd0_bits, hpd1_bits = 0; 1095 1096 hpd0_bits = nv_rd32(dev, 0xe054); 1097 nv_wr32(dev, 0xe054, hpd0_bits); 1098 1099 if (dev_priv->chipset >= 0x90) { 1100 hpd1_bits = nv_rd32(dev, 0xe074); 1101 nv_wr32(dev, 0xe074, hpd1_bits); 1102 } 1103 1104 spin_lock(&dev_priv->hpd_state.lock); 1105 dev_priv->hpd_state.hpd0_bits |= hpd0_bits; 1106 dev_priv->hpd_state.hpd1_bits |= hpd1_bits; 1107 spin_unlock(&dev_priv->hpd_state.lock); 1108 1109 queue_work(dev_priv->wq, &dev_priv->hpd_work); 1110 } 1111 1112 while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) { 1113 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0); 1114 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1); 1115 uint32_t clock; 1116 1117 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1); 1118 1119 if (!intr0 && !(intr1 & ~delayed)) 1120 break; 1121 1122 if (intr0 & 0x00010000) { 1123 nv50_display_error_handler(dev); 1124 intr0 &= ~0x00010000; 1125 } 1126 1127 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) { 1128 nv50_display_vblank_handler(dev, intr1); 1129 intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC; 1130 } 1131 1132 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 | 1133 NV50_PDISPLAY_INTR_1_CLK_UNK20 | 1134 NV50_PDISPLAY_INTR_1_CLK_UNK40)); 1135 if (clock) { 1136 nv_wr32(dev, NV03_PMC_INTR_EN_0, 0); 1137 if (!work_pending(&dev_priv->irq_work)) 1138 queue_work(dev_priv->wq, &dev_priv->irq_work); 1139 delayed |= clock; 1140 intr1 &= ~clock; 1141 } 1142 1143 if (intr0) { 1144 NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0); 1145 nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0); 1146 } 1147 1148 if (intr1) { 1149 NV_ERROR(dev, 1150 "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1); 1151 nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1); 1152 } 1153 } 1154} 1155 1156