nv50_display.c revision 9da49599a70eceac405287f34485ed57fe035393
1/* 2 * Copyright (C) 2008 Maarten Maathuis. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sublicense, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial 15 * portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27#include "nouveau_drm.h" 28#include "nouveau_dma.h" 29 30#include "nv50_display.h" 31#include "nouveau_crtc.h" 32#include "nouveau_encoder.h" 33#include "nouveau_connector.h" 34#include "nouveau_fbcon.h" 35#include <drm/drm_crtc_helper.h> 36#include "nouveau_fence.h" 37 38#include <core/gpuobj.h> 39#include <subdev/timer.h> 40 41static void nv50_display_bh(unsigned long); 42 43static inline int 44nv50_sor_nr(struct drm_device *dev) 45{ 46 struct nouveau_device *device = nouveau_dev(dev); 47 48 if (device->chipset < 0x90 || 49 device->chipset == 0x92 || 50 device->chipset == 0xa0) 51 return 2; 52 53 return 4; 54} 55 56u32 57nv50_display_active_crtcs(struct drm_device *dev) 58{ 59 struct nouveau_device *device = nouveau_dev(dev); 60 u32 mask = 0; 61 int i; 62 63 if (device->chipset < 0x90 || 64 device->chipset == 0x92 || 65 device->chipset == 0xa0) { 66 for (i = 0; i < 2; i++) 67 mask |= nv_rd32(device, NV50_PDISPLAY_SOR_MODE_CTRL_C(i)); 68 } else { 69 for (i = 0; i < 4; i++) 70 mask |= nv_rd32(device, NV90_PDISPLAY_SOR_MODE_CTRL_C(i)); 71 } 72 73 for (i = 0; i < 3; i++) 74 mask |= nv_rd32(device, NV50_PDISPLAY_DAC_MODE_CTRL_C(i)); 75 76 return mask & 3; 77} 78 79int 80nv50_display_early_init(struct drm_device *dev) 81{ 82 return 0; 83} 84 85void 86nv50_display_late_takedown(struct drm_device *dev) 87{ 88} 89 90int 91nv50_display_sync(struct drm_device *dev) 92{ 93 struct nv50_display *disp = nv50_display(dev); 94 struct nouveau_channel *evo = disp->master; 95 int ret; 96 97 ret = RING_SPACE(evo, 6); 98 if (ret == 0) { 99 BEGIN_NV04(evo, 0, 0x0084, 1); 100 OUT_RING (evo, 0x80000000); 101 BEGIN_NV04(evo, 0, 0x0080, 1); 102 OUT_RING (evo, 0); 103 BEGIN_NV04(evo, 0, 0x0084, 1); 104 OUT_RING (evo, 0x00000000); 105 106 nv_wo32(disp->ramin, 0x2000, 0x00000000); 107 FIRE_RING (evo); 108 109 if (nv_wait_ne(disp->ramin, 0x2000, 0xffffffff, 0x00000000)) 110 return 0; 111 } 112 113 return 0; 114} 115 116int 117nv50_display_init(struct drm_device *dev) 118{ 119 struct nouveau_drm *drm = nouveau_drm(dev); 120 struct nouveau_device *device = nouveau_dev(dev); 121 struct nouveau_channel *evo; 122 int ret, i; 123 u32 val; 124 125 nv_wr32(device, 0x00610184, nv_rd32(device, 0x00614004)); 126 127 /* 128 * I think the 0x006101XX range is some kind of main control area 129 * that enables things. 130 */ 131 /* CRTC? */ 132 for (i = 0; i < 2; i++) { 133 val = nv_rd32(device, 0x00616100 + (i * 0x800)); 134 nv_wr32(device, 0x00610190 + (i * 0x10), val); 135 val = nv_rd32(device, 0x00616104 + (i * 0x800)); 136 nv_wr32(device, 0x00610194 + (i * 0x10), val); 137 val = nv_rd32(device, 0x00616108 + (i * 0x800)); 138 nv_wr32(device, 0x00610198 + (i * 0x10), val); 139 val = nv_rd32(device, 0x0061610c + (i * 0x800)); 140 nv_wr32(device, 0x0061019c + (i * 0x10), val); 141 } 142 143 /* DAC */ 144 for (i = 0; i < 3; i++) { 145 val = nv_rd32(device, 0x0061a000 + (i * 0x800)); 146 nv_wr32(device, 0x006101d0 + (i * 0x04), val); 147 } 148 149 /* SOR */ 150 for (i = 0; i < nv50_sor_nr(dev); i++) { 151 val = nv_rd32(device, 0x0061c000 + (i * 0x800)); 152 nv_wr32(device, 0x006101e0 + (i * 0x04), val); 153 } 154 155 /* EXT */ 156 for (i = 0; i < 3; i++) { 157 val = nv_rd32(device, 0x0061e000 + (i * 0x800)); 158 nv_wr32(device, 0x006101f0 + (i * 0x04), val); 159 } 160 161 for (i = 0; i < 3; i++) { 162 nv_wr32(device, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 | 163 NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING); 164 nv_wr32(device, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001); 165 } 166 167 /* The precise purpose is unknown, i suspect it has something to do 168 * with text mode. 169 */ 170 if (nv_rd32(device, NV50_PDISPLAY_INTR_1) & 0x100) { 171 nv_wr32(device, NV50_PDISPLAY_INTR_1, 0x100); 172 nv_wr32(device, 0x006194e8, nv_rd32(device, 0x006194e8) & ~1); 173 if (!nv_wait(device, 0x006194e8, 2, 0)) { 174 NV_ERROR(drm, "timeout: (0x6194e8 & 2) != 0\n"); 175 NV_ERROR(drm, "0x6194e8 = 0x%08x\n", 176 nv_rd32(device, 0x6194e8)); 177 return -EBUSY; 178 } 179 } 180 181 for (i = 0; i < 2; i++) { 182 nv_wr32(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000); 183 if (!nv_wait(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 184 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) { 185 NV_ERROR(drm, "timeout: CURSOR_CTRL2_STATUS == 0\n"); 186 NV_ERROR(drm, "CURSOR_CTRL2 = 0x%08x\n", 187 nv_rd32(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i))); 188 return -EBUSY; 189 } 190 191 nv_wr32(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 192 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON); 193 if (!nv_wait(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 194 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 195 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) { 196 NV_ERROR(drm, "timeout: " 197 "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i); 198 NV_ERROR(drm, "CURSOR_CTRL2(%d) = 0x%08x\n", i, 199 nv_rd32(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i))); 200 return -EBUSY; 201 } 202 } 203 204 nv_wr32(device, NV50_PDISPLAY_PIO_CTRL, 0x00000000); 205 nv_mask(device, NV50_PDISPLAY_INTR_0, 0x00000000, 0x00000000); 206 nv_wr32(device, NV50_PDISPLAY_INTR_EN_0, 0x00000000); 207 nv_mask(device, NV50_PDISPLAY_INTR_1, 0x00000000, 0x00000000); 208 nv_wr32(device, NV50_PDISPLAY_INTR_EN_1, 209 NV50_PDISPLAY_INTR_EN_1_CLK_UNK10 | 210 NV50_PDISPLAY_INTR_EN_1_CLK_UNK20 | 211 NV50_PDISPLAY_INTR_EN_1_CLK_UNK40); 212 213 ret = nv50_evo_init(dev); 214 if (ret) 215 return ret; 216 evo = nv50_display(dev)->master; 217 218 nv_wr32(device, NV50_PDISPLAY_OBJECTS, (nv50_display(dev)->ramin->addr >> 8) | 9); 219 220 ret = RING_SPACE(evo, 3); 221 if (ret) 222 return ret; 223 BEGIN_NV04(evo, 0, NV50_EVO_UNK84, 2); 224 OUT_RING (evo, NV50_EVO_UNK84_NOTIFY_DISABLED); 225 OUT_RING (evo, NvEvoSync); 226 227 return nv50_display_sync(dev); 228} 229 230void 231nv50_display_fini(struct drm_device *dev) 232{ 233 struct nouveau_drm *drm = nouveau_drm(dev); 234 struct nouveau_device *device = nouveau_dev(dev); 235 struct nv50_display *disp = nv50_display(dev); 236 struct nouveau_channel *evo = disp->master; 237 struct drm_crtc *drm_crtc; 238 int ret, i; 239 240 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) { 241 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc); 242 243 nv50_crtc_blank(crtc, true); 244 } 245 246 ret = RING_SPACE(evo, 2); 247 if (ret == 0) { 248 BEGIN_NV04(evo, 0, NV50_EVO_UPDATE, 1); 249 OUT_RING(evo, 0); 250 } 251 FIRE_RING(evo); 252 253 /* Almost like ack'ing a vblank interrupt, maybe in the spirit of 254 * cleaning up? 255 */ 256 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) { 257 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc); 258 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index); 259 260 if (!crtc->base.enabled) 261 continue; 262 263 nv_wr32(device, NV50_PDISPLAY_INTR_1, mask); 264 if (!nv_wait(device, NV50_PDISPLAY_INTR_1, mask, mask)) { 265 NV_ERROR(drm, "timeout: (0x610024 & 0x%08x) == " 266 "0x%08x\n", mask, mask); 267 NV_ERROR(drm, "0x610024 = 0x%08x\n", 268 nv_rd32(device, NV50_PDISPLAY_INTR_1)); 269 } 270 } 271 272 for (i = 0; i < 2; i++) { 273 nv_wr32(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0); 274 if (!nv_wait(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 275 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) { 276 NV_ERROR(drm, "timeout: CURSOR_CTRL2_STATUS == 0\n"); 277 NV_ERROR(drm, "CURSOR_CTRL2 = 0x%08x\n", 278 nv_rd32(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i))); 279 } 280 } 281 282 nv50_evo_fini(dev); 283 284 for (i = 0; i < 3; i++) { 285 if (!nv_wait(device, NV50_PDISPLAY_SOR_DPMS_STATE(i), 286 NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) { 287 NV_ERROR(drm, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i); 288 NV_ERROR(drm, "SOR_DPMS_STATE(%d) = 0x%08x\n", i, 289 nv_rd32(device, NV50_PDISPLAY_SOR_DPMS_STATE(i))); 290 } 291 } 292 293 /* disable interrupts. */ 294 nv_wr32(device, NV50_PDISPLAY_INTR_EN_1, 0x00000000); 295} 296 297int 298nv50_display_create(struct drm_device *dev) 299{ 300 struct nouveau_drm *drm = nouveau_drm(dev); 301 struct dcb_table *dcb = &drm->vbios.dcb; 302 struct drm_connector *connector, *ct; 303 struct nv50_display *priv; 304 int ret, i; 305 306 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 307 if (!priv) 308 return -ENOMEM; 309 310 nouveau_display(dev)->priv = priv; 311 nouveau_display(dev)->dtor = nv50_display_destroy; 312 nouveau_display(dev)->init = nv50_display_init; 313 nouveau_display(dev)->fini = nv50_display_fini; 314 315 /* Create CRTC objects */ 316 for (i = 0; i < 2; i++) { 317 ret = nv50_crtc_create(dev, i); 318 if (ret) 319 return ret; 320 } 321 322 /* We setup the encoders from the BIOS table */ 323 for (i = 0 ; i < dcb->entries; i++) { 324 struct dcb_output *entry = &dcb->entry[i]; 325 326 if (entry->location != DCB_LOC_ON_CHIP) { 327 NV_WARN(drm, "Off-chip encoder %d/%d unsupported\n", 328 entry->type, ffs(entry->or) - 1); 329 continue; 330 } 331 332 connector = nouveau_connector_create(dev, entry->connector); 333 if (IS_ERR(connector)) 334 continue; 335 336 switch (entry->type) { 337 case DCB_OUTPUT_TMDS: 338 case DCB_OUTPUT_LVDS: 339 case DCB_OUTPUT_DP: 340 nv50_sor_create(connector, entry); 341 break; 342 case DCB_OUTPUT_ANALOG: 343 nv50_dac_create(connector, entry); 344 break; 345 default: 346 NV_WARN(drm, "DCB encoder %d unknown\n", entry->type); 347 continue; 348 } 349 } 350 351 list_for_each_entry_safe(connector, ct, 352 &dev->mode_config.connector_list, head) { 353 if (!connector->encoder_ids[0]) { 354 NV_WARN(drm, "%s has no encoders, removing\n", 355 drm_get_connector_name(connector)); 356 connector->funcs->destroy(connector); 357 } 358 } 359 360 tasklet_init(&priv->tasklet, nv50_display_bh, (unsigned long)dev); 361 362 ret = nv50_evo_create(dev); 363 if (ret) { 364 nv50_display_destroy(dev); 365 return ret; 366 } 367 368 return 0; 369} 370 371void 372nv50_display_destroy(struct drm_device *dev) 373{ 374 struct nv50_display *disp = nv50_display(dev); 375 376 nv50_evo_destroy(dev); 377 kfree(disp); 378} 379 380struct nouveau_bo * 381nv50_display_crtc_sema(struct drm_device *dev, int crtc) 382{ 383 return nv50_display(dev)->crtc[crtc].sem.bo; 384} 385 386void 387nv50_display_flip_stop(struct drm_crtc *crtc) 388{ 389 struct nv50_display *disp = nv50_display(crtc->dev); 390 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 391 struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index]; 392 struct nouveau_channel *evo = dispc->sync; 393 int ret; 394 395 ret = RING_SPACE(evo, 8); 396 if (ret) { 397 WARN_ON(1); 398 return; 399 } 400 401 BEGIN_NV04(evo, 0, 0x0084, 1); 402 OUT_RING (evo, 0x00000000); 403 BEGIN_NV04(evo, 0, 0x0094, 1); 404 OUT_RING (evo, 0x00000000); 405 BEGIN_NV04(evo, 0, 0x00c0, 1); 406 OUT_RING (evo, 0x00000000); 407 BEGIN_NV04(evo, 0, 0x0080, 1); 408 OUT_RING (evo, 0x00000000); 409 FIRE_RING (evo); 410} 411 412int 413nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb, 414 struct nouveau_channel *chan) 415{ 416 struct nouveau_drm *drm = nouveau_drm(crtc->dev); 417 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb); 418 struct nv50_display *disp = nv50_display(crtc->dev); 419 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 420 struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index]; 421 struct nouveau_channel *evo = dispc->sync; 422 int ret; 423 424 ret = RING_SPACE(evo, chan ? 25 : 27); 425 if (unlikely(ret)) 426 return ret; 427 428 /* synchronise with the rendering channel, if necessary */ 429 if (likely(chan)) { 430 ret = RING_SPACE(chan, 10); 431 if (ret) { 432 WIND_RING(evo); 433 return ret; 434 } 435 436 if (nv_device(drm->device)->chipset < 0xc0) { 437 BEGIN_NV04(chan, 0, 0x0060, 2); 438 OUT_RING (chan, NvEvoSema0 + nv_crtc->index); 439 OUT_RING (chan, dispc->sem.offset); 440 BEGIN_NV04(chan, 0, 0x006c, 1); 441 OUT_RING (chan, 0xf00d0000 | dispc->sem.value); 442 BEGIN_NV04(chan, 0, 0x0064, 2); 443 OUT_RING (chan, dispc->sem.offset ^ 0x10); 444 OUT_RING (chan, 0x74b1e000); 445 BEGIN_NV04(chan, 0, 0x0060, 1); 446 if (nv_device(drm->device)->chipset < 0x84) 447 OUT_RING (chan, NvSema); 448 else 449 OUT_RING (chan, chan->vram); 450 } else { 451 u64 offset = nvc0_fence_crtc(chan, nv_crtc->index); 452 offset += dispc->sem.offset; 453 BEGIN_NVC0(chan, 0, 0x0010, 4); 454 OUT_RING (chan, upper_32_bits(offset)); 455 OUT_RING (chan, lower_32_bits(offset)); 456 OUT_RING (chan, 0xf00d0000 | dispc->sem.value); 457 OUT_RING (chan, 0x1002); 458 BEGIN_NVC0(chan, 0, 0x0010, 4); 459 OUT_RING (chan, upper_32_bits(offset)); 460 OUT_RING (chan, lower_32_bits(offset ^ 0x10)); 461 OUT_RING (chan, 0x74b1e000); 462 OUT_RING (chan, 0x1001); 463 } 464 FIRE_RING (chan); 465 } else { 466 nouveau_bo_wr32(dispc->sem.bo, dispc->sem.offset / 4, 467 0xf00d0000 | dispc->sem.value); 468 } 469 470 /* queue the flip on the crtc's "display sync" channel */ 471 BEGIN_NV04(evo, 0, 0x0100, 1); 472 OUT_RING (evo, 0xfffe0000); 473 if (chan) { 474 BEGIN_NV04(evo, 0, 0x0084, 1); 475 OUT_RING (evo, 0x00000100); 476 } else { 477 BEGIN_NV04(evo, 0, 0x0084, 1); 478 OUT_RING (evo, 0x00000010); 479 /* allows gamma somehow, PDISP will bitch at you if 480 * you don't wait for vblank before changing this.. 481 */ 482 BEGIN_NV04(evo, 0, 0x00e0, 1); 483 OUT_RING (evo, 0x40000000); 484 } 485 BEGIN_NV04(evo, 0, 0x0088, 4); 486 OUT_RING (evo, dispc->sem.offset); 487 OUT_RING (evo, 0xf00d0000 | dispc->sem.value); 488 OUT_RING (evo, 0x74b1e000); 489 OUT_RING (evo, NvEvoSync); 490 BEGIN_NV04(evo, 0, 0x00a0, 2); 491 OUT_RING (evo, 0x00000000); 492 OUT_RING (evo, 0x00000000); 493 BEGIN_NV04(evo, 0, 0x00c0, 1); 494 OUT_RING (evo, nv_fb->r_dma); 495 BEGIN_NV04(evo, 0, 0x0110, 2); 496 OUT_RING (evo, 0x00000000); 497 OUT_RING (evo, 0x00000000); 498 BEGIN_NV04(evo, 0, 0x0800, 5); 499 OUT_RING (evo, nv_fb->nvbo->bo.offset >> 8); 500 OUT_RING (evo, 0); 501 OUT_RING (evo, (fb->height << 16) | fb->width); 502 OUT_RING (evo, nv_fb->r_pitch); 503 OUT_RING (evo, nv_fb->r_format); 504 BEGIN_NV04(evo, 0, 0x0080, 1); 505 OUT_RING (evo, 0x00000000); 506 FIRE_RING (evo); 507 508 dispc->sem.offset ^= 0x10; 509 dispc->sem.value++; 510 return 0; 511} 512 513static u16 514nv50_display_script_select(struct drm_device *dev, struct dcb_output *dcb, 515 u32 mc, int pxclk) 516{ 517 struct nouveau_drm *drm = nouveau_drm(dev); 518 struct nouveau_connector *nv_connector = NULL; 519 struct drm_encoder *encoder; 520 struct nvbios *bios = &drm->vbios; 521 u32 script = 0, or; 522 523 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 524 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 525 526 if (nv_encoder->dcb != dcb) 527 continue; 528 529 nv_connector = nouveau_encoder_connector_get(nv_encoder); 530 break; 531 } 532 533 or = ffs(dcb->or) - 1; 534 switch (dcb->type) { 535 case DCB_OUTPUT_LVDS: 536 script = (mc >> 8) & 0xf; 537 if (bios->fp_no_ddc) { 538 if (bios->fp.dual_link) 539 script |= 0x0100; 540 if (bios->fp.if_is_24bit) 541 script |= 0x0200; 542 } else { 543 /* determine number of lvds links */ 544 if (nv_connector && nv_connector->edid && 545 nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { 546 /* http://www.spwg.org */ 547 if (((u8 *)nv_connector->edid)[121] == 2) 548 script |= 0x0100; 549 } else 550 if (pxclk >= bios->fp.duallink_transition_clk) { 551 script |= 0x0100; 552 } 553 554 /* determine panel depth */ 555 if (script & 0x0100) { 556 if (bios->fp.strapless_is_24bit & 2) 557 script |= 0x0200; 558 } else { 559 if (bios->fp.strapless_is_24bit & 1) 560 script |= 0x0200; 561 } 562 563 if (nv_connector && nv_connector->edid && 564 (nv_connector->edid->revision >= 4) && 565 (nv_connector->edid->input & 0x70) >= 0x20) 566 script |= 0x0200; 567 } 568 break; 569 case DCB_OUTPUT_TMDS: 570 script = (mc >> 8) & 0xf; 571 if (pxclk >= 165000) 572 script |= 0x0100; 573 break; 574 case DCB_OUTPUT_DP: 575 script = (mc >> 8) & 0xf; 576 break; 577 case DCB_OUTPUT_ANALOG: 578 script = 0xff; 579 break; 580 default: 581 NV_ERROR(drm, "modeset on unsupported output type!\n"); 582 break; 583 } 584 585 return script; 586} 587 588static void 589nv50_display_unk10_handler(struct drm_device *dev) 590{ 591 struct nouveau_device *device = nouveau_dev(dev); 592 struct nouveau_drm *drm = nouveau_drm(dev); 593 struct nv50_display *disp = nv50_display(dev); 594 u32 unk30 = nv_rd32(device, 0x610030), mc; 595 int i, crtc, or = 0, type = DCB_OUTPUT_ANY; 596 597 NV_DEBUG(drm, "0x610030: 0x%08x\n", unk30); 598 disp->irq.dcb = NULL; 599 600 nv_wr32(device, 0x619494, nv_rd32(device, 0x619494) & ~8); 601 602 /* Determine which CRTC we're dealing with, only 1 ever will be 603 * signalled at the same time with the current nouveau code. 604 */ 605 crtc = ffs((unk30 & 0x00000060) >> 5) - 1; 606 if (crtc < 0) 607 goto ack; 608 609 /* Nothing needs to be done for the encoder */ 610 crtc = ffs((unk30 & 0x00000180) >> 7) - 1; 611 if (crtc < 0) 612 goto ack; 613 614 /* Find which encoder was connected to the CRTC */ 615 for (i = 0; type == DCB_OUTPUT_ANY && i < 3; i++) { 616 mc = nv_rd32(device, NV50_PDISPLAY_DAC_MODE_CTRL_C(i)); 617 NV_DEBUG(drm, "DAC-%d mc: 0x%08x\n", i, mc); 618 if (!(mc & (1 << crtc))) 619 continue; 620 621 switch ((mc & 0x00000f00) >> 8) { 622 case 0: type = DCB_OUTPUT_ANALOG; break; 623 case 1: type = DCB_OUTPUT_TV; break; 624 default: 625 NV_ERROR(drm, "invalid mc, DAC-%d: 0x%08x\n", i, mc); 626 goto ack; 627 } 628 629 or = i; 630 } 631 632 for (i = 0; type == DCB_OUTPUT_ANY && i < nv50_sor_nr(dev); i++) { 633 if (nv_device(drm->device)->chipset < 0x90 || 634 nv_device(drm->device)->chipset == 0x92 || 635 nv_device(drm->device)->chipset == 0xa0) 636 mc = nv_rd32(device, NV50_PDISPLAY_SOR_MODE_CTRL_C(i)); 637 else 638 mc = nv_rd32(device, NV90_PDISPLAY_SOR_MODE_CTRL_C(i)); 639 640 NV_DEBUG(drm, "SOR-%d mc: 0x%08x\n", i, mc); 641 if (!(mc & (1 << crtc))) 642 continue; 643 644 switch ((mc & 0x00000f00) >> 8) { 645 case 0: type = DCB_OUTPUT_LVDS; break; 646 case 1: type = DCB_OUTPUT_TMDS; break; 647 case 2: type = DCB_OUTPUT_TMDS; break; 648 case 5: type = DCB_OUTPUT_TMDS; break; 649 case 8: type = DCB_OUTPUT_DP; break; 650 case 9: type = DCB_OUTPUT_DP; break; 651 default: 652 NV_ERROR(drm, "invalid mc, SOR-%d: 0x%08x\n", i, mc); 653 goto ack; 654 } 655 656 or = i; 657 } 658 659 /* There was no encoder to disable */ 660 if (type == DCB_OUTPUT_ANY) 661 goto ack; 662 663 /* Disable the encoder */ 664 for (i = 0; i < drm->vbios.dcb.entries; i++) { 665 struct dcb_output *dcb = &drm->vbios.dcb.entry[i]; 666 667 if (dcb->type == type && (dcb->or & (1 << or))) { 668 nouveau_bios_run_display_table(dev, 0, -1, dcb, -1); 669 disp->irq.dcb = dcb; 670 goto ack; 671 } 672 } 673 674 NV_ERROR(drm, "no dcb for %d %d 0x%08x\n", or, type, mc); 675ack: 676 nv_wr32(device, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10); 677 nv_wr32(device, 0x610030, 0x80000000); 678} 679 680static void 681nv50_display_unk20_handler(struct drm_device *dev) 682{ 683 struct nouveau_device *device = nouveau_dev(dev); 684 struct nouveau_drm *drm = nouveau_drm(dev); 685 struct nv50_display *disp = nv50_display(dev); 686 u32 unk30 = nv_rd32(device, 0x610030), tmp, pclk, script, mc = 0; 687 struct dcb_output *dcb; 688 int i, crtc, or = 0, type = DCB_OUTPUT_ANY; 689 690 NV_DEBUG(drm, "0x610030: 0x%08x\n", unk30); 691 dcb = disp->irq.dcb; 692 if (dcb) { 693 nouveau_bios_run_display_table(dev, 0, -2, dcb, -1); 694 disp->irq.dcb = NULL; 695 } 696 697 /* CRTC clock change requested? */ 698 crtc = ffs((unk30 & 0x00000600) >> 9) - 1; 699 if (crtc >= 0) { 700 pclk = nv_rd32(device, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)); 701 pclk &= 0x003fffff; 702 if (pclk) 703 nv50_crtc_set_clock(dev, crtc, pclk); 704 705 tmp = nv_rd32(device, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc)); 706 tmp &= ~0x000000f; 707 nv_wr32(device, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp); 708 } 709 710 /* Nothing needs to be done for the encoder */ 711 crtc = ffs((unk30 & 0x00000180) >> 7) - 1; 712 if (crtc < 0) 713 goto ack; 714 pclk = nv_rd32(device, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff; 715 716 /* Find which encoder is connected to the CRTC */ 717 for (i = 0; type == DCB_OUTPUT_ANY && i < 3; i++) { 718 mc = nv_rd32(device, NV50_PDISPLAY_DAC_MODE_CTRL_P(i)); 719 NV_DEBUG(drm, "DAC-%d mc: 0x%08x\n", i, mc); 720 if (!(mc & (1 << crtc))) 721 continue; 722 723 switch ((mc & 0x00000f00) >> 8) { 724 case 0: type = DCB_OUTPUT_ANALOG; break; 725 case 1: type = DCB_OUTPUT_TV; break; 726 default: 727 NV_ERROR(drm, "invalid mc, DAC-%d: 0x%08x\n", i, mc); 728 goto ack; 729 } 730 731 or = i; 732 } 733 734 for (i = 0; type == DCB_OUTPUT_ANY && i < nv50_sor_nr(dev); i++) { 735 if (nv_device(drm->device)->chipset < 0x90 || 736 nv_device(drm->device)->chipset == 0x92 || 737 nv_device(drm->device)->chipset == 0xa0) 738 mc = nv_rd32(device, NV50_PDISPLAY_SOR_MODE_CTRL_P(i)); 739 else 740 mc = nv_rd32(device, NV90_PDISPLAY_SOR_MODE_CTRL_P(i)); 741 742 NV_DEBUG(drm, "SOR-%d mc: 0x%08x\n", i, mc); 743 if (!(mc & (1 << crtc))) 744 continue; 745 746 switch ((mc & 0x00000f00) >> 8) { 747 case 0: type = DCB_OUTPUT_LVDS; break; 748 case 1: type = DCB_OUTPUT_TMDS; break; 749 case 2: type = DCB_OUTPUT_TMDS; break; 750 case 5: type = DCB_OUTPUT_TMDS; break; 751 case 8: type = DCB_OUTPUT_DP; break; 752 case 9: type = DCB_OUTPUT_DP; break; 753 default: 754 NV_ERROR(drm, "invalid mc, SOR-%d: 0x%08x\n", i, mc); 755 goto ack; 756 } 757 758 or = i; 759 } 760 761 if (type == DCB_OUTPUT_ANY) 762 goto ack; 763 764 /* Enable the encoder */ 765 for (i = 0; i < drm->vbios.dcb.entries; i++) { 766 dcb = &drm->vbios.dcb.entry[i]; 767 if (dcb->type == type && (dcb->or & (1 << or))) 768 break; 769 } 770 771 if (i == drm->vbios.dcb.entries) { 772 NV_ERROR(drm, "no dcb for %d %d 0x%08x\n", or, type, mc); 773 goto ack; 774 } 775 776 script = nv50_display_script_select(dev, dcb, mc, pclk); 777 nouveau_bios_run_display_table(dev, script, pclk, dcb, -1); 778 779 if (type == DCB_OUTPUT_DP) { 780 int link = !(dcb->dpconf.sor.link & 1); 781 if ((mc & 0x000f0000) == 0x00020000) 782 nv50_sor_dp_calc_tu(dev, or, link, pclk, 18); 783 else 784 nv50_sor_dp_calc_tu(dev, or, link, pclk, 24); 785 } 786 787 if (dcb->type != DCB_OUTPUT_ANALOG) { 788 tmp = nv_rd32(device, NV50_PDISPLAY_SOR_CLK_CTRL2(or)); 789 tmp &= ~0x00000f0f; 790 if (script & 0x0100) 791 tmp |= 0x00000101; 792 nv_wr32(device, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp); 793 } else { 794 nv_wr32(device, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0); 795 } 796 797 disp->irq.dcb = dcb; 798 disp->irq.pclk = pclk; 799 disp->irq.script = script; 800 801ack: 802 nv_wr32(device, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20); 803 nv_wr32(device, 0x610030, 0x80000000); 804} 805 806/* If programming a TMDS output on a SOR that can also be configured for 807 * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off. 808 * 809 * It looks like the VBIOS TMDS scripts make an attempt at this, however, 810 * the VBIOS scripts on at least one board I have only switch it off on 811 * link 0, causing a blank display if the output has previously been 812 * programmed for DisplayPort. 813 */ 814static void 815nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_output *dcb) 816{ 817 struct nouveau_device *device = nouveau_dev(dev); 818 int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1); 819 struct drm_encoder *encoder; 820 u32 tmp; 821 822 if (dcb->type != DCB_OUTPUT_TMDS) 823 return; 824 825 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 826 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 827 828 if (nv_encoder->dcb->type == DCB_OUTPUT_DP && 829 nv_encoder->dcb->or & (1 << or)) { 830 tmp = nv_rd32(device, NV50_SOR_DP_CTRL(or, link)); 831 tmp &= ~NV50_SOR_DP_CTRL_ENABLED; 832 nv_wr32(device, NV50_SOR_DP_CTRL(or, link), tmp); 833 break; 834 } 835 } 836} 837 838static void 839nv50_display_unk40_handler(struct drm_device *dev) 840{ 841 struct nouveau_device *device = nouveau_dev(dev); 842 struct nouveau_drm *drm = nouveau_drm(dev); 843 struct nv50_display *disp = nv50_display(dev); 844 struct dcb_output *dcb = disp->irq.dcb; 845 u16 script = disp->irq.script; 846 u32 unk30 = nv_rd32(device, 0x610030), pclk = disp->irq.pclk; 847 848 NV_DEBUG(drm, "0x610030: 0x%08x\n", unk30); 849 disp->irq.dcb = NULL; 850 if (!dcb) 851 goto ack; 852 853 nouveau_bios_run_display_table(dev, script, -pclk, dcb, -1); 854 nv50_display_unk40_dp_set_tmds(dev, dcb); 855 856ack: 857 nv_wr32(device, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40); 858 nv_wr32(device, 0x610030, 0x80000000); 859 nv_wr32(device, 0x619494, nv_rd32(device, 0x619494) | 8); 860} 861 862static void 863nv50_display_bh(unsigned long data) 864{ 865 struct drm_device *dev = (struct drm_device *)data; 866 struct nouveau_device *device = nouveau_dev(dev); 867 struct nouveau_drm *drm = nouveau_drm(dev); 868 869 for (;;) { 870 uint32_t intr0 = nv_rd32(device, NV50_PDISPLAY_INTR_0); 871 uint32_t intr1 = nv_rd32(device, NV50_PDISPLAY_INTR_1); 872 873 NV_DEBUG(drm, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1); 874 875 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10) 876 nv50_display_unk10_handler(dev); 877 else 878 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20) 879 nv50_display_unk20_handler(dev); 880 else 881 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40) 882 nv50_display_unk40_handler(dev); 883 else 884 break; 885 } 886 887 nv_wr32(device, NV03_PMC_INTR_EN_0, 1); 888} 889 890static void 891nv50_display_error_handler(struct drm_device *dev) 892{ 893 struct nouveau_device *device = nouveau_dev(dev); 894 struct nouveau_drm *drm = nouveau_drm(dev); 895 u32 channels = (nv_rd32(device, NV50_PDISPLAY_INTR_0) & 0x001f0000) >> 16; 896 u32 addr, data; 897 int chid; 898 899 for (chid = 0; chid < 5; chid++) { 900 if (!(channels & (1 << chid))) 901 continue; 902 903 nv_wr32(device, NV50_PDISPLAY_INTR_0, 0x00010000 << chid); 904 addr = nv_rd32(device, NV50_PDISPLAY_TRAPPED_ADDR(chid)); 905 data = nv_rd32(device, NV50_PDISPLAY_TRAPPED_DATA(chid)); 906 NV_ERROR(drm, "EvoCh %d Mthd 0x%04x Data 0x%08x " 907 "(0x%04x 0x%02x)\n", chid, 908 addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf); 909 910 nv_wr32(device, NV50_PDISPLAY_TRAPPED_ADDR(chid), 0x90000000); 911 } 912} 913 914void 915nv50_display_intr(struct drm_device *dev) 916{ 917 struct nouveau_device *device = nouveau_dev(dev); 918 struct nouveau_drm *drm = nouveau_drm(dev); 919 struct nv50_display *disp = nv50_display(dev); 920 uint32_t delayed = 0; 921 922 while (nv_rd32(device, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) { 923 uint32_t intr0 = nv_rd32(device, NV50_PDISPLAY_INTR_0); 924 uint32_t intr1 = nv_rd32(device, NV50_PDISPLAY_INTR_1); 925 uint32_t clock; 926 927 NV_DEBUG(drm, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1); 928 929 if (!intr0 && !(intr1 & ~delayed)) 930 break; 931 932 if (intr0 & 0x001f0000) { 933 nv50_display_error_handler(dev); 934 intr0 &= ~0x001f0000; 935 } 936 937 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) { 938 intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC; 939 delayed |= NV50_PDISPLAY_INTR_1_VBLANK_CRTC; 940 } 941 942 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 | 943 NV50_PDISPLAY_INTR_1_CLK_UNK20 | 944 NV50_PDISPLAY_INTR_1_CLK_UNK40)); 945 if (clock) { 946 nv_wr32(device, NV03_PMC_INTR_EN_0, 0); 947 tasklet_schedule(&disp->tasklet); 948 delayed |= clock; 949 intr1 &= ~clock; 950 } 951 952 if (intr0) { 953 NV_ERROR(drm, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0); 954 nv_wr32(device, NV50_PDISPLAY_INTR_0, intr0); 955 } 956 957 if (intr1) { 958 NV_ERROR(drm, 959 "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1); 960 nv_wr32(device, NV50_PDISPLAY_INTR_1, intr1); 961 } 962 } 963} 964