nv50_display.c revision a0b25635515ef5049f93b032a1e37f18b16e0f6f
1/* 2 * Copyright (C) 2008 Maarten Maathuis. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sublicense, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial 15 * portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27#define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO) 28#include "nv50_display.h" 29#include "nouveau_crtc.h" 30#include "nouveau_encoder.h" 31#include "nouveau_connector.h" 32#include "nouveau_fb.h" 33#include "nouveau_fbcon.h" 34#include "nouveau_ramht.h" 35#include "nouveau_gpio.h" 36#include "drm_crtc_helper.h" 37 38static void nv50_display_isr(struct drm_device *); 39static void nv50_display_bh(unsigned long); 40 41static inline int 42nv50_sor_nr(struct drm_device *dev) 43{ 44 struct drm_nouveau_private *dev_priv = dev->dev_private; 45 46 if (dev_priv->chipset < 0x90 || 47 dev_priv->chipset == 0x92 || 48 dev_priv->chipset == 0xa0) 49 return 2; 50 51 return 4; 52} 53 54static int 55evo_icmd(struct drm_device *dev, int ch, u32 mthd, u32 data) 56{ 57 int ret = 0; 58 nv_mask(dev, 0x610300 + (ch * 0x08), 0x00000001, 0x00000001); 59 nv_wr32(dev, 0x610304 + (ch * 0x08), data); 60 nv_wr32(dev, 0x610300 + (ch * 0x08), 0x80000001 | mthd); 61 if (!nv_wait(dev, 0x610300 + (ch * 0x08), 0x80000000, 0x00000000)) 62 ret = -EBUSY; 63 if (ret || (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)) 64 NV_INFO(dev, "EvoPIO: %d 0x%04x 0x%08x\n", ch, mthd, data); 65 nv_mask(dev, 0x610300 + (ch * 0x08), 0x00000001, 0x00000000); 66 return ret; 67} 68 69int 70nv50_display_early_init(struct drm_device *dev) 71{ 72 u32 ctrl = nv_rd32(dev, 0x610200); 73 int i; 74 75 /* check if master evo channel is already active, a good a sign as any 76 * that the display engine is in a weird state (hibernate/kexec), if 77 * it is, do our best to reset the display engine... 78 */ 79 if ((ctrl & 0x00000003) == 0x00000003) { 80 NV_INFO(dev, "PDISP: EVO(0) 0x%08x, resetting...\n", ctrl); 81 82 /* deactivate both heads first, PDISP will disappear forever 83 * (well, until you power cycle) on some boards as soon as 84 * PMC_ENABLE is hit unless they are.. 85 */ 86 for (i = 0; i < 2; i++) { 87 evo_icmd(dev, 0, 0x0880 + (i * 0x400), 0x05000000); 88 evo_icmd(dev, 0, 0x089c + (i * 0x400), 0); 89 evo_icmd(dev, 0, 0x0840 + (i * 0x400), 0); 90 evo_icmd(dev, 0, 0x0844 + (i * 0x400), 0); 91 evo_icmd(dev, 0, 0x085c + (i * 0x400), 0); 92 evo_icmd(dev, 0, 0x0874 + (i * 0x400), 0); 93 } 94 evo_icmd(dev, 0, 0x0080, 0); 95 96 /* reset PDISP */ 97 nv_mask(dev, 0x000200, 0x40000000, 0x00000000); 98 nv_mask(dev, 0x000200, 0x40000000, 0x40000000); 99 } 100 101 return 0; 102} 103 104void 105nv50_display_late_takedown(struct drm_device *dev) 106{ 107} 108 109int 110nv50_display_sync(struct drm_device *dev) 111{ 112 struct drm_nouveau_private *dev_priv = dev->dev_private; 113 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer; 114 struct nv50_display *disp = nv50_display(dev); 115 struct nouveau_channel *evo = disp->master; 116 u64 start; 117 int ret; 118 119 ret = RING_SPACE(evo, 6); 120 if (ret == 0) { 121 BEGIN_RING(evo, 0, 0x0084, 1); 122 OUT_RING (evo, 0x80000000); 123 BEGIN_RING(evo, 0, 0x0080, 1); 124 OUT_RING (evo, 0); 125 BEGIN_RING(evo, 0, 0x0084, 1); 126 OUT_RING (evo, 0x00000000); 127 128 nv_wo32(disp->ntfy, 0x000, 0x00000000); 129 FIRE_RING (evo); 130 131 start = ptimer->read(dev); 132 do { 133 if (nv_ro32(disp->ntfy, 0x000)) 134 return 0; 135 } while (ptimer->read(dev) - start < 2000000000ULL); 136 } 137 138 return -EBUSY; 139} 140 141int 142nv50_display_init(struct drm_device *dev) 143{ 144 struct drm_connector *connector; 145 struct nouveau_channel *evo; 146 int ret, i; 147 u32 val; 148 149 NV_DEBUG_KMS(dev, "\n"); 150 151 nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004)); 152 153 /* 154 * I think the 0x006101XX range is some kind of main control area 155 * that enables things. 156 */ 157 /* CRTC? */ 158 for (i = 0; i < 2; i++) { 159 val = nv_rd32(dev, 0x00616100 + (i * 0x800)); 160 nv_wr32(dev, 0x00610190 + (i * 0x10), val); 161 val = nv_rd32(dev, 0x00616104 + (i * 0x800)); 162 nv_wr32(dev, 0x00610194 + (i * 0x10), val); 163 val = nv_rd32(dev, 0x00616108 + (i * 0x800)); 164 nv_wr32(dev, 0x00610198 + (i * 0x10), val); 165 val = nv_rd32(dev, 0x0061610c + (i * 0x800)); 166 nv_wr32(dev, 0x0061019c + (i * 0x10), val); 167 } 168 169 /* DAC */ 170 for (i = 0; i < 3; i++) { 171 val = nv_rd32(dev, 0x0061a000 + (i * 0x800)); 172 nv_wr32(dev, 0x006101d0 + (i * 0x04), val); 173 } 174 175 /* SOR */ 176 for (i = 0; i < nv50_sor_nr(dev); i++) { 177 val = nv_rd32(dev, 0x0061c000 + (i * 0x800)); 178 nv_wr32(dev, 0x006101e0 + (i * 0x04), val); 179 } 180 181 /* EXT */ 182 for (i = 0; i < 3; i++) { 183 val = nv_rd32(dev, 0x0061e000 + (i * 0x800)); 184 nv_wr32(dev, 0x006101f0 + (i * 0x04), val); 185 } 186 187 for (i = 0; i < 3; i++) { 188 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 | 189 NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING); 190 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001); 191 } 192 193 /* The precise purpose is unknown, i suspect it has something to do 194 * with text mode. 195 */ 196 if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) { 197 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100); 198 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1); 199 if (!nv_wait(dev, 0x006194e8, 2, 0)) { 200 NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n"); 201 NV_ERROR(dev, "0x6194e8 = 0x%08x\n", 202 nv_rd32(dev, 0x6194e8)); 203 return -EBUSY; 204 } 205 } 206 207 for (i = 0; i < 2; i++) { 208 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000); 209 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 210 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) { 211 NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n"); 212 NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n", 213 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i))); 214 return -EBUSY; 215 } 216 217 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 218 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON); 219 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 220 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 221 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) { 222 NV_ERROR(dev, "timeout: " 223 "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i); 224 NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i, 225 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i))); 226 return -EBUSY; 227 } 228 } 229 230 nv_wr32(dev, NV50_PDISPLAY_PIO_CTRL, 0x00000000); 231 nv_mask(dev, NV50_PDISPLAY_INTR_0, 0x00000000, 0x00000000); 232 nv_wr32(dev, NV50_PDISPLAY_INTR_EN_0, 0x00000000); 233 nv_mask(dev, NV50_PDISPLAY_INTR_1, 0x00000000, 0x00000000); 234 nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1, 235 NV50_PDISPLAY_INTR_EN_1_CLK_UNK10 | 236 NV50_PDISPLAY_INTR_EN_1_CLK_UNK20 | 237 NV50_PDISPLAY_INTR_EN_1_CLK_UNK40); 238 239 /* enable hotplug interrupts */ 240 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 241 struct nouveau_connector *conn = nouveau_connector(connector); 242 nouveau_gpio_irq(dev, 0, conn->hpd, 0xff, true); 243 } 244 245 ret = nv50_evo_init(dev); 246 if (ret) 247 return ret; 248 evo = nv50_display(dev)->master; 249 250 nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->vinst >> 8) | 9); 251 252 ret = RING_SPACE(evo, 3); 253 if (ret) 254 return ret; 255 BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2); 256 OUT_RING (evo, NV50_EVO_UNK84_NOTIFY_DISABLED); 257 OUT_RING (evo, NvEvoSync); 258 259 return nv50_display_sync(dev); 260} 261 262void 263nv50_display_fini(struct drm_device *dev) 264{ 265 struct drm_nouveau_private *dev_priv = dev->dev_private; 266 struct nv50_display *disp = nv50_display(dev); 267 struct nouveau_channel *evo = disp->master; 268 struct drm_crtc *drm_crtc; 269 int ret, i; 270 271 NV_DEBUG_KMS(dev, "\n"); 272 273 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) { 274 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc); 275 276 nv50_crtc_blank(crtc, true); 277 } 278 279 ret = RING_SPACE(evo, 2); 280 if (ret == 0) { 281 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1); 282 OUT_RING(evo, 0); 283 } 284 FIRE_RING(evo); 285 286 /* Almost like ack'ing a vblank interrupt, maybe in the spirit of 287 * cleaning up? 288 */ 289 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) { 290 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc); 291 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index); 292 293 if (!crtc->base.enabled) 294 continue; 295 296 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask); 297 if (!nv_wait(dev, NV50_PDISPLAY_INTR_1, mask, mask)) { 298 NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == " 299 "0x%08x\n", mask, mask); 300 NV_ERROR(dev, "0x610024 = 0x%08x\n", 301 nv_rd32(dev, NV50_PDISPLAY_INTR_1)); 302 } 303 } 304 305 for (i = 0; i < 2; i++) { 306 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0); 307 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 308 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) { 309 NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n"); 310 NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n", 311 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i))); 312 } 313 } 314 315 nv50_evo_fini(dev); 316 317 for (i = 0; i < 3; i++) { 318 if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i), 319 NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) { 320 NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i); 321 NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i, 322 nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i))); 323 } 324 } 325 326 /* disable interrupts. */ 327 nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1, 0x00000000); 328 329 /* disable hotplug interrupts */ 330 nv_wr32(dev, 0xe054, 0xffffffff); 331 nv_wr32(dev, 0xe050, 0x00000000); 332 if (dev_priv->chipset >= 0x90) { 333 nv_wr32(dev, 0xe074, 0xffffffff); 334 nv_wr32(dev, 0xe070, 0x00000000); 335 } 336} 337 338int 339nv50_display_create(struct drm_device *dev) 340{ 341 struct drm_nouveau_private *dev_priv = dev->dev_private; 342 struct dcb_table *dcb = &dev_priv->vbios.dcb; 343 struct drm_connector *connector, *ct; 344 struct nv50_display *priv; 345 int ret, i; 346 347 NV_DEBUG_KMS(dev, "\n"); 348 349 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 350 if (!priv) 351 return -ENOMEM; 352 dev_priv->engine.display.priv = priv; 353 354 /* Create CRTC objects */ 355 for (i = 0; i < 2; i++) 356 nv50_crtc_create(dev, i); 357 358 /* We setup the encoders from the BIOS table */ 359 for (i = 0 ; i < dcb->entries; i++) { 360 struct dcb_entry *entry = &dcb->entry[i]; 361 362 if (entry->location != DCB_LOC_ON_CHIP) { 363 NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n", 364 entry->type, ffs(entry->or) - 1); 365 continue; 366 } 367 368 connector = nouveau_connector_create(dev, entry->connector); 369 if (IS_ERR(connector)) 370 continue; 371 372 switch (entry->type) { 373 case OUTPUT_TMDS: 374 case OUTPUT_LVDS: 375 case OUTPUT_DP: 376 nv50_sor_create(connector, entry); 377 break; 378 case OUTPUT_ANALOG: 379 nv50_dac_create(connector, entry); 380 break; 381 default: 382 NV_WARN(dev, "DCB encoder %d unknown\n", entry->type); 383 continue; 384 } 385 } 386 387 list_for_each_entry_safe(connector, ct, 388 &dev->mode_config.connector_list, head) { 389 if (!connector->encoder_ids[0]) { 390 NV_WARN(dev, "%s has no encoders, removing\n", 391 drm_get_connector_name(connector)); 392 connector->funcs->destroy(connector); 393 } 394 } 395 396 tasklet_init(&priv->tasklet, nv50_display_bh, (unsigned long)dev); 397 nouveau_irq_register(dev, 26, nv50_display_isr); 398 399 ret = nv50_evo_create(dev); 400 if (ret) { 401 nv50_display_destroy(dev); 402 return ret; 403 } 404 405 return 0; 406} 407 408void 409nv50_display_destroy(struct drm_device *dev) 410{ 411 struct nv50_display *disp = nv50_display(dev); 412 413 NV_DEBUG_KMS(dev, "\n"); 414 415 nv50_evo_destroy(dev); 416 nouveau_irq_unregister(dev, 26); 417 kfree(disp); 418} 419 420void 421nv50_display_flip_stop(struct drm_crtc *crtc) 422{ 423 struct nv50_display *disp = nv50_display(crtc->dev); 424 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 425 struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index]; 426 struct nouveau_channel *evo = dispc->sync; 427 int ret; 428 429 ret = RING_SPACE(evo, 8); 430 if (ret) { 431 WARN_ON(1); 432 return; 433 } 434 435 BEGIN_RING(evo, 0, 0x0084, 1); 436 OUT_RING (evo, 0x00000000); 437 BEGIN_RING(evo, 0, 0x0094, 1); 438 OUT_RING (evo, 0x00000000); 439 BEGIN_RING(evo, 0, 0x00c0, 1); 440 OUT_RING (evo, 0x00000000); 441 BEGIN_RING(evo, 0, 0x0080, 1); 442 OUT_RING (evo, 0x00000000); 443 FIRE_RING (evo); 444} 445 446int 447nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb, 448 struct nouveau_channel *chan) 449{ 450 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private; 451 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb); 452 struct nv50_display *disp = nv50_display(crtc->dev); 453 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 454 struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index]; 455 struct nouveau_channel *evo = dispc->sync; 456 int ret; 457 458 ret = RING_SPACE(evo, chan ? 25 : 27); 459 if (unlikely(ret)) 460 return ret; 461 462 /* synchronise with the rendering channel, if necessary */ 463 if (likely(chan)) { 464 ret = RING_SPACE(chan, 10); 465 if (ret) { 466 WIND_RING(evo); 467 return ret; 468 } 469 470 if (dev_priv->chipset < 0xc0) { 471 BEGIN_RING(chan, NvSubSw, 0x0060, 2); 472 OUT_RING (chan, NvEvoSema0 + nv_crtc->index); 473 OUT_RING (chan, dispc->sem.offset); 474 BEGIN_RING(chan, NvSubSw, 0x006c, 1); 475 OUT_RING (chan, 0xf00d0000 | dispc->sem.value); 476 BEGIN_RING(chan, NvSubSw, 0x0064, 2); 477 OUT_RING (chan, dispc->sem.offset ^ 0x10); 478 OUT_RING (chan, 0x74b1e000); 479 BEGIN_RING(chan, NvSubSw, 0x0060, 1); 480 if (dev_priv->chipset < 0x84) 481 OUT_RING (chan, NvSema); 482 else 483 OUT_RING (chan, chan->vram_handle); 484 } else { 485 u64 offset = chan->dispc_vma[nv_crtc->index].offset; 486 offset += dispc->sem.offset; 487 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4); 488 OUT_RING (chan, upper_32_bits(offset)); 489 OUT_RING (chan, lower_32_bits(offset)); 490 OUT_RING (chan, 0xf00d0000 | dispc->sem.value); 491 OUT_RING (chan, 0x1002); 492 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4); 493 OUT_RING (chan, upper_32_bits(offset)); 494 OUT_RING (chan, lower_32_bits(offset ^ 0x10)); 495 OUT_RING (chan, 0x74b1e000); 496 OUT_RING (chan, 0x1001); 497 } 498 FIRE_RING (chan); 499 } else { 500 nouveau_bo_wr32(dispc->sem.bo, dispc->sem.offset / 4, 501 0xf00d0000 | dispc->sem.value); 502 } 503 504 /* queue the flip on the crtc's "display sync" channel */ 505 BEGIN_RING(evo, 0, 0x0100, 1); 506 OUT_RING (evo, 0xfffe0000); 507 if (chan) { 508 BEGIN_RING(evo, 0, 0x0084, 1); 509 OUT_RING (evo, 0x00000100); 510 } else { 511 BEGIN_RING(evo, 0, 0x0084, 1); 512 OUT_RING (evo, 0x00000010); 513 /* allows gamma somehow, PDISP will bitch at you if 514 * you don't wait for vblank before changing this.. 515 */ 516 BEGIN_RING(evo, 0, 0x00e0, 1); 517 OUT_RING (evo, 0x40000000); 518 } 519 BEGIN_RING(evo, 0, 0x0088, 4); 520 OUT_RING (evo, dispc->sem.offset); 521 OUT_RING (evo, 0xf00d0000 | dispc->sem.value); 522 OUT_RING (evo, 0x74b1e000); 523 OUT_RING (evo, NvEvoSync); 524 BEGIN_RING(evo, 0, 0x00a0, 2); 525 OUT_RING (evo, 0x00000000); 526 OUT_RING (evo, 0x00000000); 527 BEGIN_RING(evo, 0, 0x00c0, 1); 528 OUT_RING (evo, nv_fb->r_dma); 529 BEGIN_RING(evo, 0, 0x0110, 2); 530 OUT_RING (evo, 0x00000000); 531 OUT_RING (evo, 0x00000000); 532 BEGIN_RING(evo, 0, 0x0800, 5); 533 OUT_RING (evo, nv_fb->nvbo->bo.offset >> 8); 534 OUT_RING (evo, 0); 535 OUT_RING (evo, (fb->height << 16) | fb->width); 536 OUT_RING (evo, nv_fb->r_pitch); 537 OUT_RING (evo, nv_fb->r_format); 538 BEGIN_RING(evo, 0, 0x0080, 1); 539 OUT_RING (evo, 0x00000000); 540 FIRE_RING (evo); 541 542 dispc->sem.offset ^= 0x10; 543 dispc->sem.value++; 544 return 0; 545} 546 547static u16 548nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb, 549 u32 mc, int pxclk) 550{ 551 struct drm_nouveau_private *dev_priv = dev->dev_private; 552 struct nouveau_connector *nv_connector = NULL; 553 struct drm_encoder *encoder; 554 struct nvbios *bios = &dev_priv->vbios; 555 u32 script = 0, or; 556 557 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 558 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 559 560 if (nv_encoder->dcb != dcb) 561 continue; 562 563 nv_connector = nouveau_encoder_connector_get(nv_encoder); 564 break; 565 } 566 567 or = ffs(dcb->or) - 1; 568 switch (dcb->type) { 569 case OUTPUT_LVDS: 570 script = (mc >> 8) & 0xf; 571 if (bios->fp_no_ddc) { 572 if (bios->fp.dual_link) 573 script |= 0x0100; 574 if (bios->fp.if_is_24bit) 575 script |= 0x0200; 576 } else { 577 /* determine number of lvds links */ 578 if (nv_connector && nv_connector->edid && 579 nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { 580 /* http://www.spwg.org */ 581 if (((u8 *)nv_connector->edid)[121] == 2) 582 script |= 0x0100; 583 } else 584 if (pxclk >= bios->fp.duallink_transition_clk) { 585 script |= 0x0100; 586 } 587 588 /* determine panel depth */ 589 if (script & 0x0100) { 590 if (bios->fp.strapless_is_24bit & 2) 591 script |= 0x0200; 592 } else { 593 if (bios->fp.strapless_is_24bit & 1) 594 script |= 0x0200; 595 } 596 597 if (nv_connector && nv_connector->edid && 598 (nv_connector->edid->revision >= 4) && 599 (nv_connector->edid->input & 0x70) >= 0x20) 600 script |= 0x0200; 601 } 602 603 if (nouveau_uscript_lvds >= 0) { 604 NV_INFO(dev, "override script 0x%04x with 0x%04x " 605 "for output LVDS-%d\n", script, 606 nouveau_uscript_lvds, or); 607 script = nouveau_uscript_lvds; 608 } 609 break; 610 case OUTPUT_TMDS: 611 script = (mc >> 8) & 0xf; 612 if (pxclk >= 165000) 613 script |= 0x0100; 614 615 if (nouveau_uscript_tmds >= 0) { 616 NV_INFO(dev, "override script 0x%04x with 0x%04x " 617 "for output TMDS-%d\n", script, 618 nouveau_uscript_tmds, or); 619 script = nouveau_uscript_tmds; 620 } 621 break; 622 case OUTPUT_DP: 623 script = (mc >> 8) & 0xf; 624 break; 625 case OUTPUT_ANALOG: 626 script = 0xff; 627 break; 628 default: 629 NV_ERROR(dev, "modeset on unsupported output type!\n"); 630 break; 631 } 632 633 return script; 634} 635 636static void 637nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc) 638{ 639 struct drm_nouveau_private *dev_priv = dev->dev_private; 640 struct nouveau_channel *chan, *tmp; 641 642 list_for_each_entry_safe(chan, tmp, &dev_priv->vbl_waiting, 643 nvsw.vbl_wait) { 644 if (chan->nvsw.vblsem_head != crtc) 645 continue; 646 647 nouveau_bo_wr32(chan->notifier_bo, chan->nvsw.vblsem_offset, 648 chan->nvsw.vblsem_rval); 649 list_del(&chan->nvsw.vbl_wait); 650 drm_vblank_put(dev, crtc); 651 } 652 653 drm_handle_vblank(dev, crtc); 654} 655 656static void 657nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr) 658{ 659 if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0) 660 nv50_display_vblank_crtc_handler(dev, 0); 661 662 if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1) 663 nv50_display_vblank_crtc_handler(dev, 1); 664 665 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_VBLANK_CRTC); 666} 667 668static void 669nv50_display_unk10_handler(struct drm_device *dev) 670{ 671 struct drm_nouveau_private *dev_priv = dev->dev_private; 672 struct nv50_display *disp = nv50_display(dev); 673 u32 unk30 = nv_rd32(dev, 0x610030), mc; 674 int i, crtc, or = 0, type = OUTPUT_ANY; 675 676 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30); 677 disp->irq.dcb = NULL; 678 679 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8); 680 681 /* Determine which CRTC we're dealing with, only 1 ever will be 682 * signalled at the same time with the current nouveau code. 683 */ 684 crtc = ffs((unk30 & 0x00000060) >> 5) - 1; 685 if (crtc < 0) 686 goto ack; 687 688 /* Nothing needs to be done for the encoder */ 689 crtc = ffs((unk30 & 0x00000180) >> 7) - 1; 690 if (crtc < 0) 691 goto ack; 692 693 /* Find which encoder was connected to the CRTC */ 694 for (i = 0; type == OUTPUT_ANY && i < 3; i++) { 695 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i)); 696 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc); 697 if (!(mc & (1 << crtc))) 698 continue; 699 700 switch ((mc & 0x00000f00) >> 8) { 701 case 0: type = OUTPUT_ANALOG; break; 702 case 1: type = OUTPUT_TV; break; 703 default: 704 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc); 705 goto ack; 706 } 707 708 or = i; 709 } 710 711 for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) { 712 if (dev_priv->chipset < 0x90 || 713 dev_priv->chipset == 0x92 || 714 dev_priv->chipset == 0xa0) 715 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i)); 716 else 717 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i)); 718 719 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc); 720 if (!(mc & (1 << crtc))) 721 continue; 722 723 switch ((mc & 0x00000f00) >> 8) { 724 case 0: type = OUTPUT_LVDS; break; 725 case 1: type = OUTPUT_TMDS; break; 726 case 2: type = OUTPUT_TMDS; break; 727 case 5: type = OUTPUT_TMDS; break; 728 case 8: type = OUTPUT_DP; break; 729 case 9: type = OUTPUT_DP; break; 730 default: 731 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc); 732 goto ack; 733 } 734 735 or = i; 736 } 737 738 /* There was no encoder to disable */ 739 if (type == OUTPUT_ANY) 740 goto ack; 741 742 /* Disable the encoder */ 743 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) { 744 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i]; 745 746 if (dcb->type == type && (dcb->or & (1 << or))) { 747 nouveau_bios_run_display_table(dev, 0, -1, dcb, -1); 748 disp->irq.dcb = dcb; 749 goto ack; 750 } 751 } 752 753 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc); 754ack: 755 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10); 756 nv_wr32(dev, 0x610030, 0x80000000); 757} 758 759static void 760nv50_display_unk20_handler(struct drm_device *dev) 761{ 762 struct drm_nouveau_private *dev_priv = dev->dev_private; 763 struct nv50_display *disp = nv50_display(dev); 764 u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc = 0; 765 struct dcb_entry *dcb; 766 int i, crtc, or = 0, type = OUTPUT_ANY; 767 768 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30); 769 dcb = disp->irq.dcb; 770 if (dcb) { 771 nouveau_bios_run_display_table(dev, 0, -2, dcb, -1); 772 disp->irq.dcb = NULL; 773 } 774 775 /* CRTC clock change requested? */ 776 crtc = ffs((unk30 & 0x00000600) >> 9) - 1; 777 if (crtc >= 0) { 778 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)); 779 pclk &= 0x003fffff; 780 if (pclk) 781 nv50_crtc_set_clock(dev, crtc, pclk); 782 783 tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc)); 784 tmp &= ~0x000000f; 785 nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp); 786 } 787 788 /* Nothing needs to be done for the encoder */ 789 crtc = ffs((unk30 & 0x00000180) >> 7) - 1; 790 if (crtc < 0) 791 goto ack; 792 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff; 793 794 /* Find which encoder is connected to the CRTC */ 795 for (i = 0; type == OUTPUT_ANY && i < 3; i++) { 796 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i)); 797 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc); 798 if (!(mc & (1 << crtc))) 799 continue; 800 801 switch ((mc & 0x00000f00) >> 8) { 802 case 0: type = OUTPUT_ANALOG; break; 803 case 1: type = OUTPUT_TV; break; 804 default: 805 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc); 806 goto ack; 807 } 808 809 or = i; 810 } 811 812 for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) { 813 if (dev_priv->chipset < 0x90 || 814 dev_priv->chipset == 0x92 || 815 dev_priv->chipset == 0xa0) 816 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(i)); 817 else 818 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(i)); 819 820 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc); 821 if (!(mc & (1 << crtc))) 822 continue; 823 824 switch ((mc & 0x00000f00) >> 8) { 825 case 0: type = OUTPUT_LVDS; break; 826 case 1: type = OUTPUT_TMDS; break; 827 case 2: type = OUTPUT_TMDS; break; 828 case 5: type = OUTPUT_TMDS; break; 829 case 8: type = OUTPUT_DP; break; 830 case 9: type = OUTPUT_DP; break; 831 default: 832 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc); 833 goto ack; 834 } 835 836 or = i; 837 } 838 839 if (type == OUTPUT_ANY) 840 goto ack; 841 842 /* Enable the encoder */ 843 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) { 844 dcb = &dev_priv->vbios.dcb.entry[i]; 845 if (dcb->type == type && (dcb->or & (1 << or))) 846 break; 847 } 848 849 if (i == dev_priv->vbios.dcb.entries) { 850 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc); 851 goto ack; 852 } 853 854 script = nv50_display_script_select(dev, dcb, mc, pclk); 855 nouveau_bios_run_display_table(dev, script, pclk, dcb, -1); 856 857 if (type == OUTPUT_DP) { 858 int link = !(dcb->dpconf.sor.link & 1); 859 if ((mc & 0x000f0000) == 0x00020000) 860 nouveau_dp_tu_update(dev, or, link, pclk, 18); 861 else 862 nouveau_dp_tu_update(dev, or, link, pclk, 24); 863 } 864 865 if (dcb->type != OUTPUT_ANALOG) { 866 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or)); 867 tmp &= ~0x00000f0f; 868 if (script & 0x0100) 869 tmp |= 0x00000101; 870 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp); 871 } else { 872 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0); 873 } 874 875 disp->irq.dcb = dcb; 876 disp->irq.pclk = pclk; 877 disp->irq.script = script; 878 879ack: 880 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20); 881 nv_wr32(dev, 0x610030, 0x80000000); 882} 883 884/* If programming a TMDS output on a SOR that can also be configured for 885 * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off. 886 * 887 * It looks like the VBIOS TMDS scripts make an attempt at this, however, 888 * the VBIOS scripts on at least one board I have only switch it off on 889 * link 0, causing a blank display if the output has previously been 890 * programmed for DisplayPort. 891 */ 892static void 893nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_entry *dcb) 894{ 895 int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1); 896 struct drm_encoder *encoder; 897 u32 tmp; 898 899 if (dcb->type != OUTPUT_TMDS) 900 return; 901 902 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 903 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 904 905 if (nv_encoder->dcb->type == OUTPUT_DP && 906 nv_encoder->dcb->or & (1 << or)) { 907 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link)); 908 tmp &= ~NV50_SOR_DP_CTRL_ENABLED; 909 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp); 910 break; 911 } 912 } 913} 914 915static void 916nv50_display_unk40_handler(struct drm_device *dev) 917{ 918 struct nv50_display *disp = nv50_display(dev); 919 struct dcb_entry *dcb = disp->irq.dcb; 920 u16 script = disp->irq.script; 921 u32 unk30 = nv_rd32(dev, 0x610030), pclk = disp->irq.pclk; 922 923 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30); 924 disp->irq.dcb = NULL; 925 if (!dcb) 926 goto ack; 927 928 nouveau_bios_run_display_table(dev, script, -pclk, dcb, -1); 929 nv50_display_unk40_dp_set_tmds(dev, dcb); 930 931ack: 932 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40); 933 nv_wr32(dev, 0x610030, 0x80000000); 934 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8); 935} 936 937static void 938nv50_display_bh(unsigned long data) 939{ 940 struct drm_device *dev = (struct drm_device *)data; 941 942 for (;;) { 943 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0); 944 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1); 945 946 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1); 947 948 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10) 949 nv50_display_unk10_handler(dev); 950 else 951 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20) 952 nv50_display_unk20_handler(dev); 953 else 954 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40) 955 nv50_display_unk40_handler(dev); 956 else 957 break; 958 } 959 960 nv_wr32(dev, NV03_PMC_INTR_EN_0, 1); 961} 962 963static void 964nv50_display_error_handler(struct drm_device *dev) 965{ 966 u32 channels = (nv_rd32(dev, NV50_PDISPLAY_INTR_0) & 0x001f0000) >> 16; 967 u32 addr, data; 968 int chid; 969 970 for (chid = 0; chid < 5; chid++) { 971 if (!(channels & (1 << chid))) 972 continue; 973 974 nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000 << chid); 975 addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid)); 976 data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA(chid)); 977 NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x " 978 "(0x%04x 0x%02x)\n", chid, 979 addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf); 980 981 nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid), 0x90000000); 982 } 983} 984 985static void 986nv50_display_isr(struct drm_device *dev) 987{ 988 struct nv50_display *disp = nv50_display(dev); 989 uint32_t delayed = 0; 990 991 while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) { 992 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0); 993 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1); 994 uint32_t clock; 995 996 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1); 997 998 if (!intr0 && !(intr1 & ~delayed)) 999 break; 1000 1001 if (intr0 & 0x001f0000) { 1002 nv50_display_error_handler(dev); 1003 intr0 &= ~0x001f0000; 1004 } 1005 1006 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) { 1007 nv50_display_vblank_handler(dev, intr1); 1008 intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC; 1009 } 1010 1011 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 | 1012 NV50_PDISPLAY_INTR_1_CLK_UNK20 | 1013 NV50_PDISPLAY_INTR_1_CLK_UNK40)); 1014 if (clock) { 1015 nv_wr32(dev, NV03_PMC_INTR_EN_0, 0); 1016 tasklet_schedule(&disp->tasklet); 1017 delayed |= clock; 1018 intr1 &= ~clock; 1019 } 1020 1021 if (intr0) { 1022 NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0); 1023 nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0); 1024 } 1025 1026 if (intr1) { 1027 NV_ERROR(dev, 1028 "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1); 1029 nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1); 1030 } 1031 } 1032} 1033