nv50_display.c revision b7bc613a4cc08d867b43189c2af0bb83b1fa1dc6
1/* 2 * Copyright (C) 2008 Maarten Maathuis. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sublicense, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial 15 * portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27#include "nv50_display.h" 28#include "nouveau_crtc.h" 29#include "nouveau_encoder.h" 30#include "nouveau_connector.h" 31#include "nouveau_fb.h" 32#include "nouveau_fbcon.h" 33#include "nouveau_ramht.h" 34#include "drm_crtc_helper.h" 35 36static inline int 37nv50_sor_nr(struct drm_device *dev) 38{ 39 struct drm_nouveau_private *dev_priv = dev->dev_private; 40 41 if (dev_priv->chipset < 0x90 || 42 dev_priv->chipset == 0x92 || 43 dev_priv->chipset == 0xa0) 44 return 2; 45 46 return 4; 47} 48 49int 50nv50_display_early_init(struct drm_device *dev) 51{ 52 return 0; 53} 54 55void 56nv50_display_late_takedown(struct drm_device *dev) 57{ 58} 59 60int 61nv50_display_init(struct drm_device *dev) 62{ 63 struct drm_nouveau_private *dev_priv = dev->dev_private; 64 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio; 65 struct drm_connector *connector; 66 struct nouveau_channel *evo; 67 int ret, i; 68 u32 val; 69 70 NV_DEBUG_KMS(dev, "\n"); 71 72 nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004)); 73 74 /* 75 * I think the 0x006101XX range is some kind of main control area 76 * that enables things. 77 */ 78 /* CRTC? */ 79 for (i = 0; i < 2; i++) { 80 val = nv_rd32(dev, 0x00616100 + (i * 0x800)); 81 nv_wr32(dev, 0x00610190 + (i * 0x10), val); 82 val = nv_rd32(dev, 0x00616104 + (i * 0x800)); 83 nv_wr32(dev, 0x00610194 + (i * 0x10), val); 84 val = nv_rd32(dev, 0x00616108 + (i * 0x800)); 85 nv_wr32(dev, 0x00610198 + (i * 0x10), val); 86 val = nv_rd32(dev, 0x0061610c + (i * 0x800)); 87 nv_wr32(dev, 0x0061019c + (i * 0x10), val); 88 } 89 90 /* DAC */ 91 for (i = 0; i < 3; i++) { 92 val = nv_rd32(dev, 0x0061a000 + (i * 0x800)); 93 nv_wr32(dev, 0x006101d0 + (i * 0x04), val); 94 } 95 96 /* SOR */ 97 for (i = 0; i < nv50_sor_nr(dev); i++) { 98 val = nv_rd32(dev, 0x0061c000 + (i * 0x800)); 99 nv_wr32(dev, 0x006101e0 + (i * 0x04), val); 100 } 101 102 /* EXT */ 103 for (i = 0; i < 3; i++) { 104 val = nv_rd32(dev, 0x0061e000 + (i * 0x800)); 105 nv_wr32(dev, 0x006101f0 + (i * 0x04), val); 106 } 107 108 for (i = 0; i < 3; i++) { 109 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 | 110 NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING); 111 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001); 112 } 113 114 /* The precise purpose is unknown, i suspect it has something to do 115 * with text mode. 116 */ 117 if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) { 118 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100); 119 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1); 120 if (!nv_wait(dev, 0x006194e8, 2, 0)) { 121 NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n"); 122 NV_ERROR(dev, "0x6194e8 = 0x%08x\n", 123 nv_rd32(dev, 0x6194e8)); 124 return -EBUSY; 125 } 126 } 127 128 for (i = 0; i < 2; i++) { 129 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000); 130 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 131 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) { 132 NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n"); 133 NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n", 134 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i))); 135 return -EBUSY; 136 } 137 138 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 139 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON); 140 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 141 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 142 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) { 143 NV_ERROR(dev, "timeout: " 144 "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i); 145 NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i, 146 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i))); 147 return -EBUSY; 148 } 149 } 150 151 nv_wr32(dev, NV50_PDISPLAY_PIO_CTRL, 0x00000000); 152 nv_wr32(dev, 0x610028, 0x00000000); 153 nv_mask(dev, NV50_PDISPLAY_INTR_0, 0x00000000, 0x00000000); 154 nv_mask(dev, NV50_PDISPLAY_INTR_1, 0x00000000, 0x00000000); 155 nv_wr32(dev, NV50_PDISPLAY_INTR_EN, 156 NV50_PDISPLAY_INTR_EN_CLK_UNK10 | 157 NV50_PDISPLAY_INTR_EN_CLK_UNK20 | 158 NV50_PDISPLAY_INTR_EN_CLK_UNK40); 159 160 /* enable hotplug interrupts */ 161 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 162 struct nouveau_connector *conn = nouveau_connector(connector); 163 164 if (conn->dcb->gpio_tag == 0xff) 165 continue; 166 167 pgpio->irq_enable(dev, conn->dcb->gpio_tag, true); 168 } 169 170 ret = nv50_evo_init(dev); 171 if (ret) 172 return ret; 173 evo = dev_priv->evo; 174 175 nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->vinst >> 8) | 9); 176 177 ret = RING_SPACE(evo, 11); 178 if (ret) 179 return ret; 180 BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2); 181 OUT_RING(evo, NV50_EVO_UNK84_NOTIFY_DISABLED); 182 OUT_RING(evo, NV50_EVO_DMA_NOTIFY_HANDLE_NONE); 183 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, FB_DMA), 1); 184 OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE); 185 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK0800), 1); 186 OUT_RING(evo, 0); 187 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, DISPLAY_START), 1); 188 OUT_RING(evo, 0); 189 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK082C), 1); 190 OUT_RING(evo, 0); 191 FIRE_RING(evo); 192 if (!nv_wait(dev, 0x640004, 0xffffffff, evo->dma.put << 2)) 193 NV_ERROR(dev, "evo pushbuf stalled\n"); 194 195 196 return 0; 197} 198 199static int nv50_display_disable(struct drm_device *dev) 200{ 201 struct drm_nouveau_private *dev_priv = dev->dev_private; 202 struct drm_crtc *drm_crtc; 203 int ret, i; 204 205 NV_DEBUG_KMS(dev, "\n"); 206 207 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) { 208 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc); 209 210 nv50_crtc_blank(crtc, true); 211 } 212 213 ret = RING_SPACE(dev_priv->evo, 2); 214 if (ret == 0) { 215 BEGIN_RING(dev_priv->evo, 0, NV50_EVO_UPDATE, 1); 216 OUT_RING(dev_priv->evo, 0); 217 } 218 FIRE_RING(dev_priv->evo); 219 220 /* Almost like ack'ing a vblank interrupt, maybe in the spirit of 221 * cleaning up? 222 */ 223 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) { 224 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc); 225 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index); 226 227 if (!crtc->base.enabled) 228 continue; 229 230 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask); 231 if (!nv_wait(dev, NV50_PDISPLAY_INTR_1, mask, mask)) { 232 NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == " 233 "0x%08x\n", mask, mask); 234 NV_ERROR(dev, "0x610024 = 0x%08x\n", 235 nv_rd32(dev, NV50_PDISPLAY_INTR_1)); 236 } 237 } 238 239 nv50_evo_fini(dev); 240 241 for (i = 0; i < 3; i++) { 242 if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i), 243 NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) { 244 NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i); 245 NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i, 246 nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i))); 247 } 248 } 249 250 /* disable interrupts. */ 251 nv_wr32(dev, NV50_PDISPLAY_INTR_EN, 0x00000000); 252 253 /* disable hotplug interrupts */ 254 nv_wr32(dev, 0xe054, 0xffffffff); 255 nv_wr32(dev, 0xe050, 0x00000000); 256 if (dev_priv->chipset >= 0x90) { 257 nv_wr32(dev, 0xe074, 0xffffffff); 258 nv_wr32(dev, 0xe070, 0x00000000); 259 } 260 return 0; 261} 262 263int nv50_display_create(struct drm_device *dev) 264{ 265 struct drm_nouveau_private *dev_priv = dev->dev_private; 266 struct dcb_table *dcb = &dev_priv->vbios.dcb; 267 struct drm_connector *connector, *ct; 268 int ret, i; 269 270 NV_DEBUG_KMS(dev, "\n"); 271 272 /* init basic kernel modesetting */ 273 drm_mode_config_init(dev); 274 275 /* Initialise some optional connector properties. */ 276 drm_mode_create_scaling_mode_property(dev); 277 drm_mode_create_dithering_property(dev); 278 279 dev->mode_config.min_width = 0; 280 dev->mode_config.min_height = 0; 281 282 dev->mode_config.funcs = (void *)&nouveau_mode_config_funcs; 283 284 dev->mode_config.max_width = 8192; 285 dev->mode_config.max_height = 8192; 286 287 dev->mode_config.fb_base = dev_priv->fb_phys; 288 289 /* Create CRTC objects */ 290 for (i = 0; i < 2; i++) 291 nv50_crtc_create(dev, i); 292 293 /* We setup the encoders from the BIOS table */ 294 for (i = 0 ; i < dcb->entries; i++) { 295 struct dcb_entry *entry = &dcb->entry[i]; 296 297 if (entry->location != DCB_LOC_ON_CHIP) { 298 NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n", 299 entry->type, ffs(entry->or) - 1); 300 continue; 301 } 302 303 connector = nouveau_connector_create(dev, entry->connector); 304 if (IS_ERR(connector)) 305 continue; 306 307 switch (entry->type) { 308 case OUTPUT_TMDS: 309 case OUTPUT_LVDS: 310 case OUTPUT_DP: 311 nv50_sor_create(connector, entry); 312 break; 313 case OUTPUT_ANALOG: 314 nv50_dac_create(connector, entry); 315 break; 316 default: 317 NV_WARN(dev, "DCB encoder %d unknown\n", entry->type); 318 continue; 319 } 320 } 321 322 list_for_each_entry_safe(connector, ct, 323 &dev->mode_config.connector_list, head) { 324 if (!connector->encoder_ids[0]) { 325 NV_WARN(dev, "%s has no encoders, removing\n", 326 drm_get_connector_name(connector)); 327 connector->funcs->destroy(connector); 328 } 329 } 330 331 ret = nv50_display_init(dev); 332 if (ret) { 333 nv50_display_destroy(dev); 334 return ret; 335 } 336 337 return 0; 338} 339 340void 341nv50_display_destroy(struct drm_device *dev) 342{ 343 NV_DEBUG_KMS(dev, "\n"); 344 345 drm_mode_config_cleanup(dev); 346 347 nv50_display_disable(dev); 348} 349 350static u16 351nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb, 352 u32 mc, int pxclk) 353{ 354 struct drm_nouveau_private *dev_priv = dev->dev_private; 355 struct nouveau_connector *nv_connector = NULL; 356 struct drm_encoder *encoder; 357 struct nvbios *bios = &dev_priv->vbios; 358 u32 script = 0, or; 359 360 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 361 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 362 363 if (nv_encoder->dcb != dcb) 364 continue; 365 366 nv_connector = nouveau_encoder_connector_get(nv_encoder); 367 break; 368 } 369 370 or = ffs(dcb->or) - 1; 371 switch (dcb->type) { 372 case OUTPUT_LVDS: 373 script = (mc >> 8) & 0xf; 374 if (bios->fp_no_ddc) { 375 if (bios->fp.dual_link) 376 script |= 0x0100; 377 if (bios->fp.if_is_24bit) 378 script |= 0x0200; 379 } else { 380 if (pxclk >= bios->fp.duallink_transition_clk) { 381 script |= 0x0100; 382 if (bios->fp.strapless_is_24bit & 2) 383 script |= 0x0200; 384 } else 385 if (bios->fp.strapless_is_24bit & 1) 386 script |= 0x0200; 387 388 if (nv_connector && nv_connector->edid && 389 (nv_connector->edid->revision >= 4) && 390 (nv_connector->edid->input & 0x70) >= 0x20) 391 script |= 0x0200; 392 } 393 394 if (nouveau_uscript_lvds >= 0) { 395 NV_INFO(dev, "override script 0x%04x with 0x%04x " 396 "for output LVDS-%d\n", script, 397 nouveau_uscript_lvds, or); 398 script = nouveau_uscript_lvds; 399 } 400 break; 401 case OUTPUT_TMDS: 402 script = (mc >> 8) & 0xf; 403 if (pxclk >= 165000) 404 script |= 0x0100; 405 406 if (nouveau_uscript_tmds >= 0) { 407 NV_INFO(dev, "override script 0x%04x with 0x%04x " 408 "for output TMDS-%d\n", script, 409 nouveau_uscript_tmds, or); 410 script = nouveau_uscript_tmds; 411 } 412 break; 413 case OUTPUT_DP: 414 script = (mc >> 8) & 0xf; 415 break; 416 case OUTPUT_ANALOG: 417 script = 0xff; 418 break; 419 default: 420 NV_ERROR(dev, "modeset on unsupported output type!\n"); 421 break; 422 } 423 424 return script; 425} 426 427static void 428nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc) 429{ 430 struct drm_nouveau_private *dev_priv = dev->dev_private; 431 struct nouveau_channel *chan; 432 struct list_head *entry, *tmp; 433 434 list_for_each_safe(entry, tmp, &dev_priv->vbl_waiting) { 435 chan = list_entry(entry, struct nouveau_channel, nvsw.vbl_wait); 436 437 nouveau_bo_wr32(chan->notifier_bo, chan->nvsw.vblsem_offset, 438 chan->nvsw.vblsem_rval); 439 list_del(&chan->nvsw.vbl_wait); 440 } 441} 442 443static void 444nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr) 445{ 446 intr &= NV50_PDISPLAY_INTR_1_VBLANK_CRTC; 447 448 if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0) 449 nv50_display_vblank_crtc_handler(dev, 0); 450 451 if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1) 452 nv50_display_vblank_crtc_handler(dev, 1); 453 454 nv_wr32(dev, NV50_PDISPLAY_INTR_EN, nv_rd32(dev, 455 NV50_PDISPLAY_INTR_EN) & ~intr); 456 nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr); 457} 458 459static void 460nv50_display_unk10_handler(struct drm_device *dev) 461{ 462 struct drm_nouveau_private *dev_priv = dev->dev_private; 463 u32 unk30 = nv_rd32(dev, 0x610030), mc; 464 int i, crtc, or, type = OUTPUT_ANY; 465 466 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30); 467 dev_priv->evo_irq.dcb = NULL; 468 469 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8); 470 471 /* Determine which CRTC we're dealing with, only 1 ever will be 472 * signalled at the same time with the current nouveau code. 473 */ 474 crtc = ffs((unk30 & 0x00000060) >> 5) - 1; 475 if (crtc < 0) 476 goto ack; 477 478 /* Nothing needs to be done for the encoder */ 479 crtc = ffs((unk30 & 0x00000180) >> 7) - 1; 480 if (crtc < 0) 481 goto ack; 482 483 /* Find which encoder was connected to the CRTC */ 484 for (i = 0; type == OUTPUT_ANY && i < 3; i++) { 485 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i)); 486 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc); 487 if (!(mc & (1 << crtc))) 488 continue; 489 490 switch ((mc & 0x00000f00) >> 8) { 491 case 0: type = OUTPUT_ANALOG; break; 492 case 1: type = OUTPUT_TV; break; 493 default: 494 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc); 495 goto ack; 496 } 497 498 or = i; 499 } 500 501 for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) { 502 if (dev_priv->chipset < 0x90 || 503 dev_priv->chipset == 0x92 || 504 dev_priv->chipset == 0xa0) 505 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i)); 506 else 507 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i)); 508 509 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc); 510 if (!(mc & (1 << crtc))) 511 continue; 512 513 switch ((mc & 0x00000f00) >> 8) { 514 case 0: type = OUTPUT_LVDS; break; 515 case 1: type = OUTPUT_TMDS; break; 516 case 2: type = OUTPUT_TMDS; break; 517 case 5: type = OUTPUT_TMDS; break; 518 case 8: type = OUTPUT_DP; break; 519 case 9: type = OUTPUT_DP; break; 520 default: 521 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc); 522 goto ack; 523 } 524 525 or = i; 526 } 527 528 /* There was no encoder to disable */ 529 if (type == OUTPUT_ANY) 530 goto ack; 531 532 /* Disable the encoder */ 533 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) { 534 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i]; 535 536 if (dcb->type == type && (dcb->or & (1 << or))) { 537 nouveau_bios_run_display_table(dev, dcb, 0, -1); 538 dev_priv->evo_irq.dcb = dcb; 539 goto ack; 540 } 541 } 542 543 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc); 544ack: 545 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10); 546 nv_wr32(dev, 0x610030, 0x80000000); 547} 548 549static void 550nv50_display_unk20_dp_hack(struct drm_device *dev, struct dcb_entry *dcb) 551{ 552 int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1); 553 struct drm_encoder *encoder; 554 uint32_t tmp, unk0 = 0, unk1 = 0; 555 556 if (dcb->type != OUTPUT_DP) 557 return; 558 559 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 560 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 561 562 if (nv_encoder->dcb == dcb) { 563 unk0 = nv_encoder->dp.unk0; 564 unk1 = nv_encoder->dp.unk1; 565 break; 566 } 567 } 568 569 if (unk0 || unk1) { 570 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link)); 571 tmp &= 0xfffffe03; 572 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp | unk0); 573 574 tmp = nv_rd32(dev, NV50_SOR_DP_UNK128(or, link)); 575 tmp &= 0xfef080c0; 576 nv_wr32(dev, NV50_SOR_DP_UNK128(or, link), tmp | unk1); 577 } 578} 579 580static void 581nv50_display_unk20_handler(struct drm_device *dev) 582{ 583 struct drm_nouveau_private *dev_priv = dev->dev_private; 584 u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc; 585 struct dcb_entry *dcb; 586 int i, crtc, or, type = OUTPUT_ANY; 587 588 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30); 589 dcb = dev_priv->evo_irq.dcb; 590 if (dcb) { 591 nouveau_bios_run_display_table(dev, dcb, 0, -2); 592 dev_priv->evo_irq.dcb = NULL; 593 } 594 595 /* CRTC clock change requested? */ 596 crtc = ffs((unk30 & 0x00000600) >> 9) - 1; 597 if (crtc >= 0) { 598 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)); 599 pclk &= 0x003fffff; 600 601 nv50_crtc_set_clock(dev, crtc, pclk); 602 603 tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc)); 604 tmp &= ~0x000000f; 605 nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp); 606 } 607 608 /* Nothing needs to be done for the encoder */ 609 crtc = ffs((unk30 & 0x00000180) >> 7) - 1; 610 if (crtc < 0) 611 goto ack; 612 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff; 613 614 /* Find which encoder is connected to the CRTC */ 615 for (i = 0; type == OUTPUT_ANY && i < 3; i++) { 616 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i)); 617 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc); 618 if (!(mc & (1 << crtc))) 619 continue; 620 621 switch ((mc & 0x00000f00) >> 8) { 622 case 0: type = OUTPUT_ANALOG; break; 623 case 1: type = OUTPUT_TV; break; 624 default: 625 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc); 626 goto ack; 627 } 628 629 or = i; 630 } 631 632 for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) { 633 if (dev_priv->chipset < 0x90 || 634 dev_priv->chipset == 0x92 || 635 dev_priv->chipset == 0xa0) 636 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(i)); 637 else 638 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(i)); 639 640 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc); 641 if (!(mc & (1 << crtc))) 642 continue; 643 644 switch ((mc & 0x00000f00) >> 8) { 645 case 0: type = OUTPUT_LVDS; break; 646 case 1: type = OUTPUT_TMDS; break; 647 case 2: type = OUTPUT_TMDS; break; 648 case 5: type = OUTPUT_TMDS; break; 649 case 8: type = OUTPUT_DP; break; 650 case 9: type = OUTPUT_DP; break; 651 default: 652 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc); 653 goto ack; 654 } 655 656 or = i; 657 } 658 659 if (type == OUTPUT_ANY) 660 goto ack; 661 662 /* Enable the encoder */ 663 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) { 664 dcb = &dev_priv->vbios.dcb.entry[i]; 665 if (dcb->type == type && (dcb->or & (1 << or))) 666 break; 667 } 668 669 if (i == dev_priv->vbios.dcb.entries) { 670 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc); 671 goto ack; 672 } 673 674 script = nv50_display_script_select(dev, dcb, mc, pclk); 675 nouveau_bios_run_display_table(dev, dcb, script, pclk); 676 677 nv50_display_unk20_dp_hack(dev, dcb); 678 679 if (dcb->type != OUTPUT_ANALOG) { 680 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or)); 681 tmp &= ~0x00000f0f; 682 if (script & 0x0100) 683 tmp |= 0x00000101; 684 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp); 685 } else { 686 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0); 687 } 688 689 dev_priv->evo_irq.dcb = dcb; 690 dev_priv->evo_irq.pclk = pclk; 691 dev_priv->evo_irq.script = script; 692 693ack: 694 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20); 695 nv_wr32(dev, 0x610030, 0x80000000); 696} 697 698/* If programming a TMDS output on a SOR that can also be configured for 699 * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off. 700 * 701 * It looks like the VBIOS TMDS scripts make an attempt at this, however, 702 * the VBIOS scripts on at least one board I have only switch it off on 703 * link 0, causing a blank display if the output has previously been 704 * programmed for DisplayPort. 705 */ 706static void 707nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_entry *dcb) 708{ 709 int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1); 710 struct drm_encoder *encoder; 711 u32 tmp; 712 713 if (dcb->type != OUTPUT_TMDS) 714 return; 715 716 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 717 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 718 719 if (nv_encoder->dcb->type == OUTPUT_DP && 720 nv_encoder->dcb->or & (1 << or)) { 721 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link)); 722 tmp &= ~NV50_SOR_DP_CTRL_ENABLED; 723 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp); 724 break; 725 } 726 } 727} 728 729static void 730nv50_display_unk40_handler(struct drm_device *dev) 731{ 732 struct drm_nouveau_private *dev_priv = dev->dev_private; 733 struct dcb_entry *dcb = dev_priv->evo_irq.dcb; 734 u16 script = dev_priv->evo_irq.script; 735 u32 unk30 = nv_rd32(dev, 0x610030), pclk = dev_priv->evo_irq.pclk; 736 737 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30); 738 dev_priv->evo_irq.dcb = NULL; 739 if (!dcb) 740 goto ack; 741 742 nouveau_bios_run_display_table(dev, dcb, script, -pclk); 743 nv50_display_unk40_dp_set_tmds(dev, dcb); 744 745ack: 746 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40); 747 nv_wr32(dev, 0x610030, 0x80000000); 748 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8); 749} 750 751void 752nv50_display_irq_handler_bh(struct work_struct *work) 753{ 754 struct drm_nouveau_private *dev_priv = 755 container_of(work, struct drm_nouveau_private, irq_work); 756 struct drm_device *dev = dev_priv->dev; 757 758 for (;;) { 759 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0); 760 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1); 761 762 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1); 763 764 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10) 765 nv50_display_unk10_handler(dev); 766 else 767 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20) 768 nv50_display_unk20_handler(dev); 769 else 770 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40) 771 nv50_display_unk40_handler(dev); 772 else 773 break; 774 } 775 776 nv_wr32(dev, NV03_PMC_INTR_EN_0, 1); 777} 778 779static void 780nv50_display_error_handler(struct drm_device *dev) 781{ 782 uint32_t addr, data; 783 784 nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000); 785 addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR); 786 data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA); 787 788 NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x (0x%04x 0x%02x)\n", 789 0, addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf); 790 791 nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR, 0x90000000); 792} 793 794void 795nv50_display_irq_hotplug_bh(struct work_struct *work) 796{ 797 struct drm_nouveau_private *dev_priv = 798 container_of(work, struct drm_nouveau_private, hpd_work); 799 struct drm_device *dev = dev_priv->dev; 800 struct drm_connector *connector; 801 const uint32_t gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 }; 802 uint32_t unplug_mask, plug_mask, change_mask; 803 uint32_t hpd0, hpd1; 804 805 spin_lock_irq(&dev_priv->hpd_state.lock); 806 hpd0 = dev_priv->hpd_state.hpd0_bits; 807 dev_priv->hpd_state.hpd0_bits = 0; 808 hpd1 = dev_priv->hpd_state.hpd1_bits; 809 dev_priv->hpd_state.hpd1_bits = 0; 810 spin_unlock_irq(&dev_priv->hpd_state.lock); 811 812 hpd0 &= nv_rd32(dev, 0xe050); 813 if (dev_priv->chipset >= 0x90) 814 hpd1 &= nv_rd32(dev, 0xe070); 815 816 plug_mask = (hpd0 & 0x0000ffff) | (hpd1 << 16); 817 unplug_mask = (hpd0 >> 16) | (hpd1 & 0xffff0000); 818 change_mask = plug_mask | unplug_mask; 819 820 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 821 struct drm_encoder_helper_funcs *helper; 822 struct nouveau_connector *nv_connector = 823 nouveau_connector(connector); 824 struct nouveau_encoder *nv_encoder; 825 struct dcb_gpio_entry *gpio; 826 uint32_t reg; 827 bool plugged; 828 829 if (!nv_connector->dcb) 830 continue; 831 832 gpio = nouveau_bios_gpio_entry(dev, nv_connector->dcb->gpio_tag); 833 if (!gpio || !(change_mask & (1 << gpio->line))) 834 continue; 835 836 reg = nv_rd32(dev, gpio_reg[gpio->line >> 3]); 837 plugged = !!(reg & (4 << ((gpio->line & 7) << 2))); 838 NV_INFO(dev, "%splugged %s\n", plugged ? "" : "un", 839 drm_get_connector_name(connector)) ; 840 841 if (!connector->encoder || !connector->encoder->crtc || 842 !connector->encoder->crtc->enabled) 843 continue; 844 nv_encoder = nouveau_encoder(connector->encoder); 845 helper = connector->encoder->helper_private; 846 847 if (nv_encoder->dcb->type != OUTPUT_DP) 848 continue; 849 850 if (plugged) 851 helper->dpms(connector->encoder, DRM_MODE_DPMS_ON); 852 else 853 helper->dpms(connector->encoder, DRM_MODE_DPMS_OFF); 854 } 855 856 drm_helper_hpd_irq_event(dev); 857} 858 859void 860nv50_display_irq_handler(struct drm_device *dev) 861{ 862 struct drm_nouveau_private *dev_priv = dev->dev_private; 863 uint32_t delayed = 0; 864 865 if (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_HOTPLUG) { 866 uint32_t hpd0_bits, hpd1_bits = 0; 867 868 hpd0_bits = nv_rd32(dev, 0xe054); 869 nv_wr32(dev, 0xe054, hpd0_bits); 870 871 if (dev_priv->chipset >= 0x90) { 872 hpd1_bits = nv_rd32(dev, 0xe074); 873 nv_wr32(dev, 0xe074, hpd1_bits); 874 } 875 876 spin_lock(&dev_priv->hpd_state.lock); 877 dev_priv->hpd_state.hpd0_bits |= hpd0_bits; 878 dev_priv->hpd_state.hpd1_bits |= hpd1_bits; 879 spin_unlock(&dev_priv->hpd_state.lock); 880 881 queue_work(dev_priv->wq, &dev_priv->hpd_work); 882 } 883 884 while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) { 885 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0); 886 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1); 887 uint32_t clock; 888 889 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1); 890 891 if (!intr0 && !(intr1 & ~delayed)) 892 break; 893 894 if (intr0 & 0x00010000) { 895 nv50_display_error_handler(dev); 896 intr0 &= ~0x00010000; 897 } 898 899 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) { 900 nv50_display_vblank_handler(dev, intr1); 901 intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC; 902 } 903 904 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 | 905 NV50_PDISPLAY_INTR_1_CLK_UNK20 | 906 NV50_PDISPLAY_INTR_1_CLK_UNK40)); 907 if (clock) { 908 nv_wr32(dev, NV03_PMC_INTR_EN_0, 0); 909 if (!work_pending(&dev_priv->irq_work)) 910 queue_work(dev_priv->wq, &dev_priv->irq_work); 911 delayed |= clock; 912 intr1 &= ~clock; 913 } 914 915 if (intr0) { 916 NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0); 917 nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0); 918 } 919 920 if (intr1) { 921 NV_ERROR(dev, 922 "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1); 923 nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1); 924 } 925 } 926} 927 928