nv50_fence.c revision 4acfd707e28c820ba8ed8c12b497413a133d8c8f 
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24
25#include <nvif/os.h>
26#include <nvif/class.h>
27
28#include "nouveau_drm.h"
29#include "nouveau_dma.h"
30#include "nv10_fence.h"
31
32#include "nv50_display.h"
33
34static int
35nv50_fence_context_new(struct nouveau_channel *chan)
36{
37	struct drm_device *dev = chan->drm->dev;
38	struct nv10_fence_priv *priv = chan->drm->fence;
39	struct nv10_fence_chan *fctx;
40	struct ttm_mem_reg *mem = &priv->bo->bo.mem;
41	u32 start = mem->start * PAGE_SIZE;
42	u32 limit = start + mem->size - 1;
43	int ret, i;
44
45	fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
46	if (!fctx)
47		return -ENOMEM;
48
49	nouveau_fence_context_new(&fctx->base);
50	fctx->base.emit = nv10_fence_emit;
51	fctx->base.read = nv10_fence_read;
52	fctx->base.sync = nv17_fence_sync;
53
54	ret = nvif_object_init(chan->object, NULL, NvSema, NV_DMA_IN_MEMORY,
55			       &(struct nv_dma_v0) {
56					.target = NV_DMA_V0_TARGET_VRAM,
57					.access = NV_DMA_V0_ACCESS_RDWR,
58					.start = start,
59					.limit = limit,
60			       }, sizeof(struct nv_dma_v0),
61			       &fctx->sema);
62
63	/* dma objects for display sync channel semaphore blocks */
64	for (i = 0; !ret && i < dev->mode_config.num_crtc; i++) {
65		struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i);
66		u32 start = bo->bo.mem.start * PAGE_SIZE;
67		u32 limit = start + bo->bo.mem.size - 1;
68
69		ret = nvif_object_init(chan->object, NULL, NvEvoSema0 + i,
70				       NV_DMA_IN_MEMORY, &(struct nv_dma_v0) {
71						.target = NV_DMA_V0_TARGET_VRAM,
72						.access = NV_DMA_V0_ACCESS_RDWR,
73						.start = start,
74						.limit = limit,
75				       }, sizeof(struct nv_dma_v0),
76				       &fctx->head[i]);
77	}
78
79	if (ret)
80		nv10_fence_context_del(chan);
81	return ret;
82}
83
84int
85nv50_fence_create(struct nouveau_drm *drm)
86{
87	struct nv10_fence_priv *priv;
88	int ret = 0;
89
90	priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
91	if (!priv)
92		return -ENOMEM;
93
94	priv->base.dtor = nv10_fence_destroy;
95	priv->base.resume = nv17_fence_resume;
96	priv->base.context_new = nv50_fence_context_new;
97	priv->base.context_del = nv10_fence_context_del;
98	spin_lock_init(&priv->lock);
99
100	ret = nouveau_bo_new(drm->dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
101			     0, 0x0000, NULL, &priv->bo);
102	if (!ret) {
103		ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
104		if (!ret) {
105			ret = nouveau_bo_map(priv->bo);
106			if (ret)
107				nouveau_bo_unpin(priv->bo);
108		}
109		if (ret)
110			nouveau_bo_ref(NULL, &priv->bo);
111	}
112
113	if (ret) {
114		nv10_fence_destroy(drm);
115		return ret;
116	}
117
118	nouveau_bo_wr32(priv->bo, 0x000, 0x00000000);
119	return ret;
120}
121