nvc0_fence.c revision a34caf78f26bda63869471cb3f46f354f4658758 
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <core/object.h>
26#include <core/client.h>
27#include <core/class.h>
28
29#include <engine/fifo.h>
30
31#include "nouveau_drm.h"
32#include "nouveau_dma.h"
33#include "nouveau_fence.h"
34
35#include "nv50_display.h"
36
37static int
38nvc0_fence_emit(struct nouveau_fence *fence)
39{
40	struct nouveau_channel *chan = fence->channel;
41	struct nv84_fence_chan *fctx = chan->fence;
42	struct nouveau_fifo_chan *fifo = (void *)chan->object;
43	u64 addr = fctx->vma.offset + fifo->chid * 16;
44	int ret;
45
46	ret = RING_SPACE(chan, 6);
47	if (ret == 0) {
48		BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5);
49		OUT_RING  (chan, upper_32_bits(addr));
50		OUT_RING  (chan, lower_32_bits(addr));
51		OUT_RING  (chan, fence->sequence);
52		OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
53		OUT_RING  (chan, 0x00000000);
54		FIRE_RING (chan);
55	}
56
57	return ret;
58}
59
60static int
61nvc0_fence_sync(struct nouveau_fence *fence,
62		struct nouveau_channel *prev, struct nouveau_channel *chan)
63{
64	struct nv84_fence_chan *fctx = chan->fence;
65	struct nouveau_fifo_chan *fifo = (void *)prev->object;
66	u64 addr = fctx->vma.offset + fifo->chid * 16;
67	int ret;
68
69	ret = RING_SPACE(chan, 5);
70	if (ret == 0) {
71		BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
72		OUT_RING  (chan, upper_32_bits(addr));
73		OUT_RING  (chan, lower_32_bits(addr));
74		OUT_RING  (chan, fence->sequence);
75		OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL |
76				 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
77		FIRE_RING (chan);
78	}
79
80	return ret;
81}
82
83int
84nvc0_fence_create(struct nouveau_drm *drm)
85{
86	struct nouveau_fifo *pfifo = nouveau_fifo(drm->device);
87	struct nv84_fence_priv *priv;
88	int ret;
89
90	priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
91	if (!priv)
92		return -ENOMEM;
93
94	priv->base.dtor = nv84_fence_destroy;
95	priv->base.suspend = nv84_fence_suspend;
96	priv->base.resume = nv84_fence_resume;
97	priv->base.context_new = nv84_fence_context_new;
98	priv->base.context_del = nv84_fence_context_del;
99	priv->base.emit = nvc0_fence_emit;
100	priv->base.sync = nvc0_fence_sync;
101	priv->base.read = nv84_fence_read;
102
103	init_waitqueue_head(&priv->base.waiting);
104	priv->base.uevent = true;
105
106	ret = nouveau_bo_new(drm->dev, 16 * (pfifo->max + 1), 0,
107			     TTM_PL_FLAG_VRAM, 0, 0, NULL, &priv->bo);
108	if (ret == 0) {
109		ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
110		if (ret == 0) {
111			ret = nouveau_bo_map(priv->bo);
112			if (ret)
113				nouveau_bo_unpin(priv->bo);
114		}
115		if (ret)
116			nouveau_bo_ref(NULL, &priv->bo);
117	}
118
119	if (ret)
120		nv84_fence_destroy(drm);
121	return ret;
122}
123