12483b4ea982efe8a544697d3f9642932e9af4dc1Christian König/* 22483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Copyright 2013 Advanced Micro Devices, Inc. 32483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 42483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Permission is hereby granted, free of charge, to any person obtaining a 52483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * copy of this software and associated documentation files (the "Software"), 62483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * to deal in the Software without restriction, including without limitation 72483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * the rights to use, copy, modify, merge, publish, distribute, sublicense, 82483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * and/or sell copies of the Software, and to permit persons to whom the 92483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Software is furnished to do so, subject to the following conditions: 102483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 112483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * The above copyright notice and this permission notice shall be included in 122483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * all copies or substantial portions of the Software. 132483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 142483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 152483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 162483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 172483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 182483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 192483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 202483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * OTHER DEALINGS IN THE SOFTWARE. 212483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 222483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Authors: Alex Deucher 232483b4ea982efe8a544697d3f9642932e9af4dc1Christian König */ 242483b4ea982efe8a544697d3f9642932e9af4dc1Christian König#include <linux/firmware.h> 252483b4ea982efe8a544697d3f9642932e9af4dc1Christian König#include <drm/drmP.h> 262483b4ea982efe8a544697d3f9642932e9af4dc1Christian König#include "radeon.h" 27f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher#include "radeon_ucode.h" 282483b4ea982efe8a544697d3f9642932e9af4dc1Christian König#include "radeon_asic.h" 2974d360f66b99231ed7007eb197dd18cda72c961cChristian König#include "radeon_trace.h" 302483b4ea982efe8a544697d3f9642932e9af4dc1Christian König#include "cikd.h" 312483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 322483b4ea982efe8a544697d3f9642932e9af4dc1Christian König/* sdma */ 332483b4ea982efe8a544697d3f9642932e9af4dc1Christian König#define CIK_SDMA_UCODE_SIZE 1050 342483b4ea982efe8a544697d3f9642932e9af4dc1Christian König#define CIK_SDMA_UCODE_VERSION 64 352483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 362483b4ea982efe8a544697d3f9642932e9af4dc1Christian Königu32 cik_gpu_check_soft_reset(struct radeon_device *rdev); 372483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 382483b4ea982efe8a544697d3f9642932e9af4dc1Christian König/* 392483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * sDMA - System DMA 402483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Starting with CIK, the GPU has new asynchronous 412483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * DMA engines. These engines are used for compute 422483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * and gfx. There are two DMA engines (SDMA0, SDMA1) 432483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * and each one supports 1 ring buffer used for gfx 442483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * and 2 queues used for compute. 452483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 462483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * The programming model is very similar to the CP 472483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * (ring buffer, IBs, etc.), but sDMA has it's own 482483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * packet format that is different from the PM4 format 492483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * used by the CP. sDMA supports copying data, writing 502483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * embedded data, solid fills, and a number of other 512483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * things. It also has support for tiling/detiling of 522483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * buffers. 532483b4ea982efe8a544697d3f9642932e9af4dc1Christian König */ 542483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 552483b4ea982efe8a544697d3f9642932e9af4dc1Christian König/** 56ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher * cik_sdma_get_rptr - get the current read pointer 57ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher * 58ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher * @rdev: radeon_device pointer 59ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher * @ring: radeon ring pointer 60ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher * 61ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher * Get the current rptr from the hardware (CIK+). 62ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher */ 63ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucheruint32_t cik_sdma_get_rptr(struct radeon_device *rdev, 64ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher struct radeon_ring *ring) 65ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher{ 66ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher u32 rptr, reg; 67ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher 68ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher if (rdev->wb.enabled) { 69ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher rptr = rdev->wb.wb[ring->rptr_offs/4]; 70ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher } else { 71ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher if (ring->idx == R600_RING_TYPE_DMA_INDEX) 72ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET; 73ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher else 74ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET; 75ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher 76ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher rptr = RREG32(reg); 77ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher } 78ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher 79ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher return (rptr & 0x3fffc) >> 2; 80ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher} 81ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher 82ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher/** 83ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher * cik_sdma_get_wptr - get the current write pointer 84ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher * 85ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher * @rdev: radeon_device pointer 86ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher * @ring: radeon ring pointer 87ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher * 88ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher * Get the current wptr from the hardware (CIK+). 89ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher */ 90ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucheruint32_t cik_sdma_get_wptr(struct radeon_device *rdev, 91ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher struct radeon_ring *ring) 92ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher{ 93ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher u32 reg; 94ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher 95ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher if (ring->idx == R600_RING_TYPE_DMA_INDEX) 96ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; 97ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher else 98ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; 99ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher 100ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher return (RREG32(reg) & 0x3fffc) >> 2; 101ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher} 102ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher 103ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher/** 104ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher * cik_sdma_set_wptr - commit the write pointer 105ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher * 106ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher * @rdev: radeon_device pointer 107ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher * @ring: radeon ring pointer 108ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher * 109ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher * Write the wptr back to the hardware (CIK+). 110ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher */ 111ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deuchervoid cik_sdma_set_wptr(struct radeon_device *rdev, 112ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher struct radeon_ring *ring) 113ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher{ 114ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher u32 reg; 115ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher 116ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher if (ring->idx == R600_RING_TYPE_DMA_INDEX) 117ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; 118ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher else 119ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; 120ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher 121ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher WREG32(reg, (ring->wptr << 2) & 0x3fffc); 122f069dc1dbc1e17b04b2ec65f65d1c9e9af667ff5Michel Dänzer (void)RREG32(reg); 123ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher} 124ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher 125ea31bf697d27270188a93cd78cf9de4bc968aca3Alex Deucher/** 1262483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * cik_sdma_ring_ib_execute - Schedule an IB on the DMA engine 1272483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 1282483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @rdev: radeon_device pointer 1292483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @ib: IB object to schedule 1302483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 1312483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Schedule an IB in the DMA ring (CIK). 1322483b4ea982efe8a544697d3f9642932e9af4dc1Christian König */ 1332483b4ea982efe8a544697d3f9642932e9af4dc1Christian Königvoid cik_sdma_ring_ib_execute(struct radeon_device *rdev, 1342483b4ea982efe8a544697d3f9642932e9af4dc1Christian König struct radeon_ib *ib) 1352483b4ea982efe8a544697d3f9642932e9af4dc1Christian König{ 1362483b4ea982efe8a544697d3f9642932e9af4dc1Christian König struct radeon_ring *ring = &rdev->ring[ib->ring]; 1372483b4ea982efe8a544697d3f9642932e9af4dc1Christian König u32 extra_bits = (ib->vm ? ib->vm->id : 0) & 0xf; 1382483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 1392483b4ea982efe8a544697d3f9642932e9af4dc1Christian König if (rdev->wb.enabled) { 1402483b4ea982efe8a544697d3f9642932e9af4dc1Christian König u32 next_rptr = ring->wptr + 5; 1412483b4ea982efe8a544697d3f9642932e9af4dc1Christian König while ((next_rptr & 7) != 4) 1422483b4ea982efe8a544697d3f9642932e9af4dc1Christian König next_rptr++; 1432483b4ea982efe8a544697d3f9642932e9af4dc1Christian König next_rptr += 4; 1442483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); 1452483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 1465e167cdbf6ab51c7cc7c3c2efdc54ec1080834d3Christian König radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); 1472483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, 1); /* number of DWs to follow */ 1482483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, next_rptr); 1492483b4ea982efe8a544697d3f9642932e9af4dc1Christian König } 1502483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 1512483b4ea982efe8a544697d3f9642932e9af4dc1Christian König /* IB packet must end on a 8 DW boundary */ 1522483b4ea982efe8a544697d3f9642932e9af4dc1Christian König while ((ring->wptr & 7) != 4) 1532483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0)); 1542483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); 1552483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ 1565e167cdbf6ab51c7cc7c3c2efdc54ec1080834d3Christian König radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1572483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, ib->length_dw); 1582483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 1592483b4ea982efe8a544697d3f9642932e9af4dc1Christian König} 1602483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 1612483b4ea982efe8a544697d3f9642932e9af4dc1Christian König/** 162ca113f6baeb314a66463c35565b4f7955c484000Alex Deucher * cik_sdma_hdp_flush_ring_emit - emit an hdp flush on the DMA ring 163ca113f6baeb314a66463c35565b4f7955c484000Alex Deucher * 164ca113f6baeb314a66463c35565b4f7955c484000Alex Deucher * @rdev: radeon_device pointer 165ca113f6baeb314a66463c35565b4f7955c484000Alex Deucher * @ridx: radeon ring index 166ca113f6baeb314a66463c35565b4f7955c484000Alex Deucher * 167ca113f6baeb314a66463c35565b4f7955c484000Alex Deucher * Emit an hdp flush packet on the requested DMA ring. 168ca113f6baeb314a66463c35565b4f7955c484000Alex Deucher */ 169ca113f6baeb314a66463c35565b4f7955c484000Alex Deucherstatic void cik_sdma_hdp_flush_ring_emit(struct radeon_device *rdev, 170ca113f6baeb314a66463c35565b4f7955c484000Alex Deucher int ridx) 171ca113f6baeb314a66463c35565b4f7955c484000Alex Deucher{ 172ca113f6baeb314a66463c35565b4f7955c484000Alex Deucher struct radeon_ring *ring = &rdev->ring[ridx]; 173da9e07e6f53eaac4e838bc8c987d87c5769be724Alex Deucher u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) | 174da9e07e6f53eaac4e838bc8c987d87c5769be724Alex Deucher SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ 175da9e07e6f53eaac4e838bc8c987d87c5769be724Alex Deucher u32 ref_and_mask; 176ca113f6baeb314a66463c35565b4f7955c484000Alex Deucher 177da9e07e6f53eaac4e838bc8c987d87c5769be724Alex Deucher if (ridx == R600_RING_TYPE_DMA_INDEX) 178da9e07e6f53eaac4e838bc8c987d87c5769be724Alex Deucher ref_and_mask = SDMA0; 179da9e07e6f53eaac4e838bc8c987d87c5769be724Alex Deucher else 180da9e07e6f53eaac4e838bc8c987d87c5769be724Alex Deucher ref_and_mask = SDMA1; 181da9e07e6f53eaac4e838bc8c987d87c5769be724Alex Deucher 182da9e07e6f53eaac4e838bc8c987d87c5769be724Alex Deucher radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); 183da9e07e6f53eaac4e838bc8c987d87c5769be724Alex Deucher radeon_ring_write(ring, GPU_HDP_FLUSH_DONE); 184da9e07e6f53eaac4e838bc8c987d87c5769be724Alex Deucher radeon_ring_write(ring, GPU_HDP_FLUSH_REQ); 185da9e07e6f53eaac4e838bc8c987d87c5769be724Alex Deucher radeon_ring_write(ring, ref_and_mask); /* reference */ 186da9e07e6f53eaac4e838bc8c987d87c5769be724Alex Deucher radeon_ring_write(ring, ref_and_mask); /* mask */ 187da9e07e6f53eaac4e838bc8c987d87c5769be724Alex Deucher radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ 188ca113f6baeb314a66463c35565b4f7955c484000Alex Deucher} 189ca113f6baeb314a66463c35565b4f7955c484000Alex Deucher 190ca113f6baeb314a66463c35565b4f7955c484000Alex Deucher/** 1912483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * cik_sdma_fence_ring_emit - emit a fence on the DMA ring 1922483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 1932483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @rdev: radeon_device pointer 1942483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @fence: radeon fence object 1952483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 1962483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Add a DMA fence packet to the ring to write 1972483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * the fence seq number and DMA trap packet to generate 1982483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * an interrupt if needed (CIK). 1992483b4ea982efe8a544697d3f9642932e9af4dc1Christian König */ 2002483b4ea982efe8a544697d3f9642932e9af4dc1Christian Königvoid cik_sdma_fence_ring_emit(struct radeon_device *rdev, 2012483b4ea982efe8a544697d3f9642932e9af4dc1Christian König struct radeon_fence *fence) 2022483b4ea982efe8a544697d3f9642932e9af4dc1Christian König{ 2032483b4ea982efe8a544697d3f9642932e9af4dc1Christian König struct radeon_ring *ring = &rdev->ring[fence->ring]; 2042483b4ea982efe8a544697d3f9642932e9af4dc1Christian König u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 2052483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 2062483b4ea982efe8a544697d3f9642932e9af4dc1Christian König /* write the fence */ 2072483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); 2085e167cdbf6ab51c7cc7c3c2efdc54ec1080834d3Christian König radeon_ring_write(ring, lower_32_bits(addr)); 2095e167cdbf6ab51c7cc7c3c2efdc54ec1080834d3Christian König radeon_ring_write(ring, upper_32_bits(addr)); 2102483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, fence->seq); 2112483b4ea982efe8a544697d3f9642932e9af4dc1Christian König /* generate an interrupt */ 2122483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); 2132483b4ea982efe8a544697d3f9642932e9af4dc1Christian König /* flush HDP */ 214ca113f6baeb314a66463c35565b4f7955c484000Alex Deucher cik_sdma_hdp_flush_ring_emit(rdev, fence->ring); 2152483b4ea982efe8a544697d3f9642932e9af4dc1Christian König} 2162483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 2172483b4ea982efe8a544697d3f9642932e9af4dc1Christian König/** 2182483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * cik_sdma_semaphore_ring_emit - emit a semaphore on the dma ring 2192483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 2202483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @rdev: radeon_device pointer 2212483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @ring: radeon_ring structure holding ring information 2222483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @semaphore: radeon semaphore object 2232483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @emit_wait: wait or signal semaphore 2242483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 2252483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Add a DMA semaphore packet to the ring wait on or signal 2262483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * other rings (CIK). 2272483b4ea982efe8a544697d3f9642932e9af4dc1Christian König */ 2281654b817d8f5f1c27ebc98773fe0e517b0ba2f1eChristian Königbool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev, 2292483b4ea982efe8a544697d3f9642932e9af4dc1Christian König struct radeon_ring *ring, 2302483b4ea982efe8a544697d3f9642932e9af4dc1Christian König struct radeon_semaphore *semaphore, 2312483b4ea982efe8a544697d3f9642932e9af4dc1Christian König bool emit_wait) 2322483b4ea982efe8a544697d3f9642932e9af4dc1Christian König{ 2332483b4ea982efe8a544697d3f9642932e9af4dc1Christian König u64 addr = semaphore->gpu_addr; 2342483b4ea982efe8a544697d3f9642932e9af4dc1Christian König u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S; 2352483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 2362483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits)); 2372483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, addr & 0xfffffff8); 2385e167cdbf6ab51c7cc7c3c2efdc54ec1080834d3Christian König radeon_ring_write(ring, upper_32_bits(addr)); 2391654b817d8f5f1c27ebc98773fe0e517b0ba2f1eChristian König 2401654b817d8f5f1c27ebc98773fe0e517b0ba2f1eChristian König return true; 2412483b4ea982efe8a544697d3f9642932e9af4dc1Christian König} 2422483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 2432483b4ea982efe8a544697d3f9642932e9af4dc1Christian König/** 2442483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * cik_sdma_gfx_stop - stop the gfx async dma engines 2452483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 2462483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @rdev: radeon_device pointer 2472483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 2482483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Stop the gfx async dma ring buffers (CIK). 2492483b4ea982efe8a544697d3f9642932e9af4dc1Christian König */ 2502483b4ea982efe8a544697d3f9642932e9af4dc1Christian Königstatic void cik_sdma_gfx_stop(struct radeon_device *rdev) 2512483b4ea982efe8a544697d3f9642932e9af4dc1Christian König{ 2522483b4ea982efe8a544697d3f9642932e9af4dc1Christian König u32 rb_cntl, reg_offset; 2532483b4ea982efe8a544697d3f9642932e9af4dc1Christian König int i; 2542483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 25550efa51afddb50a6ab47ee15614fcf180130888cAlex Deucher if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) || 25650efa51afddb50a6ab47ee15614fcf180130888cAlex Deucher (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX)) 25750efa51afddb50a6ab47ee15614fcf180130888cAlex Deucher radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 2582483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 2592483b4ea982efe8a544697d3f9642932e9af4dc1Christian König for (i = 0; i < 2; i++) { 2602483b4ea982efe8a544697d3f9642932e9af4dc1Christian König if (i == 0) 2612483b4ea982efe8a544697d3f9642932e9af4dc1Christian König reg_offset = SDMA0_REGISTER_OFFSET; 2622483b4ea982efe8a544697d3f9642932e9af4dc1Christian König else 2632483b4ea982efe8a544697d3f9642932e9af4dc1Christian König reg_offset = SDMA1_REGISTER_OFFSET; 2642483b4ea982efe8a544697d3f9642932e9af4dc1Christian König rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset); 2652483b4ea982efe8a544697d3f9642932e9af4dc1Christian König rb_cntl &= ~SDMA_RB_ENABLE; 2662483b4ea982efe8a544697d3f9642932e9af4dc1Christian König WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); 2672483b4ea982efe8a544697d3f9642932e9af4dc1Christian König WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0); 2682483b4ea982efe8a544697d3f9642932e9af4dc1Christian König } 2697b1bbe883b3ed962ca2be4daf321f318f5091340Alex Deucher rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false; 2707b1bbe883b3ed962ca2be4daf321f318f5091340Alex Deucher rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false; 2712483b4ea982efe8a544697d3f9642932e9af4dc1Christian König} 2722483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 2732483b4ea982efe8a544697d3f9642932e9af4dc1Christian König/** 2742483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * cik_sdma_rlc_stop - stop the compute async dma engines 2752483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 2762483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @rdev: radeon_device pointer 2772483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 2782483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Stop the compute async dma queues (CIK). 2792483b4ea982efe8a544697d3f9642932e9af4dc1Christian König */ 2802483b4ea982efe8a544697d3f9642932e9af4dc1Christian Königstatic void cik_sdma_rlc_stop(struct radeon_device *rdev) 2812483b4ea982efe8a544697d3f9642932e9af4dc1Christian König{ 2822483b4ea982efe8a544697d3f9642932e9af4dc1Christian König /* XXX todo */ 2832483b4ea982efe8a544697d3f9642932e9af4dc1Christian König} 2842483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 2852483b4ea982efe8a544697d3f9642932e9af4dc1Christian König/** 2862483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * cik_sdma_enable - stop the async dma engines 2872483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 2882483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @rdev: radeon_device pointer 2892483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @enable: enable/disable the DMA MEs. 2902483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 2912483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Halt or unhalt the async dma engines (CIK). 2922483b4ea982efe8a544697d3f9642932e9af4dc1Christian König */ 2932483b4ea982efe8a544697d3f9642932e9af4dc1Christian Königvoid cik_sdma_enable(struct radeon_device *rdev, bool enable) 2942483b4ea982efe8a544697d3f9642932e9af4dc1Christian König{ 2952483b4ea982efe8a544697d3f9642932e9af4dc1Christian König u32 me_cntl, reg_offset; 2962483b4ea982efe8a544697d3f9642932e9af4dc1Christian König int i; 2972483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 29807ae78c9798b79bad3d3adf983c94ba23fde54d4Alex Deucher if (enable == false) { 29907ae78c9798b79bad3d3adf983c94ba23fde54d4Alex Deucher cik_sdma_gfx_stop(rdev); 30007ae78c9798b79bad3d3adf983c94ba23fde54d4Alex Deucher cik_sdma_rlc_stop(rdev); 30107ae78c9798b79bad3d3adf983c94ba23fde54d4Alex Deucher } 30207ae78c9798b79bad3d3adf983c94ba23fde54d4Alex Deucher 3032483b4ea982efe8a544697d3f9642932e9af4dc1Christian König for (i = 0; i < 2; i++) { 3042483b4ea982efe8a544697d3f9642932e9af4dc1Christian König if (i == 0) 3052483b4ea982efe8a544697d3f9642932e9af4dc1Christian König reg_offset = SDMA0_REGISTER_OFFSET; 3062483b4ea982efe8a544697d3f9642932e9af4dc1Christian König else 3072483b4ea982efe8a544697d3f9642932e9af4dc1Christian König reg_offset = SDMA1_REGISTER_OFFSET; 3082483b4ea982efe8a544697d3f9642932e9af4dc1Christian König me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset); 3092483b4ea982efe8a544697d3f9642932e9af4dc1Christian König if (enable) 3102483b4ea982efe8a544697d3f9642932e9af4dc1Christian König me_cntl &= ~SDMA_HALT; 3112483b4ea982efe8a544697d3f9642932e9af4dc1Christian König else 3122483b4ea982efe8a544697d3f9642932e9af4dc1Christian König me_cntl |= SDMA_HALT; 3132483b4ea982efe8a544697d3f9642932e9af4dc1Christian König WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl); 3142483b4ea982efe8a544697d3f9642932e9af4dc1Christian König } 3152483b4ea982efe8a544697d3f9642932e9af4dc1Christian König} 3162483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 3172483b4ea982efe8a544697d3f9642932e9af4dc1Christian König/** 3182483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * cik_sdma_gfx_resume - setup and start the async dma engines 3192483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 3202483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @rdev: radeon_device pointer 3212483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 3222483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Set up the gfx DMA ring buffers and enable them (CIK). 3232483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Returns 0 for success, error for failure. 3242483b4ea982efe8a544697d3f9642932e9af4dc1Christian König */ 3252483b4ea982efe8a544697d3f9642932e9af4dc1Christian Königstatic int cik_sdma_gfx_resume(struct radeon_device *rdev) 3262483b4ea982efe8a544697d3f9642932e9af4dc1Christian König{ 3272483b4ea982efe8a544697d3f9642932e9af4dc1Christian König struct radeon_ring *ring; 3282483b4ea982efe8a544697d3f9642932e9af4dc1Christian König u32 rb_cntl, ib_cntl; 3292483b4ea982efe8a544697d3f9642932e9af4dc1Christian König u32 rb_bufsz; 3302483b4ea982efe8a544697d3f9642932e9af4dc1Christian König u32 reg_offset, wb_offset; 3312483b4ea982efe8a544697d3f9642932e9af4dc1Christian König int i, r; 3322483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 3332483b4ea982efe8a544697d3f9642932e9af4dc1Christian König for (i = 0; i < 2; i++) { 3342483b4ea982efe8a544697d3f9642932e9af4dc1Christian König if (i == 0) { 3352483b4ea982efe8a544697d3f9642932e9af4dc1Christian König ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 3362483b4ea982efe8a544697d3f9642932e9af4dc1Christian König reg_offset = SDMA0_REGISTER_OFFSET; 3372483b4ea982efe8a544697d3f9642932e9af4dc1Christian König wb_offset = R600_WB_DMA_RPTR_OFFSET; 3382483b4ea982efe8a544697d3f9642932e9af4dc1Christian König } else { 3392483b4ea982efe8a544697d3f9642932e9af4dc1Christian König ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; 3402483b4ea982efe8a544697d3f9642932e9af4dc1Christian König reg_offset = SDMA1_REGISTER_OFFSET; 3412483b4ea982efe8a544697d3f9642932e9af4dc1Christian König wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET; 3422483b4ea982efe8a544697d3f9642932e9af4dc1Christian König } 3432483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 3442483b4ea982efe8a544697d3f9642932e9af4dc1Christian König WREG32(SDMA0_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0); 3452483b4ea982efe8a544697d3f9642932e9af4dc1Christian König WREG32(SDMA0_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0); 3462483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 3472483b4ea982efe8a544697d3f9642932e9af4dc1Christian König /* Set ring buffer size in dwords */ 3489c725e5bcdae59d5383d4aec33a34c822582dda5Dave Airlie rb_bufsz = order_base_2(ring->ring_size / 4); 3492483b4ea982efe8a544697d3f9642932e9af4dc1Christian König rb_cntl = rb_bufsz << 1; 3502483b4ea982efe8a544697d3f9642932e9af4dc1Christian König#ifdef __BIG_ENDIAN 3512483b4ea982efe8a544697d3f9642932e9af4dc1Christian König rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE; 3522483b4ea982efe8a544697d3f9642932e9af4dc1Christian König#endif 3532483b4ea982efe8a544697d3f9642932e9af4dc1Christian König WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); 3542483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 3552483b4ea982efe8a544697d3f9642932e9af4dc1Christian König /* Initialize the ring buffer's read and write pointers */ 3562483b4ea982efe8a544697d3f9642932e9af4dc1Christian König WREG32(SDMA0_GFX_RB_RPTR + reg_offset, 0); 3572483b4ea982efe8a544697d3f9642932e9af4dc1Christian König WREG32(SDMA0_GFX_RB_WPTR + reg_offset, 0); 3582483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 3592483b4ea982efe8a544697d3f9642932e9af4dc1Christian König /* set the wb address whether it's enabled or not */ 3602483b4ea982efe8a544697d3f9642932e9af4dc1Christian König WREG32(SDMA0_GFX_RB_RPTR_ADDR_HI + reg_offset, 3612483b4ea982efe8a544697d3f9642932e9af4dc1Christian König upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 3622483b4ea982efe8a544697d3f9642932e9af4dc1Christian König WREG32(SDMA0_GFX_RB_RPTR_ADDR_LO + reg_offset, 3632483b4ea982efe8a544697d3f9642932e9af4dc1Christian König ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); 3642483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 3652483b4ea982efe8a544697d3f9642932e9af4dc1Christian König if (rdev->wb.enabled) 3662483b4ea982efe8a544697d3f9642932e9af4dc1Christian König rb_cntl |= SDMA_RPTR_WRITEBACK_ENABLE; 3672483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 3682483b4ea982efe8a544697d3f9642932e9af4dc1Christian König WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8); 3692483b4ea982efe8a544697d3f9642932e9af4dc1Christian König WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40); 3702483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 3712483b4ea982efe8a544697d3f9642932e9af4dc1Christian König ring->wptr = 0; 3722483b4ea982efe8a544697d3f9642932e9af4dc1Christian König WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2); 3732483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 3742483b4ea982efe8a544697d3f9642932e9af4dc1Christian König /* enable DMA RB */ 3752483b4ea982efe8a544697d3f9642932e9af4dc1Christian König WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE); 3762483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 3772483b4ea982efe8a544697d3f9642932e9af4dc1Christian König ib_cntl = SDMA_IB_ENABLE; 3782483b4ea982efe8a544697d3f9642932e9af4dc1Christian König#ifdef __BIG_ENDIAN 3792483b4ea982efe8a544697d3f9642932e9af4dc1Christian König ib_cntl |= SDMA_IB_SWAP_ENABLE; 3802483b4ea982efe8a544697d3f9642932e9af4dc1Christian König#endif 3812483b4ea982efe8a544697d3f9642932e9af4dc1Christian König /* enable DMA IBs */ 3822483b4ea982efe8a544697d3f9642932e9af4dc1Christian König WREG32(SDMA0_GFX_IB_CNTL + reg_offset, ib_cntl); 3832483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 3842483b4ea982efe8a544697d3f9642932e9af4dc1Christian König ring->ready = true; 3852483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 3862483b4ea982efe8a544697d3f9642932e9af4dc1Christian König r = radeon_ring_test(rdev, ring->idx, ring); 3872483b4ea982efe8a544697d3f9642932e9af4dc1Christian König if (r) { 3882483b4ea982efe8a544697d3f9642932e9af4dc1Christian König ring->ready = false; 3892483b4ea982efe8a544697d3f9642932e9af4dc1Christian König return r; 3902483b4ea982efe8a544697d3f9642932e9af4dc1Christian König } 3912483b4ea982efe8a544697d3f9642932e9af4dc1Christian König } 3922483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 39350efa51afddb50a6ab47ee15614fcf180130888cAlex Deucher if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) || 39450efa51afddb50a6ab47ee15614fcf180130888cAlex Deucher (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX)) 39550efa51afddb50a6ab47ee15614fcf180130888cAlex Deucher radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 3962483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 3972483b4ea982efe8a544697d3f9642932e9af4dc1Christian König return 0; 3982483b4ea982efe8a544697d3f9642932e9af4dc1Christian König} 3992483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 4002483b4ea982efe8a544697d3f9642932e9af4dc1Christian König/** 4012483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * cik_sdma_rlc_resume - setup and start the async dma engines 4022483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 4032483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @rdev: radeon_device pointer 4042483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 4052483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Set up the compute DMA queues and enable them (CIK). 4062483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Returns 0 for success, error for failure. 4072483b4ea982efe8a544697d3f9642932e9af4dc1Christian König */ 4082483b4ea982efe8a544697d3f9642932e9af4dc1Christian Königstatic int cik_sdma_rlc_resume(struct radeon_device *rdev) 4092483b4ea982efe8a544697d3f9642932e9af4dc1Christian König{ 4102483b4ea982efe8a544697d3f9642932e9af4dc1Christian König /* XXX todo */ 4112483b4ea982efe8a544697d3f9642932e9af4dc1Christian König return 0; 4122483b4ea982efe8a544697d3f9642932e9af4dc1Christian König} 4132483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 4142483b4ea982efe8a544697d3f9642932e9af4dc1Christian König/** 4152483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * cik_sdma_load_microcode - load the sDMA ME ucode 4162483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 4172483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @rdev: radeon_device pointer 4182483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 4192483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Loads the sDMA0/1 ucode. 4202483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Returns 0 for success, -EINVAL if the ucode is not available. 4212483b4ea982efe8a544697d3f9642932e9af4dc1Christian König */ 4222483b4ea982efe8a544697d3f9642932e9af4dc1Christian Königstatic int cik_sdma_load_microcode(struct radeon_device *rdev) 4232483b4ea982efe8a544697d3f9642932e9af4dc1Christian König{ 4242483b4ea982efe8a544697d3f9642932e9af4dc1Christian König int i; 4252483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 4262483b4ea982efe8a544697d3f9642932e9af4dc1Christian König if (!rdev->sdma_fw) 4272483b4ea982efe8a544697d3f9642932e9af4dc1Christian König return -EINVAL; 4282483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 4292483b4ea982efe8a544697d3f9642932e9af4dc1Christian König /* halt the MEs */ 4302483b4ea982efe8a544697d3f9642932e9af4dc1Christian König cik_sdma_enable(rdev, false); 4312483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 432f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher if (rdev->new_fw) { 433f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher const struct sdma_firmware_header_v1_0 *hdr = 434f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher (const struct sdma_firmware_header_v1_0 *)rdev->sdma_fw->data; 435f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher const __le32 *fw_data; 436f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher u32 fw_size; 437f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher 438f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher radeon_ucode_print_sdma_hdr(&hdr->header); 439f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher 440f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher /* sdma0 */ 441f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher fw_data = (const __le32 *) 442f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher (rdev->sdma_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 443f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 444f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); 445f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher for (i = 0; i < fw_size; i++) 446f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, le32_to_cpup(fw_data++)); 447f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); 448f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher 449f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher /* sdma1 */ 450f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher fw_data = (const __le32 *) 451f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher (rdev->sdma_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 452f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 453f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); 454f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher for (i = 0; i < fw_size; i++) 455f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, le32_to_cpup(fw_data++)); 456f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); 457f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher } else { 458f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher const __be32 *fw_data; 459f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher 460f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher /* sdma0 */ 461f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher fw_data = (const __be32 *)rdev->sdma_fw->data; 462f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); 463f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++) 464f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, be32_to_cpup(fw_data++)); 465f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); 466f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher 467f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher /* sdma1 */ 468f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher fw_data = (const __be32 *)rdev->sdma_fw->data; 469f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); 470f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++) 471f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, be32_to_cpup(fw_data++)); 472f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); 473f2c6b0f452c3804496f55655fda28c2809e1a58bAlex Deucher } 4742483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 4752483b4ea982efe8a544697d3f9642932e9af4dc1Christian König WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); 4762483b4ea982efe8a544697d3f9642932e9af4dc1Christian König WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); 4772483b4ea982efe8a544697d3f9642932e9af4dc1Christian König return 0; 4782483b4ea982efe8a544697d3f9642932e9af4dc1Christian König} 4792483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 4802483b4ea982efe8a544697d3f9642932e9af4dc1Christian König/** 4812483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * cik_sdma_resume - setup and start the async dma engines 4822483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 4832483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @rdev: radeon_device pointer 4842483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 4852483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Set up the DMA engines and enable them (CIK). 4862483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Returns 0 for success, error for failure. 4872483b4ea982efe8a544697d3f9642932e9af4dc1Christian König */ 4882483b4ea982efe8a544697d3f9642932e9af4dc1Christian Königint cik_sdma_resume(struct radeon_device *rdev) 4892483b4ea982efe8a544697d3f9642932e9af4dc1Christian König{ 4902483b4ea982efe8a544697d3f9642932e9af4dc1Christian König int r; 4912483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 4922483b4ea982efe8a544697d3f9642932e9af4dc1Christian König r = cik_sdma_load_microcode(rdev); 4932483b4ea982efe8a544697d3f9642932e9af4dc1Christian König if (r) 4942483b4ea982efe8a544697d3f9642932e9af4dc1Christian König return r; 4952483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 4962483b4ea982efe8a544697d3f9642932e9af4dc1Christian König /* unhalt the MEs */ 4972483b4ea982efe8a544697d3f9642932e9af4dc1Christian König cik_sdma_enable(rdev, true); 4982483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 4992483b4ea982efe8a544697d3f9642932e9af4dc1Christian König /* start the gfx rings and rlc compute queues */ 5002483b4ea982efe8a544697d3f9642932e9af4dc1Christian König r = cik_sdma_gfx_resume(rdev); 5012483b4ea982efe8a544697d3f9642932e9af4dc1Christian König if (r) 5022483b4ea982efe8a544697d3f9642932e9af4dc1Christian König return r; 5032483b4ea982efe8a544697d3f9642932e9af4dc1Christian König r = cik_sdma_rlc_resume(rdev); 5042483b4ea982efe8a544697d3f9642932e9af4dc1Christian König if (r) 5052483b4ea982efe8a544697d3f9642932e9af4dc1Christian König return r; 5062483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 5072483b4ea982efe8a544697d3f9642932e9af4dc1Christian König return 0; 5082483b4ea982efe8a544697d3f9642932e9af4dc1Christian König} 5092483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 5102483b4ea982efe8a544697d3f9642932e9af4dc1Christian König/** 5112483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * cik_sdma_fini - tear down the async dma engines 5122483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 5132483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @rdev: radeon_device pointer 5142483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 5152483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Stop the async dma engines and free the rings (CIK). 5162483b4ea982efe8a544697d3f9642932e9af4dc1Christian König */ 5172483b4ea982efe8a544697d3f9642932e9af4dc1Christian Königvoid cik_sdma_fini(struct radeon_device *rdev) 5182483b4ea982efe8a544697d3f9642932e9af4dc1Christian König{ 5192483b4ea982efe8a544697d3f9642932e9af4dc1Christian König /* halt the MEs */ 5202483b4ea982efe8a544697d3f9642932e9af4dc1Christian König cik_sdma_enable(rdev, false); 5212483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]); 5222483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]); 5232483b4ea982efe8a544697d3f9642932e9af4dc1Christian König /* XXX - compute dma queue tear down */ 5242483b4ea982efe8a544697d3f9642932e9af4dc1Christian König} 5252483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 5262483b4ea982efe8a544697d3f9642932e9af4dc1Christian König/** 5272483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * cik_copy_dma - copy pages using the DMA engine 5282483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 5292483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @rdev: radeon_device pointer 5302483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @src_offset: src GPU address 5312483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @dst_offset: dst GPU address 5322483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @num_gpu_pages: number of GPU pages to xfer 53357d20a43c9b30663bdbacde8294a902edef35a84Christian König * @resv: reservation object to sync to 5342483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 5352483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Copy GPU paging using the DMA engine (CIK). 5362483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Used by the radeon ttm implementation to move pages if 5372483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * registered as the asic copy callback. 5382483b4ea982efe8a544697d3f9642932e9af4dc1Christian König */ 53957d20a43c9b30663bdbacde8294a902edef35a84Christian Königstruct radeon_fence *cik_copy_dma(struct radeon_device *rdev, 54057d20a43c9b30663bdbacde8294a902edef35a84Christian König uint64_t src_offset, uint64_t dst_offset, 54157d20a43c9b30663bdbacde8294a902edef35a84Christian König unsigned num_gpu_pages, 54257d20a43c9b30663bdbacde8294a902edef35a84Christian König struct reservation_object *resv) 5432483b4ea982efe8a544697d3f9642932e9af4dc1Christian König{ 5442483b4ea982efe8a544697d3f9642932e9af4dc1Christian König struct radeon_semaphore *sem = NULL; 54557d20a43c9b30663bdbacde8294a902edef35a84Christian König struct radeon_fence *fence; 5462483b4ea982efe8a544697d3f9642932e9af4dc1Christian König int ring_index = rdev->asic->copy.dma_ring_index; 5472483b4ea982efe8a544697d3f9642932e9af4dc1Christian König struct radeon_ring *ring = &rdev->ring[ring_index]; 5482483b4ea982efe8a544697d3f9642932e9af4dc1Christian König u32 size_in_bytes, cur_size_in_bytes; 5492483b4ea982efe8a544697d3f9642932e9af4dc1Christian König int i, num_loops; 5502483b4ea982efe8a544697d3f9642932e9af4dc1Christian König int r = 0; 5512483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 5522483b4ea982efe8a544697d3f9642932e9af4dc1Christian König r = radeon_semaphore_create(rdev, &sem); 5532483b4ea982efe8a544697d3f9642932e9af4dc1Christian König if (r) { 5542483b4ea982efe8a544697d3f9642932e9af4dc1Christian König DRM_ERROR("radeon: moving bo (%d).\n", r); 55557d20a43c9b30663bdbacde8294a902edef35a84Christian König return ERR_PTR(r); 5562483b4ea982efe8a544697d3f9642932e9af4dc1Christian König } 5572483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 5582483b4ea982efe8a544697d3f9642932e9af4dc1Christian König size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); 5592483b4ea982efe8a544697d3f9642932e9af4dc1Christian König num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff); 5602483b4ea982efe8a544697d3f9642932e9af4dc1Christian König r = radeon_ring_lock(rdev, ring, num_loops * 7 + 14); 5612483b4ea982efe8a544697d3f9642932e9af4dc1Christian König if (r) { 5622483b4ea982efe8a544697d3f9642932e9af4dc1Christian König DRM_ERROR("radeon: moving bo (%d).\n", r); 5632483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_semaphore_free(rdev, &sem, NULL); 56457d20a43c9b30663bdbacde8294a902edef35a84Christian König return ERR_PTR(r); 5652483b4ea982efe8a544697d3f9642932e9af4dc1Christian König } 5662483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 567392a250bd080e296f97ccc7e91b051a6b5da0ff1Maarten Lankhorst radeon_semaphore_sync_resv(rdev, sem, resv, false); 5681654b817d8f5f1c27ebc98773fe0e517b0ba2f1eChristian König radeon_semaphore_sync_rings(rdev, sem, ring->idx); 5692483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 5702483b4ea982efe8a544697d3f9642932e9af4dc1Christian König for (i = 0; i < num_loops; i++) { 5712483b4ea982efe8a544697d3f9642932e9af4dc1Christian König cur_size_in_bytes = size_in_bytes; 5722483b4ea982efe8a544697d3f9642932e9af4dc1Christian König if (cur_size_in_bytes > 0x1fffff) 5732483b4ea982efe8a544697d3f9642932e9af4dc1Christian König cur_size_in_bytes = 0x1fffff; 5742483b4ea982efe8a544697d3f9642932e9af4dc1Christian König size_in_bytes -= cur_size_in_bytes; 5752483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0)); 5762483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, cur_size_in_bytes); 5772483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, 0); /* src/dst endian swap */ 5785e167cdbf6ab51c7cc7c3c2efdc54ec1080834d3Christian König radeon_ring_write(ring, lower_32_bits(src_offset)); 5795e167cdbf6ab51c7cc7c3c2efdc54ec1080834d3Christian König radeon_ring_write(ring, upper_32_bits(src_offset)); 5805e167cdbf6ab51c7cc7c3c2efdc54ec1080834d3Christian König radeon_ring_write(ring, lower_32_bits(dst_offset)); 5815e167cdbf6ab51c7cc7c3c2efdc54ec1080834d3Christian König radeon_ring_write(ring, upper_32_bits(dst_offset)); 5822483b4ea982efe8a544697d3f9642932e9af4dc1Christian König src_offset += cur_size_in_bytes; 5832483b4ea982efe8a544697d3f9642932e9af4dc1Christian König dst_offset += cur_size_in_bytes; 5842483b4ea982efe8a544697d3f9642932e9af4dc1Christian König } 5852483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 58657d20a43c9b30663bdbacde8294a902edef35a84Christian König r = radeon_fence_emit(rdev, &fence, ring->idx); 5872483b4ea982efe8a544697d3f9642932e9af4dc1Christian König if (r) { 5882483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_unlock_undo(rdev, ring); 589aa4c8b36e5fcf70ba5ec7d175da19dac4a33c51aMaarten Lankhorst radeon_semaphore_free(rdev, &sem, NULL); 59057d20a43c9b30663bdbacde8294a902edef35a84Christian König return ERR_PTR(r); 5912483b4ea982efe8a544697d3f9642932e9af4dc1Christian König } 5922483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 5931538a9e0e04f6a5b323cd3d65e9320512978fcecMichel Dänzer radeon_ring_unlock_commit(rdev, ring, false); 59457d20a43c9b30663bdbacde8294a902edef35a84Christian König radeon_semaphore_free(rdev, &sem, fence); 5952483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 59657d20a43c9b30663bdbacde8294a902edef35a84Christian König return fence; 5972483b4ea982efe8a544697d3f9642932e9af4dc1Christian König} 5982483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 5992483b4ea982efe8a544697d3f9642932e9af4dc1Christian König/** 6002483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * cik_sdma_ring_test - simple async dma engine test 6012483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 6022483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @rdev: radeon_device pointer 6032483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @ring: radeon_ring structure holding ring information 6042483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 6052483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Test the DMA engine by writing using it to write an 6062483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * value to memory. (CIK). 6072483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Returns 0 for success, error for failure. 6082483b4ea982efe8a544697d3f9642932e9af4dc1Christian König */ 6092483b4ea982efe8a544697d3f9642932e9af4dc1Christian Königint cik_sdma_ring_test(struct radeon_device *rdev, 6102483b4ea982efe8a544697d3f9642932e9af4dc1Christian König struct radeon_ring *ring) 6112483b4ea982efe8a544697d3f9642932e9af4dc1Christian König{ 6122483b4ea982efe8a544697d3f9642932e9af4dc1Christian König unsigned i; 6132483b4ea982efe8a544697d3f9642932e9af4dc1Christian König int r; 614adfed2b0587289013f8143c54913ddfd44ac1fd3Alex Deucher unsigned index; 6152483b4ea982efe8a544697d3f9642932e9af4dc1Christian König u32 tmp; 616adfed2b0587289013f8143c54913ddfd44ac1fd3Alex Deucher u64 gpu_addr; 6172483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 618adfed2b0587289013f8143c54913ddfd44ac1fd3Alex Deucher if (ring->idx == R600_RING_TYPE_DMA_INDEX) 619adfed2b0587289013f8143c54913ddfd44ac1fd3Alex Deucher index = R600_WB_DMA_RING_TEST_OFFSET; 620adfed2b0587289013f8143c54913ddfd44ac1fd3Alex Deucher else 621adfed2b0587289013f8143c54913ddfd44ac1fd3Alex Deucher index = CAYMAN_WB_DMA1_RING_TEST_OFFSET; 622adfed2b0587289013f8143c54913ddfd44ac1fd3Alex Deucher 623adfed2b0587289013f8143c54913ddfd44ac1fd3Alex Deucher gpu_addr = rdev->wb.gpu_addr + index; 6242483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 6252483b4ea982efe8a544697d3f9642932e9af4dc1Christian König tmp = 0xCAFEDEAD; 626adfed2b0587289013f8143c54913ddfd44ac1fd3Alex Deucher rdev->wb.wb[index/4] = cpu_to_le32(tmp); 6272483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 6287e95cfb0b797678cd3493ca0322ef2675547a0bcAlex Deucher r = radeon_ring_lock(rdev, ring, 5); 6292483b4ea982efe8a544697d3f9642932e9af4dc1Christian König if (r) { 6302483b4ea982efe8a544697d3f9642932e9af4dc1Christian König DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r); 6312483b4ea982efe8a544697d3f9642932e9af4dc1Christian König return r; 6322483b4ea982efe8a544697d3f9642932e9af4dc1Christian König } 6332483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); 634adfed2b0587289013f8143c54913ddfd44ac1fd3Alex Deucher radeon_ring_write(ring, lower_32_bits(gpu_addr)); 635adfed2b0587289013f8143c54913ddfd44ac1fd3Alex Deucher radeon_ring_write(ring, upper_32_bits(gpu_addr)); 6362483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, 1); /* number of DWs to follow */ 6372483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, 0xDEADBEEF); 6381538a9e0e04f6a5b323cd3d65e9320512978fcecMichel Dänzer radeon_ring_unlock_commit(rdev, ring, false); 6392483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 6402483b4ea982efe8a544697d3f9642932e9af4dc1Christian König for (i = 0; i < rdev->usec_timeout; i++) { 641adfed2b0587289013f8143c54913ddfd44ac1fd3Alex Deucher tmp = le32_to_cpu(rdev->wb.wb[index/4]); 6422483b4ea982efe8a544697d3f9642932e9af4dc1Christian König if (tmp == 0xDEADBEEF) 6432483b4ea982efe8a544697d3f9642932e9af4dc1Christian König break; 6442483b4ea982efe8a544697d3f9642932e9af4dc1Christian König DRM_UDELAY(1); 6452483b4ea982efe8a544697d3f9642932e9af4dc1Christian König } 6462483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 6472483b4ea982efe8a544697d3f9642932e9af4dc1Christian König if (i < rdev->usec_timeout) { 6482483b4ea982efe8a544697d3f9642932e9af4dc1Christian König DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 6492483b4ea982efe8a544697d3f9642932e9af4dc1Christian König } else { 6502483b4ea982efe8a544697d3f9642932e9af4dc1Christian König DRM_ERROR("radeon: ring %d test failed (0x%08X)\n", 6512483b4ea982efe8a544697d3f9642932e9af4dc1Christian König ring->idx, tmp); 6522483b4ea982efe8a544697d3f9642932e9af4dc1Christian König r = -EINVAL; 6532483b4ea982efe8a544697d3f9642932e9af4dc1Christian König } 6542483b4ea982efe8a544697d3f9642932e9af4dc1Christian König return r; 6552483b4ea982efe8a544697d3f9642932e9af4dc1Christian König} 6562483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 6572483b4ea982efe8a544697d3f9642932e9af4dc1Christian König/** 6582483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * cik_sdma_ib_test - test an IB on the DMA engine 6592483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 6602483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @rdev: radeon_device pointer 6612483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @ring: radeon_ring structure holding ring information 6622483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 6632483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Test a simple IB in the DMA ring (CIK). 6642483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Returns 0 on success, error on failure. 6652483b4ea982efe8a544697d3f9642932e9af4dc1Christian König */ 6662483b4ea982efe8a544697d3f9642932e9af4dc1Christian Königint cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 6672483b4ea982efe8a544697d3f9642932e9af4dc1Christian König{ 6682483b4ea982efe8a544697d3f9642932e9af4dc1Christian König struct radeon_ib ib; 6692483b4ea982efe8a544697d3f9642932e9af4dc1Christian König unsigned i; 6700b021c5802fbe5addf6f89f5030f684adf04f7b7Alex Deucher unsigned index; 6712483b4ea982efe8a544697d3f9642932e9af4dc1Christian König int r; 6722483b4ea982efe8a544697d3f9642932e9af4dc1Christian König u32 tmp = 0; 6730b021c5802fbe5addf6f89f5030f684adf04f7b7Alex Deucher u64 gpu_addr; 6742483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 6750b021c5802fbe5addf6f89f5030f684adf04f7b7Alex Deucher if (ring->idx == R600_RING_TYPE_DMA_INDEX) 6760b021c5802fbe5addf6f89f5030f684adf04f7b7Alex Deucher index = R600_WB_DMA_RING_TEST_OFFSET; 6770b021c5802fbe5addf6f89f5030f684adf04f7b7Alex Deucher else 6780b021c5802fbe5addf6f89f5030f684adf04f7b7Alex Deucher index = CAYMAN_WB_DMA1_RING_TEST_OFFSET; 6790b021c5802fbe5addf6f89f5030f684adf04f7b7Alex Deucher 6800b021c5802fbe5addf6f89f5030f684adf04f7b7Alex Deucher gpu_addr = rdev->wb.gpu_addr + index; 6812483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 6822483b4ea982efe8a544697d3f9642932e9af4dc1Christian König tmp = 0xCAFEDEAD; 6830b021c5802fbe5addf6f89f5030f684adf04f7b7Alex Deucher rdev->wb.wb[index/4] = cpu_to_le32(tmp); 6842483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 6852483b4ea982efe8a544697d3f9642932e9af4dc1Christian König r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 6862483b4ea982efe8a544697d3f9642932e9af4dc1Christian König if (r) { 6872483b4ea982efe8a544697d3f9642932e9af4dc1Christian König DRM_ERROR("radeon: failed to get ib (%d).\n", r); 6882483b4ea982efe8a544697d3f9642932e9af4dc1Christian König return r; 6892483b4ea982efe8a544697d3f9642932e9af4dc1Christian König } 6902483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 6912483b4ea982efe8a544697d3f9642932e9af4dc1Christian König ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 6920b021c5802fbe5addf6f89f5030f684adf04f7b7Alex Deucher ib.ptr[1] = lower_32_bits(gpu_addr); 6930b021c5802fbe5addf6f89f5030f684adf04f7b7Alex Deucher ib.ptr[2] = upper_32_bits(gpu_addr); 6942483b4ea982efe8a544697d3f9642932e9af4dc1Christian König ib.ptr[3] = 1; 6952483b4ea982efe8a544697d3f9642932e9af4dc1Christian König ib.ptr[4] = 0xDEADBEEF; 6962483b4ea982efe8a544697d3f9642932e9af4dc1Christian König ib.length_dw = 5; 6972483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 6981538a9e0e04f6a5b323cd3d65e9320512978fcecMichel Dänzer r = radeon_ib_schedule(rdev, &ib, NULL, false); 6992483b4ea982efe8a544697d3f9642932e9af4dc1Christian König if (r) { 7002483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ib_free(rdev, &ib); 7012483b4ea982efe8a544697d3f9642932e9af4dc1Christian König DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 7022483b4ea982efe8a544697d3f9642932e9af4dc1Christian König return r; 7032483b4ea982efe8a544697d3f9642932e9af4dc1Christian König } 7042483b4ea982efe8a544697d3f9642932e9af4dc1Christian König r = radeon_fence_wait(ib.fence, false); 7052483b4ea982efe8a544697d3f9642932e9af4dc1Christian König if (r) { 7062483b4ea982efe8a544697d3f9642932e9af4dc1Christian König DRM_ERROR("radeon: fence wait failed (%d).\n", r); 7072483b4ea982efe8a544697d3f9642932e9af4dc1Christian König return r; 7082483b4ea982efe8a544697d3f9642932e9af4dc1Christian König } 7092483b4ea982efe8a544697d3f9642932e9af4dc1Christian König for (i = 0; i < rdev->usec_timeout; i++) { 7100b021c5802fbe5addf6f89f5030f684adf04f7b7Alex Deucher tmp = le32_to_cpu(rdev->wb.wb[index/4]); 7112483b4ea982efe8a544697d3f9642932e9af4dc1Christian König if (tmp == 0xDEADBEEF) 7122483b4ea982efe8a544697d3f9642932e9af4dc1Christian König break; 7132483b4ea982efe8a544697d3f9642932e9af4dc1Christian König DRM_UDELAY(1); 7142483b4ea982efe8a544697d3f9642932e9af4dc1Christian König } 7152483b4ea982efe8a544697d3f9642932e9af4dc1Christian König if (i < rdev->usec_timeout) { 7162483b4ea982efe8a544697d3f9642932e9af4dc1Christian König DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 7172483b4ea982efe8a544697d3f9642932e9af4dc1Christian König } else { 7182483b4ea982efe8a544697d3f9642932e9af4dc1Christian König DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp); 7192483b4ea982efe8a544697d3f9642932e9af4dc1Christian König r = -EINVAL; 7202483b4ea982efe8a544697d3f9642932e9af4dc1Christian König } 7212483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ib_free(rdev, &ib); 7222483b4ea982efe8a544697d3f9642932e9af4dc1Christian König return r; 7232483b4ea982efe8a544697d3f9642932e9af4dc1Christian König} 7242483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 7252483b4ea982efe8a544697d3f9642932e9af4dc1Christian König/** 7262483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * cik_sdma_is_lockup - Check if the DMA engine is locked up 7272483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 7282483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @rdev: radeon_device pointer 7292483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @ring: radeon_ring structure holding ring information 7302483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 7312483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Check if the async DMA engine is locked up (CIK). 7322483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Returns true if the engine appears to be locked up, false if not. 7332483b4ea982efe8a544697d3f9642932e9af4dc1Christian König */ 7342483b4ea982efe8a544697d3f9642932e9af4dc1Christian Königbool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 7352483b4ea982efe8a544697d3f9642932e9af4dc1Christian König{ 7362483b4ea982efe8a544697d3f9642932e9af4dc1Christian König u32 reset_mask = cik_gpu_check_soft_reset(rdev); 7372483b4ea982efe8a544697d3f9642932e9af4dc1Christian König u32 mask; 7382483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 7392483b4ea982efe8a544697d3f9642932e9af4dc1Christian König if (ring->idx == R600_RING_TYPE_DMA_INDEX) 7402483b4ea982efe8a544697d3f9642932e9af4dc1Christian König mask = RADEON_RESET_DMA; 7412483b4ea982efe8a544697d3f9642932e9af4dc1Christian König else 7422483b4ea982efe8a544697d3f9642932e9af4dc1Christian König mask = RADEON_RESET_DMA1; 7432483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 7442483b4ea982efe8a544697d3f9642932e9af4dc1Christian König if (!(reset_mask & mask)) { 745ff212f25feb44a915ce9c0144faef7fae27a6e61Christian König radeon_ring_lockup_update(rdev, ring); 7462483b4ea982efe8a544697d3f9642932e9af4dc1Christian König return false; 7472483b4ea982efe8a544697d3f9642932e9af4dc1Christian König } 7482483b4ea982efe8a544697d3f9642932e9af4dc1Christian König return radeon_ring_test_lockup(rdev, ring); 7492483b4ea982efe8a544697d3f9642932e9af4dc1Christian König} 7502483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 7512483b4ea982efe8a544697d3f9642932e9af4dc1Christian König/** 75203f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART 75303f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König * 75403f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König * @rdev: radeon_device pointer 75503f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König * @ib: indirect buffer to fill with commands 75603f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König * @pe: addr of the page entry 75703f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König * @src: src addr to copy from 75803f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König * @count: number of page entries to update 75903f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König * 76003f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König * Update PTEs by copying them from the GART using sDMA (CIK). 76103f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König */ 76203f62abd112d5150b6ce8957fa85d4f6e85e357fChristian Königvoid cik_sdma_vm_copy_pages(struct radeon_device *rdev, 76303f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König struct radeon_ib *ib, 76403f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König uint64_t pe, uint64_t src, 76503f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König unsigned count) 76603f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König{ 76703f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König while (count) { 76803f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König unsigned bytes = count * 8; 76903f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König if (bytes > 0x1FFFF8) 77003f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König bytes = 0x1FFFF8; 77103f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König 77203f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, 77303f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 77403f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König ib->ptr[ib->length_dw++] = bytes; 77503f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 77603f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König ib->ptr[ib->length_dw++] = lower_32_bits(src); 77703f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König ib->ptr[ib->length_dw++] = upper_32_bits(src); 77803f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König ib->ptr[ib->length_dw++] = lower_32_bits(pe); 77903f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König ib->ptr[ib->length_dw++] = upper_32_bits(pe); 78003f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König 78103f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König pe += bytes; 78203f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König src += bytes; 78303f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König count -= bytes / 8; 78403f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König } 78503f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König} 78603f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König 78703f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König/** 78803f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König * cik_sdma_vm_write_pages - update PTEs by writing them manually 7892483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 7902483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @rdev: radeon_device pointer 7912483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @ib: indirect buffer to fill with commands 7922483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @pe: addr of the page entry 7932483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @addr: dst addr to write into pe 7942483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @count: number of page entries to update 7952483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @incr: increase next addr by incr bytes 7962483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @flags: access flags 7972483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 79803f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König * Update PTEs by writing them manually using sDMA (CIK). 7992483b4ea982efe8a544697d3f9642932e9af4dc1Christian König */ 80003f62abd112d5150b6ce8957fa85d4f6e85e357fChristian Königvoid cik_sdma_vm_write_pages(struct radeon_device *rdev, 80103f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König struct radeon_ib *ib, 80203f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König uint64_t pe, 80303f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König uint64_t addr, unsigned count, 80403f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König uint32_t incr, uint32_t flags) 8052483b4ea982efe8a544697d3f9642932e9af4dc1Christian König{ 8062483b4ea982efe8a544697d3f9642932e9af4dc1Christian König uint64_t value; 8072483b4ea982efe8a544697d3f9642932e9af4dc1Christian König unsigned ndw; 8082483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 80903f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König while (count) { 81003f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König ndw = count * 2; 81103f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König if (ndw > 0xFFFFE) 81203f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König ndw = 0xFFFFE; 81303f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König 81403f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König /* for non-physically contiguous pages (system) */ 81503f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE, 81603f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 81703f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König ib->ptr[ib->length_dw++] = pe; 81803f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König ib->ptr[ib->length_dw++] = upper_32_bits(pe); 81903f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König ib->ptr[ib->length_dw++] = ndw; 82003f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König for (; ndw > 0; ndw -= 2, --count, pe += 8) { 82103f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König if (flags & R600_PTE_SYSTEM) { 82224c164393dd2fa1c1fb51d5fec2f50bd6b7c037bChristian König value = radeon_vm_map_gart(rdev, addr); 82324c164393dd2fa1c1fb51d5fec2f50bd6b7c037bChristian König value &= 0xFFFFFFFFFFFFF000ULL; 82403f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König } else if (flags & R600_PTE_VALID) { 8252483b4ea982efe8a544697d3f9642932e9af4dc1Christian König value = addr; 82603f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König } else { 8272483b4ea982efe8a544697d3f9642932e9af4dc1Christian König value = 0; 82803f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König } 82903f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König addr += incr; 83003f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König value |= flags; 83103f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König ib->ptr[ib->length_dw++] = value; 8322483b4ea982efe8a544697d3f9642932e9af4dc1Christian König ib->ptr[ib->length_dw++] = upper_32_bits(value); 8332483b4ea982efe8a544697d3f9642932e9af4dc1Christian König } 8342483b4ea982efe8a544697d3f9642932e9af4dc1Christian König } 83503f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König} 83603f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König 83703f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König/** 83803f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König * cik_sdma_vm_set_pages - update the page tables using sDMA 83903f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König * 84003f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König * @rdev: radeon_device pointer 84103f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König * @ib: indirect buffer to fill with commands 84203f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König * @pe: addr of the page entry 84303f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König * @addr: dst addr to write into pe 84403f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König * @count: number of page entries to update 84503f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König * @incr: increase next addr by incr bytes 84603f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König * @flags: access flags 84703f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König * 84803f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König * Update the page tables using sDMA (CIK). 84903f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König */ 85003f62abd112d5150b6ce8957fa85d4f6e85e357fChristian Königvoid cik_sdma_vm_set_pages(struct radeon_device *rdev, 85103f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König struct radeon_ib *ib, 85203f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König uint64_t pe, 85303f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König uint64_t addr, unsigned count, 85403f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König uint32_t incr, uint32_t flags) 85503f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König{ 85603f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König uint64_t value; 85703f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König unsigned ndw; 85803f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König 85903f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König while (count) { 86003f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König ndw = count; 86103f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König if (ndw > 0x7FFFF) 86203f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König ndw = 0x7FFFF; 86303f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König 86403f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König if (flags & R600_PTE_VALID) 86503f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König value = addr; 86603f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König else 86703f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König value = 0; 86803f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König 86903f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König /* for physically contiguous pages (vram) */ 87003f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0); 87103f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König ib->ptr[ib->length_dw++] = pe; /* dst addr */ 87203f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König ib->ptr[ib->length_dw++] = upper_32_bits(pe); 87303f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König ib->ptr[ib->length_dw++] = flags; /* mask */ 87403f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König ib->ptr[ib->length_dw++] = 0; 87503f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König ib->ptr[ib->length_dw++] = value; /* value */ 87603f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König ib->ptr[ib->length_dw++] = upper_32_bits(value); 87703f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König ib->ptr[ib->length_dw++] = incr; /* increment size */ 87803f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König ib->ptr[ib->length_dw++] = 0; 87903f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König ib->ptr[ib->length_dw++] = ndw; /* number of entries */ 88003f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König 88103f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König pe += ndw * 8; 88203f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König addr += ndw * incr; 88303f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König count -= ndw; 88403f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König } 88503f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König} 88603f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König 88703f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König/** 88803f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König * cik_sdma_vm_pad_ib - pad the IB to the required number of dw 88903f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König * 89003f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König * @ib: indirect buffer to fill with padding 89103f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König * 89203f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König */ 89303f62abd112d5150b6ce8957fa85d4f6e85e357fChristian Königvoid cik_sdma_vm_pad_ib(struct radeon_ib *ib) 89403f62abd112d5150b6ce8957fa85d4f6e85e357fChristian König{ 8952483b4ea982efe8a544697d3f9642932e9af4dc1Christian König while (ib->length_dw & 0x7) 8962483b4ea982efe8a544697d3f9642932e9af4dc1Christian König ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0); 8972483b4ea982efe8a544697d3f9642932e9af4dc1Christian König} 8982483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 8992483b4ea982efe8a544697d3f9642932e9af4dc1Christian König/** 9002483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * cik_dma_vm_flush - cik vm flush using sDMA 9012483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 9022483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * @rdev: radeon_device pointer 9032483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * 9042483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * Update the page table base and flush the VM TLB 9052483b4ea982efe8a544697d3f9642932e9af4dc1Christian König * using sDMA (CIK). 9062483b4ea982efe8a544697d3f9642932e9af4dc1Christian König */ 9072483b4ea982efe8a544697d3f9642932e9af4dc1Christian Königvoid cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) 9082483b4ea982efe8a544697d3f9642932e9af4dc1Christian König{ 9092483b4ea982efe8a544697d3f9642932e9af4dc1Christian König struct radeon_ring *ring = &rdev->ring[ridx]; 9102483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 9112483b4ea982efe8a544697d3f9642932e9af4dc1Christian König if (vm == NULL) 9122483b4ea982efe8a544697d3f9642932e9af4dc1Christian König return; 9132483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 9142483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 9152483b4ea982efe8a544697d3f9642932e9af4dc1Christian König if (vm->id < 8) { 9162483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2); 9172483b4ea982efe8a544697d3f9642932e9af4dc1Christian König } else { 9182483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2); 9192483b4ea982efe8a544697d3f9642932e9af4dc1Christian König } 9202483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, vm->pd_gpu_addr >> 12); 9212483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 9222483b4ea982efe8a544697d3f9642932e9af4dc1Christian König /* update SH_MEM_* regs */ 9232483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 9242483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); 9252483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, VMID(vm->id)); 9262483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 9272483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 9282483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, SH_MEM_BASES >> 2); 9292483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, 0); 9302483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 9312483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 9322483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, SH_MEM_CONFIG >> 2); 9332483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, 0); 9342483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 9352483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 9362483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, SH_MEM_APE1_BASE >> 2); 9372483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, 1); 9382483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 9392483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 9402483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, SH_MEM_APE1_LIMIT >> 2); 9412483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, 0); 9422483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 9432483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 9442483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); 9452483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, VMID(0)); 9462483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 9472483b4ea982efe8a544697d3f9642932e9af4dc1Christian König /* flush HDP */ 948ca113f6baeb314a66463c35565b4f7955c484000Alex Deucher cik_sdma_hdp_flush_ring_emit(rdev, ridx); 9492483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 9502483b4ea982efe8a544697d3f9642932e9af4dc1Christian König /* flush TLB */ 9512483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 9522483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); 9532483b4ea982efe8a544697d3f9642932e9af4dc1Christian König radeon_ring_write(ring, 1 << vm->id); 9542483b4ea982efe8a544697d3f9642932e9af4dc1Christian König} 9552483b4ea982efe8a544697d3f9642932e9af4dc1Christian König 956