1dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher/* 2dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher * Copyright 2011 Advanced Micro Devices, Inc. 3dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher * 4dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher * copy of this software and associated documentation files (the "Software"), 6dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher * to deal in the Software without restriction, including without limitation 7dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher * Software is furnished to do so, subject to the following conditions: 10dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher * 11dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher * The above copyright notice and this permission notice shall be included in 12dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher * all copies or substantial portions of the Software. 13dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher * 14dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher * 22dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher */ 23dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher#ifndef __CYPRESS_DPM_H__ 24dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher#define __CYPRESS_DPM_H__ 25dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher 26dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher#include "rv770_dpm.h" 27dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher#include "evergreen_smc.h" 28dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher 29dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucherstruct evergreen_mc_reg_entry { 30dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher u32 mclk_max; 31dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher u32 mc_data[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; 32dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher}; 33dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher 34dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucherstruct evergreen_mc_reg_table { 35dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher u8 last; 36dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher u8 num_entries; 37dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher u16 valid_flag; 38dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher struct evergreen_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; 39dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher SMC_Evergreen_MCRegisterAddress mc_reg_address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; 40dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher}; 41dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher 42dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucherstruct evergreen_ulv_param { 43dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher bool supported; 44dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher struct rv7xx_pl *pl; 45dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher}; 46dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher 47dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucherstruct evergreen_arb_registers { 48dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher u32 mc_arb_dram_timing; 49dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher u32 mc_arb_dram_timing2; 50dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher u32 mc_arb_rfsh_rate; 51dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher u32 mc_arb_burst_time; 52dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher}; 53dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher 54f85392bcf94c5ae8bf55852827dcfa46f86502dcAlex Deucherstruct at { 55f85392bcf94c5ae8bf55852827dcfa46f86502dcAlex Deucher u32 rlp; 56f85392bcf94c5ae8bf55852827dcfa46f86502dcAlex Deucher u32 rmp; 57f85392bcf94c5ae8bf55852827dcfa46f86502dcAlex Deucher u32 lhp; 58f85392bcf94c5ae8bf55852827dcfa46f86502dcAlex Deucher u32 lmp; 59f85392bcf94c5ae8bf55852827dcfa46f86502dcAlex Deucher}; 60f85392bcf94c5ae8bf55852827dcfa46f86502dcAlex Deucher 61dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucherstruct evergreen_power_info { 62dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher /* must be first! */ 63dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher struct rv7xx_power_info rv7xx; 64dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher /* flags */ 65dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher bool vddci_control; 66dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher bool dynamic_ac_timing; 67dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher bool abm; 68dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher bool mcls; 69dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher bool light_sleep; 70dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher bool memory_transition; 71dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher bool pcie_performance_request; 72dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher bool pcie_performance_request_registered; 73dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher bool sclk_deep_sleep; 74dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher bool dll_default_on; 75dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher bool ls_clock_gating; 76f85392bcf94c5ae8bf55852827dcfa46f86502dcAlex Deucher bool smu_uvd_hs; 77f85392bcf94c5ae8bf55852827dcfa46f86502dcAlex Deucher bool uvd_enabled; 78dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher /* stored values */ 79dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher u16 acpi_vddci; 80dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher u8 mvdd_high_index; 81dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher u8 mvdd_low_index; 82dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher u32 mclk_edc_wr_enable_threshold; 83dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher struct evergreen_mc_reg_table mc_reg_table; 84dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher struct atom_voltage_table vddc_voltage_table; 85dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher struct atom_voltage_table vddci_voltage_table; 86dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher struct evergreen_arb_registers bootup_arb_registers; 87dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher struct evergreen_ulv_param ulv; 88f85392bcf94c5ae8bf55852827dcfa46f86502dcAlex Deucher struct at ats[2]; 89dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher /* smc offsets */ 90dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher u16 mc_reg_table_start; 91e8a9539fa098623ae3af1e077b49794917ea073dAlex Deucher struct radeon_ps current_rps; 92e8a9539fa098623ae3af1e077b49794917ea073dAlex Deucher struct rv7xx_ps current_ps; 93e8a9539fa098623ae3af1e077b49794917ea073dAlex Deucher struct radeon_ps requested_rps; 94e8a9539fa098623ae3af1e077b49794917ea073dAlex Deucher struct rv7xx_ps requested_ps; 95dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher}; 96dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher 97dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher#define CYPRESS_HASI_DFLT 400000 98dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher#define CYPRESS_MGCGTTLOCAL0_DFLT 0x00000000 99dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher#define CYPRESS_MGCGTTLOCAL1_DFLT 0x00000000 100dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher#define CYPRESS_MGCGTTLOCAL2_DFLT 0x00000000 101dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher#define CYPRESS_MGCGTTLOCAL3_DFLT 0x00000000 102dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher#define CYPRESS_MGCGCGTSSMCTRL_DFLT 0x81944bc0 103dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher#define REDWOOD_MGCGCGTSSMCTRL_DFLT 0x6e944040 104dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher#define CEDAR_MGCGCGTSSMCTRL_DFLT 0x46944040 105dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher#define CYPRESS_VRC_DFLT 0xC00033 106dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher 107dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher#define PCIE_PERF_REQ_REMOVE_REGISTRY 0 108dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher#define PCIE_PERF_REQ_FORCE_LOWPOWER 1 109dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher#define PCIE_PERF_REQ_PECI_GEN1 2 110dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher#define PCIE_PERF_REQ_PECI_GEN2 3 111dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher#define PCIE_PERF_REQ_PECI_GEN3 4 112dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher 113dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucherint cypress_convert_power_level_to_smc(struct radeon_device *rdev, 114dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher struct rv7xx_pl *pl, 115dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher RV770_SMC_HW_PERFORMANCE_LEVEL *level, 116dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher u8 watermark_level); 117dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucherint cypress_populate_smc_acpi_state(struct radeon_device *rdev, 118dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher RV770_SMC_STATETABLE *table); 119dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucherint cypress_populate_smc_voltage_tables(struct radeon_device *rdev, 120dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher RV770_SMC_STATETABLE *table); 121dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucherint cypress_populate_smc_initial_state(struct radeon_device *rdev, 122dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher struct radeon_ps *radeon_initial_state, 123dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher RV770_SMC_STATETABLE *table); 124dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucheru32 cypress_calculate_burst_time(struct radeon_device *rdev, 125dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher u32 engine_clock, u32 memory_clock); 126dbc341602444d7c0cdd1a75d7057a4a16c96fb3dAlex Deuchervoid cypress_notify_link_speed_change_before_state_change(struct radeon_device *rdev, 127dbc341602444d7c0cdd1a75d7057a4a16c96fb3dAlex Deucher struct radeon_ps *radeon_new_state, 128dbc341602444d7c0cdd1a75d7057a4a16c96fb3dAlex Deucher struct radeon_ps *radeon_current_state); 129dbc341602444d7c0cdd1a75d7057a4a16c96fb3dAlex Deucherint cypress_upload_sw_state(struct radeon_device *rdev, 130dbc341602444d7c0cdd1a75d7057a4a16c96fb3dAlex Deucher struct radeon_ps *radeon_new_state); 131dbc341602444d7c0cdd1a75d7057a4a16c96fb3dAlex Deucherint cypress_upload_mc_reg_table(struct radeon_device *rdev, 132dbc341602444d7c0cdd1a75d7057a4a16c96fb3dAlex Deucher struct radeon_ps *radeon_new_state); 133dbc341602444d7c0cdd1a75d7057a4a16c96fb3dAlex Deuchervoid cypress_program_memory_timing_parameters(struct radeon_device *rdev, 134dbc341602444d7c0cdd1a75d7057a4a16c96fb3dAlex Deucher struct radeon_ps *radeon_new_state); 135dbc341602444d7c0cdd1a75d7057a4a16c96fb3dAlex Deuchervoid cypress_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 136dbc341602444d7c0cdd1a75d7057a4a16c96fb3dAlex Deucher struct radeon_ps *radeon_new_state, 137dbc341602444d7c0cdd1a75d7057a4a16c96fb3dAlex Deucher struct radeon_ps *radeon_current_state); 138dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucherint cypress_construct_voltage_tables(struct radeon_device *rdev); 139dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucherint cypress_get_mvdd_configuration(struct radeon_device *rdev); 140dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deuchervoid cypress_enable_spread_spectrum(struct radeon_device *rdev, 141dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher bool enable); 142dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deuchervoid cypress_enable_display_gap(struct radeon_device *rdev); 143dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucherint cypress_get_table_locations(struct radeon_device *rdev); 144dbc341602444d7c0cdd1a75d7057a4a16c96fb3dAlex Deucherint cypress_populate_mc_reg_table(struct radeon_device *rdev, 145dbc341602444d7c0cdd1a75d7057a4a16c96fb3dAlex Deucher struct radeon_ps *radeon_boot_state); 146dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deuchervoid cypress_program_response_times(struct radeon_device *rdev); 147dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucherint cypress_notify_smc_display_change(struct radeon_device *rdev, 148dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher bool has_display); 149dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deuchervoid cypress_enable_sclk_control(struct radeon_device *rdev, 150dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher bool enable); 151dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deuchervoid cypress_enable_mclk_control(struct radeon_device *rdev, 152dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher bool enable); 153dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deuchervoid cypress_start_dpm(struct radeon_device *rdev); 154dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deuchervoid cypress_advertise_gen2_capability(struct radeon_device *rdev); 15569e0b57a91adca2e3eb56ed4db39ab90f3ae1043Alex Deucheru32 cypress_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf); 15669e0b57a91adca2e3eb56ed4db39ab90f3ae1043Alex Deucheru8 cypress_get_mclk_frequency_ratio(struct radeon_device *rdev, 15769e0b57a91adca2e3eb56ed4db39ab90f3ae1043Alex Deucher u32 memory_clock, bool strobe_mode); 15869e0b57a91adca2e3eb56ed4db39ab90f3ae1043Alex Deucheru8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk); 159dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher 160dc50ba7f9a6d9a920409892c7f30bce266067345Alex Deucher#endif 161