r600_cp.c revision 6546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06
1c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher/* 2c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Copyright 2008-2009 Advanced Micro Devices, Inc. 3c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Copyright 2008 Red Hat Inc. 4c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * 5c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 6c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * copy of this software and associated documentation files (the "Software"), 7c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * to deal in the Software without restriction, including without limitation 8c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * and/or sell copies of the Software, and to permit persons to whom the 10c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Software is furnished to do so, subject to the following conditions: 11c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * 12c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * The above copyright notice and this permission notice (including the next 13c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * paragraph) shall be included in all copies or substantial portions of the 14c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Software. 15c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * 16c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * DEALINGS IN THE SOFTWARE. 23c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * 24c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Authors: 25c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Dave Airlie <airlied@redhat.com> 26c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Alex Deucher <alexander.deucher@amd.com> 27c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 28c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 29c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#include "drmP.h" 30c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#include "drm.h" 31c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#include "radeon_drm.h" 32c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#include "radeon_drv.h" 33c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 34c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#include "r600_microcode.h" 35c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 36c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ 37c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher# define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1)) 38c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 39c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R600_PTE_VALID (1 << 0) 40c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R600_PTE_SYSTEM (1 << 1) 41c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R600_PTE_SNOOPED (1 << 2) 42c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R600_PTE_READABLE (1 << 5) 43c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R600_PTE_WRITEABLE (1 << 6) 44c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 45c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher/* MAX values used for gfx init */ 46c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_SH_GPRS 256 47c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_TEMP_GPRS 16 48c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_SH_THREADS 256 49c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_SH_STACK_ENTRIES 4096 50c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_BACKENDS 8 51c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_BACKENDS_MASK 0xff 52c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_SIMDS 8 53c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_SIMDS_MASK 0xff 54c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_PIPES 8 55c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_PIPES_MASK 0xff 56c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 57c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_SH_GPRS 256 58c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_TEMP_GPRS 16 59c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_SH_THREADS 256 60c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_SH_STACK_ENTRIES 4096 61c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_BACKENDS 8 62c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_BACKENDS_MASK 0xff 63c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_SIMDS 16 64c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_SIMDS_MASK 0xffff 65c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_PIPES 8 66c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_PIPES_MASK 0xff 67c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 68c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries) 69c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 70c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i; 71c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 72c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 73c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 74c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < dev_priv->usec_timeout; i++) { 75c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int slots; 76c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 77c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher slots = (RADEON_READ(R600_GRBM_STATUS) 78c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher & R700_CMDFIFO_AVAIL_MASK); 79c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 80c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher slots = (RADEON_READ(R600_GRBM_STATUS) 81c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher & R600_CMDFIFO_AVAIL_MASK); 82c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (slots >= entries) 83c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return 0; 84c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(1); 85c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 86c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n", 87c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_STATUS), 88c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_STATUS2)); 89c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 90c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EBUSY; 91c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 92c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 93c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv) 94c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 95c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i, ret; 96c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 97c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 98c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 99c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 100c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ret = r600_do_wait_for_fifo(dev_priv, 8); 101c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 102c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ret = r600_do_wait_for_fifo(dev_priv, 16); 103c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (ret) 104c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return ret; 105c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < dev_priv->usec_timeout; i++) { 106c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE)) 107c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return 0; 108c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(1); 109c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 110c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n", 111c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_STATUS), 112c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_STATUS2)); 113c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 114c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EBUSY; 115c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 116c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 117c1556f71513f2e660fb2bbdc29344361b1ebff35Alex Deuchervoid r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info) 118c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 119c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_sg_mem *entry = dev->sg; 120c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int max_pages; 121c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int pages; 122c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i; 123c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 12408932156cc2d4f8807dc5ca5c3d6ccd85080610aAlex Deucher if (!entry) 12508932156cc2d4f8807dc5ca5c3d6ccd85080610aAlex Deucher return; 12608932156cc2d4f8807dc5ca5c3d6ccd85080610aAlex Deucher 127c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (gart_info->bus_addr) { 128c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher max_pages = (gart_info->table_size / sizeof(u32)); 129c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher pages = (entry->pages <= max_pages) 130c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ? entry->pages : max_pages; 131c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 132c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < pages; i++) { 133c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!entry->busaddr[i]) 134c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 135a763d7dc0adb1159c1a52d43e566409da9fa59f0Dave Airlie pci_unmap_page(dev->pdev, entry->busaddr[i], 136a763d7dc0adb1159c1a52d43e566409da9fa59f0Dave Airlie PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 137c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 138c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) 139c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gart_info->bus_addr = 0; 140c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 141c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 142c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 143c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher/* R600 has page table setup */ 144c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherint r600_page_table_init(struct drm_device *dev) 145c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 146c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 147c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info; 148eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie struct drm_local_map *map = &gart_info->mapping; 149c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_sg_mem *entry = dev->sg; 150c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int ret = 0; 151c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i, j; 152eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie int pages; 153eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie u64 page_base; 154c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dma_addr_t entry_addr; 155eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie int max_ati_pages, max_real_pages, gart_idx; 156c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 157c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* okay page table is available - lets rock */ 158eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie max_ati_pages = (gart_info->table_size / sizeof(u64)); 159eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); 160c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 161eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie pages = (entry->pages <= max_real_pages) ? 162eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie entry->pages : max_real_pages; 163c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 164eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie memset_io((void __iomem *)map->handle, 0, max_ati_pages * sizeof(u64)); 165c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 166eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie gart_idx = 0; 167c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < pages; i++) { 168a763d7dc0adb1159c1a52d43e566409da9fa59f0Dave Airlie entry->busaddr[i] = pci_map_page(dev->pdev, 169a763d7dc0adb1159c1a52d43e566409da9fa59f0Dave Airlie entry->pagelist[i], 0, 170a763d7dc0adb1159c1a52d43e566409da9fa59f0Dave Airlie PAGE_SIZE, 171a763d7dc0adb1159c1a52d43e566409da9fa59f0Dave Airlie PCI_DMA_BIDIRECTIONAL); 172c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (entry->busaddr[i] == 0) { 173c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("unable to map PCIGART pages!\n"); 174c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_page_table_cleanup(dev, gart_info); 175c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ret = -EINVAL; 176c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher goto done; 177c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 178c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher entry_addr = entry->busaddr[i]; 179c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) { 180c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK; 181c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; 182c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE; 183c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 184eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie DRM_WRITE64(map, gart_idx * sizeof(u64), page_base); 185eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie 186eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie gart_idx++; 187c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 188c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((i % 128) == 0) 189c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("page entry %d: 0x%016llx\n", 190c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher i, (unsigned long long)page_base); 191c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher entry_addr += ATI_PCIGART_PAGE_SIZE; 192c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 193c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 194c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherdone: 195c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return ret; 196c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 197c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 198c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r600_vm_flush_gart_range(struct drm_device *dev) 199c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 200c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 201c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 resp, countdown = 1000; 202c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12); 203c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 204c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2); 205c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 206c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher do { 207c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE); 208c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher countdown--; 209c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(1); 210c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } while (((resp & 0xf0) == 0) && countdown); 211c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 212c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 213c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r600_vm_init(struct drm_device *dev) 214c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 215c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 216c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* initialise the VM to use the page table we constructed up there */ 217c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 vm_c0, i; 218c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 mc_rd_a; 219c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 vm_l2_cntl, vm_l2_cntl3; 220c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* okay set up the PCIE aperture type thingo */ 221c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); 222c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 223c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 224c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 225c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* setup MC RD a */ 226c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS | 227c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) | 228c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY; 229c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 230c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a); 231c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a); 232c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 233c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a); 234c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a); 235c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 236c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a); 237c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a); 238c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 239c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a); 240c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a); 241c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 242c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING); 243c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/); 244c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 245c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a); 246c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a); 247c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 248c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE); 249c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a); 250c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 251c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W; 252c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7); 253c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl); 254c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 255c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_L2_CNTL2, 0); 256c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) | 257c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VM_L2_CNTL3_BANK_SELECT_1(1) | 258c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2)); 259c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3); 260c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 261c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT; 262c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 263c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0); 264c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 265c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_c0 &= ~R600_VM_ENABLE_CONTEXT; 266c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 267c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* disable all other contexts */ 268c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 1; i < 8; i++) 269c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0); 270c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 271c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); 272c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); 273c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 274c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 275c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_vm_flush_gart_range(dev); 276c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 277c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 278c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher/* load r600 microcode */ 279c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r600_cp_load_microcode(drm_radeon_private_t *dev_priv) 280c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 281c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i; 282c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 283c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cp_stop(dev_priv); 284c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 285c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 286c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_RB_NO_UPDATE | 287c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_RB_BLKSZ(15) | 288c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_RB_BUFSZ(3)); 289c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 290c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 291c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_SOFT_RESET); 292c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(15000); 293c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 294c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 295c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 296c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 297c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600)) { 298c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading R600 CP Microcode\n"); 299c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < PM4_UCODE_SIZE; i++) { 300c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 301c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_cp_microcode[i][0]); 302c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 303c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_cp_microcode[i][1]); 304c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 305c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_cp_microcode[i][2]); 306c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 307c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 308c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 309c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading R600 PFP Microcode\n"); 310c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < PFP_UCODE_SIZE; i++) 311c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_DATA, R600_pfp_microcode[i]); 312c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610)) { 313c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV610 CP Microcode\n"); 314c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < PM4_UCODE_SIZE; i++) { 315c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 316c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV610_cp_microcode[i][0]); 317c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 318c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV610_cp_microcode[i][1]); 319c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 320c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV610_cp_microcode[i][2]); 321c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 322c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 323c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 324c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV610 PFP Microcode\n"); 325c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < PFP_UCODE_SIZE; i++) 326c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV610_pfp_microcode[i]); 327c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) { 328c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV630 CP Microcode\n"); 329c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < PM4_UCODE_SIZE; i++) { 330c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 331c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV630_cp_microcode[i][0]); 332c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 333c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV630_cp_microcode[i][1]); 334c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 335c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV630_cp_microcode[i][2]); 336c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 337c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 338c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 339c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV630 PFP Microcode\n"); 340c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < PFP_UCODE_SIZE; i++) 341c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV630_pfp_microcode[i]); 342c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620)) { 343c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV620 CP Microcode\n"); 344c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < PM4_UCODE_SIZE; i++) { 345c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 346c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV620_cp_microcode[i][0]); 347c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 348c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV620_cp_microcode[i][1]); 349c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 350c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV620_cp_microcode[i][2]); 351c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 352c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 353c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 354c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV620 PFP Microcode\n"); 355c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < PFP_UCODE_SIZE; i++) 356c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV620_pfp_microcode[i]); 357c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) { 358c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV635 CP Microcode\n"); 359c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < PM4_UCODE_SIZE; i++) { 360c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 361c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV635_cp_microcode[i][0]); 362c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 363c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV635_cp_microcode[i][1]); 364c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 365c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV635_cp_microcode[i][2]); 366c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 367c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 368c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 369c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV635 PFP Microcode\n"); 370c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < PFP_UCODE_SIZE; i++) 371c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV635_pfp_microcode[i]); 372c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)) { 373c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV670 CP Microcode\n"); 374c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < PM4_UCODE_SIZE; i++) { 375c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 376c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV670_cp_microcode[i][0]); 377c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 378c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV670_cp_microcode[i][1]); 379c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 380c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV670_cp_microcode[i][2]); 381c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 382c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 383c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 384c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV670 PFP Microcode\n"); 385c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < PFP_UCODE_SIZE; i++) 386c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV670_pfp_microcode[i]); 387c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) { 388c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RS780 CP Microcode\n"); 389c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < PM4_UCODE_SIZE; i++) { 390c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 391c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV670_cp_microcode[i][0]); 392c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 393c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV670_cp_microcode[i][1]); 394c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 395c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV670_cp_microcode[i][2]); 396c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 397c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 398c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 399c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RS780 PFP Microcode\n"); 400c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < PFP_UCODE_SIZE; i++) 401c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV670_pfp_microcode[i]); 402c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 403c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 404c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 405c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); 406c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 407c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 408c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 409c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r700_vm_init(struct drm_device *dev) 410c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 411c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 412c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* initialise the VM to use the page table we constructed up there */ 413c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 vm_c0, i; 414c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 mc_vm_md_l1; 415c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 vm_l2_cntl, vm_l2_cntl3; 416c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* okay set up the PCIE aperture type thingo */ 417c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); 418c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 419c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 420c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 421c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher mc_vm_md_l1 = R700_ENABLE_L1_TLB | 422c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_ENABLE_L1_FRAGMENT_PROCESSING | 423c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SYSTEM_ACCESS_MODE_IN_SYS | 424c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 425c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_EFFECTIVE_L1_TLB_SIZE(5) | 426c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_EFFECTIVE_L1_QUEUE_SIZE(5); 427c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 428c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1); 429c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1); 430c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1); 431c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1); 432c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1); 433c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1); 434c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1); 435c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 436c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W; 437c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7); 438c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl); 439c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 440c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_L2_CNTL2, 0); 441c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2); 442c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3); 443c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 444c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT; 445c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 446c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0); 447c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 448c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_c0 &= ~R600_VM_ENABLE_CONTEXT; 449c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 450c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* disable all other contexts */ 451c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 1; i < 8; i++) 452c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0); 453c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 454c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); 455c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); 456c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 457c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 458c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_vm_flush_gart_range(dev); 459c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 460c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 461c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher/* load r600 microcode */ 462c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r700_cp_load_microcode(drm_radeon_private_t *dev_priv) 463c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 464c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i; 465c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 466c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cp_stop(dev_priv); 467c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 468c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 469c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_RB_NO_UPDATE | 470c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (15 << 8) | 471c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (3 << 0)); 472c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 473c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 474c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_SOFT_RESET); 475c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(15000); 476c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 477c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 478c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 479c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)) { 480c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 481c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV770 PFP Microcode\n"); 482c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < R700_PFP_UCODE_SIZE; i++) 483c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV770_pfp_microcode[i]); 484c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 485c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 486c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 487c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV770 CP Microcode\n"); 488c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < R700_PM4_UCODE_SIZE; i++) 489c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, RV770_cp_microcode[i]); 490c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 491c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 492c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV730)) { 493c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 494c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV730 PFP Microcode\n"); 495c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < R700_PFP_UCODE_SIZE; i++) 496c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV730_pfp_microcode[i]); 497c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 498c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 499c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 500c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV730 CP Microcode\n"); 501c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < R700_PM4_UCODE_SIZE; i++) 502c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, RV730_cp_microcode[i]); 503c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 504c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 505c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)) { 506c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 507c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV710 PFP Microcode\n"); 508c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < R700_PFP_UCODE_SIZE; i++) 509c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV710_pfp_microcode[i]); 510c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 511c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 512c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 513c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV710 CP Microcode\n"); 514c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < R700_PM4_UCODE_SIZE; i++) 515c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, RV710_cp_microcode[i]); 516c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 517c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 518c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 519c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 520c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 521c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); 522c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 523c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 524c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 525c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r600_test_writeback(drm_radeon_private_t *dev_priv) 526c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 527c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 tmp; 528c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 529c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Start with assuming that writeback doesn't work */ 530c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->writeback_works = 0; 531c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 532c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Writeback doesn't seem to work everywhere, test it here and possibly 533c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * enable it if it appears to work 534c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 535c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0); 536c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 537c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef); 538c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 539c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { 540c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 val; 541c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 542c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1)); 543c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (val == 0xdeadbeef) 544c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 545c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(1); 546c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 547c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 548c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (tmp < dev_priv->usec_timeout) { 549c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->writeback_works = 1; 550c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("writeback test succeeded in %d usecs\n", tmp); 551c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else { 552c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->writeback_works = 0; 553c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("writeback test failed\n"); 554c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 555c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (radeon_no_wb == 1) { 556c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->writeback_works = 0; 557c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("writeback forced off\n"); 558c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 559c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 560c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev_priv->writeback_works) { 561c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Disable writeback to avoid unnecessary bus master transfer */ 562c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, RADEON_READ(R600_CP_RB_CNTL) | 563c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_RB_NO_UPDATE); 564c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SCRATCH_UMSK, 0); 565c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 566c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 567c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 568c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherint r600_do_engine_reset(struct drm_device *dev) 569c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 570c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 571c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cp_ptr, cp_me_cntl, cp_rb_cntl; 572c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 573c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Resetting GPU\n"); 574c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 575c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cp_ptr = RADEON_READ(R600_CP_RB_WPTR); 576c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL); 577c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT); 578c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 579c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff); 580c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_SOFT_RESET); 581c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(50); 582c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 583c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_SOFT_RESET); 584c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 585c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); 586c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL); 587c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, R600_RB_RPTR_WR_ENA); 588c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 589c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr); 590c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr); 591c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl); 592c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl); 593c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 594c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Reset the CP ring */ 595c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cp_reset(dev_priv); 596c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 597c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* The CP is no longer running after an engine reset */ 598c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_running = 0; 599c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 600c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Reset any pending vertex, indirect buffers */ 601c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_freelist_reset(dev); 602c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 603c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return 0; 604c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 605c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 606c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 607c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes, 608c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 num_backends, 609c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 backend_disable_mask) 610c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 611c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 backend_map = 0; 612c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 enabled_backends_mask; 613c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 enabled_backends_count; 614c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cur_pipe; 615c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 swizzle_pipe[R6XX_MAX_PIPES]; 616c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cur_backend; 617c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 i; 618c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 619c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_tile_pipes > R6XX_MAX_PIPES) 620c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_tile_pipes = R6XX_MAX_PIPES; 621c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_tile_pipes < 1) 622c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_tile_pipes = 1; 623c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_backends > R6XX_MAX_BACKENDS) 624c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_backends = R6XX_MAX_BACKENDS; 625c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_backends < 1) 626c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_backends = 1; 627c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 628c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_mask = 0; 629c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_count = 0; 630c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < R6XX_MAX_BACKENDS; ++i) { 631c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((backend_disable_mask >> i) & 1) == 0) { 632c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_mask |= (1 << i); 633c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ++enabled_backends_count; 634c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 635c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (enabled_backends_count == num_backends) 636c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 637c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 638c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 639c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (enabled_backends_count == 0) { 640c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_mask = 1; 641c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_count = 1; 642c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 643c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 644c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (enabled_backends_count != num_backends) 645c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_backends = enabled_backends_count; 646c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 647c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES); 648c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (num_tile_pipes) { 649c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 1: 650c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 651c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 652c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 2: 653c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 654c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 1; 655c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 656c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 3: 657c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 658c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 1; 659c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 2; 660c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 661c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 4: 662c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 663c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 1; 664c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 2; 665c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 3; 666c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 667c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 5: 668c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 669c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 1; 670c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 2; 671c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 3; 672c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[4] = 4; 673c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 674c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 6: 675c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 676c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 2; 677c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 4; 678c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 5; 679c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[4] = 1; 680c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[5] = 3; 681c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 682c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 7: 683c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 684c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 2; 685c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 4; 686c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 6; 687c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[4] = 1; 688c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[5] = 3; 689c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[6] = 5; 690c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 691c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 8: 692c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 693c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 2; 694c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 4; 695c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 6; 696c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[4] = 1; 697c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[5] = 3; 698c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[6] = 5; 699c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[7] = 7; 700c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 701c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 702c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 703c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cur_backend = 0; 704c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 705c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher while (((1 << cur_backend) & enabled_backends_mask) == 0) 706c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; 707c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 708c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 709c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 710c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; 711c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 712c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 713c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return backend_map; 714c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 715c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 716c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic int r600_count_pipe_bits(uint32_t val) 717c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 718c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i, ret = 0; 719c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < 32; i++) { 720c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ret += val & 1; 721c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher val >>= 1; 722c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 723c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return ret; 724c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 725c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 726c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r600_gfx_init(struct drm_device *dev, 727c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv) 728c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 729c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i, j, num_qd_pipes; 730c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sx_debug_1; 731c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 tc_cntl; 732c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 arb_pop; 733c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 num_gs_verts_per_thread; 734c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 vgt_gs_per_es; 735c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 gs_prim_buffer_depth = 0; 736c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_ms_fifo_sizes; 737c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_config; 738c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_gpr_resource_mgmt_1 = 0; 739c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_gpr_resource_mgmt_2 = 0; 740c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_thread_resource_mgmt = 0; 741c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_stack_resource_mgmt_1 = 0; 742c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_stack_resource_mgmt_2 = 0; 743c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 hdp_host_path_cntl; 744c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 backend_map; 745c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 gb_tiling_config = 0; 746c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cc_rb_backend_disable = 0; 747c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cc_gc_shader_pipe_config = 0; 748c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 ramcfg; 749c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 750c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* setup chip specs */ 751c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->flags & RADEON_FAMILY_MASK) { 752c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_R600: 753c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_pipes = 4; 754c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_tile_pipes = 8; 755c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_simds = 4; 756c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends = 4; 757c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gprs = 256; 758c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_threads = 192; 759c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_stack_entries = 256; 760c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_hw_contexts = 8; 761c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gs_threads = 16; 762c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_size = 128; 763c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_pos_size = 16; 764c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_smx_size = 128; 765c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sq_num_cf_insts = 2; 766c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 767c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV630: 768c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV635: 769c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_pipes = 2; 770c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_tile_pipes = 2; 771c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_simds = 3; 772c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends = 1; 773c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gprs = 128; 774c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_threads = 192; 775c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_stack_entries = 128; 776c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_hw_contexts = 8; 777c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gs_threads = 4; 778c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_size = 128; 779c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_pos_size = 16; 780c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_smx_size = 128; 781c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sq_num_cf_insts = 2; 782c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 783c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV610: 784c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RS780: 785c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV620: 786c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_pipes = 1; 787c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_tile_pipes = 1; 788c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_simds = 2; 789c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends = 1; 790c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gprs = 128; 791c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_threads = 192; 792c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_stack_entries = 128; 793c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_hw_contexts = 4; 794c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gs_threads = 4; 795c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_size = 128; 796c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_pos_size = 16; 797c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_smx_size = 128; 798c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sq_num_cf_insts = 1; 799c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 800c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV670: 801c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_pipes = 4; 802c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_tile_pipes = 4; 803c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_simds = 4; 804c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends = 4; 805c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gprs = 192; 806c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_threads = 192; 807c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_stack_entries = 256; 808c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_hw_contexts = 8; 809c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gs_threads = 16; 810c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_size = 128; 811c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_pos_size = 16; 812c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_smx_size = 128; 813c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sq_num_cf_insts = 2; 814c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 815c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 816c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 817c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 818c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 819c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Initialize HDP */ 820c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher j = 0; 821c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < 32; i++) { 822c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c14 + j), 0x00000000); 823c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c18 + j), 0x00000000); 824c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c1c + j), 0x00000000); 825c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c20 + j), 0x00000000); 826c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c24 + j), 0x00000000); 827c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher j += 0x18; 828c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 829c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 830c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff)); 831c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 832c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* setup tiling, simd, pipe config */ 833c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ramcfg = RADEON_READ(R600_RAMCFG); 834c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 835c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->r600_max_tile_pipes) { 836c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 1: 837c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(0); 838c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 839c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 2: 840c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(1); 841c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 842c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 4: 843c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(2); 844c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 845c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 8: 846c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(3); 847c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 848c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 849c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 850c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 851c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 852c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK); 853c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 854c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_GROUP_SIZE(0); 855c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 856c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) { 857c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_ROW_TILING(3); 858c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_SAMPLE_SPLIT(3); 859c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else { 860c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= 861c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK)); 862c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= 863c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK)); 864c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 865c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 866c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_BANK_SWAPS(1); 867c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 868c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes, 869c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends, 870c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (0xff << dev_priv->r600_max_backends) & 0xff); 871c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_BACKEND_MAP(backend_map); 872c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 873c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cc_gc_shader_pipe_config = 874c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK); 875c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cc_gc_shader_pipe_config |= 876c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK); 877c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 878c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cc_rb_backend_disable = 879c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK); 880c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 881c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); 882c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 883c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 884c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 885c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 886c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 887c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 888c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 889c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_qd_pipes = 890c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R6XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK); 891c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK); 892c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK); 893c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 894c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* set HW defaults for 3D engine */ 895c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) | 896c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ROQ_IB2_START(0x2b))); 897c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 898c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) | 899c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ROQ_END(0x40))); 900c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 901c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO | 902c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SYNC_GRADIENT | 903c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SYNC_WALKER | 904c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SYNC_ALIGNER)); 905c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 906c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) 907c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021); 908c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 909c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1); 910c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sx_debug_1 |= R600_SMX_EVENT_RELEASE; 911c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600)) 912c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS; 913c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1); 914c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 915c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || 916c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || 917c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 918c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 919c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) 920c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE); 921c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 922c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_DB_DEBUG, 0); 923c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 924c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) | 925c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_DEPTH_FLUSH(16) | 926c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_DEPTH_PENDING_FREE(4) | 927c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_DEPTH_CACHELINE_FREE(16))); 928c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 929c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0); 930c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 931c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0)); 932c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0)); 933c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 934c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES); 935c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 936c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 937c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) { 938c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) | 939c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_FETCH_FIFO_HIWATER(0xa) | 940c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_DONE_FIFO_HIWATER(0xe0) | 941c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ALU_UPDATE_FIFO_HIWATER(0x8)); 942c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || 943c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) { 944c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff); 945c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4); 946c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 947c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 948c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 949c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 950c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * should be adjusted as needed by the 2D/3D drivers. This just sets default values 951c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 952c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config = RADEON_READ(R600_SQ_CONFIG); 953c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config &= ~(R600_PS_PRIO(3) | 954c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VS_PRIO(3) | 955c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_GS_PRIO(3) | 956c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ES_PRIO(3)); 957c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config |= (R600_DX9_CONSTS | 958c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VC_ENABLE | 959c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_PS_PRIO(0) | 960c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VS_PRIO(1) | 961c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_GS_PRIO(2) | 962c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ES_PRIO(3)); 963c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 964c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) { 965c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) | 966c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_GPRS(124) | 967c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_CLAUSE_TEMP_GPRS(4)); 968c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) | 969c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_GPRS(0)); 970c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) | 971c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_THREADS(48) | 972c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_GS_THREADS(4) | 973c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_THREADS(4)); 974c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) | 975c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_STACK_ENTRIES(128)); 976c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) | 977c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_STACK_ENTRIES(0)); 978c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 979c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 980c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) { 981c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* no vertex cache */ 982c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config &= ~R600_VC_ENABLE; 983c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 984c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 985c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_GPRS(44) | 986c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_CLAUSE_TEMP_GPRS(2)); 987c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) | 988c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_GPRS(17)); 989c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 990c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_THREADS(78) | 991c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_GS_THREADS(4) | 992c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_THREADS(31)); 993c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) | 994c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_STACK_ENTRIES(40)); 995c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) | 996c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_STACK_ENTRIES(16)); 997c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || 998c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) { 999c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 1000c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_GPRS(44) | 1001c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_CLAUSE_TEMP_GPRS(2)); 1002c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) | 1003c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_GPRS(18)); 1004c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 1005c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_THREADS(78) | 1006c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_GS_THREADS(4) | 1007c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_THREADS(31)); 1008c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) | 1009c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_STACK_ENTRIES(40)); 1010c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) | 1011c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_STACK_ENTRIES(16)); 1012c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) { 1013c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 1014c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_GPRS(44) | 1015c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_CLAUSE_TEMP_GPRS(2)); 1016c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) | 1017c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_GPRS(17)); 1018c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 1019c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_THREADS(78) | 1020c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_GS_THREADS(4) | 1021c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_THREADS(31)); 1022c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) | 1023c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_STACK_ENTRIES(64)); 1024c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) | 1025c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_STACK_ENTRIES(64)); 1026c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1027c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1028c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_CONFIG, sq_config); 1029c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 1030c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 1031c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1032c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 1033c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 1034c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1035c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 1036c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 1037c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) 1038c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY)); 1039c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 1040c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC)); 1041c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1042c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) | 1043c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S0_Y(0x4) | 1044c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S1_X(0x4) | 1045c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S1_Y(0xc))); 1046c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) | 1047c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S0_Y(0xe) | 1048c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S1_X(0x2) | 1049c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S1_Y(0x2) | 1050c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S2_X(0xa) | 1051c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S2_Y(0x6) | 1052c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S3_X(0x6) | 1053c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S3_Y(0xa))); 1054c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) | 1055c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S0_Y(0xb) | 1056c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S1_X(0x4) | 1057c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S1_Y(0xc) | 1058c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S2_X(0x1) | 1059c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S2_Y(0x6) | 1060c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S3_X(0xa) | 1061c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S3_Y(0xe))); 1062c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) | 1063c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S4_Y(0x1) | 1064c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S5_X(0x0) | 1065c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S5_Y(0x0) | 1066c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S6_X(0xb) | 1067c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S6_Y(0x4) | 1068c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S7_X(0x7) | 1069c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S7_Y(0x8))); 1070c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1071c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1072c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1073c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_R600: 1074c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV630: 1075c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV635: 1076c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gs_prim_buffer_depth = 0; 1077c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1078c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV610: 1079c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RS780: 1080c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV620: 1081c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gs_prim_buffer_depth = 32; 1082c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1083c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV670: 1084c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gs_prim_buffer_depth = 128; 1085c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1086c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 1087c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1088c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1089c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1090c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; 1091c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 1092c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Max value for this is 256 */ 1093c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (vgt_gs_per_es > 256) 1094c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vgt_gs_per_es = 256; 1095c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1096c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_ES_PER_GS, 128); 1097c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es); 1098c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_GS_PER_VS, 2); 1099c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16); 1100c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1101c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* more default values. 2D/3D driver should adjust as needed */ 1102c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0); 1103c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_STRMOUT_EN, 0); 1104c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SX_MISC, 0); 1105c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0); 1106c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0); 1107c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0); 1108c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_INPUT_Z, 0); 1109c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2)); 1110c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR7_FRAG, 0); 1111c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1112c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* clear render buffer base addresses */ 1113c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR0_BASE, 0); 1114c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR1_BASE, 0); 1115c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR2_BASE, 0); 1116c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR3_BASE, 0); 1117c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR4_BASE, 0); 1118c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR5_BASE, 0); 1119c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR6_BASE, 0); 1120c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR7_BASE, 0); 1121c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1122c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1123c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV610: 1124c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RS780: 1125c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV620: 1126c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher tc_cntl = R600_TC_L2_SIZE(8); 1127c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1128c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV630: 1129c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV635: 1130c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher tc_cntl = R600_TC_L2_SIZE(4); 1131c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1132c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_R600: 1133c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT; 1134c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1135c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 1136c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher tc_cntl = R600_TC_L2_SIZE(0); 1137c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1138c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1139c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1140c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_TC_CNTL, tc_cntl); 1141c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1142c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL); 1143c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1144c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1145c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher arb_pop = RADEON_READ(R600_ARB_POP); 1146c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher arb_pop |= R600_ENABLE_TC128; 1147c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_ARB_POP, arb_pop); 1148c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1149c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1150c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA | 1151c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_CLIP_SEQ(3))); 1152c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095)); 1153c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1154c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 1155c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1156c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes, 1157c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 num_backends, 1158c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 backend_disable_mask) 1159c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 1160c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 backend_map = 0; 1161c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 enabled_backends_mask; 1162c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 enabled_backends_count; 1163c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cur_pipe; 1164c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 swizzle_pipe[R7XX_MAX_PIPES]; 1165c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cur_backend; 1166c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 i; 1167c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1168c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_tile_pipes > R7XX_MAX_PIPES) 1169c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_tile_pipes = R7XX_MAX_PIPES; 1170c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_tile_pipes < 1) 1171c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_tile_pipes = 1; 1172c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_backends > R7XX_MAX_BACKENDS) 1173c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_backends = R7XX_MAX_BACKENDS; 1174c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_backends < 1) 1175c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_backends = 1; 1176c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1177c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_mask = 0; 1178c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_count = 0; 1179c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < R7XX_MAX_BACKENDS; ++i) { 1180c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((backend_disable_mask >> i) & 1) == 0) { 1181c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_mask |= (1 << i); 1182c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ++enabled_backends_count; 1183c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1184c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (enabled_backends_count == num_backends) 1185c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1186c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1187c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1188c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (enabled_backends_count == 0) { 1189c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_mask = 1; 1190c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_count = 1; 1191c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1192c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1193c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (enabled_backends_count != num_backends) 1194c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_backends = enabled_backends_count; 1195c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1196c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES); 1197c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (num_tile_pipes) { 1198c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 1: 1199c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 1200c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1201c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 2: 1202c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 1203c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 1; 1204c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1205c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 3: 1206c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 1207c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 2; 1208c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 1; 1209c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1210c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 4: 1211c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 1212c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 2; 1213c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 3; 1214c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 1; 1215c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1216c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 5: 1217c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 1218c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 2; 1219c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 4; 1220c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 1; 1221c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[4] = 3; 1222c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1223c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 6: 1224c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 1225c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 2; 1226c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 4; 1227c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 5; 1228c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[4] = 3; 1229c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[5] = 1; 1230c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1231c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 7: 1232c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 1233c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 2; 1234c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 4; 1235c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 6; 1236c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[4] = 3; 1237c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[5] = 1; 1238c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[6] = 5; 1239c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1240c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 8: 1241c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 1242c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 2; 1243c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 4; 1244c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 6; 1245c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[4] = 3; 1246c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[5] = 1; 1247c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[6] = 7; 1248c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[7] = 5; 1249c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1250c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1251c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1252c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cur_backend = 0; 1253c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 1254c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher while (((1 << cur_backend) & enabled_backends_mask) == 0) 1255c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 1256c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1257c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 1258c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1259c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 1260c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1261c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1262c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return backend_map; 1263c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 1264c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1265c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r700_gfx_init(struct drm_device *dev, 1266c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv) 1267c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 1268c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i, j, num_qd_pipes; 1269c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sx_debug_1; 1270c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 smx_dc_ctl0; 1271c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 num_gs_verts_per_thread; 1272c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 vgt_gs_per_es; 1273c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 gs_prim_buffer_depth = 0; 1274c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_ms_fifo_sizes; 1275c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_config; 1276c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_thread_resource_mgmt; 1277c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 hdp_host_path_cntl; 1278c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_dyn_gpr_size_simd_ab_0; 1279c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 backend_map; 1280c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 gb_tiling_config = 0; 1281c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cc_rb_backend_disable = 0; 1282c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cc_gc_shader_pipe_config = 0; 1283c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 mc_arb_ramcfg; 1284c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 db_debug4; 1285c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1286c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* setup chip specs */ 1287c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1288c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV770: 1289c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_pipes = 4; 1290c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_tile_pipes = 8; 1291c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_simds = 10; 1292c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends = 4; 1293c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gprs = 256; 1294c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_threads = 248; 1295c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_stack_entries = 512; 1296c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_hw_contexts = 8; 1297c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gs_threads = 16 * 2; 1298c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_size = 128; 1299c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_pos_size = 16; 1300c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_smx_size = 112; 1301c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sq_num_cf_insts = 2; 1302c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1303c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sx_num_of_sets = 7; 1304c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_prim_fifo_size = 0xF9; 1305c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1306c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1307c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1308c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV730: 1309c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_pipes = 2; 1310c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_tile_pipes = 4; 1311c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_simds = 8; 1312c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends = 2; 1313c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gprs = 128; 1314c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_threads = 248; 1315c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_stack_entries = 256; 1316c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_hw_contexts = 8; 1317c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gs_threads = 16 * 2; 1318c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_size = 256; 1319c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_pos_size = 32; 1320c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_smx_size = 224; 1321c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sq_num_cf_insts = 2; 1322c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1323c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sx_num_of_sets = 7; 1324c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_prim_fifo_size = 0xf9; 1325c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1326c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1327c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1328c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV710: 1329c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_pipes = 2; 1330c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_tile_pipes = 2; 1331c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_simds = 2; 1332c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends = 1; 1333c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gprs = 256; 1334c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_threads = 192; 1335c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_stack_entries = 256; 1336c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_hw_contexts = 4; 1337c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gs_threads = 8 * 2; 1338c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_size = 128; 1339c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_pos_size = 16; 1340c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_smx_size = 112; 1341c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sq_num_cf_insts = 1; 1342c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1343c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sx_num_of_sets = 7; 1344c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_prim_fifo_size = 0x40; 1345c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1346c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1347c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1348c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 1349c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1350c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1351c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1352c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Initialize HDP */ 1353c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher j = 0; 1354c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < 32; i++) { 1355c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c14 + j), 0x00000000); 1356c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c18 + j), 0x00000000); 1357c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c1c + j), 0x00000000); 1358c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c20 + j), 0x00000000); 1359c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c24 + j), 0x00000000); 1360c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher j += 0x18; 1361c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1362c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1363c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff)); 1364c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1365c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* setup tiling, simd, pipe config */ 1366c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG); 1367c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1368c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->r600_max_tile_pipes) { 1369c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 1: 1370c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(0); 1371c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1372c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 2: 1373c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(1); 1374c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1375c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 4: 1376c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(2); 1377c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1378c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 8: 1379c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(3); 1380c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1381c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 1382c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1383c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1384c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1385c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770) 1386c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_BANK_TILING(1); 1387c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 1388c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK); 1389c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1390c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_GROUP_SIZE(0); 1391c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1392c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) { 1393c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_ROW_TILING(3); 1394c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_SAMPLE_SPLIT(3); 1395c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else { 1396c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= 1397c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK)); 1398c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= 1399c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK)); 1400c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1401c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1402c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_BANK_SWAPS(1); 1403c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1404c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher backend_map = r700_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes, 1405c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends, 1406c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (0xff << dev_priv->r600_max_backends) & 0xff); 1407c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_BACKEND_MAP(backend_map); 1408c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1409c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cc_gc_shader_pipe_config = 1410c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK); 1411c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cc_gc_shader_pipe_config |= 1412c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK); 1413c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1414c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cc_rb_backend_disable = 1415c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK); 1416c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1417c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); 1418c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1419c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1420c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1421c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 1422c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 1423c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 1424c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1425c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); 1426c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0); 1427c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0); 1428c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0); 1429c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0); 1430c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1431c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_qd_pipes = 1432c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK); 1433c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK); 1434c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK); 1435c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1436c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* set HW defaults for 3D engine */ 1437c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) | 1438c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ROQ_IB2_START(0x2b))); 1439c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1440c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30)); 1441c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1442c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO | 1443c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SYNC_GRADIENT | 1444c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SYNC_WALKER | 1445c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SYNC_ALIGNER)); 1446c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1447c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1); 1448c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS; 1449c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1); 1450c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1451c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0); 1452c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff); 1453c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1); 1454c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0); 1455c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1456c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) | 1457c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_GS_FLUSH_CTL(4) | 1458c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_ACK_FLUSH_CTL(3) | 1459c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SYNC_FLUSH_CTL)); 1460c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1461c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770) 1462c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_DB_DEBUG3, R700_DB_CLK_OFF_DELAY(0x1f)); 1463c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else { 1464c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher db_debug4 = RADEON_READ(RV700_DB_DEBUG4); 1465c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER; 1466c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(RV700_DB_DEBUG4, db_debug4); 1467c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1468c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1469c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) | 1470c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) | 1471c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1))); 1472c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1473c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) | 1474c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) | 1475c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize))); 1476c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1477c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1478c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1479c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1); 1480c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1481c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0)); 1482c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1483c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4)); 1484c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1485c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PERFMON_CNTL, 0); 1486c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1487c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) | 1488c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_DONE_FIFO_HIWATER(0xe0) | 1489c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ALU_UPDATE_FIFO_HIWATER(0x8)); 1490c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1491c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV770: 1492c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1); 1493c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1494c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV730: 1495c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV710: 1496c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 1497c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4); 1498c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1499c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1500c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 1501c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1502c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 1503c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * should be adjusted as needed by the 2D/3D drivers. This just sets default values 1504c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 1505c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config = RADEON_READ(R600_SQ_CONFIG); 1506c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config &= ~(R600_PS_PRIO(3) | 1507c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VS_PRIO(3) | 1508c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_GS_PRIO(3) | 1509c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ES_PRIO(3)); 1510c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config |= (R600_DX9_CONSTS | 1511c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VC_ENABLE | 1512c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_EXPORT_SRC_C | 1513c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_PS_PRIO(0) | 1514c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VS_PRIO(1) | 1515c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_GS_PRIO(2) | 1516c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ES_PRIO(3)); 1517c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) 1518c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* no vertex cache */ 1519c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config &= ~R600_VC_ENABLE; 1520c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1521c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_CONFIG, sq_config); 1522c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1523c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) | 1524c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) | 1525c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2))); 1526c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1527c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) | 1528c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64))); 1529c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1530c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) | 1531c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) | 1532c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8)); 1533c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads) 1534c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads); 1535c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 1536c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8); 1537c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1538c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1539c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) | 1540c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); 1541c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1542c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) | 1543c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); 1544c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1545c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) | 1546c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) | 1547c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) | 1548c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64)); 1549c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1550c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); 1551c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); 1552c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); 1553c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); 1554c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); 1555c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); 1556c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); 1557c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); 1558c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1559c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) | 1560c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_FORCE_EOV_MAX_REZ_CNT(255))); 1561c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1562c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) 1563c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) | 1564c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO))); 1565c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 1566c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) | 1567c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO))); 1568c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1569c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1570c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV770: 1571c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV730: 1572c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gs_prim_buffer_depth = 384; 1573c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1574c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV710: 1575c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gs_prim_buffer_depth = 128; 1576c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1577c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 1578c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1579c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1580c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1581c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; 1582c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 1583c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Max value for this is 256 */ 1584c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (vgt_gs_per_es > 256) 1585c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vgt_gs_per_es = 256; 1586c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1587c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_ES_PER_GS, 128); 1588c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es); 1589c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_GS_PER_VS, 2); 1590c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1591c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* more default values. 2D/3D driver should adjust as needed */ 1592c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16); 1593c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0); 1594c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_STRMOUT_EN, 0); 1595c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SX_MISC, 0); 1596c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0); 1597c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa); 1598c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0); 1599c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff); 1600c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0); 1601c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_INPUT_Z, 0); 1602c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2)); 1603c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR7_FRAG, 0); 1604c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1605c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* clear render buffer base addresses */ 1606c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR0_BASE, 0); 1607c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR1_BASE, 0); 1608c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR2_BASE, 0); 1609c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR3_BASE, 0); 1610c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR4_BASE, 0); 1611c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR5_BASE, 0); 1612c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR6_BASE, 0); 1613c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR7_BASE, 0); 1614c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1615c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_TCP_CNTL, 0); 1616c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1617c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL); 1618c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1619c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1620c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1621c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1622c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA | 1623c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_CLIP_SEQ(3))); 1624c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1625c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 1626c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1627c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r600_cp_init_ring_buffer(struct drm_device *dev, 1628c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv, 1629c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_file *file_priv) 1630c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 1631c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_radeon_master_private *master_priv; 1632c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 ring_start; 16336546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie u64 rptr_addr; 1634c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1635c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 1636c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r700_gfx_init(dev, dev_priv); 1637c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 1638c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_gfx_init(dev, dev_priv); 1639c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1640c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 1641c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_SOFT_RESET); 1642c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(15000); 1643c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 1644c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1645c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1646c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Set ring buffer size */ 1647c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#ifdef __BIG_ENDIAN 1648c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 1649c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_BUF_SWAP_32BIT | 1650c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_RB_NO_UPDATE | 1651c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->ring.rptr_update_l2qw << 8) | 1652c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size_l2qw); 1653c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#else 1654c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 1655c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_RB_NO_UPDATE | 1656c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->ring.rptr_update_l2qw << 8) | 1657c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size_l2qw); 1658c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 1659c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1660c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x4); 1661c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1662c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Set the write pointer delay */ 1663c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); 1664c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1665c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#ifdef __BIG_ENDIAN 1666c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 1667c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_BUF_SWAP_32BIT | 1668c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_RB_NO_UPDATE | 1669c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_RB_RPTR_WR_ENA | 1670c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->ring.rptr_update_l2qw << 8) | 1671c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size_l2qw); 1672c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#else 1673c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 1674c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_RB_NO_UPDATE | 1675c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_RB_RPTR_WR_ENA | 1676c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->ring.rptr_update_l2qw << 8) | 1677c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size_l2qw); 1678c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 1679c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1680c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Initialize the ring buffer's read and write pointers */ 1681c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_RPTR_WR, 0); 1682c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_WPTR, 0); 1683c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher SET_RING_HEAD(dev_priv, 0); 1684c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.tail = 0; 1685c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1686c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#if __OS_HAS_AGP 1687c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->flags & RADEON_IS_AGP) { 16886546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie rptr_addr = dev_priv->ring_rptr->offset 16896546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie - dev->agp->base + 16906546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie dev_priv->gart_vm_start; 1691c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else 1692c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 1693c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher { 16946546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie rptr_addr = dev_priv->ring_rptr->offset 16956546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie - ((unsigned long) dev->sg->virtual) 16966546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie + dev_priv->gart_vm_start; 1697c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 16986546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie RADEON_WRITE(R600_CP_RB_RPTR_ADDR, 16996546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie rptr_addr & 0xffffffff); 17006546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI, 17016546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie upper_32_bits(rptr_addr)); 1702c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1703c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#ifdef __BIG_ENDIAN 1704c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 1705c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_BUF_SWAP_32BIT | 1706c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->ring.rptr_update_l2qw << 8) | 1707c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size_l2qw); 1708c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#else 1709c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 1710c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->ring.rptr_update_l2qw << 8) | 1711c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size_l2qw); 1712c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 1713c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1714c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#if __OS_HAS_AGP 1715c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->flags & RADEON_IS_AGP) { 1716c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* XXX */ 1717c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_write_agp_base(dev_priv, dev->agp->base); 1718c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1719c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* XXX */ 1720c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_write_agp_location(dev_priv, 1721c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (((dev_priv->gart_vm_start - 1 + 1722c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_size) & 0xffff0000) | 1723c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->gart_vm_start >> 16))); 1724c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1725c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ring_start = (dev_priv->cp_ring->offset 1726c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher - dev->agp->base 1727c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + dev_priv->gart_vm_start); 1728c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else 1729c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 1730c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ring_start = (dev_priv->cp_ring->offset 1731c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher - (unsigned long)dev->sg->virtual 1732c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + dev_priv->gart_vm_start); 1733c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1734c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8); 1735c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1736c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_CNTL, 0xff); 1737c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1738c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28)); 1739c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1740c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Start with assuming that writeback doesn't work */ 1741c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->writeback_works = 0; 1742c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1743c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Initialize the scratch register pointer. This will cause 1744c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * the scratch register values to be written out to memory 1745c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * whenever they are updated. 1746c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * 1747c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * We simply put this behind the ring read pointer, this works 1748c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * with PCI GART as well as (whatever kind of) AGP GART 1749c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 17506546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie { 17516546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie u64 scratch_addr; 17526546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie 17536546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR); 17546546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32; 17556546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie scratch_addr += R600_SCRATCH_REG_OFFSET; 17566546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie scratch_addr >>= 8; 17576546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie scratch_addr &= 0xffffffff; 17586546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie 17596546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr); 17606546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie } 1761c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1762c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SCRATCH_UMSK, 0x7); 1763c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1764c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Turn on bus mastering */ 1765c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_enable_bm(dev_priv); 1766c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1767c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0); 1768c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_LAST_FRAME_REG, 0); 1769c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1770c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0); 1771c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_LAST_DISPATCH_REG, 0); 1772c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1773c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0); 1774c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_LAST_CLEAR_REG, 0); 1775c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1776c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* reset sarea copies of these */ 1777c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher master_priv = file_priv->master->driver_priv; 1778c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (master_priv->sarea_priv) { 1779c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher master_priv->sarea_priv->last_frame = 0; 1780c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher master_priv->sarea_priv->last_dispatch = 0; 1781c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher master_priv->sarea_priv->last_clear = 0; 1782c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1783c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1784c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_wait_for_idle(dev_priv); 1785c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1786c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 1787c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1788c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherint r600_do_cleanup_cp(struct drm_device *dev) 1789c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 1790c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 1791c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("\n"); 1792c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1793c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Make sure interrupts are disabled here because the uninstall ioctl 1794c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * may not have been called from userspace and after dev_private 1795c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * is freed, it's too late. 1796c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 1797c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev->irq_enabled) 1798c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_irq_uninstall(dev); 1799c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1800c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#if __OS_HAS_AGP 1801c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->flags & RADEON_IS_AGP) { 1802c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->cp_ring != NULL) { 1803c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_core_ioremapfree(dev_priv->cp_ring, dev); 1804c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_ring = NULL; 1805c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1806c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->ring_rptr != NULL) { 1807c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_core_ioremapfree(dev_priv->ring_rptr, dev); 1808c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring_rptr = NULL; 1809c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1810c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev->agp_buffer_map != NULL) { 1811c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_core_ioremapfree(dev->agp_buffer_map, dev); 1812c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev->agp_buffer_map = NULL; 1813c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1814c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else 1815c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 1816c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher { 1817c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1818c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->gart_info.bus_addr) 1819c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_page_table_cleanup(dev, &dev_priv->gart_info); 1820c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1821c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) { 1822c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); 18238f497aade8df2a619eacda927a43ebe82167a84cHannes Eder dev_priv->gart_info.addr = NULL; 1824c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1825c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1826c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* only clear to the start of flags */ 1827c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); 1828c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1829c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return 0; 1830c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 1831c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1832c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherint r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, 1833c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_file *file_priv) 1834c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 1835c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 1836c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; 1837c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1838c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("\n"); 1839c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1840c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* if we require new memory map but we don't have it fail */ 1841c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { 1842c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); 1843c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 1844c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 1845c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1846c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1847c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) { 1848c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("Forcing AGP card to PCI mode\n"); 1849c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->flags &= ~RADEON_IS_AGP; 1850c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* The writeback test succeeds, but when writeback is enabled, 1851c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * the ring buffer read ptr update fails after first 128 bytes. 1852c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 1853c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_no_wb = 1; 1854c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) 1855c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher && !init->is_pci) { 1856c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("Restoring AGP flag\n"); 1857c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->flags |= RADEON_IS_AGP; 1858c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1859c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1860c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->usec_timeout = init->usec_timeout; 1861c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->usec_timeout < 1 || 1862c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { 1863c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("TIMEOUT problem!\n"); 1864c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 1865c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 1866c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1867c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1868c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Enable vblank on CRTC1 for older X servers 1869c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 1870c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; 1871c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1872c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_mode = init->cp_mode; 1873c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1874c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* We don't support anything other than bus-mastering ring mode, 1875c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * but the ring can be in either AGP or PCI space for the ring 1876c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * read pointer. 1877c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 1878c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && 1879c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { 1880c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); 1881c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 1882c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 1883c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1884c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1885c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (init->fb_bpp) { 1886c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 16: 1887c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; 1888c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1889c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 32: 1890c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 1891c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; 1892c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1893c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1894c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->front_offset = init->front_offset; 1895c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->front_pitch = init->front_pitch; 1896c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->back_offset = init->back_offset; 1897c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->back_pitch = init->back_pitch; 1898c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1899c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring_offset = init->ring_offset; 1900c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring_rptr_offset = init->ring_rptr_offset; 1901c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->buffers_offset = init->buffers_offset; 1902c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_textures_offset = init->gart_textures_offset; 1903c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1904c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher master_priv->sarea = drm_getsarea(dev); 1905c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!master_priv->sarea) { 1906c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("could not find sarea!\n"); 1907c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 1908c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 1909c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1910c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1911c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); 1912c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev_priv->cp_ring) { 1913c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("could not find cp ring region!\n"); 1914c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 1915c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 1916c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1917c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); 1918c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev_priv->ring_rptr) { 1919c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("could not find ring read pointer!\n"); 1920c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 1921c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 1922c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1923c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev->agp_buffer_token = init->buffers_offset; 1924c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); 1925c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev->agp_buffer_map) { 1926c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("could not find dma buffer region!\n"); 1927c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 1928c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 1929c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1930c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1931c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (init->gart_textures_offset) { 1932c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_textures = 1933c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_core_findmap(dev, init->gart_textures_offset); 1934c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev_priv->gart_textures) { 1935c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("could not find GART texture region!\n"); 1936c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 1937c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 1938c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1939c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1940c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1941c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#if __OS_HAS_AGP 1942c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* XXX */ 1943c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->flags & RADEON_IS_AGP) { 19447659e9804b7a66047433182d86393d38ba4eff79Alex Deucher drm_core_ioremap_wc(dev_priv->cp_ring, dev); 19457659e9804b7a66047433182d86393d38ba4eff79Alex Deucher drm_core_ioremap_wc(dev_priv->ring_rptr, dev); 19467659e9804b7a66047433182d86393d38ba4eff79Alex Deucher drm_core_ioremap_wc(dev->agp_buffer_map, dev); 1947c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev_priv->cp_ring->handle || 1948c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher !dev_priv->ring_rptr->handle || 1949c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher !dev->agp_buffer_map->handle) { 1950c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("could not find ioremap agp regions!\n"); 1951c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 1952c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 1953c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1954c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else 1955c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 1956c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher { 1957c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset; 1958c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring_rptr->handle = 1959c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (void *)dev_priv->ring_rptr->offset; 1960c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev->agp_buffer_map->handle = 1961c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (void *)dev->agp_buffer_map->offset; 1962c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1963c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("dev_priv->cp_ring->handle %p\n", 1964c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_ring->handle); 1965c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", 1966c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring_rptr->handle); 1967c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("dev->agp_buffer_map->handle %p\n", 1968c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev->agp_buffer_map->handle); 1969c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1970c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1971c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24; 1972c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->fb_size = 1973c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000) 1974c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher - dev_priv->fb_location; 1975c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1976c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | 1977c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->front_offset 1978c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + dev_priv->fb_location) >> 10)); 1979c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1980c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | 1981c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->back_offset 1982c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + dev_priv->fb_location) >> 10)); 1983c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1984c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | 1985c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->depth_offset 1986c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + dev_priv->fb_location) >> 10)); 1987c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1988c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_size = init->gart_size; 1989c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1990c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* New let's set the memory map ... */ 1991c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->new_memmap) { 1992c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 base = 0; 1993c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1994c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Setting GART location based on new memory map\n"); 1995c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1996c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* If using AGP, try to locate the AGP aperture at the same 1997c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * location in the card and on the bus, though we have to 1998c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * align it down. 1999c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 2000c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#if __OS_HAS_AGP 2001c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* XXX */ 2002c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->flags & RADEON_IS_AGP) { 2003c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher base = dev->agp->base; 2004c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Check if valid */ 2005c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && 2006c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { 2007c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n", 2008c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev->agp->base); 2009c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher base = 0; 2010c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2011c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2012c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 2013c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* If not or if AGP is at 0 (Macs), try to put it elsewhere */ 2014c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (base == 0) { 2015c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher base = dev_priv->fb_location + dev_priv->fb_size; 2016c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (base < dev_priv->fb_location || 2017c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((base + dev_priv->gart_size) & 0xfffffffful) < base) 2018c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher base = dev_priv->fb_location 2019c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher - dev_priv->gart_size; 2020c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2021c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_vm_start = base & 0xffc00000u; 2022c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->gart_vm_start != base) 2023c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n", 2024c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher base, dev_priv->gart_vm_start); 2025c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2026c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2027c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#if __OS_HAS_AGP 2028c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* XXX */ 2029c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->flags & RADEON_IS_AGP) 2030c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 2031c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher - dev->agp->base 2032c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + dev_priv->gart_vm_start); 2033c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 2034c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 2035c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 2036c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher - (unsigned long)dev->sg->virtual 2037c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + dev_priv->gart_vm_start); 2038c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2039c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("fb 0x%08x size %d\n", 2040c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (unsigned int) dev_priv->fb_location, 2041c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (unsigned int) dev_priv->fb_size); 2042c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); 2043c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n", 2044c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (unsigned int) dev_priv->gart_vm_start); 2045c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n", 2046c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_buffers_offset); 2047c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2048c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; 2049c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle 2050c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + init->ring_size / sizeof(u32)); 2051c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size = init->ring_size; 2052c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); 2053c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2054c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; 2055c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8); 2056c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2057c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.fetch_size = /* init->fetch_size */ 32; 2058c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16); 2059c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2060c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; 2061c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2062c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; 2063c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2064c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#if __OS_HAS_AGP 2065c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->flags & RADEON_IS_AGP) { 2066c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* XXX turn off pcie gart */ 2067c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else 2068c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 2069c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher { 2070c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); 2071c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* if we have an offset set from userspace */ 2072c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev_priv->pcigart_offset_set) { 2073c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("Need gart offset from userspace\n"); 2074c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2075c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2076c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2077c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2078c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset); 2079c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2080c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.bus_addr = 2081c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->pcigart_offset + dev_priv->fb_location; 2082c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.mapping.offset = 2083c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->pcigart_offset + dev_priv->fb_aper_offset; 2084c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.mapping.size = 2085c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.table_size; 2086c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2087c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev); 2088c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev_priv->gart_info.mapping.handle) { 2089c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("ioremap failed.\n"); 2090c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2091c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2092c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2093c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2094c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.addr = 2095c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.mapping.handle; 2096c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2097c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n", 2098c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.addr, 2099c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->pcigart_offset); 2100c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2101c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (r600_page_table_init(dev)) { 2102c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("Failed to init GART table\n"); 2103c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2104c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2105c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2106c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2107c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 2108c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r700_vm_init(dev); 2109c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 2110c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_vm_init(dev); 2111c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2112c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2113c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 2114c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r700_cp_load_microcode(dev_priv); 2115c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 2116c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_cp_load_microcode(dev_priv); 2117c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2118c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_cp_init_ring_buffer(dev, dev_priv, file_priv); 2119c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2120c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->last_buf = 0; 2121c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2122c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_engine_reset(dev); 2123c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_test_writeback(dev_priv); 2124c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2125c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return 0; 2126c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 2127c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2128c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherint r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv) 2129c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 2130c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 2131c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2132c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("\n"); 2133c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) { 2134c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r700_vm_init(dev); 2135c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r700_cp_load_microcode(dev_priv); 2136c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else { 2137c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_vm_init(dev); 2138c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_cp_load_microcode(dev_priv); 2139c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2140c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_cp_init_ring_buffer(dev, dev_priv, file_priv); 2141c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_engine_reset(dev); 2142c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2143c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return 0; 2144c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 2145c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2146c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher/* Wait for the CP to go idle. 2147c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 2148c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherint r600_do_cp_idle(drm_radeon_private_t *dev_priv) 2149c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 2150c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RING_LOCALS; 2151c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("\n"); 2152c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2153c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher BEGIN_RING(5); 2154c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); 2155c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT); 2156c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* wait for 3D idle clean */ 2157c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); 2158c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2); 2159c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN); 2160c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2161c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ADVANCE_RING(); 2162c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher COMMIT_RING(); 2163c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2164c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return r600_do_wait_for_idle(dev_priv); 2165c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 2166c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2167c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher/* Start the Command Processor. 2168c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 2169c05ce0834a268f7d18274847190f6ed826b99332Alex Deuchervoid r600_do_cp_start(drm_radeon_private_t *dev_priv) 2170c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 2171c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cp_me; 2172c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RING_LOCALS; 2173c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("\n"); 2174c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2175c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher BEGIN_RING(7); 2176c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5)); 2177c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(0x00000001); 2178c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) 2179c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(0x00000003); 2180c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 2181c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(0x00000000); 2182c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING((dev_priv->r600_max_hw_contexts - 1)); 2183c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1)); 2184c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(0x00000000); 2185c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(0x00000000); 2186c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ADVANCE_RING(); 2187c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher COMMIT_RING(); 2188c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2189c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* set the mux and reset the halt bit */ 2190c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cp_me = 0xff; 2191c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_CNTL, cp_me); 2192c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2193c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_running = 1; 2194c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2195c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 2196c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2197c05ce0834a268f7d18274847190f6ed826b99332Alex Deuchervoid r600_do_cp_reset(drm_radeon_private_t *dev_priv) 2198c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 2199c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cur_read_ptr; 2200c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("\n"); 2201c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2202c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR); 2203c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr); 2204c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher SET_RING_HEAD(dev_priv, cur_read_ptr); 2205c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.tail = cur_read_ptr; 2206c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 2207c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2208c05ce0834a268f7d18274847190f6ed826b99332Alex Deuchervoid r600_do_cp_stop(drm_radeon_private_t *dev_priv) 2209c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 2210c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher uint32_t cp_me; 2211c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2212c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("\n"); 2213c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2214c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cp_me = 0xff | R600_CP_ME_HALT; 2215c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2216c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_CNTL, cp_me); 2217c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2218c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_running = 0; 2219c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 2220c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2221c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherint r600_cp_dispatch_indirect(struct drm_device *dev, 2222c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_buf *buf, int start, int end) 2223c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 2224c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 2225c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RING_LOCALS; 2226c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2227c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (start != end) { 2228c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher unsigned long offset = (dev_priv->gart_buffers_offset 2229c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + buf->offset + start); 2230c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int dwords = (end - start + 3) / sizeof(u32); 2231c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2232c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("dwords:%d\n", dwords); 2233c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("offset 0x%lx\n", offset); 2234c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2235c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2236c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Indirect buffer data must be a multiple of 16 dwords. 2237c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * pad the data with a Type-2 CP packet. 2238c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 2239c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher while (dwords & 0xf) { 2240c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 *data = (u32 *) 2241c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((char *)dev->agp_buffer_map->handle 2242c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + buf->offset + start); 2243c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher data[dwords++] = RADEON_CP_PACKET2; 2244c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2245c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2246c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Fire off the indirect buffer */ 2247c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher BEGIN_RING(4); 2248c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2)); 2249c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING((offset & 0xfffffffc)); 2250c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING((upper_32_bits(offset) & 0xff)); 2251c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(dwords); 2252c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ADVANCE_RING(); 2253c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2254c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2255c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return 0; 2256c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 2257