r600_cp.c revision c05ce0834a268f7d18274847190f6ed826b99332
1c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher/* 2c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Copyright 2008-2009 Advanced Micro Devices, Inc. 3c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Copyright 2008 Red Hat Inc. 4c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * 5c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 6c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * copy of this software and associated documentation files (the "Software"), 7c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * to deal in the Software without restriction, including without limitation 8c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * and/or sell copies of the Software, and to permit persons to whom the 10c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Software is furnished to do so, subject to the following conditions: 11c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * 12c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * The above copyright notice and this permission notice (including the next 13c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * paragraph) shall be included in all copies or substantial portions of the 14c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Software. 15c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * 16c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * DEALINGS IN THE SOFTWARE. 23c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * 24c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Authors: 25c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Dave Airlie <airlied@redhat.com> 26c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Alex Deucher <alexander.deucher@amd.com> 27c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 28c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 29c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#include "drmP.h" 30c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#include "drm.h" 31c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#include "radeon_drm.h" 32c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#include "radeon_drv.h" 33c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 34c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#include "r600_microcode.h" 35c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 36c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ 37c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher# define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1)) 38c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 39c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R600_PTE_VALID (1 << 0) 40c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R600_PTE_SYSTEM (1 << 1) 41c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R600_PTE_SNOOPED (1 << 2) 42c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R600_PTE_READABLE (1 << 5) 43c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R600_PTE_WRITEABLE (1 << 6) 44c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 45c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher/* MAX values used for gfx init */ 46c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_SH_GPRS 256 47c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_TEMP_GPRS 16 48c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_SH_THREADS 256 49c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_SH_STACK_ENTRIES 4096 50c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_BACKENDS 8 51c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_BACKENDS_MASK 0xff 52c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_SIMDS 8 53c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_SIMDS_MASK 0xff 54c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_PIPES 8 55c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_PIPES_MASK 0xff 56c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 57c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_SH_GPRS 256 58c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_TEMP_GPRS 16 59c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_SH_THREADS 256 60c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_SH_STACK_ENTRIES 4096 61c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_BACKENDS 8 62c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_BACKENDS_MASK 0xff 63c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_SIMDS 16 64c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_SIMDS_MASK 0xffff 65c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_PIPES 8 66c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_PIPES_MASK 0xff 67c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 68c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries) 69c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 70c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i; 71c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 72c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 73c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 74c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < dev_priv->usec_timeout; i++) { 75c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int slots; 76c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 77c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher slots = (RADEON_READ(R600_GRBM_STATUS) 78c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher & R700_CMDFIFO_AVAIL_MASK); 79c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 80c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher slots = (RADEON_READ(R600_GRBM_STATUS) 81c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher & R600_CMDFIFO_AVAIL_MASK); 82c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (slots >= entries) 83c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return 0; 84c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(1); 85c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 86c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n", 87c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_STATUS), 88c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_STATUS2)); 89c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 90c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EBUSY; 91c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 92c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 93c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv) 94c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 95c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i, ret; 96c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 97c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 98c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 99c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 100c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ret = r600_do_wait_for_fifo(dev_priv, 8); 101c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 102c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ret = r600_do_wait_for_fifo(dev_priv, 16); 103c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (ret) 104c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return ret; 105c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < dev_priv->usec_timeout; i++) { 106c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE)) 107c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return 0; 108c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(1); 109c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 110c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n", 111c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_STATUS), 112c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_STATUS2)); 113c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 114c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EBUSY; 115c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 116c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 117c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info) 118c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 119c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_sg_mem *entry = dev->sg; 120c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int max_pages; 121c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int pages; 122c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i; 123c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 124c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (gart_info->bus_addr) { 125c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher max_pages = (gart_info->table_size / sizeof(u32)); 126c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher pages = (entry->pages <= max_pages) 127c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ? entry->pages : max_pages; 128c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 129c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < pages; i++) { 130c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!entry->busaddr[i]) 131c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 132c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher pci_unmap_single(dev->pdev, entry->busaddr[i], 133c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher PAGE_SIZE, PCI_DMA_TODEVICE); 134c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 135c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) 136c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gart_info->bus_addr = 0; 137c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 138c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 139c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 140c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher/* R600 has page table setup */ 141c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherint r600_page_table_init(struct drm_device *dev) 142c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 143c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 144c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info; 145c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_sg_mem *entry = dev->sg; 146c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int ret = 0; 147c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i, j; 148c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int max_pages, pages; 149c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u64 *pci_gart, page_base; 150c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dma_addr_t entry_addr; 151c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 152c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* okay page table is available - lets rock */ 153c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 154c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* PTEs are 64-bits */ 155c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher pci_gart = (u64 *)gart_info->addr; 156c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 157c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher max_pages = (gart_info->table_size / sizeof(u64)); 158c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher pages = (entry->pages <= max_pages) ? entry->pages : max_pages; 159c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 160c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher memset(pci_gart, 0, max_pages * sizeof(u64)); 161c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 162c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < pages; i++) { 163c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher entry->busaddr[i] = pci_map_single(dev->pdev, 164c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher page_address(entry-> 165c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher pagelist[i]), 166c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher PAGE_SIZE, PCI_DMA_TODEVICE); 167c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (entry->busaddr[i] == 0) { 168c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("unable to map PCIGART pages!\n"); 169c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_page_table_cleanup(dev, gart_info); 170c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ret = -EINVAL; 171c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher goto done; 172c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 173c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher entry_addr = entry->busaddr[i]; 174c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) { 175c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK; 176c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; 177c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE; 178c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 179c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher *pci_gart = page_base; 180c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 181c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((i % 128) == 0) 182c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("page entry %d: 0x%016llx\n", 183c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher i, (unsigned long long)page_base); 184c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher pci_gart++; 185c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher entry_addr += ATI_PCIGART_PAGE_SIZE; 186c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 187c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 188c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherdone: 189c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return ret; 190c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 191c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 192c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r600_vm_flush_gart_range(struct drm_device *dev) 193c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 194c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 195c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 resp, countdown = 1000; 196c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12); 197c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 198c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2); 199c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 200c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher do { 201c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE); 202c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher countdown--; 203c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(1); 204c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } while (((resp & 0xf0) == 0) && countdown); 205c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 206c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 207c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r600_vm_init(struct drm_device *dev) 208c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 209c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 210c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* initialise the VM to use the page table we constructed up there */ 211c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 vm_c0, i; 212c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 mc_rd_a; 213c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 vm_l2_cntl, vm_l2_cntl3; 214c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* okay set up the PCIE aperture type thingo */ 215c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); 216c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 217c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 218c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 219c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* setup MC RD a */ 220c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS | 221c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) | 222c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY; 223c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 224c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a); 225c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a); 226c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 227c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a); 228c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a); 229c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 230c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a); 231c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a); 232c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 233c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a); 234c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a); 235c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 236c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING); 237c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/); 238c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 239c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a); 240c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a); 241c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 242c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE); 243c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a); 244c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 245c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W; 246c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7); 247c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl); 248c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 249c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_L2_CNTL2, 0); 250c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) | 251c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VM_L2_CNTL3_BANK_SELECT_1(1) | 252c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2)); 253c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3); 254c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 255c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT; 256c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 257c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0); 258c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 259c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_c0 &= ~R600_VM_ENABLE_CONTEXT; 260c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 261c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* disable all other contexts */ 262c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 1; i < 8; i++) 263c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0); 264c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 265c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); 266c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); 267c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 268c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 269c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_vm_flush_gart_range(dev); 270c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 271c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 272c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher/* load r600 microcode */ 273c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r600_cp_load_microcode(drm_radeon_private_t *dev_priv) 274c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 275c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i; 276c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 277c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cp_stop(dev_priv); 278c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 279c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 280c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_RB_NO_UPDATE | 281c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_RB_BLKSZ(15) | 282c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_RB_BUFSZ(3)); 283c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 284c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 285c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_SOFT_RESET); 286c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(15000); 287c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 288c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 289c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 290c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 291c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600)) { 292c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading R600 CP Microcode\n"); 293c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < PM4_UCODE_SIZE; i++) { 294c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 295c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_cp_microcode[i][0]); 296c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 297c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_cp_microcode[i][1]); 298c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 299c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_cp_microcode[i][2]); 300c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 301c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 302c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 303c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading R600 PFP Microcode\n"); 304c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < PFP_UCODE_SIZE; i++) 305c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_DATA, R600_pfp_microcode[i]); 306c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610)) { 307c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV610 CP Microcode\n"); 308c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < PM4_UCODE_SIZE; i++) { 309c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 310c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV610_cp_microcode[i][0]); 311c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 312c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV610_cp_microcode[i][1]); 313c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 314c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV610_cp_microcode[i][2]); 315c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 316c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 317c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 318c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV610 PFP Microcode\n"); 319c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < PFP_UCODE_SIZE; i++) 320c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV610_pfp_microcode[i]); 321c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) { 322c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV630 CP Microcode\n"); 323c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < PM4_UCODE_SIZE; i++) { 324c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 325c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV630_cp_microcode[i][0]); 326c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 327c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV630_cp_microcode[i][1]); 328c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 329c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV630_cp_microcode[i][2]); 330c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 331c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 332c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 333c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV630 PFP Microcode\n"); 334c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < PFP_UCODE_SIZE; i++) 335c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV630_pfp_microcode[i]); 336c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620)) { 337c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV620 CP Microcode\n"); 338c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < PM4_UCODE_SIZE; i++) { 339c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 340c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV620_cp_microcode[i][0]); 341c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 342c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV620_cp_microcode[i][1]); 343c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 344c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV620_cp_microcode[i][2]); 345c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 346c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 347c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 348c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV620 PFP Microcode\n"); 349c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < PFP_UCODE_SIZE; i++) 350c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV620_pfp_microcode[i]); 351c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) { 352c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV635 CP Microcode\n"); 353c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < PM4_UCODE_SIZE; i++) { 354c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 355c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV635_cp_microcode[i][0]); 356c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 357c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV635_cp_microcode[i][1]); 358c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 359c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV635_cp_microcode[i][2]); 360c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 361c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 362c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 363c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV635 PFP Microcode\n"); 364c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < PFP_UCODE_SIZE; i++) 365c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV635_pfp_microcode[i]); 366c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)) { 367c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV670 CP Microcode\n"); 368c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < PM4_UCODE_SIZE; i++) { 369c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 370c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV670_cp_microcode[i][0]); 371c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 372c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV670_cp_microcode[i][1]); 373c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 374c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV670_cp_microcode[i][2]); 375c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 376c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 377c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 378c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV670 PFP Microcode\n"); 379c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < PFP_UCODE_SIZE; i++) 380c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV670_pfp_microcode[i]); 381c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) { 382c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RS780 CP Microcode\n"); 383c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < PM4_UCODE_SIZE; i++) { 384c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 385c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV670_cp_microcode[i][0]); 386c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 387c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV670_cp_microcode[i][1]); 388c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, 389c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RV670_cp_microcode[i][2]); 390c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 391c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 392c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 393c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RS780 PFP Microcode\n"); 394c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < PFP_UCODE_SIZE; i++) 395c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV670_pfp_microcode[i]); 396c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 397c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 398c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 399c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); 400c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 401c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 402c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 403c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r700_vm_init(struct drm_device *dev) 404c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 405c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 406c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* initialise the VM to use the page table we constructed up there */ 407c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 vm_c0, i; 408c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 mc_vm_md_l1; 409c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 vm_l2_cntl, vm_l2_cntl3; 410c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* okay set up the PCIE aperture type thingo */ 411c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); 412c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 413c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 414c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 415c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher mc_vm_md_l1 = R700_ENABLE_L1_TLB | 416c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_ENABLE_L1_FRAGMENT_PROCESSING | 417c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SYSTEM_ACCESS_MODE_IN_SYS | 418c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 419c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_EFFECTIVE_L1_TLB_SIZE(5) | 420c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_EFFECTIVE_L1_QUEUE_SIZE(5); 421c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 422c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1); 423c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1); 424c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1); 425c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1); 426c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1); 427c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1); 428c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1); 429c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 430c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W; 431c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7); 432c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl); 433c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 434c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_L2_CNTL2, 0); 435c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2); 436c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3); 437c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 438c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT; 439c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 440c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0); 441c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 442c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_c0 &= ~R600_VM_ENABLE_CONTEXT; 443c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 444c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* disable all other contexts */ 445c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 1; i < 8; i++) 446c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0); 447c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 448c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); 449c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); 450c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 451c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 452c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_vm_flush_gart_range(dev); 453c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 454c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 455c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher/* load r600 microcode */ 456c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r700_cp_load_microcode(drm_radeon_private_t *dev_priv) 457c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 458c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i; 459c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 460c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cp_stop(dev_priv); 461c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 462c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 463c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_RB_NO_UPDATE | 464c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (15 << 8) | 465c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (3 << 0)); 466c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 467c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 468c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_SOFT_RESET); 469c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(15000); 470c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 471c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 472c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 473c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)) { 474c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 475c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV770 PFP Microcode\n"); 476c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < R700_PFP_UCODE_SIZE; i++) 477c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV770_pfp_microcode[i]); 478c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 479c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 480c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 481c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV770 CP Microcode\n"); 482c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < R700_PM4_UCODE_SIZE; i++) 483c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, RV770_cp_microcode[i]); 484c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 485c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 486c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV730)) { 487c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 488c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV730 PFP Microcode\n"); 489c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < R700_PFP_UCODE_SIZE; i++) 490c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV730_pfp_microcode[i]); 491c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 492c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 493c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 494c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV730 CP Microcode\n"); 495c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < R700_PM4_UCODE_SIZE; i++) 496c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, RV730_cp_microcode[i]); 497c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 498c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 499c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)) { 500c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 501c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV710 PFP Microcode\n"); 502c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < R700_PFP_UCODE_SIZE; i++) 503c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV710_pfp_microcode[i]); 504c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 505c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 506c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 507c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Loading RV710 CP Microcode\n"); 508c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < R700_PM4_UCODE_SIZE; i++) 509c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_DATA, RV710_cp_microcode[i]); 510c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 511c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 512c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 513c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 514c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 515c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); 516c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 517c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 518c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 519c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r600_test_writeback(drm_radeon_private_t *dev_priv) 520c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 521c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 tmp; 522c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 523c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Start with assuming that writeback doesn't work */ 524c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->writeback_works = 0; 525c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 526c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Writeback doesn't seem to work everywhere, test it here and possibly 527c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * enable it if it appears to work 528c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 529c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0); 530c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 531c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef); 532c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 533c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { 534c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 val; 535c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 536c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1)); 537c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (val == 0xdeadbeef) 538c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 539c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(1); 540c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 541c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 542c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (tmp < dev_priv->usec_timeout) { 543c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->writeback_works = 1; 544c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("writeback test succeeded in %d usecs\n", tmp); 545c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else { 546c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->writeback_works = 0; 547c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("writeback test failed\n"); 548c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 549c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (radeon_no_wb == 1) { 550c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->writeback_works = 0; 551c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("writeback forced off\n"); 552c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 553c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 554c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev_priv->writeback_works) { 555c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Disable writeback to avoid unnecessary bus master transfer */ 556c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, RADEON_READ(R600_CP_RB_CNTL) | 557c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_RB_NO_UPDATE); 558c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SCRATCH_UMSK, 0); 559c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 560c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 561c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 562c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherint r600_do_engine_reset(struct drm_device *dev) 563c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 564c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 565c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cp_ptr, cp_me_cntl, cp_rb_cntl; 566c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 567c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Resetting GPU\n"); 568c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 569c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cp_ptr = RADEON_READ(R600_CP_RB_WPTR); 570c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL); 571c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT); 572c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 573c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff); 574c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_SOFT_RESET); 575c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(50); 576c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 577c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_SOFT_RESET); 578c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 579c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); 580c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL); 581c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, R600_RB_RPTR_WR_ENA); 582c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 583c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr); 584c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr); 585c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl); 586c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl); 587c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 588c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Reset the CP ring */ 589c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cp_reset(dev_priv); 590c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 591c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* The CP is no longer running after an engine reset */ 592c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_running = 0; 593c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 594c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Reset any pending vertex, indirect buffers */ 595c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_freelist_reset(dev); 596c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 597c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return 0; 598c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 599c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 600c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 601c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes, 602c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 num_backends, 603c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 backend_disable_mask) 604c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 605c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 backend_map = 0; 606c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 enabled_backends_mask; 607c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 enabled_backends_count; 608c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cur_pipe; 609c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 swizzle_pipe[R6XX_MAX_PIPES]; 610c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cur_backend; 611c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 i; 612c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 613c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_tile_pipes > R6XX_MAX_PIPES) 614c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_tile_pipes = R6XX_MAX_PIPES; 615c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_tile_pipes < 1) 616c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_tile_pipes = 1; 617c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_backends > R6XX_MAX_BACKENDS) 618c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_backends = R6XX_MAX_BACKENDS; 619c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_backends < 1) 620c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_backends = 1; 621c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 622c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_mask = 0; 623c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_count = 0; 624c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < R6XX_MAX_BACKENDS; ++i) { 625c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((backend_disable_mask >> i) & 1) == 0) { 626c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_mask |= (1 << i); 627c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ++enabled_backends_count; 628c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 629c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (enabled_backends_count == num_backends) 630c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 631c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 632c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 633c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (enabled_backends_count == 0) { 634c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_mask = 1; 635c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_count = 1; 636c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 637c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 638c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (enabled_backends_count != num_backends) 639c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_backends = enabled_backends_count; 640c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 641c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES); 642c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (num_tile_pipes) { 643c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 1: 644c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 645c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 646c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 2: 647c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 648c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 1; 649c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 650c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 3: 651c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 652c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 1; 653c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 2; 654c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 655c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 4: 656c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 657c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 1; 658c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 2; 659c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 3; 660c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 661c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 5: 662c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 663c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 1; 664c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 2; 665c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 3; 666c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[4] = 4; 667c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 668c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 6: 669c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 670c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 2; 671c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 4; 672c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 5; 673c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[4] = 1; 674c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[5] = 3; 675c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 676c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 7: 677c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 678c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 2; 679c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 4; 680c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 6; 681c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[4] = 1; 682c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[5] = 3; 683c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[6] = 5; 684c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 685c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 8: 686c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 687c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 2; 688c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 4; 689c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 6; 690c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[4] = 1; 691c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[5] = 3; 692c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[6] = 5; 693c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[7] = 7; 694c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 695c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 696c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 697c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cur_backend = 0; 698c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 699c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher while (((1 << cur_backend) & enabled_backends_mask) == 0) 700c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; 701c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 702c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 703c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 704c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; 705c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 706c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 707c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return backend_map; 708c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 709c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 710c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic int r600_count_pipe_bits(uint32_t val) 711c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 712c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i, ret = 0; 713c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < 32; i++) { 714c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ret += val & 1; 715c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher val >>= 1; 716c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 717c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return ret; 718c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 719c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 720c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r600_gfx_init(struct drm_device *dev, 721c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv) 722c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 723c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i, j, num_qd_pipes; 724c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sx_debug_1; 725c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 tc_cntl; 726c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 arb_pop; 727c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 num_gs_verts_per_thread; 728c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 vgt_gs_per_es; 729c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 gs_prim_buffer_depth = 0; 730c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_ms_fifo_sizes; 731c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_config; 732c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_gpr_resource_mgmt_1 = 0; 733c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_gpr_resource_mgmt_2 = 0; 734c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_thread_resource_mgmt = 0; 735c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_stack_resource_mgmt_1 = 0; 736c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_stack_resource_mgmt_2 = 0; 737c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 hdp_host_path_cntl; 738c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 backend_map; 739c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 gb_tiling_config = 0; 740c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cc_rb_backend_disable = 0; 741c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cc_gc_shader_pipe_config = 0; 742c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 ramcfg; 743c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 744c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* setup chip specs */ 745c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->flags & RADEON_FAMILY_MASK) { 746c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_R600: 747c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_pipes = 4; 748c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_tile_pipes = 8; 749c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_simds = 4; 750c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends = 4; 751c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gprs = 256; 752c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_threads = 192; 753c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_stack_entries = 256; 754c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_hw_contexts = 8; 755c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gs_threads = 16; 756c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_size = 128; 757c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_pos_size = 16; 758c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_smx_size = 128; 759c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sq_num_cf_insts = 2; 760c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 761c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV630: 762c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV635: 763c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_pipes = 2; 764c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_tile_pipes = 2; 765c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_simds = 3; 766c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends = 1; 767c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gprs = 128; 768c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_threads = 192; 769c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_stack_entries = 128; 770c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_hw_contexts = 8; 771c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gs_threads = 4; 772c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_size = 128; 773c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_pos_size = 16; 774c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_smx_size = 128; 775c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sq_num_cf_insts = 2; 776c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 777c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV610: 778c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RS780: 779c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV620: 780c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_pipes = 1; 781c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_tile_pipes = 1; 782c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_simds = 2; 783c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends = 1; 784c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gprs = 128; 785c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_threads = 192; 786c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_stack_entries = 128; 787c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_hw_contexts = 4; 788c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gs_threads = 4; 789c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_size = 128; 790c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_pos_size = 16; 791c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_smx_size = 128; 792c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sq_num_cf_insts = 1; 793c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 794c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV670: 795c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_pipes = 4; 796c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_tile_pipes = 4; 797c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_simds = 4; 798c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends = 4; 799c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gprs = 192; 800c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_threads = 192; 801c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_stack_entries = 256; 802c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_hw_contexts = 8; 803c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gs_threads = 16; 804c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_size = 128; 805c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_pos_size = 16; 806c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_smx_size = 128; 807c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sq_num_cf_insts = 2; 808c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 809c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 810c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 811c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 812c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 813c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Initialize HDP */ 814c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher j = 0; 815c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < 32; i++) { 816c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c14 + j), 0x00000000); 817c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c18 + j), 0x00000000); 818c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c1c + j), 0x00000000); 819c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c20 + j), 0x00000000); 820c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c24 + j), 0x00000000); 821c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher j += 0x18; 822c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 823c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 824c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff)); 825c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 826c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* setup tiling, simd, pipe config */ 827c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ramcfg = RADEON_READ(R600_RAMCFG); 828c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 829c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->r600_max_tile_pipes) { 830c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 1: 831c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(0); 832c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 833c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 2: 834c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(1); 835c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 836c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 4: 837c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(2); 838c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 839c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 8: 840c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(3); 841c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 842c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 843c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 844c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 845c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 846c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK); 847c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 848c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_GROUP_SIZE(0); 849c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 850c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) { 851c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_ROW_TILING(3); 852c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_SAMPLE_SPLIT(3); 853c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else { 854c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= 855c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK)); 856c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= 857c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK)); 858c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 859c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 860c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_BANK_SWAPS(1); 861c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 862c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes, 863c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends, 864c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (0xff << dev_priv->r600_max_backends) & 0xff); 865c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_BACKEND_MAP(backend_map); 866c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 867c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cc_gc_shader_pipe_config = 868c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK); 869c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cc_gc_shader_pipe_config |= 870c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK); 871c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 872c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cc_rb_backend_disable = 873c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK); 874c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 875c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); 876c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 877c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 878c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 879c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 880c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 881c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 882c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 883c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_qd_pipes = 884c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R6XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK); 885c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK); 886c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK); 887c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 888c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* set HW defaults for 3D engine */ 889c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) | 890c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ROQ_IB2_START(0x2b))); 891c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 892c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) | 893c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ROQ_END(0x40))); 894c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 895c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO | 896c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SYNC_GRADIENT | 897c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SYNC_WALKER | 898c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SYNC_ALIGNER)); 899c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 900c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) 901c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021); 902c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 903c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1); 904c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sx_debug_1 |= R600_SMX_EVENT_RELEASE; 905c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600)) 906c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS; 907c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1); 908c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 909c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || 910c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || 911c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 912c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 913c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) 914c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE); 915c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 916c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_DB_DEBUG, 0); 917c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 918c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) | 919c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_DEPTH_FLUSH(16) | 920c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_DEPTH_PENDING_FREE(4) | 921c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_DEPTH_CACHELINE_FREE(16))); 922c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 923c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0); 924c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 925c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0)); 926c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0)); 927c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 928c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES); 929c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 930c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 931c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) { 932c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) | 933c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_FETCH_FIFO_HIWATER(0xa) | 934c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_DONE_FIFO_HIWATER(0xe0) | 935c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ALU_UPDATE_FIFO_HIWATER(0x8)); 936c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || 937c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) { 938c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff); 939c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4); 940c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 941c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 942c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 943c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 944c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * should be adjusted as needed by the 2D/3D drivers. This just sets default values 945c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 946c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config = RADEON_READ(R600_SQ_CONFIG); 947c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config &= ~(R600_PS_PRIO(3) | 948c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VS_PRIO(3) | 949c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_GS_PRIO(3) | 950c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ES_PRIO(3)); 951c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config |= (R600_DX9_CONSTS | 952c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VC_ENABLE | 953c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_PS_PRIO(0) | 954c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VS_PRIO(1) | 955c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_GS_PRIO(2) | 956c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ES_PRIO(3)); 957c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 958c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) { 959c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) | 960c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_GPRS(124) | 961c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_CLAUSE_TEMP_GPRS(4)); 962c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) | 963c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_GPRS(0)); 964c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) | 965c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_THREADS(48) | 966c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_GS_THREADS(4) | 967c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_THREADS(4)); 968c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) | 969c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_STACK_ENTRIES(128)); 970c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) | 971c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_STACK_ENTRIES(0)); 972c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 973c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 974c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) { 975c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* no vertex cache */ 976c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config &= ~R600_VC_ENABLE; 977c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 978c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 979c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_GPRS(44) | 980c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_CLAUSE_TEMP_GPRS(2)); 981c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) | 982c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_GPRS(17)); 983c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 984c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_THREADS(78) | 985c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_GS_THREADS(4) | 986c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_THREADS(31)); 987c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) | 988c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_STACK_ENTRIES(40)); 989c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) | 990c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_STACK_ENTRIES(16)); 991c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || 992c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) { 993c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 994c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_GPRS(44) | 995c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_CLAUSE_TEMP_GPRS(2)); 996c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) | 997c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_GPRS(18)); 998c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 999c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_THREADS(78) | 1000c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_GS_THREADS(4) | 1001c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_THREADS(31)); 1002c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) | 1003c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_STACK_ENTRIES(40)); 1004c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) | 1005c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_STACK_ENTRIES(16)); 1006c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) { 1007c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 1008c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_GPRS(44) | 1009c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_CLAUSE_TEMP_GPRS(2)); 1010c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) | 1011c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_GPRS(17)); 1012c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 1013c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_THREADS(78) | 1014c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_GS_THREADS(4) | 1015c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_THREADS(31)); 1016c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) | 1017c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_STACK_ENTRIES(64)); 1018c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) | 1019c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_STACK_ENTRIES(64)); 1020c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1021c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1022c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_CONFIG, sq_config); 1023c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 1024c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 1025c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1026c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 1027c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 1028c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1029c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 1030c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 1031c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) 1032c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY)); 1033c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 1034c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC)); 1035c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1036c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) | 1037c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S0_Y(0x4) | 1038c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S1_X(0x4) | 1039c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S1_Y(0xc))); 1040c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) | 1041c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S0_Y(0xe) | 1042c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S1_X(0x2) | 1043c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S1_Y(0x2) | 1044c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S2_X(0xa) | 1045c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S2_Y(0x6) | 1046c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S3_X(0x6) | 1047c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S3_Y(0xa))); 1048c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) | 1049c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S0_Y(0xb) | 1050c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S1_X(0x4) | 1051c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S1_Y(0xc) | 1052c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S2_X(0x1) | 1053c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S2_Y(0x6) | 1054c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S3_X(0xa) | 1055c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S3_Y(0xe))); 1056c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) | 1057c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S4_Y(0x1) | 1058c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S5_X(0x0) | 1059c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S5_Y(0x0) | 1060c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S6_X(0xb) | 1061c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S6_Y(0x4) | 1062c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S7_X(0x7) | 1063c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S7_Y(0x8))); 1064c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1065c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1066c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1067c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_R600: 1068c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV630: 1069c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV635: 1070c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gs_prim_buffer_depth = 0; 1071c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1072c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV610: 1073c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RS780: 1074c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV620: 1075c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gs_prim_buffer_depth = 32; 1076c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1077c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV670: 1078c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gs_prim_buffer_depth = 128; 1079c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1080c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 1081c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1082c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1083c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1084c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; 1085c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 1086c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Max value for this is 256 */ 1087c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (vgt_gs_per_es > 256) 1088c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vgt_gs_per_es = 256; 1089c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1090c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_ES_PER_GS, 128); 1091c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es); 1092c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_GS_PER_VS, 2); 1093c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16); 1094c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1095c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* more default values. 2D/3D driver should adjust as needed */ 1096c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0); 1097c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_STRMOUT_EN, 0); 1098c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SX_MISC, 0); 1099c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0); 1100c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0); 1101c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0); 1102c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_INPUT_Z, 0); 1103c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2)); 1104c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR7_FRAG, 0); 1105c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1106c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* clear render buffer base addresses */ 1107c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR0_BASE, 0); 1108c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR1_BASE, 0); 1109c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR2_BASE, 0); 1110c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR3_BASE, 0); 1111c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR4_BASE, 0); 1112c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR5_BASE, 0); 1113c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR6_BASE, 0); 1114c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR7_BASE, 0); 1115c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1116c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1117c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV610: 1118c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RS780: 1119c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV620: 1120c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher tc_cntl = R600_TC_L2_SIZE(8); 1121c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1122c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV630: 1123c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV635: 1124c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher tc_cntl = R600_TC_L2_SIZE(4); 1125c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1126c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_R600: 1127c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT; 1128c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1129c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 1130c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher tc_cntl = R600_TC_L2_SIZE(0); 1131c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1132c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1133c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1134c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_TC_CNTL, tc_cntl); 1135c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1136c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL); 1137c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1138c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1139c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher arb_pop = RADEON_READ(R600_ARB_POP); 1140c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher arb_pop |= R600_ENABLE_TC128; 1141c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_ARB_POP, arb_pop); 1142c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1143c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1144c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA | 1145c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_CLIP_SEQ(3))); 1146c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095)); 1147c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1148c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 1149c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1150c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes, 1151c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 num_backends, 1152c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 backend_disable_mask) 1153c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 1154c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 backend_map = 0; 1155c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 enabled_backends_mask; 1156c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 enabled_backends_count; 1157c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cur_pipe; 1158c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 swizzle_pipe[R7XX_MAX_PIPES]; 1159c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cur_backend; 1160c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 i; 1161c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1162c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_tile_pipes > R7XX_MAX_PIPES) 1163c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_tile_pipes = R7XX_MAX_PIPES; 1164c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_tile_pipes < 1) 1165c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_tile_pipes = 1; 1166c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_backends > R7XX_MAX_BACKENDS) 1167c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_backends = R7XX_MAX_BACKENDS; 1168c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_backends < 1) 1169c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_backends = 1; 1170c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1171c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_mask = 0; 1172c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_count = 0; 1173c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < R7XX_MAX_BACKENDS; ++i) { 1174c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((backend_disable_mask >> i) & 1) == 0) { 1175c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_mask |= (1 << i); 1176c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ++enabled_backends_count; 1177c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1178c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (enabled_backends_count == num_backends) 1179c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1180c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1181c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1182c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (enabled_backends_count == 0) { 1183c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_mask = 1; 1184c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_count = 1; 1185c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1186c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1187c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (enabled_backends_count != num_backends) 1188c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_backends = enabled_backends_count; 1189c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1190c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES); 1191c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (num_tile_pipes) { 1192c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 1: 1193c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 1194c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1195c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 2: 1196c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 1197c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 1; 1198c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1199c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 3: 1200c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 1201c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 2; 1202c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 1; 1203c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1204c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 4: 1205c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 1206c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 2; 1207c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 3; 1208c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 1; 1209c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1210c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 5: 1211c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 1212c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 2; 1213c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 4; 1214c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 1; 1215c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[4] = 3; 1216c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1217c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 6: 1218c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 1219c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 2; 1220c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 4; 1221c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 5; 1222c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[4] = 3; 1223c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[5] = 1; 1224c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1225c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 7: 1226c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 1227c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 2; 1228c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 4; 1229c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 6; 1230c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[4] = 3; 1231c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[5] = 1; 1232c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[6] = 5; 1233c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1234c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 8: 1235c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 1236c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 2; 1237c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 4; 1238c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 6; 1239c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[4] = 3; 1240c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[5] = 1; 1241c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[6] = 7; 1242c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[7] = 5; 1243c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1244c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1245c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1246c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cur_backend = 0; 1247c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 1248c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher while (((1 << cur_backend) & enabled_backends_mask) == 0) 1249c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 1250c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1251c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 1252c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1253c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 1254c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1255c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1256c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return backend_map; 1257c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 1258c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1259c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r700_gfx_init(struct drm_device *dev, 1260c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv) 1261c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 1262c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i, j, num_qd_pipes; 1263c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sx_debug_1; 1264c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 smx_dc_ctl0; 1265c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 num_gs_verts_per_thread; 1266c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 vgt_gs_per_es; 1267c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 gs_prim_buffer_depth = 0; 1268c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_ms_fifo_sizes; 1269c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_config; 1270c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_thread_resource_mgmt; 1271c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 hdp_host_path_cntl; 1272c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_dyn_gpr_size_simd_ab_0; 1273c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 backend_map; 1274c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 gb_tiling_config = 0; 1275c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cc_rb_backend_disable = 0; 1276c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cc_gc_shader_pipe_config = 0; 1277c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 mc_arb_ramcfg; 1278c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 db_debug4; 1279c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1280c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* setup chip specs */ 1281c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1282c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV770: 1283c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_pipes = 4; 1284c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_tile_pipes = 8; 1285c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_simds = 10; 1286c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends = 4; 1287c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gprs = 256; 1288c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_threads = 248; 1289c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_stack_entries = 512; 1290c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_hw_contexts = 8; 1291c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gs_threads = 16 * 2; 1292c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_size = 128; 1293c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_pos_size = 16; 1294c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_smx_size = 112; 1295c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sq_num_cf_insts = 2; 1296c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1297c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sx_num_of_sets = 7; 1298c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_prim_fifo_size = 0xF9; 1299c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1300c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1301c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1302c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV730: 1303c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_pipes = 2; 1304c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_tile_pipes = 4; 1305c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_simds = 8; 1306c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends = 2; 1307c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gprs = 128; 1308c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_threads = 248; 1309c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_stack_entries = 256; 1310c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_hw_contexts = 8; 1311c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gs_threads = 16 * 2; 1312c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_size = 256; 1313c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_pos_size = 32; 1314c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_smx_size = 224; 1315c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sq_num_cf_insts = 2; 1316c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1317c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sx_num_of_sets = 7; 1318c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_prim_fifo_size = 0xf9; 1319c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1320c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1321c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1322c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV710: 1323c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_pipes = 2; 1324c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_tile_pipes = 2; 1325c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_simds = 2; 1326c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends = 1; 1327c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gprs = 256; 1328c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_threads = 192; 1329c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_stack_entries = 256; 1330c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_hw_contexts = 4; 1331c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gs_threads = 8 * 2; 1332c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_size = 128; 1333c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_pos_size = 16; 1334c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_smx_size = 112; 1335c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sq_num_cf_insts = 1; 1336c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1337c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sx_num_of_sets = 7; 1338c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_prim_fifo_size = 0x40; 1339c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1340c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1341c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1342c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 1343c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1344c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1345c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1346c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Initialize HDP */ 1347c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher j = 0; 1348c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < 32; i++) { 1349c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c14 + j), 0x00000000); 1350c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c18 + j), 0x00000000); 1351c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c1c + j), 0x00000000); 1352c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c20 + j), 0x00000000); 1353c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c24 + j), 0x00000000); 1354c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher j += 0x18; 1355c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1356c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1357c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff)); 1358c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1359c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* setup tiling, simd, pipe config */ 1360c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG); 1361c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1362c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->r600_max_tile_pipes) { 1363c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 1: 1364c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(0); 1365c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1366c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 2: 1367c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(1); 1368c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1369c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 4: 1370c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(2); 1371c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1372c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 8: 1373c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(3); 1374c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1375c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 1376c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1377c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1378c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1379c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770) 1380c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_BANK_TILING(1); 1381c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 1382c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK); 1383c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1384c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_GROUP_SIZE(0); 1385c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1386c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) { 1387c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_ROW_TILING(3); 1388c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_SAMPLE_SPLIT(3); 1389c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else { 1390c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= 1391c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK)); 1392c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= 1393c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK)); 1394c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1395c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1396c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_BANK_SWAPS(1); 1397c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1398c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher backend_map = r700_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes, 1399c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends, 1400c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (0xff << dev_priv->r600_max_backends) & 0xff); 1401c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_BACKEND_MAP(backend_map); 1402c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1403c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cc_gc_shader_pipe_config = 1404c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK); 1405c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cc_gc_shader_pipe_config |= 1406c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK); 1407c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1408c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cc_rb_backend_disable = 1409c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK); 1410c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1411c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); 1412c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1413c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1414c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1415c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 1416c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 1417c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 1418c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1419c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); 1420c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0); 1421c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0); 1422c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0); 1423c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0); 1424c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1425c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_qd_pipes = 1426c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK); 1427c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK); 1428c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK); 1429c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1430c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* set HW defaults for 3D engine */ 1431c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) | 1432c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ROQ_IB2_START(0x2b))); 1433c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1434c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30)); 1435c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1436c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO | 1437c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SYNC_GRADIENT | 1438c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SYNC_WALKER | 1439c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SYNC_ALIGNER)); 1440c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1441c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1); 1442c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS; 1443c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1); 1444c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1445c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0); 1446c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff); 1447c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1); 1448c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0); 1449c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1450c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) | 1451c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_GS_FLUSH_CTL(4) | 1452c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_ACK_FLUSH_CTL(3) | 1453c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SYNC_FLUSH_CTL)); 1454c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1455c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770) 1456c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_DB_DEBUG3, R700_DB_CLK_OFF_DELAY(0x1f)); 1457c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else { 1458c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher db_debug4 = RADEON_READ(RV700_DB_DEBUG4); 1459c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER; 1460c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(RV700_DB_DEBUG4, db_debug4); 1461c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1462c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1463c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) | 1464c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) | 1465c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1))); 1466c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1467c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) | 1468c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) | 1469c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize))); 1470c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1471c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1472c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1473c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1); 1474c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1475c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0)); 1476c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1477c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4)); 1478c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1479c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PERFMON_CNTL, 0); 1480c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1481c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) | 1482c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_DONE_FIFO_HIWATER(0xe0) | 1483c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ALU_UPDATE_FIFO_HIWATER(0x8)); 1484c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1485c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV770: 1486c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1); 1487c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1488c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV730: 1489c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV710: 1490c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 1491c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4); 1492c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1493c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1494c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 1495c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1496c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 1497c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * should be adjusted as needed by the 2D/3D drivers. This just sets default values 1498c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 1499c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config = RADEON_READ(R600_SQ_CONFIG); 1500c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config &= ~(R600_PS_PRIO(3) | 1501c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VS_PRIO(3) | 1502c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_GS_PRIO(3) | 1503c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ES_PRIO(3)); 1504c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config |= (R600_DX9_CONSTS | 1505c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VC_ENABLE | 1506c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_EXPORT_SRC_C | 1507c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_PS_PRIO(0) | 1508c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VS_PRIO(1) | 1509c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_GS_PRIO(2) | 1510c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ES_PRIO(3)); 1511c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) 1512c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* no vertex cache */ 1513c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config &= ~R600_VC_ENABLE; 1514c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1515c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_CONFIG, sq_config); 1516c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1517c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) | 1518c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) | 1519c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2))); 1520c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1521c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) | 1522c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64))); 1523c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1524c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) | 1525c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) | 1526c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8)); 1527c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads) 1528c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads); 1529c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 1530c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8); 1531c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1532c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1533c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) | 1534c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); 1535c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1536c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) | 1537c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); 1538c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1539c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) | 1540c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) | 1541c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) | 1542c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64)); 1543c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1544c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); 1545c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); 1546c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); 1547c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); 1548c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); 1549c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); 1550c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); 1551c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); 1552c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1553c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) | 1554c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_FORCE_EOV_MAX_REZ_CNT(255))); 1555c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1556c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) 1557c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) | 1558c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO))); 1559c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 1560c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) | 1561c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO))); 1562c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1563c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1564c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV770: 1565c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV730: 1566c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gs_prim_buffer_depth = 384; 1567c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1568c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV710: 1569c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gs_prim_buffer_depth = 128; 1570c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1571c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 1572c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1573c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1574c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1575c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; 1576c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 1577c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Max value for this is 256 */ 1578c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (vgt_gs_per_es > 256) 1579c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vgt_gs_per_es = 256; 1580c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1581c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_ES_PER_GS, 128); 1582c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es); 1583c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_GS_PER_VS, 2); 1584c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1585c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* more default values. 2D/3D driver should adjust as needed */ 1586c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16); 1587c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0); 1588c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_STRMOUT_EN, 0); 1589c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SX_MISC, 0); 1590c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0); 1591c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa); 1592c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0); 1593c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff); 1594c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0); 1595c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_INPUT_Z, 0); 1596c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2)); 1597c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR7_FRAG, 0); 1598c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1599c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* clear render buffer base addresses */ 1600c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR0_BASE, 0); 1601c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR1_BASE, 0); 1602c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR2_BASE, 0); 1603c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR3_BASE, 0); 1604c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR4_BASE, 0); 1605c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR5_BASE, 0); 1606c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR6_BASE, 0); 1607c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR7_BASE, 0); 1608c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1609c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_TCP_CNTL, 0); 1610c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1611c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL); 1612c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1613c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1614c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1615c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1616c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA | 1617c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_CLIP_SEQ(3))); 1618c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1619c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 1620c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1621c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r600_cp_init_ring_buffer(struct drm_device *dev, 1622c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv, 1623c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_file *file_priv) 1624c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 1625c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_radeon_master_private *master_priv; 1626c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 ring_start; 1627c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1628c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 1629c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r700_gfx_init(dev, dev_priv); 1630c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 1631c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_gfx_init(dev, dev_priv); 1632c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1633c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 1634c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_SOFT_RESET); 1635c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(15000); 1636c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 1637c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1638c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1639c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Set ring buffer size */ 1640c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#ifdef __BIG_ENDIAN 1641c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 1642c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_BUF_SWAP_32BIT | 1643c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_RB_NO_UPDATE | 1644c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->ring.rptr_update_l2qw << 8) | 1645c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size_l2qw); 1646c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#else 1647c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 1648c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_RB_NO_UPDATE | 1649c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->ring.rptr_update_l2qw << 8) | 1650c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size_l2qw); 1651c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 1652c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1653c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x4); 1654c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1655c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Set the write pointer delay */ 1656c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); 1657c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1658c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#ifdef __BIG_ENDIAN 1659c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 1660c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_BUF_SWAP_32BIT | 1661c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_RB_NO_UPDATE | 1662c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_RB_RPTR_WR_ENA | 1663c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->ring.rptr_update_l2qw << 8) | 1664c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size_l2qw); 1665c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#else 1666c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 1667c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_RB_NO_UPDATE | 1668c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_RB_RPTR_WR_ENA | 1669c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->ring.rptr_update_l2qw << 8) | 1670c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size_l2qw); 1671c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 1672c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1673c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Initialize the ring buffer's read and write pointers */ 1674c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_RPTR_WR, 0); 1675c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_WPTR, 0); 1676c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher SET_RING_HEAD(dev_priv, 0); 1677c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.tail = 0; 1678c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1679c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#if __OS_HAS_AGP 1680c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->flags & RADEON_IS_AGP) { 1681c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* XXX */ 1682c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_RPTR_ADDR, 1683c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->ring_rptr->offset 1684c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher - dev->agp->base + dev_priv->gart_vm_start) >> 8); 1685c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI, 0); 1686c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else 1687c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 1688c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher { 1689c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_sg_mem *entry = dev->sg; 1690c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher unsigned long tmp_ofs, page_ofs; 1691c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1692c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher tmp_ofs = dev_priv->ring_rptr->offset - 1693c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (unsigned long)dev->sg->virtual; 1694c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher page_ofs = tmp_ofs >> PAGE_SHIFT; 1695c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1696c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs] >> 8); 1697c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI, 0); 1698c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n", 1699c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (unsigned long)entry->busaddr[page_ofs], 1700c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher entry->handle + tmp_ofs); 1701c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1702c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1703c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#ifdef __BIG_ENDIAN 1704c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 1705c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_BUF_SWAP_32BIT | 1706c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->ring.rptr_update_l2qw << 8) | 1707c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size_l2qw); 1708c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#else 1709c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 1710c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->ring.rptr_update_l2qw << 8) | 1711c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size_l2qw); 1712c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 1713c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1714c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#if __OS_HAS_AGP 1715c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->flags & RADEON_IS_AGP) { 1716c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* XXX */ 1717c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_write_agp_base(dev_priv, dev->agp->base); 1718c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1719c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* XXX */ 1720c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_write_agp_location(dev_priv, 1721c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (((dev_priv->gart_vm_start - 1 + 1722c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_size) & 0xffff0000) | 1723c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->gart_vm_start >> 16))); 1724c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1725c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ring_start = (dev_priv->cp_ring->offset 1726c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher - dev->agp->base 1727c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + dev_priv->gart_vm_start); 1728c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else 1729c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 1730c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ring_start = (dev_priv->cp_ring->offset 1731c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher - (unsigned long)dev->sg->virtual 1732c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + dev_priv->gart_vm_start); 1733c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1734c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8); 1735c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1736c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_CNTL, 0xff); 1737c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1738c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28)); 1739c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1740c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Start with assuming that writeback doesn't work */ 1741c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->writeback_works = 0; 1742c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1743c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Initialize the scratch register pointer. This will cause 1744c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * the scratch register values to be written out to memory 1745c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * whenever they are updated. 1746c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * 1747c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * We simply put this behind the ring read pointer, this works 1748c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * with PCI GART as well as (whatever kind of) AGP GART 1749c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 1750c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SCRATCH_ADDR, ((RADEON_READ(R600_CP_RB_RPTR_ADDR) << 8) 1751c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + R600_SCRATCH_REG_OFFSET) >> 8); 1752c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1753c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SCRATCH_UMSK, 0x7); 1754c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1755c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Turn on bus mastering */ 1756c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_enable_bm(dev_priv); 1757c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1758c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0); 1759c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_LAST_FRAME_REG, 0); 1760c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1761c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0); 1762c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_LAST_DISPATCH_REG, 0); 1763c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1764c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0); 1765c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_LAST_CLEAR_REG, 0); 1766c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1767c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* reset sarea copies of these */ 1768c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher master_priv = file_priv->master->driver_priv; 1769c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (master_priv->sarea_priv) { 1770c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher master_priv->sarea_priv->last_frame = 0; 1771c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher master_priv->sarea_priv->last_dispatch = 0; 1772c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher master_priv->sarea_priv->last_clear = 0; 1773c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1774c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1775c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_wait_for_idle(dev_priv); 1776c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1777c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 1778c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1779c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherint r600_do_cleanup_cp(struct drm_device *dev) 1780c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 1781c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 1782c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("\n"); 1783c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1784c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Make sure interrupts are disabled here because the uninstall ioctl 1785c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * may not have been called from userspace and after dev_private 1786c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * is freed, it's too late. 1787c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 1788c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev->irq_enabled) 1789c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_irq_uninstall(dev); 1790c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1791c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#if __OS_HAS_AGP 1792c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->flags & RADEON_IS_AGP) { 1793c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->cp_ring != NULL) { 1794c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_core_ioremapfree(dev_priv->cp_ring, dev); 1795c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_ring = NULL; 1796c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1797c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->ring_rptr != NULL) { 1798c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_core_ioremapfree(dev_priv->ring_rptr, dev); 1799c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring_rptr = NULL; 1800c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1801c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev->agp_buffer_map != NULL) { 1802c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_core_ioremapfree(dev->agp_buffer_map, dev); 1803c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev->agp_buffer_map = NULL; 1804c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1805c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else 1806c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 1807c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher { 1808c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1809c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->gart_info.bus_addr) 1810c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_page_table_cleanup(dev, &dev_priv->gart_info); 1811c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1812c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) { 1813c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); 1814c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.addr = 0; 1815c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1816c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1817c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* only clear to the start of flags */ 1818c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); 1819c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1820c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return 0; 1821c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 1822c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1823c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherint r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, 1824c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_file *file_priv) 1825c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 1826c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 1827c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; 1828c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1829c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("\n"); 1830c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1831c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* if we require new memory map but we don't have it fail */ 1832c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { 1833c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); 1834c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 1835c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 1836c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1837c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1838c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) { 1839c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("Forcing AGP card to PCI mode\n"); 1840c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->flags &= ~RADEON_IS_AGP; 1841c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* The writeback test succeeds, but when writeback is enabled, 1842c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * the ring buffer read ptr update fails after first 128 bytes. 1843c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 1844c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_no_wb = 1; 1845c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) 1846c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher && !init->is_pci) { 1847c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("Restoring AGP flag\n"); 1848c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->flags |= RADEON_IS_AGP; 1849c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1850c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1851c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->usec_timeout = init->usec_timeout; 1852c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->usec_timeout < 1 || 1853c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { 1854c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("TIMEOUT problem!\n"); 1855c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 1856c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 1857c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1858c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1859c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Enable vblank on CRTC1 for older X servers 1860c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 1861c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; 1862c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1863c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_mode = init->cp_mode; 1864c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1865c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* We don't support anything other than bus-mastering ring mode, 1866c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * but the ring can be in either AGP or PCI space for the ring 1867c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * read pointer. 1868c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 1869c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && 1870c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { 1871c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); 1872c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 1873c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 1874c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1875c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1876c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (init->fb_bpp) { 1877c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 16: 1878c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; 1879c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1880c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 32: 1881c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 1882c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; 1883c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1884c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1885c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->front_offset = init->front_offset; 1886c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->front_pitch = init->front_pitch; 1887c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->back_offset = init->back_offset; 1888c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->back_pitch = init->back_pitch; 1889c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1890c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring_offset = init->ring_offset; 1891c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring_rptr_offset = init->ring_rptr_offset; 1892c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->buffers_offset = init->buffers_offset; 1893c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_textures_offset = init->gart_textures_offset; 1894c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1895c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher master_priv->sarea = drm_getsarea(dev); 1896c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!master_priv->sarea) { 1897c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("could not find sarea!\n"); 1898c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 1899c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 1900c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1901c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1902c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); 1903c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev_priv->cp_ring) { 1904c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("could not find cp ring region!\n"); 1905c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 1906c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 1907c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1908c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); 1909c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev_priv->ring_rptr) { 1910c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("could not find ring read pointer!\n"); 1911c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 1912c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 1913c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1914c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev->agp_buffer_token = init->buffers_offset; 1915c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); 1916c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev->agp_buffer_map) { 1917c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("could not find dma buffer region!\n"); 1918c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 1919c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 1920c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1921c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1922c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (init->gart_textures_offset) { 1923c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_textures = 1924c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_core_findmap(dev, init->gart_textures_offset); 1925c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev_priv->gart_textures) { 1926c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("could not find GART texture region!\n"); 1927c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 1928c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 1929c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1930c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1931c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1932c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#if __OS_HAS_AGP 1933c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* XXX */ 1934c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->flags & RADEON_IS_AGP) { 1935c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_core_ioremap(dev_priv->cp_ring, dev); 1936c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_core_ioremap(dev_priv->ring_rptr, dev); 1937c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_core_ioremap(dev->agp_buffer_map, dev); 1938c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev_priv->cp_ring->handle || 1939c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher !dev_priv->ring_rptr->handle || 1940c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher !dev->agp_buffer_map->handle) { 1941c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("could not find ioremap agp regions!\n"); 1942c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 1943c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 1944c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1945c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else 1946c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 1947c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher { 1948c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset; 1949c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring_rptr->handle = 1950c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (void *)dev_priv->ring_rptr->offset; 1951c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev->agp_buffer_map->handle = 1952c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (void *)dev->agp_buffer_map->offset; 1953c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1954c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("dev_priv->cp_ring->handle %p\n", 1955c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_ring->handle); 1956c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", 1957c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring_rptr->handle); 1958c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("dev->agp_buffer_map->handle %p\n", 1959c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev->agp_buffer_map->handle); 1960c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1961c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1962c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24; 1963c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->fb_size = 1964c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000) 1965c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher - dev_priv->fb_location; 1966c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1967c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | 1968c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->front_offset 1969c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + dev_priv->fb_location) >> 10)); 1970c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1971c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | 1972c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->back_offset 1973c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + dev_priv->fb_location) >> 10)); 1974c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1975c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | 1976c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->depth_offset 1977c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + dev_priv->fb_location) >> 10)); 1978c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1979c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_size = init->gart_size; 1980c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1981c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* New let's set the memory map ... */ 1982c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->new_memmap) { 1983c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 base = 0; 1984c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1985c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Setting GART location based on new memory map\n"); 1986c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1987c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* If using AGP, try to locate the AGP aperture at the same 1988c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * location in the card and on the bus, though we have to 1989c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * align it down. 1990c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 1991c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#if __OS_HAS_AGP 1992c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* XXX */ 1993c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->flags & RADEON_IS_AGP) { 1994c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher base = dev->agp->base; 1995c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Check if valid */ 1996c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && 1997c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { 1998c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n", 1999c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev->agp->base); 2000c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher base = 0; 2001c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2002c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2003c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 2004c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* If not or if AGP is at 0 (Macs), try to put it elsewhere */ 2005c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (base == 0) { 2006c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher base = dev_priv->fb_location + dev_priv->fb_size; 2007c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (base < dev_priv->fb_location || 2008c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((base + dev_priv->gart_size) & 0xfffffffful) < base) 2009c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher base = dev_priv->fb_location 2010c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher - dev_priv->gart_size; 2011c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2012c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_vm_start = base & 0xffc00000u; 2013c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->gart_vm_start != base) 2014c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n", 2015c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher base, dev_priv->gart_vm_start); 2016c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2017c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2018c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#if __OS_HAS_AGP 2019c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* XXX */ 2020c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->flags & RADEON_IS_AGP) 2021c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 2022c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher - dev->agp->base 2023c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + dev_priv->gart_vm_start); 2024c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 2025c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 2026c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 2027c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher - (unsigned long)dev->sg->virtual 2028c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + dev_priv->gart_vm_start); 2029c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2030c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("fb 0x%08x size %d\n", 2031c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (unsigned int) dev_priv->fb_location, 2032c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (unsigned int) dev_priv->fb_size); 2033c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); 2034c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n", 2035c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (unsigned int) dev_priv->gart_vm_start); 2036c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n", 2037c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_buffers_offset); 2038c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2039c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; 2040c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle 2041c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + init->ring_size / sizeof(u32)); 2042c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size = init->ring_size; 2043c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); 2044c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2045c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; 2046c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8); 2047c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2048c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.fetch_size = /* init->fetch_size */ 32; 2049c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16); 2050c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2051c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; 2052c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2053c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; 2054c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2055c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#if __OS_HAS_AGP 2056c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->flags & RADEON_IS_AGP) { 2057c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* XXX turn off pcie gart */ 2058c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else 2059c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 2060c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher { 2061c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); 2062c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* if we have an offset set from userspace */ 2063c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev_priv->pcigart_offset_set) { 2064c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("Need gart offset from userspace\n"); 2065c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2066c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2067c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2068c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2069c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset); 2070c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2071c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.bus_addr = 2072c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->pcigart_offset + dev_priv->fb_location; 2073c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.mapping.offset = 2074c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->pcigart_offset + dev_priv->fb_aper_offset; 2075c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.mapping.size = 2076c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.table_size; 2077c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2078c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev); 2079c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev_priv->gart_info.mapping.handle) { 2080c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("ioremap failed.\n"); 2081c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2082c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2083c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2084c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2085c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.addr = 2086c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.mapping.handle; 2087c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2088c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n", 2089c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.addr, 2090c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->pcigart_offset); 2091c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2092c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (r600_page_table_init(dev)) { 2093c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("Failed to init GART table\n"); 2094c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2095c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2096c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2097c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2098c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 2099c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r700_vm_init(dev); 2100c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 2101c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_vm_init(dev); 2102c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2103c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2104c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 2105c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r700_cp_load_microcode(dev_priv); 2106c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 2107c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_cp_load_microcode(dev_priv); 2108c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2109c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_cp_init_ring_buffer(dev, dev_priv, file_priv); 2110c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2111c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->last_buf = 0; 2112c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2113c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_engine_reset(dev); 2114c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_test_writeback(dev_priv); 2115c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2116c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return 0; 2117c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 2118c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2119c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherint r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv) 2120c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 2121c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 2122c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2123c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("\n"); 2124c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) { 2125c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r700_vm_init(dev); 2126c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r700_cp_load_microcode(dev_priv); 2127c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else { 2128c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_vm_init(dev); 2129c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_cp_load_microcode(dev_priv); 2130c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2131c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_cp_init_ring_buffer(dev, dev_priv, file_priv); 2132c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_engine_reset(dev); 2133c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2134c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return 0; 2135c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 2136c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2137c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher/* Wait for the CP to go idle. 2138c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 2139c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherint r600_do_cp_idle(drm_radeon_private_t *dev_priv) 2140c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 2141c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RING_LOCALS; 2142c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("\n"); 2143c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2144c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher BEGIN_RING(5); 2145c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); 2146c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT); 2147c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* wait for 3D idle clean */ 2148c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); 2149c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2); 2150c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN); 2151c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2152c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ADVANCE_RING(); 2153c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher COMMIT_RING(); 2154c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2155c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return r600_do_wait_for_idle(dev_priv); 2156c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 2157c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2158c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher/* Start the Command Processor. 2159c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 2160c05ce0834a268f7d18274847190f6ed826b99332Alex Deuchervoid r600_do_cp_start(drm_radeon_private_t *dev_priv) 2161c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 2162c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cp_me; 2163c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RING_LOCALS; 2164c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("\n"); 2165c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2166c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher BEGIN_RING(7); 2167c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5)); 2168c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(0x00000001); 2169c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) 2170c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(0x00000003); 2171c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 2172c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(0x00000000); 2173c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING((dev_priv->r600_max_hw_contexts - 1)); 2174c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1)); 2175c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(0x00000000); 2176c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(0x00000000); 2177c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ADVANCE_RING(); 2178c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher COMMIT_RING(); 2179c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2180c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* set the mux and reset the halt bit */ 2181c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cp_me = 0xff; 2182c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_CNTL, cp_me); 2183c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2184c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_running = 1; 2185c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2186c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 2187c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2188c05ce0834a268f7d18274847190f6ed826b99332Alex Deuchervoid r600_do_cp_reset(drm_radeon_private_t *dev_priv) 2189c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 2190c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cur_read_ptr; 2191c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("\n"); 2192c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2193c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR); 2194c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr); 2195c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher SET_RING_HEAD(dev_priv, cur_read_ptr); 2196c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.tail = cur_read_ptr; 2197c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 2198c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2199c05ce0834a268f7d18274847190f6ed826b99332Alex Deuchervoid r600_do_cp_stop(drm_radeon_private_t *dev_priv) 2200c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 2201c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher uint32_t cp_me; 2202c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2203c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("\n"); 2204c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2205c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cp_me = 0xff | R600_CP_ME_HALT; 2206c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2207c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_CNTL, cp_me); 2208c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2209c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_running = 0; 2210c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 2211c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2212c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherint r600_cp_dispatch_indirect(struct drm_device *dev, 2213c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_buf *buf, int start, int end) 2214c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 2215c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 2216c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RING_LOCALS; 2217c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2218c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (start != end) { 2219c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher unsigned long offset = (dev_priv->gart_buffers_offset 2220c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + buf->offset + start); 2221c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int dwords = (end - start + 3) / sizeof(u32); 2222c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2223c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("dwords:%d\n", dwords); 2224c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("offset 0x%lx\n", offset); 2225c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2226c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2227c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Indirect buffer data must be a multiple of 16 dwords. 2228c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * pad the data with a Type-2 CP packet. 2229c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 2230c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher while (dwords & 0xf) { 2231c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 *data = (u32 *) 2232c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((char *)dev->agp_buffer_map->handle 2233c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + buf->offset + start); 2234c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher data[dwords++] = RADEON_CP_PACKET2; 2235c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2236c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2237c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Fire off the indirect buffer */ 2238c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher BEGIN_RING(4); 2239c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2)); 2240c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING((offset & 0xfffffffc)); 2241c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING((upper_32_bits(offset) & 0xff)); 2242c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(dwords); 2243c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ADVANCE_RING(); 2244c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2245c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2246c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return 0; 2247c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 2248