r600_cp.c revision dee54c40a1a9898bcd156436a1d3524f530b5a90
1c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher/* 2c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Copyright 2008-2009 Advanced Micro Devices, Inc. 3c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Copyright 2008 Red Hat Inc. 4c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * 5c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 6c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * copy of this software and associated documentation files (the "Software"), 7c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * to deal in the Software without restriction, including without limitation 8c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * and/or sell copies of the Software, and to permit persons to whom the 10c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Software is furnished to do so, subject to the following conditions: 11c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * 12c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * The above copyright notice and this permission notice (including the next 13c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * paragraph) shall be included in all copies or substantial portions of the 14c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Software. 15c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * 16c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * DEALINGS IN THE SOFTWARE. 23c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * 24c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Authors: 25c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Dave Airlie <airlied@redhat.com> 26c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Alex Deucher <alexander.deucher@amd.com> 27c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 28c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 29c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#include "drmP.h" 30c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#include "drm.h" 31c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#include "radeon_drm.h" 32c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#include "radeon_drv.h" 33c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 3470967ab9c0c9017645d167d33675eab996633631Ben Hutchings#define PFP_UCODE_SIZE 576 3570967ab9c0c9017645d167d33675eab996633631Ben Hutchings#define PM4_UCODE_SIZE 1792 3670967ab9c0c9017645d167d33675eab996633631Ben Hutchings#define R700_PFP_UCODE_SIZE 848 3770967ab9c0c9017645d167d33675eab996633631Ben Hutchings#define R700_PM4_UCODE_SIZE 1360 3870967ab9c0c9017645d167d33675eab996633631Ben Hutchings 3970967ab9c0c9017645d167d33675eab996633631Ben Hutchings/* Firmware Names */ 4070967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/R600_pfp.bin"); 4170967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/R600_me.bin"); 4270967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV610_pfp.bin"); 4370967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV610_me.bin"); 4470967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV630_pfp.bin"); 4570967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV630_me.bin"); 4670967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV620_pfp.bin"); 4770967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV620_me.bin"); 4870967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV635_pfp.bin"); 4970967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV635_me.bin"); 5070967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV670_pfp.bin"); 5170967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV670_me.bin"); 5270967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RS780_pfp.bin"); 5370967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RS780_me.bin"); 5470967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV770_pfp.bin"); 5570967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV770_me.bin"); 5670967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV730_pfp.bin"); 5770967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV730_me.bin"); 5870967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV710_pfp.bin"); 5970967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV710_me.bin"); 60c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 613ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 623ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisseint r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp, 633ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse unsigned family, u32 *ib, int *l); 643ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glissevoid r600_cs_legacy_init(void); 653ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 663ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 67c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ 68c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher# define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1)) 69c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 70c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R600_PTE_VALID (1 << 0) 71c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R600_PTE_SYSTEM (1 << 1) 72c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R600_PTE_SNOOPED (1 << 2) 73c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R600_PTE_READABLE (1 << 5) 74c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R600_PTE_WRITEABLE (1 << 6) 75c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 76c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher/* MAX values used for gfx init */ 77c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_SH_GPRS 256 78c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_TEMP_GPRS 16 79c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_SH_THREADS 256 80c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_SH_STACK_ENTRIES 4096 81c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_BACKENDS 8 82c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_BACKENDS_MASK 0xff 83c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_SIMDS 8 84c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_SIMDS_MASK 0xff 85c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_PIPES 8 86c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_PIPES_MASK 0xff 87c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 88c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_SH_GPRS 256 89c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_TEMP_GPRS 16 90c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_SH_THREADS 256 91c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_SH_STACK_ENTRIES 4096 92c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_BACKENDS 8 93c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_BACKENDS_MASK 0xff 94c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_SIMDS 16 95c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_SIMDS_MASK 0xffff 96c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_PIPES 8 97c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_PIPES_MASK 0xff 98c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 99c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries) 100c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 101c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i; 102c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 103c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 104c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 105c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < dev_priv->usec_timeout; i++) { 106c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int slots; 107c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 108c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher slots = (RADEON_READ(R600_GRBM_STATUS) 109c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher & R700_CMDFIFO_AVAIL_MASK); 110c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 111c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher slots = (RADEON_READ(R600_GRBM_STATUS) 112c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher & R600_CMDFIFO_AVAIL_MASK); 113c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (slots >= entries) 114c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return 0; 115c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(1); 116c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 117c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n", 118c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_STATUS), 119c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_STATUS2)); 120c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 121c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EBUSY; 122c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 123c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 124c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv) 125c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 126c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i, ret; 127c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 128c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 129c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 130c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 131c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ret = r600_do_wait_for_fifo(dev_priv, 8); 132c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 133c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ret = r600_do_wait_for_fifo(dev_priv, 16); 134c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (ret) 135c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return ret; 136c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < dev_priv->usec_timeout; i++) { 137c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE)) 138c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return 0; 139c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(1); 140c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 141c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n", 142c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_STATUS), 143c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_STATUS2)); 144c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 145c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EBUSY; 146c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 147c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 148c1556f71513f2e660fb2bbdc29344361b1ebff35Alex Deuchervoid r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info) 149c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 150c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_sg_mem *entry = dev->sg; 151c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int max_pages; 152c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int pages; 153c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i; 154c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 15508932156cc2d4f8807dc5ca5c3d6ccd85080610aAlex Deucher if (!entry) 15608932156cc2d4f8807dc5ca5c3d6ccd85080610aAlex Deucher return; 15708932156cc2d4f8807dc5ca5c3d6ccd85080610aAlex Deucher 158c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (gart_info->bus_addr) { 15906f0a488c1b642d3cd7769da66600e5148c3fad8Dave Airlie max_pages = (gart_info->table_size / sizeof(u64)); 160c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher pages = (entry->pages <= max_pages) 161c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ? entry->pages : max_pages; 162c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 163c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < pages; i++) { 164c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!entry->busaddr[i]) 165c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 166a763d7dc0adb1159c1a52d43e566409da9fa59f0Dave Airlie pci_unmap_page(dev->pdev, entry->busaddr[i], 167a763d7dc0adb1159c1a52d43e566409da9fa59f0Dave Airlie PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 168c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 169c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) 170c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gart_info->bus_addr = 0; 171c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 172c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 173c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 174c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher/* R600 has page table setup */ 175c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherint r600_page_table_init(struct drm_device *dev) 176c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 177c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 178c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info; 179eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie struct drm_local_map *map = &gart_info->mapping; 180c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_sg_mem *entry = dev->sg; 181c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int ret = 0; 182c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i, j; 183eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie int pages; 184eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie u64 page_base; 185c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dma_addr_t entry_addr; 186eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie int max_ati_pages, max_real_pages, gart_idx; 187c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 188c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* okay page table is available - lets rock */ 189eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie max_ati_pages = (gart_info->table_size / sizeof(u64)); 190eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); 191c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 192eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie pages = (entry->pages <= max_real_pages) ? 193eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie entry->pages : max_real_pages; 194c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 195eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie memset_io((void __iomem *)map->handle, 0, max_ati_pages * sizeof(u64)); 196c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 197eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie gart_idx = 0; 198c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < pages; i++) { 199a763d7dc0adb1159c1a52d43e566409da9fa59f0Dave Airlie entry->busaddr[i] = pci_map_page(dev->pdev, 200a763d7dc0adb1159c1a52d43e566409da9fa59f0Dave Airlie entry->pagelist[i], 0, 201a763d7dc0adb1159c1a52d43e566409da9fa59f0Dave Airlie PAGE_SIZE, 202a763d7dc0adb1159c1a52d43e566409da9fa59f0Dave Airlie PCI_DMA_BIDIRECTIONAL); 203a30f6fb7ce86275af16c7a00dc1b1e46cbb99692Benjamin Herrenschmidt if (pci_dma_mapping_error(dev->pdev, entry->busaddr[i])) { 204c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("unable to map PCIGART pages!\n"); 205c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_page_table_cleanup(dev, gart_info); 206c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher goto done; 207c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 208c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher entry_addr = entry->busaddr[i]; 209c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) { 210c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK; 211c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; 212c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE; 213c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 214eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie DRM_WRITE64(map, gart_idx * sizeof(u64), page_base); 215eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie 216eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie gart_idx++; 217c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 218c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((i % 128) == 0) 219c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("page entry %d: 0x%016llx\n", 220c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher i, (unsigned long long)page_base); 221c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher entry_addr += ATI_PCIGART_PAGE_SIZE; 222c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 223c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 22441f13fe81dd1b08723ab9f3fc3c7f29cfa81f1a5Alex Deucher ret = 1; 225c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherdone: 226c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return ret; 227c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 228c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 229c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r600_vm_flush_gart_range(struct drm_device *dev) 230c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 231c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 232c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 resp, countdown = 1000; 233c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12); 234c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 235c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2); 236c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 237c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher do { 238c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE); 239c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher countdown--; 240c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(1); 241c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } while (((resp & 0xf0) == 0) && countdown); 242c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 243c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 244c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r600_vm_init(struct drm_device *dev) 245c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 246c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 247c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* initialise the VM to use the page table we constructed up there */ 248c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 vm_c0, i; 249c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 mc_rd_a; 250c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 vm_l2_cntl, vm_l2_cntl3; 251c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* okay set up the PCIE aperture type thingo */ 252c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); 253c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 254c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 255c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 256c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* setup MC RD a */ 257c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS | 258c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) | 259c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY; 260c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 261c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a); 262c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a); 263c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 264c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a); 265c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a); 266c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 267c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a); 268c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a); 269c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 270c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a); 271c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a); 272c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 273c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING); 274c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/); 275c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 276c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a); 277c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a); 278c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 279c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE); 280c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a); 281c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 282c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W; 283c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7); 284c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl); 285c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 286c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_L2_CNTL2, 0); 287c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) | 288c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VM_L2_CNTL3_BANK_SELECT_1(1) | 289c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2)); 290c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3); 291c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 292c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT; 293c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 294c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0); 295c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 296c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_c0 &= ~R600_VM_ENABLE_CONTEXT; 297c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 298c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* disable all other contexts */ 299c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 1; i < 8; i++) 300c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0); 301c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 302c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); 303c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); 304c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 305c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 306c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_vm_flush_gart_range(dev); 307c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 308c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 30970967ab9c0c9017645d167d33675eab996633631Ben Hutchingsstatic int r600_cp_init_microcode(drm_radeon_private_t *dev_priv) 31070967ab9c0c9017645d167d33675eab996633631Ben Hutchings{ 31170967ab9c0c9017645d167d33675eab996633631Ben Hutchings struct platform_device *pdev; 31270967ab9c0c9017645d167d33675eab996633631Ben Hutchings const char *chip_name; 31370967ab9c0c9017645d167d33675eab996633631Ben Hutchings size_t pfp_req_size, me_req_size; 31470967ab9c0c9017645d167d33675eab996633631Ben Hutchings char fw_name[30]; 31570967ab9c0c9017645d167d33675eab996633631Ben Hutchings int err; 31670967ab9c0c9017645d167d33675eab996633631Ben Hutchings 31770967ab9c0c9017645d167d33675eab996633631Ben Hutchings pdev = platform_device_register_simple("r600_cp", 0, NULL, 0); 31870967ab9c0c9017645d167d33675eab996633631Ben Hutchings err = IS_ERR(pdev); 31970967ab9c0c9017645d167d33675eab996633631Ben Hutchings if (err) { 32070967ab9c0c9017645d167d33675eab996633631Ben Hutchings printk(KERN_ERR "r600_cp: Failed to register firmware\n"); 32170967ab9c0c9017645d167d33675eab996633631Ben Hutchings return -EINVAL; 32270967ab9c0c9017645d167d33675eab996633631Ben Hutchings } 32370967ab9c0c9017645d167d33675eab996633631Ben Hutchings 32470967ab9c0c9017645d167d33675eab996633631Ben Hutchings switch (dev_priv->flags & RADEON_FAMILY_MASK) { 32570967ab9c0c9017645d167d33675eab996633631Ben Hutchings case CHIP_R600: chip_name = "R600"; break; 32670967ab9c0c9017645d167d33675eab996633631Ben Hutchings case CHIP_RV610: chip_name = "RV610"; break; 32770967ab9c0c9017645d167d33675eab996633631Ben Hutchings case CHIP_RV630: chip_name = "RV630"; break; 32870967ab9c0c9017645d167d33675eab996633631Ben Hutchings case CHIP_RV620: chip_name = "RV620"; break; 32970967ab9c0c9017645d167d33675eab996633631Ben Hutchings case CHIP_RV635: chip_name = "RV635"; break; 33070967ab9c0c9017645d167d33675eab996633631Ben Hutchings case CHIP_RV670: chip_name = "RV670"; break; 33170967ab9c0c9017645d167d33675eab996633631Ben Hutchings case CHIP_RS780: 33270967ab9c0c9017645d167d33675eab996633631Ben Hutchings case CHIP_RS880: chip_name = "RS780"; break; 33370967ab9c0c9017645d167d33675eab996633631Ben Hutchings case CHIP_RV770: chip_name = "RV770"; break; 33470967ab9c0c9017645d167d33675eab996633631Ben Hutchings case CHIP_RV730: 33570967ab9c0c9017645d167d33675eab996633631Ben Hutchings case CHIP_RV740: chip_name = "RV730"; break; 33670967ab9c0c9017645d167d33675eab996633631Ben Hutchings case CHIP_RV710: chip_name = "RV710"; break; 33770967ab9c0c9017645d167d33675eab996633631Ben Hutchings default: BUG(); 33870967ab9c0c9017645d167d33675eab996633631Ben Hutchings } 33970967ab9c0c9017645d167d33675eab996633631Ben Hutchings 34070967ab9c0c9017645d167d33675eab996633631Ben Hutchings if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) { 34170967ab9c0c9017645d167d33675eab996633631Ben Hutchings pfp_req_size = R700_PFP_UCODE_SIZE * 4; 34270967ab9c0c9017645d167d33675eab996633631Ben Hutchings me_req_size = R700_PM4_UCODE_SIZE * 4; 34370967ab9c0c9017645d167d33675eab996633631Ben Hutchings } else { 34470967ab9c0c9017645d167d33675eab996633631Ben Hutchings pfp_req_size = PFP_UCODE_SIZE * 4; 34570967ab9c0c9017645d167d33675eab996633631Ben Hutchings me_req_size = PM4_UCODE_SIZE * 12; 34670967ab9c0c9017645d167d33675eab996633631Ben Hutchings } 34770967ab9c0c9017645d167d33675eab996633631Ben Hutchings 34870967ab9c0c9017645d167d33675eab996633631Ben Hutchings DRM_INFO("Loading %s CP Microcode\n", chip_name); 34970967ab9c0c9017645d167d33675eab996633631Ben Hutchings 35070967ab9c0c9017645d167d33675eab996633631Ben Hutchings snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 35170967ab9c0c9017645d167d33675eab996633631Ben Hutchings err = request_firmware(&dev_priv->pfp_fw, fw_name, &pdev->dev); 35270967ab9c0c9017645d167d33675eab996633631Ben Hutchings if (err) 35370967ab9c0c9017645d167d33675eab996633631Ben Hutchings goto out; 35470967ab9c0c9017645d167d33675eab996633631Ben Hutchings if (dev_priv->pfp_fw->size != pfp_req_size) { 35570967ab9c0c9017645d167d33675eab996633631Ben Hutchings printk(KERN_ERR 35670967ab9c0c9017645d167d33675eab996633631Ben Hutchings "r600_cp: Bogus length %zu in firmware \"%s\"\n", 35770967ab9c0c9017645d167d33675eab996633631Ben Hutchings dev_priv->pfp_fw->size, fw_name); 35870967ab9c0c9017645d167d33675eab996633631Ben Hutchings err = -EINVAL; 35970967ab9c0c9017645d167d33675eab996633631Ben Hutchings goto out; 36070967ab9c0c9017645d167d33675eab996633631Ben Hutchings } 36170967ab9c0c9017645d167d33675eab996633631Ben Hutchings 36270967ab9c0c9017645d167d33675eab996633631Ben Hutchings snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 36370967ab9c0c9017645d167d33675eab996633631Ben Hutchings err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev); 36470967ab9c0c9017645d167d33675eab996633631Ben Hutchings if (err) 36570967ab9c0c9017645d167d33675eab996633631Ben Hutchings goto out; 36670967ab9c0c9017645d167d33675eab996633631Ben Hutchings if (dev_priv->me_fw->size != me_req_size) { 36770967ab9c0c9017645d167d33675eab996633631Ben Hutchings printk(KERN_ERR 36870967ab9c0c9017645d167d33675eab996633631Ben Hutchings "r600_cp: Bogus length %zu in firmware \"%s\"\n", 36970967ab9c0c9017645d167d33675eab996633631Ben Hutchings dev_priv->me_fw->size, fw_name); 37070967ab9c0c9017645d167d33675eab996633631Ben Hutchings err = -EINVAL; 37170967ab9c0c9017645d167d33675eab996633631Ben Hutchings } 37270967ab9c0c9017645d167d33675eab996633631Ben Hutchingsout: 37370967ab9c0c9017645d167d33675eab996633631Ben Hutchings platform_device_unregister(pdev); 37470967ab9c0c9017645d167d33675eab996633631Ben Hutchings 37570967ab9c0c9017645d167d33675eab996633631Ben Hutchings if (err) { 37670967ab9c0c9017645d167d33675eab996633631Ben Hutchings if (err != -EINVAL) 37770967ab9c0c9017645d167d33675eab996633631Ben Hutchings printk(KERN_ERR 37870967ab9c0c9017645d167d33675eab996633631Ben Hutchings "r600_cp: Failed to load firmware \"%s\"\n", 37970967ab9c0c9017645d167d33675eab996633631Ben Hutchings fw_name); 38070967ab9c0c9017645d167d33675eab996633631Ben Hutchings release_firmware(dev_priv->pfp_fw); 38170967ab9c0c9017645d167d33675eab996633631Ben Hutchings dev_priv->pfp_fw = NULL; 38270967ab9c0c9017645d167d33675eab996633631Ben Hutchings release_firmware(dev_priv->me_fw); 38370967ab9c0c9017645d167d33675eab996633631Ben Hutchings dev_priv->me_fw = NULL; 38470967ab9c0c9017645d167d33675eab996633631Ben Hutchings } 38570967ab9c0c9017645d167d33675eab996633631Ben Hutchings return err; 38670967ab9c0c9017645d167d33675eab996633631Ben Hutchings} 38770967ab9c0c9017645d167d33675eab996633631Ben Hutchings 388c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r600_cp_load_microcode(drm_radeon_private_t *dev_priv) 389c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 39070967ab9c0c9017645d167d33675eab996633631Ben Hutchings const __be32 *fw_data; 391c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i; 392c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 39370967ab9c0c9017645d167d33675eab996633631Ben Hutchings if (!dev_priv->me_fw || !dev_priv->pfp_fw) 39470967ab9c0c9017645d167d33675eab996633631Ben Hutchings return; 39570967ab9c0c9017645d167d33675eab996633631Ben Hutchings 396c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cp_stop(dev_priv); 397c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 398c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 399dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano#ifdef __BIG_ENDIAN 400dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano R600_BUF_SWAP_32BIT | 401dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano#endif 402c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_RB_NO_UPDATE | 403c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_RB_BLKSZ(15) | 404c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_RB_BUFSZ(3)); 405c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 406c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 407c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_SOFT_RESET); 408c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(15000); 409c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 410c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 41170967ab9c0c9017645d167d33675eab996633631Ben Hutchings fw_data = (const __be32 *)dev_priv->me_fw->data; 412c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 41370967ab9c0c9017645d167d33675eab996633631Ben Hutchings for (i = 0; i < PM4_UCODE_SIZE * 3; i++) 41470967ab9c0c9017645d167d33675eab996633631Ben Hutchings RADEON_WRITE(R600_CP_ME_RAM_DATA, 41570967ab9c0c9017645d167d33675eab996633631Ben Hutchings be32_to_cpup(fw_data++)); 416c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 41770967ab9c0c9017645d167d33675eab996633631Ben Hutchings fw_data = (const __be32 *)dev_priv->pfp_fw->data; 41870967ab9c0c9017645d167d33675eab996633631Ben Hutchings RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 41970967ab9c0c9017645d167d33675eab996633631Ben Hutchings for (i = 0; i < PFP_UCODE_SIZE; i++) 42070967ab9c0c9017645d167d33675eab996633631Ben Hutchings RADEON_WRITE(R600_CP_PFP_UCODE_DATA, 42170967ab9c0c9017645d167d33675eab996633631Ben Hutchings be32_to_cpup(fw_data++)); 422c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 423c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 424c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 425c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); 426c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 427c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 428c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 429c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r700_vm_init(struct drm_device *dev) 430c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 431c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 432c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* initialise the VM to use the page table we constructed up there */ 433c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 vm_c0, i; 434c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 mc_vm_md_l1; 435c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 vm_l2_cntl, vm_l2_cntl3; 436c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* okay set up the PCIE aperture type thingo */ 437c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); 438c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 439c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 440c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 441c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher mc_vm_md_l1 = R700_ENABLE_L1_TLB | 442c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_ENABLE_L1_FRAGMENT_PROCESSING | 443c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SYSTEM_ACCESS_MODE_IN_SYS | 444c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 445c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_EFFECTIVE_L1_TLB_SIZE(5) | 446c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_EFFECTIVE_L1_QUEUE_SIZE(5); 447c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 448c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1); 449c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1); 450c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1); 451c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1); 452c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1); 453c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1); 454c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1); 455c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 456c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W; 457c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7); 458c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl); 459c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 460c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_L2_CNTL2, 0); 461c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2); 462c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3); 463c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 464c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT; 465c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 466c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0); 467c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 468c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_c0 &= ~R600_VM_ENABLE_CONTEXT; 469c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 470c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* disable all other contexts */ 471c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 1; i < 8; i++) 472c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0); 473c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 474c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); 475c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); 476c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 477c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 478c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_vm_flush_gart_range(dev); 479c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 480c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 481c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r700_cp_load_microcode(drm_radeon_private_t *dev_priv) 482c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 48370967ab9c0c9017645d167d33675eab996633631Ben Hutchings const __be32 *fw_data; 484c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i; 485c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 48670967ab9c0c9017645d167d33675eab996633631Ben Hutchings if (!dev_priv->me_fw || !dev_priv->pfp_fw) 48770967ab9c0c9017645d167d33675eab996633631Ben Hutchings return; 48870967ab9c0c9017645d167d33675eab996633631Ben Hutchings 489c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cp_stop(dev_priv); 490c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 491c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 492dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano#ifdef __BIG_ENDIAN 493dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano R600_BUF_SWAP_32BIT | 494dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano#endif 495c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_RB_NO_UPDATE | 496dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano R600_RB_BLKSZ(15) | 497dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano R600_RB_BUFSZ(3)); 498c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 499c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 500c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_SOFT_RESET); 501c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(15000); 502c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 503c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 50470967ab9c0c9017645d167d33675eab996633631Ben Hutchings fw_data = (const __be32 *)dev_priv->pfp_fw->data; 50570967ab9c0c9017645d167d33675eab996633631Ben Hutchings RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 50670967ab9c0c9017645d167d33675eab996633631Ben Hutchings for (i = 0; i < R700_PFP_UCODE_SIZE; i++) 50770967ab9c0c9017645d167d33675eab996633631Ben Hutchings RADEON_WRITE(R600_CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 50870967ab9c0c9017645d167d33675eab996633631Ben Hutchings RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 509c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 51070967ab9c0c9017645d167d33675eab996633631Ben Hutchings fw_data = (const __be32 *)dev_priv->me_fw->data; 51170967ab9c0c9017645d167d33675eab996633631Ben Hutchings RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 51270967ab9c0c9017645d167d33675eab996633631Ben Hutchings for (i = 0; i < R700_PM4_UCODE_SIZE; i++) 51370967ab9c0c9017645d167d33675eab996633631Ben Hutchings RADEON_WRITE(R600_CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 51470967ab9c0c9017645d167d33675eab996633631Ben Hutchings RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 515c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 516c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 517c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 518c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); 519c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 520c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 521c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 522c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r600_test_writeback(drm_radeon_private_t *dev_priv) 523c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 524c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 tmp; 525c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 526c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Start with assuming that writeback doesn't work */ 527c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->writeback_works = 0; 528c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 529c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Writeback doesn't seem to work everywhere, test it here and possibly 530c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * enable it if it appears to work 531c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 532c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0); 533c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 534c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef); 535c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 536c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { 537c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 val; 538c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 539c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1)); 540c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (val == 0xdeadbeef) 541c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 542c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(1); 543c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 544c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 545c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (tmp < dev_priv->usec_timeout) { 546c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->writeback_works = 1; 547c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("writeback test succeeded in %d usecs\n", tmp); 548c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else { 549c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->writeback_works = 0; 550c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("writeback test failed\n"); 551c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 552c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (radeon_no_wb == 1) { 553c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->writeback_works = 0; 554c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("writeback forced off\n"); 555c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 556c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 557c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev_priv->writeback_works) { 558c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Disable writeback to avoid unnecessary bus master transfer */ 559dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano RADEON_WRITE(R600_CP_RB_CNTL, 560dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano#ifdef __BIG_ENDIAN 561dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano R600_BUF_SWAP_32BIT | 562dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano#endif 563dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano RADEON_READ(R600_CP_RB_CNTL) | 564dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano R600_RB_NO_UPDATE); 565c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SCRATCH_UMSK, 0); 566c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 567c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 568c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 569c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherint r600_do_engine_reset(struct drm_device *dev) 570c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 571c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 572c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cp_ptr, cp_me_cntl, cp_rb_cntl; 573c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 574c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Resetting GPU\n"); 575c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 576c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cp_ptr = RADEON_READ(R600_CP_RB_WPTR); 577c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL); 578c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT); 579c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 580c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff); 581c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_SOFT_RESET); 582c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(50); 583c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 584c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_SOFT_RESET); 585c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 586c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); 587c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL); 588dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano RADEON_WRITE(R600_CP_RB_CNTL, 589dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano#ifdef __BIG_ENDIAN 590dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano R600_BUF_SWAP_32BIT | 591dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano#endif 592dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano R600_RB_RPTR_WR_ENA); 593c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 594c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr); 595c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr); 596c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl); 597c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl); 598c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 599c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Reset the CP ring */ 600c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cp_reset(dev_priv); 601c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 602c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* The CP is no longer running after an engine reset */ 603c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_running = 0; 604c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 605c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Reset any pending vertex, indirect buffers */ 606c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_freelist_reset(dev); 607c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 608c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return 0; 609c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 610c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 611c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 612c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes, 613c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 num_backends, 614c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 backend_disable_mask) 615c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 616c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 backend_map = 0; 617c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 enabled_backends_mask; 618c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 enabled_backends_count; 619c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cur_pipe; 620c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 swizzle_pipe[R6XX_MAX_PIPES]; 621c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cur_backend; 622c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 i; 623c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 624c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_tile_pipes > R6XX_MAX_PIPES) 625c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_tile_pipes = R6XX_MAX_PIPES; 626c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_tile_pipes < 1) 627c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_tile_pipes = 1; 628c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_backends > R6XX_MAX_BACKENDS) 629c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_backends = R6XX_MAX_BACKENDS; 630c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_backends < 1) 631c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_backends = 1; 632c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 633c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_mask = 0; 634c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_count = 0; 635c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < R6XX_MAX_BACKENDS; ++i) { 636c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((backend_disable_mask >> i) & 1) == 0) { 637c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_mask |= (1 << i); 638c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ++enabled_backends_count; 639c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 640c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (enabled_backends_count == num_backends) 641c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 642c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 643c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 644c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (enabled_backends_count == 0) { 645c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_mask = 1; 646c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_count = 1; 647c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 648c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 649c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (enabled_backends_count != num_backends) 650c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_backends = enabled_backends_count; 651c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 652c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES); 653c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (num_tile_pipes) { 654c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 1: 655c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 656c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 657c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 2: 658c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 659c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 1; 660c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 661c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 3: 662c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 663c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 1; 664c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 2; 665c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 666c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 4: 667c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 668c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 1; 669c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 2; 670c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 3; 671c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 672c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 5: 673c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 674c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 1; 675c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 2; 676c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 3; 677c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[4] = 4; 678c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 679c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 6: 680c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 681c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 2; 682c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 4; 683c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 5; 684c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[4] = 1; 685c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[5] = 3; 686c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 687c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 7: 688c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 689c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 2; 690c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 4; 691c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 6; 692c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[4] = 1; 693c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[5] = 3; 694c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[6] = 5; 695c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 696c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 8: 697c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 698c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 2; 699c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 4; 700c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 6; 701c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[4] = 1; 702c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[5] = 3; 703c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[6] = 5; 704c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[7] = 7; 705c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 706c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 707c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 708c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cur_backend = 0; 709c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 710c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher while (((1 << cur_backend) & enabled_backends_mask) == 0) 711c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; 712c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 713c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 714c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 715c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; 716c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 717c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 718c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return backend_map; 719c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 720c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 721c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic int r600_count_pipe_bits(uint32_t val) 722c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 723c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i, ret = 0; 724c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < 32; i++) { 725c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ret += val & 1; 726c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher val >>= 1; 727c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 728c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return ret; 729c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 730c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 731c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r600_gfx_init(struct drm_device *dev, 732c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv) 733c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 734c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i, j, num_qd_pipes; 735c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sx_debug_1; 736c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 tc_cntl; 737c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 arb_pop; 738c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 num_gs_verts_per_thread; 739c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 vgt_gs_per_es; 740c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 gs_prim_buffer_depth = 0; 741c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_ms_fifo_sizes; 742c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_config; 743c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_gpr_resource_mgmt_1 = 0; 744c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_gpr_resource_mgmt_2 = 0; 745c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_thread_resource_mgmt = 0; 746c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_stack_resource_mgmt_1 = 0; 747c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_stack_resource_mgmt_2 = 0; 748c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 hdp_host_path_cntl; 749c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 backend_map; 750c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 gb_tiling_config = 0; 751d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher u32 cc_rb_backend_disable; 752d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher u32 cc_gc_shader_pipe_config; 753c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 ramcfg; 754c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 755c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* setup chip specs */ 756c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->flags & RADEON_FAMILY_MASK) { 757c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_R600: 758c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_pipes = 4; 759c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_tile_pipes = 8; 760c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_simds = 4; 761c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends = 4; 762c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gprs = 256; 763c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_threads = 192; 764c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_stack_entries = 256; 765c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_hw_contexts = 8; 766c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gs_threads = 16; 767c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_size = 128; 768c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_pos_size = 16; 769c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_smx_size = 128; 770c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sq_num_cf_insts = 2; 771c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 772c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV630: 773c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV635: 774c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_pipes = 2; 775c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_tile_pipes = 2; 776c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_simds = 3; 777c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends = 1; 778c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gprs = 128; 779c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_threads = 192; 780c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_stack_entries = 128; 781c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_hw_contexts = 8; 782c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gs_threads = 4; 783c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_size = 128; 784c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_pos_size = 16; 785c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_smx_size = 128; 786c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sq_num_cf_insts = 2; 787c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 788c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV610: 789c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RS780: 7906502fbfaf81b09b3f474bb7b3796257e9450273eAlex Deucher case CHIP_RS880: 791c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV620: 792c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_pipes = 1; 793c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_tile_pipes = 1; 794c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_simds = 2; 795c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends = 1; 796c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gprs = 128; 797c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_threads = 192; 798c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_stack_entries = 128; 799c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_hw_contexts = 4; 800c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gs_threads = 4; 801c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_size = 128; 802c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_pos_size = 16; 803c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_smx_size = 128; 804c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sq_num_cf_insts = 1; 805c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 806c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV670: 807c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_pipes = 4; 808c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_tile_pipes = 4; 809c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_simds = 4; 810c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends = 4; 811c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gprs = 192; 812c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_threads = 192; 813c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_stack_entries = 256; 814c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_hw_contexts = 8; 815c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gs_threads = 16; 816c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_size = 128; 817c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_pos_size = 16; 818c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_smx_size = 128; 819c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sq_num_cf_insts = 2; 820c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 821c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 822c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 823c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 824c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 825c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Initialize HDP */ 826c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher j = 0; 827c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < 32; i++) { 828c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c14 + j), 0x00000000); 829c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c18 + j), 0x00000000); 830c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c1c + j), 0x00000000); 831c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c20 + j), 0x00000000); 832c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c24 + j), 0x00000000); 833c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher j += 0x18; 834c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 835c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 836c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff)); 837c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 838c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* setup tiling, simd, pipe config */ 839c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ramcfg = RADEON_READ(R600_RAMCFG); 840c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 841c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->r600_max_tile_pipes) { 842c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 1: 843c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(0); 844c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 845c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 2: 846c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(1); 847c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 848c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 4: 849c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(2); 850c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 851c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 8: 852c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(3); 853c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 854c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 855c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 856c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 857c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 858c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK); 859c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 860c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_GROUP_SIZE(0); 861c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 862c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) { 863c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_ROW_TILING(3); 864c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_SAMPLE_SPLIT(3); 865c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else { 866c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= 867c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK)); 868c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= 869c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK)); 870c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 871c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 872c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_BANK_SWAPS(1); 873c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 874d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher cc_rb_backend_disable = RADEON_READ(R600_CC_RB_BACKEND_DISABLE) & 0x00ff0000; 875d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher cc_rb_backend_disable |= 876d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK); 877c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 878d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher cc_gc_shader_pipe_config = RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; 879d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher cc_gc_shader_pipe_config |= 880c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK); 881c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cc_gc_shader_pipe_config |= 882c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK); 883c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 884d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes, 885d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher (R6XX_MAX_BACKENDS - 886d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher r600_count_pipe_bits((cc_rb_backend_disable & 887d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher R6XX_MAX_BACKENDS_MASK) >> 16)), 888d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher (cc_rb_backend_disable >> 16)); 889d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher gb_tiling_config |= R600_BACKEND_MAP(backend_map); 890c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 891c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); 892c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 893c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 894961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse if (gb_tiling_config & 0xc0) { 895961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse dev_priv->r600_group_size = 512; 896961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse } else { 897961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse dev_priv->r600_group_size = 256; 898961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse } 899961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7); 900961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse if (gb_tiling_config & 0x30) { 901961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse dev_priv->r600_nbanks = 8; 902961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse } else { 903961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse dev_priv->r600_nbanks = 4; 904961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse } 905c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 906c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 907c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 908c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 909c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 910c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_qd_pipes = 911d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8); 912c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK); 913c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK); 914c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 915c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* set HW defaults for 3D engine */ 916c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) | 917c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ROQ_IB2_START(0x2b))); 918c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 919c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) | 920c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ROQ_END(0x40))); 921c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 922c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO | 923c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SYNC_GRADIENT | 924c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SYNC_WALKER | 925c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SYNC_ALIGNER)); 926c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 927c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) 928c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021); 929c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 930c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1); 931c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sx_debug_1 |= R600_SMX_EVENT_RELEASE; 932c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600)) 933c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS; 934c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1); 935c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 936c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || 937c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || 938c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 939c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 9406502fbfaf81b09b3f474bb7b3796257e9450273eAlex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || 9416502fbfaf81b09b3f474bb7b3796257e9450273eAlex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) 942c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE); 943c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 944c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_DB_DEBUG, 0); 945c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 946c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) | 947c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_DEPTH_FLUSH(16) | 948c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_DEPTH_PENDING_FREE(4) | 949c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_DEPTH_CACHELINE_FREE(16))); 950c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 951c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0); 952c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 953c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0)); 954c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0)); 955c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 956c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES); 957c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 958c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 9596502fbfaf81b09b3f474bb7b3796257e9450273eAlex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || 9606502fbfaf81b09b3f474bb7b3796257e9450273eAlex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) { 961c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) | 962c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_FETCH_FIFO_HIWATER(0xa) | 963c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_DONE_FIFO_HIWATER(0xe0) | 964c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ALU_UPDATE_FIFO_HIWATER(0x8)); 965c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || 966c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) { 967c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff); 968c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4); 969c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 970c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 971c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 972c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 973c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * should be adjusted as needed by the 2D/3D drivers. This just sets default values 974c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 975c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config = RADEON_READ(R600_SQ_CONFIG); 976c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config &= ~(R600_PS_PRIO(3) | 977c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VS_PRIO(3) | 978c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_GS_PRIO(3) | 979c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ES_PRIO(3)); 980c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config |= (R600_DX9_CONSTS | 981c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VC_ENABLE | 982c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_PS_PRIO(0) | 983c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VS_PRIO(1) | 984c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_GS_PRIO(2) | 985c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ES_PRIO(3)); 986c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 987c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) { 988c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) | 989c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_GPRS(124) | 990c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_CLAUSE_TEMP_GPRS(4)); 991c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) | 992c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_GPRS(0)); 993c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) | 994c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_THREADS(48) | 995c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_GS_THREADS(4) | 996c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_THREADS(4)); 997c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) | 998c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_STACK_ENTRIES(128)); 999c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) | 1000c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_STACK_ENTRIES(0)); 1001c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 1002c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 10036502fbfaf81b09b3f474bb7b3796257e9450273eAlex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || 10046502fbfaf81b09b3f474bb7b3796257e9450273eAlex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) { 1005c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* no vertex cache */ 1006c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config &= ~R600_VC_ENABLE; 1007c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1008c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 1009c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_GPRS(44) | 1010c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_CLAUSE_TEMP_GPRS(2)); 1011c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) | 1012c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_GPRS(17)); 1013c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 1014c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_THREADS(78) | 1015c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_GS_THREADS(4) | 1016c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_THREADS(31)); 1017c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) | 1018c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_STACK_ENTRIES(40)); 1019c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) | 1020c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_STACK_ENTRIES(16)); 1021c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || 1022c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) { 1023c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 1024c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_GPRS(44) | 1025c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_CLAUSE_TEMP_GPRS(2)); 1026c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) | 1027c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_GPRS(18)); 1028c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 1029c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_THREADS(78) | 1030c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_GS_THREADS(4) | 1031c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_THREADS(31)); 1032c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) | 1033c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_STACK_ENTRIES(40)); 1034c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) | 1035c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_STACK_ENTRIES(16)); 1036c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) { 1037c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 1038c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_GPRS(44) | 1039c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_CLAUSE_TEMP_GPRS(2)); 1040c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) | 1041c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_GPRS(17)); 1042c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 1043c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_THREADS(78) | 1044c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_GS_THREADS(4) | 1045c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_THREADS(31)); 1046c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) | 1047c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_STACK_ENTRIES(64)); 1048c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) | 1049c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_STACK_ENTRIES(64)); 1050c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1051c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1052c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_CONFIG, sq_config); 1053c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 1054c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 1055c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1056c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 1057c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 1058c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1059c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 1060c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 10616502fbfaf81b09b3f474bb7b3796257e9450273eAlex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || 10626502fbfaf81b09b3f474bb7b3796257e9450273eAlex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) 1063c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY)); 1064c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 1065c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC)); 1066c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1067c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) | 1068c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S0_Y(0x4) | 1069c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S1_X(0x4) | 1070c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S1_Y(0xc))); 1071c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) | 1072c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S0_Y(0xe) | 1073c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S1_X(0x2) | 1074c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S1_Y(0x2) | 1075c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S2_X(0xa) | 1076c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S2_Y(0x6) | 1077c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S3_X(0x6) | 1078c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S3_Y(0xa))); 1079c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) | 1080c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S0_Y(0xb) | 1081c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S1_X(0x4) | 1082c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S1_Y(0xc) | 1083c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S2_X(0x1) | 1084c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S2_Y(0x6) | 1085c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S3_X(0xa) | 1086c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S3_Y(0xe))); 1087c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) | 1088c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S4_Y(0x1) | 1089c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S5_X(0x0) | 1090c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S5_Y(0x0) | 1091c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S6_X(0xb) | 1092c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S6_Y(0x4) | 1093c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S7_X(0x7) | 1094c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S7_Y(0x8))); 1095c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1096c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1097c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1098c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_R600: 1099c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV630: 1100c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV635: 1101c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gs_prim_buffer_depth = 0; 1102c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1103c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV610: 1104c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RS780: 11056502fbfaf81b09b3f474bb7b3796257e9450273eAlex Deucher case CHIP_RS880: 1106c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV620: 1107c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gs_prim_buffer_depth = 32; 1108c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1109c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV670: 1110c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gs_prim_buffer_depth = 128; 1111c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1112c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 1113c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1114c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1115c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1116c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; 1117c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 1118c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Max value for this is 256 */ 1119c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (vgt_gs_per_es > 256) 1120c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vgt_gs_per_es = 256; 1121c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1122c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_ES_PER_GS, 128); 1123c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es); 1124c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_GS_PER_VS, 2); 1125c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16); 1126c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1127c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* more default values. 2D/3D driver should adjust as needed */ 1128c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0); 1129c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_STRMOUT_EN, 0); 1130c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SX_MISC, 0); 1131c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0); 1132c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0); 1133c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0); 1134c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_INPUT_Z, 0); 1135c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2)); 1136c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR7_FRAG, 0); 1137c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1138c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* clear render buffer base addresses */ 1139c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR0_BASE, 0); 1140c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR1_BASE, 0); 1141c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR2_BASE, 0); 1142c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR3_BASE, 0); 1143c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR4_BASE, 0); 1144c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR5_BASE, 0); 1145c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR6_BASE, 0); 1146c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR7_BASE, 0); 1147c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1148c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1149c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV610: 1150c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RS780: 11516502fbfaf81b09b3f474bb7b3796257e9450273eAlex Deucher case CHIP_RS880: 1152c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV620: 1153c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher tc_cntl = R600_TC_L2_SIZE(8); 1154c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1155c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV630: 1156c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV635: 1157c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher tc_cntl = R600_TC_L2_SIZE(4); 1158c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1159c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_R600: 1160c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT; 1161c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1162c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 1163c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher tc_cntl = R600_TC_L2_SIZE(0); 1164c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1165c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1166c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1167c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_TC_CNTL, tc_cntl); 1168c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1169c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL); 1170c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1171c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1172c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher arb_pop = RADEON_READ(R600_ARB_POP); 1173c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher arb_pop |= R600_ENABLE_TC128; 1174c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_ARB_POP, arb_pop); 1175c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1176c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1177c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA | 1178c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_CLIP_SEQ(3))); 1179c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095)); 1180c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1181c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 1182c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1183d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucherstatic u32 r700_get_tile_pipe_to_backend_map(drm_radeon_private_t *dev_priv, 1184d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher u32 num_tile_pipes, 1185c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 num_backends, 1186c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 backend_disable_mask) 1187c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 1188c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 backend_map = 0; 1189c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 enabled_backends_mask; 1190c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 enabled_backends_count; 1191c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cur_pipe; 1192c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 swizzle_pipe[R7XX_MAX_PIPES]; 1193c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cur_backend; 1194c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 i; 1195d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher bool force_no_swizzle; 1196c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1197c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_tile_pipes > R7XX_MAX_PIPES) 1198c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_tile_pipes = R7XX_MAX_PIPES; 1199c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_tile_pipes < 1) 1200c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_tile_pipes = 1; 1201c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_backends > R7XX_MAX_BACKENDS) 1202c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_backends = R7XX_MAX_BACKENDS; 1203c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_backends < 1) 1204c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_backends = 1; 1205c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1206c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_mask = 0; 1207c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_count = 0; 1208c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < R7XX_MAX_BACKENDS; ++i) { 1209c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((backend_disable_mask >> i) & 1) == 0) { 1210c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_mask |= (1 << i); 1211c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ++enabled_backends_count; 1212c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1213c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (enabled_backends_count == num_backends) 1214c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1215c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1216c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1217c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (enabled_backends_count == 0) { 1218c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_mask = 1; 1219c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_count = 1; 1220c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1221c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1222c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (enabled_backends_count != num_backends) 1223c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_backends = enabled_backends_count; 1224c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1225d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1226d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher case CHIP_RV770: 1227d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher case CHIP_RV730: 1228d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher force_no_swizzle = false; 1229d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher break; 1230d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher case CHIP_RV710: 1231d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher case CHIP_RV740: 1232d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher default: 1233d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher force_no_swizzle = true; 1234d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher break; 1235d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher } 1236d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher 1237c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES); 1238c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (num_tile_pipes) { 1239c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 1: 1240c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 1241c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1242c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 2: 1243c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 1244c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 1; 1245c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1246c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 3: 1247d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher if (force_no_swizzle) { 1248d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[0] = 0; 1249d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[1] = 1; 1250d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[2] = 2; 1251d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher } else { 1252d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[0] = 0; 1253d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[1] = 2; 1254d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[2] = 1; 1255d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher } 1256c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1257c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 4: 1258d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher if (force_no_swizzle) { 1259d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[0] = 0; 1260d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[1] = 1; 1261d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[2] = 2; 1262d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[3] = 3; 1263d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher } else { 1264d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[0] = 0; 1265d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[1] = 2; 1266d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[2] = 3; 1267d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[3] = 1; 1268d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher } 1269c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1270c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 5: 1271d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher if (force_no_swizzle) { 1272d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[0] = 0; 1273d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[1] = 1; 1274d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[2] = 2; 1275d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[3] = 3; 1276d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[4] = 4; 1277d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher } else { 1278d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[0] = 0; 1279d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[1] = 2; 1280d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[2] = 4; 1281d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[3] = 1; 1282d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[4] = 3; 1283d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher } 1284c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1285c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 6: 1286d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher if (force_no_swizzle) { 1287d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[0] = 0; 1288d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[1] = 1; 1289d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[2] = 2; 1290d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[3] = 3; 1291d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[4] = 4; 1292d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[5] = 5; 1293d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher } else { 1294d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[0] = 0; 1295d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[1] = 2; 1296d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[2] = 4; 1297d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[3] = 5; 1298d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[4] = 3; 1299d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[5] = 1; 1300d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher } 1301c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1302c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 7: 1303d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher if (force_no_swizzle) { 1304d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[0] = 0; 1305d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[1] = 1; 1306d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[2] = 2; 1307d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[3] = 3; 1308d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[4] = 4; 1309d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[5] = 5; 1310d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[6] = 6; 1311d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher } else { 1312d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[0] = 0; 1313d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[1] = 2; 1314d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[2] = 4; 1315d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[3] = 6; 1316d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[4] = 3; 1317d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[5] = 1; 1318d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[6] = 5; 1319d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher } 1320c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1321c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 8: 1322d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher if (force_no_swizzle) { 1323d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[0] = 0; 1324d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[1] = 1; 1325d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[2] = 2; 1326d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[3] = 3; 1327d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[4] = 4; 1328d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[5] = 5; 1329d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[6] = 6; 1330d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[7] = 7; 1331d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher } else { 1332d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[0] = 0; 1333d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[1] = 2; 1334d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[2] = 4; 1335d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[3] = 6; 1336d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[4] = 3; 1337d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[5] = 1; 1338d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[6] = 7; 1339d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[7] = 5; 1340d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher } 1341c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1342c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1343c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1344c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cur_backend = 0; 1345c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 1346c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher while (((1 << cur_backend) & enabled_backends_mask) == 0) 1347c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 1348c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1349c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 1350c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1351c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 1352c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1353c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1354c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return backend_map; 1355c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 1356c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1357c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r700_gfx_init(struct drm_device *dev, 1358c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv) 1359c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 1360c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i, j, num_qd_pipes; 1361d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher u32 ta_aux_cntl; 1362c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sx_debug_1; 1363c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 smx_dc_ctl0; 1364d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher u32 db_debug3; 1365c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 num_gs_verts_per_thread; 1366c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 vgt_gs_per_es; 1367c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 gs_prim_buffer_depth = 0; 1368c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_ms_fifo_sizes; 1369c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_config; 1370c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_thread_resource_mgmt; 1371c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 hdp_host_path_cntl; 1372c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_dyn_gpr_size_simd_ab_0; 1373c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 backend_map; 1374c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 gb_tiling_config = 0; 1375d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher u32 cc_rb_backend_disable; 1376d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher u32 cc_gc_shader_pipe_config; 1377c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 mc_arb_ramcfg; 1378c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 db_debug4; 1379c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1380c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* setup chip specs */ 1381c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1382c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV770: 1383c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_pipes = 4; 1384c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_tile_pipes = 8; 1385c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_simds = 10; 1386c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends = 4; 1387c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gprs = 256; 1388c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_threads = 248; 1389c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_stack_entries = 512; 1390c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_hw_contexts = 8; 1391c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gs_threads = 16 * 2; 1392c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_size = 128; 1393c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_pos_size = 16; 1394c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_smx_size = 112; 1395c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sq_num_cf_insts = 2; 1396c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1397c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sx_num_of_sets = 7; 1398c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_prim_fifo_size = 0xF9; 1399c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1400c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1401c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1402c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV730: 1403c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_pipes = 2; 1404c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_tile_pipes = 4; 1405c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_simds = 8; 1406c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends = 2; 1407c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gprs = 128; 1408c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_threads = 248; 1409c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_stack_entries = 256; 1410c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_hw_contexts = 8; 1411c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gs_threads = 16 * 2; 1412c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_size = 256; 1413c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_pos_size = 32; 1414c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_smx_size = 224; 1415c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sq_num_cf_insts = 2; 1416c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1417c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sx_num_of_sets = 7; 1418c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_prim_fifo_size = 0xf9; 1419c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1420c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 14212a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher if (dev_priv->r600_sx_max_export_pos_size > 16) { 14222a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_sx_max_export_pos_size -= 16; 14232a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_sx_max_export_smx_size += 16; 14242a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher } 1425c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1426c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV710: 1427c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_pipes = 2; 1428c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_tile_pipes = 2; 1429c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_simds = 2; 1430c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends = 1; 1431c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gprs = 256; 1432c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_threads = 192; 1433c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_stack_entries = 256; 1434c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_hw_contexts = 4; 1435c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gs_threads = 8 * 2; 1436c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_size = 128; 1437c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_pos_size = 16; 1438c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_smx_size = 112; 1439c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sq_num_cf_insts = 1; 1440c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1441c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sx_num_of_sets = 7; 1442c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_prim_fifo_size = 0x40; 1443c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1444c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1445c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 14462a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher case CHIP_RV740: 14472a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_max_pipes = 4; 14482a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_max_tile_pipes = 4; 14492a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_max_simds = 8; 14502a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_max_backends = 4; 14512a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_max_gprs = 256; 14522a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_max_threads = 248; 14532a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_max_stack_entries = 512; 14542a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_max_hw_contexts = 8; 14552a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_max_gs_threads = 16 * 2; 14562a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_sx_max_export_size = 256; 14572a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_sx_max_export_pos_size = 32; 14582a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_sx_max_export_smx_size = 224; 14592a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_sq_num_cf_insts = 2; 14602a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher 14612a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r700_sx_num_of_sets = 7; 14622a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r700_sc_prim_fifo_size = 0x100; 14632a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 14642a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 14652a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher 14662a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher if (dev_priv->r600_sx_max_export_pos_size > 16) { 14672a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_sx_max_export_pos_size -= 16; 14682a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_sx_max_export_smx_size += 16; 14692a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher } 14702a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher break; 1471c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 1472c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1473c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1474c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1475c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Initialize HDP */ 1476c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher j = 0; 1477c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < 32; i++) { 1478c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c14 + j), 0x00000000); 1479c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c18 + j), 0x00000000); 1480c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c1c + j), 0x00000000); 1481c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c20 + j), 0x00000000); 1482c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c24 + j), 0x00000000); 1483c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher j += 0x18; 1484c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1485c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1486c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff)); 1487c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1488c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* setup tiling, simd, pipe config */ 1489c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG); 1490c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1491c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->r600_max_tile_pipes) { 1492c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 1: 1493c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(0); 1494c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1495c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 2: 1496c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(1); 1497c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1498c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 4: 1499c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(2); 1500c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1501c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 8: 1502c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(3); 1503c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1504c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 1505c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1506c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1507c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1508c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770) 1509c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_BANK_TILING(1); 1510c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 1511c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK); 1512c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1513c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_GROUP_SIZE(0); 1514c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1515c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) { 1516c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_ROW_TILING(3); 1517c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_SAMPLE_SPLIT(3); 1518c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else { 1519c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= 1520c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK)); 1521c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= 1522c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK)); 1523c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1524c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1525c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_BANK_SWAPS(1); 1526c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1527d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher cc_rb_backend_disable = RADEON_READ(R600_CC_RB_BACKEND_DISABLE) & 0x00ff0000; 1528d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher cc_rb_backend_disable |= 1529d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK); 1530c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1531d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher cc_gc_shader_pipe_config = RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; 1532d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher cc_gc_shader_pipe_config |= 1533c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK); 1534c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cc_gc_shader_pipe_config |= 1535c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK); 1536c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1537d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740) 1538d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher backend_map = 0x28; 1539d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher else 1540d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher backend_map = r700_get_tile_pipe_to_backend_map(dev_priv, 1541d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher dev_priv->r600_max_tile_pipes, 1542d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher (R7XX_MAX_BACKENDS - 1543d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher r600_count_pipe_bits((cc_rb_backend_disable & 1544d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher R7XX_MAX_BACKENDS_MASK) >> 16)), 1545d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher (cc_rb_backend_disable >> 16)); 1546d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher gb_tiling_config |= R600_BACKEND_MAP(backend_map); 1547c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1548c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); 1549c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1550c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1551961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse if (gb_tiling_config & 0xc0) { 1552961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse dev_priv->r600_group_size = 512; 1553961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse } else { 1554961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse dev_priv->r600_group_size = 256; 1555961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse } 1556961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7); 1557961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse if (gb_tiling_config & 0x30) { 1558961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse dev_priv->r600_nbanks = 8; 1559961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse } else { 1560961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse dev_priv->r600_nbanks = 4; 1561961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse } 1562c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1563c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 1564c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 1565f867c60def7a8dcd86657fd38a8920a4354f305eAlex Deucher RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 1566c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1567c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); 1568c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0); 1569c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0); 1570f867c60def7a8dcd86657fd38a8920a4354f305eAlex Deucher RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0); 1571f867c60def7a8dcd86657fd38a8920a4354f305eAlex Deucher RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0); 1572c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1573c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_qd_pipes = 1574d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8); 1575c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK); 1576c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK); 1577c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1578c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* set HW defaults for 3D engine */ 1579c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) | 1580c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ROQ_IB2_START(0x2b))); 1581c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1582c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30)); 1583c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1584d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher ta_aux_cntl = RADEON_READ(R600_TA_CNTL_AUX); 1585d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher RADEON_WRITE(R600_TA_CNTL_AUX, ta_aux_cntl | R600_DISABLE_CUBE_ANISO); 1586c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1587c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1); 1588c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS; 1589c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1); 1590c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1591c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0); 1592c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff); 1593c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1); 1594c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0); 1595c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1596d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV740) 1597d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) | 1598d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher R700_GS_FLUSH_CTL(4) | 1599d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher R700_ACK_FLUSH_CTL(3) | 1600d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher R700_SYNC_FLUSH_CTL)); 1601c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1602d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher db_debug3 = RADEON_READ(R700_DB_DEBUG3); 1603d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher db_debug3 &= ~R700_DB_CLK_OFF_DELAY(0x1f); 1604d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1605d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher case CHIP_RV770: 1606d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher case CHIP_RV740: 1607d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher db_debug3 |= R700_DB_CLK_OFF_DELAY(0x1f); 1608d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher break; 1609d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher case CHIP_RV710: 1610d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher case CHIP_RV730: 1611d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher default: 1612d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher db_debug3 |= R700_DB_CLK_OFF_DELAY(2); 1613d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher break; 1614d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher } 1615d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher RADEON_WRITE(R700_DB_DEBUG3, db_debug3); 1616d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher 1617d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV770) { 1618c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher db_debug4 = RADEON_READ(RV700_DB_DEBUG4); 1619c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER; 1620c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(RV700_DB_DEBUG4, db_debug4); 1621c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1622c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1623c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) | 1624c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) | 1625c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1))); 1626c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1627c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) | 1628c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) | 1629c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize))); 1630c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1631c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1632c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1633c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1); 1634c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1635c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0)); 1636c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1637c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4)); 1638c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1639c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PERFMON_CNTL, 0); 1640c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1641c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) | 1642c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_DONE_FIFO_HIWATER(0xe0) | 1643c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ALU_UPDATE_FIFO_HIWATER(0x8)); 1644c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1645c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV770: 1646c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV730: 1647c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV710: 1648d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1); 1649d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher break; 16502a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher case CHIP_RV740: 1651c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 1652c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4); 1653c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1654c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1655c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 1656c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1657c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 1658c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * should be adjusted as needed by the 2D/3D drivers. This just sets default values 1659c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 1660c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config = RADEON_READ(R600_SQ_CONFIG); 1661c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config &= ~(R600_PS_PRIO(3) | 1662c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VS_PRIO(3) | 1663c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_GS_PRIO(3) | 1664c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ES_PRIO(3)); 1665c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config |= (R600_DX9_CONSTS | 1666c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VC_ENABLE | 1667c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_EXPORT_SRC_C | 1668c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_PS_PRIO(0) | 1669c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VS_PRIO(1) | 1670c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_GS_PRIO(2) | 1671c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ES_PRIO(3)); 1672c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) 1673c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* no vertex cache */ 1674c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config &= ~R600_VC_ENABLE; 1675c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1676c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_CONFIG, sq_config); 1677c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1678c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) | 1679c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) | 1680c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2))); 1681c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1682c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) | 1683c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64))); 1684c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1685c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) | 1686c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) | 1687c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8)); 1688c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads) 1689c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads); 1690c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 1691c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8); 1692c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1693c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1694c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) | 1695c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); 1696c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1697c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) | 1698c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); 1699c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1700c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) | 1701c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) | 1702c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) | 1703c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64)); 1704c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1705c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); 1706c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); 1707c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); 1708c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); 1709c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); 1710c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); 1711c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); 1712c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); 1713c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1714c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) | 1715c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_FORCE_EOV_MAX_REZ_CNT(255))); 1716c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1717c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) 1718c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) | 1719c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO))); 1720c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 1721c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) | 1722c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO))); 1723c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1724c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1725c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV770: 1726c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV730: 17272a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher case CHIP_RV740: 1728c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gs_prim_buffer_depth = 384; 1729c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1730c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV710: 1731c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gs_prim_buffer_depth = 128; 1732c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1733c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 1734c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1735c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1736c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1737c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; 1738c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 1739c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Max value for this is 256 */ 1740c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (vgt_gs_per_es > 256) 1741c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vgt_gs_per_es = 256; 1742c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1743c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_ES_PER_GS, 128); 1744c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es); 1745c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_GS_PER_VS, 2); 1746c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1747c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* more default values. 2D/3D driver should adjust as needed */ 1748c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16); 1749c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0); 1750c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_STRMOUT_EN, 0); 1751c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SX_MISC, 0); 1752c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0); 1753c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa); 1754c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0); 1755c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff); 1756c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0); 1757c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_INPUT_Z, 0); 1758c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2)); 1759c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR7_FRAG, 0); 1760c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1761c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* clear render buffer base addresses */ 1762c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR0_BASE, 0); 1763c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR1_BASE, 0); 1764c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR2_BASE, 0); 1765c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR3_BASE, 0); 1766c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR4_BASE, 0); 1767c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR5_BASE, 0); 1768c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR6_BASE, 0); 1769c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR7_BASE, 0); 1770c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1771c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_TCP_CNTL, 0); 1772c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1773c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL); 1774c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1775c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1776c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1777c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1778c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA | 1779c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_CLIP_SEQ(3))); 1780c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1781c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 1782c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1783c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r600_cp_init_ring_buffer(struct drm_device *dev, 1784c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv, 1785c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_file *file_priv) 1786c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 1787c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_radeon_master_private *master_priv; 1788c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 ring_start; 17896546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie u64 rptr_addr; 1790c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1791c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 1792c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r700_gfx_init(dev, dev_priv); 1793c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 1794c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_gfx_init(dev, dev_priv); 1795c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1796c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 1797c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_SOFT_RESET); 1798c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(15000); 1799c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 1800c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1801c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1802c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Set ring buffer size */ 1803c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#ifdef __BIG_ENDIAN 1804c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 1805c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_BUF_SWAP_32BIT | 1806c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_RB_NO_UPDATE | 1807c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->ring.rptr_update_l2qw << 8) | 1808c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size_l2qw); 1809c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#else 1810c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 1811c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_RB_NO_UPDATE | 1812c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->ring.rptr_update_l2qw << 8) | 1813c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size_l2qw); 1814c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 1815c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1816c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x4); 1817c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1818c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Set the write pointer delay */ 1819c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); 1820c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1821c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#ifdef __BIG_ENDIAN 1822c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 1823c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_BUF_SWAP_32BIT | 1824c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_RB_NO_UPDATE | 1825c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_RB_RPTR_WR_ENA | 1826c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->ring.rptr_update_l2qw << 8) | 1827c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size_l2qw); 1828c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#else 1829c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 1830c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_RB_NO_UPDATE | 1831c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_RB_RPTR_WR_ENA | 1832c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->ring.rptr_update_l2qw << 8) | 1833c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size_l2qw); 1834c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 1835c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1836c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Initialize the ring buffer's read and write pointers */ 1837c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_RPTR_WR, 0); 1838c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_WPTR, 0); 1839c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher SET_RING_HEAD(dev_priv, 0); 1840c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.tail = 0; 1841c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1842c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#if __OS_HAS_AGP 1843c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->flags & RADEON_IS_AGP) { 18446546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie rptr_addr = dev_priv->ring_rptr->offset 18456546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie - dev->agp->base + 18466546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie dev_priv->gart_vm_start; 1847c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else 1848c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 1849c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher { 18506546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie rptr_addr = dev_priv->ring_rptr->offset 18516546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie - ((unsigned long) dev->sg->virtual) 18526546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie + dev_priv->gart_vm_start; 1853c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 18546546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie RADEON_WRITE(R600_CP_RB_RPTR_ADDR, 1855dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano#ifdef __BIG_ENDIAN 1856dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano (2 << 0) | 1857dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano#endif 1858dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano (rptr_addr & 0xfffffffc)); 18596546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI, 18606546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie upper_32_bits(rptr_addr)); 1861c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1862c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#ifdef __BIG_ENDIAN 1863c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 1864c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_BUF_SWAP_32BIT | 1865c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->ring.rptr_update_l2qw << 8) | 1866c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size_l2qw); 1867c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#else 1868c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 1869c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->ring.rptr_update_l2qw << 8) | 1870c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size_l2qw); 1871c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 1872c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1873c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#if __OS_HAS_AGP 1874c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->flags & RADEON_IS_AGP) { 1875c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* XXX */ 1876c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_write_agp_base(dev_priv, dev->agp->base); 1877c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1878c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* XXX */ 1879c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_write_agp_location(dev_priv, 1880c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (((dev_priv->gart_vm_start - 1 + 1881c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_size) & 0xffff0000) | 1882c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->gart_vm_start >> 16))); 1883c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1884c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ring_start = (dev_priv->cp_ring->offset 1885c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher - dev->agp->base 1886c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + dev_priv->gart_vm_start); 1887c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else 1888c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 1889c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ring_start = (dev_priv->cp_ring->offset 1890c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher - (unsigned long)dev->sg->virtual 1891c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + dev_priv->gart_vm_start); 1892c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1893c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8); 1894c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1895c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_CNTL, 0xff); 1896c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1897c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28)); 1898c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1899c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Initialize the scratch register pointer. This will cause 1900c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * the scratch register values to be written out to memory 1901c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * whenever they are updated. 1902c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * 1903c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * We simply put this behind the ring read pointer, this works 1904c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * with PCI GART as well as (whatever kind of) AGP GART 1905c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 19066546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie { 19076546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie u64 scratch_addr; 19086546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie 1909dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR) & 0xFFFFFFFC; 19106546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32; 19116546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie scratch_addr += R600_SCRATCH_REG_OFFSET; 19126546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie scratch_addr >>= 8; 19136546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie scratch_addr &= 0xffffffff; 19146546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie 19156546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr); 19166546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie } 1917c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1918c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SCRATCH_UMSK, 0x7); 1919c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1920c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Turn on bus mastering */ 1921c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_enable_bm(dev_priv); 1922c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1923c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0); 1924c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_LAST_FRAME_REG, 0); 1925c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1926c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0); 1927c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_LAST_DISPATCH_REG, 0); 1928c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1929c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0); 1930c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_LAST_CLEAR_REG, 0); 1931c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1932c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* reset sarea copies of these */ 1933c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher master_priv = file_priv->master->driver_priv; 1934c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (master_priv->sarea_priv) { 1935c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher master_priv->sarea_priv->last_frame = 0; 1936c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher master_priv->sarea_priv->last_dispatch = 0; 1937c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher master_priv->sarea_priv->last_clear = 0; 1938c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1939c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1940c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_wait_for_idle(dev_priv); 1941c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1942c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 1943c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1944c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherint r600_do_cleanup_cp(struct drm_device *dev) 1945c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 1946c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 1947c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("\n"); 1948c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1949c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Make sure interrupts are disabled here because the uninstall ioctl 1950c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * may not have been called from userspace and after dev_private 1951c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * is freed, it's too late. 1952c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 1953c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev->irq_enabled) 1954c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_irq_uninstall(dev); 1955c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1956c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#if __OS_HAS_AGP 1957c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->flags & RADEON_IS_AGP) { 1958c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->cp_ring != NULL) { 1959c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_core_ioremapfree(dev_priv->cp_ring, dev); 1960c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_ring = NULL; 1961c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1962c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->ring_rptr != NULL) { 1963c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_core_ioremapfree(dev_priv->ring_rptr, dev); 1964c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring_rptr = NULL; 1965c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1966c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev->agp_buffer_map != NULL) { 1967c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_core_ioremapfree(dev->agp_buffer_map, dev); 1968c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev->agp_buffer_map = NULL; 1969c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1970c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else 1971c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 1972c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher { 1973c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1974c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->gart_info.bus_addr) 1975c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_page_table_cleanup(dev, &dev_priv->gart_info); 1976c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1977c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) { 1978c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); 19798f497aade8df2a619eacda927a43ebe82167a84cHannes Eder dev_priv->gart_info.addr = NULL; 1980c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1981c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1982c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* only clear to the start of flags */ 1983c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); 1984c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1985c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return 0; 1986c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 1987c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1988c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherint r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, 1989c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_file *file_priv) 1990c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 1991c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 1992c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; 1993c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1994c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("\n"); 1995c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 19963ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse mutex_init(&dev_priv->cs_mutex); 19973ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse r600_cs_legacy_init(); 1998c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* if we require new memory map but we don't have it fail */ 1999c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { 2000c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); 2001c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2002c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2003c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2004c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2005c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) { 2006c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("Forcing AGP card to PCI mode\n"); 2007c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->flags &= ~RADEON_IS_AGP; 2008c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* The writeback test succeeds, but when writeback is enabled, 2009c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * the ring buffer read ptr update fails after first 128 bytes. 2010c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 2011c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_no_wb = 1; 2012c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) 2013c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher && !init->is_pci) { 2014c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("Restoring AGP flag\n"); 2015c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->flags |= RADEON_IS_AGP; 2016c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2017c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2018c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->usec_timeout = init->usec_timeout; 2019c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->usec_timeout < 1 || 2020c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { 2021c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("TIMEOUT problem!\n"); 2022c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2023c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2024c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2025c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2026c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Enable vblank on CRTC1 for older X servers 2027c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 2028c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; 20293ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse dev_priv->do_boxes = 0; 2030c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_mode = init->cp_mode; 2031c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2032c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* We don't support anything other than bus-mastering ring mode, 2033c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * but the ring can be in either AGP or PCI space for the ring 2034c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * read pointer. 2035c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 2036c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && 2037c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { 2038c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); 2039c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2040c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2041c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2042c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2043c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (init->fb_bpp) { 2044c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 16: 2045c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; 2046c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 2047c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 32: 2048c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 2049c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; 2050c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 2051c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2052c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->front_offset = init->front_offset; 2053c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->front_pitch = init->front_pitch; 2054c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->back_offset = init->back_offset; 2055c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->back_pitch = init->back_pitch; 2056c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2057c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring_offset = init->ring_offset; 2058c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring_rptr_offset = init->ring_rptr_offset; 2059c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->buffers_offset = init->buffers_offset; 2060c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_textures_offset = init->gart_textures_offset; 2061c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2062c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher master_priv->sarea = drm_getsarea(dev); 2063c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!master_priv->sarea) { 2064c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("could not find sarea!\n"); 2065c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2066c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2067c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2068c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2069c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); 2070c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev_priv->cp_ring) { 2071c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("could not find cp ring region!\n"); 2072c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2073c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2074c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2075c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); 2076c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev_priv->ring_rptr) { 2077c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("could not find ring read pointer!\n"); 2078c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2079c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2080c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2081c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev->agp_buffer_token = init->buffers_offset; 2082c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); 2083c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev->agp_buffer_map) { 2084c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("could not find dma buffer region!\n"); 2085c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2086c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2087c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2088c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2089c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (init->gart_textures_offset) { 2090c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_textures = 2091c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_core_findmap(dev, init->gart_textures_offset); 2092c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev_priv->gart_textures) { 2093c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("could not find GART texture region!\n"); 2094c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2095c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2096c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2097c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2098c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2099c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#if __OS_HAS_AGP 2100c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* XXX */ 2101c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->flags & RADEON_IS_AGP) { 21027659e9804b7a66047433182d86393d38ba4eff79Alex Deucher drm_core_ioremap_wc(dev_priv->cp_ring, dev); 21037659e9804b7a66047433182d86393d38ba4eff79Alex Deucher drm_core_ioremap_wc(dev_priv->ring_rptr, dev); 21047659e9804b7a66047433182d86393d38ba4eff79Alex Deucher drm_core_ioremap_wc(dev->agp_buffer_map, dev); 2105c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev_priv->cp_ring->handle || 2106c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher !dev_priv->ring_rptr->handle || 2107c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher !dev->agp_buffer_map->handle) { 2108c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("could not find ioremap agp regions!\n"); 2109c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2110c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2111c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2112c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else 2113c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 2114c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher { 21153ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse dev_priv->cp_ring->handle = (void *)(unsigned long)dev_priv->cp_ring->offset; 2116c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring_rptr->handle = 21173ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse (void *)(unsigned long)dev_priv->ring_rptr->offset; 2118c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev->agp_buffer_map->handle = 21193ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse (void *)(unsigned long)dev->agp_buffer_map->offset; 2120c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2121c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("dev_priv->cp_ring->handle %p\n", 2122c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_ring->handle); 2123c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", 2124c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring_rptr->handle); 2125c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("dev->agp_buffer_map->handle %p\n", 2126c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev->agp_buffer_map->handle); 2127c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2128c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2129c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24; 2130c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->fb_size = 2131c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000) 2132c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher - dev_priv->fb_location; 2133c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2134c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | 2135c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->front_offset 2136c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + dev_priv->fb_location) >> 10)); 2137c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2138c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | 2139c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->back_offset 2140c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + dev_priv->fb_location) >> 10)); 2141c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2142c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | 2143c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->depth_offset 2144c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + dev_priv->fb_location) >> 10)); 2145c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2146c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_size = init->gart_size; 2147c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2148c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* New let's set the memory map ... */ 2149c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->new_memmap) { 2150c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 base = 0; 2151c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2152c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Setting GART location based on new memory map\n"); 2153c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2154c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* If using AGP, try to locate the AGP aperture at the same 2155c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * location in the card and on the bus, though we have to 2156c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * align it down. 2157c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 2158c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#if __OS_HAS_AGP 2159c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* XXX */ 2160c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->flags & RADEON_IS_AGP) { 2161c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher base = dev->agp->base; 2162c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Check if valid */ 2163c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && 2164c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { 2165c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n", 2166c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev->agp->base); 2167c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher base = 0; 2168c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2169c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2170c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 2171c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* If not or if AGP is at 0 (Macs), try to put it elsewhere */ 2172c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (base == 0) { 2173c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher base = dev_priv->fb_location + dev_priv->fb_size; 2174c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (base < dev_priv->fb_location || 2175c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((base + dev_priv->gart_size) & 0xfffffffful) < base) 2176c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher base = dev_priv->fb_location 2177c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher - dev_priv->gart_size; 2178c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2179c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_vm_start = base & 0xffc00000u; 2180c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->gart_vm_start != base) 2181c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n", 2182c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher base, dev_priv->gart_vm_start); 2183c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2184c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2185c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#if __OS_HAS_AGP 2186c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* XXX */ 2187c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->flags & RADEON_IS_AGP) 2188c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 2189c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher - dev->agp->base 2190c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + dev_priv->gart_vm_start); 2191c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 2192c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 2193c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 2194c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher - (unsigned long)dev->sg->virtual 2195c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + dev_priv->gart_vm_start); 2196c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2197c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("fb 0x%08x size %d\n", 2198c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (unsigned int) dev_priv->fb_location, 2199c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (unsigned int) dev_priv->fb_size); 2200c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); 2201c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n", 2202c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (unsigned int) dev_priv->gart_vm_start); 2203c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n", 2204c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_buffers_offset); 2205c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2206c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; 2207c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle 2208c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + init->ring_size / sizeof(u32)); 2209c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size = init->ring_size; 2210c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); 2211c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2212c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; 2213c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8); 2214c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2215c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.fetch_size = /* init->fetch_size */ 32; 2216c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16); 2217c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2218c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; 2219c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2220c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; 2221c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2222c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#if __OS_HAS_AGP 2223c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->flags & RADEON_IS_AGP) { 2224c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* XXX turn off pcie gart */ 2225c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else 2226c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 2227c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher { 2228c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); 2229c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* if we have an offset set from userspace */ 2230c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev_priv->pcigart_offset_set) { 2231c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("Need gart offset from userspace\n"); 2232c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2233c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2234c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2235c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2236c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset); 2237c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2238c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.bus_addr = 2239c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->pcigart_offset + dev_priv->fb_location; 2240c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.mapping.offset = 2241c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->pcigart_offset + dev_priv->fb_aper_offset; 2242c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.mapping.size = 2243c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.table_size; 2244c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2245c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev); 2246c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev_priv->gart_info.mapping.handle) { 2247c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("ioremap failed.\n"); 2248c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2249c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2250c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2251c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2252c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.addr = 2253c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.mapping.handle; 2254c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2255c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n", 2256c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.addr, 2257c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->pcigart_offset); 2258c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 225941f13fe81dd1b08723ab9f3fc3c7f29cfa81f1a5Alex Deucher if (!r600_page_table_init(dev)) { 2260c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("Failed to init GART table\n"); 2261c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2262c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2263c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2264c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2265c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 2266c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r700_vm_init(dev); 2267c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 2268c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_vm_init(dev); 2269c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2270c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 227170967ab9c0c9017645d167d33675eab996633631Ben Hutchings if (!dev_priv->me_fw || !dev_priv->pfp_fw) { 227270967ab9c0c9017645d167d33675eab996633631Ben Hutchings int err = r600_cp_init_microcode(dev_priv); 227370967ab9c0c9017645d167d33675eab996633631Ben Hutchings if (err) { 227470967ab9c0c9017645d167d33675eab996633631Ben Hutchings DRM_ERROR("Failed to load firmware!\n"); 227570967ab9c0c9017645d167d33675eab996633631Ben Hutchings r600_do_cleanup_cp(dev); 227670967ab9c0c9017645d167d33675eab996633631Ben Hutchings return err; 227770967ab9c0c9017645d167d33675eab996633631Ben Hutchings } 227870967ab9c0c9017645d167d33675eab996633631Ben Hutchings } 2279c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 2280c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r700_cp_load_microcode(dev_priv); 2281c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 2282c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_cp_load_microcode(dev_priv); 2283c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2284c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_cp_init_ring_buffer(dev, dev_priv, file_priv); 2285c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2286c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->last_buf = 0; 2287c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2288c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_engine_reset(dev); 2289c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_test_writeback(dev_priv); 2290c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2291c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return 0; 2292c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 2293c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2294c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherint r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv) 2295c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 2296c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 2297c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2298c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("\n"); 2299c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) { 2300c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r700_vm_init(dev); 2301c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r700_cp_load_microcode(dev_priv); 2302c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else { 2303c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_vm_init(dev); 2304c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_cp_load_microcode(dev_priv); 2305c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2306c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_cp_init_ring_buffer(dev, dev_priv, file_priv); 2307c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_engine_reset(dev); 2308c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2309c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return 0; 2310c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 2311c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2312c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher/* Wait for the CP to go idle. 2313c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 2314c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherint r600_do_cp_idle(drm_radeon_private_t *dev_priv) 2315c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 2316c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RING_LOCALS; 2317c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("\n"); 2318c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2319c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher BEGIN_RING(5); 2320c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); 2321c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT); 2322c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* wait for 3D idle clean */ 2323c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); 2324c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2); 2325c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN); 2326c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2327c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ADVANCE_RING(); 2328c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher COMMIT_RING(); 2329c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2330c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return r600_do_wait_for_idle(dev_priv); 2331c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 2332c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2333c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher/* Start the Command Processor. 2334c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 2335c05ce0834a268f7d18274847190f6ed826b99332Alex Deuchervoid r600_do_cp_start(drm_radeon_private_t *dev_priv) 2336c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 2337c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cp_me; 2338c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RING_LOCALS; 2339c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("\n"); 2340c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2341c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher BEGIN_RING(7); 2342c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5)); 2343c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(0x00000001); 2344c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) 2345c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(0x00000003); 2346c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 2347c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(0x00000000); 2348c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING((dev_priv->r600_max_hw_contexts - 1)); 2349c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1)); 2350c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(0x00000000); 2351c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(0x00000000); 2352c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ADVANCE_RING(); 2353c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher COMMIT_RING(); 2354c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2355c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* set the mux and reset the halt bit */ 2356c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cp_me = 0xff; 2357c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_CNTL, cp_me); 2358c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2359c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_running = 1; 2360c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2361c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 2362c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2363c05ce0834a268f7d18274847190f6ed826b99332Alex Deuchervoid r600_do_cp_reset(drm_radeon_private_t *dev_priv) 2364c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 2365c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cur_read_ptr; 2366c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("\n"); 2367c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2368c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR); 2369c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr); 2370c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher SET_RING_HEAD(dev_priv, cur_read_ptr); 2371c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.tail = cur_read_ptr; 2372c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 2373c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2374c05ce0834a268f7d18274847190f6ed826b99332Alex Deuchervoid r600_do_cp_stop(drm_radeon_private_t *dev_priv) 2375c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 2376c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher uint32_t cp_me; 2377c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2378c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("\n"); 2379c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2380c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cp_me = 0xff | R600_CP_ME_HALT; 2381c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2382c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_CNTL, cp_me); 2383c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2384c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_running = 0; 2385c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 2386c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2387c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherint r600_cp_dispatch_indirect(struct drm_device *dev, 2388c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_buf *buf, int start, int end) 2389c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 2390c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 2391c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RING_LOCALS; 2392c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2393c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (start != end) { 2394c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher unsigned long offset = (dev_priv->gart_buffers_offset 2395c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + buf->offset + start); 2396c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int dwords = (end - start + 3) / sizeof(u32); 2397c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2398c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("dwords:%d\n", dwords); 2399c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("offset 0x%lx\n", offset); 2400c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2401c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2402c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Indirect buffer data must be a multiple of 16 dwords. 2403c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * pad the data with a Type-2 CP packet. 2404c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 2405c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher while (dwords & 0xf) { 2406c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 *data = (u32 *) 2407c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((char *)dev->agp_buffer_map->handle 2408c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + buf->offset + start); 2409c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher data[dwords++] = RADEON_CP_PACKET2; 2410c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2411c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2412c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Fire off the indirect buffer */ 2413c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher BEGIN_RING(4); 2414c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2)); 2415c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING((offset & 0xfffffffc)); 2416c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING((upper_32_bits(offset) & 0xff)); 2417c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(dwords); 2418c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ADVANCE_RING(); 2419c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2420c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2421c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return 0; 2422c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 24233ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 24243ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glissevoid r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv) 24253ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse{ 24263ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse drm_radeon_private_t *dev_priv = dev->dev_private; 24273ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse struct drm_master *master = file_priv->master; 24283ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse struct drm_radeon_master_private *master_priv = master->driver_priv; 24293ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; 24303ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse int nbox = sarea_priv->nbox; 24313ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse struct drm_clip_rect *pbox = sarea_priv->boxes; 24323ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse int i, cpp, src_pitch, dst_pitch; 24333ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse uint64_t src, dst; 24343ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse RING_LOCALS; 24353ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse DRM_DEBUG("\n"); 24363ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 24373ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (dev_priv->color_fmt == RADEON_COLOR_FORMAT_ARGB8888) 24383ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse cpp = 4; 24393ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse else 24403ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse cpp = 2; 24413ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 24423ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (sarea_priv->pfCurrentPage == 0) { 24433ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse src_pitch = dev_priv->back_pitch; 24443ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse dst_pitch = dev_priv->front_pitch; 24453ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse src = dev_priv->back_offset + dev_priv->fb_location; 24463ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse dst = dev_priv->front_offset + dev_priv->fb_location; 24473ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } else { 24483ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse src_pitch = dev_priv->front_pitch; 24493ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse dst_pitch = dev_priv->back_pitch; 24503ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse src = dev_priv->front_offset + dev_priv->fb_location; 24513ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse dst = dev_priv->back_offset + dev_priv->fb_location; 24523ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 24533ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 24543ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (r600_prepare_blit_copy(dev, file_priv)) { 24553ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse DRM_ERROR("unable to allocate vertex buffer for swap buffer\n"); 24563ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return; 24573ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 24583ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse for (i = 0; i < nbox; i++) { 24593ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse int x = pbox[i].x1; 24603ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse int y = pbox[i].y1; 24613ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse int w = pbox[i].x2 - x; 24623ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse int h = pbox[i].y2 - y; 24633ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 24643ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h); 24653ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 24663ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse r600_blit_swap(dev, 24673ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse src, dst, 24683ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse x, y, x, y, w, h, 24693ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse src_pitch, dst_pitch, cpp); 24703ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 24713ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse r600_done_blit_copy(dev); 24723ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 24733ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse /* Increment the frame counter. The client-side 3D driver must 24743ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse * throttle the framerate by waiting for this value before 24753ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse * performing the swapbuffer ioctl. 24763ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse */ 24773ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse sarea_priv->last_frame++; 24783ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 24793ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse BEGIN_RING(3); 24803ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse R600_FRAME_AGE(sarea_priv->last_frame); 24813ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse ADVANCE_RING(); 24823ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse} 24833ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 24843ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisseint r600_cp_dispatch_texture(struct drm_device *dev, 24853ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse struct drm_file *file_priv, 24863ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse drm_radeon_texture_t *tex, 24873ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse drm_radeon_tex_image_t *image) 24883ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse{ 24893ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse drm_radeon_private_t *dev_priv = dev->dev_private; 24903ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse struct drm_buf *buf; 24913ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse u32 *buffer; 24923ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse const u8 __user *data; 24933ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse int size, pass_size; 24943ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse u64 src_offset, dst_offset; 24953ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 24963ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (!radeon_check_offset(dev_priv, tex->offset)) { 24973ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse DRM_ERROR("Invalid destination offset\n"); 24983ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return -EINVAL; 24993ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 25003ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25013ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse /* this might fail for zero-sized uploads - are those illegal? */ 25023ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (!radeon_check_offset(dev_priv, tex->offset + tex->height * tex->pitch - 1)) { 25033ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse DRM_ERROR("Invalid final destination offset\n"); 25043ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return -EINVAL; 25053ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 25063ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25073ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse size = tex->height * tex->pitch; 25083ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25093ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (size == 0) 25103ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return 0; 25113ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25123ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse dst_offset = tex->offset; 25133ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25143ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (r600_prepare_blit_copy(dev, file_priv)) { 25153ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse DRM_ERROR("unable to allocate vertex buffer for swap buffer\n"); 25163ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return -EAGAIN; 25173ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 25183ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse do { 25193ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse data = (const u8 __user *)image->data; 25203ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse pass_size = size; 25213ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25223ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse buf = radeon_freelist_get(dev); 25233ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (!buf) { 25243ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse DRM_DEBUG("EAGAIN\n"); 25253ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image))) 25263ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return -EFAULT; 25273ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return -EAGAIN; 25283ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 25293ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25303ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (pass_size > buf->total) 25313ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse pass_size = buf->total; 25323ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25333ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse /* Dispatch the indirect buffer. 25343ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse */ 25353ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse buffer = 25363ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset); 25373ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25383ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (DRM_COPY_FROM_USER(buffer, data, pass_size)) { 25393ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse DRM_ERROR("EFAULT on pad, %d bytes\n", pass_size); 25403ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return -EFAULT; 25413ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 25423ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25433ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse buf->file_priv = file_priv; 25443ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse buf->used = pass_size; 25453ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse src_offset = dev_priv->gart_buffers_offset + buf->offset; 25463ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25473ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse r600_blit_copy(dev, src_offset, dst_offset, pass_size); 25483ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25493ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse radeon_cp_discard_buffer(dev, file_priv->master, buf); 25503ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25513ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse /* Update the input parameters for next time */ 25523ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse image->data = (const u8 __user *)image->data + pass_size; 25533ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse dst_offset += pass_size; 25543ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse size -= pass_size; 25553ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } while (size > 0); 25563ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse r600_done_blit_copy(dev); 25573ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25583ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return 0; 25593ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse} 25603ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25613ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse/* 25623ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse * Legacy cs ioctl 25633ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse */ 25643ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glissestatic u32 radeon_cs_id_get(struct drm_radeon_private *radeon) 25653ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse{ 25663ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse /* FIXME: check if wrap affect last reported wrap & sequence */ 25673ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse radeon->cs_id_scnt = (radeon->cs_id_scnt + 1) & 0x00FFFFFF; 25683ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (!radeon->cs_id_scnt) { 25693ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse /* increment wrap counter */ 25703ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse radeon->cs_id_wcnt += 0x01000000; 25713ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse /* valid sequence counter start at 1 */ 25723ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse radeon->cs_id_scnt = 1; 25733ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 25743ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return (radeon->cs_id_scnt | radeon->cs_id_wcnt); 25753ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse} 25763ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25773ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glissestatic void r600_cs_id_emit(drm_radeon_private_t *dev_priv, u32 *id) 25783ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse{ 25793ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse RING_LOCALS; 25803ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25813ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse *id = radeon_cs_id_get(dev_priv); 25823ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25833ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse /* SCRATCH 2 */ 25843ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse BEGIN_RING(3); 25853ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse R600_CLEAR_AGE(*id); 25863ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse ADVANCE_RING(); 25873ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse COMMIT_RING(); 25883ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse} 25893ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25903ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glissestatic int r600_ib_get(struct drm_device *dev, 25913ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse struct drm_file *fpriv, 25923ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse struct drm_buf **buffer) 25933ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse{ 25943ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse struct drm_buf *buf; 25953ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25963ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse *buffer = NULL; 25973ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse buf = radeon_freelist_get(dev); 25983ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (!buf) { 25993ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return -EBUSY; 26003ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 26013ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse buf->file_priv = fpriv; 26023ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse *buffer = buf; 26033ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return 0; 26043ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse} 26053ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 26063ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glissestatic void r600_ib_free(struct drm_device *dev, struct drm_buf *buf, 26073ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse struct drm_file *fpriv, int l, int r) 26083ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse{ 26093ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse drm_radeon_private_t *dev_priv = dev->dev_private; 26103ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 26113ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (buf) { 26123ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (!r) 26133ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse r600_cp_dispatch_indirect(dev, buf, 0, l * 4); 26143ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse radeon_cp_discard_buffer(dev, fpriv->master, buf); 26153ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse COMMIT_RING(); 26163ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 26173ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse} 26183ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 26193ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisseint r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv) 26203ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse{ 26213ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse struct drm_radeon_private *dev_priv = dev->dev_private; 26223ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse struct drm_radeon_cs *cs = data; 26233ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse struct drm_buf *buf; 26243ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse unsigned family; 26253ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse int l, r = 0; 26263ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse u32 *ib, cs_id = 0; 26273ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 26283ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (dev_priv == NULL) { 26293ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse DRM_ERROR("called with no initialization\n"); 26303ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return -EINVAL; 26313ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 26323ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse family = dev_priv->flags & RADEON_FAMILY_MASK; 26333ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (family < CHIP_R600) { 26343ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse DRM_ERROR("cs ioctl valid only for R6XX & R7XX in legacy mode\n"); 26353ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return -EINVAL; 26363ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 26373ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse mutex_lock(&dev_priv->cs_mutex); 26383ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse /* get ib */ 26393ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse r = r600_ib_get(dev, fpriv, &buf); 26403ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (r) { 26413ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse DRM_ERROR("ib_get failed\n"); 26423ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse goto out; 26433ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 26443ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse ib = dev->agp_buffer_map->handle + buf->offset; 26453ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse /* now parse command stream */ 26463ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse r = r600_cs_legacy(dev, data, fpriv, family, ib, &l); 26473ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (r) { 26483ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse goto out; 26493ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 26503ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 26513ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisseout: 26523ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse r600_ib_free(dev, buf, fpriv, l, r); 26533ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse /* emit cs id sequence */ 26543ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse r600_cs_id_emit(dev_priv, &cs_id); 26553ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse cs->cs_id = cs_id; 26563ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse mutex_unlock(&dev_priv->cs_mutex); 26573ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return r; 26583ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse} 2659961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse 2660961fb597c17e2e4f55407d56b7211c188ab41effJerome Glissevoid r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size) 2661961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse{ 2662961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse struct drm_radeon_private *dev_priv = dev->dev_private; 2663961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse 2664961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse *npipes = dev_priv->r600_npipes; 2665961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse *nbanks = dev_priv->r600_nbanks; 2666961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse *group_size = dev_priv->r600_group_size; 2667961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse} 2668