r600_cp.c revision ef8cf3a1c523afa499d15856e7db3844ad59d1fb
1c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher/* 2c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Copyright 2008-2009 Advanced Micro Devices, Inc. 3c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Copyright 2008 Red Hat Inc. 4c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * 5c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 6c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * copy of this software and associated documentation files (the "Software"), 7c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * to deal in the Software without restriction, including without limitation 8c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * and/or sell copies of the Software, and to permit persons to whom the 10c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Software is furnished to do so, subject to the following conditions: 11c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * 12c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * The above copyright notice and this permission notice (including the next 13c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * paragraph) shall be included in all copies or substantial portions of the 14c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Software. 15c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * 16c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * DEALINGS IN THE SOFTWARE. 23c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * 24c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Authors: 25c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Dave Airlie <airlied@redhat.com> 26c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * Alex Deucher <alexander.deucher@amd.com> 27c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 28c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 29e0cd3608135b2ed8eddbe3fdf048d22e0593d836Paul Gortmaker#include <linux/module.h> 30e0cd3608135b2ed8eddbe3fdf048d22e0593d836Paul Gortmaker 31760285e7e7ab282c25b5e90816f7c47000557f4fDavid Howells#include <drm/drmP.h> 32760285e7e7ab282c25b5e90816f7c47000557f4fDavid Howells#include <drm/radeon_drm.h> 33c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#include "radeon_drv.h" 34c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 3570967ab9c0c9017645d167d33675eab996633631Ben Hutchings#define PFP_UCODE_SIZE 576 3670967ab9c0c9017645d167d33675eab996633631Ben Hutchings#define PM4_UCODE_SIZE 1792 3770967ab9c0c9017645d167d33675eab996633631Ben Hutchings#define R700_PFP_UCODE_SIZE 848 3870967ab9c0c9017645d167d33675eab996633631Ben Hutchings#define R700_PM4_UCODE_SIZE 1360 3970967ab9c0c9017645d167d33675eab996633631Ben Hutchings 4070967ab9c0c9017645d167d33675eab996633631Ben Hutchings/* Firmware Names */ 4170967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/R600_pfp.bin"); 4270967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/R600_me.bin"); 4370967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV610_pfp.bin"); 4470967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV610_me.bin"); 4570967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV630_pfp.bin"); 4670967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV630_me.bin"); 4770967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV620_pfp.bin"); 4870967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV620_me.bin"); 4970967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV635_pfp.bin"); 5070967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV635_me.bin"); 5170967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV670_pfp.bin"); 5270967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV670_me.bin"); 5370967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RS780_pfp.bin"); 5470967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RS780_me.bin"); 5570967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV770_pfp.bin"); 5670967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV770_me.bin"); 5770967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV730_pfp.bin"); 5870967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV730_me.bin"); 5970967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV710_pfp.bin"); 6070967ab9c0c9017645d167d33675eab996633631Ben HutchingsMODULE_FIRMWARE("radeon/RV710_me.bin"); 61c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 623ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 633ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisseint r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp, 643ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse unsigned family, u32 *ib, int *l); 653ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glissevoid r600_cs_legacy_init(void); 663ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 673ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 68c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ 69c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher# define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1)) 70c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 71c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R600_PTE_VALID (1 << 0) 72c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R600_PTE_SYSTEM (1 << 1) 73c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R600_PTE_SNOOPED (1 << 2) 74c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R600_PTE_READABLE (1 << 5) 75c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R600_PTE_WRITEABLE (1 << 6) 76c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 77c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher/* MAX values used for gfx init */ 78c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_SH_GPRS 256 79c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_TEMP_GPRS 16 80c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_SH_THREADS 256 81c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_SH_STACK_ENTRIES 4096 82c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_BACKENDS 8 83c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_BACKENDS_MASK 0xff 84c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_SIMDS 8 85c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_SIMDS_MASK 0xff 86c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_PIPES 8 87c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R6XX_MAX_PIPES_MASK 0xff 88c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 89c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_SH_GPRS 256 90c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_TEMP_GPRS 16 91c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_SH_THREADS 256 92c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_SH_STACK_ENTRIES 4096 93c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_BACKENDS 8 94c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_BACKENDS_MASK 0xff 95c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_SIMDS 16 96c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_SIMDS_MASK 0xffff 97c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_PIPES 8 98c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#define R7XX_MAX_PIPES_MASK 0xff 99c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 100c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries) 101c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 102c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i; 103c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 104c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 105c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 106c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < dev_priv->usec_timeout; i++) { 107c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int slots; 108c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 109c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher slots = (RADEON_READ(R600_GRBM_STATUS) 110c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher & R700_CMDFIFO_AVAIL_MASK); 111c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 112c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher slots = (RADEON_READ(R600_GRBM_STATUS) 113c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher & R600_CMDFIFO_AVAIL_MASK); 114c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (slots >= entries) 115c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return 0; 116c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(1); 117c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 118c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n", 119c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_STATUS), 120c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_STATUS2)); 121c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 122c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EBUSY; 123c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 124c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 125c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv) 126c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 127c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i, ret; 128c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 129c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 130c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 131c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 132c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ret = r600_do_wait_for_fifo(dev_priv, 8); 133c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 134c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ret = r600_do_wait_for_fifo(dev_priv, 16); 135c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (ret) 136c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return ret; 137c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < dev_priv->usec_timeout; i++) { 138c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE)) 139c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return 0; 140c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(1); 141c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 142c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n", 143c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_STATUS), 144c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_STATUS2)); 145c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 146c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EBUSY; 147c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 148c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 149c1556f71513f2e660fb2bbdc29344361b1ebff35Alex Deuchervoid r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info) 150c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 151c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_sg_mem *entry = dev->sg; 152c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int max_pages; 153c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int pages; 154c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i; 155c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 15608932156cc2d4f8807dc5ca5c3d6ccd85080610aAlex Deucher if (!entry) 15708932156cc2d4f8807dc5ca5c3d6ccd85080610aAlex Deucher return; 15808932156cc2d4f8807dc5ca5c3d6ccd85080610aAlex Deucher 159c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (gart_info->bus_addr) { 16006f0a488c1b642d3cd7769da66600e5148c3fad8Dave Airlie max_pages = (gart_info->table_size / sizeof(u64)); 161c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher pages = (entry->pages <= max_pages) 162c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ? entry->pages : max_pages; 163c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 164c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < pages; i++) { 165c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!entry->busaddr[i]) 166c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 167a763d7dc0adb1159c1a52d43e566409da9fa59f0Dave Airlie pci_unmap_page(dev->pdev, entry->busaddr[i], 168a763d7dc0adb1159c1a52d43e566409da9fa59f0Dave Airlie PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 169c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 170c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) 171c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gart_info->bus_addr = 0; 172c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 173c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 174c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 175c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher/* R600 has page table setup */ 176c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherint r600_page_table_init(struct drm_device *dev) 177c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 178c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 179c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info; 180eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie struct drm_local_map *map = &gart_info->mapping; 181c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_sg_mem *entry = dev->sg; 182c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int ret = 0; 183c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i, j; 184eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie int pages; 185eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie u64 page_base; 186c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dma_addr_t entry_addr; 187eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie int max_ati_pages, max_real_pages, gart_idx; 188c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 189c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* okay page table is available - lets rock */ 190eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie max_ati_pages = (gart_info->table_size / sizeof(u64)); 191eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); 192c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 193eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie pages = (entry->pages <= max_real_pages) ? 194eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie entry->pages : max_real_pages; 195c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 196eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie memset_io((void __iomem *)map->handle, 0, max_ati_pages * sizeof(u64)); 197c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 198eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie gart_idx = 0; 199c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < pages; i++) { 200a763d7dc0adb1159c1a52d43e566409da9fa59f0Dave Airlie entry->busaddr[i] = pci_map_page(dev->pdev, 201a763d7dc0adb1159c1a52d43e566409da9fa59f0Dave Airlie entry->pagelist[i], 0, 202a763d7dc0adb1159c1a52d43e566409da9fa59f0Dave Airlie PAGE_SIZE, 203a763d7dc0adb1159c1a52d43e566409da9fa59f0Dave Airlie PCI_DMA_BIDIRECTIONAL); 204a30f6fb7ce86275af16c7a00dc1b1e46cbb99692Benjamin Herrenschmidt if (pci_dma_mapping_error(dev->pdev, entry->busaddr[i])) { 205c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("unable to map PCIGART pages!\n"); 206c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_page_table_cleanup(dev, gart_info); 207c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher goto done; 208c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 209c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher entry_addr = entry->busaddr[i]; 210c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) { 211c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK; 212c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; 213c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE; 214c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 215eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie DRM_WRITE64(map, gart_idx * sizeof(u64), page_base); 216eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie 217eb1d91954ededc00ddcfb51e2626f114ff351524Dave Airlie gart_idx++; 218c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 219c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((i % 128) == 0) 220c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("page entry %d: 0x%016llx\n", 221c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher i, (unsigned long long)page_base); 222c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher entry_addr += ATI_PCIGART_PAGE_SIZE; 223c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 224c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 22541f13fe81dd1b08723ab9f3fc3c7f29cfa81f1a5Alex Deucher ret = 1; 226c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherdone: 227c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return ret; 228c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 229c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 230c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r600_vm_flush_gart_range(struct drm_device *dev) 231c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 232c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 233c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 resp, countdown = 1000; 234c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12); 235c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 236c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2); 237c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 238c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher do { 239c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE); 240c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher countdown--; 241c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(1); 242c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } while (((resp & 0xf0) == 0) && countdown); 243c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 244c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 245c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r600_vm_init(struct drm_device *dev) 246c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 247c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 248c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* initialise the VM to use the page table we constructed up there */ 249c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 vm_c0, i; 250c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 mc_rd_a; 251c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 vm_l2_cntl, vm_l2_cntl3; 252c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* okay set up the PCIE aperture type thingo */ 253c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); 254c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 255c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 256c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 257c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* setup MC RD a */ 258c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS | 259c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) | 260c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY; 261c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 262c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a); 263c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a); 264c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 265c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a); 266c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a); 267c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 268c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a); 269c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a); 270c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 271c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a); 272c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a); 273c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 274c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING); 275c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/); 276c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 277c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a); 278c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a); 279c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 280c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE); 281c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a); 282c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 283c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W; 284c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7); 285c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl); 286c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 287c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_L2_CNTL2, 0); 288c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) | 289c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VM_L2_CNTL3_BANK_SELECT_1(1) | 290c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2)); 291c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3); 292c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 293c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT; 294c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 295c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0); 296c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 297c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_c0 &= ~R600_VM_ENABLE_CONTEXT; 298c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 299c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* disable all other contexts */ 300c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 1; i < 8; i++) 301c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0); 302c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 303c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); 304c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); 305c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 306c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 307c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_vm_flush_gart_range(dev); 308c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 309c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 31070967ab9c0c9017645d167d33675eab996633631Ben Hutchingsstatic int r600_cp_init_microcode(drm_radeon_private_t *dev_priv) 31170967ab9c0c9017645d167d33675eab996633631Ben Hutchings{ 31270967ab9c0c9017645d167d33675eab996633631Ben Hutchings struct platform_device *pdev; 31370967ab9c0c9017645d167d33675eab996633631Ben Hutchings const char *chip_name; 31470967ab9c0c9017645d167d33675eab996633631Ben Hutchings size_t pfp_req_size, me_req_size; 31570967ab9c0c9017645d167d33675eab996633631Ben Hutchings char fw_name[30]; 31670967ab9c0c9017645d167d33675eab996633631Ben Hutchings int err; 31770967ab9c0c9017645d167d33675eab996633631Ben Hutchings 31870967ab9c0c9017645d167d33675eab996633631Ben Hutchings pdev = platform_device_register_simple("r600_cp", 0, NULL, 0); 31970967ab9c0c9017645d167d33675eab996633631Ben Hutchings err = IS_ERR(pdev); 32070967ab9c0c9017645d167d33675eab996633631Ben Hutchings if (err) { 32170967ab9c0c9017645d167d33675eab996633631Ben Hutchings printk(KERN_ERR "r600_cp: Failed to register firmware\n"); 32270967ab9c0c9017645d167d33675eab996633631Ben Hutchings return -EINVAL; 32370967ab9c0c9017645d167d33675eab996633631Ben Hutchings } 32470967ab9c0c9017645d167d33675eab996633631Ben Hutchings 32570967ab9c0c9017645d167d33675eab996633631Ben Hutchings switch (dev_priv->flags & RADEON_FAMILY_MASK) { 32670967ab9c0c9017645d167d33675eab996633631Ben Hutchings case CHIP_R600: chip_name = "R600"; break; 32770967ab9c0c9017645d167d33675eab996633631Ben Hutchings case CHIP_RV610: chip_name = "RV610"; break; 32870967ab9c0c9017645d167d33675eab996633631Ben Hutchings case CHIP_RV630: chip_name = "RV630"; break; 32970967ab9c0c9017645d167d33675eab996633631Ben Hutchings case CHIP_RV620: chip_name = "RV620"; break; 33070967ab9c0c9017645d167d33675eab996633631Ben Hutchings case CHIP_RV635: chip_name = "RV635"; break; 33170967ab9c0c9017645d167d33675eab996633631Ben Hutchings case CHIP_RV670: chip_name = "RV670"; break; 33270967ab9c0c9017645d167d33675eab996633631Ben Hutchings case CHIP_RS780: 33370967ab9c0c9017645d167d33675eab996633631Ben Hutchings case CHIP_RS880: chip_name = "RS780"; break; 33470967ab9c0c9017645d167d33675eab996633631Ben Hutchings case CHIP_RV770: chip_name = "RV770"; break; 33570967ab9c0c9017645d167d33675eab996633631Ben Hutchings case CHIP_RV730: 33670967ab9c0c9017645d167d33675eab996633631Ben Hutchings case CHIP_RV740: chip_name = "RV730"; break; 33770967ab9c0c9017645d167d33675eab996633631Ben Hutchings case CHIP_RV710: chip_name = "RV710"; break; 33870967ab9c0c9017645d167d33675eab996633631Ben Hutchings default: BUG(); 33970967ab9c0c9017645d167d33675eab996633631Ben Hutchings } 34070967ab9c0c9017645d167d33675eab996633631Ben Hutchings 34170967ab9c0c9017645d167d33675eab996633631Ben Hutchings if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) { 34270967ab9c0c9017645d167d33675eab996633631Ben Hutchings pfp_req_size = R700_PFP_UCODE_SIZE * 4; 34370967ab9c0c9017645d167d33675eab996633631Ben Hutchings me_req_size = R700_PM4_UCODE_SIZE * 4; 34470967ab9c0c9017645d167d33675eab996633631Ben Hutchings } else { 34570967ab9c0c9017645d167d33675eab996633631Ben Hutchings pfp_req_size = PFP_UCODE_SIZE * 4; 34670967ab9c0c9017645d167d33675eab996633631Ben Hutchings me_req_size = PM4_UCODE_SIZE * 12; 34770967ab9c0c9017645d167d33675eab996633631Ben Hutchings } 34870967ab9c0c9017645d167d33675eab996633631Ben Hutchings 34970967ab9c0c9017645d167d33675eab996633631Ben Hutchings DRM_INFO("Loading %s CP Microcode\n", chip_name); 35070967ab9c0c9017645d167d33675eab996633631Ben Hutchings 35170967ab9c0c9017645d167d33675eab996633631Ben Hutchings snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 35270967ab9c0c9017645d167d33675eab996633631Ben Hutchings err = request_firmware(&dev_priv->pfp_fw, fw_name, &pdev->dev); 35370967ab9c0c9017645d167d33675eab996633631Ben Hutchings if (err) 35470967ab9c0c9017645d167d33675eab996633631Ben Hutchings goto out; 35570967ab9c0c9017645d167d33675eab996633631Ben Hutchings if (dev_priv->pfp_fw->size != pfp_req_size) { 35670967ab9c0c9017645d167d33675eab996633631Ben Hutchings printk(KERN_ERR 35770967ab9c0c9017645d167d33675eab996633631Ben Hutchings "r600_cp: Bogus length %zu in firmware \"%s\"\n", 35870967ab9c0c9017645d167d33675eab996633631Ben Hutchings dev_priv->pfp_fw->size, fw_name); 35970967ab9c0c9017645d167d33675eab996633631Ben Hutchings err = -EINVAL; 36070967ab9c0c9017645d167d33675eab996633631Ben Hutchings goto out; 36170967ab9c0c9017645d167d33675eab996633631Ben Hutchings } 36270967ab9c0c9017645d167d33675eab996633631Ben Hutchings 36370967ab9c0c9017645d167d33675eab996633631Ben Hutchings snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 36470967ab9c0c9017645d167d33675eab996633631Ben Hutchings err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev); 36570967ab9c0c9017645d167d33675eab996633631Ben Hutchings if (err) 36670967ab9c0c9017645d167d33675eab996633631Ben Hutchings goto out; 36770967ab9c0c9017645d167d33675eab996633631Ben Hutchings if (dev_priv->me_fw->size != me_req_size) { 36870967ab9c0c9017645d167d33675eab996633631Ben Hutchings printk(KERN_ERR 36970967ab9c0c9017645d167d33675eab996633631Ben Hutchings "r600_cp: Bogus length %zu in firmware \"%s\"\n", 37070967ab9c0c9017645d167d33675eab996633631Ben Hutchings dev_priv->me_fw->size, fw_name); 37170967ab9c0c9017645d167d33675eab996633631Ben Hutchings err = -EINVAL; 37270967ab9c0c9017645d167d33675eab996633631Ben Hutchings } 37370967ab9c0c9017645d167d33675eab996633631Ben Hutchingsout: 37470967ab9c0c9017645d167d33675eab996633631Ben Hutchings platform_device_unregister(pdev); 37570967ab9c0c9017645d167d33675eab996633631Ben Hutchings 37670967ab9c0c9017645d167d33675eab996633631Ben Hutchings if (err) { 37770967ab9c0c9017645d167d33675eab996633631Ben Hutchings if (err != -EINVAL) 37870967ab9c0c9017645d167d33675eab996633631Ben Hutchings printk(KERN_ERR 37970967ab9c0c9017645d167d33675eab996633631Ben Hutchings "r600_cp: Failed to load firmware \"%s\"\n", 38070967ab9c0c9017645d167d33675eab996633631Ben Hutchings fw_name); 38170967ab9c0c9017645d167d33675eab996633631Ben Hutchings release_firmware(dev_priv->pfp_fw); 38270967ab9c0c9017645d167d33675eab996633631Ben Hutchings dev_priv->pfp_fw = NULL; 38370967ab9c0c9017645d167d33675eab996633631Ben Hutchings release_firmware(dev_priv->me_fw); 38470967ab9c0c9017645d167d33675eab996633631Ben Hutchings dev_priv->me_fw = NULL; 38570967ab9c0c9017645d167d33675eab996633631Ben Hutchings } 38670967ab9c0c9017645d167d33675eab996633631Ben Hutchings return err; 38770967ab9c0c9017645d167d33675eab996633631Ben Hutchings} 38870967ab9c0c9017645d167d33675eab996633631Ben Hutchings 389c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r600_cp_load_microcode(drm_radeon_private_t *dev_priv) 390c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 39170967ab9c0c9017645d167d33675eab996633631Ben Hutchings const __be32 *fw_data; 392c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i; 393c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 39470967ab9c0c9017645d167d33675eab996633631Ben Hutchings if (!dev_priv->me_fw || !dev_priv->pfp_fw) 39570967ab9c0c9017645d167d33675eab996633631Ben Hutchings return; 39670967ab9c0c9017645d167d33675eab996633631Ben Hutchings 397c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cp_stop(dev_priv); 398c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 399c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 400dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano#ifdef __BIG_ENDIAN 401dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano R600_BUF_SWAP_32BIT | 402dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano#endif 403c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_RB_NO_UPDATE | 404c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_RB_BLKSZ(15) | 405c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_RB_BUFSZ(3)); 406c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 407c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 408c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_SOFT_RESET); 4094de833c337509916b7931982734d858191cf0700Arnd Bergmann mdelay(15); 410c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 411c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 41270967ab9c0c9017645d167d33675eab996633631Ben Hutchings fw_data = (const __be32 *)dev_priv->me_fw->data; 413c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 41470967ab9c0c9017645d167d33675eab996633631Ben Hutchings for (i = 0; i < PM4_UCODE_SIZE * 3; i++) 41570967ab9c0c9017645d167d33675eab996633631Ben Hutchings RADEON_WRITE(R600_CP_ME_RAM_DATA, 41670967ab9c0c9017645d167d33675eab996633631Ben Hutchings be32_to_cpup(fw_data++)); 417c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 41870967ab9c0c9017645d167d33675eab996633631Ben Hutchings fw_data = (const __be32 *)dev_priv->pfp_fw->data; 41970967ab9c0c9017645d167d33675eab996633631Ben Hutchings RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 42070967ab9c0c9017645d167d33675eab996633631Ben Hutchings for (i = 0; i < PFP_UCODE_SIZE; i++) 42170967ab9c0c9017645d167d33675eab996633631Ben Hutchings RADEON_WRITE(R600_CP_PFP_UCODE_DATA, 42270967ab9c0c9017645d167d33675eab996633631Ben Hutchings be32_to_cpup(fw_data++)); 423c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 424c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 425c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 426c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); 427c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 428c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 429c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 430c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r700_vm_init(struct drm_device *dev) 431c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 432c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 433c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* initialise the VM to use the page table we constructed up there */ 434c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 vm_c0, i; 435c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 mc_vm_md_l1; 436c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 vm_l2_cntl, vm_l2_cntl3; 437c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* okay set up the PCIE aperture type thingo */ 438c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); 439c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 440c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 441c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 442c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher mc_vm_md_l1 = R700_ENABLE_L1_TLB | 443c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_ENABLE_L1_FRAGMENT_PROCESSING | 444c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SYSTEM_ACCESS_MODE_IN_SYS | 445c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 446c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_EFFECTIVE_L1_TLB_SIZE(5) | 447c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_EFFECTIVE_L1_QUEUE_SIZE(5); 448c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 449c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1); 450c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1); 451c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1); 452c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1); 453c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1); 454c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1); 455c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1); 456c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 457c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W; 458c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7); 459c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl); 460c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 461c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_L2_CNTL2, 0); 462c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2); 463c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3); 464c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 465c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT; 466c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 467c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0); 468c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 469c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vm_c0 &= ~R600_VM_ENABLE_CONTEXT; 470c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 471c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* disable all other contexts */ 472c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 1; i < 8; i++) 473c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0); 474c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 475c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); 476c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); 477c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 478c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 479c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_vm_flush_gart_range(dev); 480c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 481c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 482c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r700_cp_load_microcode(drm_radeon_private_t *dev_priv) 483c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 48470967ab9c0c9017645d167d33675eab996633631Ben Hutchings const __be32 *fw_data; 485c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i; 486c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 48770967ab9c0c9017645d167d33675eab996633631Ben Hutchings if (!dev_priv->me_fw || !dev_priv->pfp_fw) 48870967ab9c0c9017645d167d33675eab996633631Ben Hutchings return; 48970967ab9c0c9017645d167d33675eab996633631Ben Hutchings 490c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cp_stop(dev_priv); 491c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 492c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 493dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano#ifdef __BIG_ENDIAN 494dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano R600_BUF_SWAP_32BIT | 495dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano#endif 496c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_RB_NO_UPDATE | 497dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano R600_RB_BLKSZ(15) | 498dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano R600_RB_BUFSZ(3)); 499c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 500c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 501c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_SOFT_RESET); 5024de833c337509916b7931982734d858191cf0700Arnd Bergmann mdelay(15); 503c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 504c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 50570967ab9c0c9017645d167d33675eab996633631Ben Hutchings fw_data = (const __be32 *)dev_priv->pfp_fw->data; 50670967ab9c0c9017645d167d33675eab996633631Ben Hutchings RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 50770967ab9c0c9017645d167d33675eab996633631Ben Hutchings for (i = 0; i < R700_PFP_UCODE_SIZE; i++) 50870967ab9c0c9017645d167d33675eab996633631Ben Hutchings RADEON_WRITE(R600_CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 50970967ab9c0c9017645d167d33675eab996633631Ben Hutchings RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 510c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 51170967ab9c0c9017645d167d33675eab996633631Ben Hutchings fw_data = (const __be32 *)dev_priv->me_fw->data; 51270967ab9c0c9017645d167d33675eab996633631Ben Hutchings RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 51370967ab9c0c9017645d167d33675eab996633631Ben Hutchings for (i = 0; i < R700_PM4_UCODE_SIZE; i++) 51470967ab9c0c9017645d167d33675eab996633631Ben Hutchings RADEON_WRITE(R600_CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 51570967ab9c0c9017645d167d33675eab996633631Ben Hutchings RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 516c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 517c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 518c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 519c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); 520c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 521c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 522c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 523c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r600_test_writeback(drm_radeon_private_t *dev_priv) 524c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 525c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 tmp; 526c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 527c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Start with assuming that writeback doesn't work */ 528c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->writeback_works = 0; 529c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 530c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Writeback doesn't seem to work everywhere, test it here and possibly 531c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * enable it if it appears to work 532c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 533c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0); 534c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 535c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef); 536c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 537c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { 538c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 val; 539c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 540c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1)); 541c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (val == 0xdeadbeef) 542c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 543c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(1); 544c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 545c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 546c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (tmp < dev_priv->usec_timeout) { 547c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->writeback_works = 1; 548c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("writeback test succeeded in %d usecs\n", tmp); 549c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else { 550c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->writeback_works = 0; 551c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("writeback test failed\n"); 552c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 553c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (radeon_no_wb == 1) { 554c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->writeback_works = 0; 555c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("writeback forced off\n"); 556c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 557c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 558c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev_priv->writeback_works) { 559c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Disable writeback to avoid unnecessary bus master transfer */ 560dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano RADEON_WRITE(R600_CP_RB_CNTL, 561dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano#ifdef __BIG_ENDIAN 562dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano R600_BUF_SWAP_32BIT | 563dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano#endif 564dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano RADEON_READ(R600_CP_RB_CNTL) | 565dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano R600_RB_NO_UPDATE); 566c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SCRATCH_UMSK, 0); 567c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 568c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 569c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 570c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherint r600_do_engine_reset(struct drm_device *dev) 571c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 572c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 573c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cp_ptr, cp_me_cntl, cp_rb_cntl; 574c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 575c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Resetting GPU\n"); 576c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 577c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cp_ptr = RADEON_READ(R600_CP_RB_WPTR); 578c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL); 579c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT); 580c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 581c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff); 582c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_SOFT_RESET); 583c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_UDELAY(50); 584c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 585c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_SOFT_RESET); 586c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 587c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); 588c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL); 589dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano RADEON_WRITE(R600_CP_RB_CNTL, 590dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano#ifdef __BIG_ENDIAN 591dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano R600_BUF_SWAP_32BIT | 592dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano#endif 593dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano R600_RB_RPTR_WR_ENA); 594c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 595c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr); 596c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr); 597c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl); 598c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl); 599c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 600c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Reset the CP ring */ 601c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cp_reset(dev_priv); 602c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 603c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* The CP is no longer running after an engine reset */ 604c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_running = 0; 605c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 606c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Reset any pending vertex, indirect buffers */ 607c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_freelist_reset(dev); 608c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 609c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return 0; 610c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 611c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 612c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 613c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes, 614c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 num_backends, 615c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 backend_disable_mask) 616c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 617c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 backend_map = 0; 618c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 enabled_backends_mask; 619c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 enabled_backends_count; 620c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cur_pipe; 621c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 swizzle_pipe[R6XX_MAX_PIPES]; 622c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cur_backend; 623c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 i; 624c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 625c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_tile_pipes > R6XX_MAX_PIPES) 626c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_tile_pipes = R6XX_MAX_PIPES; 627c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_tile_pipes < 1) 628c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_tile_pipes = 1; 629c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_backends > R6XX_MAX_BACKENDS) 630c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_backends = R6XX_MAX_BACKENDS; 631c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_backends < 1) 632c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_backends = 1; 633c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 634c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_mask = 0; 635c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_count = 0; 636c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < R6XX_MAX_BACKENDS; ++i) { 637c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((backend_disable_mask >> i) & 1) == 0) { 638c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_mask |= (1 << i); 639c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ++enabled_backends_count; 640c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 641c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (enabled_backends_count == num_backends) 642c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 643c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 644c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 645c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (enabled_backends_count == 0) { 646c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_mask = 1; 647c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_count = 1; 648c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 649c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 650c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (enabled_backends_count != num_backends) 651c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_backends = enabled_backends_count; 652c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 653c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES); 654c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (num_tile_pipes) { 655c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 1: 656c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 657c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 658c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 2: 659c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 660c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 1; 661c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 662c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 3: 663c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 664c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 1; 665c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 2; 666c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 667c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 4: 668c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 669c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 1; 670c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 2; 671c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 3; 672c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 673c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 5: 674c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 675c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 1; 676c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 2; 677c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 3; 678c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[4] = 4; 679c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 680c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 6: 681c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 682c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 2; 683c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 4; 684c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 5; 685c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[4] = 1; 686c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[5] = 3; 687c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 688c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 7: 689c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 690c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 2; 691c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 4; 692c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 6; 693c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[4] = 1; 694c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[5] = 3; 695c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[6] = 5; 696c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 697c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 8: 698c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 699c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 2; 700c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[2] = 4; 701c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[3] = 6; 702c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[4] = 1; 703c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[5] = 3; 704c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[6] = 5; 705c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[7] = 7; 706c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 707c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 708c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 709c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cur_backend = 0; 710c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 711c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher while (((1 << cur_backend) & enabled_backends_mask) == 0) 712c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; 713c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 714c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 715c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 716c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; 717c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 718c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 719c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return backend_map; 720c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 721c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 722c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic int r600_count_pipe_bits(uint32_t val) 723c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 724ef8cf3a1c523afa499d15856e7db3844ad59d1fbAkinobu Mita return hweight32(val); 725c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 726c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 727c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r600_gfx_init(struct drm_device *dev, 728c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv) 729c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 730c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i, j, num_qd_pipes; 731c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sx_debug_1; 732c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 tc_cntl; 733c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 arb_pop; 734c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 num_gs_verts_per_thread; 735c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 vgt_gs_per_es; 736c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 gs_prim_buffer_depth = 0; 737c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_ms_fifo_sizes; 738c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_config; 739c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_gpr_resource_mgmt_1 = 0; 740c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_gpr_resource_mgmt_2 = 0; 741c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_thread_resource_mgmt = 0; 742c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_stack_resource_mgmt_1 = 0; 743c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_stack_resource_mgmt_2 = 0; 744c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 hdp_host_path_cntl; 745c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 backend_map; 746c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 gb_tiling_config = 0; 747d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher u32 cc_rb_backend_disable; 748d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher u32 cc_gc_shader_pipe_config; 749c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 ramcfg; 750c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 751c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* setup chip specs */ 752c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->flags & RADEON_FAMILY_MASK) { 753c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_R600: 754c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_pipes = 4; 755c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_tile_pipes = 8; 756c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_simds = 4; 757c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends = 4; 758c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gprs = 256; 759c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_threads = 192; 760c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_stack_entries = 256; 761c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_hw_contexts = 8; 762c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gs_threads = 16; 763c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_size = 128; 764c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_pos_size = 16; 765c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_smx_size = 128; 766c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sq_num_cf_insts = 2; 767c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 768c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV630: 769c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV635: 770c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_pipes = 2; 771c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_tile_pipes = 2; 772c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_simds = 3; 773c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends = 1; 774c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gprs = 128; 775c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_threads = 192; 776c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_stack_entries = 128; 777c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_hw_contexts = 8; 778c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gs_threads = 4; 779c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_size = 128; 780c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_pos_size = 16; 781c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_smx_size = 128; 782c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sq_num_cf_insts = 2; 783c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 784c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV610: 785c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RS780: 7866502fbfaf81b09b3f474bb7b3796257e9450273eAlex Deucher case CHIP_RS880: 787c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV620: 788c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_pipes = 1; 789c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_tile_pipes = 1; 790c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_simds = 2; 791c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends = 1; 792c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gprs = 128; 793c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_threads = 192; 794c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_stack_entries = 128; 795c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_hw_contexts = 4; 796c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gs_threads = 4; 797c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_size = 128; 798c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_pos_size = 16; 799c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_smx_size = 128; 800c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sq_num_cf_insts = 1; 801c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 802c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV670: 803c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_pipes = 4; 804c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_tile_pipes = 4; 805c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_simds = 4; 806c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends = 4; 807c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gprs = 192; 808c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_threads = 192; 809c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_stack_entries = 256; 810c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_hw_contexts = 8; 811c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gs_threads = 16; 812c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_size = 128; 813c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_pos_size = 16; 814c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_smx_size = 128; 815c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sq_num_cf_insts = 2; 816c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 817c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 818c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 819c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 820c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 821c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Initialize HDP */ 822c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher j = 0; 823c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < 32; i++) { 824c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c14 + j), 0x00000000); 825c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c18 + j), 0x00000000); 826c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c1c + j), 0x00000000); 827c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c20 + j), 0x00000000); 828c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c24 + j), 0x00000000); 829c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher j += 0x18; 830c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 831c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 832c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff)); 833c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 834c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* setup tiling, simd, pipe config */ 835c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ramcfg = RADEON_READ(R600_RAMCFG); 836c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 837c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->r600_max_tile_pipes) { 838c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 1: 839c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(0); 840c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 841c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 2: 842c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(1); 843c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 844c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 4: 845c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(2); 846c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 847c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 8: 848c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(3); 849c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 850c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 851c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 852c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 853c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 854c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK); 855c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 856c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_GROUP_SIZE(0); 857c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 858c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) { 859c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_ROW_TILING(3); 860c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_SAMPLE_SPLIT(3); 861c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else { 862c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= 863c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK)); 864c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= 865c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK)); 866c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 867c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 868c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_BANK_SWAPS(1); 869c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 870d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher cc_rb_backend_disable = RADEON_READ(R600_CC_RB_BACKEND_DISABLE) & 0x00ff0000; 871d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher cc_rb_backend_disable |= 872d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK); 873c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 874d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher cc_gc_shader_pipe_config = RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; 875d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher cc_gc_shader_pipe_config |= 876c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK); 877c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cc_gc_shader_pipe_config |= 878c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK); 879c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 880d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes, 881d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher (R6XX_MAX_BACKENDS - 882d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher r600_count_pipe_bits((cc_rb_backend_disable & 883d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher R6XX_MAX_BACKENDS_MASK) >> 16)), 884d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher (cc_rb_backend_disable >> 16)); 885d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher gb_tiling_config |= R600_BACKEND_MAP(backend_map); 886c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 887c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); 888c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 889c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 890961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse if (gb_tiling_config & 0xc0) { 891961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse dev_priv->r600_group_size = 512; 892961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse } else { 893961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse dev_priv->r600_group_size = 256; 894961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse } 895961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7); 896961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse if (gb_tiling_config & 0x30) { 897961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse dev_priv->r600_nbanks = 8; 898961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse } else { 899961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse dev_priv->r600_nbanks = 4; 900961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse } 901c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 902c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 903c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 904c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 905c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 906c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_qd_pipes = 907d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8); 908c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK); 909c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK); 910c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 911c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* set HW defaults for 3D engine */ 912c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) | 913c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ROQ_IB2_START(0x2b))); 914c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 915c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) | 916c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ROQ_END(0x40))); 917c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 918c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO | 919c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SYNC_GRADIENT | 920c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SYNC_WALKER | 921c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SYNC_ALIGNER)); 922c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 923c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) 924c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021); 925c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 926c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1); 927c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sx_debug_1 |= R600_SMX_EVENT_RELEASE; 928c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600)) 929c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS; 930c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1); 931c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 932c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || 933c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || 934c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 935c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 9366502fbfaf81b09b3f474bb7b3796257e9450273eAlex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || 9376502fbfaf81b09b3f474bb7b3796257e9450273eAlex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) 938c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE); 939c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 940c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_DB_DEBUG, 0); 941c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 942c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) | 943c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_DEPTH_FLUSH(16) | 944c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_DEPTH_PENDING_FREE(4) | 945c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_DEPTH_CACHELINE_FREE(16))); 946c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 947c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0); 948c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 949c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0)); 950c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0)); 951c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 952c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES); 953c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 954c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 9556502fbfaf81b09b3f474bb7b3796257e9450273eAlex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || 9566502fbfaf81b09b3f474bb7b3796257e9450273eAlex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) { 957c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) | 958c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_FETCH_FIFO_HIWATER(0xa) | 959c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_DONE_FIFO_HIWATER(0xe0) | 960c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ALU_UPDATE_FIFO_HIWATER(0x8)); 961c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || 962c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) { 963c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff); 964c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4); 965c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 966c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 967c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 968c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 969c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * should be adjusted as needed by the 2D/3D drivers. This just sets default values 970c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 971c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config = RADEON_READ(R600_SQ_CONFIG); 972c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config &= ~(R600_PS_PRIO(3) | 973c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VS_PRIO(3) | 974c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_GS_PRIO(3) | 975c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ES_PRIO(3)); 976c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config |= (R600_DX9_CONSTS | 977c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VC_ENABLE | 978c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_PS_PRIO(0) | 979c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VS_PRIO(1) | 980c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_GS_PRIO(2) | 981c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ES_PRIO(3)); 982c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 983c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) { 984c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) | 985c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_GPRS(124) | 986c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_CLAUSE_TEMP_GPRS(4)); 987c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) | 988c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_GPRS(0)); 989c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) | 990c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_THREADS(48) | 991c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_GS_THREADS(4) | 992c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_THREADS(4)); 993c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) | 994c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_STACK_ENTRIES(128)); 995c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) | 996c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_STACK_ENTRIES(0)); 997c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 998c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 9996502fbfaf81b09b3f474bb7b3796257e9450273eAlex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || 10006502fbfaf81b09b3f474bb7b3796257e9450273eAlex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) { 1001c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* no vertex cache */ 1002c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config &= ~R600_VC_ENABLE; 1003c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1004c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 1005c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_GPRS(44) | 1006c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_CLAUSE_TEMP_GPRS(2)); 1007c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) | 1008c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_GPRS(17)); 1009c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 1010c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_THREADS(78) | 1011c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_GS_THREADS(4) | 1012c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_THREADS(31)); 1013c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) | 1014c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_STACK_ENTRIES(40)); 1015c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) | 1016c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_STACK_ENTRIES(16)); 1017c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || 1018c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) { 1019c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 1020c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_GPRS(44) | 1021c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_CLAUSE_TEMP_GPRS(2)); 1022c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) | 1023c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_GPRS(18)); 1024c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 1025c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_THREADS(78) | 1026c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_GS_THREADS(4) | 1027c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_THREADS(31)); 1028c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) | 1029c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_STACK_ENTRIES(40)); 1030c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) | 1031c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_STACK_ENTRIES(16)); 1032c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) { 1033c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 1034c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_GPRS(44) | 1035c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_CLAUSE_TEMP_GPRS(2)); 1036c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) | 1037c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_GPRS(17)); 1038c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 1039c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_THREADS(78) | 1040c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_GS_THREADS(4) | 1041c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_THREADS(31)); 1042c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) | 1043c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_STACK_ENTRIES(64)); 1044c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) | 1045c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_STACK_ENTRIES(64)); 1046c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1047c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1048c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_CONFIG, sq_config); 1049c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 1050c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 1051c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1052c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 1053c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 1054c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1055c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 1056c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 10576502fbfaf81b09b3f474bb7b3796257e9450273eAlex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || 10586502fbfaf81b09b3f474bb7b3796257e9450273eAlex Deucher ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) 1059c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY)); 1060c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 1061c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC)); 1062c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1063c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) | 1064c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S0_Y(0x4) | 1065c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S1_X(0x4) | 1066c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S1_Y(0xc))); 1067c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) | 1068c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S0_Y(0xe) | 1069c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S1_X(0x2) | 1070c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S1_Y(0x2) | 1071c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S2_X(0xa) | 1072c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S2_Y(0x6) | 1073c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S3_X(0x6) | 1074c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S3_Y(0xa))); 1075c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) | 1076c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S0_Y(0xb) | 1077c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S1_X(0x4) | 1078c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S1_Y(0xc) | 1079c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S2_X(0x1) | 1080c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S2_Y(0x6) | 1081c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S3_X(0xa) | 1082c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S3_Y(0xe))); 1083c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) | 1084c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S4_Y(0x1) | 1085c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S5_X(0x0) | 1086c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S5_Y(0x0) | 1087c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S6_X(0xb) | 1088c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S6_Y(0x4) | 1089c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S7_X(0x7) | 1090c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_S7_Y(0x8))); 1091c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1092c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1093c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1094c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_R600: 1095c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV630: 1096c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV635: 1097c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gs_prim_buffer_depth = 0; 1098c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1099c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV610: 1100c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RS780: 11016502fbfaf81b09b3f474bb7b3796257e9450273eAlex Deucher case CHIP_RS880: 1102c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV620: 1103c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gs_prim_buffer_depth = 32; 1104c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1105c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV670: 1106c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gs_prim_buffer_depth = 128; 1107c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1108c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 1109c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1110c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1111c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1112c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; 1113c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 1114c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Max value for this is 256 */ 1115c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (vgt_gs_per_es > 256) 1116c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vgt_gs_per_es = 256; 1117c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1118c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_ES_PER_GS, 128); 1119c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es); 1120c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_GS_PER_VS, 2); 1121c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16); 1122c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1123c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* more default values. 2D/3D driver should adjust as needed */ 1124c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0); 1125c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_STRMOUT_EN, 0); 1126c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SX_MISC, 0); 1127c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0); 1128c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0); 1129c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0); 1130c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_INPUT_Z, 0); 1131c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2)); 1132c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR7_FRAG, 0); 1133c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1134c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* clear render buffer base addresses */ 1135c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR0_BASE, 0); 1136c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR1_BASE, 0); 1137c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR2_BASE, 0); 1138c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR3_BASE, 0); 1139c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR4_BASE, 0); 1140c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR5_BASE, 0); 1141c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR6_BASE, 0); 1142c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR7_BASE, 0); 1143c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1144c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1145c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV610: 1146c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RS780: 11476502fbfaf81b09b3f474bb7b3796257e9450273eAlex Deucher case CHIP_RS880: 1148c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV620: 1149c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher tc_cntl = R600_TC_L2_SIZE(8); 1150c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1151c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV630: 1152c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV635: 1153c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher tc_cntl = R600_TC_L2_SIZE(4); 1154c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1155c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_R600: 1156c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT; 1157c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1158c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 1159c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher tc_cntl = R600_TC_L2_SIZE(0); 1160c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1161c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1162c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1163c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_TC_CNTL, tc_cntl); 1164c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1165c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL); 1166c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1167c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1168c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher arb_pop = RADEON_READ(R600_ARB_POP); 1169c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher arb_pop |= R600_ENABLE_TC128; 1170c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_ARB_POP, arb_pop); 1171c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1172c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1173c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA | 1174c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_CLIP_SEQ(3))); 1175c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095)); 1176c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1177c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 1178c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1179d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucherstatic u32 r700_get_tile_pipe_to_backend_map(drm_radeon_private_t *dev_priv, 1180d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher u32 num_tile_pipes, 1181c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 num_backends, 1182c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 backend_disable_mask) 1183c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 1184c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 backend_map = 0; 1185c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 enabled_backends_mask; 1186c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 enabled_backends_count; 1187c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cur_pipe; 1188c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 swizzle_pipe[R7XX_MAX_PIPES]; 1189c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cur_backend; 1190c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 i; 1191d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher bool force_no_swizzle; 1192c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1193c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_tile_pipes > R7XX_MAX_PIPES) 1194c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_tile_pipes = R7XX_MAX_PIPES; 1195c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_tile_pipes < 1) 1196c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_tile_pipes = 1; 1197c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_backends > R7XX_MAX_BACKENDS) 1198c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_backends = R7XX_MAX_BACKENDS; 1199c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (num_backends < 1) 1200c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_backends = 1; 1201c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1202c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_mask = 0; 1203c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_count = 0; 1204c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < R7XX_MAX_BACKENDS; ++i) { 1205c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((backend_disable_mask >> i) & 1) == 0) { 1206c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_mask |= (1 << i); 1207c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ++enabled_backends_count; 1208c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1209c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (enabled_backends_count == num_backends) 1210c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1211c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1212c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1213c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (enabled_backends_count == 0) { 1214c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_mask = 1; 1215c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher enabled_backends_count = 1; 1216c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1217c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1218c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (enabled_backends_count != num_backends) 1219c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_backends = enabled_backends_count; 1220c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1221d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1222d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher case CHIP_RV770: 1223d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher case CHIP_RV730: 1224d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher force_no_swizzle = false; 1225d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher break; 1226d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher case CHIP_RV710: 1227d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher case CHIP_RV740: 1228d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher default: 1229d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher force_no_swizzle = true; 1230d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher break; 1231d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher } 1232d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher 1233c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES); 1234c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (num_tile_pipes) { 1235c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 1: 1236c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 1237c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1238c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 2: 1239c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[0] = 0; 1240c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher swizzle_pipe[1] = 1; 1241c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1242c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 3: 1243d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher if (force_no_swizzle) { 1244d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[0] = 0; 1245d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[1] = 1; 1246d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[2] = 2; 1247d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher } else { 1248d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[0] = 0; 1249d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[1] = 2; 1250d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[2] = 1; 1251d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher } 1252c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1253c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 4: 1254d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher if (force_no_swizzle) { 1255d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[0] = 0; 1256d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[1] = 1; 1257d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[2] = 2; 1258d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[3] = 3; 1259d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher } else { 1260d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[0] = 0; 1261d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[1] = 2; 1262d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[2] = 3; 1263d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[3] = 1; 1264d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher } 1265c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1266c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 5: 1267d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher if (force_no_swizzle) { 1268d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[0] = 0; 1269d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[1] = 1; 1270d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[2] = 2; 1271d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[3] = 3; 1272d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[4] = 4; 1273d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher } else { 1274d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[0] = 0; 1275d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[1] = 2; 1276d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[2] = 4; 1277d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[3] = 1; 1278d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[4] = 3; 1279d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher } 1280c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1281c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 6: 1282d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher if (force_no_swizzle) { 1283d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[0] = 0; 1284d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[1] = 1; 1285d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[2] = 2; 1286d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[3] = 3; 1287d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[4] = 4; 1288d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[5] = 5; 1289d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher } else { 1290d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[0] = 0; 1291d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[1] = 2; 1292d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[2] = 4; 1293d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[3] = 5; 1294d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[4] = 3; 1295d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[5] = 1; 1296d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher } 1297c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1298c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 7: 1299d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher if (force_no_swizzle) { 1300d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[0] = 0; 1301d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[1] = 1; 1302d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[2] = 2; 1303d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[3] = 3; 1304d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[4] = 4; 1305d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[5] = 5; 1306d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[6] = 6; 1307d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher } else { 1308d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[0] = 0; 1309d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[1] = 2; 1310d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[2] = 4; 1311d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[3] = 6; 1312d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[4] = 3; 1313d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[5] = 1; 1314d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[6] = 5; 1315d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher } 1316c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1317c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 8: 1318d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher if (force_no_swizzle) { 1319d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[0] = 0; 1320d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[1] = 1; 1321d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[2] = 2; 1322d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[3] = 3; 1323d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[4] = 4; 1324d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[5] = 5; 1325d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[6] = 6; 1326d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[7] = 7; 1327d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher } else { 1328d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[0] = 0; 1329d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[1] = 2; 1330d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[2] = 4; 1331d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[3] = 6; 1332d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[4] = 3; 1333d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[5] = 1; 1334d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[6] = 7; 1335d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher swizzle_pipe[7] = 5; 1336d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher } 1337c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1338c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1339c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1340c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cur_backend = 0; 1341c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 1342c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher while (((1 << cur_backend) & enabled_backends_mask) == 0) 1343c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 1344c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1345c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 1346c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1347c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 1348c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1349c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1350c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return backend_map; 1351c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 1352c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1353c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r700_gfx_init(struct drm_device *dev, 1354c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv) 1355c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 1356c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int i, j, num_qd_pipes; 1357d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher u32 ta_aux_cntl; 1358c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sx_debug_1; 1359c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 smx_dc_ctl0; 1360d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher u32 db_debug3; 1361c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 num_gs_verts_per_thread; 1362c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 vgt_gs_per_es; 1363c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 gs_prim_buffer_depth = 0; 1364c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_ms_fifo_sizes; 1365c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_config; 1366c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_thread_resource_mgmt; 1367c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 hdp_host_path_cntl; 1368c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 sq_dyn_gpr_size_simd_ab_0; 1369c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 backend_map; 1370c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 gb_tiling_config = 0; 1371d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher u32 cc_rb_backend_disable; 1372d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher u32 cc_gc_shader_pipe_config; 1373c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 mc_arb_ramcfg; 1374c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 db_debug4; 1375c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1376c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* setup chip specs */ 1377c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1378c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV770: 1379c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_pipes = 4; 1380c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_tile_pipes = 8; 1381c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_simds = 10; 1382c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends = 4; 1383c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gprs = 256; 1384c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_threads = 248; 1385c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_stack_entries = 512; 1386c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_hw_contexts = 8; 1387c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gs_threads = 16 * 2; 1388c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_size = 128; 1389c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_pos_size = 16; 1390c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_smx_size = 112; 1391c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sq_num_cf_insts = 2; 1392c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1393c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sx_num_of_sets = 7; 1394c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_prim_fifo_size = 0xF9; 1395c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1396c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1397c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1398c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV730: 1399c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_pipes = 2; 1400c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_tile_pipes = 4; 1401c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_simds = 8; 1402c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends = 2; 1403c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gprs = 128; 1404c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_threads = 248; 1405c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_stack_entries = 256; 1406c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_hw_contexts = 8; 1407c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gs_threads = 16 * 2; 1408c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_size = 256; 1409c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_pos_size = 32; 1410c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_smx_size = 224; 1411c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sq_num_cf_insts = 2; 1412c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1413c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sx_num_of_sets = 7; 1414c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_prim_fifo_size = 0xf9; 1415c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1416c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 14172a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher if (dev_priv->r600_sx_max_export_pos_size > 16) { 14182a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_sx_max_export_pos_size -= 16; 14192a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_sx_max_export_smx_size += 16; 14202a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher } 1421c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1422c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV710: 1423c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_pipes = 2; 1424c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_tile_pipes = 2; 1425c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_simds = 2; 1426c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_backends = 1; 1427c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gprs = 256; 1428c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_threads = 192; 1429c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_stack_entries = 256; 1430c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_hw_contexts = 4; 1431c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_max_gs_threads = 8 * 2; 1432c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_size = 128; 1433c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_pos_size = 16; 1434c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sx_max_export_smx_size = 112; 1435c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r600_sq_num_cf_insts = 1; 1436c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1437c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sx_num_of_sets = 7; 1438c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_prim_fifo_size = 0x40; 1439c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1440c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1441c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 14422a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher case CHIP_RV740: 14432a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_max_pipes = 4; 14442a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_max_tile_pipes = 4; 14452a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_max_simds = 8; 14462a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_max_backends = 4; 14472a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_max_gprs = 256; 14482a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_max_threads = 248; 14492a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_max_stack_entries = 512; 14502a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_max_hw_contexts = 8; 14512a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_max_gs_threads = 16 * 2; 14522a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_sx_max_export_size = 256; 14532a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_sx_max_export_pos_size = 32; 14542a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_sx_max_export_smx_size = 224; 14552a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_sq_num_cf_insts = 2; 14562a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher 14572a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r700_sx_num_of_sets = 7; 14582a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r700_sc_prim_fifo_size = 0x100; 14592a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 14602a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 14612a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher 14622a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher if (dev_priv->r600_sx_max_export_pos_size > 16) { 14632a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_sx_max_export_pos_size -= 16; 14642a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher dev_priv->r600_sx_max_export_smx_size += 16; 14652a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher } 14662a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher break; 1467c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 1468c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1469c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1470c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1471c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Initialize HDP */ 1472c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher j = 0; 1473c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher for (i = 0; i < 32; i++) { 1474c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c14 + j), 0x00000000); 1475c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c18 + j), 0x00000000); 1476c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c1c + j), 0x00000000); 1477c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c20 + j), 0x00000000); 1478c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE((0x2c24 + j), 0x00000000); 1479c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher j += 0x18; 1480c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1481c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1482c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff)); 1483c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1484c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* setup tiling, simd, pipe config */ 1485c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG); 1486c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1487c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->r600_max_tile_pipes) { 1488c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 1: 1489c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(0); 1490c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1491c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 2: 1492c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(1); 1493c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1494c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 4: 1495c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(2); 1496c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1497c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 8: 1498c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_PIPE_TILING(3); 1499c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1500c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 1501c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1502c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1503c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1504c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770) 1505c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_BANK_TILING(1); 1506c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 1507c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK); 1508c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1509c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_GROUP_SIZE(0); 1510c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1511c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) { 1512c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_ROW_TILING(3); 1513c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_SAMPLE_SPLIT(3); 1514c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else { 1515c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= 1516c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK)); 1517c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= 1518c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK)); 1519c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1520c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1521c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gb_tiling_config |= R600_BANK_SWAPS(1); 1522c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1523d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher cc_rb_backend_disable = RADEON_READ(R600_CC_RB_BACKEND_DISABLE) & 0x00ff0000; 1524d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher cc_rb_backend_disable |= 1525d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK); 1526c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1527d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher cc_gc_shader_pipe_config = RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; 1528d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher cc_gc_shader_pipe_config |= 1529c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK); 1530c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cc_gc_shader_pipe_config |= 1531c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK); 1532c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1533d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740) 1534d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher backend_map = 0x28; 1535d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher else 1536d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher backend_map = r700_get_tile_pipe_to_backend_map(dev_priv, 1537d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher dev_priv->r600_max_tile_pipes, 1538d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher (R7XX_MAX_BACKENDS - 1539d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher r600_count_pipe_bits((cc_rb_backend_disable & 1540d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher R7XX_MAX_BACKENDS_MASK) >> 16)), 1541d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher (cc_rb_backend_disable >> 16)); 1542d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher gb_tiling_config |= R600_BACKEND_MAP(backend_map); 1543c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1544c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); 1545c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1546c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1547961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse if (gb_tiling_config & 0xc0) { 1548961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse dev_priv->r600_group_size = 512; 1549961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse } else { 1550961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse dev_priv->r600_group_size = 256; 1551961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse } 1552961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7); 1553961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse if (gb_tiling_config & 0x30) { 1554961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse dev_priv->r600_nbanks = 8; 1555961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse } else { 1556961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse dev_priv->r600_nbanks = 4; 1557961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse } 1558c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1559c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 1560c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 1561f867c60def7a8dcd86657fd38a8920a4354f305eAlex Deucher RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 1562c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1563c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); 1564c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0); 1565c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0); 1566f867c60def7a8dcd86657fd38a8920a4354f305eAlex Deucher RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0); 1567f867c60def7a8dcd86657fd38a8920a4354f305eAlex Deucher RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0); 1568c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1569c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_qd_pipes = 1570d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8); 1571c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK); 1572c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK); 1573c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1574c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* set HW defaults for 3D engine */ 1575c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) | 1576c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ROQ_IB2_START(0x2b))); 1577c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1578c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30)); 1579c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1580d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher ta_aux_cntl = RADEON_READ(R600_TA_CNTL_AUX); 1581d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher RADEON_WRITE(R600_TA_CNTL_AUX, ta_aux_cntl | R600_DISABLE_CUBE_ANISO); 1582c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1583c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1); 1584c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS; 1585c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1); 1586c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1587c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0); 1588c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff); 1589c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1); 1590c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0); 1591c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1592d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV740) 1593d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) | 1594d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher R700_GS_FLUSH_CTL(4) | 1595d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher R700_ACK_FLUSH_CTL(3) | 1596d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher R700_SYNC_FLUSH_CTL)); 1597c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1598d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher db_debug3 = RADEON_READ(R700_DB_DEBUG3); 1599d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher db_debug3 &= ~R700_DB_CLK_OFF_DELAY(0x1f); 1600d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1601d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher case CHIP_RV770: 1602d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher case CHIP_RV740: 1603d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher db_debug3 |= R700_DB_CLK_OFF_DELAY(0x1f); 1604d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher break; 1605d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher case CHIP_RV710: 1606d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher case CHIP_RV730: 1607d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher default: 1608d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher db_debug3 |= R700_DB_CLK_OFF_DELAY(2); 1609d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher break; 1610d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher } 1611d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher RADEON_WRITE(R700_DB_DEBUG3, db_debug3); 1612d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher 1613d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV770) { 1614c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher db_debug4 = RADEON_READ(RV700_DB_DEBUG4); 1615c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER; 1616c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(RV700_DB_DEBUG4, db_debug4); 1617c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1618c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1619c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) | 1620c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) | 1621c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1))); 1622c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1623c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) | 1624c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) | 1625c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize))); 1626c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1627c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1628c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1629c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1); 1630c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1631c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0)); 1632c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1633c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4)); 1634c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1635c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_PERFMON_CNTL, 0); 1636c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1637c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) | 1638c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_DONE_FIFO_HIWATER(0xe0) | 1639c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ALU_UPDATE_FIFO_HIWATER(0x8)); 1640c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1641c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV770: 1642c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV730: 1643c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV710: 1644d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1); 1645d03f5d5971f2dd4bd259c46e065299661d8fdc9fAlex Deucher break; 16462a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher case CHIP_RV740: 1647c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 1648c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4); 1649c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1650c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1651c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 1652c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1653c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 1654c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * should be adjusted as needed by the 2D/3D drivers. This just sets default values 1655c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 1656c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config = RADEON_READ(R600_SQ_CONFIG); 1657c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config &= ~(R600_PS_PRIO(3) | 1658c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VS_PRIO(3) | 1659c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_GS_PRIO(3) | 1660c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ES_PRIO(3)); 1661c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config |= (R600_DX9_CONSTS | 1662c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VC_ENABLE | 1663c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_EXPORT_SRC_C | 1664c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_PS_PRIO(0) | 1665c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_VS_PRIO(1) | 1666c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_GS_PRIO(2) | 1667c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_ES_PRIO(3)); 1668c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) 1669c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* no vertex cache */ 1670c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_config &= ~R600_VC_ENABLE; 1671c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1672c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_CONFIG, sq_config); 1673c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1674c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) | 1675c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) | 1676c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2))); 1677c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1678c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) | 1679c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64))); 1680c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1681c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) | 1682c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) | 1683c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8)); 1684c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads) 1685c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads); 1686c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 1687c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8); 1688c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1689c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1690c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) | 1691c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); 1692c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1693c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) | 1694c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); 1695c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1696c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) | 1697c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) | 1698c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) | 1699c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64)); 1700c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1701c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); 1702c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); 1703c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); 1704c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); 1705c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); 1706c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); 1707c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); 1708c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); 1709c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1710c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) | 1711c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_FORCE_EOV_MAX_REZ_CNT(255))); 1712c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1713c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) 1714c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) | 1715c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO))); 1716c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 1717c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) | 1718c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO))); 1719c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1720c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1721c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV770: 1722c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV730: 17232a71ebcd85bcc4d6607f577f23a491f796c30e82Alex Deucher case CHIP_RV740: 1724c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gs_prim_buffer_depth = 384; 1725c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1726c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case CHIP_RV710: 1727c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher gs_prim_buffer_depth = 128; 1728c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1729c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 1730c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 1731c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1732c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1733c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; 1734c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 1735c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Max value for this is 256 */ 1736c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (vgt_gs_per_es > 256) 1737c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher vgt_gs_per_es = 256; 1738c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1739c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_ES_PER_GS, 128); 1740c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es); 1741c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_GS_PER_VS, 2); 1742c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1743c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* more default values. 2D/3D driver should adjust as needed */ 1744c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16); 1745c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0); 1746c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_VGT_STRMOUT_EN, 0); 1747c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SX_MISC, 0); 1748c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0); 1749c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa); 1750c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0); 1751c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff); 1752c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0); 1753c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_INPUT_Z, 0); 1754c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2)); 1755c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR7_FRAG, 0); 1756c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1757c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* clear render buffer base addresses */ 1758c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR0_BASE, 0); 1759c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR1_BASE, 0); 1760c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR2_BASE, 0); 1761c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR3_BASE, 0); 1762c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR4_BASE, 0); 1763c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR5_BASE, 0); 1764c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR6_BASE, 0); 1765c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CB_COLOR7_BASE, 0); 1766c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1767c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R700_TCP_CNTL, 0); 1768c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1769c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL); 1770c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1771c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1772c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1773c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1774c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA | 1775c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher R600_NUM_CLIP_SEQ(3))); 1776c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1777c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 1778c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1779c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherstatic void r600_cp_init_ring_buffer(struct drm_device *dev, 1780c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv, 1781c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_file *file_priv) 1782c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 1783c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_radeon_master_private *master_priv; 1784c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 ring_start; 17856546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie u64 rptr_addr; 1786c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1787c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 1788c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r700_gfx_init(dev, dev_priv); 1789c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 1790c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_gfx_init(dev, dev_priv); 1791c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1792c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 1793c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_READ(R600_GRBM_SOFT_RESET); 17944de833c337509916b7931982734d858191cf0700Arnd Bergmann mdelay(15); 1795c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 1796c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1797c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1798c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Set ring buffer size */ 1799c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#ifdef __BIG_ENDIAN 1800c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 1801df07d6999e4e502ff474eeafe11ea0055f4cd68dBenjamin Herrenschmidt R600_BUF_SWAP_32BIT | 1802df07d6999e4e502ff474eeafe11ea0055f4cd68dBenjamin Herrenschmidt R600_RB_NO_UPDATE | 1803c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->ring.rptr_update_l2qw << 8) | 1804c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size_l2qw); 1805c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#else 1806c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 1807c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_RB_NO_UPDATE | 1808c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->ring.rptr_update_l2qw << 8) | 1809c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size_l2qw); 1810c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 1811c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 181215d3332f31afd571a6d23971dbc8d8db2856e661Christian König RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x0); 1813c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1814c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Set the write pointer delay */ 1815c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); 1816c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1817c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#ifdef __BIG_ENDIAN 1818c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 1819df07d6999e4e502ff474eeafe11ea0055f4cd68dBenjamin Herrenschmidt R600_BUF_SWAP_32BIT | 1820df07d6999e4e502ff474eeafe11ea0055f4cd68dBenjamin Herrenschmidt R600_RB_NO_UPDATE | 1821df07d6999e4e502ff474eeafe11ea0055f4cd68dBenjamin Herrenschmidt R600_RB_RPTR_WR_ENA | 1822c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->ring.rptr_update_l2qw << 8) | 1823c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size_l2qw); 1824c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#else 1825c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 1826df07d6999e4e502ff474eeafe11ea0055f4cd68dBenjamin Herrenschmidt R600_RB_NO_UPDATE | 1827df07d6999e4e502ff474eeafe11ea0055f4cd68dBenjamin Herrenschmidt R600_RB_RPTR_WR_ENA | 1828c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->ring.rptr_update_l2qw << 8) | 1829c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size_l2qw); 1830c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 1831c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1832c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Initialize the ring buffer's read and write pointers */ 1833c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_RPTR_WR, 0); 1834c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_WPTR, 0); 1835c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher SET_RING_HEAD(dev_priv, 0); 1836c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.tail = 0; 1837c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1838c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#if __OS_HAS_AGP 1839c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->flags & RADEON_IS_AGP) { 18406546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie rptr_addr = dev_priv->ring_rptr->offset 18416546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie - dev->agp->base + 18426546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie dev_priv->gart_vm_start; 1843c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else 1844c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 1845c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher { 18466546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie rptr_addr = dev_priv->ring_rptr->offset 18476546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie - ((unsigned long) dev->sg->virtual) 18486546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie + dev_priv->gart_vm_start; 1849c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1850df07d6999e4e502ff474eeafe11ea0055f4cd68dBenjamin Herrenschmidt RADEON_WRITE(R600_CP_RB_RPTR_ADDR, (rptr_addr & 0xfffffffc)); 1851df07d6999e4e502ff474eeafe11ea0055f4cd68dBenjamin Herrenschmidt RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI, upper_32_bits(rptr_addr)); 1852c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1853c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#ifdef __BIG_ENDIAN 1854c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 1855c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_BUF_SWAP_32BIT | 1856c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->ring.rptr_update_l2qw << 8) | 1857c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size_l2qw); 1858c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#else 1859c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_CNTL, 1860c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->ring.rptr_update_l2qw << 8) | 1861c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size_l2qw); 1862c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 1863c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1864c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#if __OS_HAS_AGP 1865c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->flags & RADEON_IS_AGP) { 1866c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* XXX */ 1867c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_write_agp_base(dev_priv, dev->agp->base); 1868c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1869c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* XXX */ 1870c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_write_agp_location(dev_priv, 1871c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (((dev_priv->gart_vm_start - 1 + 1872c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_size) & 0xffff0000) | 1873c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (dev_priv->gart_vm_start >> 16))); 1874c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1875c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ring_start = (dev_priv->cp_ring->offset 1876c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher - dev->agp->base 1877c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + dev_priv->gart_vm_start); 1878c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else 1879c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 1880c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ring_start = (dev_priv->cp_ring->offset 1881c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher - (unsigned long)dev->sg->virtual 1882c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + dev_priv->gart_vm_start); 1883c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1884c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8); 1885c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1886c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_CNTL, 0xff); 1887c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1888c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28)); 1889c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1890c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Initialize the scratch register pointer. This will cause 1891c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * the scratch register values to be written out to memory 1892c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * whenever they are updated. 1893c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * 1894c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * We simply put this behind the ring read pointer, this works 1895c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * with PCI GART as well as (whatever kind of) AGP GART 1896c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 18976546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie { 18986546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie u64 scratch_addr; 18996546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie 1900dee54c40a1a9898bcd156436a1d3524f530b5a90Cédric Cano scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR) & 0xFFFFFFFC; 19016546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32; 19026546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie scratch_addr += R600_SCRATCH_REG_OFFSET; 19036546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie scratch_addr >>= 8; 19046546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie scratch_addr &= 0xffffffff; 19056546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie 19066546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr); 19076546bf6d6cbf1f9ac350fd278a1d937d4bb9ad06Dave Airlie } 1908c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1909c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_SCRATCH_UMSK, 0x7); 1910c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1911c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Turn on bus mastering */ 1912c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_enable_bm(dev_priv); 1913c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1914c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0); 1915c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_LAST_FRAME_REG, 0); 1916c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1917c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0); 1918c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_LAST_DISPATCH_REG, 0); 1919c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1920c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0); 1921c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_LAST_CLEAR_REG, 0); 1922c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1923c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* reset sarea copies of these */ 1924c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher master_priv = file_priv->master->driver_priv; 1925c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (master_priv->sarea_priv) { 1926c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher master_priv->sarea_priv->last_frame = 0; 1927c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher master_priv->sarea_priv->last_dispatch = 0; 1928c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher master_priv->sarea_priv->last_clear = 0; 1929c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1930c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1931c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_wait_for_idle(dev_priv); 1932c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1933c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 1934c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1935c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherint r600_do_cleanup_cp(struct drm_device *dev) 1936c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 1937c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 1938c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("\n"); 1939c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1940c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Make sure interrupts are disabled here because the uninstall ioctl 1941c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * may not have been called from userspace and after dev_private 1942c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * is freed, it's too late. 1943c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 1944c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev->irq_enabled) 1945c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_irq_uninstall(dev); 1946c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1947c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#if __OS_HAS_AGP 1948c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->flags & RADEON_IS_AGP) { 1949c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->cp_ring != NULL) { 1950c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_core_ioremapfree(dev_priv->cp_ring, dev); 1951c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_ring = NULL; 1952c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1953c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->ring_rptr != NULL) { 1954c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_core_ioremapfree(dev_priv->ring_rptr, dev); 1955c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring_rptr = NULL; 1956c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1957c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev->agp_buffer_map != NULL) { 1958c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_core_ioremapfree(dev->agp_buffer_map, dev); 1959c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev->agp_buffer_map = NULL; 1960c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1961c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else 1962c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 1963c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher { 1964c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1965c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->gart_info.bus_addr) 1966c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_page_table_cleanup(dev, &dev_priv->gart_info); 1967c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1968c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) { 1969c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); 19708f497aade8df2a619eacda927a43ebe82167a84cHannes Eder dev_priv->gart_info.addr = NULL; 1971c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1972c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1973c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* only clear to the start of flags */ 1974c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); 1975c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1976c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return 0; 1977c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 1978c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1979c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherint r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, 1980c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_file *file_priv) 1981c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 1982c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 1983c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; 1984c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1985c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("\n"); 1986c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 19873ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse mutex_init(&dev_priv->cs_mutex); 19883ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse r600_cs_legacy_init(); 1989c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* if we require new memory map but we don't have it fail */ 1990c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { 1991c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); 1992c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 1993c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 1994c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 1995c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 1996c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) { 1997c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("Forcing AGP card to PCI mode\n"); 1998c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->flags &= ~RADEON_IS_AGP; 1999c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* The writeback test succeeds, but when writeback is enabled, 2000c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * the ring buffer read ptr update fails after first 128 bytes. 2001c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 2002c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher radeon_no_wb = 1; 2003c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) 2004c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher && !init->is_pci) { 2005c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("Restoring AGP flag\n"); 2006c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->flags |= RADEON_IS_AGP; 2007c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2008c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2009c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->usec_timeout = init->usec_timeout; 2010c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->usec_timeout < 1 || 2011c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { 2012c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("TIMEOUT problem!\n"); 2013c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2014c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2015c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2016c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2017c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Enable vblank on CRTC1 for older X servers 2018c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 2019c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; 20203ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse dev_priv->do_boxes = 0; 2021c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_mode = init->cp_mode; 2022c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2023c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* We don't support anything other than bus-mastering ring mode, 2024c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * but the ring can be in either AGP or PCI space for the ring 2025c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * read pointer. 2026c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 2027c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && 2028c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { 2029c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); 2030c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2031c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2032c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2033c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2034c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher switch (init->fb_bpp) { 2035c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 16: 2036c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; 2037c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 2038c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher case 32: 2039c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher default: 2040c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; 2041c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher break; 2042c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2043c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->front_offset = init->front_offset; 2044c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->front_pitch = init->front_pitch; 2045c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->back_offset = init->back_offset; 2046c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->back_pitch = init->back_pitch; 2047c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2048c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring_offset = init->ring_offset; 2049c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring_rptr_offset = init->ring_rptr_offset; 2050c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->buffers_offset = init->buffers_offset; 2051c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_textures_offset = init->gart_textures_offset; 2052c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2053c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher master_priv->sarea = drm_getsarea(dev); 2054c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!master_priv->sarea) { 2055c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("could not find sarea!\n"); 2056c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2057c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2058c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2059c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2060c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); 2061c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev_priv->cp_ring) { 2062c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("could not find cp ring region!\n"); 2063c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2064c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2065c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2066c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); 2067c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev_priv->ring_rptr) { 2068c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("could not find ring read pointer!\n"); 2069c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2070c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2071c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2072c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev->agp_buffer_token = init->buffers_offset; 2073c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); 2074c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev->agp_buffer_map) { 2075c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("could not find dma buffer region!\n"); 2076c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2077c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2078c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2079c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2080c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (init->gart_textures_offset) { 2081c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_textures = 2082c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_core_findmap(dev, init->gart_textures_offset); 2083c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev_priv->gart_textures) { 2084c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("could not find GART texture region!\n"); 2085c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2086c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2087c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2088c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2089c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2090c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#if __OS_HAS_AGP 2091c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* XXX */ 2092c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->flags & RADEON_IS_AGP) { 20937659e9804b7a66047433182d86393d38ba4eff79Alex Deucher drm_core_ioremap_wc(dev_priv->cp_ring, dev); 20947659e9804b7a66047433182d86393d38ba4eff79Alex Deucher drm_core_ioremap_wc(dev_priv->ring_rptr, dev); 20957659e9804b7a66047433182d86393d38ba4eff79Alex Deucher drm_core_ioremap_wc(dev->agp_buffer_map, dev); 2096c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev_priv->cp_ring->handle || 2097c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher !dev_priv->ring_rptr->handle || 2098c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher !dev->agp_buffer_map->handle) { 2099c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("could not find ioremap agp regions!\n"); 2100c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2101c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2102c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2103c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else 2104c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 2105c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher { 21063ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse dev_priv->cp_ring->handle = (void *)(unsigned long)dev_priv->cp_ring->offset; 2107c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring_rptr->handle = 21083ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse (void *)(unsigned long)dev_priv->ring_rptr->offset; 2109c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev->agp_buffer_map->handle = 21103ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse (void *)(unsigned long)dev->agp_buffer_map->offset; 2111c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2112c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("dev_priv->cp_ring->handle %p\n", 2113c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_ring->handle); 2114c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", 2115c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring_rptr->handle); 2116c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("dev->agp_buffer_map->handle %p\n", 2117c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev->agp_buffer_map->handle); 2118c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2119c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2120c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24; 2121c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->fb_size = 2122c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000) 2123c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher - dev_priv->fb_location; 2124c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2125c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | 2126c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->front_offset 2127c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + dev_priv->fb_location) >> 10)); 2128c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2129c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | 2130c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->back_offset 2131c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + dev_priv->fb_location) >> 10)); 2132c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2133c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | 2134c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((dev_priv->depth_offset 2135c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + dev_priv->fb_location) >> 10)); 2136c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2137c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_size = init->gart_size; 2138c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2139c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* New let's set the memory map ... */ 2140c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->new_memmap) { 2141c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 base = 0; 2142c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2143c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Setting GART location based on new memory map\n"); 2144c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2145c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* If using AGP, try to locate the AGP aperture at the same 2146c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * location in the card and on the bus, though we have to 2147c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * align it down. 2148c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 2149c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#if __OS_HAS_AGP 2150c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* XXX */ 2151c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->flags & RADEON_IS_AGP) { 2152c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher base = dev->agp->base; 2153c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Check if valid */ 2154c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && 2155c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { 2156c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n", 2157c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev->agp->base); 2158c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher base = 0; 2159c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2160c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2161c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 2162c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* If not or if AGP is at 0 (Macs), try to put it elsewhere */ 2163c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (base == 0) { 2164c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher base = dev_priv->fb_location + dev_priv->fb_size; 2165c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (base < dev_priv->fb_location || 2166c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((base + dev_priv->gart_size) & 0xfffffffful) < base) 2167c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher base = dev_priv->fb_location 2168c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher - dev_priv->gart_size; 2169c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2170c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_vm_start = base & 0xffc00000u; 2171c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->gart_vm_start != base) 2172c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n", 2173c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher base, dev_priv->gart_vm_start); 2174c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2175c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2176c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#if __OS_HAS_AGP 2177c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* XXX */ 2178c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->flags & RADEON_IS_AGP) 2179c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 2180c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher - dev->agp->base 2181c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + dev_priv->gart_vm_start); 2182c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 2183c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 2184c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 2185c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher - (unsigned long)dev->sg->virtual 2186c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + dev_priv->gart_vm_start); 2187c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2188c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("fb 0x%08x size %d\n", 2189c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (unsigned int) dev_priv->fb_location, 2190c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (unsigned int) dev_priv->fb_size); 2191c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); 2192c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n", 2193c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher (unsigned int) dev_priv->gart_vm_start); 2194c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n", 2195c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_buffers_offset); 2196c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2197c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; 2198c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle 2199c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + init->ring_size / sizeof(u32)); 2200c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size = init->ring_size; 2201c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); 2202c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2203c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; 2204c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8); 2205c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2206c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.fetch_size = /* init->fetch_size */ 32; 2207c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16); 2208c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2209c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; 2210c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2211c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; 2212c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2213c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#if __OS_HAS_AGP 2214c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (dev_priv->flags & RADEON_IS_AGP) { 2215c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* XXX turn off pcie gart */ 2216c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else 2217c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher#endif 2218c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher { 2219c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); 2220c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* if we have an offset set from userspace */ 2221c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev_priv->pcigart_offset_set) { 2222c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("Need gart offset from userspace\n"); 2223c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2224c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2225c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2226c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2227c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset); 2228c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2229c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.bus_addr = 2230c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->pcigart_offset + dev_priv->fb_location; 2231c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.mapping.offset = 2232c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->pcigart_offset + dev_priv->fb_aper_offset; 2233c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.mapping.size = 2234c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.table_size; 2235c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2236c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev); 2237c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (!dev_priv->gart_info.mapping.handle) { 2238c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("ioremap failed.\n"); 2239c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2240c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2241c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2242c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2243c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.addr = 2244c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.mapping.handle; 2245c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2246c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n", 2247c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->gart_info.addr, 2248c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->pcigart_offset); 2249c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 225041f13fe81dd1b08723ab9f3fc3c7f29cfa81f1a5Alex Deucher if (!r600_page_table_init(dev)) { 2251c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_ERROR("Failed to init GART table\n"); 2252c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_cleanup_cp(dev); 2253c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return -EINVAL; 2254c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2255c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2256c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 2257c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r700_vm_init(dev); 2258c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 2259c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_vm_init(dev); 2260c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2261c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 226270967ab9c0c9017645d167d33675eab996633631Ben Hutchings if (!dev_priv->me_fw || !dev_priv->pfp_fw) { 226370967ab9c0c9017645d167d33675eab996633631Ben Hutchings int err = r600_cp_init_microcode(dev_priv); 226470967ab9c0c9017645d167d33675eab996633631Ben Hutchings if (err) { 226570967ab9c0c9017645d167d33675eab996633631Ben Hutchings DRM_ERROR("Failed to load firmware!\n"); 226670967ab9c0c9017645d167d33675eab996633631Ben Hutchings r600_do_cleanup_cp(dev); 226770967ab9c0c9017645d167d33675eab996633631Ben Hutchings return err; 226870967ab9c0c9017645d167d33675eab996633631Ben Hutchings } 226970967ab9c0c9017645d167d33675eab996633631Ben Hutchings } 2270c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 2271c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r700_cp_load_microcode(dev_priv); 2272c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 2273c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_cp_load_microcode(dev_priv); 2274c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2275c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_cp_init_ring_buffer(dev, dev_priv, file_priv); 2276c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2277c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->last_buf = 0; 2278c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2279c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_engine_reset(dev); 2280c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_test_writeback(dev_priv); 2281c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2282c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return 0; 2283c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 2284c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2285c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherint r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv) 2286c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 2287c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 2288c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2289c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("\n"); 2290c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) { 2291c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r700_vm_init(dev); 2292c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r700_cp_load_microcode(dev_priv); 2293c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } else { 2294c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_vm_init(dev); 2295c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_cp_load_microcode(dev_priv); 2296c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2297c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_cp_init_ring_buffer(dev, dev_priv, file_priv); 2298c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher r600_do_engine_reset(dev); 2299c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2300c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return 0; 2301c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 2302c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2303c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher/* Wait for the CP to go idle. 2304c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 2305c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherint r600_do_cp_idle(drm_radeon_private_t *dev_priv) 2306c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 2307c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RING_LOCALS; 2308c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("\n"); 2309c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2310c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher BEGIN_RING(5); 2311c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); 2312c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT); 2313c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* wait for 3D idle clean */ 2314c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); 2315c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2); 2316c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN); 2317c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2318c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ADVANCE_RING(); 2319c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher COMMIT_RING(); 2320c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2321c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return r600_do_wait_for_idle(dev_priv); 2322c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 2323c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2324c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher/* Start the Command Processor. 2325c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 2326c05ce0834a268f7d18274847190f6ed826b99332Alex Deuchervoid r600_do_cp_start(drm_radeon_private_t *dev_priv) 2327c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 2328c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cp_me; 2329c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RING_LOCALS; 2330c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("\n"); 2331c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2332c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher BEGIN_RING(7); 2333c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5)); 2334c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(0x00000001); 2335c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) 2336c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(0x00000003); 2337c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher else 2338c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(0x00000000); 2339c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING((dev_priv->r600_max_hw_contexts - 1)); 2340c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1)); 2341c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(0x00000000); 2342c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(0x00000000); 2343c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ADVANCE_RING(); 2344c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher COMMIT_RING(); 2345c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2346c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* set the mux and reset the halt bit */ 2347c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cp_me = 0xff; 2348c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_CNTL, cp_me); 2349c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2350c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_running = 1; 2351c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2352c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 2353c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2354c05ce0834a268f7d18274847190f6ed826b99332Alex Deuchervoid r600_do_cp_reset(drm_radeon_private_t *dev_priv) 2355c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 2356c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 cur_read_ptr; 2357c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("\n"); 2358c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2359c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR); 2360c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr); 2361c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher SET_RING_HEAD(dev_priv, cur_read_ptr); 2362c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->ring.tail = cur_read_ptr; 2363c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 2364c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2365c05ce0834a268f7d18274847190f6ed826b99332Alex Deuchervoid r600_do_cp_stop(drm_radeon_private_t *dev_priv) 2366c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 2367c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher uint32_t cp_me; 2368c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2369c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("\n"); 2370c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2371c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher cp_me = 0xff | R600_CP_ME_HALT; 2372c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2373c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RADEON_WRITE(R600_CP_ME_CNTL, cp_me); 2374c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2375c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher dev_priv->cp_running = 0; 2376c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 2377c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2378c05ce0834a268f7d18274847190f6ed826b99332Alex Deucherint r600_cp_dispatch_indirect(struct drm_device *dev, 2379c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher struct drm_buf *buf, int start, int end) 2380c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher{ 2381c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher drm_radeon_private_t *dev_priv = dev->dev_private; 2382c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher RING_LOCALS; 2383c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2384c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher if (start != end) { 2385c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher unsigned long offset = (dev_priv->gart_buffers_offset 2386c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + buf->offset + start); 2387c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher int dwords = (end - start + 3) / sizeof(u32); 2388c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2389c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("dwords:%d\n", dwords); 2390c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher DRM_DEBUG("offset 0x%lx\n", offset); 2391c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2392c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2393c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Indirect buffer data must be a multiple of 16 dwords. 2394c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher * pad the data with a Type-2 CP packet. 2395c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher */ 2396c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher while (dwords & 0xf) { 2397c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher u32 *data = (u32 *) 2398c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ((char *)dev->agp_buffer_map->handle 2399c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher + buf->offset + start); 2400c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher data[dwords++] = RADEON_CP_PACKET2; 2401c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2402c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2403c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher /* Fire off the indirect buffer */ 2404c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher BEGIN_RING(4); 2405c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2)); 2406c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING((offset & 0xfffffffc)); 2407c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING((upper_32_bits(offset) & 0xff)); 2408c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher OUT_RING(dwords); 2409c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher ADVANCE_RING(); 2410c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher } 2411c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher 2412c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher return 0; 2413c05ce0834a268f7d18274847190f6ed826b99332Alex Deucher} 24143ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 24153ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glissevoid r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv) 24163ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse{ 24173ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse drm_radeon_private_t *dev_priv = dev->dev_private; 24183ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse struct drm_master *master = file_priv->master; 24193ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse struct drm_radeon_master_private *master_priv = master->driver_priv; 24203ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; 24213ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse int nbox = sarea_priv->nbox; 24223ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse struct drm_clip_rect *pbox = sarea_priv->boxes; 24233ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse int i, cpp, src_pitch, dst_pitch; 24243ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse uint64_t src, dst; 24253ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse RING_LOCALS; 24263ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse DRM_DEBUG("\n"); 24273ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 24283ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (dev_priv->color_fmt == RADEON_COLOR_FORMAT_ARGB8888) 24293ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse cpp = 4; 24303ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse else 24313ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse cpp = 2; 24323ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 24333ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (sarea_priv->pfCurrentPage == 0) { 24343ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse src_pitch = dev_priv->back_pitch; 24353ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse dst_pitch = dev_priv->front_pitch; 24363ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse src = dev_priv->back_offset + dev_priv->fb_location; 24373ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse dst = dev_priv->front_offset + dev_priv->fb_location; 24383ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } else { 24393ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse src_pitch = dev_priv->front_pitch; 24403ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse dst_pitch = dev_priv->back_pitch; 24413ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse src = dev_priv->front_offset + dev_priv->fb_location; 24423ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse dst = dev_priv->back_offset + dev_priv->fb_location; 24433ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 24443ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 24453ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (r600_prepare_blit_copy(dev, file_priv)) { 24463ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse DRM_ERROR("unable to allocate vertex buffer for swap buffer\n"); 24473ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return; 24483ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 24493ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse for (i = 0; i < nbox; i++) { 24503ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse int x = pbox[i].x1; 24513ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse int y = pbox[i].y1; 24523ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse int w = pbox[i].x2 - x; 24533ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse int h = pbox[i].y2 - y; 24543ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 24553ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h); 24563ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 24573ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse r600_blit_swap(dev, 24583ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse src, dst, 24593ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse x, y, x, y, w, h, 24603ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse src_pitch, dst_pitch, cpp); 24613ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 24623ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse r600_done_blit_copy(dev); 24633ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 24643ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse /* Increment the frame counter. The client-side 3D driver must 24653ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse * throttle the framerate by waiting for this value before 24663ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse * performing the swapbuffer ioctl. 24673ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse */ 24683ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse sarea_priv->last_frame++; 24693ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 24703ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse BEGIN_RING(3); 24713ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse R600_FRAME_AGE(sarea_priv->last_frame); 24723ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse ADVANCE_RING(); 24733ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse} 24743ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 24753ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisseint r600_cp_dispatch_texture(struct drm_device *dev, 24763ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse struct drm_file *file_priv, 24773ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse drm_radeon_texture_t *tex, 24783ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse drm_radeon_tex_image_t *image) 24793ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse{ 24803ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse drm_radeon_private_t *dev_priv = dev->dev_private; 24813ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse struct drm_buf *buf; 24823ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse u32 *buffer; 24833ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse const u8 __user *data; 24843ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse int size, pass_size; 24853ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse u64 src_offset, dst_offset; 24863ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 24873ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (!radeon_check_offset(dev_priv, tex->offset)) { 24883ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse DRM_ERROR("Invalid destination offset\n"); 24893ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return -EINVAL; 24903ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 24913ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 24923ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse /* this might fail for zero-sized uploads - are those illegal? */ 24933ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (!radeon_check_offset(dev_priv, tex->offset + tex->height * tex->pitch - 1)) { 24943ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse DRM_ERROR("Invalid final destination offset\n"); 24953ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return -EINVAL; 24963ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 24973ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 24983ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse size = tex->height * tex->pitch; 24993ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25003ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (size == 0) 25013ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return 0; 25023ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25033ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse dst_offset = tex->offset; 25043ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25053ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (r600_prepare_blit_copy(dev, file_priv)) { 25063ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse DRM_ERROR("unable to allocate vertex buffer for swap buffer\n"); 25073ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return -EAGAIN; 25083ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 25093ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse do { 25103ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse data = (const u8 __user *)image->data; 25113ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse pass_size = size; 25123ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25133ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse buf = radeon_freelist_get(dev); 25143ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (!buf) { 25153ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse DRM_DEBUG("EAGAIN\n"); 25163ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image))) 25173ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return -EFAULT; 25183ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return -EAGAIN; 25193ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 25203ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25213ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (pass_size > buf->total) 25223ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse pass_size = buf->total; 25233ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25243ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse /* Dispatch the indirect buffer. 25253ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse */ 25263ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse buffer = 25273ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset); 25283ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25293ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (DRM_COPY_FROM_USER(buffer, data, pass_size)) { 25303ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse DRM_ERROR("EFAULT on pad, %d bytes\n", pass_size); 25313ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return -EFAULT; 25323ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 25333ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25343ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse buf->file_priv = file_priv; 25353ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse buf->used = pass_size; 25363ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse src_offset = dev_priv->gart_buffers_offset + buf->offset; 25373ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25383ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse r600_blit_copy(dev, src_offset, dst_offset, pass_size); 25393ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25403ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse radeon_cp_discard_buffer(dev, file_priv->master, buf); 25413ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25423ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse /* Update the input parameters for next time */ 25433ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse image->data = (const u8 __user *)image->data + pass_size; 25443ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse dst_offset += pass_size; 25453ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse size -= pass_size; 25463ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } while (size > 0); 25473ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse r600_done_blit_copy(dev); 25483ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25493ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return 0; 25503ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse} 25513ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25523ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse/* 25533ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse * Legacy cs ioctl 25543ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse */ 25553ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glissestatic u32 radeon_cs_id_get(struct drm_radeon_private *radeon) 25563ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse{ 25573ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse /* FIXME: check if wrap affect last reported wrap & sequence */ 25583ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse radeon->cs_id_scnt = (radeon->cs_id_scnt + 1) & 0x00FFFFFF; 25593ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (!radeon->cs_id_scnt) { 25603ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse /* increment wrap counter */ 25613ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse radeon->cs_id_wcnt += 0x01000000; 25623ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse /* valid sequence counter start at 1 */ 25633ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse radeon->cs_id_scnt = 1; 25643ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 25653ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return (radeon->cs_id_scnt | radeon->cs_id_wcnt); 25663ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse} 25673ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25683ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glissestatic void r600_cs_id_emit(drm_radeon_private_t *dev_priv, u32 *id) 25693ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse{ 25703ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse RING_LOCALS; 25713ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25723ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse *id = radeon_cs_id_get(dev_priv); 25733ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25743ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse /* SCRATCH 2 */ 25753ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse BEGIN_RING(3); 25763ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse R600_CLEAR_AGE(*id); 25773ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse ADVANCE_RING(); 25783ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse COMMIT_RING(); 25793ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse} 25803ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25813ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glissestatic int r600_ib_get(struct drm_device *dev, 25823ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse struct drm_file *fpriv, 25833ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse struct drm_buf **buffer) 25843ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse{ 25853ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse struct drm_buf *buf; 25863ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25873ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse *buffer = NULL; 25883ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse buf = radeon_freelist_get(dev); 25893ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (!buf) { 25903ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return -EBUSY; 25913ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 25923ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse buf->file_priv = fpriv; 25933ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse *buffer = buf; 25943ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return 0; 25953ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse} 25963ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 25973ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glissestatic void r600_ib_free(struct drm_device *dev, struct drm_buf *buf, 25983ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse struct drm_file *fpriv, int l, int r) 25993ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse{ 26003ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse drm_radeon_private_t *dev_priv = dev->dev_private; 26013ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 26023ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (buf) { 26033ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (!r) 26043ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse r600_cp_dispatch_indirect(dev, buf, 0, l * 4); 26053ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse radeon_cp_discard_buffer(dev, fpriv->master, buf); 26063ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse COMMIT_RING(); 26073ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 26083ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse} 26093ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 26103ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisseint r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv) 26113ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse{ 26123ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse struct drm_radeon_private *dev_priv = dev->dev_private; 26133ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse struct drm_radeon_cs *cs = data; 26143ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse struct drm_buf *buf; 26153ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse unsigned family; 26163ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse int l, r = 0; 26173ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse u32 *ib, cs_id = 0; 26183ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 26193ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (dev_priv == NULL) { 26203ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse DRM_ERROR("called with no initialization\n"); 26213ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return -EINVAL; 26223ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 26233ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse family = dev_priv->flags & RADEON_FAMILY_MASK; 26243ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (family < CHIP_R600) { 26253ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse DRM_ERROR("cs ioctl valid only for R6XX & R7XX in legacy mode\n"); 26263ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return -EINVAL; 26273ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 26283ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse mutex_lock(&dev_priv->cs_mutex); 26293ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse /* get ib */ 26303ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse r = r600_ib_get(dev, fpriv, &buf); 26313ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (r) { 26323ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse DRM_ERROR("ib_get failed\n"); 26333ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse goto out; 26343ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 26353ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse ib = dev->agp_buffer_map->handle + buf->offset; 26363ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse /* now parse command stream */ 26373ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse r = r600_cs_legacy(dev, data, fpriv, family, ib, &l); 26383ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse if (r) { 26393ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse goto out; 26403ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse } 26413ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse 26423ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisseout: 26433ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse r600_ib_free(dev, buf, fpriv, l, r); 26443ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse /* emit cs id sequence */ 26453ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse r600_cs_id_emit(dev_priv, &cs_id); 26463ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse cs->cs_id = cs_id; 26473ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse mutex_unlock(&dev_priv->cs_mutex); 26483ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse return r; 26493ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse} 2650961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse 2651961fb597c17e2e4f55407d56b7211c188ab41effJerome Glissevoid r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size) 2652961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse{ 2653961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse struct drm_radeon_private *dev_priv = dev->dev_private; 2654961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse 2655961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse *npipes = dev_priv->r600_npipes; 2656961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse *nbanks = dev_priv->r600_nbanks; 2657961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse *group_size = dev_priv->r600_group_size; 2658961fb597c17e2e4f55407d56b7211c188ab41effJerome Glisse} 2659