r600_cp.c revision 2a71ebcd85bcc4d6607f577f23a491f796c30e82
1/* 2 * Copyright 2008-2009 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Dave Airlie <airlied@redhat.com> 26 * Alex Deucher <alexander.deucher@amd.com> 27 */ 28 29#include "drmP.h" 30#include "drm.h" 31#include "radeon_drm.h" 32#include "radeon_drv.h" 33 34#include "r600_microcode.h" 35 36# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ 37# define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1)) 38 39#define R600_PTE_VALID (1 << 0) 40#define R600_PTE_SYSTEM (1 << 1) 41#define R600_PTE_SNOOPED (1 << 2) 42#define R600_PTE_READABLE (1 << 5) 43#define R600_PTE_WRITEABLE (1 << 6) 44 45/* MAX values used for gfx init */ 46#define R6XX_MAX_SH_GPRS 256 47#define R6XX_MAX_TEMP_GPRS 16 48#define R6XX_MAX_SH_THREADS 256 49#define R6XX_MAX_SH_STACK_ENTRIES 4096 50#define R6XX_MAX_BACKENDS 8 51#define R6XX_MAX_BACKENDS_MASK 0xff 52#define R6XX_MAX_SIMDS 8 53#define R6XX_MAX_SIMDS_MASK 0xff 54#define R6XX_MAX_PIPES 8 55#define R6XX_MAX_PIPES_MASK 0xff 56 57#define R7XX_MAX_SH_GPRS 256 58#define R7XX_MAX_TEMP_GPRS 16 59#define R7XX_MAX_SH_THREADS 256 60#define R7XX_MAX_SH_STACK_ENTRIES 4096 61#define R7XX_MAX_BACKENDS 8 62#define R7XX_MAX_BACKENDS_MASK 0xff 63#define R7XX_MAX_SIMDS 16 64#define R7XX_MAX_SIMDS_MASK 0xffff 65#define R7XX_MAX_PIPES 8 66#define R7XX_MAX_PIPES_MASK 0xff 67 68static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries) 69{ 70 int i; 71 72 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 73 74 for (i = 0; i < dev_priv->usec_timeout; i++) { 75 int slots; 76 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 77 slots = (RADEON_READ(R600_GRBM_STATUS) 78 & R700_CMDFIFO_AVAIL_MASK); 79 else 80 slots = (RADEON_READ(R600_GRBM_STATUS) 81 & R600_CMDFIFO_AVAIL_MASK); 82 if (slots >= entries) 83 return 0; 84 DRM_UDELAY(1); 85 } 86 DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n", 87 RADEON_READ(R600_GRBM_STATUS), 88 RADEON_READ(R600_GRBM_STATUS2)); 89 90 return -EBUSY; 91} 92 93static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv) 94{ 95 int i, ret; 96 97 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 98 99 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 100 ret = r600_do_wait_for_fifo(dev_priv, 8); 101 else 102 ret = r600_do_wait_for_fifo(dev_priv, 16); 103 if (ret) 104 return ret; 105 for (i = 0; i < dev_priv->usec_timeout; i++) { 106 if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE)) 107 return 0; 108 DRM_UDELAY(1); 109 } 110 DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n", 111 RADEON_READ(R600_GRBM_STATUS), 112 RADEON_READ(R600_GRBM_STATUS2)); 113 114 return -EBUSY; 115} 116 117void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info) 118{ 119 struct drm_sg_mem *entry = dev->sg; 120 int max_pages; 121 int pages; 122 int i; 123 124 if (!entry) 125 return; 126 127 if (gart_info->bus_addr) { 128 max_pages = (gart_info->table_size / sizeof(u64)); 129 pages = (entry->pages <= max_pages) 130 ? entry->pages : max_pages; 131 132 for (i = 0; i < pages; i++) { 133 if (!entry->busaddr[i]) 134 break; 135 pci_unmap_page(dev->pdev, entry->busaddr[i], 136 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 137 } 138 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) 139 gart_info->bus_addr = 0; 140 } 141} 142 143/* R600 has page table setup */ 144int r600_page_table_init(struct drm_device *dev) 145{ 146 drm_radeon_private_t *dev_priv = dev->dev_private; 147 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info; 148 struct drm_local_map *map = &gart_info->mapping; 149 struct drm_sg_mem *entry = dev->sg; 150 int ret = 0; 151 int i, j; 152 int pages; 153 u64 page_base; 154 dma_addr_t entry_addr; 155 int max_ati_pages, max_real_pages, gart_idx; 156 157 /* okay page table is available - lets rock */ 158 max_ati_pages = (gart_info->table_size / sizeof(u64)); 159 max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); 160 161 pages = (entry->pages <= max_real_pages) ? 162 entry->pages : max_real_pages; 163 164 memset_io((void __iomem *)map->handle, 0, max_ati_pages * sizeof(u64)); 165 166 gart_idx = 0; 167 for (i = 0; i < pages; i++) { 168 entry->busaddr[i] = pci_map_page(dev->pdev, 169 entry->pagelist[i], 0, 170 PAGE_SIZE, 171 PCI_DMA_BIDIRECTIONAL); 172 if (entry->busaddr[i] == 0) { 173 DRM_ERROR("unable to map PCIGART pages!\n"); 174 r600_page_table_cleanup(dev, gart_info); 175 goto done; 176 } 177 entry_addr = entry->busaddr[i]; 178 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) { 179 page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK; 180 page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; 181 page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE; 182 183 DRM_WRITE64(map, gart_idx * sizeof(u64), page_base); 184 185 gart_idx++; 186 187 if ((i % 128) == 0) 188 DRM_DEBUG("page entry %d: 0x%016llx\n", 189 i, (unsigned long long)page_base); 190 entry_addr += ATI_PCIGART_PAGE_SIZE; 191 } 192 } 193 ret = 1; 194done: 195 return ret; 196} 197 198static void r600_vm_flush_gart_range(struct drm_device *dev) 199{ 200 drm_radeon_private_t *dev_priv = dev->dev_private; 201 u32 resp, countdown = 1000; 202 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12); 203 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 204 RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2); 205 206 do { 207 resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE); 208 countdown--; 209 DRM_UDELAY(1); 210 } while (((resp & 0xf0) == 0) && countdown); 211} 212 213static void r600_vm_init(struct drm_device *dev) 214{ 215 drm_radeon_private_t *dev_priv = dev->dev_private; 216 /* initialise the VM to use the page table we constructed up there */ 217 u32 vm_c0, i; 218 u32 mc_rd_a; 219 u32 vm_l2_cntl, vm_l2_cntl3; 220 /* okay set up the PCIE aperture type thingo */ 221 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); 222 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 223 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 224 225 /* setup MC RD a */ 226 mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS | 227 R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) | 228 R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY; 229 230 RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a); 231 RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a); 232 233 RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a); 234 RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a); 235 236 RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a); 237 RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a); 238 239 RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a); 240 RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a); 241 242 RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING); 243 RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/); 244 245 RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a); 246 RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a); 247 248 RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE); 249 RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a); 250 251 vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W; 252 vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7); 253 RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl); 254 255 RADEON_WRITE(R600_VM_L2_CNTL2, 0); 256 vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) | 257 R600_VM_L2_CNTL3_BANK_SELECT_1(1) | 258 R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2)); 259 RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3); 260 261 vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT; 262 263 RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0); 264 265 vm_c0 &= ~R600_VM_ENABLE_CONTEXT; 266 267 /* disable all other contexts */ 268 for (i = 1; i < 8; i++) 269 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0); 270 271 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); 272 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); 273 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 274 275 r600_vm_flush_gart_range(dev); 276} 277 278/* load r600 microcode */ 279static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv) 280{ 281 int i; 282 283 r600_do_cp_stop(dev_priv); 284 285 RADEON_WRITE(R600_CP_RB_CNTL, 286 R600_RB_NO_UPDATE | 287 R600_RB_BLKSZ(15) | 288 R600_RB_BUFSZ(3)); 289 290 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 291 RADEON_READ(R600_GRBM_SOFT_RESET); 292 DRM_UDELAY(15000); 293 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 294 295 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 296 297 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600)) { 298 DRM_INFO("Loading R600 CP Microcode\n"); 299 for (i = 0; i < PM4_UCODE_SIZE; i++) { 300 RADEON_WRITE(R600_CP_ME_RAM_DATA, 301 R600_cp_microcode[i][0]); 302 RADEON_WRITE(R600_CP_ME_RAM_DATA, 303 R600_cp_microcode[i][1]); 304 RADEON_WRITE(R600_CP_ME_RAM_DATA, 305 R600_cp_microcode[i][2]); 306 } 307 308 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 309 DRM_INFO("Loading R600 PFP Microcode\n"); 310 for (i = 0; i < PFP_UCODE_SIZE; i++) 311 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, R600_pfp_microcode[i]); 312 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610)) { 313 DRM_INFO("Loading RV610 CP Microcode\n"); 314 for (i = 0; i < PM4_UCODE_SIZE; i++) { 315 RADEON_WRITE(R600_CP_ME_RAM_DATA, 316 RV610_cp_microcode[i][0]); 317 RADEON_WRITE(R600_CP_ME_RAM_DATA, 318 RV610_cp_microcode[i][1]); 319 RADEON_WRITE(R600_CP_ME_RAM_DATA, 320 RV610_cp_microcode[i][2]); 321 } 322 323 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 324 DRM_INFO("Loading RV610 PFP Microcode\n"); 325 for (i = 0; i < PFP_UCODE_SIZE; i++) 326 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV610_pfp_microcode[i]); 327 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) { 328 DRM_INFO("Loading RV630 CP Microcode\n"); 329 for (i = 0; i < PM4_UCODE_SIZE; i++) { 330 RADEON_WRITE(R600_CP_ME_RAM_DATA, 331 RV630_cp_microcode[i][0]); 332 RADEON_WRITE(R600_CP_ME_RAM_DATA, 333 RV630_cp_microcode[i][1]); 334 RADEON_WRITE(R600_CP_ME_RAM_DATA, 335 RV630_cp_microcode[i][2]); 336 } 337 338 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 339 DRM_INFO("Loading RV630 PFP Microcode\n"); 340 for (i = 0; i < PFP_UCODE_SIZE; i++) 341 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV630_pfp_microcode[i]); 342 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620)) { 343 DRM_INFO("Loading RV620 CP Microcode\n"); 344 for (i = 0; i < PM4_UCODE_SIZE; i++) { 345 RADEON_WRITE(R600_CP_ME_RAM_DATA, 346 RV620_cp_microcode[i][0]); 347 RADEON_WRITE(R600_CP_ME_RAM_DATA, 348 RV620_cp_microcode[i][1]); 349 RADEON_WRITE(R600_CP_ME_RAM_DATA, 350 RV620_cp_microcode[i][2]); 351 } 352 353 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 354 DRM_INFO("Loading RV620 PFP Microcode\n"); 355 for (i = 0; i < PFP_UCODE_SIZE; i++) 356 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV620_pfp_microcode[i]); 357 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) { 358 DRM_INFO("Loading RV635 CP Microcode\n"); 359 for (i = 0; i < PM4_UCODE_SIZE; i++) { 360 RADEON_WRITE(R600_CP_ME_RAM_DATA, 361 RV635_cp_microcode[i][0]); 362 RADEON_WRITE(R600_CP_ME_RAM_DATA, 363 RV635_cp_microcode[i][1]); 364 RADEON_WRITE(R600_CP_ME_RAM_DATA, 365 RV635_cp_microcode[i][2]); 366 } 367 368 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 369 DRM_INFO("Loading RV635 PFP Microcode\n"); 370 for (i = 0; i < PFP_UCODE_SIZE; i++) 371 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV635_pfp_microcode[i]); 372 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)) { 373 DRM_INFO("Loading RV670 CP Microcode\n"); 374 for (i = 0; i < PM4_UCODE_SIZE; i++) { 375 RADEON_WRITE(R600_CP_ME_RAM_DATA, 376 RV670_cp_microcode[i][0]); 377 RADEON_WRITE(R600_CP_ME_RAM_DATA, 378 RV670_cp_microcode[i][1]); 379 RADEON_WRITE(R600_CP_ME_RAM_DATA, 380 RV670_cp_microcode[i][2]); 381 } 382 383 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 384 DRM_INFO("Loading RV670 PFP Microcode\n"); 385 for (i = 0; i < PFP_UCODE_SIZE; i++) 386 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV670_pfp_microcode[i]); 387 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) { 388 DRM_INFO("Loading RS780 CP Microcode\n"); 389 for (i = 0; i < PM4_UCODE_SIZE; i++) { 390 RADEON_WRITE(R600_CP_ME_RAM_DATA, 391 RS780_cp_microcode[i][0]); 392 RADEON_WRITE(R600_CP_ME_RAM_DATA, 393 RS780_cp_microcode[i][1]); 394 RADEON_WRITE(R600_CP_ME_RAM_DATA, 395 RS780_cp_microcode[i][2]); 396 } 397 398 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 399 DRM_INFO("Loading RS780 PFP Microcode\n"); 400 for (i = 0; i < PFP_UCODE_SIZE; i++) 401 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RS780_pfp_microcode[i]); 402 } 403 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 404 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 405 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); 406 407} 408 409static void r700_vm_init(struct drm_device *dev) 410{ 411 drm_radeon_private_t *dev_priv = dev->dev_private; 412 /* initialise the VM to use the page table we constructed up there */ 413 u32 vm_c0, i; 414 u32 mc_vm_md_l1; 415 u32 vm_l2_cntl, vm_l2_cntl3; 416 /* okay set up the PCIE aperture type thingo */ 417 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); 418 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 419 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 420 421 mc_vm_md_l1 = R700_ENABLE_L1_TLB | 422 R700_ENABLE_L1_FRAGMENT_PROCESSING | 423 R700_SYSTEM_ACCESS_MODE_IN_SYS | 424 R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 425 R700_EFFECTIVE_L1_TLB_SIZE(5) | 426 R700_EFFECTIVE_L1_QUEUE_SIZE(5); 427 428 RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1); 429 RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1); 430 RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1); 431 RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1); 432 RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1); 433 RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1); 434 RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1); 435 436 vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W; 437 vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7); 438 RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl); 439 440 RADEON_WRITE(R600_VM_L2_CNTL2, 0); 441 vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2); 442 RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3); 443 444 vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT; 445 446 RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0); 447 448 vm_c0 &= ~R600_VM_ENABLE_CONTEXT; 449 450 /* disable all other contexts */ 451 for (i = 1; i < 8; i++) 452 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0); 453 454 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); 455 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); 456 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 457 458 r600_vm_flush_gart_range(dev); 459} 460 461/* load r600 microcode */ 462static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv) 463{ 464 int i; 465 466 r600_do_cp_stop(dev_priv); 467 468 RADEON_WRITE(R600_CP_RB_CNTL, 469 R600_RB_NO_UPDATE | 470 (15 << 8) | 471 (3 << 0)); 472 473 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 474 RADEON_READ(R600_GRBM_SOFT_RESET); 475 DRM_UDELAY(15000); 476 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 477 478 479 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)) { 480 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 481 DRM_INFO("Loading RV770 PFP Microcode\n"); 482 for (i = 0; i < R700_PFP_UCODE_SIZE; i++) 483 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV770_pfp_microcode[i]); 484 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 485 486 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 487 DRM_INFO("Loading RV770 CP Microcode\n"); 488 for (i = 0; i < R700_PM4_UCODE_SIZE; i++) 489 RADEON_WRITE(R600_CP_ME_RAM_DATA, RV770_cp_microcode[i]); 490 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 491 492 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV730) || 493 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740)) { 494 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 495 DRM_INFO("Loading RV730/RV740 PFP Microcode\n"); 496 for (i = 0; i < R700_PFP_UCODE_SIZE; i++) 497 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV730_pfp_microcode[i]); 498 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 499 500 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 501 DRM_INFO("Loading RV730/RV740 CP Microcode\n"); 502 for (i = 0; i < R700_PM4_UCODE_SIZE; i++) 503 RADEON_WRITE(R600_CP_ME_RAM_DATA, RV730_cp_microcode[i]); 504 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 505 506 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)) { 507 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 508 DRM_INFO("Loading RV710 PFP Microcode\n"); 509 for (i = 0; i < R700_PFP_UCODE_SIZE; i++) 510 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV710_pfp_microcode[i]); 511 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 512 513 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 514 DRM_INFO("Loading RV710 CP Microcode\n"); 515 for (i = 0; i < R700_PM4_UCODE_SIZE; i++) 516 RADEON_WRITE(R600_CP_ME_RAM_DATA, RV710_cp_microcode[i]); 517 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 518 519 } 520 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 521 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 522 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); 523 524} 525 526static void r600_test_writeback(drm_radeon_private_t *dev_priv) 527{ 528 u32 tmp; 529 530 /* Start with assuming that writeback doesn't work */ 531 dev_priv->writeback_works = 0; 532 533 /* Writeback doesn't seem to work everywhere, test it here and possibly 534 * enable it if it appears to work 535 */ 536 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0); 537 538 RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef); 539 540 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { 541 u32 val; 542 543 val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1)); 544 if (val == 0xdeadbeef) 545 break; 546 DRM_UDELAY(1); 547 } 548 549 if (tmp < dev_priv->usec_timeout) { 550 dev_priv->writeback_works = 1; 551 DRM_INFO("writeback test succeeded in %d usecs\n", tmp); 552 } else { 553 dev_priv->writeback_works = 0; 554 DRM_INFO("writeback test failed\n"); 555 } 556 if (radeon_no_wb == 1) { 557 dev_priv->writeback_works = 0; 558 DRM_INFO("writeback forced off\n"); 559 } 560 561 if (!dev_priv->writeback_works) { 562 /* Disable writeback to avoid unnecessary bus master transfer */ 563 RADEON_WRITE(R600_CP_RB_CNTL, RADEON_READ(R600_CP_RB_CNTL) | 564 RADEON_RB_NO_UPDATE); 565 RADEON_WRITE(R600_SCRATCH_UMSK, 0); 566 } 567} 568 569int r600_do_engine_reset(struct drm_device *dev) 570{ 571 drm_radeon_private_t *dev_priv = dev->dev_private; 572 u32 cp_ptr, cp_me_cntl, cp_rb_cntl; 573 574 DRM_INFO("Resetting GPU\n"); 575 576 cp_ptr = RADEON_READ(R600_CP_RB_WPTR); 577 cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL); 578 RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT); 579 580 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff); 581 RADEON_READ(R600_GRBM_SOFT_RESET); 582 DRM_UDELAY(50); 583 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 584 RADEON_READ(R600_GRBM_SOFT_RESET); 585 586 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); 587 cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL); 588 RADEON_WRITE(R600_CP_RB_CNTL, R600_RB_RPTR_WR_ENA); 589 590 RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr); 591 RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr); 592 RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl); 593 RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl); 594 595 /* Reset the CP ring */ 596 r600_do_cp_reset(dev_priv); 597 598 /* The CP is no longer running after an engine reset */ 599 dev_priv->cp_running = 0; 600 601 /* Reset any pending vertex, indirect buffers */ 602 radeon_freelist_reset(dev); 603 604 return 0; 605 606} 607 608static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes, 609 u32 num_backends, 610 u32 backend_disable_mask) 611{ 612 u32 backend_map = 0; 613 u32 enabled_backends_mask; 614 u32 enabled_backends_count; 615 u32 cur_pipe; 616 u32 swizzle_pipe[R6XX_MAX_PIPES]; 617 u32 cur_backend; 618 u32 i; 619 620 if (num_tile_pipes > R6XX_MAX_PIPES) 621 num_tile_pipes = R6XX_MAX_PIPES; 622 if (num_tile_pipes < 1) 623 num_tile_pipes = 1; 624 if (num_backends > R6XX_MAX_BACKENDS) 625 num_backends = R6XX_MAX_BACKENDS; 626 if (num_backends < 1) 627 num_backends = 1; 628 629 enabled_backends_mask = 0; 630 enabled_backends_count = 0; 631 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) { 632 if (((backend_disable_mask >> i) & 1) == 0) { 633 enabled_backends_mask |= (1 << i); 634 ++enabled_backends_count; 635 } 636 if (enabled_backends_count == num_backends) 637 break; 638 } 639 640 if (enabled_backends_count == 0) { 641 enabled_backends_mask = 1; 642 enabled_backends_count = 1; 643 } 644 645 if (enabled_backends_count != num_backends) 646 num_backends = enabled_backends_count; 647 648 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES); 649 switch (num_tile_pipes) { 650 case 1: 651 swizzle_pipe[0] = 0; 652 break; 653 case 2: 654 swizzle_pipe[0] = 0; 655 swizzle_pipe[1] = 1; 656 break; 657 case 3: 658 swizzle_pipe[0] = 0; 659 swizzle_pipe[1] = 1; 660 swizzle_pipe[2] = 2; 661 break; 662 case 4: 663 swizzle_pipe[0] = 0; 664 swizzle_pipe[1] = 1; 665 swizzle_pipe[2] = 2; 666 swizzle_pipe[3] = 3; 667 break; 668 case 5: 669 swizzle_pipe[0] = 0; 670 swizzle_pipe[1] = 1; 671 swizzle_pipe[2] = 2; 672 swizzle_pipe[3] = 3; 673 swizzle_pipe[4] = 4; 674 break; 675 case 6: 676 swizzle_pipe[0] = 0; 677 swizzle_pipe[1] = 2; 678 swizzle_pipe[2] = 4; 679 swizzle_pipe[3] = 5; 680 swizzle_pipe[4] = 1; 681 swizzle_pipe[5] = 3; 682 break; 683 case 7: 684 swizzle_pipe[0] = 0; 685 swizzle_pipe[1] = 2; 686 swizzle_pipe[2] = 4; 687 swizzle_pipe[3] = 6; 688 swizzle_pipe[4] = 1; 689 swizzle_pipe[5] = 3; 690 swizzle_pipe[6] = 5; 691 break; 692 case 8: 693 swizzle_pipe[0] = 0; 694 swizzle_pipe[1] = 2; 695 swizzle_pipe[2] = 4; 696 swizzle_pipe[3] = 6; 697 swizzle_pipe[4] = 1; 698 swizzle_pipe[5] = 3; 699 swizzle_pipe[6] = 5; 700 swizzle_pipe[7] = 7; 701 break; 702 } 703 704 cur_backend = 0; 705 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 706 while (((1 << cur_backend) & enabled_backends_mask) == 0) 707 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; 708 709 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 710 711 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; 712 } 713 714 return backend_map; 715} 716 717static int r600_count_pipe_bits(uint32_t val) 718{ 719 int i, ret = 0; 720 for (i = 0; i < 32; i++) { 721 ret += val & 1; 722 val >>= 1; 723 } 724 return ret; 725} 726 727static void r600_gfx_init(struct drm_device *dev, 728 drm_radeon_private_t *dev_priv) 729{ 730 int i, j, num_qd_pipes; 731 u32 sx_debug_1; 732 u32 tc_cntl; 733 u32 arb_pop; 734 u32 num_gs_verts_per_thread; 735 u32 vgt_gs_per_es; 736 u32 gs_prim_buffer_depth = 0; 737 u32 sq_ms_fifo_sizes; 738 u32 sq_config; 739 u32 sq_gpr_resource_mgmt_1 = 0; 740 u32 sq_gpr_resource_mgmt_2 = 0; 741 u32 sq_thread_resource_mgmt = 0; 742 u32 sq_stack_resource_mgmt_1 = 0; 743 u32 sq_stack_resource_mgmt_2 = 0; 744 u32 hdp_host_path_cntl; 745 u32 backend_map; 746 u32 gb_tiling_config = 0; 747 u32 cc_rb_backend_disable = 0; 748 u32 cc_gc_shader_pipe_config = 0; 749 u32 ramcfg; 750 751 /* setup chip specs */ 752 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 753 case CHIP_R600: 754 dev_priv->r600_max_pipes = 4; 755 dev_priv->r600_max_tile_pipes = 8; 756 dev_priv->r600_max_simds = 4; 757 dev_priv->r600_max_backends = 4; 758 dev_priv->r600_max_gprs = 256; 759 dev_priv->r600_max_threads = 192; 760 dev_priv->r600_max_stack_entries = 256; 761 dev_priv->r600_max_hw_contexts = 8; 762 dev_priv->r600_max_gs_threads = 16; 763 dev_priv->r600_sx_max_export_size = 128; 764 dev_priv->r600_sx_max_export_pos_size = 16; 765 dev_priv->r600_sx_max_export_smx_size = 128; 766 dev_priv->r600_sq_num_cf_insts = 2; 767 break; 768 case CHIP_RV630: 769 case CHIP_RV635: 770 dev_priv->r600_max_pipes = 2; 771 dev_priv->r600_max_tile_pipes = 2; 772 dev_priv->r600_max_simds = 3; 773 dev_priv->r600_max_backends = 1; 774 dev_priv->r600_max_gprs = 128; 775 dev_priv->r600_max_threads = 192; 776 dev_priv->r600_max_stack_entries = 128; 777 dev_priv->r600_max_hw_contexts = 8; 778 dev_priv->r600_max_gs_threads = 4; 779 dev_priv->r600_sx_max_export_size = 128; 780 dev_priv->r600_sx_max_export_pos_size = 16; 781 dev_priv->r600_sx_max_export_smx_size = 128; 782 dev_priv->r600_sq_num_cf_insts = 2; 783 break; 784 case CHIP_RV610: 785 case CHIP_RS780: 786 case CHIP_RV620: 787 dev_priv->r600_max_pipes = 1; 788 dev_priv->r600_max_tile_pipes = 1; 789 dev_priv->r600_max_simds = 2; 790 dev_priv->r600_max_backends = 1; 791 dev_priv->r600_max_gprs = 128; 792 dev_priv->r600_max_threads = 192; 793 dev_priv->r600_max_stack_entries = 128; 794 dev_priv->r600_max_hw_contexts = 4; 795 dev_priv->r600_max_gs_threads = 4; 796 dev_priv->r600_sx_max_export_size = 128; 797 dev_priv->r600_sx_max_export_pos_size = 16; 798 dev_priv->r600_sx_max_export_smx_size = 128; 799 dev_priv->r600_sq_num_cf_insts = 1; 800 break; 801 case CHIP_RV670: 802 dev_priv->r600_max_pipes = 4; 803 dev_priv->r600_max_tile_pipes = 4; 804 dev_priv->r600_max_simds = 4; 805 dev_priv->r600_max_backends = 4; 806 dev_priv->r600_max_gprs = 192; 807 dev_priv->r600_max_threads = 192; 808 dev_priv->r600_max_stack_entries = 256; 809 dev_priv->r600_max_hw_contexts = 8; 810 dev_priv->r600_max_gs_threads = 16; 811 dev_priv->r600_sx_max_export_size = 128; 812 dev_priv->r600_sx_max_export_pos_size = 16; 813 dev_priv->r600_sx_max_export_smx_size = 128; 814 dev_priv->r600_sq_num_cf_insts = 2; 815 break; 816 default: 817 break; 818 } 819 820 /* Initialize HDP */ 821 j = 0; 822 for (i = 0; i < 32; i++) { 823 RADEON_WRITE((0x2c14 + j), 0x00000000); 824 RADEON_WRITE((0x2c18 + j), 0x00000000); 825 RADEON_WRITE((0x2c1c + j), 0x00000000); 826 RADEON_WRITE((0x2c20 + j), 0x00000000); 827 RADEON_WRITE((0x2c24 + j), 0x00000000); 828 j += 0x18; 829 } 830 831 RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff)); 832 833 /* setup tiling, simd, pipe config */ 834 ramcfg = RADEON_READ(R600_RAMCFG); 835 836 switch (dev_priv->r600_max_tile_pipes) { 837 case 1: 838 gb_tiling_config |= R600_PIPE_TILING(0); 839 break; 840 case 2: 841 gb_tiling_config |= R600_PIPE_TILING(1); 842 break; 843 case 4: 844 gb_tiling_config |= R600_PIPE_TILING(2); 845 break; 846 case 8: 847 gb_tiling_config |= R600_PIPE_TILING(3); 848 break; 849 default: 850 break; 851 } 852 853 gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK); 854 855 gb_tiling_config |= R600_GROUP_SIZE(0); 856 857 if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) { 858 gb_tiling_config |= R600_ROW_TILING(3); 859 gb_tiling_config |= R600_SAMPLE_SPLIT(3); 860 } else { 861 gb_tiling_config |= 862 R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK)); 863 gb_tiling_config |= 864 R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK)); 865 } 866 867 gb_tiling_config |= R600_BANK_SWAPS(1); 868 869 backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes, 870 dev_priv->r600_max_backends, 871 (0xff << dev_priv->r600_max_backends) & 0xff); 872 gb_tiling_config |= R600_BACKEND_MAP(backend_map); 873 874 cc_gc_shader_pipe_config = 875 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK); 876 cc_gc_shader_pipe_config |= 877 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK); 878 879 cc_rb_backend_disable = 880 R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK); 881 882 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); 883 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 884 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 885 886 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 887 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 888 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 889 890 num_qd_pipes = 891 R6XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK); 892 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK); 893 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK); 894 895 /* set HW defaults for 3D engine */ 896 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) | 897 R600_ROQ_IB2_START(0x2b))); 898 899 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) | 900 R600_ROQ_END(0x40))); 901 902 RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO | 903 R600_SYNC_GRADIENT | 904 R600_SYNC_WALKER | 905 R600_SYNC_ALIGNER)); 906 907 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) 908 RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021); 909 910 sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1); 911 sx_debug_1 |= R600_SMX_EVENT_RELEASE; 912 if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600)) 913 sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS; 914 RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1); 915 916 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || 917 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || 918 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 919 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 920 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) 921 RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE); 922 else 923 RADEON_WRITE(R600_DB_DEBUG, 0); 924 925 RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) | 926 R600_DEPTH_FLUSH(16) | 927 R600_DEPTH_PENDING_FREE(4) | 928 R600_DEPTH_CACHELINE_FREE(16))); 929 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 930 RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0); 931 932 RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0)); 933 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0)); 934 935 sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES); 936 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 937 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 938 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) { 939 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) | 940 R600_FETCH_FIFO_HIWATER(0xa) | 941 R600_DONE_FIFO_HIWATER(0xe0) | 942 R600_ALU_UPDATE_FIFO_HIWATER(0x8)); 943 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || 944 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) { 945 sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff); 946 sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4); 947 } 948 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 949 950 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 951 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 952 */ 953 sq_config = RADEON_READ(R600_SQ_CONFIG); 954 sq_config &= ~(R600_PS_PRIO(3) | 955 R600_VS_PRIO(3) | 956 R600_GS_PRIO(3) | 957 R600_ES_PRIO(3)); 958 sq_config |= (R600_DX9_CONSTS | 959 R600_VC_ENABLE | 960 R600_PS_PRIO(0) | 961 R600_VS_PRIO(1) | 962 R600_GS_PRIO(2) | 963 R600_ES_PRIO(3)); 964 965 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) { 966 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) | 967 R600_NUM_VS_GPRS(124) | 968 R600_NUM_CLAUSE_TEMP_GPRS(4)); 969 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) | 970 R600_NUM_ES_GPRS(0)); 971 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) | 972 R600_NUM_VS_THREADS(48) | 973 R600_NUM_GS_THREADS(4) | 974 R600_NUM_ES_THREADS(4)); 975 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) | 976 R600_NUM_VS_STACK_ENTRIES(128)); 977 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) | 978 R600_NUM_ES_STACK_ENTRIES(0)); 979 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 980 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 981 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) { 982 /* no vertex cache */ 983 sq_config &= ~R600_VC_ENABLE; 984 985 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 986 R600_NUM_VS_GPRS(44) | 987 R600_NUM_CLAUSE_TEMP_GPRS(2)); 988 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) | 989 R600_NUM_ES_GPRS(17)); 990 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 991 R600_NUM_VS_THREADS(78) | 992 R600_NUM_GS_THREADS(4) | 993 R600_NUM_ES_THREADS(31)); 994 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) | 995 R600_NUM_VS_STACK_ENTRIES(40)); 996 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) | 997 R600_NUM_ES_STACK_ENTRIES(16)); 998 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || 999 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) { 1000 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 1001 R600_NUM_VS_GPRS(44) | 1002 R600_NUM_CLAUSE_TEMP_GPRS(2)); 1003 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) | 1004 R600_NUM_ES_GPRS(18)); 1005 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 1006 R600_NUM_VS_THREADS(78) | 1007 R600_NUM_GS_THREADS(4) | 1008 R600_NUM_ES_THREADS(31)); 1009 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) | 1010 R600_NUM_VS_STACK_ENTRIES(40)); 1011 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) | 1012 R600_NUM_ES_STACK_ENTRIES(16)); 1013 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) { 1014 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 1015 R600_NUM_VS_GPRS(44) | 1016 R600_NUM_CLAUSE_TEMP_GPRS(2)); 1017 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) | 1018 R600_NUM_ES_GPRS(17)); 1019 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 1020 R600_NUM_VS_THREADS(78) | 1021 R600_NUM_GS_THREADS(4) | 1022 R600_NUM_ES_THREADS(31)); 1023 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) | 1024 R600_NUM_VS_STACK_ENTRIES(64)); 1025 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) | 1026 R600_NUM_ES_STACK_ENTRIES(64)); 1027 } 1028 1029 RADEON_WRITE(R600_SQ_CONFIG, sq_config); 1030 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 1031 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 1032 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1033 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 1034 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 1035 1036 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 1037 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 1038 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) 1039 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY)); 1040 else 1041 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC)); 1042 1043 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) | 1044 R600_S0_Y(0x4) | 1045 R600_S1_X(0x4) | 1046 R600_S1_Y(0xc))); 1047 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) | 1048 R600_S0_Y(0xe) | 1049 R600_S1_X(0x2) | 1050 R600_S1_Y(0x2) | 1051 R600_S2_X(0xa) | 1052 R600_S2_Y(0x6) | 1053 R600_S3_X(0x6) | 1054 R600_S3_Y(0xa))); 1055 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) | 1056 R600_S0_Y(0xb) | 1057 R600_S1_X(0x4) | 1058 R600_S1_Y(0xc) | 1059 R600_S2_X(0x1) | 1060 R600_S2_Y(0x6) | 1061 R600_S3_X(0xa) | 1062 R600_S3_Y(0xe))); 1063 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) | 1064 R600_S4_Y(0x1) | 1065 R600_S5_X(0x0) | 1066 R600_S5_Y(0x0) | 1067 R600_S6_X(0xb) | 1068 R600_S6_Y(0x4) | 1069 R600_S7_X(0x7) | 1070 R600_S7_Y(0x8))); 1071 1072 1073 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1074 case CHIP_R600: 1075 case CHIP_RV630: 1076 case CHIP_RV635: 1077 gs_prim_buffer_depth = 0; 1078 break; 1079 case CHIP_RV610: 1080 case CHIP_RS780: 1081 case CHIP_RV620: 1082 gs_prim_buffer_depth = 32; 1083 break; 1084 case CHIP_RV670: 1085 gs_prim_buffer_depth = 128; 1086 break; 1087 default: 1088 break; 1089 } 1090 1091 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; 1092 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 1093 /* Max value for this is 256 */ 1094 if (vgt_gs_per_es > 256) 1095 vgt_gs_per_es = 256; 1096 1097 RADEON_WRITE(R600_VGT_ES_PER_GS, 128); 1098 RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es); 1099 RADEON_WRITE(R600_VGT_GS_PER_VS, 2); 1100 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16); 1101 1102 /* more default values. 2D/3D driver should adjust as needed */ 1103 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0); 1104 RADEON_WRITE(R600_VGT_STRMOUT_EN, 0); 1105 RADEON_WRITE(R600_SX_MISC, 0); 1106 RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0); 1107 RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0); 1108 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0); 1109 RADEON_WRITE(R600_SPI_INPUT_Z, 0); 1110 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2)); 1111 RADEON_WRITE(R600_CB_COLOR7_FRAG, 0); 1112 1113 /* clear render buffer base addresses */ 1114 RADEON_WRITE(R600_CB_COLOR0_BASE, 0); 1115 RADEON_WRITE(R600_CB_COLOR1_BASE, 0); 1116 RADEON_WRITE(R600_CB_COLOR2_BASE, 0); 1117 RADEON_WRITE(R600_CB_COLOR3_BASE, 0); 1118 RADEON_WRITE(R600_CB_COLOR4_BASE, 0); 1119 RADEON_WRITE(R600_CB_COLOR5_BASE, 0); 1120 RADEON_WRITE(R600_CB_COLOR6_BASE, 0); 1121 RADEON_WRITE(R600_CB_COLOR7_BASE, 0); 1122 1123 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1124 case CHIP_RV610: 1125 case CHIP_RS780: 1126 case CHIP_RV620: 1127 tc_cntl = R600_TC_L2_SIZE(8); 1128 break; 1129 case CHIP_RV630: 1130 case CHIP_RV635: 1131 tc_cntl = R600_TC_L2_SIZE(4); 1132 break; 1133 case CHIP_R600: 1134 tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT; 1135 break; 1136 default: 1137 tc_cntl = R600_TC_L2_SIZE(0); 1138 break; 1139 } 1140 1141 RADEON_WRITE(R600_TC_CNTL, tc_cntl); 1142 1143 hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL); 1144 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1145 1146 arb_pop = RADEON_READ(R600_ARB_POP); 1147 arb_pop |= R600_ENABLE_TC128; 1148 RADEON_WRITE(R600_ARB_POP, arb_pop); 1149 1150 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1151 RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA | 1152 R600_NUM_CLIP_SEQ(3))); 1153 RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095)); 1154 1155} 1156 1157static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes, 1158 u32 num_backends, 1159 u32 backend_disable_mask) 1160{ 1161 u32 backend_map = 0; 1162 u32 enabled_backends_mask; 1163 u32 enabled_backends_count; 1164 u32 cur_pipe; 1165 u32 swizzle_pipe[R7XX_MAX_PIPES]; 1166 u32 cur_backend; 1167 u32 i; 1168 1169 if (num_tile_pipes > R7XX_MAX_PIPES) 1170 num_tile_pipes = R7XX_MAX_PIPES; 1171 if (num_tile_pipes < 1) 1172 num_tile_pipes = 1; 1173 if (num_backends > R7XX_MAX_BACKENDS) 1174 num_backends = R7XX_MAX_BACKENDS; 1175 if (num_backends < 1) 1176 num_backends = 1; 1177 1178 enabled_backends_mask = 0; 1179 enabled_backends_count = 0; 1180 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) { 1181 if (((backend_disable_mask >> i) & 1) == 0) { 1182 enabled_backends_mask |= (1 << i); 1183 ++enabled_backends_count; 1184 } 1185 if (enabled_backends_count == num_backends) 1186 break; 1187 } 1188 1189 if (enabled_backends_count == 0) { 1190 enabled_backends_mask = 1; 1191 enabled_backends_count = 1; 1192 } 1193 1194 if (enabled_backends_count != num_backends) 1195 num_backends = enabled_backends_count; 1196 1197 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES); 1198 switch (num_tile_pipes) { 1199 case 1: 1200 swizzle_pipe[0] = 0; 1201 break; 1202 case 2: 1203 swizzle_pipe[0] = 0; 1204 swizzle_pipe[1] = 1; 1205 break; 1206 case 3: 1207 swizzle_pipe[0] = 0; 1208 swizzle_pipe[1] = 2; 1209 swizzle_pipe[2] = 1; 1210 break; 1211 case 4: 1212 swizzle_pipe[0] = 0; 1213 swizzle_pipe[1] = 2; 1214 swizzle_pipe[2] = 3; 1215 swizzle_pipe[3] = 1; 1216 break; 1217 case 5: 1218 swizzle_pipe[0] = 0; 1219 swizzle_pipe[1] = 2; 1220 swizzle_pipe[2] = 4; 1221 swizzle_pipe[3] = 1; 1222 swizzle_pipe[4] = 3; 1223 break; 1224 case 6: 1225 swizzle_pipe[0] = 0; 1226 swizzle_pipe[1] = 2; 1227 swizzle_pipe[2] = 4; 1228 swizzle_pipe[3] = 5; 1229 swizzle_pipe[4] = 3; 1230 swizzle_pipe[5] = 1; 1231 break; 1232 case 7: 1233 swizzle_pipe[0] = 0; 1234 swizzle_pipe[1] = 2; 1235 swizzle_pipe[2] = 4; 1236 swizzle_pipe[3] = 6; 1237 swizzle_pipe[4] = 3; 1238 swizzle_pipe[5] = 1; 1239 swizzle_pipe[6] = 5; 1240 break; 1241 case 8: 1242 swizzle_pipe[0] = 0; 1243 swizzle_pipe[1] = 2; 1244 swizzle_pipe[2] = 4; 1245 swizzle_pipe[3] = 6; 1246 swizzle_pipe[4] = 3; 1247 swizzle_pipe[5] = 1; 1248 swizzle_pipe[6] = 7; 1249 swizzle_pipe[7] = 5; 1250 break; 1251 } 1252 1253 cur_backend = 0; 1254 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 1255 while (((1 << cur_backend) & enabled_backends_mask) == 0) 1256 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 1257 1258 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 1259 1260 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 1261 } 1262 1263 return backend_map; 1264} 1265 1266static void r700_gfx_init(struct drm_device *dev, 1267 drm_radeon_private_t *dev_priv) 1268{ 1269 int i, j, num_qd_pipes; 1270 u32 sx_debug_1; 1271 u32 smx_dc_ctl0; 1272 u32 num_gs_verts_per_thread; 1273 u32 vgt_gs_per_es; 1274 u32 gs_prim_buffer_depth = 0; 1275 u32 sq_ms_fifo_sizes; 1276 u32 sq_config; 1277 u32 sq_thread_resource_mgmt; 1278 u32 hdp_host_path_cntl; 1279 u32 sq_dyn_gpr_size_simd_ab_0; 1280 u32 backend_map; 1281 u32 gb_tiling_config = 0; 1282 u32 cc_rb_backend_disable = 0; 1283 u32 cc_gc_shader_pipe_config = 0; 1284 u32 mc_arb_ramcfg; 1285 u32 db_debug4; 1286 1287 /* setup chip specs */ 1288 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1289 case CHIP_RV770: 1290 dev_priv->r600_max_pipes = 4; 1291 dev_priv->r600_max_tile_pipes = 8; 1292 dev_priv->r600_max_simds = 10; 1293 dev_priv->r600_max_backends = 4; 1294 dev_priv->r600_max_gprs = 256; 1295 dev_priv->r600_max_threads = 248; 1296 dev_priv->r600_max_stack_entries = 512; 1297 dev_priv->r600_max_hw_contexts = 8; 1298 dev_priv->r600_max_gs_threads = 16 * 2; 1299 dev_priv->r600_sx_max_export_size = 128; 1300 dev_priv->r600_sx_max_export_pos_size = 16; 1301 dev_priv->r600_sx_max_export_smx_size = 112; 1302 dev_priv->r600_sq_num_cf_insts = 2; 1303 1304 dev_priv->r700_sx_num_of_sets = 7; 1305 dev_priv->r700_sc_prim_fifo_size = 0xF9; 1306 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1307 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1308 break; 1309 case CHIP_RV730: 1310 dev_priv->r600_max_pipes = 2; 1311 dev_priv->r600_max_tile_pipes = 4; 1312 dev_priv->r600_max_simds = 8; 1313 dev_priv->r600_max_backends = 2; 1314 dev_priv->r600_max_gprs = 128; 1315 dev_priv->r600_max_threads = 248; 1316 dev_priv->r600_max_stack_entries = 256; 1317 dev_priv->r600_max_hw_contexts = 8; 1318 dev_priv->r600_max_gs_threads = 16 * 2; 1319 dev_priv->r600_sx_max_export_size = 256; 1320 dev_priv->r600_sx_max_export_pos_size = 32; 1321 dev_priv->r600_sx_max_export_smx_size = 224; 1322 dev_priv->r600_sq_num_cf_insts = 2; 1323 1324 dev_priv->r700_sx_num_of_sets = 7; 1325 dev_priv->r700_sc_prim_fifo_size = 0xf9; 1326 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1327 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1328 if (dev_priv->r600_sx_max_export_pos_size > 16) { 1329 dev_priv->r600_sx_max_export_pos_size -= 16; 1330 dev_priv->r600_sx_max_export_smx_size += 16; 1331 } 1332 break; 1333 case CHIP_RV710: 1334 dev_priv->r600_max_pipes = 2; 1335 dev_priv->r600_max_tile_pipes = 2; 1336 dev_priv->r600_max_simds = 2; 1337 dev_priv->r600_max_backends = 1; 1338 dev_priv->r600_max_gprs = 256; 1339 dev_priv->r600_max_threads = 192; 1340 dev_priv->r600_max_stack_entries = 256; 1341 dev_priv->r600_max_hw_contexts = 4; 1342 dev_priv->r600_max_gs_threads = 8 * 2; 1343 dev_priv->r600_sx_max_export_size = 128; 1344 dev_priv->r600_sx_max_export_pos_size = 16; 1345 dev_priv->r600_sx_max_export_smx_size = 112; 1346 dev_priv->r600_sq_num_cf_insts = 1; 1347 1348 dev_priv->r700_sx_num_of_sets = 7; 1349 dev_priv->r700_sc_prim_fifo_size = 0x40; 1350 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1351 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1352 break; 1353 case CHIP_RV740: 1354 dev_priv->r600_max_pipes = 4; 1355 dev_priv->r600_max_tile_pipes = 4; 1356 dev_priv->r600_max_simds = 8; 1357 dev_priv->r600_max_backends = 4; 1358 dev_priv->r600_max_gprs = 256; 1359 dev_priv->r600_max_threads = 248; 1360 dev_priv->r600_max_stack_entries = 512; 1361 dev_priv->r600_max_hw_contexts = 8; 1362 dev_priv->r600_max_gs_threads = 16 * 2; 1363 dev_priv->r600_sx_max_export_size = 256; 1364 dev_priv->r600_sx_max_export_pos_size = 32; 1365 dev_priv->r600_sx_max_export_smx_size = 224; 1366 dev_priv->r600_sq_num_cf_insts = 2; 1367 1368 dev_priv->r700_sx_num_of_sets = 7; 1369 dev_priv->r700_sc_prim_fifo_size = 0x100; 1370 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1371 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1372 1373 if (dev_priv->r600_sx_max_export_pos_size > 16) { 1374 dev_priv->r600_sx_max_export_pos_size -= 16; 1375 dev_priv->r600_sx_max_export_smx_size += 16; 1376 } 1377 break; 1378 default: 1379 break; 1380 } 1381 1382 /* Initialize HDP */ 1383 j = 0; 1384 for (i = 0; i < 32; i++) { 1385 RADEON_WRITE((0x2c14 + j), 0x00000000); 1386 RADEON_WRITE((0x2c18 + j), 0x00000000); 1387 RADEON_WRITE((0x2c1c + j), 0x00000000); 1388 RADEON_WRITE((0x2c20 + j), 0x00000000); 1389 RADEON_WRITE((0x2c24 + j), 0x00000000); 1390 j += 0x18; 1391 } 1392 1393 RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff)); 1394 1395 /* setup tiling, simd, pipe config */ 1396 mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG); 1397 1398 switch (dev_priv->r600_max_tile_pipes) { 1399 case 1: 1400 gb_tiling_config |= R600_PIPE_TILING(0); 1401 break; 1402 case 2: 1403 gb_tiling_config |= R600_PIPE_TILING(1); 1404 break; 1405 case 4: 1406 gb_tiling_config |= R600_PIPE_TILING(2); 1407 break; 1408 case 8: 1409 gb_tiling_config |= R600_PIPE_TILING(3); 1410 break; 1411 default: 1412 break; 1413 } 1414 1415 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770) 1416 gb_tiling_config |= R600_BANK_TILING(1); 1417 else 1418 gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK); 1419 1420 gb_tiling_config |= R600_GROUP_SIZE(0); 1421 1422 if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) { 1423 gb_tiling_config |= R600_ROW_TILING(3); 1424 gb_tiling_config |= R600_SAMPLE_SPLIT(3); 1425 } else { 1426 gb_tiling_config |= 1427 R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK)); 1428 gb_tiling_config |= 1429 R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK)); 1430 } 1431 1432 gb_tiling_config |= R600_BANK_SWAPS(1); 1433 1434 backend_map = r700_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes, 1435 dev_priv->r600_max_backends, 1436 (0xff << dev_priv->r600_max_backends) & 0xff); 1437 gb_tiling_config |= R600_BACKEND_MAP(backend_map); 1438 1439 cc_gc_shader_pipe_config = 1440 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK); 1441 cc_gc_shader_pipe_config |= 1442 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK); 1443 1444 cc_rb_backend_disable = 1445 R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK); 1446 1447 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); 1448 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1449 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1450 1451 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 1452 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 1453 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 1454 1455 RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); 1456 RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0); 1457 RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0); 1458 RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0); 1459 RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0); 1460 1461 num_qd_pipes = 1462 R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK); 1463 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK); 1464 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK); 1465 1466 /* set HW defaults for 3D engine */ 1467 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) | 1468 R600_ROQ_IB2_START(0x2b))); 1469 1470 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30)); 1471 1472 RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO | 1473 R600_SYNC_GRADIENT | 1474 R600_SYNC_WALKER | 1475 R600_SYNC_ALIGNER)); 1476 1477 sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1); 1478 sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS; 1479 RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1); 1480 1481 smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0); 1482 smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff); 1483 smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1); 1484 RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0); 1485 1486 RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) | 1487 R700_GS_FLUSH_CTL(4) | 1488 R700_ACK_FLUSH_CTL(3) | 1489 R700_SYNC_FLUSH_CTL)); 1490 1491 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770) 1492 RADEON_WRITE(R700_DB_DEBUG3, R700_DB_CLK_OFF_DELAY(0x1f)); 1493 else { 1494 db_debug4 = RADEON_READ(RV700_DB_DEBUG4); 1495 db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER; 1496 RADEON_WRITE(RV700_DB_DEBUG4, db_debug4); 1497 } 1498 1499 RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) | 1500 R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) | 1501 R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1))); 1502 1503 RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) | 1504 R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) | 1505 R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize))); 1506 1507 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1508 1509 RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1); 1510 1511 RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0)); 1512 1513 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4)); 1514 1515 RADEON_WRITE(R600_CP_PERFMON_CNTL, 0); 1516 1517 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) | 1518 R600_DONE_FIFO_HIWATER(0xe0) | 1519 R600_ALU_UPDATE_FIFO_HIWATER(0x8)); 1520 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1521 case CHIP_RV770: 1522 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1); 1523 break; 1524 case CHIP_RV730: 1525 case CHIP_RV710: 1526 case CHIP_RV740: 1527 default: 1528 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4); 1529 break; 1530 } 1531 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 1532 1533 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 1534 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 1535 */ 1536 sq_config = RADEON_READ(R600_SQ_CONFIG); 1537 sq_config &= ~(R600_PS_PRIO(3) | 1538 R600_VS_PRIO(3) | 1539 R600_GS_PRIO(3) | 1540 R600_ES_PRIO(3)); 1541 sq_config |= (R600_DX9_CONSTS | 1542 R600_VC_ENABLE | 1543 R600_EXPORT_SRC_C | 1544 R600_PS_PRIO(0) | 1545 R600_VS_PRIO(1) | 1546 R600_GS_PRIO(2) | 1547 R600_ES_PRIO(3)); 1548 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) 1549 /* no vertex cache */ 1550 sq_config &= ~R600_VC_ENABLE; 1551 1552 RADEON_WRITE(R600_SQ_CONFIG, sq_config); 1553 1554 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) | 1555 R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) | 1556 R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2))); 1557 1558 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) | 1559 R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64))); 1560 1561 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) | 1562 R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) | 1563 R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8)); 1564 if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads) 1565 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads); 1566 else 1567 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8); 1568 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1569 1570 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) | 1571 R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); 1572 1573 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) | 1574 R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); 1575 1576 sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) | 1577 R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) | 1578 R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) | 1579 R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64)); 1580 1581 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); 1582 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); 1583 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); 1584 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); 1585 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); 1586 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); 1587 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); 1588 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); 1589 1590 RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) | 1591 R700_FORCE_EOV_MAX_REZ_CNT(255))); 1592 1593 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) 1594 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) | 1595 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO))); 1596 else 1597 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) | 1598 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO))); 1599 1600 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1601 case CHIP_RV770: 1602 case CHIP_RV730: 1603 case CHIP_RV740: 1604 gs_prim_buffer_depth = 384; 1605 break; 1606 case CHIP_RV710: 1607 gs_prim_buffer_depth = 128; 1608 break; 1609 default: 1610 break; 1611 } 1612 1613 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; 1614 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 1615 /* Max value for this is 256 */ 1616 if (vgt_gs_per_es > 256) 1617 vgt_gs_per_es = 256; 1618 1619 RADEON_WRITE(R600_VGT_ES_PER_GS, 128); 1620 RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es); 1621 RADEON_WRITE(R600_VGT_GS_PER_VS, 2); 1622 1623 /* more default values. 2D/3D driver should adjust as needed */ 1624 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16); 1625 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0); 1626 RADEON_WRITE(R600_VGT_STRMOUT_EN, 0); 1627 RADEON_WRITE(R600_SX_MISC, 0); 1628 RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0); 1629 RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa); 1630 RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0); 1631 RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff); 1632 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0); 1633 RADEON_WRITE(R600_SPI_INPUT_Z, 0); 1634 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2)); 1635 RADEON_WRITE(R600_CB_COLOR7_FRAG, 0); 1636 1637 /* clear render buffer base addresses */ 1638 RADEON_WRITE(R600_CB_COLOR0_BASE, 0); 1639 RADEON_WRITE(R600_CB_COLOR1_BASE, 0); 1640 RADEON_WRITE(R600_CB_COLOR2_BASE, 0); 1641 RADEON_WRITE(R600_CB_COLOR3_BASE, 0); 1642 RADEON_WRITE(R600_CB_COLOR4_BASE, 0); 1643 RADEON_WRITE(R600_CB_COLOR5_BASE, 0); 1644 RADEON_WRITE(R600_CB_COLOR6_BASE, 0); 1645 RADEON_WRITE(R600_CB_COLOR7_BASE, 0); 1646 1647 RADEON_WRITE(R700_TCP_CNTL, 0); 1648 1649 hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL); 1650 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1651 1652 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1653 1654 RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA | 1655 R600_NUM_CLIP_SEQ(3))); 1656 1657} 1658 1659static void r600_cp_init_ring_buffer(struct drm_device *dev, 1660 drm_radeon_private_t *dev_priv, 1661 struct drm_file *file_priv) 1662{ 1663 struct drm_radeon_master_private *master_priv; 1664 u32 ring_start; 1665 u64 rptr_addr; 1666 1667 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 1668 r700_gfx_init(dev, dev_priv); 1669 else 1670 r600_gfx_init(dev, dev_priv); 1671 1672 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 1673 RADEON_READ(R600_GRBM_SOFT_RESET); 1674 DRM_UDELAY(15000); 1675 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 1676 1677 1678 /* Set ring buffer size */ 1679#ifdef __BIG_ENDIAN 1680 RADEON_WRITE(R600_CP_RB_CNTL, 1681 RADEON_BUF_SWAP_32BIT | 1682 RADEON_RB_NO_UPDATE | 1683 (dev_priv->ring.rptr_update_l2qw << 8) | 1684 dev_priv->ring.size_l2qw); 1685#else 1686 RADEON_WRITE(R600_CP_RB_CNTL, 1687 RADEON_RB_NO_UPDATE | 1688 (dev_priv->ring.rptr_update_l2qw << 8) | 1689 dev_priv->ring.size_l2qw); 1690#endif 1691 1692 RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x4); 1693 1694 /* Set the write pointer delay */ 1695 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); 1696 1697#ifdef __BIG_ENDIAN 1698 RADEON_WRITE(R600_CP_RB_CNTL, 1699 RADEON_BUF_SWAP_32BIT | 1700 RADEON_RB_NO_UPDATE | 1701 RADEON_RB_RPTR_WR_ENA | 1702 (dev_priv->ring.rptr_update_l2qw << 8) | 1703 dev_priv->ring.size_l2qw); 1704#else 1705 RADEON_WRITE(R600_CP_RB_CNTL, 1706 RADEON_RB_NO_UPDATE | 1707 RADEON_RB_RPTR_WR_ENA | 1708 (dev_priv->ring.rptr_update_l2qw << 8) | 1709 dev_priv->ring.size_l2qw); 1710#endif 1711 1712 /* Initialize the ring buffer's read and write pointers */ 1713 RADEON_WRITE(R600_CP_RB_RPTR_WR, 0); 1714 RADEON_WRITE(R600_CP_RB_WPTR, 0); 1715 SET_RING_HEAD(dev_priv, 0); 1716 dev_priv->ring.tail = 0; 1717 1718#if __OS_HAS_AGP 1719 if (dev_priv->flags & RADEON_IS_AGP) { 1720 rptr_addr = dev_priv->ring_rptr->offset 1721 - dev->agp->base + 1722 dev_priv->gart_vm_start; 1723 } else 1724#endif 1725 { 1726 rptr_addr = dev_priv->ring_rptr->offset 1727 - ((unsigned long) dev->sg->virtual) 1728 + dev_priv->gart_vm_start; 1729 } 1730 RADEON_WRITE(R600_CP_RB_RPTR_ADDR, 1731 rptr_addr & 0xffffffff); 1732 RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI, 1733 upper_32_bits(rptr_addr)); 1734 1735#ifdef __BIG_ENDIAN 1736 RADEON_WRITE(R600_CP_RB_CNTL, 1737 RADEON_BUF_SWAP_32BIT | 1738 (dev_priv->ring.rptr_update_l2qw << 8) | 1739 dev_priv->ring.size_l2qw); 1740#else 1741 RADEON_WRITE(R600_CP_RB_CNTL, 1742 (dev_priv->ring.rptr_update_l2qw << 8) | 1743 dev_priv->ring.size_l2qw); 1744#endif 1745 1746#if __OS_HAS_AGP 1747 if (dev_priv->flags & RADEON_IS_AGP) { 1748 /* XXX */ 1749 radeon_write_agp_base(dev_priv, dev->agp->base); 1750 1751 /* XXX */ 1752 radeon_write_agp_location(dev_priv, 1753 (((dev_priv->gart_vm_start - 1 + 1754 dev_priv->gart_size) & 0xffff0000) | 1755 (dev_priv->gart_vm_start >> 16))); 1756 1757 ring_start = (dev_priv->cp_ring->offset 1758 - dev->agp->base 1759 + dev_priv->gart_vm_start); 1760 } else 1761#endif 1762 ring_start = (dev_priv->cp_ring->offset 1763 - (unsigned long)dev->sg->virtual 1764 + dev_priv->gart_vm_start); 1765 1766 RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8); 1767 1768 RADEON_WRITE(R600_CP_ME_CNTL, 0xff); 1769 1770 RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28)); 1771 1772 /* Initialize the scratch register pointer. This will cause 1773 * the scratch register values to be written out to memory 1774 * whenever they are updated. 1775 * 1776 * We simply put this behind the ring read pointer, this works 1777 * with PCI GART as well as (whatever kind of) AGP GART 1778 */ 1779 { 1780 u64 scratch_addr; 1781 1782 scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR); 1783 scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32; 1784 scratch_addr += R600_SCRATCH_REG_OFFSET; 1785 scratch_addr >>= 8; 1786 scratch_addr &= 0xffffffff; 1787 1788 RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr); 1789 } 1790 1791 RADEON_WRITE(R600_SCRATCH_UMSK, 0x7); 1792 1793 /* Turn on bus mastering */ 1794 radeon_enable_bm(dev_priv); 1795 1796 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0); 1797 RADEON_WRITE(R600_LAST_FRAME_REG, 0); 1798 1799 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0); 1800 RADEON_WRITE(R600_LAST_DISPATCH_REG, 0); 1801 1802 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0); 1803 RADEON_WRITE(R600_LAST_CLEAR_REG, 0); 1804 1805 /* reset sarea copies of these */ 1806 master_priv = file_priv->master->driver_priv; 1807 if (master_priv->sarea_priv) { 1808 master_priv->sarea_priv->last_frame = 0; 1809 master_priv->sarea_priv->last_dispatch = 0; 1810 master_priv->sarea_priv->last_clear = 0; 1811 } 1812 1813 r600_do_wait_for_idle(dev_priv); 1814 1815} 1816 1817int r600_do_cleanup_cp(struct drm_device *dev) 1818{ 1819 drm_radeon_private_t *dev_priv = dev->dev_private; 1820 DRM_DEBUG("\n"); 1821 1822 /* Make sure interrupts are disabled here because the uninstall ioctl 1823 * may not have been called from userspace and after dev_private 1824 * is freed, it's too late. 1825 */ 1826 if (dev->irq_enabled) 1827 drm_irq_uninstall(dev); 1828 1829#if __OS_HAS_AGP 1830 if (dev_priv->flags & RADEON_IS_AGP) { 1831 if (dev_priv->cp_ring != NULL) { 1832 drm_core_ioremapfree(dev_priv->cp_ring, dev); 1833 dev_priv->cp_ring = NULL; 1834 } 1835 if (dev_priv->ring_rptr != NULL) { 1836 drm_core_ioremapfree(dev_priv->ring_rptr, dev); 1837 dev_priv->ring_rptr = NULL; 1838 } 1839 if (dev->agp_buffer_map != NULL) { 1840 drm_core_ioremapfree(dev->agp_buffer_map, dev); 1841 dev->agp_buffer_map = NULL; 1842 } 1843 } else 1844#endif 1845 { 1846 1847 if (dev_priv->gart_info.bus_addr) 1848 r600_page_table_cleanup(dev, &dev_priv->gart_info); 1849 1850 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) { 1851 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); 1852 dev_priv->gart_info.addr = NULL; 1853 } 1854 } 1855 /* only clear to the start of flags */ 1856 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); 1857 1858 return 0; 1859} 1860 1861int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, 1862 struct drm_file *file_priv) 1863{ 1864 drm_radeon_private_t *dev_priv = dev->dev_private; 1865 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; 1866 1867 DRM_DEBUG("\n"); 1868 1869 /* if we require new memory map but we don't have it fail */ 1870 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { 1871 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); 1872 r600_do_cleanup_cp(dev); 1873 return -EINVAL; 1874 } 1875 1876 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) { 1877 DRM_DEBUG("Forcing AGP card to PCI mode\n"); 1878 dev_priv->flags &= ~RADEON_IS_AGP; 1879 /* The writeback test succeeds, but when writeback is enabled, 1880 * the ring buffer read ptr update fails after first 128 bytes. 1881 */ 1882 radeon_no_wb = 1; 1883 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) 1884 && !init->is_pci) { 1885 DRM_DEBUG("Restoring AGP flag\n"); 1886 dev_priv->flags |= RADEON_IS_AGP; 1887 } 1888 1889 dev_priv->usec_timeout = init->usec_timeout; 1890 if (dev_priv->usec_timeout < 1 || 1891 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { 1892 DRM_DEBUG("TIMEOUT problem!\n"); 1893 r600_do_cleanup_cp(dev); 1894 return -EINVAL; 1895 } 1896 1897 /* Enable vblank on CRTC1 for older X servers 1898 */ 1899 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; 1900 1901 dev_priv->cp_mode = init->cp_mode; 1902 1903 /* We don't support anything other than bus-mastering ring mode, 1904 * but the ring can be in either AGP or PCI space for the ring 1905 * read pointer. 1906 */ 1907 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && 1908 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { 1909 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); 1910 r600_do_cleanup_cp(dev); 1911 return -EINVAL; 1912 } 1913 1914 switch (init->fb_bpp) { 1915 case 16: 1916 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; 1917 break; 1918 case 32: 1919 default: 1920 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; 1921 break; 1922 } 1923 dev_priv->front_offset = init->front_offset; 1924 dev_priv->front_pitch = init->front_pitch; 1925 dev_priv->back_offset = init->back_offset; 1926 dev_priv->back_pitch = init->back_pitch; 1927 1928 dev_priv->ring_offset = init->ring_offset; 1929 dev_priv->ring_rptr_offset = init->ring_rptr_offset; 1930 dev_priv->buffers_offset = init->buffers_offset; 1931 dev_priv->gart_textures_offset = init->gart_textures_offset; 1932 1933 master_priv->sarea = drm_getsarea(dev); 1934 if (!master_priv->sarea) { 1935 DRM_ERROR("could not find sarea!\n"); 1936 r600_do_cleanup_cp(dev); 1937 return -EINVAL; 1938 } 1939 1940 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); 1941 if (!dev_priv->cp_ring) { 1942 DRM_ERROR("could not find cp ring region!\n"); 1943 r600_do_cleanup_cp(dev); 1944 return -EINVAL; 1945 } 1946 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); 1947 if (!dev_priv->ring_rptr) { 1948 DRM_ERROR("could not find ring read pointer!\n"); 1949 r600_do_cleanup_cp(dev); 1950 return -EINVAL; 1951 } 1952 dev->agp_buffer_token = init->buffers_offset; 1953 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); 1954 if (!dev->agp_buffer_map) { 1955 DRM_ERROR("could not find dma buffer region!\n"); 1956 r600_do_cleanup_cp(dev); 1957 return -EINVAL; 1958 } 1959 1960 if (init->gart_textures_offset) { 1961 dev_priv->gart_textures = 1962 drm_core_findmap(dev, init->gart_textures_offset); 1963 if (!dev_priv->gart_textures) { 1964 DRM_ERROR("could not find GART texture region!\n"); 1965 r600_do_cleanup_cp(dev); 1966 return -EINVAL; 1967 } 1968 } 1969 1970#if __OS_HAS_AGP 1971 /* XXX */ 1972 if (dev_priv->flags & RADEON_IS_AGP) { 1973 drm_core_ioremap_wc(dev_priv->cp_ring, dev); 1974 drm_core_ioremap_wc(dev_priv->ring_rptr, dev); 1975 drm_core_ioremap_wc(dev->agp_buffer_map, dev); 1976 if (!dev_priv->cp_ring->handle || 1977 !dev_priv->ring_rptr->handle || 1978 !dev->agp_buffer_map->handle) { 1979 DRM_ERROR("could not find ioremap agp regions!\n"); 1980 r600_do_cleanup_cp(dev); 1981 return -EINVAL; 1982 } 1983 } else 1984#endif 1985 { 1986 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset; 1987 dev_priv->ring_rptr->handle = 1988 (void *)dev_priv->ring_rptr->offset; 1989 dev->agp_buffer_map->handle = 1990 (void *)dev->agp_buffer_map->offset; 1991 1992 DRM_DEBUG("dev_priv->cp_ring->handle %p\n", 1993 dev_priv->cp_ring->handle); 1994 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", 1995 dev_priv->ring_rptr->handle); 1996 DRM_DEBUG("dev->agp_buffer_map->handle %p\n", 1997 dev->agp_buffer_map->handle); 1998 } 1999 2000 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24; 2001 dev_priv->fb_size = 2002 (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000) 2003 - dev_priv->fb_location; 2004 2005 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | 2006 ((dev_priv->front_offset 2007 + dev_priv->fb_location) >> 10)); 2008 2009 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | 2010 ((dev_priv->back_offset 2011 + dev_priv->fb_location) >> 10)); 2012 2013 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | 2014 ((dev_priv->depth_offset 2015 + dev_priv->fb_location) >> 10)); 2016 2017 dev_priv->gart_size = init->gart_size; 2018 2019 /* New let's set the memory map ... */ 2020 if (dev_priv->new_memmap) { 2021 u32 base = 0; 2022 2023 DRM_INFO("Setting GART location based on new memory map\n"); 2024 2025 /* If using AGP, try to locate the AGP aperture at the same 2026 * location in the card and on the bus, though we have to 2027 * align it down. 2028 */ 2029#if __OS_HAS_AGP 2030 /* XXX */ 2031 if (dev_priv->flags & RADEON_IS_AGP) { 2032 base = dev->agp->base; 2033 /* Check if valid */ 2034 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && 2035 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { 2036 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n", 2037 dev->agp->base); 2038 base = 0; 2039 } 2040 } 2041#endif 2042 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */ 2043 if (base == 0) { 2044 base = dev_priv->fb_location + dev_priv->fb_size; 2045 if (base < dev_priv->fb_location || 2046 ((base + dev_priv->gart_size) & 0xfffffffful) < base) 2047 base = dev_priv->fb_location 2048 - dev_priv->gart_size; 2049 } 2050 dev_priv->gart_vm_start = base & 0xffc00000u; 2051 if (dev_priv->gart_vm_start != base) 2052 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n", 2053 base, dev_priv->gart_vm_start); 2054 } 2055 2056#if __OS_HAS_AGP 2057 /* XXX */ 2058 if (dev_priv->flags & RADEON_IS_AGP) 2059 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 2060 - dev->agp->base 2061 + dev_priv->gart_vm_start); 2062 else 2063#endif 2064 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 2065 - (unsigned long)dev->sg->virtual 2066 + dev_priv->gart_vm_start); 2067 2068 DRM_DEBUG("fb 0x%08x size %d\n", 2069 (unsigned int) dev_priv->fb_location, 2070 (unsigned int) dev_priv->fb_size); 2071 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); 2072 DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n", 2073 (unsigned int) dev_priv->gart_vm_start); 2074 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n", 2075 dev_priv->gart_buffers_offset); 2076 2077 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; 2078 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle 2079 + init->ring_size / sizeof(u32)); 2080 dev_priv->ring.size = init->ring_size; 2081 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); 2082 2083 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; 2084 dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8); 2085 2086 dev_priv->ring.fetch_size = /* init->fetch_size */ 32; 2087 dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16); 2088 2089 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; 2090 2091 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; 2092 2093#if __OS_HAS_AGP 2094 if (dev_priv->flags & RADEON_IS_AGP) { 2095 /* XXX turn off pcie gart */ 2096 } else 2097#endif 2098 { 2099 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); 2100 /* if we have an offset set from userspace */ 2101 if (!dev_priv->pcigart_offset_set) { 2102 DRM_ERROR("Need gart offset from userspace\n"); 2103 r600_do_cleanup_cp(dev); 2104 return -EINVAL; 2105 } 2106 2107 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset); 2108 2109 dev_priv->gart_info.bus_addr = 2110 dev_priv->pcigart_offset + dev_priv->fb_location; 2111 dev_priv->gart_info.mapping.offset = 2112 dev_priv->pcigart_offset + dev_priv->fb_aper_offset; 2113 dev_priv->gart_info.mapping.size = 2114 dev_priv->gart_info.table_size; 2115 2116 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev); 2117 if (!dev_priv->gart_info.mapping.handle) { 2118 DRM_ERROR("ioremap failed.\n"); 2119 r600_do_cleanup_cp(dev); 2120 return -EINVAL; 2121 } 2122 2123 dev_priv->gart_info.addr = 2124 dev_priv->gart_info.mapping.handle; 2125 2126 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n", 2127 dev_priv->gart_info.addr, 2128 dev_priv->pcigart_offset); 2129 2130 if (!r600_page_table_init(dev)) { 2131 DRM_ERROR("Failed to init GART table\n"); 2132 r600_do_cleanup_cp(dev); 2133 return -EINVAL; 2134 } 2135 2136 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 2137 r700_vm_init(dev); 2138 else 2139 r600_vm_init(dev); 2140 } 2141 2142 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 2143 r700_cp_load_microcode(dev_priv); 2144 else 2145 r600_cp_load_microcode(dev_priv); 2146 2147 r600_cp_init_ring_buffer(dev, dev_priv, file_priv); 2148 2149 dev_priv->last_buf = 0; 2150 2151 r600_do_engine_reset(dev); 2152 r600_test_writeback(dev_priv); 2153 2154 return 0; 2155} 2156 2157int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv) 2158{ 2159 drm_radeon_private_t *dev_priv = dev->dev_private; 2160 2161 DRM_DEBUG("\n"); 2162 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) { 2163 r700_vm_init(dev); 2164 r700_cp_load_microcode(dev_priv); 2165 } else { 2166 r600_vm_init(dev); 2167 r600_cp_load_microcode(dev_priv); 2168 } 2169 r600_cp_init_ring_buffer(dev, dev_priv, file_priv); 2170 r600_do_engine_reset(dev); 2171 2172 return 0; 2173} 2174 2175/* Wait for the CP to go idle. 2176 */ 2177int r600_do_cp_idle(drm_radeon_private_t *dev_priv) 2178{ 2179 RING_LOCALS; 2180 DRM_DEBUG("\n"); 2181 2182 BEGIN_RING(5); 2183 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); 2184 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT); 2185 /* wait for 3D idle clean */ 2186 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); 2187 OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2); 2188 OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN); 2189 2190 ADVANCE_RING(); 2191 COMMIT_RING(); 2192 2193 return r600_do_wait_for_idle(dev_priv); 2194} 2195 2196/* Start the Command Processor. 2197 */ 2198void r600_do_cp_start(drm_radeon_private_t *dev_priv) 2199{ 2200 u32 cp_me; 2201 RING_LOCALS; 2202 DRM_DEBUG("\n"); 2203 2204 BEGIN_RING(7); 2205 OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5)); 2206 OUT_RING(0x00000001); 2207 if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) 2208 OUT_RING(0x00000003); 2209 else 2210 OUT_RING(0x00000000); 2211 OUT_RING((dev_priv->r600_max_hw_contexts - 1)); 2212 OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1)); 2213 OUT_RING(0x00000000); 2214 OUT_RING(0x00000000); 2215 ADVANCE_RING(); 2216 COMMIT_RING(); 2217 2218 /* set the mux and reset the halt bit */ 2219 cp_me = 0xff; 2220 RADEON_WRITE(R600_CP_ME_CNTL, cp_me); 2221 2222 dev_priv->cp_running = 1; 2223 2224} 2225 2226void r600_do_cp_reset(drm_radeon_private_t *dev_priv) 2227{ 2228 u32 cur_read_ptr; 2229 DRM_DEBUG("\n"); 2230 2231 cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR); 2232 RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr); 2233 SET_RING_HEAD(dev_priv, cur_read_ptr); 2234 dev_priv->ring.tail = cur_read_ptr; 2235} 2236 2237void r600_do_cp_stop(drm_radeon_private_t *dev_priv) 2238{ 2239 uint32_t cp_me; 2240 2241 DRM_DEBUG("\n"); 2242 2243 cp_me = 0xff | R600_CP_ME_HALT; 2244 2245 RADEON_WRITE(R600_CP_ME_CNTL, cp_me); 2246 2247 dev_priv->cp_running = 0; 2248} 2249 2250int r600_cp_dispatch_indirect(struct drm_device *dev, 2251 struct drm_buf *buf, int start, int end) 2252{ 2253 drm_radeon_private_t *dev_priv = dev->dev_private; 2254 RING_LOCALS; 2255 2256 if (start != end) { 2257 unsigned long offset = (dev_priv->gart_buffers_offset 2258 + buf->offset + start); 2259 int dwords = (end - start + 3) / sizeof(u32); 2260 2261 DRM_DEBUG("dwords:%d\n", dwords); 2262 DRM_DEBUG("offset 0x%lx\n", offset); 2263 2264 2265 /* Indirect buffer data must be a multiple of 16 dwords. 2266 * pad the data with a Type-2 CP packet. 2267 */ 2268 while (dwords & 0xf) { 2269 u32 *data = (u32 *) 2270 ((char *)dev->agp_buffer_map->handle 2271 + buf->offset + start); 2272 data[dwords++] = RADEON_CP_PACKET2; 2273 } 2274 2275 /* Fire off the indirect buffer */ 2276 BEGIN_RING(4); 2277 OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2)); 2278 OUT_RING((offset & 0xfffffffc)); 2279 OUT_RING((upper_32_bits(offset) & 0xff)); 2280 OUT_RING(dwords); 2281 ADVANCE_RING(); 2282 } 2283 2284 return 0; 2285} 2286