r600_cp.c revision 3ce0a23d2d253185df24e22e3d5f89800bb3dd1c
1/* 2 * Copyright 2008-2009 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Dave Airlie <airlied@redhat.com> 26 * Alex Deucher <alexander.deucher@amd.com> 27 */ 28 29#include "drmP.h" 30#include "drm.h" 31#include "radeon_drm.h" 32#include "radeon_drv.h" 33 34#define PFP_UCODE_SIZE 576 35#define PM4_UCODE_SIZE 1792 36#define R700_PFP_UCODE_SIZE 848 37#define R700_PM4_UCODE_SIZE 1360 38 39/* Firmware Names */ 40MODULE_FIRMWARE("radeon/R600_pfp.bin"); 41MODULE_FIRMWARE("radeon/R600_me.bin"); 42MODULE_FIRMWARE("radeon/RV610_pfp.bin"); 43MODULE_FIRMWARE("radeon/RV610_me.bin"); 44MODULE_FIRMWARE("radeon/RV630_pfp.bin"); 45MODULE_FIRMWARE("radeon/RV630_me.bin"); 46MODULE_FIRMWARE("radeon/RV620_pfp.bin"); 47MODULE_FIRMWARE("radeon/RV620_me.bin"); 48MODULE_FIRMWARE("radeon/RV635_pfp.bin"); 49MODULE_FIRMWARE("radeon/RV635_me.bin"); 50MODULE_FIRMWARE("radeon/RV670_pfp.bin"); 51MODULE_FIRMWARE("radeon/RV670_me.bin"); 52MODULE_FIRMWARE("radeon/RS780_pfp.bin"); 53MODULE_FIRMWARE("radeon/RS780_me.bin"); 54MODULE_FIRMWARE("radeon/RV770_pfp.bin"); 55MODULE_FIRMWARE("radeon/RV770_me.bin"); 56MODULE_FIRMWARE("radeon/RV730_pfp.bin"); 57MODULE_FIRMWARE("radeon/RV730_me.bin"); 58MODULE_FIRMWARE("radeon/RV710_pfp.bin"); 59MODULE_FIRMWARE("radeon/RV710_me.bin"); 60 61 62int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp, 63 unsigned family, u32 *ib, int *l); 64void r600_cs_legacy_init(void); 65 66 67# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ 68# define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1)) 69 70#define R600_PTE_VALID (1 << 0) 71#define R600_PTE_SYSTEM (1 << 1) 72#define R600_PTE_SNOOPED (1 << 2) 73#define R600_PTE_READABLE (1 << 5) 74#define R600_PTE_WRITEABLE (1 << 6) 75 76/* MAX values used for gfx init */ 77#define R6XX_MAX_SH_GPRS 256 78#define R6XX_MAX_TEMP_GPRS 16 79#define R6XX_MAX_SH_THREADS 256 80#define R6XX_MAX_SH_STACK_ENTRIES 4096 81#define R6XX_MAX_BACKENDS 8 82#define R6XX_MAX_BACKENDS_MASK 0xff 83#define R6XX_MAX_SIMDS 8 84#define R6XX_MAX_SIMDS_MASK 0xff 85#define R6XX_MAX_PIPES 8 86#define R6XX_MAX_PIPES_MASK 0xff 87 88#define R7XX_MAX_SH_GPRS 256 89#define R7XX_MAX_TEMP_GPRS 16 90#define R7XX_MAX_SH_THREADS 256 91#define R7XX_MAX_SH_STACK_ENTRIES 4096 92#define R7XX_MAX_BACKENDS 8 93#define R7XX_MAX_BACKENDS_MASK 0xff 94#define R7XX_MAX_SIMDS 16 95#define R7XX_MAX_SIMDS_MASK 0xffff 96#define R7XX_MAX_PIPES 8 97#define R7XX_MAX_PIPES_MASK 0xff 98 99static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries) 100{ 101 int i; 102 103 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 104 105 for (i = 0; i < dev_priv->usec_timeout; i++) { 106 int slots; 107 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 108 slots = (RADEON_READ(R600_GRBM_STATUS) 109 & R700_CMDFIFO_AVAIL_MASK); 110 else 111 slots = (RADEON_READ(R600_GRBM_STATUS) 112 & R600_CMDFIFO_AVAIL_MASK); 113 if (slots >= entries) 114 return 0; 115 DRM_UDELAY(1); 116 } 117 DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n", 118 RADEON_READ(R600_GRBM_STATUS), 119 RADEON_READ(R600_GRBM_STATUS2)); 120 121 return -EBUSY; 122} 123 124static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv) 125{ 126 int i, ret; 127 128 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 129 130 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 131 ret = r600_do_wait_for_fifo(dev_priv, 8); 132 else 133 ret = r600_do_wait_for_fifo(dev_priv, 16); 134 if (ret) 135 return ret; 136 for (i = 0; i < dev_priv->usec_timeout; i++) { 137 if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE)) 138 return 0; 139 DRM_UDELAY(1); 140 } 141 DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n", 142 RADEON_READ(R600_GRBM_STATUS), 143 RADEON_READ(R600_GRBM_STATUS2)); 144 145 return -EBUSY; 146} 147 148void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info) 149{ 150 struct drm_sg_mem *entry = dev->sg; 151 int max_pages; 152 int pages; 153 int i; 154 155 if (!entry) 156 return; 157 158 if (gart_info->bus_addr) { 159 max_pages = (gart_info->table_size / sizeof(u64)); 160 pages = (entry->pages <= max_pages) 161 ? entry->pages : max_pages; 162 163 for (i = 0; i < pages; i++) { 164 if (!entry->busaddr[i]) 165 break; 166 pci_unmap_page(dev->pdev, entry->busaddr[i], 167 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 168 } 169 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) 170 gart_info->bus_addr = 0; 171 } 172} 173 174/* R600 has page table setup */ 175int r600_page_table_init(struct drm_device *dev) 176{ 177 drm_radeon_private_t *dev_priv = dev->dev_private; 178 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info; 179 struct drm_local_map *map = &gart_info->mapping; 180 struct drm_sg_mem *entry = dev->sg; 181 int ret = 0; 182 int i, j; 183 int pages; 184 u64 page_base; 185 dma_addr_t entry_addr; 186 int max_ati_pages, max_real_pages, gart_idx; 187 188 /* okay page table is available - lets rock */ 189 max_ati_pages = (gart_info->table_size / sizeof(u64)); 190 max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); 191 192 pages = (entry->pages <= max_real_pages) ? 193 entry->pages : max_real_pages; 194 195 memset_io((void __iomem *)map->handle, 0, max_ati_pages * sizeof(u64)); 196 197 gart_idx = 0; 198 for (i = 0; i < pages; i++) { 199 entry->busaddr[i] = pci_map_page(dev->pdev, 200 entry->pagelist[i], 0, 201 PAGE_SIZE, 202 PCI_DMA_BIDIRECTIONAL); 203 if (entry->busaddr[i] == 0) { 204 DRM_ERROR("unable to map PCIGART pages!\n"); 205 r600_page_table_cleanup(dev, gart_info); 206 goto done; 207 } 208 entry_addr = entry->busaddr[i]; 209 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) { 210 page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK; 211 page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; 212 page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE; 213 214 DRM_WRITE64(map, gart_idx * sizeof(u64), page_base); 215 216 gart_idx++; 217 218 if ((i % 128) == 0) 219 DRM_DEBUG("page entry %d: 0x%016llx\n", 220 i, (unsigned long long)page_base); 221 entry_addr += ATI_PCIGART_PAGE_SIZE; 222 } 223 } 224 ret = 1; 225done: 226 return ret; 227} 228 229static void r600_vm_flush_gart_range(struct drm_device *dev) 230{ 231 drm_radeon_private_t *dev_priv = dev->dev_private; 232 u32 resp, countdown = 1000; 233 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12); 234 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 235 RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2); 236 237 do { 238 resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE); 239 countdown--; 240 DRM_UDELAY(1); 241 } while (((resp & 0xf0) == 0) && countdown); 242} 243 244static void r600_vm_init(struct drm_device *dev) 245{ 246 drm_radeon_private_t *dev_priv = dev->dev_private; 247 /* initialise the VM to use the page table we constructed up there */ 248 u32 vm_c0, i; 249 u32 mc_rd_a; 250 u32 vm_l2_cntl, vm_l2_cntl3; 251 /* okay set up the PCIE aperture type thingo */ 252 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); 253 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 254 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 255 256 /* setup MC RD a */ 257 mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS | 258 R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) | 259 R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY; 260 261 RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a); 262 RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a); 263 264 RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a); 265 RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a); 266 267 RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a); 268 RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a); 269 270 RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a); 271 RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a); 272 273 RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING); 274 RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/); 275 276 RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a); 277 RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a); 278 279 RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE); 280 RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a); 281 282 vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W; 283 vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7); 284 RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl); 285 286 RADEON_WRITE(R600_VM_L2_CNTL2, 0); 287 vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) | 288 R600_VM_L2_CNTL3_BANK_SELECT_1(1) | 289 R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2)); 290 RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3); 291 292 vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT; 293 294 RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0); 295 296 vm_c0 &= ~R600_VM_ENABLE_CONTEXT; 297 298 /* disable all other contexts */ 299 for (i = 1; i < 8; i++) 300 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0); 301 302 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); 303 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); 304 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 305 306 r600_vm_flush_gart_range(dev); 307} 308 309static int r600_cp_init_microcode(drm_radeon_private_t *dev_priv) 310{ 311 struct platform_device *pdev; 312 const char *chip_name; 313 size_t pfp_req_size, me_req_size; 314 char fw_name[30]; 315 int err; 316 317 pdev = platform_device_register_simple("r600_cp", 0, NULL, 0); 318 err = IS_ERR(pdev); 319 if (err) { 320 printk(KERN_ERR "r600_cp: Failed to register firmware\n"); 321 return -EINVAL; 322 } 323 324 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 325 case CHIP_R600: chip_name = "R600"; break; 326 case CHIP_RV610: chip_name = "RV610"; break; 327 case CHIP_RV630: chip_name = "RV630"; break; 328 case CHIP_RV620: chip_name = "RV620"; break; 329 case CHIP_RV635: chip_name = "RV635"; break; 330 case CHIP_RV670: chip_name = "RV670"; break; 331 case CHIP_RS780: 332 case CHIP_RS880: chip_name = "RS780"; break; 333 case CHIP_RV770: chip_name = "RV770"; break; 334 case CHIP_RV730: 335 case CHIP_RV740: chip_name = "RV730"; break; 336 case CHIP_RV710: chip_name = "RV710"; break; 337 default: BUG(); 338 } 339 340 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) { 341 pfp_req_size = R700_PFP_UCODE_SIZE * 4; 342 me_req_size = R700_PM4_UCODE_SIZE * 4; 343 } else { 344 pfp_req_size = PFP_UCODE_SIZE * 4; 345 me_req_size = PM4_UCODE_SIZE * 12; 346 } 347 348 DRM_INFO("Loading %s CP Microcode\n", chip_name); 349 350 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 351 err = request_firmware(&dev_priv->pfp_fw, fw_name, &pdev->dev); 352 if (err) 353 goto out; 354 if (dev_priv->pfp_fw->size != pfp_req_size) { 355 printk(KERN_ERR 356 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 357 dev_priv->pfp_fw->size, fw_name); 358 err = -EINVAL; 359 goto out; 360 } 361 362 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 363 err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev); 364 if (err) 365 goto out; 366 if (dev_priv->me_fw->size != me_req_size) { 367 printk(KERN_ERR 368 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 369 dev_priv->me_fw->size, fw_name); 370 err = -EINVAL; 371 } 372out: 373 platform_device_unregister(pdev); 374 375 if (err) { 376 if (err != -EINVAL) 377 printk(KERN_ERR 378 "r600_cp: Failed to load firmware \"%s\"\n", 379 fw_name); 380 release_firmware(dev_priv->pfp_fw); 381 dev_priv->pfp_fw = NULL; 382 release_firmware(dev_priv->me_fw); 383 dev_priv->me_fw = NULL; 384 } 385 return err; 386} 387 388static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv) 389{ 390 const __be32 *fw_data; 391 int i; 392 393 if (!dev_priv->me_fw || !dev_priv->pfp_fw) 394 return; 395 396 r600_do_cp_stop(dev_priv); 397 398 RADEON_WRITE(R600_CP_RB_CNTL, 399 R600_RB_NO_UPDATE | 400 R600_RB_BLKSZ(15) | 401 R600_RB_BUFSZ(3)); 402 403 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 404 RADEON_READ(R600_GRBM_SOFT_RESET); 405 DRM_UDELAY(15000); 406 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 407 408 fw_data = (const __be32 *)dev_priv->me_fw->data; 409 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 410 for (i = 0; i < PM4_UCODE_SIZE * 3; i++) 411 RADEON_WRITE(R600_CP_ME_RAM_DATA, 412 be32_to_cpup(fw_data++)); 413 414 fw_data = (const __be32 *)dev_priv->pfp_fw->data; 415 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 416 for (i = 0; i < PFP_UCODE_SIZE; i++) 417 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, 418 be32_to_cpup(fw_data++)); 419 420 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 421 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 422 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); 423 424} 425 426static void r700_vm_init(struct drm_device *dev) 427{ 428 drm_radeon_private_t *dev_priv = dev->dev_private; 429 /* initialise the VM to use the page table we constructed up there */ 430 u32 vm_c0, i; 431 u32 mc_vm_md_l1; 432 u32 vm_l2_cntl, vm_l2_cntl3; 433 /* okay set up the PCIE aperture type thingo */ 434 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); 435 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 436 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 437 438 mc_vm_md_l1 = R700_ENABLE_L1_TLB | 439 R700_ENABLE_L1_FRAGMENT_PROCESSING | 440 R700_SYSTEM_ACCESS_MODE_IN_SYS | 441 R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 442 R700_EFFECTIVE_L1_TLB_SIZE(5) | 443 R700_EFFECTIVE_L1_QUEUE_SIZE(5); 444 445 RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1); 446 RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1); 447 RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1); 448 RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1); 449 RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1); 450 RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1); 451 RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1); 452 453 vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W; 454 vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7); 455 RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl); 456 457 RADEON_WRITE(R600_VM_L2_CNTL2, 0); 458 vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2); 459 RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3); 460 461 vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT; 462 463 RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0); 464 465 vm_c0 &= ~R600_VM_ENABLE_CONTEXT; 466 467 /* disable all other contexts */ 468 for (i = 1; i < 8; i++) 469 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0); 470 471 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); 472 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); 473 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 474 475 r600_vm_flush_gart_range(dev); 476} 477 478static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv) 479{ 480 const __be32 *fw_data; 481 int i; 482 483 if (!dev_priv->me_fw || !dev_priv->pfp_fw) 484 return; 485 486 r600_do_cp_stop(dev_priv); 487 488 RADEON_WRITE(R600_CP_RB_CNTL, 489 R600_RB_NO_UPDATE | 490 (15 << 8) | 491 (3 << 0)); 492 493 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 494 RADEON_READ(R600_GRBM_SOFT_RESET); 495 DRM_UDELAY(15000); 496 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 497 498 fw_data = (const __be32 *)dev_priv->pfp_fw->data; 499 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 500 for (i = 0; i < R700_PFP_UCODE_SIZE; i++) 501 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 502 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 503 504 fw_data = (const __be32 *)dev_priv->me_fw->data; 505 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 506 for (i = 0; i < R700_PM4_UCODE_SIZE; i++) 507 RADEON_WRITE(R600_CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 508 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 509 510 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 511 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 512 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); 513 514} 515 516static void r600_test_writeback(drm_radeon_private_t *dev_priv) 517{ 518 u32 tmp; 519 520 /* Start with assuming that writeback doesn't work */ 521 dev_priv->writeback_works = 0; 522 523 /* Writeback doesn't seem to work everywhere, test it here and possibly 524 * enable it if it appears to work 525 */ 526 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0); 527 528 RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef); 529 530 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { 531 u32 val; 532 533 val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1)); 534 if (val == 0xdeadbeef) 535 break; 536 DRM_UDELAY(1); 537 } 538 539 if (tmp < dev_priv->usec_timeout) { 540 dev_priv->writeback_works = 1; 541 DRM_INFO("writeback test succeeded in %d usecs\n", tmp); 542 } else { 543 dev_priv->writeback_works = 0; 544 DRM_INFO("writeback test failed\n"); 545 } 546 if (radeon_no_wb == 1) { 547 dev_priv->writeback_works = 0; 548 DRM_INFO("writeback forced off\n"); 549 } 550 551 if (!dev_priv->writeback_works) { 552 /* Disable writeback to avoid unnecessary bus master transfer */ 553 RADEON_WRITE(R600_CP_RB_CNTL, RADEON_READ(R600_CP_RB_CNTL) | 554 RADEON_RB_NO_UPDATE); 555 RADEON_WRITE(R600_SCRATCH_UMSK, 0); 556 } 557} 558 559int r600_do_engine_reset(struct drm_device *dev) 560{ 561 drm_radeon_private_t *dev_priv = dev->dev_private; 562 u32 cp_ptr, cp_me_cntl, cp_rb_cntl; 563 564 DRM_INFO("Resetting GPU\n"); 565 566 cp_ptr = RADEON_READ(R600_CP_RB_WPTR); 567 cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL); 568 RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT); 569 570 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff); 571 RADEON_READ(R600_GRBM_SOFT_RESET); 572 DRM_UDELAY(50); 573 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 574 RADEON_READ(R600_GRBM_SOFT_RESET); 575 576 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); 577 cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL); 578 RADEON_WRITE(R600_CP_RB_CNTL, R600_RB_RPTR_WR_ENA); 579 580 RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr); 581 RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr); 582 RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl); 583 RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl); 584 585 /* Reset the CP ring */ 586 r600_do_cp_reset(dev_priv); 587 588 /* The CP is no longer running after an engine reset */ 589 dev_priv->cp_running = 0; 590 591 /* Reset any pending vertex, indirect buffers */ 592 radeon_freelist_reset(dev); 593 594 return 0; 595 596} 597 598static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes, 599 u32 num_backends, 600 u32 backend_disable_mask) 601{ 602 u32 backend_map = 0; 603 u32 enabled_backends_mask; 604 u32 enabled_backends_count; 605 u32 cur_pipe; 606 u32 swizzle_pipe[R6XX_MAX_PIPES]; 607 u32 cur_backend; 608 u32 i; 609 610 if (num_tile_pipes > R6XX_MAX_PIPES) 611 num_tile_pipes = R6XX_MAX_PIPES; 612 if (num_tile_pipes < 1) 613 num_tile_pipes = 1; 614 if (num_backends > R6XX_MAX_BACKENDS) 615 num_backends = R6XX_MAX_BACKENDS; 616 if (num_backends < 1) 617 num_backends = 1; 618 619 enabled_backends_mask = 0; 620 enabled_backends_count = 0; 621 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) { 622 if (((backend_disable_mask >> i) & 1) == 0) { 623 enabled_backends_mask |= (1 << i); 624 ++enabled_backends_count; 625 } 626 if (enabled_backends_count == num_backends) 627 break; 628 } 629 630 if (enabled_backends_count == 0) { 631 enabled_backends_mask = 1; 632 enabled_backends_count = 1; 633 } 634 635 if (enabled_backends_count != num_backends) 636 num_backends = enabled_backends_count; 637 638 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES); 639 switch (num_tile_pipes) { 640 case 1: 641 swizzle_pipe[0] = 0; 642 break; 643 case 2: 644 swizzle_pipe[0] = 0; 645 swizzle_pipe[1] = 1; 646 break; 647 case 3: 648 swizzle_pipe[0] = 0; 649 swizzle_pipe[1] = 1; 650 swizzle_pipe[2] = 2; 651 break; 652 case 4: 653 swizzle_pipe[0] = 0; 654 swizzle_pipe[1] = 1; 655 swizzle_pipe[2] = 2; 656 swizzle_pipe[3] = 3; 657 break; 658 case 5: 659 swizzle_pipe[0] = 0; 660 swizzle_pipe[1] = 1; 661 swizzle_pipe[2] = 2; 662 swizzle_pipe[3] = 3; 663 swizzle_pipe[4] = 4; 664 break; 665 case 6: 666 swizzle_pipe[0] = 0; 667 swizzle_pipe[1] = 2; 668 swizzle_pipe[2] = 4; 669 swizzle_pipe[3] = 5; 670 swizzle_pipe[4] = 1; 671 swizzle_pipe[5] = 3; 672 break; 673 case 7: 674 swizzle_pipe[0] = 0; 675 swizzle_pipe[1] = 2; 676 swizzle_pipe[2] = 4; 677 swizzle_pipe[3] = 6; 678 swizzle_pipe[4] = 1; 679 swizzle_pipe[5] = 3; 680 swizzle_pipe[6] = 5; 681 break; 682 case 8: 683 swizzle_pipe[0] = 0; 684 swizzle_pipe[1] = 2; 685 swizzle_pipe[2] = 4; 686 swizzle_pipe[3] = 6; 687 swizzle_pipe[4] = 1; 688 swizzle_pipe[5] = 3; 689 swizzle_pipe[6] = 5; 690 swizzle_pipe[7] = 7; 691 break; 692 } 693 694 cur_backend = 0; 695 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 696 while (((1 << cur_backend) & enabled_backends_mask) == 0) 697 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; 698 699 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 700 701 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; 702 } 703 704 return backend_map; 705} 706 707static int r600_count_pipe_bits(uint32_t val) 708{ 709 int i, ret = 0; 710 for (i = 0; i < 32; i++) { 711 ret += val & 1; 712 val >>= 1; 713 } 714 return ret; 715} 716 717static void r600_gfx_init(struct drm_device *dev, 718 drm_radeon_private_t *dev_priv) 719{ 720 int i, j, num_qd_pipes; 721 u32 sx_debug_1; 722 u32 tc_cntl; 723 u32 arb_pop; 724 u32 num_gs_verts_per_thread; 725 u32 vgt_gs_per_es; 726 u32 gs_prim_buffer_depth = 0; 727 u32 sq_ms_fifo_sizes; 728 u32 sq_config; 729 u32 sq_gpr_resource_mgmt_1 = 0; 730 u32 sq_gpr_resource_mgmt_2 = 0; 731 u32 sq_thread_resource_mgmt = 0; 732 u32 sq_stack_resource_mgmt_1 = 0; 733 u32 sq_stack_resource_mgmt_2 = 0; 734 u32 hdp_host_path_cntl; 735 u32 backend_map; 736 u32 gb_tiling_config = 0; 737 u32 cc_rb_backend_disable = 0; 738 u32 cc_gc_shader_pipe_config = 0; 739 u32 ramcfg; 740 741 /* setup chip specs */ 742 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 743 case CHIP_R600: 744 dev_priv->r600_max_pipes = 4; 745 dev_priv->r600_max_tile_pipes = 8; 746 dev_priv->r600_max_simds = 4; 747 dev_priv->r600_max_backends = 4; 748 dev_priv->r600_max_gprs = 256; 749 dev_priv->r600_max_threads = 192; 750 dev_priv->r600_max_stack_entries = 256; 751 dev_priv->r600_max_hw_contexts = 8; 752 dev_priv->r600_max_gs_threads = 16; 753 dev_priv->r600_sx_max_export_size = 128; 754 dev_priv->r600_sx_max_export_pos_size = 16; 755 dev_priv->r600_sx_max_export_smx_size = 128; 756 dev_priv->r600_sq_num_cf_insts = 2; 757 break; 758 case CHIP_RV630: 759 case CHIP_RV635: 760 dev_priv->r600_max_pipes = 2; 761 dev_priv->r600_max_tile_pipes = 2; 762 dev_priv->r600_max_simds = 3; 763 dev_priv->r600_max_backends = 1; 764 dev_priv->r600_max_gprs = 128; 765 dev_priv->r600_max_threads = 192; 766 dev_priv->r600_max_stack_entries = 128; 767 dev_priv->r600_max_hw_contexts = 8; 768 dev_priv->r600_max_gs_threads = 4; 769 dev_priv->r600_sx_max_export_size = 128; 770 dev_priv->r600_sx_max_export_pos_size = 16; 771 dev_priv->r600_sx_max_export_smx_size = 128; 772 dev_priv->r600_sq_num_cf_insts = 2; 773 break; 774 case CHIP_RV610: 775 case CHIP_RS780: 776 case CHIP_RS880: 777 case CHIP_RV620: 778 dev_priv->r600_max_pipes = 1; 779 dev_priv->r600_max_tile_pipes = 1; 780 dev_priv->r600_max_simds = 2; 781 dev_priv->r600_max_backends = 1; 782 dev_priv->r600_max_gprs = 128; 783 dev_priv->r600_max_threads = 192; 784 dev_priv->r600_max_stack_entries = 128; 785 dev_priv->r600_max_hw_contexts = 4; 786 dev_priv->r600_max_gs_threads = 4; 787 dev_priv->r600_sx_max_export_size = 128; 788 dev_priv->r600_sx_max_export_pos_size = 16; 789 dev_priv->r600_sx_max_export_smx_size = 128; 790 dev_priv->r600_sq_num_cf_insts = 1; 791 break; 792 case CHIP_RV670: 793 dev_priv->r600_max_pipes = 4; 794 dev_priv->r600_max_tile_pipes = 4; 795 dev_priv->r600_max_simds = 4; 796 dev_priv->r600_max_backends = 4; 797 dev_priv->r600_max_gprs = 192; 798 dev_priv->r600_max_threads = 192; 799 dev_priv->r600_max_stack_entries = 256; 800 dev_priv->r600_max_hw_contexts = 8; 801 dev_priv->r600_max_gs_threads = 16; 802 dev_priv->r600_sx_max_export_size = 128; 803 dev_priv->r600_sx_max_export_pos_size = 16; 804 dev_priv->r600_sx_max_export_smx_size = 128; 805 dev_priv->r600_sq_num_cf_insts = 2; 806 break; 807 default: 808 break; 809 } 810 811 /* Initialize HDP */ 812 j = 0; 813 for (i = 0; i < 32; i++) { 814 RADEON_WRITE((0x2c14 + j), 0x00000000); 815 RADEON_WRITE((0x2c18 + j), 0x00000000); 816 RADEON_WRITE((0x2c1c + j), 0x00000000); 817 RADEON_WRITE((0x2c20 + j), 0x00000000); 818 RADEON_WRITE((0x2c24 + j), 0x00000000); 819 j += 0x18; 820 } 821 822 RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff)); 823 824 /* setup tiling, simd, pipe config */ 825 ramcfg = RADEON_READ(R600_RAMCFG); 826 827 switch (dev_priv->r600_max_tile_pipes) { 828 case 1: 829 gb_tiling_config |= R600_PIPE_TILING(0); 830 break; 831 case 2: 832 gb_tiling_config |= R600_PIPE_TILING(1); 833 break; 834 case 4: 835 gb_tiling_config |= R600_PIPE_TILING(2); 836 break; 837 case 8: 838 gb_tiling_config |= R600_PIPE_TILING(3); 839 break; 840 default: 841 break; 842 } 843 844 gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK); 845 846 gb_tiling_config |= R600_GROUP_SIZE(0); 847 848 if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) { 849 gb_tiling_config |= R600_ROW_TILING(3); 850 gb_tiling_config |= R600_SAMPLE_SPLIT(3); 851 } else { 852 gb_tiling_config |= 853 R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK)); 854 gb_tiling_config |= 855 R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK)); 856 } 857 858 gb_tiling_config |= R600_BANK_SWAPS(1); 859 860 backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes, 861 dev_priv->r600_max_backends, 862 (0xff << dev_priv->r600_max_backends) & 0xff); 863 gb_tiling_config |= R600_BACKEND_MAP(backend_map); 864 865 cc_gc_shader_pipe_config = 866 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK); 867 cc_gc_shader_pipe_config |= 868 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK); 869 870 cc_rb_backend_disable = 871 R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK); 872 873 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); 874 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 875 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 876 877 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 878 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 879 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 880 881 num_qd_pipes = 882 R6XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK); 883 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK); 884 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK); 885 886 /* set HW defaults for 3D engine */ 887 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) | 888 R600_ROQ_IB2_START(0x2b))); 889 890 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) | 891 R600_ROQ_END(0x40))); 892 893 RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO | 894 R600_SYNC_GRADIENT | 895 R600_SYNC_WALKER | 896 R600_SYNC_ALIGNER)); 897 898 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) 899 RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021); 900 901 sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1); 902 sx_debug_1 |= R600_SMX_EVENT_RELEASE; 903 if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600)) 904 sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS; 905 RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1); 906 907 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || 908 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || 909 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 910 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 911 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || 912 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) 913 RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE); 914 else 915 RADEON_WRITE(R600_DB_DEBUG, 0); 916 917 RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) | 918 R600_DEPTH_FLUSH(16) | 919 R600_DEPTH_PENDING_FREE(4) | 920 R600_DEPTH_CACHELINE_FREE(16))); 921 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 922 RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0); 923 924 RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0)); 925 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0)); 926 927 sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES); 928 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 929 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 930 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || 931 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) { 932 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) | 933 R600_FETCH_FIFO_HIWATER(0xa) | 934 R600_DONE_FIFO_HIWATER(0xe0) | 935 R600_ALU_UPDATE_FIFO_HIWATER(0x8)); 936 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || 937 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) { 938 sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff); 939 sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4); 940 } 941 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 942 943 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 944 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 945 */ 946 sq_config = RADEON_READ(R600_SQ_CONFIG); 947 sq_config &= ~(R600_PS_PRIO(3) | 948 R600_VS_PRIO(3) | 949 R600_GS_PRIO(3) | 950 R600_ES_PRIO(3)); 951 sq_config |= (R600_DX9_CONSTS | 952 R600_VC_ENABLE | 953 R600_PS_PRIO(0) | 954 R600_VS_PRIO(1) | 955 R600_GS_PRIO(2) | 956 R600_ES_PRIO(3)); 957 958 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) { 959 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) | 960 R600_NUM_VS_GPRS(124) | 961 R600_NUM_CLAUSE_TEMP_GPRS(4)); 962 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) | 963 R600_NUM_ES_GPRS(0)); 964 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) | 965 R600_NUM_VS_THREADS(48) | 966 R600_NUM_GS_THREADS(4) | 967 R600_NUM_ES_THREADS(4)); 968 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) | 969 R600_NUM_VS_STACK_ENTRIES(128)); 970 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) | 971 R600_NUM_ES_STACK_ENTRIES(0)); 972 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 973 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 974 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || 975 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) { 976 /* no vertex cache */ 977 sq_config &= ~R600_VC_ENABLE; 978 979 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 980 R600_NUM_VS_GPRS(44) | 981 R600_NUM_CLAUSE_TEMP_GPRS(2)); 982 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) | 983 R600_NUM_ES_GPRS(17)); 984 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 985 R600_NUM_VS_THREADS(78) | 986 R600_NUM_GS_THREADS(4) | 987 R600_NUM_ES_THREADS(31)); 988 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) | 989 R600_NUM_VS_STACK_ENTRIES(40)); 990 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) | 991 R600_NUM_ES_STACK_ENTRIES(16)); 992 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || 993 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) { 994 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 995 R600_NUM_VS_GPRS(44) | 996 R600_NUM_CLAUSE_TEMP_GPRS(2)); 997 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) | 998 R600_NUM_ES_GPRS(18)); 999 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 1000 R600_NUM_VS_THREADS(78) | 1001 R600_NUM_GS_THREADS(4) | 1002 R600_NUM_ES_THREADS(31)); 1003 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) | 1004 R600_NUM_VS_STACK_ENTRIES(40)); 1005 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) | 1006 R600_NUM_ES_STACK_ENTRIES(16)); 1007 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) { 1008 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 1009 R600_NUM_VS_GPRS(44) | 1010 R600_NUM_CLAUSE_TEMP_GPRS(2)); 1011 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) | 1012 R600_NUM_ES_GPRS(17)); 1013 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 1014 R600_NUM_VS_THREADS(78) | 1015 R600_NUM_GS_THREADS(4) | 1016 R600_NUM_ES_THREADS(31)); 1017 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) | 1018 R600_NUM_VS_STACK_ENTRIES(64)); 1019 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) | 1020 R600_NUM_ES_STACK_ENTRIES(64)); 1021 } 1022 1023 RADEON_WRITE(R600_SQ_CONFIG, sq_config); 1024 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 1025 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 1026 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1027 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 1028 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 1029 1030 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 1031 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 1032 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || 1033 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) 1034 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY)); 1035 else 1036 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC)); 1037 1038 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) | 1039 R600_S0_Y(0x4) | 1040 R600_S1_X(0x4) | 1041 R600_S1_Y(0xc))); 1042 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) | 1043 R600_S0_Y(0xe) | 1044 R600_S1_X(0x2) | 1045 R600_S1_Y(0x2) | 1046 R600_S2_X(0xa) | 1047 R600_S2_Y(0x6) | 1048 R600_S3_X(0x6) | 1049 R600_S3_Y(0xa))); 1050 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) | 1051 R600_S0_Y(0xb) | 1052 R600_S1_X(0x4) | 1053 R600_S1_Y(0xc) | 1054 R600_S2_X(0x1) | 1055 R600_S2_Y(0x6) | 1056 R600_S3_X(0xa) | 1057 R600_S3_Y(0xe))); 1058 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) | 1059 R600_S4_Y(0x1) | 1060 R600_S5_X(0x0) | 1061 R600_S5_Y(0x0) | 1062 R600_S6_X(0xb) | 1063 R600_S6_Y(0x4) | 1064 R600_S7_X(0x7) | 1065 R600_S7_Y(0x8))); 1066 1067 1068 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1069 case CHIP_R600: 1070 case CHIP_RV630: 1071 case CHIP_RV635: 1072 gs_prim_buffer_depth = 0; 1073 break; 1074 case CHIP_RV610: 1075 case CHIP_RS780: 1076 case CHIP_RS880: 1077 case CHIP_RV620: 1078 gs_prim_buffer_depth = 32; 1079 break; 1080 case CHIP_RV670: 1081 gs_prim_buffer_depth = 128; 1082 break; 1083 default: 1084 break; 1085 } 1086 1087 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; 1088 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 1089 /* Max value for this is 256 */ 1090 if (vgt_gs_per_es > 256) 1091 vgt_gs_per_es = 256; 1092 1093 RADEON_WRITE(R600_VGT_ES_PER_GS, 128); 1094 RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es); 1095 RADEON_WRITE(R600_VGT_GS_PER_VS, 2); 1096 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16); 1097 1098 /* more default values. 2D/3D driver should adjust as needed */ 1099 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0); 1100 RADEON_WRITE(R600_VGT_STRMOUT_EN, 0); 1101 RADEON_WRITE(R600_SX_MISC, 0); 1102 RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0); 1103 RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0); 1104 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0); 1105 RADEON_WRITE(R600_SPI_INPUT_Z, 0); 1106 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2)); 1107 RADEON_WRITE(R600_CB_COLOR7_FRAG, 0); 1108 1109 /* clear render buffer base addresses */ 1110 RADEON_WRITE(R600_CB_COLOR0_BASE, 0); 1111 RADEON_WRITE(R600_CB_COLOR1_BASE, 0); 1112 RADEON_WRITE(R600_CB_COLOR2_BASE, 0); 1113 RADEON_WRITE(R600_CB_COLOR3_BASE, 0); 1114 RADEON_WRITE(R600_CB_COLOR4_BASE, 0); 1115 RADEON_WRITE(R600_CB_COLOR5_BASE, 0); 1116 RADEON_WRITE(R600_CB_COLOR6_BASE, 0); 1117 RADEON_WRITE(R600_CB_COLOR7_BASE, 0); 1118 1119 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1120 case CHIP_RV610: 1121 case CHIP_RS780: 1122 case CHIP_RS880: 1123 case CHIP_RV620: 1124 tc_cntl = R600_TC_L2_SIZE(8); 1125 break; 1126 case CHIP_RV630: 1127 case CHIP_RV635: 1128 tc_cntl = R600_TC_L2_SIZE(4); 1129 break; 1130 case CHIP_R600: 1131 tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT; 1132 break; 1133 default: 1134 tc_cntl = R600_TC_L2_SIZE(0); 1135 break; 1136 } 1137 1138 RADEON_WRITE(R600_TC_CNTL, tc_cntl); 1139 1140 hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL); 1141 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1142 1143 arb_pop = RADEON_READ(R600_ARB_POP); 1144 arb_pop |= R600_ENABLE_TC128; 1145 RADEON_WRITE(R600_ARB_POP, arb_pop); 1146 1147 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1148 RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA | 1149 R600_NUM_CLIP_SEQ(3))); 1150 RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095)); 1151 1152} 1153 1154static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes, 1155 u32 num_backends, 1156 u32 backend_disable_mask) 1157{ 1158 u32 backend_map = 0; 1159 u32 enabled_backends_mask; 1160 u32 enabled_backends_count; 1161 u32 cur_pipe; 1162 u32 swizzle_pipe[R7XX_MAX_PIPES]; 1163 u32 cur_backend; 1164 u32 i; 1165 1166 if (num_tile_pipes > R7XX_MAX_PIPES) 1167 num_tile_pipes = R7XX_MAX_PIPES; 1168 if (num_tile_pipes < 1) 1169 num_tile_pipes = 1; 1170 if (num_backends > R7XX_MAX_BACKENDS) 1171 num_backends = R7XX_MAX_BACKENDS; 1172 if (num_backends < 1) 1173 num_backends = 1; 1174 1175 enabled_backends_mask = 0; 1176 enabled_backends_count = 0; 1177 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) { 1178 if (((backend_disable_mask >> i) & 1) == 0) { 1179 enabled_backends_mask |= (1 << i); 1180 ++enabled_backends_count; 1181 } 1182 if (enabled_backends_count == num_backends) 1183 break; 1184 } 1185 1186 if (enabled_backends_count == 0) { 1187 enabled_backends_mask = 1; 1188 enabled_backends_count = 1; 1189 } 1190 1191 if (enabled_backends_count != num_backends) 1192 num_backends = enabled_backends_count; 1193 1194 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES); 1195 switch (num_tile_pipes) { 1196 case 1: 1197 swizzle_pipe[0] = 0; 1198 break; 1199 case 2: 1200 swizzle_pipe[0] = 0; 1201 swizzle_pipe[1] = 1; 1202 break; 1203 case 3: 1204 swizzle_pipe[0] = 0; 1205 swizzle_pipe[1] = 2; 1206 swizzle_pipe[2] = 1; 1207 break; 1208 case 4: 1209 swizzle_pipe[0] = 0; 1210 swizzle_pipe[1] = 2; 1211 swizzle_pipe[2] = 3; 1212 swizzle_pipe[3] = 1; 1213 break; 1214 case 5: 1215 swizzle_pipe[0] = 0; 1216 swizzle_pipe[1] = 2; 1217 swizzle_pipe[2] = 4; 1218 swizzle_pipe[3] = 1; 1219 swizzle_pipe[4] = 3; 1220 break; 1221 case 6: 1222 swizzle_pipe[0] = 0; 1223 swizzle_pipe[1] = 2; 1224 swizzle_pipe[2] = 4; 1225 swizzle_pipe[3] = 5; 1226 swizzle_pipe[4] = 3; 1227 swizzle_pipe[5] = 1; 1228 break; 1229 case 7: 1230 swizzle_pipe[0] = 0; 1231 swizzle_pipe[1] = 2; 1232 swizzle_pipe[2] = 4; 1233 swizzle_pipe[3] = 6; 1234 swizzle_pipe[4] = 3; 1235 swizzle_pipe[5] = 1; 1236 swizzle_pipe[6] = 5; 1237 break; 1238 case 8: 1239 swizzle_pipe[0] = 0; 1240 swizzle_pipe[1] = 2; 1241 swizzle_pipe[2] = 4; 1242 swizzle_pipe[3] = 6; 1243 swizzle_pipe[4] = 3; 1244 swizzle_pipe[5] = 1; 1245 swizzle_pipe[6] = 7; 1246 swizzle_pipe[7] = 5; 1247 break; 1248 } 1249 1250 cur_backend = 0; 1251 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 1252 while (((1 << cur_backend) & enabled_backends_mask) == 0) 1253 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 1254 1255 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 1256 1257 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 1258 } 1259 1260 return backend_map; 1261} 1262 1263static void r700_gfx_init(struct drm_device *dev, 1264 drm_radeon_private_t *dev_priv) 1265{ 1266 int i, j, num_qd_pipes; 1267 u32 sx_debug_1; 1268 u32 smx_dc_ctl0; 1269 u32 num_gs_verts_per_thread; 1270 u32 vgt_gs_per_es; 1271 u32 gs_prim_buffer_depth = 0; 1272 u32 sq_ms_fifo_sizes; 1273 u32 sq_config; 1274 u32 sq_thread_resource_mgmt; 1275 u32 hdp_host_path_cntl; 1276 u32 sq_dyn_gpr_size_simd_ab_0; 1277 u32 backend_map; 1278 u32 gb_tiling_config = 0; 1279 u32 cc_rb_backend_disable = 0; 1280 u32 cc_gc_shader_pipe_config = 0; 1281 u32 mc_arb_ramcfg; 1282 u32 db_debug4; 1283 1284 /* setup chip specs */ 1285 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1286 case CHIP_RV770: 1287 dev_priv->r600_max_pipes = 4; 1288 dev_priv->r600_max_tile_pipes = 8; 1289 dev_priv->r600_max_simds = 10; 1290 dev_priv->r600_max_backends = 4; 1291 dev_priv->r600_max_gprs = 256; 1292 dev_priv->r600_max_threads = 248; 1293 dev_priv->r600_max_stack_entries = 512; 1294 dev_priv->r600_max_hw_contexts = 8; 1295 dev_priv->r600_max_gs_threads = 16 * 2; 1296 dev_priv->r600_sx_max_export_size = 128; 1297 dev_priv->r600_sx_max_export_pos_size = 16; 1298 dev_priv->r600_sx_max_export_smx_size = 112; 1299 dev_priv->r600_sq_num_cf_insts = 2; 1300 1301 dev_priv->r700_sx_num_of_sets = 7; 1302 dev_priv->r700_sc_prim_fifo_size = 0xF9; 1303 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1304 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1305 break; 1306 case CHIP_RV730: 1307 dev_priv->r600_max_pipes = 2; 1308 dev_priv->r600_max_tile_pipes = 4; 1309 dev_priv->r600_max_simds = 8; 1310 dev_priv->r600_max_backends = 2; 1311 dev_priv->r600_max_gprs = 128; 1312 dev_priv->r600_max_threads = 248; 1313 dev_priv->r600_max_stack_entries = 256; 1314 dev_priv->r600_max_hw_contexts = 8; 1315 dev_priv->r600_max_gs_threads = 16 * 2; 1316 dev_priv->r600_sx_max_export_size = 256; 1317 dev_priv->r600_sx_max_export_pos_size = 32; 1318 dev_priv->r600_sx_max_export_smx_size = 224; 1319 dev_priv->r600_sq_num_cf_insts = 2; 1320 1321 dev_priv->r700_sx_num_of_sets = 7; 1322 dev_priv->r700_sc_prim_fifo_size = 0xf9; 1323 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1324 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1325 if (dev_priv->r600_sx_max_export_pos_size > 16) { 1326 dev_priv->r600_sx_max_export_pos_size -= 16; 1327 dev_priv->r600_sx_max_export_smx_size += 16; 1328 } 1329 break; 1330 case CHIP_RV710: 1331 dev_priv->r600_max_pipes = 2; 1332 dev_priv->r600_max_tile_pipes = 2; 1333 dev_priv->r600_max_simds = 2; 1334 dev_priv->r600_max_backends = 1; 1335 dev_priv->r600_max_gprs = 256; 1336 dev_priv->r600_max_threads = 192; 1337 dev_priv->r600_max_stack_entries = 256; 1338 dev_priv->r600_max_hw_contexts = 4; 1339 dev_priv->r600_max_gs_threads = 8 * 2; 1340 dev_priv->r600_sx_max_export_size = 128; 1341 dev_priv->r600_sx_max_export_pos_size = 16; 1342 dev_priv->r600_sx_max_export_smx_size = 112; 1343 dev_priv->r600_sq_num_cf_insts = 1; 1344 1345 dev_priv->r700_sx_num_of_sets = 7; 1346 dev_priv->r700_sc_prim_fifo_size = 0x40; 1347 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1348 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1349 break; 1350 case CHIP_RV740: 1351 dev_priv->r600_max_pipes = 4; 1352 dev_priv->r600_max_tile_pipes = 4; 1353 dev_priv->r600_max_simds = 8; 1354 dev_priv->r600_max_backends = 4; 1355 dev_priv->r600_max_gprs = 256; 1356 dev_priv->r600_max_threads = 248; 1357 dev_priv->r600_max_stack_entries = 512; 1358 dev_priv->r600_max_hw_contexts = 8; 1359 dev_priv->r600_max_gs_threads = 16 * 2; 1360 dev_priv->r600_sx_max_export_size = 256; 1361 dev_priv->r600_sx_max_export_pos_size = 32; 1362 dev_priv->r600_sx_max_export_smx_size = 224; 1363 dev_priv->r600_sq_num_cf_insts = 2; 1364 1365 dev_priv->r700_sx_num_of_sets = 7; 1366 dev_priv->r700_sc_prim_fifo_size = 0x100; 1367 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1368 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1369 1370 if (dev_priv->r600_sx_max_export_pos_size > 16) { 1371 dev_priv->r600_sx_max_export_pos_size -= 16; 1372 dev_priv->r600_sx_max_export_smx_size += 16; 1373 } 1374 break; 1375 default: 1376 break; 1377 } 1378 1379 /* Initialize HDP */ 1380 j = 0; 1381 for (i = 0; i < 32; i++) { 1382 RADEON_WRITE((0x2c14 + j), 0x00000000); 1383 RADEON_WRITE((0x2c18 + j), 0x00000000); 1384 RADEON_WRITE((0x2c1c + j), 0x00000000); 1385 RADEON_WRITE((0x2c20 + j), 0x00000000); 1386 RADEON_WRITE((0x2c24 + j), 0x00000000); 1387 j += 0x18; 1388 } 1389 1390 RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff)); 1391 1392 /* setup tiling, simd, pipe config */ 1393 mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG); 1394 1395 switch (dev_priv->r600_max_tile_pipes) { 1396 case 1: 1397 gb_tiling_config |= R600_PIPE_TILING(0); 1398 break; 1399 case 2: 1400 gb_tiling_config |= R600_PIPE_TILING(1); 1401 break; 1402 case 4: 1403 gb_tiling_config |= R600_PIPE_TILING(2); 1404 break; 1405 case 8: 1406 gb_tiling_config |= R600_PIPE_TILING(3); 1407 break; 1408 default: 1409 break; 1410 } 1411 1412 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770) 1413 gb_tiling_config |= R600_BANK_TILING(1); 1414 else 1415 gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK); 1416 1417 gb_tiling_config |= R600_GROUP_SIZE(0); 1418 1419 if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) { 1420 gb_tiling_config |= R600_ROW_TILING(3); 1421 gb_tiling_config |= R600_SAMPLE_SPLIT(3); 1422 } else { 1423 gb_tiling_config |= 1424 R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK)); 1425 gb_tiling_config |= 1426 R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK)); 1427 } 1428 1429 gb_tiling_config |= R600_BANK_SWAPS(1); 1430 1431 backend_map = r700_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes, 1432 dev_priv->r600_max_backends, 1433 (0xff << dev_priv->r600_max_backends) & 0xff); 1434 gb_tiling_config |= R600_BACKEND_MAP(backend_map); 1435 1436 cc_gc_shader_pipe_config = 1437 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK); 1438 cc_gc_shader_pipe_config |= 1439 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK); 1440 1441 cc_rb_backend_disable = 1442 R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK); 1443 1444 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); 1445 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1446 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1447 1448 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 1449 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 1450 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 1451 1452 RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); 1453 RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0); 1454 RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0); 1455 RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0); 1456 RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0); 1457 1458 num_qd_pipes = 1459 R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK); 1460 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK); 1461 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK); 1462 1463 /* set HW defaults for 3D engine */ 1464 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) | 1465 R600_ROQ_IB2_START(0x2b))); 1466 1467 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30)); 1468 1469 RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO | 1470 R600_SYNC_GRADIENT | 1471 R600_SYNC_WALKER | 1472 R600_SYNC_ALIGNER)); 1473 1474 sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1); 1475 sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS; 1476 RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1); 1477 1478 smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0); 1479 smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff); 1480 smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1); 1481 RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0); 1482 1483 RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) | 1484 R700_GS_FLUSH_CTL(4) | 1485 R700_ACK_FLUSH_CTL(3) | 1486 R700_SYNC_FLUSH_CTL)); 1487 1488 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770) 1489 RADEON_WRITE(R700_DB_DEBUG3, R700_DB_CLK_OFF_DELAY(0x1f)); 1490 else { 1491 db_debug4 = RADEON_READ(RV700_DB_DEBUG4); 1492 db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER; 1493 RADEON_WRITE(RV700_DB_DEBUG4, db_debug4); 1494 } 1495 1496 RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) | 1497 R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) | 1498 R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1))); 1499 1500 RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) | 1501 R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) | 1502 R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize))); 1503 1504 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1505 1506 RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1); 1507 1508 RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0)); 1509 1510 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4)); 1511 1512 RADEON_WRITE(R600_CP_PERFMON_CNTL, 0); 1513 1514 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) | 1515 R600_DONE_FIFO_HIWATER(0xe0) | 1516 R600_ALU_UPDATE_FIFO_HIWATER(0x8)); 1517 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1518 case CHIP_RV770: 1519 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1); 1520 break; 1521 case CHIP_RV730: 1522 case CHIP_RV710: 1523 case CHIP_RV740: 1524 default: 1525 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4); 1526 break; 1527 } 1528 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 1529 1530 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 1531 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 1532 */ 1533 sq_config = RADEON_READ(R600_SQ_CONFIG); 1534 sq_config &= ~(R600_PS_PRIO(3) | 1535 R600_VS_PRIO(3) | 1536 R600_GS_PRIO(3) | 1537 R600_ES_PRIO(3)); 1538 sq_config |= (R600_DX9_CONSTS | 1539 R600_VC_ENABLE | 1540 R600_EXPORT_SRC_C | 1541 R600_PS_PRIO(0) | 1542 R600_VS_PRIO(1) | 1543 R600_GS_PRIO(2) | 1544 R600_ES_PRIO(3)); 1545 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) 1546 /* no vertex cache */ 1547 sq_config &= ~R600_VC_ENABLE; 1548 1549 RADEON_WRITE(R600_SQ_CONFIG, sq_config); 1550 1551 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) | 1552 R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) | 1553 R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2))); 1554 1555 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) | 1556 R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64))); 1557 1558 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) | 1559 R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) | 1560 R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8)); 1561 if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads) 1562 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads); 1563 else 1564 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8); 1565 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1566 1567 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) | 1568 R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); 1569 1570 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) | 1571 R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); 1572 1573 sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) | 1574 R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) | 1575 R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) | 1576 R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64)); 1577 1578 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); 1579 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); 1580 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); 1581 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); 1582 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); 1583 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); 1584 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); 1585 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); 1586 1587 RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) | 1588 R700_FORCE_EOV_MAX_REZ_CNT(255))); 1589 1590 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) 1591 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) | 1592 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO))); 1593 else 1594 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) | 1595 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO))); 1596 1597 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1598 case CHIP_RV770: 1599 case CHIP_RV730: 1600 case CHIP_RV740: 1601 gs_prim_buffer_depth = 384; 1602 break; 1603 case CHIP_RV710: 1604 gs_prim_buffer_depth = 128; 1605 break; 1606 default: 1607 break; 1608 } 1609 1610 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; 1611 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 1612 /* Max value for this is 256 */ 1613 if (vgt_gs_per_es > 256) 1614 vgt_gs_per_es = 256; 1615 1616 RADEON_WRITE(R600_VGT_ES_PER_GS, 128); 1617 RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es); 1618 RADEON_WRITE(R600_VGT_GS_PER_VS, 2); 1619 1620 /* more default values. 2D/3D driver should adjust as needed */ 1621 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16); 1622 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0); 1623 RADEON_WRITE(R600_VGT_STRMOUT_EN, 0); 1624 RADEON_WRITE(R600_SX_MISC, 0); 1625 RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0); 1626 RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa); 1627 RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0); 1628 RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff); 1629 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0); 1630 RADEON_WRITE(R600_SPI_INPUT_Z, 0); 1631 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2)); 1632 RADEON_WRITE(R600_CB_COLOR7_FRAG, 0); 1633 1634 /* clear render buffer base addresses */ 1635 RADEON_WRITE(R600_CB_COLOR0_BASE, 0); 1636 RADEON_WRITE(R600_CB_COLOR1_BASE, 0); 1637 RADEON_WRITE(R600_CB_COLOR2_BASE, 0); 1638 RADEON_WRITE(R600_CB_COLOR3_BASE, 0); 1639 RADEON_WRITE(R600_CB_COLOR4_BASE, 0); 1640 RADEON_WRITE(R600_CB_COLOR5_BASE, 0); 1641 RADEON_WRITE(R600_CB_COLOR6_BASE, 0); 1642 RADEON_WRITE(R600_CB_COLOR7_BASE, 0); 1643 1644 RADEON_WRITE(R700_TCP_CNTL, 0); 1645 1646 hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL); 1647 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1648 1649 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1650 1651 RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA | 1652 R600_NUM_CLIP_SEQ(3))); 1653 1654} 1655 1656static void r600_cp_init_ring_buffer(struct drm_device *dev, 1657 drm_radeon_private_t *dev_priv, 1658 struct drm_file *file_priv) 1659{ 1660 struct drm_radeon_master_private *master_priv; 1661 u32 ring_start; 1662 u64 rptr_addr; 1663 1664 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 1665 r700_gfx_init(dev, dev_priv); 1666 else 1667 r600_gfx_init(dev, dev_priv); 1668 1669 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 1670 RADEON_READ(R600_GRBM_SOFT_RESET); 1671 DRM_UDELAY(15000); 1672 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 1673 1674 1675 /* Set ring buffer size */ 1676#ifdef __BIG_ENDIAN 1677 RADEON_WRITE(R600_CP_RB_CNTL, 1678 RADEON_BUF_SWAP_32BIT | 1679 RADEON_RB_NO_UPDATE | 1680 (dev_priv->ring.rptr_update_l2qw << 8) | 1681 dev_priv->ring.size_l2qw); 1682#else 1683 RADEON_WRITE(R600_CP_RB_CNTL, 1684 RADEON_RB_NO_UPDATE | 1685 (dev_priv->ring.rptr_update_l2qw << 8) | 1686 dev_priv->ring.size_l2qw); 1687#endif 1688 1689 RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x4); 1690 1691 /* Set the write pointer delay */ 1692 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); 1693 1694#ifdef __BIG_ENDIAN 1695 RADEON_WRITE(R600_CP_RB_CNTL, 1696 RADEON_BUF_SWAP_32BIT | 1697 RADEON_RB_NO_UPDATE | 1698 RADEON_RB_RPTR_WR_ENA | 1699 (dev_priv->ring.rptr_update_l2qw << 8) | 1700 dev_priv->ring.size_l2qw); 1701#else 1702 RADEON_WRITE(R600_CP_RB_CNTL, 1703 RADEON_RB_NO_UPDATE | 1704 RADEON_RB_RPTR_WR_ENA | 1705 (dev_priv->ring.rptr_update_l2qw << 8) | 1706 dev_priv->ring.size_l2qw); 1707#endif 1708 1709 /* Initialize the ring buffer's read and write pointers */ 1710 RADEON_WRITE(R600_CP_RB_RPTR_WR, 0); 1711 RADEON_WRITE(R600_CP_RB_WPTR, 0); 1712 SET_RING_HEAD(dev_priv, 0); 1713 dev_priv->ring.tail = 0; 1714 1715#if __OS_HAS_AGP 1716 if (dev_priv->flags & RADEON_IS_AGP) { 1717 rptr_addr = dev_priv->ring_rptr->offset 1718 - dev->agp->base + 1719 dev_priv->gart_vm_start; 1720 } else 1721#endif 1722 { 1723 rptr_addr = dev_priv->ring_rptr->offset 1724 - ((unsigned long) dev->sg->virtual) 1725 + dev_priv->gart_vm_start; 1726 } 1727 RADEON_WRITE(R600_CP_RB_RPTR_ADDR, 1728 rptr_addr & 0xffffffff); 1729 RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI, 1730 upper_32_bits(rptr_addr)); 1731 1732#ifdef __BIG_ENDIAN 1733 RADEON_WRITE(R600_CP_RB_CNTL, 1734 RADEON_BUF_SWAP_32BIT | 1735 (dev_priv->ring.rptr_update_l2qw << 8) | 1736 dev_priv->ring.size_l2qw); 1737#else 1738 RADEON_WRITE(R600_CP_RB_CNTL, 1739 (dev_priv->ring.rptr_update_l2qw << 8) | 1740 dev_priv->ring.size_l2qw); 1741#endif 1742 1743#if __OS_HAS_AGP 1744 if (dev_priv->flags & RADEON_IS_AGP) { 1745 /* XXX */ 1746 radeon_write_agp_base(dev_priv, dev->agp->base); 1747 1748 /* XXX */ 1749 radeon_write_agp_location(dev_priv, 1750 (((dev_priv->gart_vm_start - 1 + 1751 dev_priv->gart_size) & 0xffff0000) | 1752 (dev_priv->gart_vm_start >> 16))); 1753 1754 ring_start = (dev_priv->cp_ring->offset 1755 - dev->agp->base 1756 + dev_priv->gart_vm_start); 1757 } else 1758#endif 1759 ring_start = (dev_priv->cp_ring->offset 1760 - (unsigned long)dev->sg->virtual 1761 + dev_priv->gart_vm_start); 1762 1763 RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8); 1764 1765 RADEON_WRITE(R600_CP_ME_CNTL, 0xff); 1766 1767 RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28)); 1768 1769 /* Initialize the scratch register pointer. This will cause 1770 * the scratch register values to be written out to memory 1771 * whenever they are updated. 1772 * 1773 * We simply put this behind the ring read pointer, this works 1774 * with PCI GART as well as (whatever kind of) AGP GART 1775 */ 1776 { 1777 u64 scratch_addr; 1778 1779 scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR); 1780 scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32; 1781 scratch_addr += R600_SCRATCH_REG_OFFSET; 1782 scratch_addr >>= 8; 1783 scratch_addr &= 0xffffffff; 1784 1785 RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr); 1786 } 1787 1788 RADEON_WRITE(R600_SCRATCH_UMSK, 0x7); 1789 1790 /* Turn on bus mastering */ 1791 radeon_enable_bm(dev_priv); 1792 1793 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0); 1794 RADEON_WRITE(R600_LAST_FRAME_REG, 0); 1795 1796 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0); 1797 RADEON_WRITE(R600_LAST_DISPATCH_REG, 0); 1798 1799 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0); 1800 RADEON_WRITE(R600_LAST_CLEAR_REG, 0); 1801 1802 /* reset sarea copies of these */ 1803 master_priv = file_priv->master->driver_priv; 1804 if (master_priv->sarea_priv) { 1805 master_priv->sarea_priv->last_frame = 0; 1806 master_priv->sarea_priv->last_dispatch = 0; 1807 master_priv->sarea_priv->last_clear = 0; 1808 } 1809 1810 r600_do_wait_for_idle(dev_priv); 1811 1812} 1813 1814int r600_do_cleanup_cp(struct drm_device *dev) 1815{ 1816 drm_radeon_private_t *dev_priv = dev->dev_private; 1817 DRM_DEBUG("\n"); 1818 1819 /* Make sure interrupts are disabled here because the uninstall ioctl 1820 * may not have been called from userspace and after dev_private 1821 * is freed, it's too late. 1822 */ 1823 if (dev->irq_enabled) 1824 drm_irq_uninstall(dev); 1825 1826#if __OS_HAS_AGP 1827 if (dev_priv->flags & RADEON_IS_AGP) { 1828 if (dev_priv->cp_ring != NULL) { 1829 drm_core_ioremapfree(dev_priv->cp_ring, dev); 1830 dev_priv->cp_ring = NULL; 1831 } 1832 if (dev_priv->ring_rptr != NULL) { 1833 drm_core_ioremapfree(dev_priv->ring_rptr, dev); 1834 dev_priv->ring_rptr = NULL; 1835 } 1836 if (dev->agp_buffer_map != NULL) { 1837 drm_core_ioremapfree(dev->agp_buffer_map, dev); 1838 dev->agp_buffer_map = NULL; 1839 } 1840 } else 1841#endif 1842 { 1843 1844 if (dev_priv->gart_info.bus_addr) 1845 r600_page_table_cleanup(dev, &dev_priv->gart_info); 1846 1847 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) { 1848 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); 1849 dev_priv->gart_info.addr = NULL; 1850 } 1851 } 1852 /* only clear to the start of flags */ 1853 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); 1854 1855 return 0; 1856} 1857 1858int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, 1859 struct drm_file *file_priv) 1860{ 1861 drm_radeon_private_t *dev_priv = dev->dev_private; 1862 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; 1863 1864 DRM_DEBUG("\n"); 1865 1866 mutex_init(&dev_priv->cs_mutex); 1867 r600_cs_legacy_init(); 1868 /* if we require new memory map but we don't have it fail */ 1869 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { 1870 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); 1871 r600_do_cleanup_cp(dev); 1872 return -EINVAL; 1873 } 1874 1875 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) { 1876 DRM_DEBUG("Forcing AGP card to PCI mode\n"); 1877 dev_priv->flags &= ~RADEON_IS_AGP; 1878 /* The writeback test succeeds, but when writeback is enabled, 1879 * the ring buffer read ptr update fails after first 128 bytes. 1880 */ 1881 radeon_no_wb = 1; 1882 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) 1883 && !init->is_pci) { 1884 DRM_DEBUG("Restoring AGP flag\n"); 1885 dev_priv->flags |= RADEON_IS_AGP; 1886 } 1887 1888 dev_priv->usec_timeout = init->usec_timeout; 1889 if (dev_priv->usec_timeout < 1 || 1890 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { 1891 DRM_DEBUG("TIMEOUT problem!\n"); 1892 r600_do_cleanup_cp(dev); 1893 return -EINVAL; 1894 } 1895 1896 /* Enable vblank on CRTC1 for older X servers 1897 */ 1898 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; 1899 dev_priv->do_boxes = 0; 1900 dev_priv->cp_mode = init->cp_mode; 1901 1902 /* We don't support anything other than bus-mastering ring mode, 1903 * but the ring can be in either AGP or PCI space for the ring 1904 * read pointer. 1905 */ 1906 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && 1907 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { 1908 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); 1909 r600_do_cleanup_cp(dev); 1910 return -EINVAL; 1911 } 1912 1913 switch (init->fb_bpp) { 1914 case 16: 1915 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; 1916 break; 1917 case 32: 1918 default: 1919 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; 1920 break; 1921 } 1922 dev_priv->front_offset = init->front_offset; 1923 dev_priv->front_pitch = init->front_pitch; 1924 dev_priv->back_offset = init->back_offset; 1925 dev_priv->back_pitch = init->back_pitch; 1926 1927 dev_priv->ring_offset = init->ring_offset; 1928 dev_priv->ring_rptr_offset = init->ring_rptr_offset; 1929 dev_priv->buffers_offset = init->buffers_offset; 1930 dev_priv->gart_textures_offset = init->gart_textures_offset; 1931 1932 master_priv->sarea = drm_getsarea(dev); 1933 if (!master_priv->sarea) { 1934 DRM_ERROR("could not find sarea!\n"); 1935 r600_do_cleanup_cp(dev); 1936 return -EINVAL; 1937 } 1938 1939 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); 1940 if (!dev_priv->cp_ring) { 1941 DRM_ERROR("could not find cp ring region!\n"); 1942 r600_do_cleanup_cp(dev); 1943 return -EINVAL; 1944 } 1945 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); 1946 if (!dev_priv->ring_rptr) { 1947 DRM_ERROR("could not find ring read pointer!\n"); 1948 r600_do_cleanup_cp(dev); 1949 return -EINVAL; 1950 } 1951 dev->agp_buffer_token = init->buffers_offset; 1952 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); 1953 if (!dev->agp_buffer_map) { 1954 DRM_ERROR("could not find dma buffer region!\n"); 1955 r600_do_cleanup_cp(dev); 1956 return -EINVAL; 1957 } 1958 1959 if (init->gart_textures_offset) { 1960 dev_priv->gart_textures = 1961 drm_core_findmap(dev, init->gart_textures_offset); 1962 if (!dev_priv->gart_textures) { 1963 DRM_ERROR("could not find GART texture region!\n"); 1964 r600_do_cleanup_cp(dev); 1965 return -EINVAL; 1966 } 1967 } 1968 1969#if __OS_HAS_AGP 1970 /* XXX */ 1971 if (dev_priv->flags & RADEON_IS_AGP) { 1972 drm_core_ioremap_wc(dev_priv->cp_ring, dev); 1973 drm_core_ioremap_wc(dev_priv->ring_rptr, dev); 1974 drm_core_ioremap_wc(dev->agp_buffer_map, dev); 1975 if (!dev_priv->cp_ring->handle || 1976 !dev_priv->ring_rptr->handle || 1977 !dev->agp_buffer_map->handle) { 1978 DRM_ERROR("could not find ioremap agp regions!\n"); 1979 r600_do_cleanup_cp(dev); 1980 return -EINVAL; 1981 } 1982 } else 1983#endif 1984 { 1985 dev_priv->cp_ring->handle = (void *)(unsigned long)dev_priv->cp_ring->offset; 1986 dev_priv->ring_rptr->handle = 1987 (void *)(unsigned long)dev_priv->ring_rptr->offset; 1988 dev->agp_buffer_map->handle = 1989 (void *)(unsigned long)dev->agp_buffer_map->offset; 1990 1991 DRM_DEBUG("dev_priv->cp_ring->handle %p\n", 1992 dev_priv->cp_ring->handle); 1993 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", 1994 dev_priv->ring_rptr->handle); 1995 DRM_DEBUG("dev->agp_buffer_map->handle %p\n", 1996 dev->agp_buffer_map->handle); 1997 } 1998 1999 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24; 2000 dev_priv->fb_size = 2001 (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000) 2002 - dev_priv->fb_location; 2003 2004 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | 2005 ((dev_priv->front_offset 2006 + dev_priv->fb_location) >> 10)); 2007 2008 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | 2009 ((dev_priv->back_offset 2010 + dev_priv->fb_location) >> 10)); 2011 2012 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | 2013 ((dev_priv->depth_offset 2014 + dev_priv->fb_location) >> 10)); 2015 2016 dev_priv->gart_size = init->gart_size; 2017 2018 /* New let's set the memory map ... */ 2019 if (dev_priv->new_memmap) { 2020 u32 base = 0; 2021 2022 DRM_INFO("Setting GART location based on new memory map\n"); 2023 2024 /* If using AGP, try to locate the AGP aperture at the same 2025 * location in the card and on the bus, though we have to 2026 * align it down. 2027 */ 2028#if __OS_HAS_AGP 2029 /* XXX */ 2030 if (dev_priv->flags & RADEON_IS_AGP) { 2031 base = dev->agp->base; 2032 /* Check if valid */ 2033 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && 2034 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { 2035 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n", 2036 dev->agp->base); 2037 base = 0; 2038 } 2039 } 2040#endif 2041 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */ 2042 if (base == 0) { 2043 base = dev_priv->fb_location + dev_priv->fb_size; 2044 if (base < dev_priv->fb_location || 2045 ((base + dev_priv->gart_size) & 0xfffffffful) < base) 2046 base = dev_priv->fb_location 2047 - dev_priv->gart_size; 2048 } 2049 dev_priv->gart_vm_start = base & 0xffc00000u; 2050 if (dev_priv->gart_vm_start != base) 2051 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n", 2052 base, dev_priv->gart_vm_start); 2053 } 2054 2055#if __OS_HAS_AGP 2056 /* XXX */ 2057 if (dev_priv->flags & RADEON_IS_AGP) 2058 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 2059 - dev->agp->base 2060 + dev_priv->gart_vm_start); 2061 else 2062#endif 2063 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 2064 - (unsigned long)dev->sg->virtual 2065 + dev_priv->gart_vm_start); 2066 2067 DRM_DEBUG("fb 0x%08x size %d\n", 2068 (unsigned int) dev_priv->fb_location, 2069 (unsigned int) dev_priv->fb_size); 2070 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); 2071 DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n", 2072 (unsigned int) dev_priv->gart_vm_start); 2073 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n", 2074 dev_priv->gart_buffers_offset); 2075 2076 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; 2077 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle 2078 + init->ring_size / sizeof(u32)); 2079 dev_priv->ring.size = init->ring_size; 2080 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); 2081 2082 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; 2083 dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8); 2084 2085 dev_priv->ring.fetch_size = /* init->fetch_size */ 32; 2086 dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16); 2087 2088 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; 2089 2090 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; 2091 2092#if __OS_HAS_AGP 2093 if (dev_priv->flags & RADEON_IS_AGP) { 2094 /* XXX turn off pcie gart */ 2095 } else 2096#endif 2097 { 2098 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); 2099 /* if we have an offset set from userspace */ 2100 if (!dev_priv->pcigart_offset_set) { 2101 DRM_ERROR("Need gart offset from userspace\n"); 2102 r600_do_cleanup_cp(dev); 2103 return -EINVAL; 2104 } 2105 2106 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset); 2107 2108 dev_priv->gart_info.bus_addr = 2109 dev_priv->pcigart_offset + dev_priv->fb_location; 2110 dev_priv->gart_info.mapping.offset = 2111 dev_priv->pcigart_offset + dev_priv->fb_aper_offset; 2112 dev_priv->gart_info.mapping.size = 2113 dev_priv->gart_info.table_size; 2114 2115 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev); 2116 if (!dev_priv->gart_info.mapping.handle) { 2117 DRM_ERROR("ioremap failed.\n"); 2118 r600_do_cleanup_cp(dev); 2119 return -EINVAL; 2120 } 2121 2122 dev_priv->gart_info.addr = 2123 dev_priv->gart_info.mapping.handle; 2124 2125 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n", 2126 dev_priv->gart_info.addr, 2127 dev_priv->pcigart_offset); 2128 2129 if (!r600_page_table_init(dev)) { 2130 DRM_ERROR("Failed to init GART table\n"); 2131 r600_do_cleanup_cp(dev); 2132 return -EINVAL; 2133 } 2134 2135 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 2136 r700_vm_init(dev); 2137 else 2138 r600_vm_init(dev); 2139 } 2140 2141 if (!dev_priv->me_fw || !dev_priv->pfp_fw) { 2142 int err = r600_cp_init_microcode(dev_priv); 2143 if (err) { 2144 DRM_ERROR("Failed to load firmware!\n"); 2145 r600_do_cleanup_cp(dev); 2146 return err; 2147 } 2148 } 2149 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 2150 r700_cp_load_microcode(dev_priv); 2151 else 2152 r600_cp_load_microcode(dev_priv); 2153 2154 r600_cp_init_ring_buffer(dev, dev_priv, file_priv); 2155 2156 dev_priv->last_buf = 0; 2157 2158 r600_do_engine_reset(dev); 2159 r600_test_writeback(dev_priv); 2160 2161 return 0; 2162} 2163 2164int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv) 2165{ 2166 drm_radeon_private_t *dev_priv = dev->dev_private; 2167 2168 DRM_DEBUG("\n"); 2169 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) { 2170 r700_vm_init(dev); 2171 r700_cp_load_microcode(dev_priv); 2172 } else { 2173 r600_vm_init(dev); 2174 r600_cp_load_microcode(dev_priv); 2175 } 2176 r600_cp_init_ring_buffer(dev, dev_priv, file_priv); 2177 r600_do_engine_reset(dev); 2178 2179 return 0; 2180} 2181 2182/* Wait for the CP to go idle. 2183 */ 2184int r600_do_cp_idle(drm_radeon_private_t *dev_priv) 2185{ 2186 RING_LOCALS; 2187 DRM_DEBUG("\n"); 2188 2189 BEGIN_RING(5); 2190 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); 2191 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT); 2192 /* wait for 3D idle clean */ 2193 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); 2194 OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2); 2195 OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN); 2196 2197 ADVANCE_RING(); 2198 COMMIT_RING(); 2199 2200 return r600_do_wait_for_idle(dev_priv); 2201} 2202 2203/* Start the Command Processor. 2204 */ 2205void r600_do_cp_start(drm_radeon_private_t *dev_priv) 2206{ 2207 u32 cp_me; 2208 RING_LOCALS; 2209 DRM_DEBUG("\n"); 2210 2211 BEGIN_RING(7); 2212 OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5)); 2213 OUT_RING(0x00000001); 2214 if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) 2215 OUT_RING(0x00000003); 2216 else 2217 OUT_RING(0x00000000); 2218 OUT_RING((dev_priv->r600_max_hw_contexts - 1)); 2219 OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1)); 2220 OUT_RING(0x00000000); 2221 OUT_RING(0x00000000); 2222 ADVANCE_RING(); 2223 COMMIT_RING(); 2224 2225 /* set the mux and reset the halt bit */ 2226 cp_me = 0xff; 2227 RADEON_WRITE(R600_CP_ME_CNTL, cp_me); 2228 2229 dev_priv->cp_running = 1; 2230 2231} 2232 2233void r600_do_cp_reset(drm_radeon_private_t *dev_priv) 2234{ 2235 u32 cur_read_ptr; 2236 DRM_DEBUG("\n"); 2237 2238 cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR); 2239 RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr); 2240 SET_RING_HEAD(dev_priv, cur_read_ptr); 2241 dev_priv->ring.tail = cur_read_ptr; 2242} 2243 2244void r600_do_cp_stop(drm_radeon_private_t *dev_priv) 2245{ 2246 uint32_t cp_me; 2247 2248 DRM_DEBUG("\n"); 2249 2250 cp_me = 0xff | R600_CP_ME_HALT; 2251 2252 RADEON_WRITE(R600_CP_ME_CNTL, cp_me); 2253 2254 dev_priv->cp_running = 0; 2255} 2256 2257int r600_cp_dispatch_indirect(struct drm_device *dev, 2258 struct drm_buf *buf, int start, int end) 2259{ 2260 drm_radeon_private_t *dev_priv = dev->dev_private; 2261 RING_LOCALS; 2262 2263 if (start != end) { 2264 unsigned long offset = (dev_priv->gart_buffers_offset 2265 + buf->offset + start); 2266 int dwords = (end - start + 3) / sizeof(u32); 2267 2268 DRM_DEBUG("dwords:%d\n", dwords); 2269 DRM_DEBUG("offset 0x%lx\n", offset); 2270 2271 2272 /* Indirect buffer data must be a multiple of 16 dwords. 2273 * pad the data with a Type-2 CP packet. 2274 */ 2275 while (dwords & 0xf) { 2276 u32 *data = (u32 *) 2277 ((char *)dev->agp_buffer_map->handle 2278 + buf->offset + start); 2279 data[dwords++] = RADEON_CP_PACKET2; 2280 } 2281 2282 /* Fire off the indirect buffer */ 2283 BEGIN_RING(4); 2284 OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2)); 2285 OUT_RING((offset & 0xfffffffc)); 2286 OUT_RING((upper_32_bits(offset) & 0xff)); 2287 OUT_RING(dwords); 2288 ADVANCE_RING(); 2289 } 2290 2291 return 0; 2292} 2293 2294void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv) 2295{ 2296 drm_radeon_private_t *dev_priv = dev->dev_private; 2297 struct drm_master *master = file_priv->master; 2298 struct drm_radeon_master_private *master_priv = master->driver_priv; 2299 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; 2300 int nbox = sarea_priv->nbox; 2301 struct drm_clip_rect *pbox = sarea_priv->boxes; 2302 int i, cpp, src_pitch, dst_pitch; 2303 uint64_t src, dst; 2304 RING_LOCALS; 2305 DRM_DEBUG("\n"); 2306 2307 if (dev_priv->color_fmt == RADEON_COLOR_FORMAT_ARGB8888) 2308 cpp = 4; 2309 else 2310 cpp = 2; 2311 2312 if (sarea_priv->pfCurrentPage == 0) { 2313 src_pitch = dev_priv->back_pitch; 2314 dst_pitch = dev_priv->front_pitch; 2315 src = dev_priv->back_offset + dev_priv->fb_location; 2316 dst = dev_priv->front_offset + dev_priv->fb_location; 2317 } else { 2318 src_pitch = dev_priv->front_pitch; 2319 dst_pitch = dev_priv->back_pitch; 2320 src = dev_priv->front_offset + dev_priv->fb_location; 2321 dst = dev_priv->back_offset + dev_priv->fb_location; 2322 } 2323 2324 if (r600_prepare_blit_copy(dev, file_priv)) { 2325 DRM_ERROR("unable to allocate vertex buffer for swap buffer\n"); 2326 return; 2327 } 2328 for (i = 0; i < nbox; i++) { 2329 int x = pbox[i].x1; 2330 int y = pbox[i].y1; 2331 int w = pbox[i].x2 - x; 2332 int h = pbox[i].y2 - y; 2333 2334 DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h); 2335 2336 r600_blit_swap(dev, 2337 src, dst, 2338 x, y, x, y, w, h, 2339 src_pitch, dst_pitch, cpp); 2340 } 2341 r600_done_blit_copy(dev); 2342 2343 /* Increment the frame counter. The client-side 3D driver must 2344 * throttle the framerate by waiting for this value before 2345 * performing the swapbuffer ioctl. 2346 */ 2347 sarea_priv->last_frame++; 2348 2349 BEGIN_RING(3); 2350 R600_FRAME_AGE(sarea_priv->last_frame); 2351 ADVANCE_RING(); 2352} 2353 2354int r600_cp_dispatch_texture(struct drm_device *dev, 2355 struct drm_file *file_priv, 2356 drm_radeon_texture_t *tex, 2357 drm_radeon_tex_image_t *image) 2358{ 2359 drm_radeon_private_t *dev_priv = dev->dev_private; 2360 struct drm_buf *buf; 2361 u32 *buffer; 2362 const u8 __user *data; 2363 int size, pass_size; 2364 u64 src_offset, dst_offset; 2365 2366 if (!radeon_check_offset(dev_priv, tex->offset)) { 2367 DRM_ERROR("Invalid destination offset\n"); 2368 return -EINVAL; 2369 } 2370 2371 /* this might fail for zero-sized uploads - are those illegal? */ 2372 if (!radeon_check_offset(dev_priv, tex->offset + tex->height * tex->pitch - 1)) { 2373 DRM_ERROR("Invalid final destination offset\n"); 2374 return -EINVAL; 2375 } 2376 2377 size = tex->height * tex->pitch; 2378 2379 if (size == 0) 2380 return 0; 2381 2382 dst_offset = tex->offset; 2383 2384 if (r600_prepare_blit_copy(dev, file_priv)) { 2385 DRM_ERROR("unable to allocate vertex buffer for swap buffer\n"); 2386 return -EAGAIN; 2387 } 2388 do { 2389 data = (const u8 __user *)image->data; 2390 pass_size = size; 2391 2392 buf = radeon_freelist_get(dev); 2393 if (!buf) { 2394 DRM_DEBUG("EAGAIN\n"); 2395 if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image))) 2396 return -EFAULT; 2397 return -EAGAIN; 2398 } 2399 2400 if (pass_size > buf->total) 2401 pass_size = buf->total; 2402 2403 /* Dispatch the indirect buffer. 2404 */ 2405 buffer = 2406 (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset); 2407 2408 if (DRM_COPY_FROM_USER(buffer, data, pass_size)) { 2409 DRM_ERROR("EFAULT on pad, %d bytes\n", pass_size); 2410 return -EFAULT; 2411 } 2412 2413 buf->file_priv = file_priv; 2414 buf->used = pass_size; 2415 src_offset = dev_priv->gart_buffers_offset + buf->offset; 2416 2417 r600_blit_copy(dev, src_offset, dst_offset, pass_size); 2418 2419 radeon_cp_discard_buffer(dev, file_priv->master, buf); 2420 2421 /* Update the input parameters for next time */ 2422 image->data = (const u8 __user *)image->data + pass_size; 2423 dst_offset += pass_size; 2424 size -= pass_size; 2425 } while (size > 0); 2426 r600_done_blit_copy(dev); 2427 2428 return 0; 2429} 2430 2431/* 2432 * Legacy cs ioctl 2433 */ 2434static u32 radeon_cs_id_get(struct drm_radeon_private *radeon) 2435{ 2436 /* FIXME: check if wrap affect last reported wrap & sequence */ 2437 radeon->cs_id_scnt = (radeon->cs_id_scnt + 1) & 0x00FFFFFF; 2438 if (!radeon->cs_id_scnt) { 2439 /* increment wrap counter */ 2440 radeon->cs_id_wcnt += 0x01000000; 2441 /* valid sequence counter start at 1 */ 2442 radeon->cs_id_scnt = 1; 2443 } 2444 return (radeon->cs_id_scnt | radeon->cs_id_wcnt); 2445} 2446 2447static void r600_cs_id_emit(drm_radeon_private_t *dev_priv, u32 *id) 2448{ 2449 RING_LOCALS; 2450 2451 *id = radeon_cs_id_get(dev_priv); 2452 2453 /* SCRATCH 2 */ 2454 BEGIN_RING(3); 2455 R600_CLEAR_AGE(*id); 2456 ADVANCE_RING(); 2457 COMMIT_RING(); 2458} 2459 2460static int r600_ib_get(struct drm_device *dev, 2461 struct drm_file *fpriv, 2462 struct drm_buf **buffer) 2463{ 2464 struct drm_buf *buf; 2465 2466 *buffer = NULL; 2467 buf = radeon_freelist_get(dev); 2468 if (!buf) { 2469 return -EBUSY; 2470 } 2471 buf->file_priv = fpriv; 2472 *buffer = buf; 2473 return 0; 2474} 2475 2476static void r600_ib_free(struct drm_device *dev, struct drm_buf *buf, 2477 struct drm_file *fpriv, int l, int r) 2478{ 2479 drm_radeon_private_t *dev_priv = dev->dev_private; 2480 2481 if (buf) { 2482 if (!r) 2483 r600_cp_dispatch_indirect(dev, buf, 0, l * 4); 2484 radeon_cp_discard_buffer(dev, fpriv->master, buf); 2485 COMMIT_RING(); 2486 } 2487} 2488 2489int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv) 2490{ 2491 struct drm_radeon_private *dev_priv = dev->dev_private; 2492 struct drm_radeon_cs *cs = data; 2493 struct drm_buf *buf; 2494 unsigned family; 2495 int l, r = 0; 2496 u32 *ib, cs_id = 0; 2497 2498 if (dev_priv == NULL) { 2499 DRM_ERROR("called with no initialization\n"); 2500 return -EINVAL; 2501 } 2502 family = dev_priv->flags & RADEON_FAMILY_MASK; 2503 if (family < CHIP_R600) { 2504 DRM_ERROR("cs ioctl valid only for R6XX & R7XX in legacy mode\n"); 2505 return -EINVAL; 2506 } 2507 mutex_lock(&dev_priv->cs_mutex); 2508 /* get ib */ 2509 r = r600_ib_get(dev, fpriv, &buf); 2510 if (r) { 2511 DRM_ERROR("ib_get failed\n"); 2512 goto out; 2513 } 2514 ib = dev->agp_buffer_map->handle + buf->offset; 2515 /* now parse command stream */ 2516 r = r600_cs_legacy(dev, data, fpriv, family, ib, &l); 2517 if (r) { 2518 goto out; 2519 } 2520 2521out: 2522 r600_ib_free(dev, buf, fpriv, l, r); 2523 /* emit cs id sequence */ 2524 r600_cs_id_emit(dev_priv, &cs_id); 2525 cs->cs_id = cs_id; 2526 mutex_unlock(&dev_priv->cs_mutex); 2527 return r; 2528} 2529