radeon_combios.c revision 6a93cb250a60af1bb7b4070949f8546a2fdc52ef
1/* 2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario 3 * Copyright 2007-8 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 */ 27#include "drmP.h" 28#include "radeon_drm.h" 29#include "radeon.h" 30#include "atom.h" 31 32#ifdef CONFIG_PPC_PMAC 33/* not sure which of these are needed */ 34#include <asm/machdep.h> 35#include <asm/pmac_feature.h> 36#include <asm/prom.h> 37#include <asm/pci-bridge.h> 38#endif /* CONFIG_PPC_PMAC */ 39 40/* from radeon_encoder.c */ 41extern uint32_t 42radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, 43 uint8_t dac); 44extern void radeon_link_encoder_connector(struct drm_device *dev); 45 46/* from radeon_connector.c */ 47extern void 48radeon_add_legacy_connector(struct drm_device *dev, 49 uint32_t connector_id, 50 uint32_t supported_device, 51 int connector_type, 52 struct radeon_i2c_bus_rec *i2c_bus, 53 uint16_t connector_object_id); 54 55/* from radeon_legacy_encoder.c */ 56extern void 57radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, 58 uint32_t supported_device); 59 60/* old legacy ATI BIOS routines */ 61 62/* COMBIOS table offsets */ 63enum radeon_combios_table_offset { 64 /* absolute offset tables */ 65 COMBIOS_ASIC_INIT_1_TABLE, 66 COMBIOS_BIOS_SUPPORT_TABLE, 67 COMBIOS_DAC_PROGRAMMING_TABLE, 68 COMBIOS_MAX_COLOR_DEPTH_TABLE, 69 COMBIOS_CRTC_INFO_TABLE, 70 COMBIOS_PLL_INFO_TABLE, 71 COMBIOS_TV_INFO_TABLE, 72 COMBIOS_DFP_INFO_TABLE, 73 COMBIOS_HW_CONFIG_INFO_TABLE, 74 COMBIOS_MULTIMEDIA_INFO_TABLE, 75 COMBIOS_TV_STD_PATCH_TABLE, 76 COMBIOS_LCD_INFO_TABLE, 77 COMBIOS_MOBILE_INFO_TABLE, 78 COMBIOS_PLL_INIT_TABLE, 79 COMBIOS_MEM_CONFIG_TABLE, 80 COMBIOS_SAVE_MASK_TABLE, 81 COMBIOS_HARDCODED_EDID_TABLE, 82 COMBIOS_ASIC_INIT_2_TABLE, 83 COMBIOS_CONNECTOR_INFO_TABLE, 84 COMBIOS_DYN_CLK_1_TABLE, 85 COMBIOS_RESERVED_MEM_TABLE, 86 COMBIOS_EXT_TMDS_INFO_TABLE, 87 COMBIOS_MEM_CLK_INFO_TABLE, 88 COMBIOS_EXT_DAC_INFO_TABLE, 89 COMBIOS_MISC_INFO_TABLE, 90 COMBIOS_CRT_INFO_TABLE, 91 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE, 92 COMBIOS_COMPONENT_VIDEO_INFO_TABLE, 93 COMBIOS_FAN_SPEED_INFO_TABLE, 94 COMBIOS_OVERDRIVE_INFO_TABLE, 95 COMBIOS_OEM_INFO_TABLE, 96 COMBIOS_DYN_CLK_2_TABLE, 97 COMBIOS_POWER_CONNECTOR_INFO_TABLE, 98 COMBIOS_I2C_INFO_TABLE, 99 /* relative offset tables */ 100 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */ 101 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */ 102 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */ 103 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */ 104 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */ 105 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */ 106 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */ 107 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */ 108 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */ 109 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */ 110 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */ 111}; 112 113enum radeon_combios_ddc { 114 DDC_NONE_DETECTED, 115 DDC_MONID, 116 DDC_DVI, 117 DDC_VGA, 118 DDC_CRT2, 119 DDC_LCD, 120 DDC_GPIO, 121}; 122 123enum radeon_combios_connector { 124 CONNECTOR_NONE_LEGACY, 125 CONNECTOR_PROPRIETARY_LEGACY, 126 CONNECTOR_CRT_LEGACY, 127 CONNECTOR_DVI_I_LEGACY, 128 CONNECTOR_DVI_D_LEGACY, 129 CONNECTOR_CTV_LEGACY, 130 CONNECTOR_STV_LEGACY, 131 CONNECTOR_UNSUPPORTED_LEGACY 132}; 133 134const int legacy_connector_convert[] = { 135 DRM_MODE_CONNECTOR_Unknown, 136 DRM_MODE_CONNECTOR_DVID, 137 DRM_MODE_CONNECTOR_VGA, 138 DRM_MODE_CONNECTOR_DVII, 139 DRM_MODE_CONNECTOR_DVID, 140 DRM_MODE_CONNECTOR_Composite, 141 DRM_MODE_CONNECTOR_SVIDEO, 142 DRM_MODE_CONNECTOR_Unknown, 143}; 144 145static uint16_t combios_get_table_offset(struct drm_device *dev, 146 enum radeon_combios_table_offset table) 147{ 148 struct radeon_device *rdev = dev->dev_private; 149 int rev; 150 uint16_t offset = 0, check_offset; 151 152 switch (table) { 153 /* absolute offset tables */ 154 case COMBIOS_ASIC_INIT_1_TABLE: 155 check_offset = RBIOS16(rdev->bios_header_start + 0xc); 156 if (check_offset) 157 offset = check_offset; 158 break; 159 case COMBIOS_BIOS_SUPPORT_TABLE: 160 check_offset = RBIOS16(rdev->bios_header_start + 0x14); 161 if (check_offset) 162 offset = check_offset; 163 break; 164 case COMBIOS_DAC_PROGRAMMING_TABLE: 165 check_offset = RBIOS16(rdev->bios_header_start + 0x2a); 166 if (check_offset) 167 offset = check_offset; 168 break; 169 case COMBIOS_MAX_COLOR_DEPTH_TABLE: 170 check_offset = RBIOS16(rdev->bios_header_start + 0x2c); 171 if (check_offset) 172 offset = check_offset; 173 break; 174 case COMBIOS_CRTC_INFO_TABLE: 175 check_offset = RBIOS16(rdev->bios_header_start + 0x2e); 176 if (check_offset) 177 offset = check_offset; 178 break; 179 case COMBIOS_PLL_INFO_TABLE: 180 check_offset = RBIOS16(rdev->bios_header_start + 0x30); 181 if (check_offset) 182 offset = check_offset; 183 break; 184 case COMBIOS_TV_INFO_TABLE: 185 check_offset = RBIOS16(rdev->bios_header_start + 0x32); 186 if (check_offset) 187 offset = check_offset; 188 break; 189 case COMBIOS_DFP_INFO_TABLE: 190 check_offset = RBIOS16(rdev->bios_header_start + 0x34); 191 if (check_offset) 192 offset = check_offset; 193 break; 194 case COMBIOS_HW_CONFIG_INFO_TABLE: 195 check_offset = RBIOS16(rdev->bios_header_start + 0x36); 196 if (check_offset) 197 offset = check_offset; 198 break; 199 case COMBIOS_MULTIMEDIA_INFO_TABLE: 200 check_offset = RBIOS16(rdev->bios_header_start + 0x38); 201 if (check_offset) 202 offset = check_offset; 203 break; 204 case COMBIOS_TV_STD_PATCH_TABLE: 205 check_offset = RBIOS16(rdev->bios_header_start + 0x3e); 206 if (check_offset) 207 offset = check_offset; 208 break; 209 case COMBIOS_LCD_INFO_TABLE: 210 check_offset = RBIOS16(rdev->bios_header_start + 0x40); 211 if (check_offset) 212 offset = check_offset; 213 break; 214 case COMBIOS_MOBILE_INFO_TABLE: 215 check_offset = RBIOS16(rdev->bios_header_start + 0x42); 216 if (check_offset) 217 offset = check_offset; 218 break; 219 case COMBIOS_PLL_INIT_TABLE: 220 check_offset = RBIOS16(rdev->bios_header_start + 0x46); 221 if (check_offset) 222 offset = check_offset; 223 break; 224 case COMBIOS_MEM_CONFIG_TABLE: 225 check_offset = RBIOS16(rdev->bios_header_start + 0x48); 226 if (check_offset) 227 offset = check_offset; 228 break; 229 case COMBIOS_SAVE_MASK_TABLE: 230 check_offset = RBIOS16(rdev->bios_header_start + 0x4a); 231 if (check_offset) 232 offset = check_offset; 233 break; 234 case COMBIOS_HARDCODED_EDID_TABLE: 235 check_offset = RBIOS16(rdev->bios_header_start + 0x4c); 236 if (check_offset) 237 offset = check_offset; 238 break; 239 case COMBIOS_ASIC_INIT_2_TABLE: 240 check_offset = RBIOS16(rdev->bios_header_start + 0x4e); 241 if (check_offset) 242 offset = check_offset; 243 break; 244 case COMBIOS_CONNECTOR_INFO_TABLE: 245 check_offset = RBIOS16(rdev->bios_header_start + 0x50); 246 if (check_offset) 247 offset = check_offset; 248 break; 249 case COMBIOS_DYN_CLK_1_TABLE: 250 check_offset = RBIOS16(rdev->bios_header_start + 0x52); 251 if (check_offset) 252 offset = check_offset; 253 break; 254 case COMBIOS_RESERVED_MEM_TABLE: 255 check_offset = RBIOS16(rdev->bios_header_start + 0x54); 256 if (check_offset) 257 offset = check_offset; 258 break; 259 case COMBIOS_EXT_TMDS_INFO_TABLE: 260 check_offset = RBIOS16(rdev->bios_header_start + 0x58); 261 if (check_offset) 262 offset = check_offset; 263 break; 264 case COMBIOS_MEM_CLK_INFO_TABLE: 265 check_offset = RBIOS16(rdev->bios_header_start + 0x5a); 266 if (check_offset) 267 offset = check_offset; 268 break; 269 case COMBIOS_EXT_DAC_INFO_TABLE: 270 check_offset = RBIOS16(rdev->bios_header_start + 0x5c); 271 if (check_offset) 272 offset = check_offset; 273 break; 274 case COMBIOS_MISC_INFO_TABLE: 275 check_offset = RBIOS16(rdev->bios_header_start + 0x5e); 276 if (check_offset) 277 offset = check_offset; 278 break; 279 case COMBIOS_CRT_INFO_TABLE: 280 check_offset = RBIOS16(rdev->bios_header_start + 0x60); 281 if (check_offset) 282 offset = check_offset; 283 break; 284 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE: 285 check_offset = RBIOS16(rdev->bios_header_start + 0x62); 286 if (check_offset) 287 offset = check_offset; 288 break; 289 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE: 290 check_offset = RBIOS16(rdev->bios_header_start + 0x64); 291 if (check_offset) 292 offset = check_offset; 293 break; 294 case COMBIOS_FAN_SPEED_INFO_TABLE: 295 check_offset = RBIOS16(rdev->bios_header_start + 0x66); 296 if (check_offset) 297 offset = check_offset; 298 break; 299 case COMBIOS_OVERDRIVE_INFO_TABLE: 300 check_offset = RBIOS16(rdev->bios_header_start + 0x68); 301 if (check_offset) 302 offset = check_offset; 303 break; 304 case COMBIOS_OEM_INFO_TABLE: 305 check_offset = RBIOS16(rdev->bios_header_start + 0x6a); 306 if (check_offset) 307 offset = check_offset; 308 break; 309 case COMBIOS_DYN_CLK_2_TABLE: 310 check_offset = RBIOS16(rdev->bios_header_start + 0x6c); 311 if (check_offset) 312 offset = check_offset; 313 break; 314 case COMBIOS_POWER_CONNECTOR_INFO_TABLE: 315 check_offset = RBIOS16(rdev->bios_header_start + 0x6e); 316 if (check_offset) 317 offset = check_offset; 318 break; 319 case COMBIOS_I2C_INFO_TABLE: 320 check_offset = RBIOS16(rdev->bios_header_start + 0x70); 321 if (check_offset) 322 offset = check_offset; 323 break; 324 /* relative offset tables */ 325 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */ 326 check_offset = 327 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 328 if (check_offset) { 329 rev = RBIOS8(check_offset); 330 if (rev > 0) { 331 check_offset = RBIOS16(check_offset + 0x3); 332 if (check_offset) 333 offset = check_offset; 334 } 335 } 336 break; 337 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */ 338 check_offset = 339 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 340 if (check_offset) { 341 rev = RBIOS8(check_offset); 342 if (rev > 0) { 343 check_offset = RBIOS16(check_offset + 0x5); 344 if (check_offset) 345 offset = check_offset; 346 } 347 } 348 break; 349 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */ 350 check_offset = 351 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 352 if (check_offset) { 353 rev = RBIOS8(check_offset); 354 if (rev > 0) { 355 check_offset = RBIOS16(check_offset + 0x7); 356 if (check_offset) 357 offset = check_offset; 358 } 359 } 360 break; 361 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */ 362 check_offset = 363 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 364 if (check_offset) { 365 rev = RBIOS8(check_offset); 366 if (rev == 2) { 367 check_offset = RBIOS16(check_offset + 0x9); 368 if (check_offset) 369 offset = check_offset; 370 } 371 } 372 break; 373 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */ 374 check_offset = 375 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 376 if (check_offset) { 377 while (RBIOS8(check_offset++)); 378 check_offset += 2; 379 if (check_offset) 380 offset = check_offset; 381 } 382 break; 383 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */ 384 check_offset = 385 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 386 if (check_offset) { 387 check_offset = RBIOS16(check_offset + 0x11); 388 if (check_offset) 389 offset = check_offset; 390 } 391 break; 392 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */ 393 check_offset = 394 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 395 if (check_offset) { 396 check_offset = RBIOS16(check_offset + 0x13); 397 if (check_offset) 398 offset = check_offset; 399 } 400 break; 401 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */ 402 check_offset = 403 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 404 if (check_offset) { 405 check_offset = RBIOS16(check_offset + 0x15); 406 if (check_offset) 407 offset = check_offset; 408 } 409 break; 410 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */ 411 check_offset = 412 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 413 if (check_offset) { 414 check_offset = RBIOS16(check_offset + 0x17); 415 if (check_offset) 416 offset = check_offset; 417 } 418 break; 419 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */ 420 check_offset = 421 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 422 if (check_offset) { 423 check_offset = RBIOS16(check_offset + 0x2); 424 if (check_offset) 425 offset = check_offset; 426 } 427 break; 428 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */ 429 check_offset = 430 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 431 if (check_offset) { 432 check_offset = RBIOS16(check_offset + 0x4); 433 if (check_offset) 434 offset = check_offset; 435 } 436 break; 437 default: 438 break; 439 } 440 441 return offset; 442 443} 444 445static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev, 446 int ddc_line) 447{ 448 struct radeon_i2c_bus_rec i2c; 449 450 if (ddc_line == RADEON_GPIOPAD_MASK) { 451 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; 452 i2c.mask_data_reg = RADEON_GPIOPAD_MASK; 453 i2c.a_clk_reg = RADEON_GPIOPAD_A; 454 i2c.a_data_reg = RADEON_GPIOPAD_A; 455 i2c.en_clk_reg = RADEON_GPIOPAD_EN; 456 i2c.en_data_reg = RADEON_GPIOPAD_EN; 457 i2c.y_clk_reg = RADEON_GPIOPAD_Y; 458 i2c.y_data_reg = RADEON_GPIOPAD_Y; 459 } else if (ddc_line == RADEON_MDGPIO_MASK) { 460 i2c.mask_clk_reg = RADEON_MDGPIO_MASK; 461 i2c.mask_data_reg = RADEON_MDGPIO_MASK; 462 i2c.a_clk_reg = RADEON_MDGPIO_A; 463 i2c.a_data_reg = RADEON_MDGPIO_A; 464 i2c.en_clk_reg = RADEON_MDGPIO_EN; 465 i2c.en_data_reg = RADEON_MDGPIO_EN; 466 i2c.y_clk_reg = RADEON_MDGPIO_Y; 467 i2c.y_data_reg = RADEON_MDGPIO_Y; 468 } else { 469 i2c.mask_clk_mask = RADEON_GPIO_EN_1; 470 i2c.mask_data_mask = RADEON_GPIO_EN_0; 471 i2c.a_clk_mask = RADEON_GPIO_A_1; 472 i2c.a_data_mask = RADEON_GPIO_A_0; 473 i2c.en_clk_mask = RADEON_GPIO_EN_1; 474 i2c.en_data_mask = RADEON_GPIO_EN_0; 475 i2c.y_clk_mask = RADEON_GPIO_Y_1; 476 i2c.y_data_mask = RADEON_GPIO_Y_0; 477 478 i2c.mask_clk_reg = ddc_line; 479 i2c.mask_data_reg = ddc_line; 480 i2c.a_clk_reg = ddc_line; 481 i2c.a_data_reg = ddc_line; 482 i2c.en_clk_reg = ddc_line; 483 i2c.en_data_reg = ddc_line; 484 i2c.y_clk_reg = ddc_line; 485 i2c.y_data_reg = ddc_line; 486 } 487 488 if (rdev->family < CHIP_R200) 489 i2c.hw_capable = false; 490 else { 491 switch (ddc_line) { 492 case RADEON_GPIO_VGA_DDC: 493 case RADEON_GPIO_DVI_DDC: 494 i2c.hw_capable = true; 495 break; 496 case RADEON_GPIO_MONID: 497 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work 498 * reliably on some pre-r4xx hardware; not sure why. 499 */ 500 i2c.hw_capable = false; 501 break; 502 default: 503 i2c.hw_capable = false; 504 break; 505 } 506 } 507 i2c.mm_i2c = false; 508 i2c.i2c_id = 0; 509 510 if (ddc_line) 511 i2c.valid = true; 512 else 513 i2c.valid = false; 514 515 return i2c; 516} 517 518bool radeon_combios_get_clock_info(struct drm_device *dev) 519{ 520 struct radeon_device *rdev = dev->dev_private; 521 uint16_t pll_info; 522 struct radeon_pll *p1pll = &rdev->clock.p1pll; 523 struct radeon_pll *p2pll = &rdev->clock.p2pll; 524 struct radeon_pll *spll = &rdev->clock.spll; 525 struct radeon_pll *mpll = &rdev->clock.mpll; 526 int8_t rev; 527 uint16_t sclk, mclk; 528 529 if (rdev->bios == NULL) 530 return false; 531 532 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE); 533 if (pll_info) { 534 rev = RBIOS8(pll_info); 535 536 /* pixel clocks */ 537 p1pll->reference_freq = RBIOS16(pll_info + 0xe); 538 p1pll->reference_div = RBIOS16(pll_info + 0x10); 539 p1pll->pll_out_min = RBIOS32(pll_info + 0x12); 540 p1pll->pll_out_max = RBIOS32(pll_info + 0x16); 541 542 if (rev > 9) { 543 p1pll->pll_in_min = RBIOS32(pll_info + 0x36); 544 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a); 545 } else { 546 p1pll->pll_in_min = 40; 547 p1pll->pll_in_max = 500; 548 } 549 *p2pll = *p1pll; 550 551 /* system clock */ 552 spll->reference_freq = RBIOS16(pll_info + 0x1a); 553 spll->reference_div = RBIOS16(pll_info + 0x1c); 554 spll->pll_out_min = RBIOS32(pll_info + 0x1e); 555 spll->pll_out_max = RBIOS32(pll_info + 0x22); 556 557 if (rev > 10) { 558 spll->pll_in_min = RBIOS32(pll_info + 0x48); 559 spll->pll_in_max = RBIOS32(pll_info + 0x4c); 560 } else { 561 /* ??? */ 562 spll->pll_in_min = 40; 563 spll->pll_in_max = 500; 564 } 565 566 /* memory clock */ 567 mpll->reference_freq = RBIOS16(pll_info + 0x26); 568 mpll->reference_div = RBIOS16(pll_info + 0x28); 569 mpll->pll_out_min = RBIOS32(pll_info + 0x2a); 570 mpll->pll_out_max = RBIOS32(pll_info + 0x2e); 571 572 if (rev > 10) { 573 mpll->pll_in_min = RBIOS32(pll_info + 0x5a); 574 mpll->pll_in_max = RBIOS32(pll_info + 0x5e); 575 } else { 576 /* ??? */ 577 mpll->pll_in_min = 40; 578 mpll->pll_in_max = 500; 579 } 580 581 /* default sclk/mclk */ 582 sclk = RBIOS16(pll_info + 0xa); 583 mclk = RBIOS16(pll_info + 0x8); 584 if (sclk == 0) 585 sclk = 200 * 100; 586 if (mclk == 0) 587 mclk = 200 * 100; 588 589 rdev->clock.default_sclk = sclk; 590 rdev->clock.default_mclk = mclk; 591 592 return true; 593 } 594 return false; 595} 596 597struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct 598 radeon_encoder 599 *encoder) 600{ 601 struct drm_device *dev = encoder->base.dev; 602 struct radeon_device *rdev = dev->dev_private; 603 uint16_t dac_info; 604 uint8_t rev, bg, dac; 605 struct radeon_encoder_primary_dac *p_dac = NULL; 606 607 if (rdev->bios == NULL) 608 return NULL; 609 610 /* check CRT table */ 611 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 612 if (dac_info) { 613 p_dac = 614 kzalloc(sizeof(struct radeon_encoder_primary_dac), 615 GFP_KERNEL); 616 617 if (!p_dac) 618 return NULL; 619 620 rev = RBIOS8(dac_info) & 0x3; 621 if (rev < 2) { 622 bg = RBIOS8(dac_info + 0x2) & 0xf; 623 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf; 624 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 625 } else { 626 bg = RBIOS8(dac_info + 0x2) & 0xf; 627 dac = RBIOS8(dac_info + 0x3) & 0xf; 628 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 629 } 630 631 } 632 633 return p_dac; 634} 635 636static enum radeon_tv_std 637radeon_combios_get_tv_info(struct radeon_encoder *encoder) 638{ 639 struct drm_device *dev = encoder->base.dev; 640 struct radeon_device *rdev = dev->dev_private; 641 uint16_t tv_info; 642 enum radeon_tv_std tv_std = TV_STD_NTSC; 643 644 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 645 if (tv_info) { 646 if (RBIOS8(tv_info + 6) == 'T') { 647 switch (RBIOS8(tv_info + 7) & 0xf) { 648 case 1: 649 tv_std = TV_STD_NTSC; 650 DRM_INFO("Default TV standard: NTSC\n"); 651 break; 652 case 2: 653 tv_std = TV_STD_PAL; 654 DRM_INFO("Default TV standard: PAL\n"); 655 break; 656 case 3: 657 tv_std = TV_STD_PAL_M; 658 DRM_INFO("Default TV standard: PAL-M\n"); 659 break; 660 case 4: 661 tv_std = TV_STD_PAL_60; 662 DRM_INFO("Default TV standard: PAL-60\n"); 663 break; 664 case 5: 665 tv_std = TV_STD_NTSC_J; 666 DRM_INFO("Default TV standard: NTSC-J\n"); 667 break; 668 case 6: 669 tv_std = TV_STD_SCART_PAL; 670 DRM_INFO("Default TV standard: SCART-PAL\n"); 671 break; 672 default: 673 tv_std = TV_STD_NTSC; 674 DRM_INFO 675 ("Unknown TV standard; defaulting to NTSC\n"); 676 break; 677 } 678 679 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) { 680 case 0: 681 DRM_INFO("29.498928713 MHz TV ref clk\n"); 682 break; 683 case 1: 684 DRM_INFO("28.636360000 MHz TV ref clk\n"); 685 break; 686 case 2: 687 DRM_INFO("14.318180000 MHz TV ref clk\n"); 688 break; 689 case 3: 690 DRM_INFO("27.000000000 MHz TV ref clk\n"); 691 break; 692 default: 693 break; 694 } 695 } 696 } 697 return tv_std; 698} 699 700static const uint32_t default_tvdac_adj[CHIP_LAST] = { 701 0x00000000, /* r100 */ 702 0x00280000, /* rv100 */ 703 0x00000000, /* rs100 */ 704 0x00880000, /* rv200 */ 705 0x00000000, /* rs200 */ 706 0x00000000, /* r200 */ 707 0x00770000, /* rv250 */ 708 0x00290000, /* rs300 */ 709 0x00560000, /* rv280 */ 710 0x00780000, /* r300 */ 711 0x00770000, /* r350 */ 712 0x00780000, /* rv350 */ 713 0x00780000, /* rv380 */ 714 0x01080000, /* r420 */ 715 0x01080000, /* r423 */ 716 0x01080000, /* rv410 */ 717 0x00780000, /* rs400 */ 718 0x00780000, /* rs480 */ 719}; 720 721static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev, 722 struct radeon_encoder_tv_dac *tv_dac) 723{ 724 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family]; 725 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250)) 726 tv_dac->ps2_tvdac_adj = 0x00880000; 727 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 728 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 729 return; 730} 731 732struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct 733 radeon_encoder 734 *encoder) 735{ 736 struct drm_device *dev = encoder->base.dev; 737 struct radeon_device *rdev = dev->dev_private; 738 uint16_t dac_info; 739 uint8_t rev, bg, dac; 740 struct radeon_encoder_tv_dac *tv_dac = NULL; 741 int found = 0; 742 743 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); 744 if (!tv_dac) 745 return NULL; 746 747 if (rdev->bios == NULL) 748 goto out; 749 750 /* first check TV table */ 751 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 752 if (dac_info) { 753 rev = RBIOS8(dac_info + 0x3); 754 if (rev > 4) { 755 bg = RBIOS8(dac_info + 0xc) & 0xf; 756 dac = RBIOS8(dac_info + 0xd) & 0xf; 757 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 758 759 bg = RBIOS8(dac_info + 0xe) & 0xf; 760 dac = RBIOS8(dac_info + 0xf) & 0xf; 761 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 762 763 bg = RBIOS8(dac_info + 0x10) & 0xf; 764 dac = RBIOS8(dac_info + 0x11) & 0xf; 765 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 766 found = 1; 767 } else if (rev > 1) { 768 bg = RBIOS8(dac_info + 0xc) & 0xf; 769 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf; 770 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 771 772 bg = RBIOS8(dac_info + 0xd) & 0xf; 773 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf; 774 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 775 776 bg = RBIOS8(dac_info + 0xe) & 0xf; 777 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf; 778 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 779 found = 1; 780 } 781 tv_dac->tv_std = radeon_combios_get_tv_info(encoder); 782 } 783 if (!found) { 784 /* then check CRT table */ 785 dac_info = 786 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 787 if (dac_info) { 788 rev = RBIOS8(dac_info) & 0x3; 789 if (rev < 2) { 790 bg = RBIOS8(dac_info + 0x3) & 0xf; 791 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf; 792 tv_dac->ps2_tvdac_adj = 793 (bg << 16) | (dac << 20); 794 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 795 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 796 found = 1; 797 } else { 798 bg = RBIOS8(dac_info + 0x4) & 0xf; 799 dac = RBIOS8(dac_info + 0x5) & 0xf; 800 tv_dac->ps2_tvdac_adj = 801 (bg << 16) | (dac << 20); 802 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 803 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 804 found = 1; 805 } 806 } else { 807 DRM_INFO("No TV DAC info found in BIOS\n"); 808 } 809 } 810 811out: 812 if (!found) /* fallback to defaults */ 813 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac); 814 815 return tv_dac; 816} 817 818static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct 819 radeon_device 820 *rdev) 821{ 822 struct radeon_encoder_lvds *lvds = NULL; 823 uint32_t fp_vert_stretch, fp_horz_stretch; 824 uint32_t ppll_div_sel, ppll_val; 825 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); 826 827 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); 828 829 if (!lvds) 830 return NULL; 831 832 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH); 833 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH); 834 835 /* These should be fail-safe defaults, fingers crossed */ 836 lvds->panel_pwr_delay = 200; 837 lvds->panel_vcc_delay = 2000; 838 839 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 840 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf; 841 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf; 842 843 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) 844 lvds->native_mode.vdisplay = 845 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >> 846 RADEON_VERT_PANEL_SHIFT) + 1; 847 else 848 lvds->native_mode.vdisplay = 849 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1; 850 851 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE) 852 lvds->native_mode.hdisplay = 853 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >> 854 RADEON_HORZ_PANEL_SHIFT) + 1) * 8; 855 else 856 lvds->native_mode.hdisplay = 857 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8; 858 859 if ((lvds->native_mode.hdisplay < 640) || 860 (lvds->native_mode.vdisplay < 480)) { 861 lvds->native_mode.hdisplay = 640; 862 lvds->native_mode.vdisplay = 480; 863 } 864 865 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; 866 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel); 867 if ((ppll_val & 0x000707ff) == 0x1bb) 868 lvds->use_bios_dividers = false; 869 else { 870 lvds->panel_ref_divider = 871 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; 872 lvds->panel_post_divider = (ppll_val >> 16) & 0x7; 873 lvds->panel_fb_divider = ppll_val & 0x7ff; 874 875 if ((lvds->panel_ref_divider != 0) && 876 (lvds->panel_fb_divider > 3)) 877 lvds->use_bios_dividers = true; 878 } 879 lvds->panel_vcc_delay = 200; 880 881 DRM_INFO("Panel info derived from registers\n"); 882 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 883 lvds->native_mode.vdisplay); 884 885 return lvds; 886} 887 888struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder 889 *encoder) 890{ 891 struct drm_device *dev = encoder->base.dev; 892 struct radeon_device *rdev = dev->dev_private; 893 uint16_t lcd_info; 894 uint32_t panel_setup; 895 char stmp[30]; 896 int tmp, i; 897 struct radeon_encoder_lvds *lvds = NULL; 898 899 if (rdev->bios == NULL) { 900 lvds = radeon_legacy_get_lvds_info_from_regs(rdev); 901 goto out; 902 } 903 904 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 905 906 if (lcd_info) { 907 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); 908 909 if (!lvds) 910 return NULL; 911 912 for (i = 0; i < 24; i++) 913 stmp[i] = RBIOS8(lcd_info + i + 1); 914 stmp[24] = 0; 915 916 DRM_INFO("Panel ID String: %s\n", stmp); 917 918 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19); 919 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b); 920 921 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 922 lvds->native_mode.vdisplay); 923 924 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c); 925 if (lvds->panel_vcc_delay > 2000 || lvds->panel_vcc_delay < 0) 926 lvds->panel_vcc_delay = 2000; 927 928 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24); 929 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf; 930 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf; 931 932 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e); 933 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30); 934 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31); 935 if ((lvds->panel_ref_divider != 0) && 936 (lvds->panel_fb_divider > 3)) 937 lvds->use_bios_dividers = true; 938 939 panel_setup = RBIOS32(lcd_info + 0x39); 940 lvds->lvds_gen_cntl = 0xff00; 941 if (panel_setup & 0x1) 942 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT; 943 944 if ((panel_setup >> 4) & 0x1) 945 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE; 946 947 switch ((panel_setup >> 8) & 0x7) { 948 case 0: 949 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM; 950 break; 951 case 1: 952 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY; 953 break; 954 case 2: 955 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY; 956 break; 957 default: 958 break; 959 } 960 961 if ((panel_setup >> 16) & 0x1) 962 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW; 963 964 if ((panel_setup >> 17) & 0x1) 965 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW; 966 967 if ((panel_setup >> 18) & 0x1) 968 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW; 969 970 if ((panel_setup >> 23) & 0x1) 971 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL; 972 973 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000); 974 975 for (i = 0; i < 32; i++) { 976 tmp = RBIOS16(lcd_info + 64 + i * 2); 977 if (tmp == 0) 978 break; 979 980 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) && 981 (RBIOS16(tmp + 2) == 982 lvds->native_mode.vdisplay)) { 983 lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8; 984 lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8; 985 lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) + 986 RBIOS16(tmp + 21)) * 8; 987 988 lvds->native_mode.vtotal = RBIOS16(tmp + 24); 989 lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff; 990 lvds->native_mode.vsync_end = 991 ((RBIOS16(tmp + 28) & 0xf800) >> 11) + 992 (RBIOS16(tmp + 28) & 0x7ff); 993 994 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10; 995 lvds->native_mode.flags = 0; 996 /* set crtc values */ 997 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); 998 999 } 1000 } 1001 } else { 1002 DRM_INFO("No panel info found in BIOS\n"); 1003 lvds = radeon_legacy_get_lvds_info_from_regs(rdev); 1004 } 1005out: 1006 if (lvds) 1007 encoder->native_mode = lvds->native_mode; 1008 return lvds; 1009} 1010 1011static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = { 1012 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */ 1013 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */ 1014 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */ 1015 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */ 1016 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */ 1017 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */ 1018 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */ 1019 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */ 1020 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */ 1021 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */ 1022 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */ 1023 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */ 1024 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */ 1025 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */ 1026 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */ 1027 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */ 1028 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */ 1029 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */ 1030}; 1031 1032bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 1033 struct radeon_encoder_int_tmds *tmds) 1034{ 1035 struct drm_device *dev = encoder->base.dev; 1036 struct radeon_device *rdev = dev->dev_private; 1037 int i; 1038 1039 for (i = 0; i < 4; i++) { 1040 tmds->tmds_pll[i].value = 1041 default_tmds_pll[rdev->family][i].value; 1042 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq; 1043 } 1044 1045 return true; 1046} 1047 1048bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 1049 struct radeon_encoder_int_tmds *tmds) 1050{ 1051 struct drm_device *dev = encoder->base.dev; 1052 struct radeon_device *rdev = dev->dev_private; 1053 uint16_t tmds_info; 1054 int i, n; 1055 uint8_t ver; 1056 1057 if (rdev->bios == NULL) 1058 return false; 1059 1060 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 1061 1062 if (tmds_info) { 1063 ver = RBIOS8(tmds_info); 1064 DRM_INFO("DFP table revision: %d\n", ver); 1065 if (ver == 3) { 1066 n = RBIOS8(tmds_info + 5) + 1; 1067 if (n > 4) 1068 n = 4; 1069 for (i = 0; i < n; i++) { 1070 tmds->tmds_pll[i].value = 1071 RBIOS32(tmds_info + i * 10 + 0x08); 1072 tmds->tmds_pll[i].freq = 1073 RBIOS16(tmds_info + i * 10 + 0x10); 1074 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n", 1075 tmds->tmds_pll[i].freq, 1076 tmds->tmds_pll[i].value); 1077 } 1078 } else if (ver == 4) { 1079 int stride = 0; 1080 n = RBIOS8(tmds_info + 5) + 1; 1081 if (n > 4) 1082 n = 4; 1083 for (i = 0; i < n; i++) { 1084 tmds->tmds_pll[i].value = 1085 RBIOS32(tmds_info + stride + 0x08); 1086 tmds->tmds_pll[i].freq = 1087 RBIOS16(tmds_info + stride + 0x10); 1088 if (i == 0) 1089 stride += 10; 1090 else 1091 stride += 6; 1092 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n", 1093 tmds->tmds_pll[i].freq, 1094 tmds->tmds_pll[i].value); 1095 } 1096 } 1097 } else { 1098 DRM_INFO("No TMDS info found in BIOS\n"); 1099 return false; 1100 } 1101 return true; 1102} 1103 1104bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 1105 struct radeon_encoder_ext_tmds *tmds) 1106{ 1107 struct drm_device *dev = encoder->base.dev; 1108 struct radeon_device *rdev = dev->dev_private; 1109 struct radeon_i2c_bus_rec i2c_bus; 1110 1111 /* default for macs */ 1112 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1113 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1114 1115 /* XXX some macs have duallink chips */ 1116 switch (rdev->mode_info.connector_table) { 1117 case CT_POWERBOOK_EXTERNAL: 1118 case CT_MINI_EXTERNAL: 1119 default: 1120 tmds->dvo_chip = DVO_SIL164; 1121 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1122 break; 1123 } 1124 1125 return true; 1126} 1127 1128bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 1129 struct radeon_encoder_ext_tmds *tmds) 1130{ 1131 struct drm_device *dev = encoder->base.dev; 1132 struct radeon_device *rdev = dev->dev_private; 1133 uint16_t offset; 1134 uint8_t ver, id, blocks, clk, data; 1135 int i; 1136 enum radeon_combios_ddc gpio; 1137 struct radeon_i2c_bus_rec i2c_bus; 1138 1139 if (rdev->bios == NULL) 1140 return false; 1141 1142 tmds->i2c_bus = NULL; 1143 if (rdev->flags & RADEON_IS_IGP) { 1144 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE); 1145 if (offset) { 1146 ver = RBIOS8(offset); 1147 DRM_INFO("GPIO Table revision: %d\n", ver); 1148 blocks = RBIOS8(offset + 2); 1149 for (i = 0; i < blocks; i++) { 1150 id = RBIOS8(offset + 3 + (i * 5) + 0); 1151 if (id == 136) { 1152 clk = RBIOS8(offset + 3 + (i * 5) + 3); 1153 data = RBIOS8(offset + 3 + (i * 5) + 4); 1154 i2c_bus.valid = true; 1155 i2c_bus.mask_clk_mask = (1 << clk); 1156 i2c_bus.mask_data_mask = (1 << data); 1157 i2c_bus.a_clk_mask = (1 << clk); 1158 i2c_bus.a_data_mask = (1 << data); 1159 i2c_bus.en_clk_mask = (1 << clk); 1160 i2c_bus.en_data_mask = (1 << data); 1161 i2c_bus.y_clk_mask = (1 << clk); 1162 i2c_bus.y_data_mask = (1 << data); 1163 i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK; 1164 i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK; 1165 i2c_bus.a_clk_reg = RADEON_GPIOPAD_A; 1166 i2c_bus.a_data_reg = RADEON_GPIOPAD_A; 1167 i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN; 1168 i2c_bus.en_data_reg = RADEON_GPIOPAD_EN; 1169 i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y; 1170 i2c_bus.y_data_reg = RADEON_GPIOPAD_Y; 1171 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1172 tmds->dvo_chip = DVO_SIL164; 1173 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1174 break; 1175 } 1176 } 1177 } 1178 } else { 1179 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 1180 if (offset) { 1181 ver = RBIOS8(offset); 1182 DRM_INFO("External TMDS Table revision: %d\n", ver); 1183 tmds->slave_addr = RBIOS8(offset + 4 + 2); 1184 tmds->slave_addr >>= 1; /* 7 bit addressing */ 1185 gpio = RBIOS8(offset + 4 + 3); 1186 switch (gpio) { 1187 case DDC_MONID: 1188 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1189 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1190 break; 1191 case DDC_DVI: 1192 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1193 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1194 break; 1195 case DDC_VGA: 1196 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1197 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1198 break; 1199 case DDC_CRT2: 1200 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */ 1201 if (rdev->family >= CHIP_R300) 1202 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1203 else 1204 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1205 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1206 break; 1207 case DDC_LCD: /* MM i2c */ 1208 DRM_ERROR("MM i2c requires hw i2c engine\n"); 1209 break; 1210 default: 1211 DRM_ERROR("Unsupported gpio %d\n", gpio); 1212 break; 1213 } 1214 } 1215 } 1216 1217 if (!tmds->i2c_bus) { 1218 DRM_INFO("No valid Ext TMDS info found in BIOS\n"); 1219 return false; 1220 } 1221 1222 return true; 1223} 1224 1225bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) 1226{ 1227 struct radeon_device *rdev = dev->dev_private; 1228 struct radeon_i2c_bus_rec ddc_i2c; 1229 1230 rdev->mode_info.connector_table = radeon_connector_table; 1231 if (rdev->mode_info.connector_table == CT_NONE) { 1232#ifdef CONFIG_PPC_PMAC 1233 if (machine_is_compatible("PowerBook3,3")) { 1234 /* powerbook with VGA */ 1235 rdev->mode_info.connector_table = CT_POWERBOOK_VGA; 1236 } else if (machine_is_compatible("PowerBook3,4") || 1237 machine_is_compatible("PowerBook3,5")) { 1238 /* powerbook with internal tmds */ 1239 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL; 1240 } else if (machine_is_compatible("PowerBook5,1") || 1241 machine_is_compatible("PowerBook5,2") || 1242 machine_is_compatible("PowerBook5,3") || 1243 machine_is_compatible("PowerBook5,4") || 1244 machine_is_compatible("PowerBook5,5")) { 1245 /* powerbook with external single link tmds (sil164) */ 1246 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1247 } else if (machine_is_compatible("PowerBook5,6")) { 1248 /* powerbook with external dual or single link tmds */ 1249 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1250 } else if (machine_is_compatible("PowerBook5,7") || 1251 machine_is_compatible("PowerBook5,8") || 1252 machine_is_compatible("PowerBook5,9")) { 1253 /* PowerBook6,2 ? */ 1254 /* powerbook with external dual link tmds (sil1178?) */ 1255 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1256 } else if (machine_is_compatible("PowerBook4,1") || 1257 machine_is_compatible("PowerBook4,2") || 1258 machine_is_compatible("PowerBook4,3") || 1259 machine_is_compatible("PowerBook6,3") || 1260 machine_is_compatible("PowerBook6,5") || 1261 machine_is_compatible("PowerBook6,7")) { 1262 /* ibook */ 1263 rdev->mode_info.connector_table = CT_IBOOK; 1264 } else if (machine_is_compatible("PowerMac4,4")) { 1265 /* emac */ 1266 rdev->mode_info.connector_table = CT_EMAC; 1267 } else if (machine_is_compatible("PowerMac10,1")) { 1268 /* mini with internal tmds */ 1269 rdev->mode_info.connector_table = CT_MINI_INTERNAL; 1270 } else if (machine_is_compatible("PowerMac10,2")) { 1271 /* mini with external tmds */ 1272 rdev->mode_info.connector_table = CT_MINI_EXTERNAL; 1273 } else if (machine_is_compatible("PowerMac12,1")) { 1274 /* PowerMac8,1 ? */ 1275 /* imac g5 isight */ 1276 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT; 1277 } else 1278#endif /* CONFIG_PPC_PMAC */ 1279 rdev->mode_info.connector_table = CT_GENERIC; 1280 } 1281 1282 switch (rdev->mode_info.connector_table) { 1283 case CT_GENERIC: 1284 DRM_INFO("Connector Table: %d (generic)\n", 1285 rdev->mode_info.connector_table); 1286 /* these are the most common settings */ 1287 if (rdev->flags & RADEON_SINGLE_CRTC) { 1288 /* VGA - primary dac */ 1289 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1290 radeon_add_legacy_encoder(dev, 1291 radeon_get_encoder_id(dev, 1292 ATOM_DEVICE_CRT1_SUPPORT, 1293 1), 1294 ATOM_DEVICE_CRT1_SUPPORT); 1295 radeon_add_legacy_connector(dev, 0, 1296 ATOM_DEVICE_CRT1_SUPPORT, 1297 DRM_MODE_CONNECTOR_VGA, 1298 &ddc_i2c, 1299 CONNECTOR_OBJECT_ID_VGA); 1300 } else if (rdev->flags & RADEON_IS_MOBILITY) { 1301 /* LVDS */ 1302 ddc_i2c = combios_setup_i2c_bus(rdev, 0); 1303 radeon_add_legacy_encoder(dev, 1304 radeon_get_encoder_id(dev, 1305 ATOM_DEVICE_LCD1_SUPPORT, 1306 0), 1307 ATOM_DEVICE_LCD1_SUPPORT); 1308 radeon_add_legacy_connector(dev, 0, 1309 ATOM_DEVICE_LCD1_SUPPORT, 1310 DRM_MODE_CONNECTOR_LVDS, 1311 &ddc_i2c, 1312 CONNECTOR_OBJECT_ID_LVDS); 1313 1314 /* VGA - primary dac */ 1315 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1316 radeon_add_legacy_encoder(dev, 1317 radeon_get_encoder_id(dev, 1318 ATOM_DEVICE_CRT1_SUPPORT, 1319 1), 1320 ATOM_DEVICE_CRT1_SUPPORT); 1321 radeon_add_legacy_connector(dev, 1, 1322 ATOM_DEVICE_CRT1_SUPPORT, 1323 DRM_MODE_CONNECTOR_VGA, 1324 &ddc_i2c, 1325 CONNECTOR_OBJECT_ID_VGA); 1326 } else { 1327 /* DVI-I - tv dac, int tmds */ 1328 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1329 radeon_add_legacy_encoder(dev, 1330 radeon_get_encoder_id(dev, 1331 ATOM_DEVICE_DFP1_SUPPORT, 1332 0), 1333 ATOM_DEVICE_DFP1_SUPPORT); 1334 radeon_add_legacy_encoder(dev, 1335 radeon_get_encoder_id(dev, 1336 ATOM_DEVICE_CRT2_SUPPORT, 1337 2), 1338 ATOM_DEVICE_CRT2_SUPPORT); 1339 radeon_add_legacy_connector(dev, 0, 1340 ATOM_DEVICE_DFP1_SUPPORT | 1341 ATOM_DEVICE_CRT2_SUPPORT, 1342 DRM_MODE_CONNECTOR_DVII, 1343 &ddc_i2c, 1344 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I); 1345 1346 /* VGA - primary dac */ 1347 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1348 radeon_add_legacy_encoder(dev, 1349 radeon_get_encoder_id(dev, 1350 ATOM_DEVICE_CRT1_SUPPORT, 1351 1), 1352 ATOM_DEVICE_CRT1_SUPPORT); 1353 radeon_add_legacy_connector(dev, 1, 1354 ATOM_DEVICE_CRT1_SUPPORT, 1355 DRM_MODE_CONNECTOR_VGA, 1356 &ddc_i2c, 1357 CONNECTOR_OBJECT_ID_VGA); 1358 } 1359 1360 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 1361 /* TV - tv dac */ 1362 radeon_add_legacy_encoder(dev, 1363 radeon_get_encoder_id(dev, 1364 ATOM_DEVICE_TV1_SUPPORT, 1365 2), 1366 ATOM_DEVICE_TV1_SUPPORT); 1367 radeon_add_legacy_connector(dev, 2, 1368 ATOM_DEVICE_TV1_SUPPORT, 1369 DRM_MODE_CONNECTOR_SVIDEO, 1370 &ddc_i2c, 1371 CONNECTOR_OBJECT_ID_SVIDEO); 1372 } 1373 break; 1374 case CT_IBOOK: 1375 DRM_INFO("Connector Table: %d (ibook)\n", 1376 rdev->mode_info.connector_table); 1377 /* LVDS */ 1378 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1379 radeon_add_legacy_encoder(dev, 1380 radeon_get_encoder_id(dev, 1381 ATOM_DEVICE_LCD1_SUPPORT, 1382 0), 1383 ATOM_DEVICE_LCD1_SUPPORT); 1384 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1385 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1386 CONNECTOR_OBJECT_ID_LVDS); 1387 /* VGA - TV DAC */ 1388 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1389 radeon_add_legacy_encoder(dev, 1390 radeon_get_encoder_id(dev, 1391 ATOM_DEVICE_CRT2_SUPPORT, 1392 2), 1393 ATOM_DEVICE_CRT2_SUPPORT); 1394 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1395 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1396 CONNECTOR_OBJECT_ID_VGA); 1397 /* TV - TV DAC */ 1398 radeon_add_legacy_encoder(dev, 1399 radeon_get_encoder_id(dev, 1400 ATOM_DEVICE_TV1_SUPPORT, 1401 2), 1402 ATOM_DEVICE_TV1_SUPPORT); 1403 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1404 DRM_MODE_CONNECTOR_SVIDEO, 1405 &ddc_i2c, 1406 CONNECTOR_OBJECT_ID_SVIDEO); 1407 break; 1408 case CT_POWERBOOK_EXTERNAL: 1409 DRM_INFO("Connector Table: %d (powerbook external tmds)\n", 1410 rdev->mode_info.connector_table); 1411 /* LVDS */ 1412 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1413 radeon_add_legacy_encoder(dev, 1414 radeon_get_encoder_id(dev, 1415 ATOM_DEVICE_LCD1_SUPPORT, 1416 0), 1417 ATOM_DEVICE_LCD1_SUPPORT); 1418 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1419 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1420 CONNECTOR_OBJECT_ID_LVDS); 1421 /* DVI-I - primary dac, ext tmds */ 1422 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1423 radeon_add_legacy_encoder(dev, 1424 radeon_get_encoder_id(dev, 1425 ATOM_DEVICE_DFP2_SUPPORT, 1426 0), 1427 ATOM_DEVICE_DFP2_SUPPORT); 1428 radeon_add_legacy_encoder(dev, 1429 radeon_get_encoder_id(dev, 1430 ATOM_DEVICE_CRT1_SUPPORT, 1431 1), 1432 ATOM_DEVICE_CRT1_SUPPORT); 1433 /* XXX some are SL */ 1434 radeon_add_legacy_connector(dev, 1, 1435 ATOM_DEVICE_DFP2_SUPPORT | 1436 ATOM_DEVICE_CRT1_SUPPORT, 1437 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1438 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I); 1439 /* TV - TV DAC */ 1440 radeon_add_legacy_encoder(dev, 1441 radeon_get_encoder_id(dev, 1442 ATOM_DEVICE_TV1_SUPPORT, 1443 2), 1444 ATOM_DEVICE_TV1_SUPPORT); 1445 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1446 DRM_MODE_CONNECTOR_SVIDEO, 1447 &ddc_i2c, 1448 CONNECTOR_OBJECT_ID_SVIDEO); 1449 break; 1450 case CT_POWERBOOK_INTERNAL: 1451 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n", 1452 rdev->mode_info.connector_table); 1453 /* LVDS */ 1454 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1455 radeon_add_legacy_encoder(dev, 1456 radeon_get_encoder_id(dev, 1457 ATOM_DEVICE_LCD1_SUPPORT, 1458 0), 1459 ATOM_DEVICE_LCD1_SUPPORT); 1460 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1461 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1462 CONNECTOR_OBJECT_ID_LVDS); 1463 /* DVI-I - primary dac, int tmds */ 1464 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1465 radeon_add_legacy_encoder(dev, 1466 radeon_get_encoder_id(dev, 1467 ATOM_DEVICE_DFP1_SUPPORT, 1468 0), 1469 ATOM_DEVICE_DFP1_SUPPORT); 1470 radeon_add_legacy_encoder(dev, 1471 radeon_get_encoder_id(dev, 1472 ATOM_DEVICE_CRT1_SUPPORT, 1473 1), 1474 ATOM_DEVICE_CRT1_SUPPORT); 1475 radeon_add_legacy_connector(dev, 1, 1476 ATOM_DEVICE_DFP1_SUPPORT | 1477 ATOM_DEVICE_CRT1_SUPPORT, 1478 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1479 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I); 1480 /* TV - TV DAC */ 1481 radeon_add_legacy_encoder(dev, 1482 radeon_get_encoder_id(dev, 1483 ATOM_DEVICE_TV1_SUPPORT, 1484 2), 1485 ATOM_DEVICE_TV1_SUPPORT); 1486 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1487 DRM_MODE_CONNECTOR_SVIDEO, 1488 &ddc_i2c, 1489 CONNECTOR_OBJECT_ID_SVIDEO); 1490 break; 1491 case CT_POWERBOOK_VGA: 1492 DRM_INFO("Connector Table: %d (powerbook vga)\n", 1493 rdev->mode_info.connector_table); 1494 /* LVDS */ 1495 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1496 radeon_add_legacy_encoder(dev, 1497 radeon_get_encoder_id(dev, 1498 ATOM_DEVICE_LCD1_SUPPORT, 1499 0), 1500 ATOM_DEVICE_LCD1_SUPPORT); 1501 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1502 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1503 CONNECTOR_OBJECT_ID_LVDS); 1504 /* VGA - primary dac */ 1505 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1506 radeon_add_legacy_encoder(dev, 1507 radeon_get_encoder_id(dev, 1508 ATOM_DEVICE_CRT1_SUPPORT, 1509 1), 1510 ATOM_DEVICE_CRT1_SUPPORT); 1511 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, 1512 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1513 CONNECTOR_OBJECT_ID_VGA); 1514 /* TV - TV DAC */ 1515 radeon_add_legacy_encoder(dev, 1516 radeon_get_encoder_id(dev, 1517 ATOM_DEVICE_TV1_SUPPORT, 1518 2), 1519 ATOM_DEVICE_TV1_SUPPORT); 1520 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1521 DRM_MODE_CONNECTOR_SVIDEO, 1522 &ddc_i2c, 1523 CONNECTOR_OBJECT_ID_SVIDEO); 1524 break; 1525 case CT_MINI_EXTERNAL: 1526 DRM_INFO("Connector Table: %d (mini external tmds)\n", 1527 rdev->mode_info.connector_table); 1528 /* DVI-I - tv dac, ext tmds */ 1529 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1530 radeon_add_legacy_encoder(dev, 1531 radeon_get_encoder_id(dev, 1532 ATOM_DEVICE_DFP2_SUPPORT, 1533 0), 1534 ATOM_DEVICE_DFP2_SUPPORT); 1535 radeon_add_legacy_encoder(dev, 1536 radeon_get_encoder_id(dev, 1537 ATOM_DEVICE_CRT2_SUPPORT, 1538 2), 1539 ATOM_DEVICE_CRT2_SUPPORT); 1540 /* XXX are any DL? */ 1541 radeon_add_legacy_connector(dev, 0, 1542 ATOM_DEVICE_DFP2_SUPPORT | 1543 ATOM_DEVICE_CRT2_SUPPORT, 1544 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1545 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I); 1546 /* TV - TV DAC */ 1547 radeon_add_legacy_encoder(dev, 1548 radeon_get_encoder_id(dev, 1549 ATOM_DEVICE_TV1_SUPPORT, 1550 2), 1551 ATOM_DEVICE_TV1_SUPPORT); 1552 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1553 DRM_MODE_CONNECTOR_SVIDEO, 1554 &ddc_i2c, 1555 CONNECTOR_OBJECT_ID_SVIDEO); 1556 break; 1557 case CT_MINI_INTERNAL: 1558 DRM_INFO("Connector Table: %d (mini internal tmds)\n", 1559 rdev->mode_info.connector_table); 1560 /* DVI-I - tv dac, int tmds */ 1561 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1562 radeon_add_legacy_encoder(dev, 1563 radeon_get_encoder_id(dev, 1564 ATOM_DEVICE_DFP1_SUPPORT, 1565 0), 1566 ATOM_DEVICE_DFP1_SUPPORT); 1567 radeon_add_legacy_encoder(dev, 1568 radeon_get_encoder_id(dev, 1569 ATOM_DEVICE_CRT2_SUPPORT, 1570 2), 1571 ATOM_DEVICE_CRT2_SUPPORT); 1572 radeon_add_legacy_connector(dev, 0, 1573 ATOM_DEVICE_DFP1_SUPPORT | 1574 ATOM_DEVICE_CRT2_SUPPORT, 1575 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1576 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I); 1577 /* TV - TV DAC */ 1578 radeon_add_legacy_encoder(dev, 1579 radeon_get_encoder_id(dev, 1580 ATOM_DEVICE_TV1_SUPPORT, 1581 2), 1582 ATOM_DEVICE_TV1_SUPPORT); 1583 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1584 DRM_MODE_CONNECTOR_SVIDEO, 1585 &ddc_i2c, 1586 CONNECTOR_OBJECT_ID_SVIDEO); 1587 break; 1588 case CT_IMAC_G5_ISIGHT: 1589 DRM_INFO("Connector Table: %d (imac g5 isight)\n", 1590 rdev->mode_info.connector_table); 1591 /* DVI-D - int tmds */ 1592 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1593 radeon_add_legacy_encoder(dev, 1594 radeon_get_encoder_id(dev, 1595 ATOM_DEVICE_DFP1_SUPPORT, 1596 0), 1597 ATOM_DEVICE_DFP1_SUPPORT); 1598 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT, 1599 DRM_MODE_CONNECTOR_DVID, &ddc_i2c, 1600 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D); 1601 /* VGA - tv dac */ 1602 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1603 radeon_add_legacy_encoder(dev, 1604 radeon_get_encoder_id(dev, 1605 ATOM_DEVICE_CRT2_SUPPORT, 1606 2), 1607 ATOM_DEVICE_CRT2_SUPPORT); 1608 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1609 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1610 CONNECTOR_OBJECT_ID_VGA); 1611 /* TV - TV DAC */ 1612 radeon_add_legacy_encoder(dev, 1613 radeon_get_encoder_id(dev, 1614 ATOM_DEVICE_TV1_SUPPORT, 1615 2), 1616 ATOM_DEVICE_TV1_SUPPORT); 1617 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1618 DRM_MODE_CONNECTOR_SVIDEO, 1619 &ddc_i2c, 1620 CONNECTOR_OBJECT_ID_SVIDEO); 1621 break; 1622 case CT_EMAC: 1623 DRM_INFO("Connector Table: %d (emac)\n", 1624 rdev->mode_info.connector_table); 1625 /* VGA - primary dac */ 1626 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1627 radeon_add_legacy_encoder(dev, 1628 radeon_get_encoder_id(dev, 1629 ATOM_DEVICE_CRT1_SUPPORT, 1630 1), 1631 ATOM_DEVICE_CRT1_SUPPORT); 1632 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, 1633 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1634 CONNECTOR_OBJECT_ID_VGA); 1635 /* VGA - tv dac */ 1636 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1637 radeon_add_legacy_encoder(dev, 1638 radeon_get_encoder_id(dev, 1639 ATOM_DEVICE_CRT2_SUPPORT, 1640 2), 1641 ATOM_DEVICE_CRT2_SUPPORT); 1642 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1643 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1644 CONNECTOR_OBJECT_ID_VGA); 1645 /* TV - TV DAC */ 1646 radeon_add_legacy_encoder(dev, 1647 radeon_get_encoder_id(dev, 1648 ATOM_DEVICE_TV1_SUPPORT, 1649 2), 1650 ATOM_DEVICE_TV1_SUPPORT); 1651 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1652 DRM_MODE_CONNECTOR_SVIDEO, 1653 &ddc_i2c, 1654 CONNECTOR_OBJECT_ID_SVIDEO); 1655 break; 1656 default: 1657 DRM_INFO("Connector table: %d (invalid)\n", 1658 rdev->mode_info.connector_table); 1659 return false; 1660 } 1661 1662 radeon_link_encoder_connector(dev); 1663 1664 return true; 1665} 1666 1667static bool radeon_apply_legacy_quirks(struct drm_device *dev, 1668 int bios_index, 1669 enum radeon_combios_connector 1670 *legacy_connector, 1671 struct radeon_i2c_bus_rec *ddc_i2c) 1672{ 1673 struct radeon_device *rdev = dev->dev_private; 1674 1675 /* XPRESS DDC quirks */ 1676 if ((rdev->family == CHIP_RS400 || 1677 rdev->family == CHIP_RS480) && 1678 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) 1679 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1680 else if ((rdev->family == CHIP_RS400 || 1681 rdev->family == CHIP_RS480) && 1682 ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) { 1683 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK); 1684 ddc_i2c->mask_clk_mask = (0x20 << 8); 1685 ddc_i2c->mask_data_mask = 0x80; 1686 ddc_i2c->a_clk_mask = (0x20 << 8); 1687 ddc_i2c->a_data_mask = 0x80; 1688 ddc_i2c->en_clk_mask = (0x20 << 8); 1689 ddc_i2c->en_data_mask = 0x80; 1690 ddc_i2c->y_clk_mask = (0x20 << 8); 1691 ddc_i2c->y_data_mask = 0x80; 1692 } 1693 1694 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */ 1695 if ((rdev->family >= CHIP_R300) && 1696 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) 1697 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1698 1699 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, 1700 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ 1701 if (dev->pdev->device == 0x515e && 1702 dev->pdev->subsystem_vendor == 0x1014) { 1703 if (*legacy_connector == CONNECTOR_CRT_LEGACY && 1704 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) 1705 return false; 1706 } 1707 1708 /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */ 1709 if (dev->pdev->device == 0x5159 && 1710 dev->pdev->subsystem_vendor == 0x1002 && 1711 dev->pdev->subsystem_device == 0x013a) { 1712 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY) 1713 *legacy_connector = CONNECTOR_CRT_LEGACY; 1714 1715 } 1716 1717 /* X300 card with extra non-existent DVI port */ 1718 if (dev->pdev->device == 0x5B60 && 1719 dev->pdev->subsystem_vendor == 0x17af && 1720 dev->pdev->subsystem_device == 0x201e && bios_index == 2) { 1721 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY) 1722 return false; 1723 } 1724 1725 return true; 1726} 1727 1728static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev) 1729{ 1730 /* Acer 5102 has non-existent TV port */ 1731 if (dev->pdev->device == 0x5975 && 1732 dev->pdev->subsystem_vendor == 0x1025 && 1733 dev->pdev->subsystem_device == 0x009f) 1734 return false; 1735 1736 /* HP dc5750 has non-existent TV port */ 1737 if (dev->pdev->device == 0x5974 && 1738 dev->pdev->subsystem_vendor == 0x103c && 1739 dev->pdev->subsystem_device == 0x280a) 1740 return false; 1741 1742 /* MSI S270 has non-existent TV port */ 1743 if (dev->pdev->device == 0x5955 && 1744 dev->pdev->subsystem_vendor == 0x1462 && 1745 dev->pdev->subsystem_device == 0x0131) 1746 return false; 1747 1748 return true; 1749} 1750 1751static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d) 1752{ 1753 struct radeon_device *rdev = dev->dev_private; 1754 uint32_t ext_tmds_info; 1755 1756 if (rdev->flags & RADEON_IS_IGP) { 1757 if (is_dvi_d) 1758 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 1759 else 1760 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 1761 } 1762 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 1763 if (ext_tmds_info) { 1764 uint8_t rev = RBIOS8(ext_tmds_info); 1765 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5); 1766 if (rev >= 3) { 1767 if (is_dvi_d) 1768 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 1769 else 1770 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 1771 } else { 1772 if (flags & 1) { 1773 if (is_dvi_d) 1774 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 1775 else 1776 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 1777 } 1778 } 1779 } 1780 if (is_dvi_d) 1781 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 1782 else 1783 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 1784} 1785 1786bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) 1787{ 1788 struct radeon_device *rdev = dev->dev_private; 1789 uint32_t conn_info, entry, devices; 1790 uint16_t tmp, connector_object_id; 1791 enum radeon_combios_ddc ddc_type; 1792 enum radeon_combios_connector connector; 1793 int i = 0; 1794 struct radeon_i2c_bus_rec ddc_i2c; 1795 1796 if (rdev->bios == NULL) 1797 return false; 1798 1799 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE); 1800 if (conn_info) { 1801 for (i = 0; i < 4; i++) { 1802 entry = conn_info + 2 + i * 2; 1803 1804 if (!RBIOS16(entry)) 1805 break; 1806 1807 tmp = RBIOS16(entry); 1808 1809 connector = (tmp >> 12) & 0xf; 1810 1811 ddc_type = (tmp >> 8) & 0xf; 1812 switch (ddc_type) { 1813 case DDC_MONID: 1814 ddc_i2c = 1815 combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1816 break; 1817 case DDC_DVI: 1818 ddc_i2c = 1819 combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1820 break; 1821 case DDC_VGA: 1822 ddc_i2c = 1823 combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1824 break; 1825 case DDC_CRT2: 1826 ddc_i2c = 1827 combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1828 break; 1829 default: 1830 break; 1831 } 1832 1833 if (!radeon_apply_legacy_quirks(dev, i, &connector, 1834 &ddc_i2c)) 1835 continue; 1836 1837 switch (connector) { 1838 case CONNECTOR_PROPRIETARY_LEGACY: 1839 if ((tmp >> 4) & 0x1) 1840 devices = ATOM_DEVICE_DFP2_SUPPORT; 1841 else 1842 devices = ATOM_DEVICE_DFP1_SUPPORT; 1843 radeon_add_legacy_encoder(dev, 1844 radeon_get_encoder_id 1845 (dev, devices, 0), 1846 devices); 1847 radeon_add_legacy_connector(dev, i, devices, 1848 legacy_connector_convert 1849 [connector], 1850 &ddc_i2c, 1851 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D); 1852 break; 1853 case CONNECTOR_CRT_LEGACY: 1854 if (tmp & 0x1) { 1855 devices = ATOM_DEVICE_CRT2_SUPPORT; 1856 radeon_add_legacy_encoder(dev, 1857 radeon_get_encoder_id 1858 (dev, 1859 ATOM_DEVICE_CRT2_SUPPORT, 1860 2), 1861 ATOM_DEVICE_CRT2_SUPPORT); 1862 } else { 1863 devices = ATOM_DEVICE_CRT1_SUPPORT; 1864 radeon_add_legacy_encoder(dev, 1865 radeon_get_encoder_id 1866 (dev, 1867 ATOM_DEVICE_CRT1_SUPPORT, 1868 1), 1869 ATOM_DEVICE_CRT1_SUPPORT); 1870 } 1871 radeon_add_legacy_connector(dev, 1872 i, 1873 devices, 1874 legacy_connector_convert 1875 [connector], 1876 &ddc_i2c, 1877 CONNECTOR_OBJECT_ID_VGA); 1878 break; 1879 case CONNECTOR_DVI_I_LEGACY: 1880 devices = 0; 1881 if (tmp & 0x1) { 1882 devices |= ATOM_DEVICE_CRT2_SUPPORT; 1883 radeon_add_legacy_encoder(dev, 1884 radeon_get_encoder_id 1885 (dev, 1886 ATOM_DEVICE_CRT2_SUPPORT, 1887 2), 1888 ATOM_DEVICE_CRT2_SUPPORT); 1889 } else { 1890 devices |= ATOM_DEVICE_CRT1_SUPPORT; 1891 radeon_add_legacy_encoder(dev, 1892 radeon_get_encoder_id 1893 (dev, 1894 ATOM_DEVICE_CRT1_SUPPORT, 1895 1), 1896 ATOM_DEVICE_CRT1_SUPPORT); 1897 } 1898 if ((tmp >> 4) & 0x1) { 1899 devices |= ATOM_DEVICE_DFP2_SUPPORT; 1900 radeon_add_legacy_encoder(dev, 1901 radeon_get_encoder_id 1902 (dev, 1903 ATOM_DEVICE_DFP2_SUPPORT, 1904 0), 1905 ATOM_DEVICE_DFP2_SUPPORT); 1906 connector_object_id = combios_check_dl_dvi(dev, 0); 1907 } else { 1908 devices |= ATOM_DEVICE_DFP1_SUPPORT; 1909 radeon_add_legacy_encoder(dev, 1910 radeon_get_encoder_id 1911 (dev, 1912 ATOM_DEVICE_DFP1_SUPPORT, 1913 0), 1914 ATOM_DEVICE_DFP1_SUPPORT); 1915 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 1916 } 1917 radeon_add_legacy_connector(dev, 1918 i, 1919 devices, 1920 legacy_connector_convert 1921 [connector], 1922 &ddc_i2c, 1923 connector_object_id); 1924 break; 1925 case CONNECTOR_DVI_D_LEGACY: 1926 if ((tmp >> 4) & 0x1) { 1927 devices = ATOM_DEVICE_DFP2_SUPPORT; 1928 connector_object_id = combios_check_dl_dvi(dev, 1); 1929 } else { 1930 devices = ATOM_DEVICE_DFP1_SUPPORT; 1931 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 1932 } 1933 radeon_add_legacy_encoder(dev, 1934 radeon_get_encoder_id 1935 (dev, devices, 0), 1936 devices); 1937 radeon_add_legacy_connector(dev, i, devices, 1938 legacy_connector_convert 1939 [connector], 1940 &ddc_i2c, 1941 connector_object_id); 1942 break; 1943 case CONNECTOR_CTV_LEGACY: 1944 case CONNECTOR_STV_LEGACY: 1945 radeon_add_legacy_encoder(dev, 1946 radeon_get_encoder_id 1947 (dev, 1948 ATOM_DEVICE_TV1_SUPPORT, 1949 2), 1950 ATOM_DEVICE_TV1_SUPPORT); 1951 radeon_add_legacy_connector(dev, i, 1952 ATOM_DEVICE_TV1_SUPPORT, 1953 legacy_connector_convert 1954 [connector], 1955 &ddc_i2c, 1956 CONNECTOR_OBJECT_ID_SVIDEO); 1957 break; 1958 default: 1959 DRM_ERROR("Unknown connector type: %d\n", 1960 connector); 1961 continue; 1962 } 1963 1964 } 1965 } else { 1966 uint16_t tmds_info = 1967 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 1968 if (tmds_info) { 1969 DRM_DEBUG("Found DFP table, assuming DVI connector\n"); 1970 1971 radeon_add_legacy_encoder(dev, 1972 radeon_get_encoder_id(dev, 1973 ATOM_DEVICE_CRT1_SUPPORT, 1974 1), 1975 ATOM_DEVICE_CRT1_SUPPORT); 1976 radeon_add_legacy_encoder(dev, 1977 radeon_get_encoder_id(dev, 1978 ATOM_DEVICE_DFP1_SUPPORT, 1979 0), 1980 ATOM_DEVICE_DFP1_SUPPORT); 1981 1982 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1983 radeon_add_legacy_connector(dev, 1984 0, 1985 ATOM_DEVICE_CRT1_SUPPORT | 1986 ATOM_DEVICE_DFP1_SUPPORT, 1987 DRM_MODE_CONNECTOR_DVII, 1988 &ddc_i2c, 1989 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I); 1990 } else { 1991 uint16_t crt_info = 1992 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 1993 DRM_DEBUG("Found CRT table, assuming VGA connector\n"); 1994 if (crt_info) { 1995 radeon_add_legacy_encoder(dev, 1996 radeon_get_encoder_id(dev, 1997 ATOM_DEVICE_CRT1_SUPPORT, 1998 1), 1999 ATOM_DEVICE_CRT1_SUPPORT); 2000 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 2001 radeon_add_legacy_connector(dev, 2002 0, 2003 ATOM_DEVICE_CRT1_SUPPORT, 2004 DRM_MODE_CONNECTOR_VGA, 2005 &ddc_i2c, 2006 CONNECTOR_OBJECT_ID_VGA); 2007 } else { 2008 DRM_DEBUG("No connector info found\n"); 2009 return false; 2010 } 2011 } 2012 } 2013 2014 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) { 2015 uint16_t lcd_info = 2016 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 2017 if (lcd_info) { 2018 uint16_t lcd_ddc_info = 2019 combios_get_table_offset(dev, 2020 COMBIOS_LCD_DDC_INFO_TABLE); 2021 2022 radeon_add_legacy_encoder(dev, 2023 radeon_get_encoder_id(dev, 2024 ATOM_DEVICE_LCD1_SUPPORT, 2025 0), 2026 ATOM_DEVICE_LCD1_SUPPORT); 2027 2028 if (lcd_ddc_info) { 2029 ddc_type = RBIOS8(lcd_ddc_info + 2); 2030 switch (ddc_type) { 2031 case DDC_MONID: 2032 ddc_i2c = 2033 combios_setup_i2c_bus 2034 (rdev, RADEON_GPIO_MONID); 2035 break; 2036 case DDC_DVI: 2037 ddc_i2c = 2038 combios_setup_i2c_bus 2039 (rdev, RADEON_GPIO_DVI_DDC); 2040 break; 2041 case DDC_VGA: 2042 ddc_i2c = 2043 combios_setup_i2c_bus 2044 (rdev, RADEON_GPIO_VGA_DDC); 2045 break; 2046 case DDC_CRT2: 2047 ddc_i2c = 2048 combios_setup_i2c_bus 2049 (rdev, RADEON_GPIO_CRT2_DDC); 2050 break; 2051 case DDC_LCD: 2052 ddc_i2c = 2053 combios_setup_i2c_bus 2054 (rdev, RADEON_GPIOPAD_MASK); 2055 ddc_i2c.mask_clk_mask = 2056 RBIOS32(lcd_ddc_info + 3); 2057 ddc_i2c.mask_data_mask = 2058 RBIOS32(lcd_ddc_info + 7); 2059 ddc_i2c.a_clk_mask = 2060 RBIOS32(lcd_ddc_info + 3); 2061 ddc_i2c.a_data_mask = 2062 RBIOS32(lcd_ddc_info + 7); 2063 ddc_i2c.en_clk_mask = 2064 RBIOS32(lcd_ddc_info + 3); 2065 ddc_i2c.en_data_mask = 2066 RBIOS32(lcd_ddc_info + 7); 2067 ddc_i2c.y_clk_mask = 2068 RBIOS32(lcd_ddc_info + 3); 2069 ddc_i2c.y_data_mask = 2070 RBIOS32(lcd_ddc_info + 7); 2071 break; 2072 case DDC_GPIO: 2073 ddc_i2c = 2074 combios_setup_i2c_bus 2075 (rdev, RADEON_MDGPIO_MASK); 2076 ddc_i2c.mask_clk_mask = 2077 RBIOS32(lcd_ddc_info + 3); 2078 ddc_i2c.mask_data_mask = 2079 RBIOS32(lcd_ddc_info + 7); 2080 ddc_i2c.a_clk_mask = 2081 RBIOS32(lcd_ddc_info + 3); 2082 ddc_i2c.a_data_mask = 2083 RBIOS32(lcd_ddc_info + 7); 2084 ddc_i2c.en_clk_mask = 2085 RBIOS32(lcd_ddc_info + 3); 2086 ddc_i2c.en_data_mask = 2087 RBIOS32(lcd_ddc_info + 7); 2088 ddc_i2c.y_clk_mask = 2089 RBIOS32(lcd_ddc_info + 3); 2090 ddc_i2c.y_data_mask = 2091 RBIOS32(lcd_ddc_info + 7); 2092 break; 2093 default: 2094 ddc_i2c.valid = false; 2095 break; 2096 } 2097 DRM_DEBUG("LCD DDC Info Table found!\n"); 2098 } else 2099 ddc_i2c.valid = false; 2100 2101 radeon_add_legacy_connector(dev, 2102 5, 2103 ATOM_DEVICE_LCD1_SUPPORT, 2104 DRM_MODE_CONNECTOR_LVDS, 2105 &ddc_i2c, 2106 CONNECTOR_OBJECT_ID_LVDS); 2107 } 2108 } 2109 2110 /* check TV table */ 2111 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 2112 uint32_t tv_info = 2113 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 2114 if (tv_info) { 2115 if (RBIOS8(tv_info + 6) == 'T') { 2116 if (radeon_apply_legacy_tv_quirks(dev)) { 2117 radeon_add_legacy_encoder(dev, 2118 radeon_get_encoder_id 2119 (dev, 2120 ATOM_DEVICE_TV1_SUPPORT, 2121 2), 2122 ATOM_DEVICE_TV1_SUPPORT); 2123 radeon_add_legacy_connector(dev, 6, 2124 ATOM_DEVICE_TV1_SUPPORT, 2125 DRM_MODE_CONNECTOR_SVIDEO, 2126 &ddc_i2c, 2127 CONNECTOR_OBJECT_ID_SVIDEO); 2128 } 2129 } 2130 } 2131 } 2132 2133 radeon_link_encoder_connector(dev); 2134 2135 return true; 2136} 2137 2138void radeon_external_tmds_setup(struct drm_encoder *encoder) 2139{ 2140 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2141 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2142 2143 if (!tmds) 2144 return; 2145 2146 switch (tmds->dvo_chip) { 2147 case DVO_SIL164: 2148 /* sil 164 */ 2149 radeon_i2c_do_lock(tmds->i2c_bus, 1); 2150 radeon_i2c_sw_put_byte(tmds->i2c_bus, 2151 tmds->slave_addr, 2152 0x08, 0x30); 2153 radeon_i2c_sw_put_byte(tmds->i2c_bus, 2154 tmds->slave_addr, 2155 0x09, 0x00); 2156 radeon_i2c_sw_put_byte(tmds->i2c_bus, 2157 tmds->slave_addr, 2158 0x0a, 0x90); 2159 radeon_i2c_sw_put_byte(tmds->i2c_bus, 2160 tmds->slave_addr, 2161 0x0c, 0x89); 2162 radeon_i2c_sw_put_byte(tmds->i2c_bus, 2163 tmds->slave_addr, 2164 0x08, 0x3b); 2165 radeon_i2c_do_lock(tmds->i2c_bus, 0); 2166 break; 2167 case DVO_SIL1178: 2168 /* sil 1178 - untested */ 2169 /* 2170 * 0x0f, 0x44 2171 * 0x0f, 0x4c 2172 * 0x0e, 0x01 2173 * 0x0a, 0x80 2174 * 0x09, 0x30 2175 * 0x0c, 0xc9 2176 * 0x0d, 0x70 2177 * 0x08, 0x32 2178 * 0x08, 0x33 2179 */ 2180 break; 2181 default: 2182 break; 2183 } 2184 2185} 2186 2187bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder) 2188{ 2189 struct drm_device *dev = encoder->dev; 2190 struct radeon_device *rdev = dev->dev_private; 2191 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2192 uint16_t offset; 2193 uint8_t blocks, slave_addr, rev; 2194 uint32_t index, id; 2195 uint32_t reg, val, and_mask, or_mask; 2196 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2197 2198 if (rdev->bios == NULL) 2199 return false; 2200 2201 if (!tmds) 2202 return false; 2203 2204 if (rdev->flags & RADEON_IS_IGP) { 2205 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE); 2206 rev = RBIOS8(offset); 2207 if (offset) { 2208 rev = RBIOS8(offset); 2209 if (rev > 1) { 2210 blocks = RBIOS8(offset + 3); 2211 index = offset + 4; 2212 while (blocks > 0) { 2213 id = RBIOS16(index); 2214 index += 2; 2215 switch (id >> 13) { 2216 case 0: 2217 reg = (id & 0x1fff) * 4; 2218 val = RBIOS32(index); 2219 index += 4; 2220 WREG32(reg, val); 2221 break; 2222 case 2: 2223 reg = (id & 0x1fff) * 4; 2224 and_mask = RBIOS32(index); 2225 index += 4; 2226 or_mask = RBIOS32(index); 2227 index += 4; 2228 val = RREG32(reg); 2229 val = (val & and_mask) | or_mask; 2230 WREG32(reg, val); 2231 break; 2232 case 3: 2233 val = RBIOS16(index); 2234 index += 2; 2235 udelay(val); 2236 break; 2237 case 4: 2238 val = RBIOS16(index); 2239 index += 2; 2240 udelay(val * 1000); 2241 break; 2242 case 6: 2243 slave_addr = id & 0xff; 2244 slave_addr >>= 1; /* 7 bit addressing */ 2245 index++; 2246 reg = RBIOS8(index); 2247 index++; 2248 val = RBIOS8(index); 2249 index++; 2250 radeon_i2c_do_lock(tmds->i2c_bus, 1); 2251 radeon_i2c_sw_put_byte(tmds->i2c_bus, 2252 slave_addr, 2253 reg, val); 2254 radeon_i2c_do_lock(tmds->i2c_bus, 0); 2255 break; 2256 default: 2257 DRM_ERROR("Unknown id %d\n", id >> 13); 2258 break; 2259 } 2260 blocks--; 2261 } 2262 return true; 2263 } 2264 } 2265 } else { 2266 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 2267 if (offset) { 2268 index = offset + 10; 2269 id = RBIOS16(index); 2270 while (id != 0xffff) { 2271 index += 2; 2272 switch (id >> 13) { 2273 case 0: 2274 reg = (id & 0x1fff) * 4; 2275 val = RBIOS32(index); 2276 WREG32(reg, val); 2277 break; 2278 case 2: 2279 reg = (id & 0x1fff) * 4; 2280 and_mask = RBIOS32(index); 2281 index += 4; 2282 or_mask = RBIOS32(index); 2283 index += 4; 2284 val = RREG32(reg); 2285 val = (val & and_mask) | or_mask; 2286 WREG32(reg, val); 2287 break; 2288 case 4: 2289 val = RBIOS16(index); 2290 index += 2; 2291 udelay(val); 2292 break; 2293 case 5: 2294 reg = id & 0x1fff; 2295 and_mask = RBIOS32(index); 2296 index += 4; 2297 or_mask = RBIOS32(index); 2298 index += 4; 2299 val = RREG32_PLL(reg); 2300 val = (val & and_mask) | or_mask; 2301 WREG32_PLL(reg, val); 2302 break; 2303 case 6: 2304 reg = id & 0x1fff; 2305 val = RBIOS8(index); 2306 index += 1; 2307 radeon_i2c_do_lock(tmds->i2c_bus, 1); 2308 radeon_i2c_sw_put_byte(tmds->i2c_bus, 2309 tmds->slave_addr, 2310 reg, val); 2311 radeon_i2c_do_lock(tmds->i2c_bus, 0); 2312 break; 2313 default: 2314 DRM_ERROR("Unknown id %d\n", id >> 13); 2315 break; 2316 } 2317 id = RBIOS16(index); 2318 } 2319 return true; 2320 } 2321 } 2322 return false; 2323} 2324 2325static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset) 2326{ 2327 struct radeon_device *rdev = dev->dev_private; 2328 2329 if (offset) { 2330 while (RBIOS16(offset)) { 2331 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13); 2332 uint32_t addr = (RBIOS16(offset) & 0x1fff); 2333 uint32_t val, and_mask, or_mask; 2334 uint32_t tmp; 2335 2336 offset += 2; 2337 switch (cmd) { 2338 case 0: 2339 val = RBIOS32(offset); 2340 offset += 4; 2341 WREG32(addr, val); 2342 break; 2343 case 1: 2344 val = RBIOS32(offset); 2345 offset += 4; 2346 WREG32(addr, val); 2347 break; 2348 case 2: 2349 and_mask = RBIOS32(offset); 2350 offset += 4; 2351 or_mask = RBIOS32(offset); 2352 offset += 4; 2353 tmp = RREG32(addr); 2354 tmp &= and_mask; 2355 tmp |= or_mask; 2356 WREG32(addr, tmp); 2357 break; 2358 case 3: 2359 and_mask = RBIOS32(offset); 2360 offset += 4; 2361 or_mask = RBIOS32(offset); 2362 offset += 4; 2363 tmp = RREG32(addr); 2364 tmp &= and_mask; 2365 tmp |= or_mask; 2366 WREG32(addr, tmp); 2367 break; 2368 case 4: 2369 val = RBIOS16(offset); 2370 offset += 2; 2371 udelay(val); 2372 break; 2373 case 5: 2374 val = RBIOS16(offset); 2375 offset += 2; 2376 switch (addr) { 2377 case 8: 2378 while (val--) { 2379 if (! 2380 (RREG32_PLL 2381 (RADEON_CLK_PWRMGT_CNTL) & 2382 RADEON_MC_BUSY)) 2383 break; 2384 } 2385 break; 2386 case 9: 2387 while (val--) { 2388 if ((RREG32(RADEON_MC_STATUS) & 2389 RADEON_MC_IDLE)) 2390 break; 2391 } 2392 break; 2393 default: 2394 break; 2395 } 2396 break; 2397 default: 2398 break; 2399 } 2400 } 2401 } 2402} 2403 2404static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset) 2405{ 2406 struct radeon_device *rdev = dev->dev_private; 2407 2408 if (offset) { 2409 while (RBIOS8(offset)) { 2410 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6); 2411 uint8_t addr = (RBIOS8(offset) & 0x3f); 2412 uint32_t val, shift, tmp; 2413 uint32_t and_mask, or_mask; 2414 2415 offset++; 2416 switch (cmd) { 2417 case 0: 2418 val = RBIOS32(offset); 2419 offset += 4; 2420 WREG32_PLL(addr, val); 2421 break; 2422 case 1: 2423 shift = RBIOS8(offset) * 8; 2424 offset++; 2425 and_mask = RBIOS8(offset) << shift; 2426 and_mask |= ~(0xff << shift); 2427 offset++; 2428 or_mask = RBIOS8(offset) << shift; 2429 offset++; 2430 tmp = RREG32_PLL(addr); 2431 tmp &= and_mask; 2432 tmp |= or_mask; 2433 WREG32_PLL(addr, tmp); 2434 break; 2435 case 2: 2436 case 3: 2437 tmp = 1000; 2438 switch (addr) { 2439 case 1: 2440 udelay(150); 2441 break; 2442 case 2: 2443 udelay(1000); 2444 break; 2445 case 3: 2446 while (tmp--) { 2447 if (! 2448 (RREG32_PLL 2449 (RADEON_CLK_PWRMGT_CNTL) & 2450 RADEON_MC_BUSY)) 2451 break; 2452 } 2453 break; 2454 case 4: 2455 while (tmp--) { 2456 if (RREG32_PLL 2457 (RADEON_CLK_PWRMGT_CNTL) & 2458 RADEON_DLL_READY) 2459 break; 2460 } 2461 break; 2462 case 5: 2463 tmp = 2464 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); 2465 if (tmp & RADEON_CG_NO1_DEBUG_0) { 2466#if 0 2467 uint32_t mclk_cntl = 2468 RREG32_PLL 2469 (RADEON_MCLK_CNTL); 2470 mclk_cntl &= 0xffff0000; 2471 /*mclk_cntl |= 0x00001111;*//* ??? */ 2472 WREG32_PLL(RADEON_MCLK_CNTL, 2473 mclk_cntl); 2474 udelay(10000); 2475#endif 2476 WREG32_PLL 2477 (RADEON_CLK_PWRMGT_CNTL, 2478 tmp & 2479 ~RADEON_CG_NO1_DEBUG_0); 2480 udelay(10000); 2481 } 2482 break; 2483 default: 2484 break; 2485 } 2486 break; 2487 default: 2488 break; 2489 } 2490 } 2491 } 2492} 2493 2494static void combios_parse_ram_reset_table(struct drm_device *dev, 2495 uint16_t offset) 2496{ 2497 struct radeon_device *rdev = dev->dev_private; 2498 uint32_t tmp; 2499 2500 if (offset) { 2501 uint8_t val = RBIOS8(offset); 2502 while (val != 0xff) { 2503 offset++; 2504 2505 if (val == 0x0f) { 2506 uint32_t channel_complete_mask; 2507 2508 if (ASIC_IS_R300(rdev)) 2509 channel_complete_mask = 2510 R300_MEM_PWRUP_COMPLETE; 2511 else 2512 channel_complete_mask = 2513 RADEON_MEM_PWRUP_COMPLETE; 2514 tmp = 20000; 2515 while (tmp--) { 2516 if ((RREG32(RADEON_MEM_STR_CNTL) & 2517 channel_complete_mask) == 2518 channel_complete_mask) 2519 break; 2520 } 2521 } else { 2522 uint32_t or_mask = RBIOS16(offset); 2523 offset += 2; 2524 2525 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 2526 tmp &= RADEON_SDRAM_MODE_MASK; 2527 tmp |= or_mask; 2528 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 2529 2530 or_mask = val << 24; 2531 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 2532 tmp &= RADEON_B3MEM_RESET_MASK; 2533 tmp |= or_mask; 2534 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 2535 } 2536 val = RBIOS8(offset); 2537 } 2538 } 2539} 2540 2541static uint32_t combios_detect_ram(struct drm_device *dev, int ram, 2542 int mem_addr_mapping) 2543{ 2544 struct radeon_device *rdev = dev->dev_private; 2545 uint32_t mem_cntl; 2546 uint32_t mem_size; 2547 uint32_t addr = 0; 2548 2549 mem_cntl = RREG32(RADEON_MEM_CNTL); 2550 if (mem_cntl & RV100_HALF_MODE) 2551 ram /= 2; 2552 mem_size = ram; 2553 mem_cntl &= ~(0xff << 8); 2554 mem_cntl |= (mem_addr_mapping & 0xff) << 8; 2555 WREG32(RADEON_MEM_CNTL, mem_cntl); 2556 RREG32(RADEON_MEM_CNTL); 2557 2558 /* sdram reset ? */ 2559 2560 /* something like this???? */ 2561 while (ram--) { 2562 addr = ram * 1024 * 1024; 2563 /* write to each page */ 2564 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER); 2565 WREG32(RADEON_MM_DATA, 0xdeadbeef); 2566 /* read back and verify */ 2567 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER); 2568 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef) 2569 return 0; 2570 } 2571 2572 return mem_size; 2573} 2574 2575static void combios_write_ram_size(struct drm_device *dev) 2576{ 2577 struct radeon_device *rdev = dev->dev_private; 2578 uint8_t rev; 2579 uint16_t offset; 2580 uint32_t mem_size = 0; 2581 uint32_t mem_cntl = 0; 2582 2583 /* should do something smarter here I guess... */ 2584 if (rdev->flags & RADEON_IS_IGP) 2585 return; 2586 2587 /* first check detected mem table */ 2588 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE); 2589 if (offset) { 2590 rev = RBIOS8(offset); 2591 if (rev < 3) { 2592 mem_cntl = RBIOS32(offset + 1); 2593 mem_size = RBIOS16(offset + 5); 2594 if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) && 2595 ((dev->pdev->device != 0x515e) 2596 && (dev->pdev->device != 0x5969))) 2597 WREG32(RADEON_MEM_CNTL, mem_cntl); 2598 } 2599 } 2600 2601 if (!mem_size) { 2602 offset = 2603 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 2604 if (offset) { 2605 rev = RBIOS8(offset - 1); 2606 if (rev < 1) { 2607 if (((rdev->flags & RADEON_FAMILY_MASK) < 2608 CHIP_R200) 2609 && ((dev->pdev->device != 0x515e) 2610 && (dev->pdev->device != 0x5969))) { 2611 int ram = 0; 2612 int mem_addr_mapping = 0; 2613 2614 while (RBIOS8(offset)) { 2615 ram = RBIOS8(offset); 2616 mem_addr_mapping = 2617 RBIOS8(offset + 1); 2618 if (mem_addr_mapping != 0x25) 2619 ram *= 2; 2620 mem_size = 2621 combios_detect_ram(dev, ram, 2622 mem_addr_mapping); 2623 if (mem_size) 2624 break; 2625 offset += 2; 2626 } 2627 } else 2628 mem_size = RBIOS8(offset); 2629 } else { 2630 mem_size = RBIOS8(offset); 2631 mem_size *= 2; /* convert to MB */ 2632 } 2633 } 2634 } 2635 2636 mem_size *= (1024 * 1024); /* convert to bytes */ 2637 WREG32(RADEON_CONFIG_MEMSIZE, mem_size); 2638} 2639 2640void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable) 2641{ 2642 uint16_t dyn_clk_info = 2643 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); 2644 2645 if (dyn_clk_info) 2646 combios_parse_pll_table(dev, dyn_clk_info); 2647} 2648 2649void radeon_combios_asic_init(struct drm_device *dev) 2650{ 2651 struct radeon_device *rdev = dev->dev_private; 2652 uint16_t table; 2653 2654 /* port hardcoded mac stuff from radeonfb */ 2655 if (rdev->bios == NULL) 2656 return; 2657 2658 /* ASIC INIT 1 */ 2659 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE); 2660 if (table) 2661 combios_parse_mmio_table(dev, table); 2662 2663 /* PLL INIT */ 2664 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE); 2665 if (table) 2666 combios_parse_pll_table(dev, table); 2667 2668 /* ASIC INIT 2 */ 2669 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE); 2670 if (table) 2671 combios_parse_mmio_table(dev, table); 2672 2673 if (!(rdev->flags & RADEON_IS_IGP)) { 2674 /* ASIC INIT 4 */ 2675 table = 2676 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE); 2677 if (table) 2678 combios_parse_mmio_table(dev, table); 2679 2680 /* RAM RESET */ 2681 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE); 2682 if (table) 2683 combios_parse_ram_reset_table(dev, table); 2684 2685 /* ASIC INIT 3 */ 2686 table = 2687 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE); 2688 if (table) 2689 combios_parse_mmio_table(dev, table); 2690 2691 /* write CONFIG_MEMSIZE */ 2692 combios_write_ram_size(dev); 2693 } 2694 2695 /* DYN CLK 1 */ 2696 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); 2697 if (table) 2698 combios_parse_pll_table(dev, table); 2699 2700} 2701 2702void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev) 2703{ 2704 struct radeon_device *rdev = dev->dev_private; 2705 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch; 2706 2707 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 2708 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 2709 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH); 2710 2711 /* let the bios control the backlight */ 2712 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; 2713 2714 /* tell the bios not to handle mode switching */ 2715 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS | 2716 RADEON_ACC_MODE_CHANGE); 2717 2718 /* tell the bios a driver is loaded */ 2719 bios_7_scratch |= RADEON_DRV_LOADED; 2720 2721 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); 2722 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 2723 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch); 2724} 2725 2726void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock) 2727{ 2728 struct drm_device *dev = encoder->dev; 2729 struct radeon_device *rdev = dev->dev_private; 2730 uint32_t bios_6_scratch; 2731 2732 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 2733 2734 if (lock) 2735 bios_6_scratch |= RADEON_DRIVER_CRITICAL; 2736 else 2737 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL; 2738 2739 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 2740} 2741 2742void 2743radeon_combios_connected_scratch_regs(struct drm_connector *connector, 2744 struct drm_encoder *encoder, 2745 bool connected) 2746{ 2747 struct drm_device *dev = connector->dev; 2748 struct radeon_device *rdev = dev->dev_private; 2749 struct radeon_connector *radeon_connector = 2750 to_radeon_connector(connector); 2751 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2752 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH); 2753 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 2754 2755 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 2756 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 2757 if (connected) { 2758 DRM_DEBUG("TV1 connected\n"); 2759 /* fix me */ 2760 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO; 2761 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */ 2762 bios_5_scratch |= RADEON_TV1_ON; 2763 bios_5_scratch |= RADEON_ACC_REQ_TV1; 2764 } else { 2765 DRM_DEBUG("TV1 disconnected\n"); 2766 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK; 2767 bios_5_scratch &= ~RADEON_TV1_ON; 2768 bios_5_scratch &= ~RADEON_ACC_REQ_TV1; 2769 } 2770 } 2771 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 2772 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 2773 if (connected) { 2774 DRM_DEBUG("LCD1 connected\n"); 2775 bios_4_scratch |= RADEON_LCD1_ATTACHED; 2776 bios_5_scratch |= RADEON_LCD1_ON; 2777 bios_5_scratch |= RADEON_ACC_REQ_LCD1; 2778 } else { 2779 DRM_DEBUG("LCD1 disconnected\n"); 2780 bios_4_scratch &= ~RADEON_LCD1_ATTACHED; 2781 bios_5_scratch &= ~RADEON_LCD1_ON; 2782 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1; 2783 } 2784 } 2785 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 2786 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 2787 if (connected) { 2788 DRM_DEBUG("CRT1 connected\n"); 2789 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR; 2790 bios_5_scratch |= RADEON_CRT1_ON; 2791 bios_5_scratch |= RADEON_ACC_REQ_CRT1; 2792 } else { 2793 DRM_DEBUG("CRT1 disconnected\n"); 2794 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK; 2795 bios_5_scratch &= ~RADEON_CRT1_ON; 2796 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1; 2797 } 2798 } 2799 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 2800 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 2801 if (connected) { 2802 DRM_DEBUG("CRT2 connected\n"); 2803 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR; 2804 bios_5_scratch |= RADEON_CRT2_ON; 2805 bios_5_scratch |= RADEON_ACC_REQ_CRT2; 2806 } else { 2807 DRM_DEBUG("CRT2 disconnected\n"); 2808 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK; 2809 bios_5_scratch &= ~RADEON_CRT2_ON; 2810 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2; 2811 } 2812 } 2813 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 2814 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 2815 if (connected) { 2816 DRM_DEBUG("DFP1 connected\n"); 2817 bios_4_scratch |= RADEON_DFP1_ATTACHED; 2818 bios_5_scratch |= RADEON_DFP1_ON; 2819 bios_5_scratch |= RADEON_ACC_REQ_DFP1; 2820 } else { 2821 DRM_DEBUG("DFP1 disconnected\n"); 2822 bios_4_scratch &= ~RADEON_DFP1_ATTACHED; 2823 bios_5_scratch &= ~RADEON_DFP1_ON; 2824 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1; 2825 } 2826 } 2827 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 2828 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 2829 if (connected) { 2830 DRM_DEBUG("DFP2 connected\n"); 2831 bios_4_scratch |= RADEON_DFP2_ATTACHED; 2832 bios_5_scratch |= RADEON_DFP2_ON; 2833 bios_5_scratch |= RADEON_ACC_REQ_DFP2; 2834 } else { 2835 DRM_DEBUG("DFP2 disconnected\n"); 2836 bios_4_scratch &= ~RADEON_DFP2_ATTACHED; 2837 bios_5_scratch &= ~RADEON_DFP2_ON; 2838 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2; 2839 } 2840 } 2841 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch); 2842 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 2843} 2844 2845void 2846radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) 2847{ 2848 struct drm_device *dev = encoder->dev; 2849 struct radeon_device *rdev = dev->dev_private; 2850 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2851 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 2852 2853 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 2854 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK; 2855 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT); 2856 } 2857 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2858 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK; 2859 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT); 2860 } 2861 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2862 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK; 2863 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT); 2864 } 2865 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 2866 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK; 2867 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT); 2868 } 2869 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 2870 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK; 2871 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT); 2872 } 2873 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 2874 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK; 2875 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT); 2876 } 2877 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 2878} 2879 2880void 2881radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) 2882{ 2883 struct drm_device *dev = encoder->dev; 2884 struct radeon_device *rdev = dev->dev_private; 2885 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2886 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 2887 2888 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 2889 if (on) 2890 bios_6_scratch |= RADEON_TV_DPMS_ON; 2891 else 2892 bios_6_scratch &= ~RADEON_TV_DPMS_ON; 2893 } 2894 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 2895 if (on) 2896 bios_6_scratch |= RADEON_CRT_DPMS_ON; 2897 else 2898 bios_6_scratch &= ~RADEON_CRT_DPMS_ON; 2899 } 2900 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2901 if (on) 2902 bios_6_scratch |= RADEON_LCD_DPMS_ON; 2903 else 2904 bios_6_scratch &= ~RADEON_LCD_DPMS_ON; 2905 } 2906 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 2907 if (on) 2908 bios_6_scratch |= RADEON_DFP_DPMS_ON; 2909 else 2910 bios_6_scratch &= ~RADEON_DFP_DPMS_ON; 2911 } 2912 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 2913} 2914