radeon_combios.c revision 76a7142a083434fe55b14f01aa2624733fea39b2
1/* 2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario 3 * Copyright 2007-8 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 */ 27#include "drmP.h" 28#include "radeon_drm.h" 29#include "radeon.h" 30#include "atom.h" 31 32#ifdef CONFIG_PPC_PMAC 33/* not sure which of these are needed */ 34#include <asm/machdep.h> 35#include <asm/pmac_feature.h> 36#include <asm/prom.h> 37#include <asm/pci-bridge.h> 38#endif /* CONFIG_PPC_PMAC */ 39 40/* from radeon_encoder.c */ 41extern uint32_t 42radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, 43 uint8_t dac); 44extern void radeon_link_encoder_connector(struct drm_device *dev); 45 46/* from radeon_connector.c */ 47extern void 48radeon_add_legacy_connector(struct drm_device *dev, 49 uint32_t connector_id, 50 uint32_t supported_device, 51 int connector_type, 52 struct radeon_i2c_bus_rec *i2c_bus, 53 uint16_t connector_object_id, 54 struct radeon_hpd *hpd); 55 56/* from radeon_legacy_encoder.c */ 57extern void 58radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, 59 uint32_t supported_device); 60 61/* old legacy ATI BIOS routines */ 62 63/* COMBIOS table offsets */ 64enum radeon_combios_table_offset { 65 /* absolute offset tables */ 66 COMBIOS_ASIC_INIT_1_TABLE, 67 COMBIOS_BIOS_SUPPORT_TABLE, 68 COMBIOS_DAC_PROGRAMMING_TABLE, 69 COMBIOS_MAX_COLOR_DEPTH_TABLE, 70 COMBIOS_CRTC_INFO_TABLE, 71 COMBIOS_PLL_INFO_TABLE, 72 COMBIOS_TV_INFO_TABLE, 73 COMBIOS_DFP_INFO_TABLE, 74 COMBIOS_HW_CONFIG_INFO_TABLE, 75 COMBIOS_MULTIMEDIA_INFO_TABLE, 76 COMBIOS_TV_STD_PATCH_TABLE, 77 COMBIOS_LCD_INFO_TABLE, 78 COMBIOS_MOBILE_INFO_TABLE, 79 COMBIOS_PLL_INIT_TABLE, 80 COMBIOS_MEM_CONFIG_TABLE, 81 COMBIOS_SAVE_MASK_TABLE, 82 COMBIOS_HARDCODED_EDID_TABLE, 83 COMBIOS_ASIC_INIT_2_TABLE, 84 COMBIOS_CONNECTOR_INFO_TABLE, 85 COMBIOS_DYN_CLK_1_TABLE, 86 COMBIOS_RESERVED_MEM_TABLE, 87 COMBIOS_EXT_TMDS_INFO_TABLE, 88 COMBIOS_MEM_CLK_INFO_TABLE, 89 COMBIOS_EXT_DAC_INFO_TABLE, 90 COMBIOS_MISC_INFO_TABLE, 91 COMBIOS_CRT_INFO_TABLE, 92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE, 93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE, 94 COMBIOS_FAN_SPEED_INFO_TABLE, 95 COMBIOS_OVERDRIVE_INFO_TABLE, 96 COMBIOS_OEM_INFO_TABLE, 97 COMBIOS_DYN_CLK_2_TABLE, 98 COMBIOS_POWER_CONNECTOR_INFO_TABLE, 99 COMBIOS_I2C_INFO_TABLE, 100 /* relative offset tables */ 101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */ 102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */ 103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */ 104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */ 105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */ 106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */ 107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */ 108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */ 109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */ 110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */ 111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */ 112}; 113 114enum radeon_combios_ddc { 115 DDC_NONE_DETECTED, 116 DDC_MONID, 117 DDC_DVI, 118 DDC_VGA, 119 DDC_CRT2, 120 DDC_LCD, 121 DDC_GPIO, 122}; 123 124enum radeon_combios_connector { 125 CONNECTOR_NONE_LEGACY, 126 CONNECTOR_PROPRIETARY_LEGACY, 127 CONNECTOR_CRT_LEGACY, 128 CONNECTOR_DVI_I_LEGACY, 129 CONNECTOR_DVI_D_LEGACY, 130 CONNECTOR_CTV_LEGACY, 131 CONNECTOR_STV_LEGACY, 132 CONNECTOR_UNSUPPORTED_LEGACY 133}; 134 135const int legacy_connector_convert[] = { 136 DRM_MODE_CONNECTOR_Unknown, 137 DRM_MODE_CONNECTOR_DVID, 138 DRM_MODE_CONNECTOR_VGA, 139 DRM_MODE_CONNECTOR_DVII, 140 DRM_MODE_CONNECTOR_DVID, 141 DRM_MODE_CONNECTOR_Composite, 142 DRM_MODE_CONNECTOR_SVIDEO, 143 DRM_MODE_CONNECTOR_Unknown, 144}; 145 146static uint16_t combios_get_table_offset(struct drm_device *dev, 147 enum radeon_combios_table_offset table) 148{ 149 struct radeon_device *rdev = dev->dev_private; 150 int rev; 151 uint16_t offset = 0, check_offset; 152 153 if (!rdev->bios) 154 return 0; 155 156 switch (table) { 157 /* absolute offset tables */ 158 case COMBIOS_ASIC_INIT_1_TABLE: 159 check_offset = RBIOS16(rdev->bios_header_start + 0xc); 160 if (check_offset) 161 offset = check_offset; 162 break; 163 case COMBIOS_BIOS_SUPPORT_TABLE: 164 check_offset = RBIOS16(rdev->bios_header_start + 0x14); 165 if (check_offset) 166 offset = check_offset; 167 break; 168 case COMBIOS_DAC_PROGRAMMING_TABLE: 169 check_offset = RBIOS16(rdev->bios_header_start + 0x2a); 170 if (check_offset) 171 offset = check_offset; 172 break; 173 case COMBIOS_MAX_COLOR_DEPTH_TABLE: 174 check_offset = RBIOS16(rdev->bios_header_start + 0x2c); 175 if (check_offset) 176 offset = check_offset; 177 break; 178 case COMBIOS_CRTC_INFO_TABLE: 179 check_offset = RBIOS16(rdev->bios_header_start + 0x2e); 180 if (check_offset) 181 offset = check_offset; 182 break; 183 case COMBIOS_PLL_INFO_TABLE: 184 check_offset = RBIOS16(rdev->bios_header_start + 0x30); 185 if (check_offset) 186 offset = check_offset; 187 break; 188 case COMBIOS_TV_INFO_TABLE: 189 check_offset = RBIOS16(rdev->bios_header_start + 0x32); 190 if (check_offset) 191 offset = check_offset; 192 break; 193 case COMBIOS_DFP_INFO_TABLE: 194 check_offset = RBIOS16(rdev->bios_header_start + 0x34); 195 if (check_offset) 196 offset = check_offset; 197 break; 198 case COMBIOS_HW_CONFIG_INFO_TABLE: 199 check_offset = RBIOS16(rdev->bios_header_start + 0x36); 200 if (check_offset) 201 offset = check_offset; 202 break; 203 case COMBIOS_MULTIMEDIA_INFO_TABLE: 204 check_offset = RBIOS16(rdev->bios_header_start + 0x38); 205 if (check_offset) 206 offset = check_offset; 207 break; 208 case COMBIOS_TV_STD_PATCH_TABLE: 209 check_offset = RBIOS16(rdev->bios_header_start + 0x3e); 210 if (check_offset) 211 offset = check_offset; 212 break; 213 case COMBIOS_LCD_INFO_TABLE: 214 check_offset = RBIOS16(rdev->bios_header_start + 0x40); 215 if (check_offset) 216 offset = check_offset; 217 break; 218 case COMBIOS_MOBILE_INFO_TABLE: 219 check_offset = RBIOS16(rdev->bios_header_start + 0x42); 220 if (check_offset) 221 offset = check_offset; 222 break; 223 case COMBIOS_PLL_INIT_TABLE: 224 check_offset = RBIOS16(rdev->bios_header_start + 0x46); 225 if (check_offset) 226 offset = check_offset; 227 break; 228 case COMBIOS_MEM_CONFIG_TABLE: 229 check_offset = RBIOS16(rdev->bios_header_start + 0x48); 230 if (check_offset) 231 offset = check_offset; 232 break; 233 case COMBIOS_SAVE_MASK_TABLE: 234 check_offset = RBIOS16(rdev->bios_header_start + 0x4a); 235 if (check_offset) 236 offset = check_offset; 237 break; 238 case COMBIOS_HARDCODED_EDID_TABLE: 239 check_offset = RBIOS16(rdev->bios_header_start + 0x4c); 240 if (check_offset) 241 offset = check_offset; 242 break; 243 case COMBIOS_ASIC_INIT_2_TABLE: 244 check_offset = RBIOS16(rdev->bios_header_start + 0x4e); 245 if (check_offset) 246 offset = check_offset; 247 break; 248 case COMBIOS_CONNECTOR_INFO_TABLE: 249 check_offset = RBIOS16(rdev->bios_header_start + 0x50); 250 if (check_offset) 251 offset = check_offset; 252 break; 253 case COMBIOS_DYN_CLK_1_TABLE: 254 check_offset = RBIOS16(rdev->bios_header_start + 0x52); 255 if (check_offset) 256 offset = check_offset; 257 break; 258 case COMBIOS_RESERVED_MEM_TABLE: 259 check_offset = RBIOS16(rdev->bios_header_start + 0x54); 260 if (check_offset) 261 offset = check_offset; 262 break; 263 case COMBIOS_EXT_TMDS_INFO_TABLE: 264 check_offset = RBIOS16(rdev->bios_header_start + 0x58); 265 if (check_offset) 266 offset = check_offset; 267 break; 268 case COMBIOS_MEM_CLK_INFO_TABLE: 269 check_offset = RBIOS16(rdev->bios_header_start + 0x5a); 270 if (check_offset) 271 offset = check_offset; 272 break; 273 case COMBIOS_EXT_DAC_INFO_TABLE: 274 check_offset = RBIOS16(rdev->bios_header_start + 0x5c); 275 if (check_offset) 276 offset = check_offset; 277 break; 278 case COMBIOS_MISC_INFO_TABLE: 279 check_offset = RBIOS16(rdev->bios_header_start + 0x5e); 280 if (check_offset) 281 offset = check_offset; 282 break; 283 case COMBIOS_CRT_INFO_TABLE: 284 check_offset = RBIOS16(rdev->bios_header_start + 0x60); 285 if (check_offset) 286 offset = check_offset; 287 break; 288 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE: 289 check_offset = RBIOS16(rdev->bios_header_start + 0x62); 290 if (check_offset) 291 offset = check_offset; 292 break; 293 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE: 294 check_offset = RBIOS16(rdev->bios_header_start + 0x64); 295 if (check_offset) 296 offset = check_offset; 297 break; 298 case COMBIOS_FAN_SPEED_INFO_TABLE: 299 check_offset = RBIOS16(rdev->bios_header_start + 0x66); 300 if (check_offset) 301 offset = check_offset; 302 break; 303 case COMBIOS_OVERDRIVE_INFO_TABLE: 304 check_offset = RBIOS16(rdev->bios_header_start + 0x68); 305 if (check_offset) 306 offset = check_offset; 307 break; 308 case COMBIOS_OEM_INFO_TABLE: 309 check_offset = RBIOS16(rdev->bios_header_start + 0x6a); 310 if (check_offset) 311 offset = check_offset; 312 break; 313 case COMBIOS_DYN_CLK_2_TABLE: 314 check_offset = RBIOS16(rdev->bios_header_start + 0x6c); 315 if (check_offset) 316 offset = check_offset; 317 break; 318 case COMBIOS_POWER_CONNECTOR_INFO_TABLE: 319 check_offset = RBIOS16(rdev->bios_header_start + 0x6e); 320 if (check_offset) 321 offset = check_offset; 322 break; 323 case COMBIOS_I2C_INFO_TABLE: 324 check_offset = RBIOS16(rdev->bios_header_start + 0x70); 325 if (check_offset) 326 offset = check_offset; 327 break; 328 /* relative offset tables */ 329 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */ 330 check_offset = 331 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 332 if (check_offset) { 333 rev = RBIOS8(check_offset); 334 if (rev > 0) { 335 check_offset = RBIOS16(check_offset + 0x3); 336 if (check_offset) 337 offset = check_offset; 338 } 339 } 340 break; 341 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */ 342 check_offset = 343 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 344 if (check_offset) { 345 rev = RBIOS8(check_offset); 346 if (rev > 0) { 347 check_offset = RBIOS16(check_offset + 0x5); 348 if (check_offset) 349 offset = check_offset; 350 } 351 } 352 break; 353 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */ 354 check_offset = 355 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 356 if (check_offset) { 357 rev = RBIOS8(check_offset); 358 if (rev > 0) { 359 check_offset = RBIOS16(check_offset + 0x7); 360 if (check_offset) 361 offset = check_offset; 362 } 363 } 364 break; 365 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */ 366 check_offset = 367 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 368 if (check_offset) { 369 rev = RBIOS8(check_offset); 370 if (rev == 2) { 371 check_offset = RBIOS16(check_offset + 0x9); 372 if (check_offset) 373 offset = check_offset; 374 } 375 } 376 break; 377 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */ 378 check_offset = 379 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 380 if (check_offset) { 381 while (RBIOS8(check_offset++)); 382 check_offset += 2; 383 if (check_offset) 384 offset = check_offset; 385 } 386 break; 387 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */ 388 check_offset = 389 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 390 if (check_offset) { 391 check_offset = RBIOS16(check_offset + 0x11); 392 if (check_offset) 393 offset = check_offset; 394 } 395 break; 396 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */ 397 check_offset = 398 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 399 if (check_offset) { 400 check_offset = RBIOS16(check_offset + 0x13); 401 if (check_offset) 402 offset = check_offset; 403 } 404 break; 405 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */ 406 check_offset = 407 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 408 if (check_offset) { 409 check_offset = RBIOS16(check_offset + 0x15); 410 if (check_offset) 411 offset = check_offset; 412 } 413 break; 414 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */ 415 check_offset = 416 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 417 if (check_offset) { 418 check_offset = RBIOS16(check_offset + 0x17); 419 if (check_offset) 420 offset = check_offset; 421 } 422 break; 423 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */ 424 check_offset = 425 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 426 if (check_offset) { 427 check_offset = RBIOS16(check_offset + 0x2); 428 if (check_offset) 429 offset = check_offset; 430 } 431 break; 432 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */ 433 check_offset = 434 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 435 if (check_offset) { 436 check_offset = RBIOS16(check_offset + 0x4); 437 if (check_offset) 438 offset = check_offset; 439 } 440 break; 441 default: 442 break; 443 } 444 445 return offset; 446 447} 448 449bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev) 450{ 451 int edid_info; 452 struct edid *edid; 453 unsigned char *raw; 454 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE); 455 if (!edid_info) 456 return false; 457 458 raw = rdev->bios + edid_info; 459 edid = kmalloc(EDID_LENGTH * (raw[0x7e] + 1), GFP_KERNEL); 460 if (edid == NULL) 461 return false; 462 463 memcpy((unsigned char *)edid, raw, EDID_LENGTH * (raw[0x7e] + 1)); 464 465 if (!drm_edid_is_valid(edid)) { 466 kfree(edid); 467 return false; 468 } 469 470 rdev->mode_info.bios_hardcoded_edid = edid; 471 return true; 472} 473 474struct edid * 475radeon_combios_get_hardcoded_edid(struct radeon_device *rdev) 476{ 477 if (rdev->mode_info.bios_hardcoded_edid) 478 return rdev->mode_info.bios_hardcoded_edid; 479 return NULL; 480} 481 482static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev, 483 int ddc_line) 484{ 485 struct radeon_i2c_bus_rec i2c; 486 487 if (ddc_line == RADEON_GPIOPAD_MASK) { 488 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; 489 i2c.mask_data_reg = RADEON_GPIOPAD_MASK; 490 i2c.a_clk_reg = RADEON_GPIOPAD_A; 491 i2c.a_data_reg = RADEON_GPIOPAD_A; 492 i2c.en_clk_reg = RADEON_GPIOPAD_EN; 493 i2c.en_data_reg = RADEON_GPIOPAD_EN; 494 i2c.y_clk_reg = RADEON_GPIOPAD_Y; 495 i2c.y_data_reg = RADEON_GPIOPAD_Y; 496 } else if (ddc_line == RADEON_MDGPIO_MASK) { 497 i2c.mask_clk_reg = RADEON_MDGPIO_MASK; 498 i2c.mask_data_reg = RADEON_MDGPIO_MASK; 499 i2c.a_clk_reg = RADEON_MDGPIO_A; 500 i2c.a_data_reg = RADEON_MDGPIO_A; 501 i2c.en_clk_reg = RADEON_MDGPIO_EN; 502 i2c.en_data_reg = RADEON_MDGPIO_EN; 503 i2c.y_clk_reg = RADEON_MDGPIO_Y; 504 i2c.y_data_reg = RADEON_MDGPIO_Y; 505 } else { 506 i2c.mask_clk_mask = RADEON_GPIO_EN_1; 507 i2c.mask_data_mask = RADEON_GPIO_EN_0; 508 i2c.a_clk_mask = RADEON_GPIO_A_1; 509 i2c.a_data_mask = RADEON_GPIO_A_0; 510 i2c.en_clk_mask = RADEON_GPIO_EN_1; 511 i2c.en_data_mask = RADEON_GPIO_EN_0; 512 i2c.y_clk_mask = RADEON_GPIO_Y_1; 513 i2c.y_data_mask = RADEON_GPIO_Y_0; 514 515 i2c.mask_clk_reg = ddc_line; 516 i2c.mask_data_reg = ddc_line; 517 i2c.a_clk_reg = ddc_line; 518 i2c.a_data_reg = ddc_line; 519 i2c.en_clk_reg = ddc_line; 520 i2c.en_data_reg = ddc_line; 521 i2c.y_clk_reg = ddc_line; 522 i2c.y_data_reg = ddc_line; 523 } 524 525 switch (rdev->family) { 526 case CHIP_R100: 527 case CHIP_RV100: 528 case CHIP_RS100: 529 case CHIP_RV200: 530 case CHIP_RS200: 531 case CHIP_RS300: 532 switch (ddc_line) { 533 case RADEON_GPIO_DVI_DDC: 534 i2c.hw_capable = true; 535 break; 536 default: 537 i2c.hw_capable = false; 538 break; 539 } 540 break; 541 case CHIP_R200: 542 switch (ddc_line) { 543 case RADEON_GPIO_DVI_DDC: 544 case RADEON_GPIO_MONID: 545 i2c.hw_capable = true; 546 break; 547 default: 548 i2c.hw_capable = false; 549 break; 550 } 551 break; 552 case CHIP_RV250: 553 case CHIP_RV280: 554 switch (ddc_line) { 555 case RADEON_GPIO_VGA_DDC: 556 case RADEON_GPIO_DVI_DDC: 557 case RADEON_GPIO_CRT2_DDC: 558 i2c.hw_capable = true; 559 break; 560 default: 561 i2c.hw_capable = false; 562 break; 563 } 564 break; 565 case CHIP_R300: 566 case CHIP_R350: 567 switch (ddc_line) { 568 case RADEON_GPIO_VGA_DDC: 569 case RADEON_GPIO_DVI_DDC: 570 i2c.hw_capable = true; 571 break; 572 default: 573 i2c.hw_capable = false; 574 break; 575 } 576 break; 577 case CHIP_RV350: 578 case CHIP_RV380: 579 case CHIP_RS400: 580 case CHIP_RS480: 581 switch (ddc_line) { 582 case RADEON_GPIO_VGA_DDC: 583 case RADEON_GPIO_DVI_DDC: 584 i2c.hw_capable = true; 585 break; 586 case RADEON_GPIO_MONID: 587 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work 588 * reliably on some pre-r4xx hardware; not sure why. 589 */ 590 i2c.hw_capable = false; 591 break; 592 default: 593 i2c.hw_capable = false; 594 break; 595 } 596 break; 597 default: 598 i2c.hw_capable = false; 599 break; 600 } 601 i2c.mm_i2c = false; 602 i2c.i2c_id = 0; 603 i2c.hpd = RADEON_HPD_NONE; 604 605 if (ddc_line) 606 i2c.valid = true; 607 else 608 i2c.valid = false; 609 610 return i2c; 611} 612 613bool radeon_combios_get_clock_info(struct drm_device *dev) 614{ 615 struct radeon_device *rdev = dev->dev_private; 616 uint16_t pll_info; 617 struct radeon_pll *p1pll = &rdev->clock.p1pll; 618 struct radeon_pll *p2pll = &rdev->clock.p2pll; 619 struct radeon_pll *spll = &rdev->clock.spll; 620 struct radeon_pll *mpll = &rdev->clock.mpll; 621 int8_t rev; 622 uint16_t sclk, mclk; 623 624 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE); 625 if (pll_info) { 626 rev = RBIOS8(pll_info); 627 628 /* pixel clocks */ 629 p1pll->reference_freq = RBIOS16(pll_info + 0xe); 630 p1pll->reference_div = RBIOS16(pll_info + 0x10); 631 p1pll->pll_out_min = RBIOS32(pll_info + 0x12); 632 p1pll->pll_out_max = RBIOS32(pll_info + 0x16); 633 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 634 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 635 636 if (rev > 9) { 637 p1pll->pll_in_min = RBIOS32(pll_info + 0x36); 638 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a); 639 } else { 640 p1pll->pll_in_min = 40; 641 p1pll->pll_in_max = 500; 642 } 643 *p2pll = *p1pll; 644 645 /* system clock */ 646 spll->reference_freq = RBIOS16(pll_info + 0x1a); 647 spll->reference_div = RBIOS16(pll_info + 0x1c); 648 spll->pll_out_min = RBIOS32(pll_info + 0x1e); 649 spll->pll_out_max = RBIOS32(pll_info + 0x22); 650 651 if (rev > 10) { 652 spll->pll_in_min = RBIOS32(pll_info + 0x48); 653 spll->pll_in_max = RBIOS32(pll_info + 0x4c); 654 } else { 655 /* ??? */ 656 spll->pll_in_min = 40; 657 spll->pll_in_max = 500; 658 } 659 660 /* memory clock */ 661 mpll->reference_freq = RBIOS16(pll_info + 0x26); 662 mpll->reference_div = RBIOS16(pll_info + 0x28); 663 mpll->pll_out_min = RBIOS32(pll_info + 0x2a); 664 mpll->pll_out_max = RBIOS32(pll_info + 0x2e); 665 666 if (rev > 10) { 667 mpll->pll_in_min = RBIOS32(pll_info + 0x5a); 668 mpll->pll_in_max = RBIOS32(pll_info + 0x5e); 669 } else { 670 /* ??? */ 671 mpll->pll_in_min = 40; 672 mpll->pll_in_max = 500; 673 } 674 675 /* default sclk/mclk */ 676 sclk = RBIOS16(pll_info + 0xa); 677 mclk = RBIOS16(pll_info + 0x8); 678 if (sclk == 0) 679 sclk = 200 * 100; 680 if (mclk == 0) 681 mclk = 200 * 100; 682 683 rdev->clock.default_sclk = sclk; 684 rdev->clock.default_mclk = mclk; 685 686 return true; 687 } 688 return false; 689} 690 691bool radeon_combios_sideport_present(struct radeon_device *rdev) 692{ 693 struct drm_device *dev = rdev->ddev; 694 u16 igp_info; 695 696 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE); 697 698 if (igp_info) { 699 if (RBIOS16(igp_info + 0x4)) 700 return true; 701 } 702 return false; 703} 704 705static const uint32_t default_primarydac_adj[CHIP_LAST] = { 706 0x00000808, /* r100 */ 707 0x00000808, /* rv100 */ 708 0x00000808, /* rs100 */ 709 0x00000808, /* rv200 */ 710 0x00000808, /* rs200 */ 711 0x00000808, /* r200 */ 712 0x00000808, /* rv250 */ 713 0x00000000, /* rs300 */ 714 0x00000808, /* rv280 */ 715 0x00000808, /* r300 */ 716 0x00000808, /* r350 */ 717 0x00000808, /* rv350 */ 718 0x00000808, /* rv380 */ 719 0x00000808, /* r420 */ 720 0x00000808, /* r423 */ 721 0x00000808, /* rv410 */ 722 0x00000000, /* rs400 */ 723 0x00000000, /* rs480 */ 724}; 725 726static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev, 727 struct radeon_encoder_primary_dac *p_dac) 728{ 729 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family]; 730 return; 731} 732 733struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct 734 radeon_encoder 735 *encoder) 736{ 737 struct drm_device *dev = encoder->base.dev; 738 struct radeon_device *rdev = dev->dev_private; 739 uint16_t dac_info; 740 uint8_t rev, bg, dac; 741 struct radeon_encoder_primary_dac *p_dac = NULL; 742 int found = 0; 743 744 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), 745 GFP_KERNEL); 746 747 if (!p_dac) 748 return NULL; 749 750 /* check CRT table */ 751 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 752 if (dac_info) { 753 rev = RBIOS8(dac_info) & 0x3; 754 if (rev < 2) { 755 bg = RBIOS8(dac_info + 0x2) & 0xf; 756 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf; 757 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 758 } else { 759 bg = RBIOS8(dac_info + 0x2) & 0xf; 760 dac = RBIOS8(dac_info + 0x3) & 0xf; 761 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 762 } 763 /* if the values are all zeros, use the table */ 764 if (p_dac->ps2_pdac_adj) 765 found = 1; 766 } 767 768 if (!found) /* fallback to defaults */ 769 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac); 770 771 return p_dac; 772} 773 774enum radeon_tv_std 775radeon_combios_get_tv_info(struct radeon_device *rdev) 776{ 777 struct drm_device *dev = rdev->ddev; 778 uint16_t tv_info; 779 enum radeon_tv_std tv_std = TV_STD_NTSC; 780 781 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 782 if (tv_info) { 783 if (RBIOS8(tv_info + 6) == 'T') { 784 switch (RBIOS8(tv_info + 7) & 0xf) { 785 case 1: 786 tv_std = TV_STD_NTSC; 787 DRM_INFO("Default TV standard: NTSC\n"); 788 break; 789 case 2: 790 tv_std = TV_STD_PAL; 791 DRM_INFO("Default TV standard: PAL\n"); 792 break; 793 case 3: 794 tv_std = TV_STD_PAL_M; 795 DRM_INFO("Default TV standard: PAL-M\n"); 796 break; 797 case 4: 798 tv_std = TV_STD_PAL_60; 799 DRM_INFO("Default TV standard: PAL-60\n"); 800 break; 801 case 5: 802 tv_std = TV_STD_NTSC_J; 803 DRM_INFO("Default TV standard: NTSC-J\n"); 804 break; 805 case 6: 806 tv_std = TV_STD_SCART_PAL; 807 DRM_INFO("Default TV standard: SCART-PAL\n"); 808 break; 809 default: 810 tv_std = TV_STD_NTSC; 811 DRM_INFO 812 ("Unknown TV standard; defaulting to NTSC\n"); 813 break; 814 } 815 816 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) { 817 case 0: 818 DRM_INFO("29.498928713 MHz TV ref clk\n"); 819 break; 820 case 1: 821 DRM_INFO("28.636360000 MHz TV ref clk\n"); 822 break; 823 case 2: 824 DRM_INFO("14.318180000 MHz TV ref clk\n"); 825 break; 826 case 3: 827 DRM_INFO("27.000000000 MHz TV ref clk\n"); 828 break; 829 default: 830 break; 831 } 832 } 833 } 834 return tv_std; 835} 836 837static const uint32_t default_tvdac_adj[CHIP_LAST] = { 838 0x00000000, /* r100 */ 839 0x00280000, /* rv100 */ 840 0x00000000, /* rs100 */ 841 0x00880000, /* rv200 */ 842 0x00000000, /* rs200 */ 843 0x00000000, /* r200 */ 844 0x00770000, /* rv250 */ 845 0x00290000, /* rs300 */ 846 0x00560000, /* rv280 */ 847 0x00780000, /* r300 */ 848 0x00770000, /* r350 */ 849 0x00780000, /* rv350 */ 850 0x00780000, /* rv380 */ 851 0x01080000, /* r420 */ 852 0x01080000, /* r423 */ 853 0x01080000, /* rv410 */ 854 0x00780000, /* rs400 */ 855 0x00780000, /* rs480 */ 856}; 857 858static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev, 859 struct radeon_encoder_tv_dac *tv_dac) 860{ 861 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family]; 862 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250)) 863 tv_dac->ps2_tvdac_adj = 0x00880000; 864 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 865 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 866 return; 867} 868 869struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct 870 radeon_encoder 871 *encoder) 872{ 873 struct drm_device *dev = encoder->base.dev; 874 struct radeon_device *rdev = dev->dev_private; 875 uint16_t dac_info; 876 uint8_t rev, bg, dac; 877 struct radeon_encoder_tv_dac *tv_dac = NULL; 878 int found = 0; 879 880 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); 881 if (!tv_dac) 882 return NULL; 883 884 /* first check TV table */ 885 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 886 if (dac_info) { 887 rev = RBIOS8(dac_info + 0x3); 888 if (rev > 4) { 889 bg = RBIOS8(dac_info + 0xc) & 0xf; 890 dac = RBIOS8(dac_info + 0xd) & 0xf; 891 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 892 893 bg = RBIOS8(dac_info + 0xe) & 0xf; 894 dac = RBIOS8(dac_info + 0xf) & 0xf; 895 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 896 897 bg = RBIOS8(dac_info + 0x10) & 0xf; 898 dac = RBIOS8(dac_info + 0x11) & 0xf; 899 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 900 /* if the values are all zeros, use the table */ 901 if (tv_dac->ps2_tvdac_adj) 902 found = 1; 903 } else if (rev > 1) { 904 bg = RBIOS8(dac_info + 0xc) & 0xf; 905 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf; 906 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 907 908 bg = RBIOS8(dac_info + 0xd) & 0xf; 909 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf; 910 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 911 912 bg = RBIOS8(dac_info + 0xe) & 0xf; 913 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf; 914 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 915 /* if the values are all zeros, use the table */ 916 if (tv_dac->ps2_tvdac_adj) 917 found = 1; 918 } 919 tv_dac->tv_std = radeon_combios_get_tv_info(rdev); 920 } 921 if (!found) { 922 /* then check CRT table */ 923 dac_info = 924 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 925 if (dac_info) { 926 rev = RBIOS8(dac_info) & 0x3; 927 if (rev < 2) { 928 bg = RBIOS8(dac_info + 0x3) & 0xf; 929 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf; 930 tv_dac->ps2_tvdac_adj = 931 (bg << 16) | (dac << 20); 932 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 933 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 934 /* if the values are all zeros, use the table */ 935 if (tv_dac->ps2_tvdac_adj) 936 found = 1; 937 } else { 938 bg = RBIOS8(dac_info + 0x4) & 0xf; 939 dac = RBIOS8(dac_info + 0x5) & 0xf; 940 tv_dac->ps2_tvdac_adj = 941 (bg << 16) | (dac << 20); 942 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 943 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 944 /* if the values are all zeros, use the table */ 945 if (tv_dac->ps2_tvdac_adj) 946 found = 1; 947 } 948 } else { 949 DRM_INFO("No TV DAC info found in BIOS\n"); 950 } 951 } 952 953 if (!found) /* fallback to defaults */ 954 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac); 955 956 return tv_dac; 957} 958 959static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct 960 radeon_device 961 *rdev) 962{ 963 struct radeon_encoder_lvds *lvds = NULL; 964 uint32_t fp_vert_stretch, fp_horz_stretch; 965 uint32_t ppll_div_sel, ppll_val; 966 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); 967 968 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); 969 970 if (!lvds) 971 return NULL; 972 973 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH); 974 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH); 975 976 /* These should be fail-safe defaults, fingers crossed */ 977 lvds->panel_pwr_delay = 200; 978 lvds->panel_vcc_delay = 2000; 979 980 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 981 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf; 982 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf; 983 984 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) 985 lvds->native_mode.vdisplay = 986 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >> 987 RADEON_VERT_PANEL_SHIFT) + 1; 988 else 989 lvds->native_mode.vdisplay = 990 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1; 991 992 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE) 993 lvds->native_mode.hdisplay = 994 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >> 995 RADEON_HORZ_PANEL_SHIFT) + 1) * 8; 996 else 997 lvds->native_mode.hdisplay = 998 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8; 999 1000 if ((lvds->native_mode.hdisplay < 640) || 1001 (lvds->native_mode.vdisplay < 480)) { 1002 lvds->native_mode.hdisplay = 640; 1003 lvds->native_mode.vdisplay = 480; 1004 } 1005 1006 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; 1007 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel); 1008 if ((ppll_val & 0x000707ff) == 0x1bb) 1009 lvds->use_bios_dividers = false; 1010 else { 1011 lvds->panel_ref_divider = 1012 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; 1013 lvds->panel_post_divider = (ppll_val >> 16) & 0x7; 1014 lvds->panel_fb_divider = ppll_val & 0x7ff; 1015 1016 if ((lvds->panel_ref_divider != 0) && 1017 (lvds->panel_fb_divider > 3)) 1018 lvds->use_bios_dividers = true; 1019 } 1020 lvds->panel_vcc_delay = 200; 1021 1022 DRM_INFO("Panel info derived from registers\n"); 1023 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 1024 lvds->native_mode.vdisplay); 1025 1026 return lvds; 1027} 1028 1029struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder 1030 *encoder) 1031{ 1032 struct drm_device *dev = encoder->base.dev; 1033 struct radeon_device *rdev = dev->dev_private; 1034 uint16_t lcd_info; 1035 uint32_t panel_setup; 1036 char stmp[30]; 1037 int tmp, i; 1038 struct radeon_encoder_lvds *lvds = NULL; 1039 1040 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 1041 1042 if (lcd_info) { 1043 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); 1044 1045 if (!lvds) 1046 return NULL; 1047 1048 for (i = 0; i < 24; i++) 1049 stmp[i] = RBIOS8(lcd_info + i + 1); 1050 stmp[24] = 0; 1051 1052 DRM_INFO("Panel ID String: %s\n", stmp); 1053 1054 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19); 1055 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b); 1056 1057 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 1058 lvds->native_mode.vdisplay); 1059 1060 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c); 1061 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000); 1062 1063 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24); 1064 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf; 1065 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf; 1066 1067 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e); 1068 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30); 1069 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31); 1070 if ((lvds->panel_ref_divider != 0) && 1071 (lvds->panel_fb_divider > 3)) 1072 lvds->use_bios_dividers = true; 1073 1074 panel_setup = RBIOS32(lcd_info + 0x39); 1075 lvds->lvds_gen_cntl = 0xff00; 1076 if (panel_setup & 0x1) 1077 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT; 1078 1079 if ((panel_setup >> 4) & 0x1) 1080 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE; 1081 1082 switch ((panel_setup >> 8) & 0x7) { 1083 case 0: 1084 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM; 1085 break; 1086 case 1: 1087 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY; 1088 break; 1089 case 2: 1090 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY; 1091 break; 1092 default: 1093 break; 1094 } 1095 1096 if ((panel_setup >> 16) & 0x1) 1097 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW; 1098 1099 if ((panel_setup >> 17) & 0x1) 1100 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW; 1101 1102 if ((panel_setup >> 18) & 0x1) 1103 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW; 1104 1105 if ((panel_setup >> 23) & 0x1) 1106 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL; 1107 1108 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000); 1109 1110 for (i = 0; i < 32; i++) { 1111 tmp = RBIOS16(lcd_info + 64 + i * 2); 1112 if (tmp == 0) 1113 break; 1114 1115 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) && 1116 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) { 1117 lvds->native_mode.htotal = lvds->native_mode.hdisplay + 1118 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8; 1119 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + 1120 (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8; 1121 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + 1122 (RBIOS8(tmp + 23) * 8); 1123 1124 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + 1125 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26)); 1126 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + 1127 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26)); 1128 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + 1129 ((RBIOS16(tmp + 28) & 0xf800) >> 11); 1130 1131 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10; 1132 lvds->native_mode.flags = 0; 1133 /* set crtc values */ 1134 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); 1135 1136 } 1137 } 1138 } else { 1139 DRM_INFO("No panel info found in BIOS\n"); 1140 lvds = radeon_legacy_get_lvds_info_from_regs(rdev); 1141 } 1142 1143 if (lvds) 1144 encoder->native_mode = lvds->native_mode; 1145 return lvds; 1146} 1147 1148static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = { 1149 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */ 1150 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */ 1151 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */ 1152 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */ 1153 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */ 1154 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */ 1155 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */ 1156 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */ 1157 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */ 1158 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */ 1159 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */ 1160 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */ 1161 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */ 1162 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */ 1163 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */ 1164 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */ 1165 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */ 1166 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */ 1167}; 1168 1169bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 1170 struct radeon_encoder_int_tmds *tmds) 1171{ 1172 struct drm_device *dev = encoder->base.dev; 1173 struct radeon_device *rdev = dev->dev_private; 1174 int i; 1175 1176 for (i = 0; i < 4; i++) { 1177 tmds->tmds_pll[i].value = 1178 default_tmds_pll[rdev->family][i].value; 1179 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq; 1180 } 1181 1182 return true; 1183} 1184 1185bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 1186 struct radeon_encoder_int_tmds *tmds) 1187{ 1188 struct drm_device *dev = encoder->base.dev; 1189 struct radeon_device *rdev = dev->dev_private; 1190 uint16_t tmds_info; 1191 int i, n; 1192 uint8_t ver; 1193 1194 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 1195 1196 if (tmds_info) { 1197 ver = RBIOS8(tmds_info); 1198 DRM_INFO("DFP table revision: %d\n", ver); 1199 if (ver == 3) { 1200 n = RBIOS8(tmds_info + 5) + 1; 1201 if (n > 4) 1202 n = 4; 1203 for (i = 0; i < n; i++) { 1204 tmds->tmds_pll[i].value = 1205 RBIOS32(tmds_info + i * 10 + 0x08); 1206 tmds->tmds_pll[i].freq = 1207 RBIOS16(tmds_info + i * 10 + 0x10); 1208 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n", 1209 tmds->tmds_pll[i].freq, 1210 tmds->tmds_pll[i].value); 1211 } 1212 } else if (ver == 4) { 1213 int stride = 0; 1214 n = RBIOS8(tmds_info + 5) + 1; 1215 if (n > 4) 1216 n = 4; 1217 for (i = 0; i < n; i++) { 1218 tmds->tmds_pll[i].value = 1219 RBIOS32(tmds_info + stride + 0x08); 1220 tmds->tmds_pll[i].freq = 1221 RBIOS16(tmds_info + stride + 0x10); 1222 if (i == 0) 1223 stride += 10; 1224 else 1225 stride += 6; 1226 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n", 1227 tmds->tmds_pll[i].freq, 1228 tmds->tmds_pll[i].value); 1229 } 1230 } 1231 } else { 1232 DRM_INFO("No TMDS info found in BIOS\n"); 1233 return false; 1234 } 1235 return true; 1236} 1237 1238bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 1239 struct radeon_encoder_ext_tmds *tmds) 1240{ 1241 struct drm_device *dev = encoder->base.dev; 1242 struct radeon_device *rdev = dev->dev_private; 1243 struct radeon_i2c_bus_rec i2c_bus; 1244 1245 /* default for macs */ 1246 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1247 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1248 1249 /* XXX some macs have duallink chips */ 1250 switch (rdev->mode_info.connector_table) { 1251 case CT_POWERBOOK_EXTERNAL: 1252 case CT_MINI_EXTERNAL: 1253 default: 1254 tmds->dvo_chip = DVO_SIL164; 1255 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1256 break; 1257 } 1258 1259 return true; 1260} 1261 1262bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 1263 struct radeon_encoder_ext_tmds *tmds) 1264{ 1265 struct drm_device *dev = encoder->base.dev; 1266 struct radeon_device *rdev = dev->dev_private; 1267 uint16_t offset; 1268 uint8_t ver, id, blocks, clk, data; 1269 int i; 1270 enum radeon_combios_ddc gpio; 1271 struct radeon_i2c_bus_rec i2c_bus; 1272 1273 tmds->i2c_bus = NULL; 1274 if (rdev->flags & RADEON_IS_IGP) { 1275 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE); 1276 if (offset) { 1277 ver = RBIOS8(offset); 1278 DRM_INFO("GPIO Table revision: %d\n", ver); 1279 blocks = RBIOS8(offset + 2); 1280 for (i = 0; i < blocks; i++) { 1281 id = RBIOS8(offset + 3 + (i * 5) + 0); 1282 if (id == 136) { 1283 clk = RBIOS8(offset + 3 + (i * 5) + 3); 1284 data = RBIOS8(offset + 3 + (i * 5) + 4); 1285 i2c_bus.valid = true; 1286 i2c_bus.mask_clk_mask = (1 << clk); 1287 i2c_bus.mask_data_mask = (1 << data); 1288 i2c_bus.a_clk_mask = (1 << clk); 1289 i2c_bus.a_data_mask = (1 << data); 1290 i2c_bus.en_clk_mask = (1 << clk); 1291 i2c_bus.en_data_mask = (1 << data); 1292 i2c_bus.y_clk_mask = (1 << clk); 1293 i2c_bus.y_data_mask = (1 << data); 1294 i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK; 1295 i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK; 1296 i2c_bus.a_clk_reg = RADEON_GPIOPAD_A; 1297 i2c_bus.a_data_reg = RADEON_GPIOPAD_A; 1298 i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN; 1299 i2c_bus.en_data_reg = RADEON_GPIOPAD_EN; 1300 i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y; 1301 i2c_bus.y_data_reg = RADEON_GPIOPAD_Y; 1302 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1303 tmds->dvo_chip = DVO_SIL164; 1304 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1305 break; 1306 } 1307 } 1308 } 1309 } else { 1310 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 1311 if (offset) { 1312 ver = RBIOS8(offset); 1313 DRM_INFO("External TMDS Table revision: %d\n", ver); 1314 tmds->slave_addr = RBIOS8(offset + 4 + 2); 1315 tmds->slave_addr >>= 1; /* 7 bit addressing */ 1316 gpio = RBIOS8(offset + 4 + 3); 1317 switch (gpio) { 1318 case DDC_MONID: 1319 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1320 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1321 break; 1322 case DDC_DVI: 1323 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1324 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1325 break; 1326 case DDC_VGA: 1327 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1328 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1329 break; 1330 case DDC_CRT2: 1331 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */ 1332 if (rdev->family >= CHIP_R300) 1333 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1334 else 1335 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1336 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1337 break; 1338 case DDC_LCD: /* MM i2c */ 1339 i2c_bus.valid = true; 1340 i2c_bus.hw_capable = true; 1341 i2c_bus.mm_i2c = true; 1342 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1343 break; 1344 default: 1345 DRM_ERROR("Unsupported gpio %d\n", gpio); 1346 break; 1347 } 1348 } 1349 } 1350 1351 if (!tmds->i2c_bus) { 1352 DRM_INFO("No valid Ext TMDS info found in BIOS\n"); 1353 return false; 1354 } 1355 1356 return true; 1357} 1358 1359bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) 1360{ 1361 struct radeon_device *rdev = dev->dev_private; 1362 struct radeon_i2c_bus_rec ddc_i2c; 1363 struct radeon_hpd hpd; 1364 1365 rdev->mode_info.connector_table = radeon_connector_table; 1366 if (rdev->mode_info.connector_table == CT_NONE) { 1367#ifdef CONFIG_PPC_PMAC 1368 if (of_machine_is_compatible("PowerBook3,3")) { 1369 /* powerbook with VGA */ 1370 rdev->mode_info.connector_table = CT_POWERBOOK_VGA; 1371 } else if (of_machine_is_compatible("PowerBook3,4") || 1372 of_machine_is_compatible("PowerBook3,5")) { 1373 /* powerbook with internal tmds */ 1374 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL; 1375 } else if (of_machine_is_compatible("PowerBook5,1") || 1376 of_machine_is_compatible("PowerBook5,2") || 1377 of_machine_is_compatible("PowerBook5,3") || 1378 of_machine_is_compatible("PowerBook5,4") || 1379 of_machine_is_compatible("PowerBook5,5")) { 1380 /* powerbook with external single link tmds (sil164) */ 1381 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1382 } else if (of_machine_is_compatible("PowerBook5,6")) { 1383 /* powerbook with external dual or single link tmds */ 1384 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1385 } else if (of_machine_is_compatible("PowerBook5,7") || 1386 of_machine_is_compatible("PowerBook5,8") || 1387 of_machine_is_compatible("PowerBook5,9")) { 1388 /* PowerBook6,2 ? */ 1389 /* powerbook with external dual link tmds (sil1178?) */ 1390 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1391 } else if (of_machine_is_compatible("PowerBook4,1") || 1392 of_machine_is_compatible("PowerBook4,2") || 1393 of_machine_is_compatible("PowerBook4,3") || 1394 of_machine_is_compatible("PowerBook6,3") || 1395 of_machine_is_compatible("PowerBook6,5") || 1396 of_machine_is_compatible("PowerBook6,7")) { 1397 /* ibook */ 1398 rdev->mode_info.connector_table = CT_IBOOK; 1399 } else if (of_machine_is_compatible("PowerMac4,4")) { 1400 /* emac */ 1401 rdev->mode_info.connector_table = CT_EMAC; 1402 } else if (of_machine_is_compatible("PowerMac10,1")) { 1403 /* mini with internal tmds */ 1404 rdev->mode_info.connector_table = CT_MINI_INTERNAL; 1405 } else if (of_machine_is_compatible("PowerMac10,2")) { 1406 /* mini with external tmds */ 1407 rdev->mode_info.connector_table = CT_MINI_EXTERNAL; 1408 } else if (of_machine_is_compatible("PowerMac12,1")) { 1409 /* PowerMac8,1 ? */ 1410 /* imac g5 isight */ 1411 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT; 1412 } else 1413#endif /* CONFIG_PPC_PMAC */ 1414#ifdef CONFIG_PPC64 1415 if (ASIC_IS_RN50(rdev)) 1416 rdev->mode_info.connector_table = CT_RN50_POWER; 1417 else 1418#endif 1419 rdev->mode_info.connector_table = CT_GENERIC; 1420 } 1421 1422 switch (rdev->mode_info.connector_table) { 1423 case CT_GENERIC: 1424 DRM_INFO("Connector Table: %d (generic)\n", 1425 rdev->mode_info.connector_table); 1426 /* these are the most common settings */ 1427 if (rdev->flags & RADEON_SINGLE_CRTC) { 1428 /* VGA - primary dac */ 1429 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1430 hpd.hpd = RADEON_HPD_NONE; 1431 radeon_add_legacy_encoder(dev, 1432 radeon_get_encoder_id(dev, 1433 ATOM_DEVICE_CRT1_SUPPORT, 1434 1), 1435 ATOM_DEVICE_CRT1_SUPPORT); 1436 radeon_add_legacy_connector(dev, 0, 1437 ATOM_DEVICE_CRT1_SUPPORT, 1438 DRM_MODE_CONNECTOR_VGA, 1439 &ddc_i2c, 1440 CONNECTOR_OBJECT_ID_VGA, 1441 &hpd); 1442 } else if (rdev->flags & RADEON_IS_MOBILITY) { 1443 /* LVDS */ 1444 ddc_i2c = combios_setup_i2c_bus(rdev, 0); 1445 hpd.hpd = RADEON_HPD_NONE; 1446 radeon_add_legacy_encoder(dev, 1447 radeon_get_encoder_id(dev, 1448 ATOM_DEVICE_LCD1_SUPPORT, 1449 0), 1450 ATOM_DEVICE_LCD1_SUPPORT); 1451 radeon_add_legacy_connector(dev, 0, 1452 ATOM_DEVICE_LCD1_SUPPORT, 1453 DRM_MODE_CONNECTOR_LVDS, 1454 &ddc_i2c, 1455 CONNECTOR_OBJECT_ID_LVDS, 1456 &hpd); 1457 1458 /* VGA - primary dac */ 1459 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1460 hpd.hpd = RADEON_HPD_NONE; 1461 radeon_add_legacy_encoder(dev, 1462 radeon_get_encoder_id(dev, 1463 ATOM_DEVICE_CRT1_SUPPORT, 1464 1), 1465 ATOM_DEVICE_CRT1_SUPPORT); 1466 radeon_add_legacy_connector(dev, 1, 1467 ATOM_DEVICE_CRT1_SUPPORT, 1468 DRM_MODE_CONNECTOR_VGA, 1469 &ddc_i2c, 1470 CONNECTOR_OBJECT_ID_VGA, 1471 &hpd); 1472 } else { 1473 /* DVI-I - tv dac, int tmds */ 1474 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1475 hpd.hpd = RADEON_HPD_1; 1476 radeon_add_legacy_encoder(dev, 1477 radeon_get_encoder_id(dev, 1478 ATOM_DEVICE_DFP1_SUPPORT, 1479 0), 1480 ATOM_DEVICE_DFP1_SUPPORT); 1481 radeon_add_legacy_encoder(dev, 1482 radeon_get_encoder_id(dev, 1483 ATOM_DEVICE_CRT2_SUPPORT, 1484 2), 1485 ATOM_DEVICE_CRT2_SUPPORT); 1486 radeon_add_legacy_connector(dev, 0, 1487 ATOM_DEVICE_DFP1_SUPPORT | 1488 ATOM_DEVICE_CRT2_SUPPORT, 1489 DRM_MODE_CONNECTOR_DVII, 1490 &ddc_i2c, 1491 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1492 &hpd); 1493 1494 /* VGA - primary dac */ 1495 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1496 hpd.hpd = RADEON_HPD_NONE; 1497 radeon_add_legacy_encoder(dev, 1498 radeon_get_encoder_id(dev, 1499 ATOM_DEVICE_CRT1_SUPPORT, 1500 1), 1501 ATOM_DEVICE_CRT1_SUPPORT); 1502 radeon_add_legacy_connector(dev, 1, 1503 ATOM_DEVICE_CRT1_SUPPORT, 1504 DRM_MODE_CONNECTOR_VGA, 1505 &ddc_i2c, 1506 CONNECTOR_OBJECT_ID_VGA, 1507 &hpd); 1508 } 1509 1510 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 1511 /* TV - tv dac */ 1512 ddc_i2c.valid = false; 1513 hpd.hpd = RADEON_HPD_NONE; 1514 radeon_add_legacy_encoder(dev, 1515 radeon_get_encoder_id(dev, 1516 ATOM_DEVICE_TV1_SUPPORT, 1517 2), 1518 ATOM_DEVICE_TV1_SUPPORT); 1519 radeon_add_legacy_connector(dev, 2, 1520 ATOM_DEVICE_TV1_SUPPORT, 1521 DRM_MODE_CONNECTOR_SVIDEO, 1522 &ddc_i2c, 1523 CONNECTOR_OBJECT_ID_SVIDEO, 1524 &hpd); 1525 } 1526 break; 1527 case CT_IBOOK: 1528 DRM_INFO("Connector Table: %d (ibook)\n", 1529 rdev->mode_info.connector_table); 1530 /* LVDS */ 1531 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1532 hpd.hpd = RADEON_HPD_NONE; 1533 radeon_add_legacy_encoder(dev, 1534 radeon_get_encoder_id(dev, 1535 ATOM_DEVICE_LCD1_SUPPORT, 1536 0), 1537 ATOM_DEVICE_LCD1_SUPPORT); 1538 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1539 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1540 CONNECTOR_OBJECT_ID_LVDS, 1541 &hpd); 1542 /* VGA - TV DAC */ 1543 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1544 hpd.hpd = RADEON_HPD_NONE; 1545 radeon_add_legacy_encoder(dev, 1546 radeon_get_encoder_id(dev, 1547 ATOM_DEVICE_CRT2_SUPPORT, 1548 2), 1549 ATOM_DEVICE_CRT2_SUPPORT); 1550 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1551 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1552 CONNECTOR_OBJECT_ID_VGA, 1553 &hpd); 1554 /* TV - TV DAC */ 1555 ddc_i2c.valid = false; 1556 hpd.hpd = RADEON_HPD_NONE; 1557 radeon_add_legacy_encoder(dev, 1558 radeon_get_encoder_id(dev, 1559 ATOM_DEVICE_TV1_SUPPORT, 1560 2), 1561 ATOM_DEVICE_TV1_SUPPORT); 1562 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1563 DRM_MODE_CONNECTOR_SVIDEO, 1564 &ddc_i2c, 1565 CONNECTOR_OBJECT_ID_SVIDEO, 1566 &hpd); 1567 break; 1568 case CT_POWERBOOK_EXTERNAL: 1569 DRM_INFO("Connector Table: %d (powerbook external tmds)\n", 1570 rdev->mode_info.connector_table); 1571 /* LVDS */ 1572 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1573 hpd.hpd = RADEON_HPD_NONE; 1574 radeon_add_legacy_encoder(dev, 1575 radeon_get_encoder_id(dev, 1576 ATOM_DEVICE_LCD1_SUPPORT, 1577 0), 1578 ATOM_DEVICE_LCD1_SUPPORT); 1579 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1580 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1581 CONNECTOR_OBJECT_ID_LVDS, 1582 &hpd); 1583 /* DVI-I - primary dac, ext tmds */ 1584 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1585 hpd.hpd = RADEON_HPD_2; /* ??? */ 1586 radeon_add_legacy_encoder(dev, 1587 radeon_get_encoder_id(dev, 1588 ATOM_DEVICE_DFP2_SUPPORT, 1589 0), 1590 ATOM_DEVICE_DFP2_SUPPORT); 1591 radeon_add_legacy_encoder(dev, 1592 radeon_get_encoder_id(dev, 1593 ATOM_DEVICE_CRT1_SUPPORT, 1594 1), 1595 ATOM_DEVICE_CRT1_SUPPORT); 1596 /* XXX some are SL */ 1597 radeon_add_legacy_connector(dev, 1, 1598 ATOM_DEVICE_DFP2_SUPPORT | 1599 ATOM_DEVICE_CRT1_SUPPORT, 1600 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1601 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, 1602 &hpd); 1603 /* TV - TV DAC */ 1604 ddc_i2c.valid = false; 1605 hpd.hpd = RADEON_HPD_NONE; 1606 radeon_add_legacy_encoder(dev, 1607 radeon_get_encoder_id(dev, 1608 ATOM_DEVICE_TV1_SUPPORT, 1609 2), 1610 ATOM_DEVICE_TV1_SUPPORT); 1611 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1612 DRM_MODE_CONNECTOR_SVIDEO, 1613 &ddc_i2c, 1614 CONNECTOR_OBJECT_ID_SVIDEO, 1615 &hpd); 1616 break; 1617 case CT_POWERBOOK_INTERNAL: 1618 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n", 1619 rdev->mode_info.connector_table); 1620 /* LVDS */ 1621 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1622 hpd.hpd = RADEON_HPD_NONE; 1623 radeon_add_legacy_encoder(dev, 1624 radeon_get_encoder_id(dev, 1625 ATOM_DEVICE_LCD1_SUPPORT, 1626 0), 1627 ATOM_DEVICE_LCD1_SUPPORT); 1628 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1629 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1630 CONNECTOR_OBJECT_ID_LVDS, 1631 &hpd); 1632 /* DVI-I - primary dac, int tmds */ 1633 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1634 hpd.hpd = RADEON_HPD_1; /* ??? */ 1635 radeon_add_legacy_encoder(dev, 1636 radeon_get_encoder_id(dev, 1637 ATOM_DEVICE_DFP1_SUPPORT, 1638 0), 1639 ATOM_DEVICE_DFP1_SUPPORT); 1640 radeon_add_legacy_encoder(dev, 1641 radeon_get_encoder_id(dev, 1642 ATOM_DEVICE_CRT1_SUPPORT, 1643 1), 1644 ATOM_DEVICE_CRT1_SUPPORT); 1645 radeon_add_legacy_connector(dev, 1, 1646 ATOM_DEVICE_DFP1_SUPPORT | 1647 ATOM_DEVICE_CRT1_SUPPORT, 1648 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1649 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1650 &hpd); 1651 /* TV - TV DAC */ 1652 ddc_i2c.valid = false; 1653 hpd.hpd = RADEON_HPD_NONE; 1654 radeon_add_legacy_encoder(dev, 1655 radeon_get_encoder_id(dev, 1656 ATOM_DEVICE_TV1_SUPPORT, 1657 2), 1658 ATOM_DEVICE_TV1_SUPPORT); 1659 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1660 DRM_MODE_CONNECTOR_SVIDEO, 1661 &ddc_i2c, 1662 CONNECTOR_OBJECT_ID_SVIDEO, 1663 &hpd); 1664 break; 1665 case CT_POWERBOOK_VGA: 1666 DRM_INFO("Connector Table: %d (powerbook vga)\n", 1667 rdev->mode_info.connector_table); 1668 /* LVDS */ 1669 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1670 hpd.hpd = RADEON_HPD_NONE; 1671 radeon_add_legacy_encoder(dev, 1672 radeon_get_encoder_id(dev, 1673 ATOM_DEVICE_LCD1_SUPPORT, 1674 0), 1675 ATOM_DEVICE_LCD1_SUPPORT); 1676 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1677 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1678 CONNECTOR_OBJECT_ID_LVDS, 1679 &hpd); 1680 /* VGA - primary dac */ 1681 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1682 hpd.hpd = RADEON_HPD_NONE; 1683 radeon_add_legacy_encoder(dev, 1684 radeon_get_encoder_id(dev, 1685 ATOM_DEVICE_CRT1_SUPPORT, 1686 1), 1687 ATOM_DEVICE_CRT1_SUPPORT); 1688 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, 1689 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1690 CONNECTOR_OBJECT_ID_VGA, 1691 &hpd); 1692 /* TV - TV DAC */ 1693 ddc_i2c.valid = false; 1694 hpd.hpd = RADEON_HPD_NONE; 1695 radeon_add_legacy_encoder(dev, 1696 radeon_get_encoder_id(dev, 1697 ATOM_DEVICE_TV1_SUPPORT, 1698 2), 1699 ATOM_DEVICE_TV1_SUPPORT); 1700 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1701 DRM_MODE_CONNECTOR_SVIDEO, 1702 &ddc_i2c, 1703 CONNECTOR_OBJECT_ID_SVIDEO, 1704 &hpd); 1705 break; 1706 case CT_MINI_EXTERNAL: 1707 DRM_INFO("Connector Table: %d (mini external tmds)\n", 1708 rdev->mode_info.connector_table); 1709 /* DVI-I - tv dac, ext tmds */ 1710 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1711 hpd.hpd = RADEON_HPD_2; /* ??? */ 1712 radeon_add_legacy_encoder(dev, 1713 radeon_get_encoder_id(dev, 1714 ATOM_DEVICE_DFP2_SUPPORT, 1715 0), 1716 ATOM_DEVICE_DFP2_SUPPORT); 1717 radeon_add_legacy_encoder(dev, 1718 radeon_get_encoder_id(dev, 1719 ATOM_DEVICE_CRT2_SUPPORT, 1720 2), 1721 ATOM_DEVICE_CRT2_SUPPORT); 1722 /* XXX are any DL? */ 1723 radeon_add_legacy_connector(dev, 0, 1724 ATOM_DEVICE_DFP2_SUPPORT | 1725 ATOM_DEVICE_CRT2_SUPPORT, 1726 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1727 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1728 &hpd); 1729 /* TV - TV DAC */ 1730 ddc_i2c.valid = false; 1731 hpd.hpd = RADEON_HPD_NONE; 1732 radeon_add_legacy_encoder(dev, 1733 radeon_get_encoder_id(dev, 1734 ATOM_DEVICE_TV1_SUPPORT, 1735 2), 1736 ATOM_DEVICE_TV1_SUPPORT); 1737 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1738 DRM_MODE_CONNECTOR_SVIDEO, 1739 &ddc_i2c, 1740 CONNECTOR_OBJECT_ID_SVIDEO, 1741 &hpd); 1742 break; 1743 case CT_MINI_INTERNAL: 1744 DRM_INFO("Connector Table: %d (mini internal tmds)\n", 1745 rdev->mode_info.connector_table); 1746 /* DVI-I - tv dac, int tmds */ 1747 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1748 hpd.hpd = RADEON_HPD_1; /* ??? */ 1749 radeon_add_legacy_encoder(dev, 1750 radeon_get_encoder_id(dev, 1751 ATOM_DEVICE_DFP1_SUPPORT, 1752 0), 1753 ATOM_DEVICE_DFP1_SUPPORT); 1754 radeon_add_legacy_encoder(dev, 1755 radeon_get_encoder_id(dev, 1756 ATOM_DEVICE_CRT2_SUPPORT, 1757 2), 1758 ATOM_DEVICE_CRT2_SUPPORT); 1759 radeon_add_legacy_connector(dev, 0, 1760 ATOM_DEVICE_DFP1_SUPPORT | 1761 ATOM_DEVICE_CRT2_SUPPORT, 1762 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1763 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1764 &hpd); 1765 /* TV - TV DAC */ 1766 ddc_i2c.valid = false; 1767 hpd.hpd = RADEON_HPD_NONE; 1768 radeon_add_legacy_encoder(dev, 1769 radeon_get_encoder_id(dev, 1770 ATOM_DEVICE_TV1_SUPPORT, 1771 2), 1772 ATOM_DEVICE_TV1_SUPPORT); 1773 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1774 DRM_MODE_CONNECTOR_SVIDEO, 1775 &ddc_i2c, 1776 CONNECTOR_OBJECT_ID_SVIDEO, 1777 &hpd); 1778 break; 1779 case CT_IMAC_G5_ISIGHT: 1780 DRM_INFO("Connector Table: %d (imac g5 isight)\n", 1781 rdev->mode_info.connector_table); 1782 /* DVI-D - int tmds */ 1783 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1784 hpd.hpd = RADEON_HPD_1; /* ??? */ 1785 radeon_add_legacy_encoder(dev, 1786 radeon_get_encoder_id(dev, 1787 ATOM_DEVICE_DFP1_SUPPORT, 1788 0), 1789 ATOM_DEVICE_DFP1_SUPPORT); 1790 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT, 1791 DRM_MODE_CONNECTOR_DVID, &ddc_i2c, 1792 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 1793 &hpd); 1794 /* VGA - tv dac */ 1795 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1796 hpd.hpd = RADEON_HPD_NONE; 1797 radeon_add_legacy_encoder(dev, 1798 radeon_get_encoder_id(dev, 1799 ATOM_DEVICE_CRT2_SUPPORT, 1800 2), 1801 ATOM_DEVICE_CRT2_SUPPORT); 1802 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1803 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1804 CONNECTOR_OBJECT_ID_VGA, 1805 &hpd); 1806 /* TV - TV DAC */ 1807 ddc_i2c.valid = false; 1808 hpd.hpd = RADEON_HPD_NONE; 1809 radeon_add_legacy_encoder(dev, 1810 radeon_get_encoder_id(dev, 1811 ATOM_DEVICE_TV1_SUPPORT, 1812 2), 1813 ATOM_DEVICE_TV1_SUPPORT); 1814 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1815 DRM_MODE_CONNECTOR_SVIDEO, 1816 &ddc_i2c, 1817 CONNECTOR_OBJECT_ID_SVIDEO, 1818 &hpd); 1819 break; 1820 case CT_EMAC: 1821 DRM_INFO("Connector Table: %d (emac)\n", 1822 rdev->mode_info.connector_table); 1823 /* VGA - primary dac */ 1824 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1825 hpd.hpd = RADEON_HPD_NONE; 1826 radeon_add_legacy_encoder(dev, 1827 radeon_get_encoder_id(dev, 1828 ATOM_DEVICE_CRT1_SUPPORT, 1829 1), 1830 ATOM_DEVICE_CRT1_SUPPORT); 1831 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, 1832 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1833 CONNECTOR_OBJECT_ID_VGA, 1834 &hpd); 1835 /* VGA - tv dac */ 1836 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1837 hpd.hpd = RADEON_HPD_NONE; 1838 radeon_add_legacy_encoder(dev, 1839 radeon_get_encoder_id(dev, 1840 ATOM_DEVICE_CRT2_SUPPORT, 1841 2), 1842 ATOM_DEVICE_CRT2_SUPPORT); 1843 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1844 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1845 CONNECTOR_OBJECT_ID_VGA, 1846 &hpd); 1847 /* TV - TV DAC */ 1848 ddc_i2c.valid = false; 1849 hpd.hpd = RADEON_HPD_NONE; 1850 radeon_add_legacy_encoder(dev, 1851 radeon_get_encoder_id(dev, 1852 ATOM_DEVICE_TV1_SUPPORT, 1853 2), 1854 ATOM_DEVICE_TV1_SUPPORT); 1855 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1856 DRM_MODE_CONNECTOR_SVIDEO, 1857 &ddc_i2c, 1858 CONNECTOR_OBJECT_ID_SVIDEO, 1859 &hpd); 1860 break; 1861 case CT_RN50_POWER: 1862 DRM_INFO("Connector Table: %d (rn50-power)\n", 1863 rdev->mode_info.connector_table); 1864 /* VGA - primary dac */ 1865 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1866 hpd.hpd = RADEON_HPD_NONE; 1867 radeon_add_legacy_encoder(dev, 1868 radeon_get_encoder_id(dev, 1869 ATOM_DEVICE_CRT1_SUPPORT, 1870 1), 1871 ATOM_DEVICE_CRT1_SUPPORT); 1872 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, 1873 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1874 CONNECTOR_OBJECT_ID_VGA, 1875 &hpd); 1876 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1877 hpd.hpd = RADEON_HPD_NONE; 1878 radeon_add_legacy_encoder(dev, 1879 radeon_get_encoder_id(dev, 1880 ATOM_DEVICE_CRT2_SUPPORT, 1881 2), 1882 ATOM_DEVICE_CRT2_SUPPORT); 1883 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1884 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1885 CONNECTOR_OBJECT_ID_VGA, 1886 &hpd); 1887 break; 1888 default: 1889 DRM_INFO("Connector table: %d (invalid)\n", 1890 rdev->mode_info.connector_table); 1891 return false; 1892 } 1893 1894 radeon_link_encoder_connector(dev); 1895 1896 return true; 1897} 1898 1899static bool radeon_apply_legacy_quirks(struct drm_device *dev, 1900 int bios_index, 1901 enum radeon_combios_connector 1902 *legacy_connector, 1903 struct radeon_i2c_bus_rec *ddc_i2c, 1904 struct radeon_hpd *hpd) 1905{ 1906 struct radeon_device *rdev = dev->dev_private; 1907 1908 /* XPRESS DDC quirks */ 1909 if ((rdev->family == CHIP_RS400 || 1910 rdev->family == CHIP_RS480) && 1911 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) 1912 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1913 else if ((rdev->family == CHIP_RS400 || 1914 rdev->family == CHIP_RS480) && 1915 ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) { 1916 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK); 1917 ddc_i2c->mask_clk_mask = (0x20 << 8); 1918 ddc_i2c->mask_data_mask = 0x80; 1919 ddc_i2c->a_clk_mask = (0x20 << 8); 1920 ddc_i2c->a_data_mask = 0x80; 1921 ddc_i2c->en_clk_mask = (0x20 << 8); 1922 ddc_i2c->en_data_mask = 0x80; 1923 ddc_i2c->y_clk_mask = (0x20 << 8); 1924 ddc_i2c->y_data_mask = 0x80; 1925 } 1926 1927 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */ 1928 if ((rdev->family >= CHIP_R300) && 1929 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) 1930 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1931 1932 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, 1933 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ 1934 if (dev->pdev->device == 0x515e && 1935 dev->pdev->subsystem_vendor == 0x1014) { 1936 if (*legacy_connector == CONNECTOR_CRT_LEGACY && 1937 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) 1938 return false; 1939 } 1940 1941 /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */ 1942 if (dev->pdev->device == 0x5159 && 1943 dev->pdev->subsystem_vendor == 0x1002 && 1944 dev->pdev->subsystem_device == 0x013a) { 1945 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY) 1946 *legacy_connector = CONNECTOR_CRT_LEGACY; 1947 1948 } 1949 1950 /* X300 card with extra non-existent DVI port */ 1951 if (dev->pdev->device == 0x5B60 && 1952 dev->pdev->subsystem_vendor == 0x17af && 1953 dev->pdev->subsystem_device == 0x201e && bios_index == 2) { 1954 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY) 1955 return false; 1956 } 1957 1958 return true; 1959} 1960 1961static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev) 1962{ 1963 /* Acer 5102 has non-existent TV port */ 1964 if (dev->pdev->device == 0x5975 && 1965 dev->pdev->subsystem_vendor == 0x1025 && 1966 dev->pdev->subsystem_device == 0x009f) 1967 return false; 1968 1969 /* HP dc5750 has non-existent TV port */ 1970 if (dev->pdev->device == 0x5974 && 1971 dev->pdev->subsystem_vendor == 0x103c && 1972 dev->pdev->subsystem_device == 0x280a) 1973 return false; 1974 1975 /* MSI S270 has non-existent TV port */ 1976 if (dev->pdev->device == 0x5955 && 1977 dev->pdev->subsystem_vendor == 0x1462 && 1978 dev->pdev->subsystem_device == 0x0131) 1979 return false; 1980 1981 return true; 1982} 1983 1984static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d) 1985{ 1986 struct radeon_device *rdev = dev->dev_private; 1987 uint32_t ext_tmds_info; 1988 1989 if (rdev->flags & RADEON_IS_IGP) { 1990 if (is_dvi_d) 1991 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 1992 else 1993 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 1994 } 1995 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 1996 if (ext_tmds_info) { 1997 uint8_t rev = RBIOS8(ext_tmds_info); 1998 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5); 1999 if (rev >= 3) { 2000 if (is_dvi_d) 2001 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 2002 else 2003 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 2004 } else { 2005 if (flags & 1) { 2006 if (is_dvi_d) 2007 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 2008 else 2009 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 2010 } 2011 } 2012 } 2013 if (is_dvi_d) 2014 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 2015 else 2016 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2017} 2018 2019bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) 2020{ 2021 struct radeon_device *rdev = dev->dev_private; 2022 uint32_t conn_info, entry, devices; 2023 uint16_t tmp, connector_object_id; 2024 enum radeon_combios_ddc ddc_type; 2025 enum radeon_combios_connector connector; 2026 int i = 0; 2027 struct radeon_i2c_bus_rec ddc_i2c; 2028 struct radeon_hpd hpd; 2029 2030 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE); 2031 if (conn_info) { 2032 for (i = 0; i < 4; i++) { 2033 entry = conn_info + 2 + i * 2; 2034 2035 if (!RBIOS16(entry)) 2036 break; 2037 2038 tmp = RBIOS16(entry); 2039 2040 connector = (tmp >> 12) & 0xf; 2041 2042 ddc_type = (tmp >> 8) & 0xf; 2043 switch (ddc_type) { 2044 case DDC_MONID: 2045 ddc_i2c = 2046 combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 2047 break; 2048 case DDC_DVI: 2049 ddc_i2c = 2050 combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 2051 break; 2052 case DDC_VGA: 2053 ddc_i2c = 2054 combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 2055 break; 2056 case DDC_CRT2: 2057 ddc_i2c = 2058 combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 2059 break; 2060 default: 2061 ddc_i2c.valid = false; 2062 break; 2063 } 2064 2065 switch (connector) { 2066 case CONNECTOR_PROPRIETARY_LEGACY: 2067 case CONNECTOR_DVI_I_LEGACY: 2068 case CONNECTOR_DVI_D_LEGACY: 2069 if ((tmp >> 4) & 0x1) 2070 hpd.hpd = RADEON_HPD_2; 2071 else 2072 hpd.hpd = RADEON_HPD_1; 2073 break; 2074 default: 2075 hpd.hpd = RADEON_HPD_NONE; 2076 break; 2077 } 2078 2079 if (!radeon_apply_legacy_quirks(dev, i, &connector, 2080 &ddc_i2c, &hpd)) 2081 continue; 2082 2083 switch (connector) { 2084 case CONNECTOR_PROPRIETARY_LEGACY: 2085 if ((tmp >> 4) & 0x1) 2086 devices = ATOM_DEVICE_DFP2_SUPPORT; 2087 else 2088 devices = ATOM_DEVICE_DFP1_SUPPORT; 2089 radeon_add_legacy_encoder(dev, 2090 radeon_get_encoder_id 2091 (dev, devices, 0), 2092 devices); 2093 radeon_add_legacy_connector(dev, i, devices, 2094 legacy_connector_convert 2095 [connector], 2096 &ddc_i2c, 2097 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 2098 &hpd); 2099 break; 2100 case CONNECTOR_CRT_LEGACY: 2101 if (tmp & 0x1) { 2102 devices = ATOM_DEVICE_CRT2_SUPPORT; 2103 radeon_add_legacy_encoder(dev, 2104 radeon_get_encoder_id 2105 (dev, 2106 ATOM_DEVICE_CRT2_SUPPORT, 2107 2), 2108 ATOM_DEVICE_CRT2_SUPPORT); 2109 } else { 2110 devices = ATOM_DEVICE_CRT1_SUPPORT; 2111 radeon_add_legacy_encoder(dev, 2112 radeon_get_encoder_id 2113 (dev, 2114 ATOM_DEVICE_CRT1_SUPPORT, 2115 1), 2116 ATOM_DEVICE_CRT1_SUPPORT); 2117 } 2118 radeon_add_legacy_connector(dev, 2119 i, 2120 devices, 2121 legacy_connector_convert 2122 [connector], 2123 &ddc_i2c, 2124 CONNECTOR_OBJECT_ID_VGA, 2125 &hpd); 2126 break; 2127 case CONNECTOR_DVI_I_LEGACY: 2128 devices = 0; 2129 if (tmp & 0x1) { 2130 devices |= ATOM_DEVICE_CRT2_SUPPORT; 2131 radeon_add_legacy_encoder(dev, 2132 radeon_get_encoder_id 2133 (dev, 2134 ATOM_DEVICE_CRT2_SUPPORT, 2135 2), 2136 ATOM_DEVICE_CRT2_SUPPORT); 2137 } else { 2138 devices |= ATOM_DEVICE_CRT1_SUPPORT; 2139 radeon_add_legacy_encoder(dev, 2140 radeon_get_encoder_id 2141 (dev, 2142 ATOM_DEVICE_CRT1_SUPPORT, 2143 1), 2144 ATOM_DEVICE_CRT1_SUPPORT); 2145 } 2146 if ((tmp >> 4) & 0x1) { 2147 devices |= ATOM_DEVICE_DFP2_SUPPORT; 2148 radeon_add_legacy_encoder(dev, 2149 radeon_get_encoder_id 2150 (dev, 2151 ATOM_DEVICE_DFP2_SUPPORT, 2152 0), 2153 ATOM_DEVICE_DFP2_SUPPORT); 2154 connector_object_id = combios_check_dl_dvi(dev, 0); 2155 } else { 2156 devices |= ATOM_DEVICE_DFP1_SUPPORT; 2157 radeon_add_legacy_encoder(dev, 2158 radeon_get_encoder_id 2159 (dev, 2160 ATOM_DEVICE_DFP1_SUPPORT, 2161 0), 2162 ATOM_DEVICE_DFP1_SUPPORT); 2163 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2164 } 2165 radeon_add_legacy_connector(dev, 2166 i, 2167 devices, 2168 legacy_connector_convert 2169 [connector], 2170 &ddc_i2c, 2171 connector_object_id, 2172 &hpd); 2173 break; 2174 case CONNECTOR_DVI_D_LEGACY: 2175 if ((tmp >> 4) & 0x1) { 2176 devices = ATOM_DEVICE_DFP2_SUPPORT; 2177 connector_object_id = combios_check_dl_dvi(dev, 1); 2178 } else { 2179 devices = ATOM_DEVICE_DFP1_SUPPORT; 2180 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2181 } 2182 radeon_add_legacy_encoder(dev, 2183 radeon_get_encoder_id 2184 (dev, devices, 0), 2185 devices); 2186 radeon_add_legacy_connector(dev, i, devices, 2187 legacy_connector_convert 2188 [connector], 2189 &ddc_i2c, 2190 connector_object_id, 2191 &hpd); 2192 break; 2193 case CONNECTOR_CTV_LEGACY: 2194 case CONNECTOR_STV_LEGACY: 2195 radeon_add_legacy_encoder(dev, 2196 radeon_get_encoder_id 2197 (dev, 2198 ATOM_DEVICE_TV1_SUPPORT, 2199 2), 2200 ATOM_DEVICE_TV1_SUPPORT); 2201 radeon_add_legacy_connector(dev, i, 2202 ATOM_DEVICE_TV1_SUPPORT, 2203 legacy_connector_convert 2204 [connector], 2205 &ddc_i2c, 2206 CONNECTOR_OBJECT_ID_SVIDEO, 2207 &hpd); 2208 break; 2209 default: 2210 DRM_ERROR("Unknown connector type: %d\n", 2211 connector); 2212 continue; 2213 } 2214 2215 } 2216 } else { 2217 uint16_t tmds_info = 2218 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 2219 if (tmds_info) { 2220 DRM_DEBUG("Found DFP table, assuming DVI connector\n"); 2221 2222 radeon_add_legacy_encoder(dev, 2223 radeon_get_encoder_id(dev, 2224 ATOM_DEVICE_CRT1_SUPPORT, 2225 1), 2226 ATOM_DEVICE_CRT1_SUPPORT); 2227 radeon_add_legacy_encoder(dev, 2228 radeon_get_encoder_id(dev, 2229 ATOM_DEVICE_DFP1_SUPPORT, 2230 0), 2231 ATOM_DEVICE_DFP1_SUPPORT); 2232 2233 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 2234 hpd.hpd = RADEON_HPD_1; 2235 radeon_add_legacy_connector(dev, 2236 0, 2237 ATOM_DEVICE_CRT1_SUPPORT | 2238 ATOM_DEVICE_DFP1_SUPPORT, 2239 DRM_MODE_CONNECTOR_DVII, 2240 &ddc_i2c, 2241 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2242 &hpd); 2243 } else { 2244 uint16_t crt_info = 2245 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 2246 DRM_DEBUG("Found CRT table, assuming VGA connector\n"); 2247 if (crt_info) { 2248 radeon_add_legacy_encoder(dev, 2249 radeon_get_encoder_id(dev, 2250 ATOM_DEVICE_CRT1_SUPPORT, 2251 1), 2252 ATOM_DEVICE_CRT1_SUPPORT); 2253 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 2254 hpd.hpd = RADEON_HPD_NONE; 2255 radeon_add_legacy_connector(dev, 2256 0, 2257 ATOM_DEVICE_CRT1_SUPPORT, 2258 DRM_MODE_CONNECTOR_VGA, 2259 &ddc_i2c, 2260 CONNECTOR_OBJECT_ID_VGA, 2261 &hpd); 2262 } else { 2263 DRM_DEBUG("No connector info found\n"); 2264 return false; 2265 } 2266 } 2267 } 2268 2269 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) { 2270 uint16_t lcd_info = 2271 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 2272 if (lcd_info) { 2273 uint16_t lcd_ddc_info = 2274 combios_get_table_offset(dev, 2275 COMBIOS_LCD_DDC_INFO_TABLE); 2276 2277 radeon_add_legacy_encoder(dev, 2278 radeon_get_encoder_id(dev, 2279 ATOM_DEVICE_LCD1_SUPPORT, 2280 0), 2281 ATOM_DEVICE_LCD1_SUPPORT); 2282 2283 if (lcd_ddc_info) { 2284 ddc_type = RBIOS8(lcd_ddc_info + 2); 2285 switch (ddc_type) { 2286 case DDC_MONID: 2287 ddc_i2c = 2288 combios_setup_i2c_bus 2289 (rdev, RADEON_GPIO_MONID); 2290 break; 2291 case DDC_DVI: 2292 ddc_i2c = 2293 combios_setup_i2c_bus 2294 (rdev, RADEON_GPIO_DVI_DDC); 2295 break; 2296 case DDC_VGA: 2297 ddc_i2c = 2298 combios_setup_i2c_bus 2299 (rdev, RADEON_GPIO_VGA_DDC); 2300 break; 2301 case DDC_CRT2: 2302 ddc_i2c = 2303 combios_setup_i2c_bus 2304 (rdev, RADEON_GPIO_CRT2_DDC); 2305 break; 2306 case DDC_LCD: 2307 ddc_i2c = 2308 combios_setup_i2c_bus 2309 (rdev, RADEON_GPIOPAD_MASK); 2310 ddc_i2c.mask_clk_mask = 2311 RBIOS32(lcd_ddc_info + 3); 2312 ddc_i2c.mask_data_mask = 2313 RBIOS32(lcd_ddc_info + 7); 2314 ddc_i2c.a_clk_mask = 2315 RBIOS32(lcd_ddc_info + 3); 2316 ddc_i2c.a_data_mask = 2317 RBIOS32(lcd_ddc_info + 7); 2318 ddc_i2c.en_clk_mask = 2319 RBIOS32(lcd_ddc_info + 3); 2320 ddc_i2c.en_data_mask = 2321 RBIOS32(lcd_ddc_info + 7); 2322 ddc_i2c.y_clk_mask = 2323 RBIOS32(lcd_ddc_info + 3); 2324 ddc_i2c.y_data_mask = 2325 RBIOS32(lcd_ddc_info + 7); 2326 break; 2327 case DDC_GPIO: 2328 ddc_i2c = 2329 combios_setup_i2c_bus 2330 (rdev, RADEON_MDGPIO_MASK); 2331 ddc_i2c.mask_clk_mask = 2332 RBIOS32(lcd_ddc_info + 3); 2333 ddc_i2c.mask_data_mask = 2334 RBIOS32(lcd_ddc_info + 7); 2335 ddc_i2c.a_clk_mask = 2336 RBIOS32(lcd_ddc_info + 3); 2337 ddc_i2c.a_data_mask = 2338 RBIOS32(lcd_ddc_info + 7); 2339 ddc_i2c.en_clk_mask = 2340 RBIOS32(lcd_ddc_info + 3); 2341 ddc_i2c.en_data_mask = 2342 RBIOS32(lcd_ddc_info + 7); 2343 ddc_i2c.y_clk_mask = 2344 RBIOS32(lcd_ddc_info + 3); 2345 ddc_i2c.y_data_mask = 2346 RBIOS32(lcd_ddc_info + 7); 2347 break; 2348 default: 2349 ddc_i2c.valid = false; 2350 break; 2351 } 2352 DRM_DEBUG("LCD DDC Info Table found!\n"); 2353 } else 2354 ddc_i2c.valid = false; 2355 2356 hpd.hpd = RADEON_HPD_NONE; 2357 radeon_add_legacy_connector(dev, 2358 5, 2359 ATOM_DEVICE_LCD1_SUPPORT, 2360 DRM_MODE_CONNECTOR_LVDS, 2361 &ddc_i2c, 2362 CONNECTOR_OBJECT_ID_LVDS, 2363 &hpd); 2364 } 2365 } 2366 2367 /* check TV table */ 2368 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 2369 uint32_t tv_info = 2370 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 2371 if (tv_info) { 2372 if (RBIOS8(tv_info + 6) == 'T') { 2373 if (radeon_apply_legacy_tv_quirks(dev)) { 2374 hpd.hpd = RADEON_HPD_NONE; 2375 ddc_i2c.valid = false; 2376 radeon_add_legacy_encoder(dev, 2377 radeon_get_encoder_id 2378 (dev, 2379 ATOM_DEVICE_TV1_SUPPORT, 2380 2), 2381 ATOM_DEVICE_TV1_SUPPORT); 2382 radeon_add_legacy_connector(dev, 6, 2383 ATOM_DEVICE_TV1_SUPPORT, 2384 DRM_MODE_CONNECTOR_SVIDEO, 2385 &ddc_i2c, 2386 CONNECTOR_OBJECT_ID_SVIDEO, 2387 &hpd); 2388 } 2389 } 2390 } 2391 } 2392 2393 radeon_link_encoder_connector(dev); 2394 2395 return true; 2396} 2397 2398void radeon_combios_get_power_modes(struct radeon_device *rdev) 2399{ 2400 struct drm_device *dev = rdev->ddev; 2401 u16 offset, misc, misc2 = 0; 2402 u8 rev, blocks, tmp; 2403 int state_index = 0; 2404 2405 rdev->pm.default_power_state_index = -1; 2406 2407 if (rdev->flags & RADEON_IS_MOBILITY) { 2408 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE); 2409 if (offset) { 2410 rev = RBIOS8(offset); 2411 blocks = RBIOS8(offset + 0x2); 2412 /* power mode 0 tends to be the only valid one */ 2413 rdev->pm.power_state[state_index].num_clock_modes = 1; 2414 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2); 2415 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6); 2416 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2417 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2418 goto default_mode; 2419 rdev->pm.power_state[state_index].type = 2420 POWER_STATE_TYPE_BATTERY; 2421 misc = RBIOS16(offset + 0x5 + 0x0); 2422 if (rev > 4) 2423 misc2 = RBIOS16(offset + 0x5 + 0xe); 2424 rdev->pm.power_state[state_index].misc = misc; 2425 rdev->pm.power_state[state_index].misc2 = misc2; 2426 if (misc & 0x4) { 2427 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO; 2428 if (misc & 0x8) 2429 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2430 true; 2431 else 2432 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2433 false; 2434 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true; 2435 if (rev < 6) { 2436 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = 2437 RBIOS16(offset + 0x5 + 0xb) * 4; 2438 tmp = RBIOS8(offset + 0x5 + 0xd); 2439 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); 2440 } else { 2441 u8 entries = RBIOS8(offset + 0x5 + 0xb); 2442 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc); 2443 if (entries && voltage_table_offset) { 2444 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = 2445 RBIOS16(voltage_table_offset) * 4; 2446 tmp = RBIOS8(voltage_table_offset + 0x2); 2447 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); 2448 } else 2449 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false; 2450 } 2451 switch ((misc2 & 0x700) >> 8) { 2452 case 0: 2453 default: 2454 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0; 2455 break; 2456 case 1: 2457 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33; 2458 break; 2459 case 2: 2460 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66; 2461 break; 2462 case 3: 2463 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99; 2464 break; 2465 case 4: 2466 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132; 2467 break; 2468 } 2469 } else 2470 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2471 if (rev > 6) 2472 rdev->pm.power_state[state_index].pcie_lanes = 2473 RBIOS8(offset + 0x5 + 0x10); 2474 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2475 state_index++; 2476 } else { 2477 /* XXX figure out some good default low power mode for mobility cards w/out power tables */ 2478 } 2479 } else { 2480 /* XXX figure out some good default low power mode for desktop cards */ 2481 } 2482 2483default_mode: 2484 /* add the default mode */ 2485 rdev->pm.power_state[state_index].type = 2486 POWER_STATE_TYPE_DEFAULT; 2487 rdev->pm.power_state[state_index].num_clock_modes = 1; 2488 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; 2489 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; 2490 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; 2491 if ((state_index > 0) && 2492 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO)) 2493 rdev->pm.power_state[state_index].clock_info[0].voltage = 2494 rdev->pm.power_state[0].clock_info[0].voltage; 2495 else 2496 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2497 rdev->pm.power_state[state_index].pcie_lanes = 16; 2498 rdev->pm.power_state[state_index].flags = 0; 2499 rdev->pm.default_power_state_index = state_index; 2500 rdev->pm.num_power_states = state_index + 1; 2501 2502 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2503 rdev->pm.current_clock_mode_index = 0; 2504} 2505 2506void radeon_external_tmds_setup(struct drm_encoder *encoder) 2507{ 2508 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2509 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2510 2511 if (!tmds) 2512 return; 2513 2514 switch (tmds->dvo_chip) { 2515 case DVO_SIL164: 2516 /* sil 164 */ 2517 radeon_i2c_put_byte(tmds->i2c_bus, 2518 tmds->slave_addr, 2519 0x08, 0x30); 2520 radeon_i2c_put_byte(tmds->i2c_bus, 2521 tmds->slave_addr, 2522 0x09, 0x00); 2523 radeon_i2c_put_byte(tmds->i2c_bus, 2524 tmds->slave_addr, 2525 0x0a, 0x90); 2526 radeon_i2c_put_byte(tmds->i2c_bus, 2527 tmds->slave_addr, 2528 0x0c, 0x89); 2529 radeon_i2c_put_byte(tmds->i2c_bus, 2530 tmds->slave_addr, 2531 0x08, 0x3b); 2532 break; 2533 case DVO_SIL1178: 2534 /* sil 1178 - untested */ 2535 /* 2536 * 0x0f, 0x44 2537 * 0x0f, 0x4c 2538 * 0x0e, 0x01 2539 * 0x0a, 0x80 2540 * 0x09, 0x30 2541 * 0x0c, 0xc9 2542 * 0x0d, 0x70 2543 * 0x08, 0x32 2544 * 0x08, 0x33 2545 */ 2546 break; 2547 default: 2548 break; 2549 } 2550 2551} 2552 2553bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder) 2554{ 2555 struct drm_device *dev = encoder->dev; 2556 struct radeon_device *rdev = dev->dev_private; 2557 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2558 uint16_t offset; 2559 uint8_t blocks, slave_addr, rev; 2560 uint32_t index, id; 2561 uint32_t reg, val, and_mask, or_mask; 2562 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2563 2564 if (!tmds) 2565 return false; 2566 2567 if (rdev->flags & RADEON_IS_IGP) { 2568 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE); 2569 rev = RBIOS8(offset); 2570 if (offset) { 2571 rev = RBIOS8(offset); 2572 if (rev > 1) { 2573 blocks = RBIOS8(offset + 3); 2574 index = offset + 4; 2575 while (blocks > 0) { 2576 id = RBIOS16(index); 2577 index += 2; 2578 switch (id >> 13) { 2579 case 0: 2580 reg = (id & 0x1fff) * 4; 2581 val = RBIOS32(index); 2582 index += 4; 2583 WREG32(reg, val); 2584 break; 2585 case 2: 2586 reg = (id & 0x1fff) * 4; 2587 and_mask = RBIOS32(index); 2588 index += 4; 2589 or_mask = RBIOS32(index); 2590 index += 4; 2591 val = RREG32(reg); 2592 val = (val & and_mask) | or_mask; 2593 WREG32(reg, val); 2594 break; 2595 case 3: 2596 val = RBIOS16(index); 2597 index += 2; 2598 udelay(val); 2599 break; 2600 case 4: 2601 val = RBIOS16(index); 2602 index += 2; 2603 udelay(val * 1000); 2604 break; 2605 case 6: 2606 slave_addr = id & 0xff; 2607 slave_addr >>= 1; /* 7 bit addressing */ 2608 index++; 2609 reg = RBIOS8(index); 2610 index++; 2611 val = RBIOS8(index); 2612 index++; 2613 radeon_i2c_put_byte(tmds->i2c_bus, 2614 slave_addr, 2615 reg, val); 2616 break; 2617 default: 2618 DRM_ERROR("Unknown id %d\n", id >> 13); 2619 break; 2620 } 2621 blocks--; 2622 } 2623 return true; 2624 } 2625 } 2626 } else { 2627 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 2628 if (offset) { 2629 index = offset + 10; 2630 id = RBIOS16(index); 2631 while (id != 0xffff) { 2632 index += 2; 2633 switch (id >> 13) { 2634 case 0: 2635 reg = (id & 0x1fff) * 4; 2636 val = RBIOS32(index); 2637 WREG32(reg, val); 2638 break; 2639 case 2: 2640 reg = (id & 0x1fff) * 4; 2641 and_mask = RBIOS32(index); 2642 index += 4; 2643 or_mask = RBIOS32(index); 2644 index += 4; 2645 val = RREG32(reg); 2646 val = (val & and_mask) | or_mask; 2647 WREG32(reg, val); 2648 break; 2649 case 4: 2650 val = RBIOS16(index); 2651 index += 2; 2652 udelay(val); 2653 break; 2654 case 5: 2655 reg = id & 0x1fff; 2656 and_mask = RBIOS32(index); 2657 index += 4; 2658 or_mask = RBIOS32(index); 2659 index += 4; 2660 val = RREG32_PLL(reg); 2661 val = (val & and_mask) | or_mask; 2662 WREG32_PLL(reg, val); 2663 break; 2664 case 6: 2665 reg = id & 0x1fff; 2666 val = RBIOS8(index); 2667 index += 1; 2668 radeon_i2c_put_byte(tmds->i2c_bus, 2669 tmds->slave_addr, 2670 reg, val); 2671 break; 2672 default: 2673 DRM_ERROR("Unknown id %d\n", id >> 13); 2674 break; 2675 } 2676 id = RBIOS16(index); 2677 } 2678 return true; 2679 } 2680 } 2681 return false; 2682} 2683 2684static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset) 2685{ 2686 struct radeon_device *rdev = dev->dev_private; 2687 2688 if (offset) { 2689 while (RBIOS16(offset)) { 2690 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13); 2691 uint32_t addr = (RBIOS16(offset) & 0x1fff); 2692 uint32_t val, and_mask, or_mask; 2693 uint32_t tmp; 2694 2695 offset += 2; 2696 switch (cmd) { 2697 case 0: 2698 val = RBIOS32(offset); 2699 offset += 4; 2700 WREG32(addr, val); 2701 break; 2702 case 1: 2703 val = RBIOS32(offset); 2704 offset += 4; 2705 WREG32(addr, val); 2706 break; 2707 case 2: 2708 and_mask = RBIOS32(offset); 2709 offset += 4; 2710 or_mask = RBIOS32(offset); 2711 offset += 4; 2712 tmp = RREG32(addr); 2713 tmp &= and_mask; 2714 tmp |= or_mask; 2715 WREG32(addr, tmp); 2716 break; 2717 case 3: 2718 and_mask = RBIOS32(offset); 2719 offset += 4; 2720 or_mask = RBIOS32(offset); 2721 offset += 4; 2722 tmp = RREG32(addr); 2723 tmp &= and_mask; 2724 tmp |= or_mask; 2725 WREG32(addr, tmp); 2726 break; 2727 case 4: 2728 val = RBIOS16(offset); 2729 offset += 2; 2730 udelay(val); 2731 break; 2732 case 5: 2733 val = RBIOS16(offset); 2734 offset += 2; 2735 switch (addr) { 2736 case 8: 2737 while (val--) { 2738 if (! 2739 (RREG32_PLL 2740 (RADEON_CLK_PWRMGT_CNTL) & 2741 RADEON_MC_BUSY)) 2742 break; 2743 } 2744 break; 2745 case 9: 2746 while (val--) { 2747 if ((RREG32(RADEON_MC_STATUS) & 2748 RADEON_MC_IDLE)) 2749 break; 2750 } 2751 break; 2752 default: 2753 break; 2754 } 2755 break; 2756 default: 2757 break; 2758 } 2759 } 2760 } 2761} 2762 2763static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset) 2764{ 2765 struct radeon_device *rdev = dev->dev_private; 2766 2767 if (offset) { 2768 while (RBIOS8(offset)) { 2769 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6); 2770 uint8_t addr = (RBIOS8(offset) & 0x3f); 2771 uint32_t val, shift, tmp; 2772 uint32_t and_mask, or_mask; 2773 2774 offset++; 2775 switch (cmd) { 2776 case 0: 2777 val = RBIOS32(offset); 2778 offset += 4; 2779 WREG32_PLL(addr, val); 2780 break; 2781 case 1: 2782 shift = RBIOS8(offset) * 8; 2783 offset++; 2784 and_mask = RBIOS8(offset) << shift; 2785 and_mask |= ~(0xff << shift); 2786 offset++; 2787 or_mask = RBIOS8(offset) << shift; 2788 offset++; 2789 tmp = RREG32_PLL(addr); 2790 tmp &= and_mask; 2791 tmp |= or_mask; 2792 WREG32_PLL(addr, tmp); 2793 break; 2794 case 2: 2795 case 3: 2796 tmp = 1000; 2797 switch (addr) { 2798 case 1: 2799 udelay(150); 2800 break; 2801 case 2: 2802 udelay(1000); 2803 break; 2804 case 3: 2805 while (tmp--) { 2806 if (! 2807 (RREG32_PLL 2808 (RADEON_CLK_PWRMGT_CNTL) & 2809 RADEON_MC_BUSY)) 2810 break; 2811 } 2812 break; 2813 case 4: 2814 while (tmp--) { 2815 if (RREG32_PLL 2816 (RADEON_CLK_PWRMGT_CNTL) & 2817 RADEON_DLL_READY) 2818 break; 2819 } 2820 break; 2821 case 5: 2822 tmp = 2823 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); 2824 if (tmp & RADEON_CG_NO1_DEBUG_0) { 2825#if 0 2826 uint32_t mclk_cntl = 2827 RREG32_PLL 2828 (RADEON_MCLK_CNTL); 2829 mclk_cntl &= 0xffff0000; 2830 /*mclk_cntl |= 0x00001111;*//* ??? */ 2831 WREG32_PLL(RADEON_MCLK_CNTL, 2832 mclk_cntl); 2833 udelay(10000); 2834#endif 2835 WREG32_PLL 2836 (RADEON_CLK_PWRMGT_CNTL, 2837 tmp & 2838 ~RADEON_CG_NO1_DEBUG_0); 2839 udelay(10000); 2840 } 2841 break; 2842 default: 2843 break; 2844 } 2845 break; 2846 default: 2847 break; 2848 } 2849 } 2850 } 2851} 2852 2853static void combios_parse_ram_reset_table(struct drm_device *dev, 2854 uint16_t offset) 2855{ 2856 struct radeon_device *rdev = dev->dev_private; 2857 uint32_t tmp; 2858 2859 if (offset) { 2860 uint8_t val = RBIOS8(offset); 2861 while (val != 0xff) { 2862 offset++; 2863 2864 if (val == 0x0f) { 2865 uint32_t channel_complete_mask; 2866 2867 if (ASIC_IS_R300(rdev)) 2868 channel_complete_mask = 2869 R300_MEM_PWRUP_COMPLETE; 2870 else 2871 channel_complete_mask = 2872 RADEON_MEM_PWRUP_COMPLETE; 2873 tmp = 20000; 2874 while (tmp--) { 2875 if ((RREG32(RADEON_MEM_STR_CNTL) & 2876 channel_complete_mask) == 2877 channel_complete_mask) 2878 break; 2879 } 2880 } else { 2881 uint32_t or_mask = RBIOS16(offset); 2882 offset += 2; 2883 2884 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 2885 tmp &= RADEON_SDRAM_MODE_MASK; 2886 tmp |= or_mask; 2887 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 2888 2889 or_mask = val << 24; 2890 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 2891 tmp &= RADEON_B3MEM_RESET_MASK; 2892 tmp |= or_mask; 2893 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 2894 } 2895 val = RBIOS8(offset); 2896 } 2897 } 2898} 2899 2900static uint32_t combios_detect_ram(struct drm_device *dev, int ram, 2901 int mem_addr_mapping) 2902{ 2903 struct radeon_device *rdev = dev->dev_private; 2904 uint32_t mem_cntl; 2905 uint32_t mem_size; 2906 uint32_t addr = 0; 2907 2908 mem_cntl = RREG32(RADEON_MEM_CNTL); 2909 if (mem_cntl & RV100_HALF_MODE) 2910 ram /= 2; 2911 mem_size = ram; 2912 mem_cntl &= ~(0xff << 8); 2913 mem_cntl |= (mem_addr_mapping & 0xff) << 8; 2914 WREG32(RADEON_MEM_CNTL, mem_cntl); 2915 RREG32(RADEON_MEM_CNTL); 2916 2917 /* sdram reset ? */ 2918 2919 /* something like this???? */ 2920 while (ram--) { 2921 addr = ram * 1024 * 1024; 2922 /* write to each page */ 2923 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER); 2924 WREG32(RADEON_MM_DATA, 0xdeadbeef); 2925 /* read back and verify */ 2926 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER); 2927 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef) 2928 return 0; 2929 } 2930 2931 return mem_size; 2932} 2933 2934static void combios_write_ram_size(struct drm_device *dev) 2935{ 2936 struct radeon_device *rdev = dev->dev_private; 2937 uint8_t rev; 2938 uint16_t offset; 2939 uint32_t mem_size = 0; 2940 uint32_t mem_cntl = 0; 2941 2942 /* should do something smarter here I guess... */ 2943 if (rdev->flags & RADEON_IS_IGP) 2944 return; 2945 2946 /* first check detected mem table */ 2947 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE); 2948 if (offset) { 2949 rev = RBIOS8(offset); 2950 if (rev < 3) { 2951 mem_cntl = RBIOS32(offset + 1); 2952 mem_size = RBIOS16(offset + 5); 2953 if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) && 2954 ((dev->pdev->device != 0x515e) 2955 && (dev->pdev->device != 0x5969))) 2956 WREG32(RADEON_MEM_CNTL, mem_cntl); 2957 } 2958 } 2959 2960 if (!mem_size) { 2961 offset = 2962 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 2963 if (offset) { 2964 rev = RBIOS8(offset - 1); 2965 if (rev < 1) { 2966 if (((rdev->flags & RADEON_FAMILY_MASK) < 2967 CHIP_R200) 2968 && ((dev->pdev->device != 0x515e) 2969 && (dev->pdev->device != 0x5969))) { 2970 int ram = 0; 2971 int mem_addr_mapping = 0; 2972 2973 while (RBIOS8(offset)) { 2974 ram = RBIOS8(offset); 2975 mem_addr_mapping = 2976 RBIOS8(offset + 1); 2977 if (mem_addr_mapping != 0x25) 2978 ram *= 2; 2979 mem_size = 2980 combios_detect_ram(dev, ram, 2981 mem_addr_mapping); 2982 if (mem_size) 2983 break; 2984 offset += 2; 2985 } 2986 } else 2987 mem_size = RBIOS8(offset); 2988 } else { 2989 mem_size = RBIOS8(offset); 2990 mem_size *= 2; /* convert to MB */ 2991 } 2992 } 2993 } 2994 2995 mem_size *= (1024 * 1024); /* convert to bytes */ 2996 WREG32(RADEON_CONFIG_MEMSIZE, mem_size); 2997} 2998 2999void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable) 3000{ 3001 uint16_t dyn_clk_info = 3002 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); 3003 3004 if (dyn_clk_info) 3005 combios_parse_pll_table(dev, dyn_clk_info); 3006} 3007 3008void radeon_combios_asic_init(struct drm_device *dev) 3009{ 3010 struct radeon_device *rdev = dev->dev_private; 3011 uint16_t table; 3012 3013 /* port hardcoded mac stuff from radeonfb */ 3014 if (rdev->bios == NULL) 3015 return; 3016 3017 /* ASIC INIT 1 */ 3018 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE); 3019 if (table) 3020 combios_parse_mmio_table(dev, table); 3021 3022 /* PLL INIT */ 3023 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE); 3024 if (table) 3025 combios_parse_pll_table(dev, table); 3026 3027 /* ASIC INIT 2 */ 3028 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE); 3029 if (table) 3030 combios_parse_mmio_table(dev, table); 3031 3032 if (!(rdev->flags & RADEON_IS_IGP)) { 3033 /* ASIC INIT 4 */ 3034 table = 3035 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE); 3036 if (table) 3037 combios_parse_mmio_table(dev, table); 3038 3039 /* RAM RESET */ 3040 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE); 3041 if (table) 3042 combios_parse_ram_reset_table(dev, table); 3043 3044 /* ASIC INIT 3 */ 3045 table = 3046 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE); 3047 if (table) 3048 combios_parse_mmio_table(dev, table); 3049 3050 /* write CONFIG_MEMSIZE */ 3051 combios_write_ram_size(dev); 3052 } 3053 3054 /* DYN CLK 1 */ 3055 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); 3056 if (table) 3057 combios_parse_pll_table(dev, table); 3058 3059} 3060 3061void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev) 3062{ 3063 struct radeon_device *rdev = dev->dev_private; 3064 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch; 3065 3066 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 3067 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3068 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH); 3069 3070 /* let the bios control the backlight */ 3071 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; 3072 3073 /* tell the bios not to handle mode switching */ 3074 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS | 3075 RADEON_ACC_MODE_CHANGE); 3076 3077 /* tell the bios a driver is loaded */ 3078 bios_7_scratch |= RADEON_DRV_LOADED; 3079 3080 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); 3081 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3082 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch); 3083} 3084 3085void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock) 3086{ 3087 struct drm_device *dev = encoder->dev; 3088 struct radeon_device *rdev = dev->dev_private; 3089 uint32_t bios_6_scratch; 3090 3091 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3092 3093 if (lock) 3094 bios_6_scratch |= RADEON_DRIVER_CRITICAL; 3095 else 3096 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL; 3097 3098 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3099} 3100 3101void 3102radeon_combios_connected_scratch_regs(struct drm_connector *connector, 3103 struct drm_encoder *encoder, 3104 bool connected) 3105{ 3106 struct drm_device *dev = connector->dev; 3107 struct radeon_device *rdev = dev->dev_private; 3108 struct radeon_connector *radeon_connector = 3109 to_radeon_connector(connector); 3110 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3111 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH); 3112 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 3113 3114 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 3115 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 3116 if (connected) { 3117 DRM_DEBUG("TV1 connected\n"); 3118 /* fix me */ 3119 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO; 3120 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */ 3121 bios_5_scratch |= RADEON_TV1_ON; 3122 bios_5_scratch |= RADEON_ACC_REQ_TV1; 3123 } else { 3124 DRM_DEBUG("TV1 disconnected\n"); 3125 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK; 3126 bios_5_scratch &= ~RADEON_TV1_ON; 3127 bios_5_scratch &= ~RADEON_ACC_REQ_TV1; 3128 } 3129 } 3130 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 3131 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 3132 if (connected) { 3133 DRM_DEBUG("LCD1 connected\n"); 3134 bios_4_scratch |= RADEON_LCD1_ATTACHED; 3135 bios_5_scratch |= RADEON_LCD1_ON; 3136 bios_5_scratch |= RADEON_ACC_REQ_LCD1; 3137 } else { 3138 DRM_DEBUG("LCD1 disconnected\n"); 3139 bios_4_scratch &= ~RADEON_LCD1_ATTACHED; 3140 bios_5_scratch &= ~RADEON_LCD1_ON; 3141 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1; 3142 } 3143 } 3144 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 3145 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 3146 if (connected) { 3147 DRM_DEBUG("CRT1 connected\n"); 3148 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR; 3149 bios_5_scratch |= RADEON_CRT1_ON; 3150 bios_5_scratch |= RADEON_ACC_REQ_CRT1; 3151 } else { 3152 DRM_DEBUG("CRT1 disconnected\n"); 3153 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK; 3154 bios_5_scratch &= ~RADEON_CRT1_ON; 3155 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1; 3156 } 3157 } 3158 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 3159 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 3160 if (connected) { 3161 DRM_DEBUG("CRT2 connected\n"); 3162 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR; 3163 bios_5_scratch |= RADEON_CRT2_ON; 3164 bios_5_scratch |= RADEON_ACC_REQ_CRT2; 3165 } else { 3166 DRM_DEBUG("CRT2 disconnected\n"); 3167 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK; 3168 bios_5_scratch &= ~RADEON_CRT2_ON; 3169 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2; 3170 } 3171 } 3172 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 3173 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 3174 if (connected) { 3175 DRM_DEBUG("DFP1 connected\n"); 3176 bios_4_scratch |= RADEON_DFP1_ATTACHED; 3177 bios_5_scratch |= RADEON_DFP1_ON; 3178 bios_5_scratch |= RADEON_ACC_REQ_DFP1; 3179 } else { 3180 DRM_DEBUG("DFP1 disconnected\n"); 3181 bios_4_scratch &= ~RADEON_DFP1_ATTACHED; 3182 bios_5_scratch &= ~RADEON_DFP1_ON; 3183 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1; 3184 } 3185 } 3186 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 3187 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 3188 if (connected) { 3189 DRM_DEBUG("DFP2 connected\n"); 3190 bios_4_scratch |= RADEON_DFP2_ATTACHED; 3191 bios_5_scratch |= RADEON_DFP2_ON; 3192 bios_5_scratch |= RADEON_ACC_REQ_DFP2; 3193 } else { 3194 DRM_DEBUG("DFP2 disconnected\n"); 3195 bios_4_scratch &= ~RADEON_DFP2_ATTACHED; 3196 bios_5_scratch &= ~RADEON_DFP2_ON; 3197 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2; 3198 } 3199 } 3200 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch); 3201 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 3202} 3203 3204void 3205radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) 3206{ 3207 struct drm_device *dev = encoder->dev; 3208 struct radeon_device *rdev = dev->dev_private; 3209 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3210 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 3211 3212 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 3213 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK; 3214 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT); 3215 } 3216 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 3217 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK; 3218 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT); 3219 } 3220 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 3221 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK; 3222 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT); 3223 } 3224 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 3225 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK; 3226 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT); 3227 } 3228 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 3229 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK; 3230 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT); 3231 } 3232 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 3233 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK; 3234 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT); 3235 } 3236 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 3237} 3238 3239void 3240radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) 3241{ 3242 struct drm_device *dev = encoder->dev; 3243 struct radeon_device *rdev = dev->dev_private; 3244 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3245 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3246 3247 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 3248 if (on) 3249 bios_6_scratch |= RADEON_TV_DPMS_ON; 3250 else 3251 bios_6_scratch &= ~RADEON_TV_DPMS_ON; 3252 } 3253 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3254 if (on) 3255 bios_6_scratch |= RADEON_CRT_DPMS_ON; 3256 else 3257 bios_6_scratch &= ~RADEON_CRT_DPMS_ON; 3258 } 3259 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3260 if (on) 3261 bios_6_scratch |= RADEON_LCD_DPMS_ON; 3262 else 3263 bios_6_scratch &= ~RADEON_LCD_DPMS_ON; 3264 } 3265 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 3266 if (on) 3267 bios_6_scratch |= RADEON_DFP_DPMS_ON; 3268 else 3269 bios_6_scratch &= ~RADEON_DFP_DPMS_ON; 3270 } 3271 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3272} 3273