radeon_combios.c revision 791cfe2684a74ed7155254816ff9e89e6064277c
1/* 2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario 3 * Copyright 2007-8 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 */ 27#include "drmP.h" 28#include "radeon_drm.h" 29#include "radeon.h" 30#include "atom.h" 31 32#ifdef CONFIG_PPC_PMAC 33/* not sure which of these are needed */ 34#include <asm/machdep.h> 35#include <asm/pmac_feature.h> 36#include <asm/prom.h> 37#include <asm/pci-bridge.h> 38#endif /* CONFIG_PPC_PMAC */ 39 40/* from radeon_encoder.c */ 41extern uint32_t 42radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, 43 uint8_t dac); 44extern void radeon_link_encoder_connector(struct drm_device *dev); 45 46/* from radeon_connector.c */ 47extern void 48radeon_add_legacy_connector(struct drm_device *dev, 49 uint32_t connector_id, 50 uint32_t supported_device, 51 int connector_type, 52 struct radeon_i2c_bus_rec *i2c_bus, 53 uint16_t connector_object_id, 54 struct radeon_hpd *hpd); 55 56/* from radeon_legacy_encoder.c */ 57extern void 58radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, 59 uint32_t supported_device); 60 61/* old legacy ATI BIOS routines */ 62 63/* COMBIOS table offsets */ 64enum radeon_combios_table_offset { 65 /* absolute offset tables */ 66 COMBIOS_ASIC_INIT_1_TABLE, 67 COMBIOS_BIOS_SUPPORT_TABLE, 68 COMBIOS_DAC_PROGRAMMING_TABLE, 69 COMBIOS_MAX_COLOR_DEPTH_TABLE, 70 COMBIOS_CRTC_INFO_TABLE, 71 COMBIOS_PLL_INFO_TABLE, 72 COMBIOS_TV_INFO_TABLE, 73 COMBIOS_DFP_INFO_TABLE, 74 COMBIOS_HW_CONFIG_INFO_TABLE, 75 COMBIOS_MULTIMEDIA_INFO_TABLE, 76 COMBIOS_TV_STD_PATCH_TABLE, 77 COMBIOS_LCD_INFO_TABLE, 78 COMBIOS_MOBILE_INFO_TABLE, 79 COMBIOS_PLL_INIT_TABLE, 80 COMBIOS_MEM_CONFIG_TABLE, 81 COMBIOS_SAVE_MASK_TABLE, 82 COMBIOS_HARDCODED_EDID_TABLE, 83 COMBIOS_ASIC_INIT_2_TABLE, 84 COMBIOS_CONNECTOR_INFO_TABLE, 85 COMBIOS_DYN_CLK_1_TABLE, 86 COMBIOS_RESERVED_MEM_TABLE, 87 COMBIOS_EXT_TMDS_INFO_TABLE, 88 COMBIOS_MEM_CLK_INFO_TABLE, 89 COMBIOS_EXT_DAC_INFO_TABLE, 90 COMBIOS_MISC_INFO_TABLE, 91 COMBIOS_CRT_INFO_TABLE, 92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE, 93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE, 94 COMBIOS_FAN_SPEED_INFO_TABLE, 95 COMBIOS_OVERDRIVE_INFO_TABLE, 96 COMBIOS_OEM_INFO_TABLE, 97 COMBIOS_DYN_CLK_2_TABLE, 98 COMBIOS_POWER_CONNECTOR_INFO_TABLE, 99 COMBIOS_I2C_INFO_TABLE, 100 /* relative offset tables */ 101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */ 102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */ 103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */ 104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */ 105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */ 106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */ 107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */ 108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */ 109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */ 110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */ 111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */ 112}; 113 114enum radeon_combios_ddc { 115 DDC_NONE_DETECTED, 116 DDC_MONID, 117 DDC_DVI, 118 DDC_VGA, 119 DDC_CRT2, 120 DDC_LCD, 121 DDC_GPIO, 122}; 123 124enum radeon_combios_connector { 125 CONNECTOR_NONE_LEGACY, 126 CONNECTOR_PROPRIETARY_LEGACY, 127 CONNECTOR_CRT_LEGACY, 128 CONNECTOR_DVI_I_LEGACY, 129 CONNECTOR_DVI_D_LEGACY, 130 CONNECTOR_CTV_LEGACY, 131 CONNECTOR_STV_LEGACY, 132 CONNECTOR_UNSUPPORTED_LEGACY 133}; 134 135const int legacy_connector_convert[] = { 136 DRM_MODE_CONNECTOR_Unknown, 137 DRM_MODE_CONNECTOR_DVID, 138 DRM_MODE_CONNECTOR_VGA, 139 DRM_MODE_CONNECTOR_DVII, 140 DRM_MODE_CONNECTOR_DVID, 141 DRM_MODE_CONNECTOR_Composite, 142 DRM_MODE_CONNECTOR_SVIDEO, 143 DRM_MODE_CONNECTOR_Unknown, 144}; 145 146static uint16_t combios_get_table_offset(struct drm_device *dev, 147 enum radeon_combios_table_offset table) 148{ 149 struct radeon_device *rdev = dev->dev_private; 150 int rev; 151 uint16_t offset = 0, check_offset; 152 153 if (!rdev->bios) 154 return 0; 155 156 switch (table) { 157 /* absolute offset tables */ 158 case COMBIOS_ASIC_INIT_1_TABLE: 159 check_offset = RBIOS16(rdev->bios_header_start + 0xc); 160 if (check_offset) 161 offset = check_offset; 162 break; 163 case COMBIOS_BIOS_SUPPORT_TABLE: 164 check_offset = RBIOS16(rdev->bios_header_start + 0x14); 165 if (check_offset) 166 offset = check_offset; 167 break; 168 case COMBIOS_DAC_PROGRAMMING_TABLE: 169 check_offset = RBIOS16(rdev->bios_header_start + 0x2a); 170 if (check_offset) 171 offset = check_offset; 172 break; 173 case COMBIOS_MAX_COLOR_DEPTH_TABLE: 174 check_offset = RBIOS16(rdev->bios_header_start + 0x2c); 175 if (check_offset) 176 offset = check_offset; 177 break; 178 case COMBIOS_CRTC_INFO_TABLE: 179 check_offset = RBIOS16(rdev->bios_header_start + 0x2e); 180 if (check_offset) 181 offset = check_offset; 182 break; 183 case COMBIOS_PLL_INFO_TABLE: 184 check_offset = RBIOS16(rdev->bios_header_start + 0x30); 185 if (check_offset) 186 offset = check_offset; 187 break; 188 case COMBIOS_TV_INFO_TABLE: 189 check_offset = RBIOS16(rdev->bios_header_start + 0x32); 190 if (check_offset) 191 offset = check_offset; 192 break; 193 case COMBIOS_DFP_INFO_TABLE: 194 check_offset = RBIOS16(rdev->bios_header_start + 0x34); 195 if (check_offset) 196 offset = check_offset; 197 break; 198 case COMBIOS_HW_CONFIG_INFO_TABLE: 199 check_offset = RBIOS16(rdev->bios_header_start + 0x36); 200 if (check_offset) 201 offset = check_offset; 202 break; 203 case COMBIOS_MULTIMEDIA_INFO_TABLE: 204 check_offset = RBIOS16(rdev->bios_header_start + 0x38); 205 if (check_offset) 206 offset = check_offset; 207 break; 208 case COMBIOS_TV_STD_PATCH_TABLE: 209 check_offset = RBIOS16(rdev->bios_header_start + 0x3e); 210 if (check_offset) 211 offset = check_offset; 212 break; 213 case COMBIOS_LCD_INFO_TABLE: 214 check_offset = RBIOS16(rdev->bios_header_start + 0x40); 215 if (check_offset) 216 offset = check_offset; 217 break; 218 case COMBIOS_MOBILE_INFO_TABLE: 219 check_offset = RBIOS16(rdev->bios_header_start + 0x42); 220 if (check_offset) 221 offset = check_offset; 222 break; 223 case COMBIOS_PLL_INIT_TABLE: 224 check_offset = RBIOS16(rdev->bios_header_start + 0x46); 225 if (check_offset) 226 offset = check_offset; 227 break; 228 case COMBIOS_MEM_CONFIG_TABLE: 229 check_offset = RBIOS16(rdev->bios_header_start + 0x48); 230 if (check_offset) 231 offset = check_offset; 232 break; 233 case COMBIOS_SAVE_MASK_TABLE: 234 check_offset = RBIOS16(rdev->bios_header_start + 0x4a); 235 if (check_offset) 236 offset = check_offset; 237 break; 238 case COMBIOS_HARDCODED_EDID_TABLE: 239 check_offset = RBIOS16(rdev->bios_header_start + 0x4c); 240 if (check_offset) 241 offset = check_offset; 242 break; 243 case COMBIOS_ASIC_INIT_2_TABLE: 244 check_offset = RBIOS16(rdev->bios_header_start + 0x4e); 245 if (check_offset) 246 offset = check_offset; 247 break; 248 case COMBIOS_CONNECTOR_INFO_TABLE: 249 check_offset = RBIOS16(rdev->bios_header_start + 0x50); 250 if (check_offset) 251 offset = check_offset; 252 break; 253 case COMBIOS_DYN_CLK_1_TABLE: 254 check_offset = RBIOS16(rdev->bios_header_start + 0x52); 255 if (check_offset) 256 offset = check_offset; 257 break; 258 case COMBIOS_RESERVED_MEM_TABLE: 259 check_offset = RBIOS16(rdev->bios_header_start + 0x54); 260 if (check_offset) 261 offset = check_offset; 262 break; 263 case COMBIOS_EXT_TMDS_INFO_TABLE: 264 check_offset = RBIOS16(rdev->bios_header_start + 0x58); 265 if (check_offset) 266 offset = check_offset; 267 break; 268 case COMBIOS_MEM_CLK_INFO_TABLE: 269 check_offset = RBIOS16(rdev->bios_header_start + 0x5a); 270 if (check_offset) 271 offset = check_offset; 272 break; 273 case COMBIOS_EXT_DAC_INFO_TABLE: 274 check_offset = RBIOS16(rdev->bios_header_start + 0x5c); 275 if (check_offset) 276 offset = check_offset; 277 break; 278 case COMBIOS_MISC_INFO_TABLE: 279 check_offset = RBIOS16(rdev->bios_header_start + 0x5e); 280 if (check_offset) 281 offset = check_offset; 282 break; 283 case COMBIOS_CRT_INFO_TABLE: 284 check_offset = RBIOS16(rdev->bios_header_start + 0x60); 285 if (check_offset) 286 offset = check_offset; 287 break; 288 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE: 289 check_offset = RBIOS16(rdev->bios_header_start + 0x62); 290 if (check_offset) 291 offset = check_offset; 292 break; 293 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE: 294 check_offset = RBIOS16(rdev->bios_header_start + 0x64); 295 if (check_offset) 296 offset = check_offset; 297 break; 298 case COMBIOS_FAN_SPEED_INFO_TABLE: 299 check_offset = RBIOS16(rdev->bios_header_start + 0x66); 300 if (check_offset) 301 offset = check_offset; 302 break; 303 case COMBIOS_OVERDRIVE_INFO_TABLE: 304 check_offset = RBIOS16(rdev->bios_header_start + 0x68); 305 if (check_offset) 306 offset = check_offset; 307 break; 308 case COMBIOS_OEM_INFO_TABLE: 309 check_offset = RBIOS16(rdev->bios_header_start + 0x6a); 310 if (check_offset) 311 offset = check_offset; 312 break; 313 case COMBIOS_DYN_CLK_2_TABLE: 314 check_offset = RBIOS16(rdev->bios_header_start + 0x6c); 315 if (check_offset) 316 offset = check_offset; 317 break; 318 case COMBIOS_POWER_CONNECTOR_INFO_TABLE: 319 check_offset = RBIOS16(rdev->bios_header_start + 0x6e); 320 if (check_offset) 321 offset = check_offset; 322 break; 323 case COMBIOS_I2C_INFO_TABLE: 324 check_offset = RBIOS16(rdev->bios_header_start + 0x70); 325 if (check_offset) 326 offset = check_offset; 327 break; 328 /* relative offset tables */ 329 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */ 330 check_offset = 331 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 332 if (check_offset) { 333 rev = RBIOS8(check_offset); 334 if (rev > 0) { 335 check_offset = RBIOS16(check_offset + 0x3); 336 if (check_offset) 337 offset = check_offset; 338 } 339 } 340 break; 341 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */ 342 check_offset = 343 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 344 if (check_offset) { 345 rev = RBIOS8(check_offset); 346 if (rev > 0) { 347 check_offset = RBIOS16(check_offset + 0x5); 348 if (check_offset) 349 offset = check_offset; 350 } 351 } 352 break; 353 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */ 354 check_offset = 355 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 356 if (check_offset) { 357 rev = RBIOS8(check_offset); 358 if (rev > 0) { 359 check_offset = RBIOS16(check_offset + 0x7); 360 if (check_offset) 361 offset = check_offset; 362 } 363 } 364 break; 365 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */ 366 check_offset = 367 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 368 if (check_offset) { 369 rev = RBIOS8(check_offset); 370 if (rev == 2) { 371 check_offset = RBIOS16(check_offset + 0x9); 372 if (check_offset) 373 offset = check_offset; 374 } 375 } 376 break; 377 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */ 378 check_offset = 379 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 380 if (check_offset) { 381 while (RBIOS8(check_offset++)); 382 check_offset += 2; 383 if (check_offset) 384 offset = check_offset; 385 } 386 break; 387 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */ 388 check_offset = 389 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 390 if (check_offset) { 391 check_offset = RBIOS16(check_offset + 0x11); 392 if (check_offset) 393 offset = check_offset; 394 } 395 break; 396 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */ 397 check_offset = 398 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 399 if (check_offset) { 400 check_offset = RBIOS16(check_offset + 0x13); 401 if (check_offset) 402 offset = check_offset; 403 } 404 break; 405 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */ 406 check_offset = 407 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 408 if (check_offset) { 409 check_offset = RBIOS16(check_offset + 0x15); 410 if (check_offset) 411 offset = check_offset; 412 } 413 break; 414 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */ 415 check_offset = 416 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 417 if (check_offset) { 418 check_offset = RBIOS16(check_offset + 0x17); 419 if (check_offset) 420 offset = check_offset; 421 } 422 break; 423 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */ 424 check_offset = 425 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 426 if (check_offset) { 427 check_offset = RBIOS16(check_offset + 0x2); 428 if (check_offset) 429 offset = check_offset; 430 } 431 break; 432 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */ 433 check_offset = 434 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 435 if (check_offset) { 436 check_offset = RBIOS16(check_offset + 0x4); 437 if (check_offset) 438 offset = check_offset; 439 } 440 break; 441 default: 442 break; 443 } 444 445 return offset; 446 447} 448 449bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev) 450{ 451 int edid_info; 452 struct edid *edid; 453 unsigned char *raw; 454 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE); 455 if (!edid_info) 456 return false; 457 458 raw = rdev->bios + edid_info; 459 edid = kmalloc(EDID_LENGTH * (raw[0x7e] + 1), GFP_KERNEL); 460 if (edid == NULL) 461 return false; 462 463 memcpy((unsigned char *)edid, raw, EDID_LENGTH * (raw[0x7e] + 1)); 464 465 if (!drm_edid_is_valid(edid)) { 466 kfree(edid); 467 return false; 468 } 469 470 rdev->mode_info.bios_hardcoded_edid = edid; 471 return true; 472} 473 474struct edid * 475radeon_combios_get_hardcoded_edid(struct radeon_device *rdev) 476{ 477 if (rdev->mode_info.bios_hardcoded_edid) 478 return rdev->mode_info.bios_hardcoded_edid; 479 return NULL; 480} 481 482static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev, 483 enum radeon_combios_ddc ddc, 484 u32 clk_mask, 485 u32 data_mask) 486{ 487 struct radeon_i2c_bus_rec i2c; 488 int ddc_line = 0; 489 490 /* ddc id = mask reg 491 * DDC_NONE_DETECTED = none 492 * DDC_DVI = RADEON_GPIO_DVI_DDC 493 * DDC_VGA = RADEON_GPIO_VGA_DDC 494 * DDC_LCD = RADEON_GPIOPAD_MASK 495 * DDC_GPIO = RADEON_MDGPIO_MASK 496 * r1xx/r2xx 497 * DDC_MONID = RADEON_GPIO_MONID 498 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC 499 * r3xx 500 * DDC_MONID = RADEON_GPIO_MONID 501 * DDC_CRT2 = RADEON_GPIO_DVI_DDC 502 * rs3xx/rs4xx 503 * DDC_MONID = RADEON_GPIOPAD_MASK 504 * DDC_CRT2 = RADEON_GPIO_MONID 505 */ 506 switch (ddc) { 507 case DDC_NONE_DETECTED: 508 default: 509 ddc_line = 0; 510 break; 511 case DDC_DVI: 512 ddc_line = RADEON_GPIO_DVI_DDC; 513 break; 514 case DDC_VGA: 515 ddc_line = RADEON_GPIO_VGA_DDC; 516 break; 517 case DDC_LCD: 518 ddc_line = RADEON_GPIOPAD_MASK; 519 break; 520 case DDC_GPIO: 521 ddc_line = RADEON_MDGPIO_MASK; 522 break; 523 case DDC_MONID: 524 if (rdev->family == CHIP_RS300 || 525 rdev->family == CHIP_RS400 || 526 rdev->family == CHIP_RS480) 527 ddc_line = RADEON_GPIOPAD_MASK; 528 else 529 ddc_line = RADEON_GPIO_MONID; 530 break; 531 case DDC_CRT2: 532 if (rdev->family == CHIP_RS300 || 533 rdev->family == CHIP_RS400 || 534 rdev->family == CHIP_RS480) 535 ddc_line = RADEON_GPIO_MONID; 536 else if (rdev->family >= CHIP_R300) { 537 ddc_line = RADEON_GPIO_DVI_DDC; 538 ddc = DDC_DVI; 539 } else 540 ddc_line = RADEON_GPIO_CRT2_DDC; 541 break; 542 } 543 544 if (ddc_line == RADEON_GPIOPAD_MASK) { 545 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; 546 i2c.mask_data_reg = RADEON_GPIOPAD_MASK; 547 i2c.a_clk_reg = RADEON_GPIOPAD_A; 548 i2c.a_data_reg = RADEON_GPIOPAD_A; 549 i2c.en_clk_reg = RADEON_GPIOPAD_EN; 550 i2c.en_data_reg = RADEON_GPIOPAD_EN; 551 i2c.y_clk_reg = RADEON_GPIOPAD_Y; 552 i2c.y_data_reg = RADEON_GPIOPAD_Y; 553 } else if (ddc_line == RADEON_MDGPIO_MASK) { 554 i2c.mask_clk_reg = RADEON_MDGPIO_MASK; 555 i2c.mask_data_reg = RADEON_MDGPIO_MASK; 556 i2c.a_clk_reg = RADEON_MDGPIO_A; 557 i2c.a_data_reg = RADEON_MDGPIO_A; 558 i2c.en_clk_reg = RADEON_MDGPIO_EN; 559 i2c.en_data_reg = RADEON_MDGPIO_EN; 560 i2c.y_clk_reg = RADEON_MDGPIO_Y; 561 i2c.y_data_reg = RADEON_MDGPIO_Y; 562 } else { 563 i2c.mask_clk_reg = ddc_line; 564 i2c.mask_data_reg = ddc_line; 565 i2c.a_clk_reg = ddc_line; 566 i2c.a_data_reg = ddc_line; 567 i2c.en_clk_reg = ddc_line; 568 i2c.en_data_reg = ddc_line; 569 i2c.y_clk_reg = ddc_line; 570 i2c.y_data_reg = ddc_line; 571 } 572 573 if (clk_mask && data_mask) { 574 /* system specific masks */ 575 i2c.mask_clk_mask = clk_mask; 576 i2c.mask_data_mask = data_mask; 577 i2c.a_clk_mask = clk_mask; 578 i2c.a_data_mask = data_mask; 579 i2c.en_clk_mask = clk_mask; 580 i2c.en_data_mask = data_mask; 581 i2c.y_clk_mask = clk_mask; 582 i2c.y_data_mask = data_mask; 583 } else if ((ddc_line == RADEON_GPIOPAD_MASK) || 584 (ddc_line == RADEON_MDGPIO_MASK)) { 585 /* default gpiopad masks */ 586 i2c.mask_clk_mask = (0x20 << 8); 587 i2c.mask_data_mask = 0x80; 588 i2c.a_clk_mask = (0x20 << 8); 589 i2c.a_data_mask = 0x80; 590 i2c.en_clk_mask = (0x20 << 8); 591 i2c.en_data_mask = 0x80; 592 i2c.y_clk_mask = (0x20 << 8); 593 i2c.y_data_mask = 0x80; 594 } else { 595 /* default masks for ddc pads */ 596 i2c.mask_clk_mask = RADEON_GPIO_EN_1; 597 i2c.mask_data_mask = RADEON_GPIO_EN_0; 598 i2c.a_clk_mask = RADEON_GPIO_A_1; 599 i2c.a_data_mask = RADEON_GPIO_A_0; 600 i2c.en_clk_mask = RADEON_GPIO_EN_1; 601 i2c.en_data_mask = RADEON_GPIO_EN_0; 602 i2c.y_clk_mask = RADEON_GPIO_Y_1; 603 i2c.y_data_mask = RADEON_GPIO_Y_0; 604 } 605 606 switch (rdev->family) { 607 case CHIP_R100: 608 case CHIP_RV100: 609 case CHIP_RS100: 610 case CHIP_RV200: 611 case CHIP_RS200: 612 case CHIP_RS300: 613 switch (ddc_line) { 614 case RADEON_GPIO_DVI_DDC: 615 i2c.hw_capable = true; 616 break; 617 default: 618 i2c.hw_capable = false; 619 break; 620 } 621 break; 622 case CHIP_R200: 623 switch (ddc_line) { 624 case RADEON_GPIO_DVI_DDC: 625 case RADEON_GPIO_MONID: 626 i2c.hw_capable = true; 627 break; 628 default: 629 i2c.hw_capable = false; 630 break; 631 } 632 break; 633 case CHIP_RV250: 634 case CHIP_RV280: 635 switch (ddc_line) { 636 case RADEON_GPIO_VGA_DDC: 637 case RADEON_GPIO_DVI_DDC: 638 case RADEON_GPIO_CRT2_DDC: 639 i2c.hw_capable = true; 640 break; 641 default: 642 i2c.hw_capable = false; 643 break; 644 } 645 break; 646 case CHIP_R300: 647 case CHIP_R350: 648 switch (ddc_line) { 649 case RADEON_GPIO_VGA_DDC: 650 case RADEON_GPIO_DVI_DDC: 651 i2c.hw_capable = true; 652 break; 653 default: 654 i2c.hw_capable = false; 655 break; 656 } 657 break; 658 case CHIP_RV350: 659 case CHIP_RV380: 660 case CHIP_RS400: 661 case CHIP_RS480: 662 switch (ddc_line) { 663 case RADEON_GPIO_VGA_DDC: 664 case RADEON_GPIO_DVI_DDC: 665 i2c.hw_capable = true; 666 break; 667 case RADEON_GPIO_MONID: 668 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work 669 * reliably on some pre-r4xx hardware; not sure why. 670 */ 671 i2c.hw_capable = false; 672 break; 673 default: 674 i2c.hw_capable = false; 675 break; 676 } 677 break; 678 default: 679 i2c.hw_capable = false; 680 break; 681 } 682 i2c.mm_i2c = false; 683 684 i2c.i2c_id = ddc; 685 i2c.hpd = RADEON_HPD_NONE; 686 687 if (ddc_line) 688 i2c.valid = true; 689 else 690 i2c.valid = false; 691 692 return i2c; 693} 694 695void radeon_combios_i2c_init(struct radeon_device *rdev) 696{ 697 struct drm_device *dev = rdev->ddev; 698 struct radeon_i2c_bus_rec i2c; 699 700 701 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 702 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC"); 703 704 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 705 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC"); 706 707 i2c.valid = true; 708 i2c.hw_capable = true; 709 i2c.mm_i2c = true; 710 i2c.i2c_id = 0xa0; 711 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C"); 712 713 if (rdev->family == CHIP_RS300 || 714 rdev->family == CHIP_RS400 || 715 rdev->family == CHIP_RS480) { 716 u16 offset; 717 u8 id, blocks, clk, data; 718 int i; 719 720 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 721 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 722 723 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE); 724 if (offset) { 725 blocks = RBIOS8(offset + 2); 726 for (i = 0; i < blocks; i++) { 727 id = RBIOS8(offset + 3 + (i * 5) + 0); 728 if (id == 136) { 729 clk = RBIOS8(offset + 3 + (i * 5) + 3); 730 data = RBIOS8(offset + 3 + (i * 5) + 4); 731 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 732 (1 << clk), (1 << data)); 733 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK"); 734 break; 735 } 736 } 737 } 738 739 } else if (rdev->family >= CHIP_R300) { 740 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 741 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 742 } else { 743 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 744 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 745 746 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 747 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC"); 748 } 749} 750 751bool radeon_combios_get_clock_info(struct drm_device *dev) 752{ 753 struct radeon_device *rdev = dev->dev_private; 754 uint16_t pll_info; 755 struct radeon_pll *p1pll = &rdev->clock.p1pll; 756 struct radeon_pll *p2pll = &rdev->clock.p2pll; 757 struct radeon_pll *spll = &rdev->clock.spll; 758 struct radeon_pll *mpll = &rdev->clock.mpll; 759 int8_t rev; 760 uint16_t sclk, mclk; 761 762 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE); 763 if (pll_info) { 764 rev = RBIOS8(pll_info); 765 766 /* pixel clocks */ 767 p1pll->reference_freq = RBIOS16(pll_info + 0xe); 768 p1pll->reference_div = RBIOS16(pll_info + 0x10); 769 p1pll->pll_out_min = RBIOS32(pll_info + 0x12); 770 p1pll->pll_out_max = RBIOS32(pll_info + 0x16); 771 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 772 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 773 774 if (rev > 9) { 775 p1pll->pll_in_min = RBIOS32(pll_info + 0x36); 776 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a); 777 } else { 778 p1pll->pll_in_min = 40; 779 p1pll->pll_in_max = 500; 780 } 781 *p2pll = *p1pll; 782 783 /* system clock */ 784 spll->reference_freq = RBIOS16(pll_info + 0x1a); 785 spll->reference_div = RBIOS16(pll_info + 0x1c); 786 spll->pll_out_min = RBIOS32(pll_info + 0x1e); 787 spll->pll_out_max = RBIOS32(pll_info + 0x22); 788 789 if (rev > 10) { 790 spll->pll_in_min = RBIOS32(pll_info + 0x48); 791 spll->pll_in_max = RBIOS32(pll_info + 0x4c); 792 } else { 793 /* ??? */ 794 spll->pll_in_min = 40; 795 spll->pll_in_max = 500; 796 } 797 798 /* memory clock */ 799 mpll->reference_freq = RBIOS16(pll_info + 0x26); 800 mpll->reference_div = RBIOS16(pll_info + 0x28); 801 mpll->pll_out_min = RBIOS32(pll_info + 0x2a); 802 mpll->pll_out_max = RBIOS32(pll_info + 0x2e); 803 804 if (rev > 10) { 805 mpll->pll_in_min = RBIOS32(pll_info + 0x5a); 806 mpll->pll_in_max = RBIOS32(pll_info + 0x5e); 807 } else { 808 /* ??? */ 809 mpll->pll_in_min = 40; 810 mpll->pll_in_max = 500; 811 } 812 813 /* default sclk/mclk */ 814 sclk = RBIOS16(pll_info + 0xa); 815 mclk = RBIOS16(pll_info + 0x8); 816 if (sclk == 0) 817 sclk = 200 * 100; 818 if (mclk == 0) 819 mclk = 200 * 100; 820 821 rdev->clock.default_sclk = sclk; 822 rdev->clock.default_mclk = mclk; 823 824 return true; 825 } 826 return false; 827} 828 829bool radeon_combios_sideport_present(struct radeon_device *rdev) 830{ 831 struct drm_device *dev = rdev->ddev; 832 u16 igp_info; 833 834 /* sideport is AMD only */ 835 if (rdev->family == CHIP_RS400) 836 return false; 837 838 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE); 839 840 if (igp_info) { 841 if (RBIOS16(igp_info + 0x4)) 842 return true; 843 } 844 return false; 845} 846 847static const uint32_t default_primarydac_adj[CHIP_LAST] = { 848 0x00000808, /* r100 */ 849 0x00000808, /* rv100 */ 850 0x00000808, /* rs100 */ 851 0x00000808, /* rv200 */ 852 0x00000808, /* rs200 */ 853 0x00000808, /* r200 */ 854 0x00000808, /* rv250 */ 855 0x00000000, /* rs300 */ 856 0x00000808, /* rv280 */ 857 0x00000808, /* r300 */ 858 0x00000808, /* r350 */ 859 0x00000808, /* rv350 */ 860 0x00000808, /* rv380 */ 861 0x00000808, /* r420 */ 862 0x00000808, /* r423 */ 863 0x00000808, /* rv410 */ 864 0x00000000, /* rs400 */ 865 0x00000000, /* rs480 */ 866}; 867 868static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev, 869 struct radeon_encoder_primary_dac *p_dac) 870{ 871 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family]; 872 return; 873} 874 875struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct 876 radeon_encoder 877 *encoder) 878{ 879 struct drm_device *dev = encoder->base.dev; 880 struct radeon_device *rdev = dev->dev_private; 881 uint16_t dac_info; 882 uint8_t rev, bg, dac; 883 struct radeon_encoder_primary_dac *p_dac = NULL; 884 int found = 0; 885 886 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), 887 GFP_KERNEL); 888 889 if (!p_dac) 890 return NULL; 891 892 /* check CRT table */ 893 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 894 if (dac_info) { 895 rev = RBIOS8(dac_info) & 0x3; 896 if (rev < 2) { 897 bg = RBIOS8(dac_info + 0x2) & 0xf; 898 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf; 899 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 900 } else { 901 bg = RBIOS8(dac_info + 0x2) & 0xf; 902 dac = RBIOS8(dac_info + 0x3) & 0xf; 903 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 904 } 905 /* if the values are all zeros, use the table */ 906 if (p_dac->ps2_pdac_adj) 907 found = 1; 908 } 909 910 if (!found) /* fallback to defaults */ 911 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac); 912 913 return p_dac; 914} 915 916enum radeon_tv_std 917radeon_combios_get_tv_info(struct radeon_device *rdev) 918{ 919 struct drm_device *dev = rdev->ddev; 920 uint16_t tv_info; 921 enum radeon_tv_std tv_std = TV_STD_NTSC; 922 923 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 924 if (tv_info) { 925 if (RBIOS8(tv_info + 6) == 'T') { 926 switch (RBIOS8(tv_info + 7) & 0xf) { 927 case 1: 928 tv_std = TV_STD_NTSC; 929 DRM_DEBUG_KMS("Default TV standard: NTSC\n"); 930 break; 931 case 2: 932 tv_std = TV_STD_PAL; 933 DRM_DEBUG_KMS("Default TV standard: PAL\n"); 934 break; 935 case 3: 936 tv_std = TV_STD_PAL_M; 937 DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); 938 break; 939 case 4: 940 tv_std = TV_STD_PAL_60; 941 DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); 942 break; 943 case 5: 944 tv_std = TV_STD_NTSC_J; 945 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); 946 break; 947 case 6: 948 tv_std = TV_STD_SCART_PAL; 949 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n"); 950 break; 951 default: 952 tv_std = TV_STD_NTSC; 953 DRM_DEBUG_KMS 954 ("Unknown TV standard; defaulting to NTSC\n"); 955 break; 956 } 957 958 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) { 959 case 0: 960 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n"); 961 break; 962 case 1: 963 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n"); 964 break; 965 case 2: 966 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n"); 967 break; 968 case 3: 969 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n"); 970 break; 971 default: 972 break; 973 } 974 } 975 } 976 return tv_std; 977} 978 979static const uint32_t default_tvdac_adj[CHIP_LAST] = { 980 0x00000000, /* r100 */ 981 0x00280000, /* rv100 */ 982 0x00000000, /* rs100 */ 983 0x00880000, /* rv200 */ 984 0x00000000, /* rs200 */ 985 0x00000000, /* r200 */ 986 0x00770000, /* rv250 */ 987 0x00290000, /* rs300 */ 988 0x00560000, /* rv280 */ 989 0x00780000, /* r300 */ 990 0x00770000, /* r350 */ 991 0x00780000, /* rv350 */ 992 0x00780000, /* rv380 */ 993 0x01080000, /* r420 */ 994 0x01080000, /* r423 */ 995 0x01080000, /* rv410 */ 996 0x00780000, /* rs400 */ 997 0x00780000, /* rs480 */ 998}; 999 1000static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev, 1001 struct radeon_encoder_tv_dac *tv_dac) 1002{ 1003 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family]; 1004 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250)) 1005 tv_dac->ps2_tvdac_adj = 0x00880000; 1006 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1007 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1008 return; 1009} 1010 1011struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct 1012 radeon_encoder 1013 *encoder) 1014{ 1015 struct drm_device *dev = encoder->base.dev; 1016 struct radeon_device *rdev = dev->dev_private; 1017 uint16_t dac_info; 1018 uint8_t rev, bg, dac; 1019 struct radeon_encoder_tv_dac *tv_dac = NULL; 1020 int found = 0; 1021 1022 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); 1023 if (!tv_dac) 1024 return NULL; 1025 1026 /* first check TV table */ 1027 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 1028 if (dac_info) { 1029 rev = RBIOS8(dac_info + 0x3); 1030 if (rev > 4) { 1031 bg = RBIOS8(dac_info + 0xc) & 0xf; 1032 dac = RBIOS8(dac_info + 0xd) & 0xf; 1033 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1034 1035 bg = RBIOS8(dac_info + 0xe) & 0xf; 1036 dac = RBIOS8(dac_info + 0xf) & 0xf; 1037 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1038 1039 bg = RBIOS8(dac_info + 0x10) & 0xf; 1040 dac = RBIOS8(dac_info + 0x11) & 0xf; 1041 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1042 /* if the values are all zeros, use the table */ 1043 if (tv_dac->ps2_tvdac_adj) 1044 found = 1; 1045 } else if (rev > 1) { 1046 bg = RBIOS8(dac_info + 0xc) & 0xf; 1047 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf; 1048 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1049 1050 bg = RBIOS8(dac_info + 0xd) & 0xf; 1051 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf; 1052 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1053 1054 bg = RBIOS8(dac_info + 0xe) & 0xf; 1055 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf; 1056 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1057 /* if the values are all zeros, use the table */ 1058 if (tv_dac->ps2_tvdac_adj) 1059 found = 1; 1060 } 1061 tv_dac->tv_std = radeon_combios_get_tv_info(rdev); 1062 } 1063 if (!found) { 1064 /* then check CRT table */ 1065 dac_info = 1066 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 1067 if (dac_info) { 1068 rev = RBIOS8(dac_info) & 0x3; 1069 if (rev < 2) { 1070 bg = RBIOS8(dac_info + 0x3) & 0xf; 1071 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf; 1072 tv_dac->ps2_tvdac_adj = 1073 (bg << 16) | (dac << 20); 1074 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1075 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1076 /* if the values are all zeros, use the table */ 1077 if (tv_dac->ps2_tvdac_adj) 1078 found = 1; 1079 } else { 1080 bg = RBIOS8(dac_info + 0x4) & 0xf; 1081 dac = RBIOS8(dac_info + 0x5) & 0xf; 1082 tv_dac->ps2_tvdac_adj = 1083 (bg << 16) | (dac << 20); 1084 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1085 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1086 /* if the values are all zeros, use the table */ 1087 if (tv_dac->ps2_tvdac_adj) 1088 found = 1; 1089 } 1090 } else { 1091 DRM_INFO("No TV DAC info found in BIOS\n"); 1092 } 1093 } 1094 1095 if (!found) /* fallback to defaults */ 1096 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac); 1097 1098 return tv_dac; 1099} 1100 1101static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct 1102 radeon_device 1103 *rdev) 1104{ 1105 struct radeon_encoder_lvds *lvds = NULL; 1106 uint32_t fp_vert_stretch, fp_horz_stretch; 1107 uint32_t ppll_div_sel, ppll_val; 1108 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); 1109 1110 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); 1111 1112 if (!lvds) 1113 return NULL; 1114 1115 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH); 1116 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH); 1117 1118 /* These should be fail-safe defaults, fingers crossed */ 1119 lvds->panel_pwr_delay = 200; 1120 lvds->panel_vcc_delay = 2000; 1121 1122 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 1123 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf; 1124 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf; 1125 1126 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) 1127 lvds->native_mode.vdisplay = 1128 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >> 1129 RADEON_VERT_PANEL_SHIFT) + 1; 1130 else 1131 lvds->native_mode.vdisplay = 1132 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1; 1133 1134 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE) 1135 lvds->native_mode.hdisplay = 1136 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >> 1137 RADEON_HORZ_PANEL_SHIFT) + 1) * 8; 1138 else 1139 lvds->native_mode.hdisplay = 1140 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8; 1141 1142 if ((lvds->native_mode.hdisplay < 640) || 1143 (lvds->native_mode.vdisplay < 480)) { 1144 lvds->native_mode.hdisplay = 640; 1145 lvds->native_mode.vdisplay = 480; 1146 } 1147 1148 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; 1149 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel); 1150 if ((ppll_val & 0x000707ff) == 0x1bb) 1151 lvds->use_bios_dividers = false; 1152 else { 1153 lvds->panel_ref_divider = 1154 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; 1155 lvds->panel_post_divider = (ppll_val >> 16) & 0x7; 1156 lvds->panel_fb_divider = ppll_val & 0x7ff; 1157 1158 if ((lvds->panel_ref_divider != 0) && 1159 (lvds->panel_fb_divider > 3)) 1160 lvds->use_bios_dividers = true; 1161 } 1162 lvds->panel_vcc_delay = 200; 1163 1164 DRM_INFO("Panel info derived from registers\n"); 1165 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 1166 lvds->native_mode.vdisplay); 1167 1168 return lvds; 1169} 1170 1171struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder 1172 *encoder) 1173{ 1174 struct drm_device *dev = encoder->base.dev; 1175 struct radeon_device *rdev = dev->dev_private; 1176 uint16_t lcd_info; 1177 uint32_t panel_setup; 1178 char stmp[30]; 1179 int tmp, i; 1180 struct radeon_encoder_lvds *lvds = NULL; 1181 1182 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 1183 1184 if (lcd_info) { 1185 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); 1186 1187 if (!lvds) 1188 return NULL; 1189 1190 for (i = 0; i < 24; i++) 1191 stmp[i] = RBIOS8(lcd_info + i + 1); 1192 stmp[24] = 0; 1193 1194 DRM_INFO("Panel ID String: %s\n", stmp); 1195 1196 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19); 1197 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b); 1198 1199 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 1200 lvds->native_mode.vdisplay); 1201 1202 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c); 1203 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000); 1204 1205 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24); 1206 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf; 1207 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf; 1208 1209 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e); 1210 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30); 1211 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31); 1212 if ((lvds->panel_ref_divider != 0) && 1213 (lvds->panel_fb_divider > 3)) 1214 lvds->use_bios_dividers = true; 1215 1216 panel_setup = RBIOS32(lcd_info + 0x39); 1217 lvds->lvds_gen_cntl = 0xff00; 1218 if (panel_setup & 0x1) 1219 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT; 1220 1221 if ((panel_setup >> 4) & 0x1) 1222 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE; 1223 1224 switch ((panel_setup >> 8) & 0x7) { 1225 case 0: 1226 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM; 1227 break; 1228 case 1: 1229 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY; 1230 break; 1231 case 2: 1232 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY; 1233 break; 1234 default: 1235 break; 1236 } 1237 1238 if ((panel_setup >> 16) & 0x1) 1239 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW; 1240 1241 if ((panel_setup >> 17) & 0x1) 1242 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW; 1243 1244 if ((panel_setup >> 18) & 0x1) 1245 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW; 1246 1247 if ((panel_setup >> 23) & 0x1) 1248 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL; 1249 1250 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000); 1251 1252 for (i = 0; i < 32; i++) { 1253 tmp = RBIOS16(lcd_info + 64 + i * 2); 1254 if (tmp == 0) 1255 break; 1256 1257 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) && 1258 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) { 1259 lvds->native_mode.htotal = lvds->native_mode.hdisplay + 1260 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8; 1261 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + 1262 (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8; 1263 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + 1264 (RBIOS8(tmp + 23) * 8); 1265 1266 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + 1267 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26)); 1268 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + 1269 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26)); 1270 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + 1271 ((RBIOS16(tmp + 28) & 0xf800) >> 11); 1272 1273 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10; 1274 lvds->native_mode.flags = 0; 1275 /* set crtc values */ 1276 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); 1277 1278 } 1279 } 1280 } else { 1281 DRM_INFO("No panel info found in BIOS\n"); 1282 lvds = radeon_legacy_get_lvds_info_from_regs(rdev); 1283 } 1284 1285 if (lvds) 1286 encoder->native_mode = lvds->native_mode; 1287 return lvds; 1288} 1289 1290static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = { 1291 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */ 1292 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */ 1293 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */ 1294 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */ 1295 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */ 1296 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */ 1297 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */ 1298 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */ 1299 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */ 1300 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */ 1301 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */ 1302 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */ 1303 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */ 1304 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */ 1305 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */ 1306 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */ 1307 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */ 1308 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */ 1309}; 1310 1311bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 1312 struct radeon_encoder_int_tmds *tmds) 1313{ 1314 struct drm_device *dev = encoder->base.dev; 1315 struct radeon_device *rdev = dev->dev_private; 1316 int i; 1317 1318 for (i = 0; i < 4; i++) { 1319 tmds->tmds_pll[i].value = 1320 default_tmds_pll[rdev->family][i].value; 1321 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq; 1322 } 1323 1324 return true; 1325} 1326 1327bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 1328 struct radeon_encoder_int_tmds *tmds) 1329{ 1330 struct drm_device *dev = encoder->base.dev; 1331 struct radeon_device *rdev = dev->dev_private; 1332 uint16_t tmds_info; 1333 int i, n; 1334 uint8_t ver; 1335 1336 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 1337 1338 if (tmds_info) { 1339 ver = RBIOS8(tmds_info); 1340 DRM_DEBUG_KMS("DFP table revision: %d\n", ver); 1341 if (ver == 3) { 1342 n = RBIOS8(tmds_info + 5) + 1; 1343 if (n > 4) 1344 n = 4; 1345 for (i = 0; i < n; i++) { 1346 tmds->tmds_pll[i].value = 1347 RBIOS32(tmds_info + i * 10 + 0x08); 1348 tmds->tmds_pll[i].freq = 1349 RBIOS16(tmds_info + i * 10 + 0x10); 1350 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", 1351 tmds->tmds_pll[i].freq, 1352 tmds->tmds_pll[i].value); 1353 } 1354 } else if (ver == 4) { 1355 int stride = 0; 1356 n = RBIOS8(tmds_info + 5) + 1; 1357 if (n > 4) 1358 n = 4; 1359 for (i = 0; i < n; i++) { 1360 tmds->tmds_pll[i].value = 1361 RBIOS32(tmds_info + stride + 0x08); 1362 tmds->tmds_pll[i].freq = 1363 RBIOS16(tmds_info + stride + 0x10); 1364 if (i == 0) 1365 stride += 10; 1366 else 1367 stride += 6; 1368 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", 1369 tmds->tmds_pll[i].freq, 1370 tmds->tmds_pll[i].value); 1371 } 1372 } 1373 } else { 1374 DRM_INFO("No TMDS info found in BIOS\n"); 1375 return false; 1376 } 1377 return true; 1378} 1379 1380bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 1381 struct radeon_encoder_ext_tmds *tmds) 1382{ 1383 struct drm_device *dev = encoder->base.dev; 1384 struct radeon_device *rdev = dev->dev_private; 1385 struct radeon_i2c_bus_rec i2c_bus; 1386 1387 /* default for macs */ 1388 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1389 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1390 1391 /* XXX some macs have duallink chips */ 1392 switch (rdev->mode_info.connector_table) { 1393 case CT_POWERBOOK_EXTERNAL: 1394 case CT_MINI_EXTERNAL: 1395 default: 1396 tmds->dvo_chip = DVO_SIL164; 1397 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1398 break; 1399 } 1400 1401 return true; 1402} 1403 1404bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 1405 struct radeon_encoder_ext_tmds *tmds) 1406{ 1407 struct drm_device *dev = encoder->base.dev; 1408 struct radeon_device *rdev = dev->dev_private; 1409 uint16_t offset; 1410 uint8_t ver; 1411 enum radeon_combios_ddc gpio; 1412 struct radeon_i2c_bus_rec i2c_bus; 1413 1414 tmds->i2c_bus = NULL; 1415 if (rdev->flags & RADEON_IS_IGP) { 1416 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1417 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1418 tmds->dvo_chip = DVO_SIL164; 1419 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1420 } else { 1421 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 1422 if (offset) { 1423 ver = RBIOS8(offset); 1424 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver); 1425 tmds->slave_addr = RBIOS8(offset + 4 + 2); 1426 tmds->slave_addr >>= 1; /* 7 bit addressing */ 1427 gpio = RBIOS8(offset + 4 + 3); 1428 if (gpio == DDC_LCD) { 1429 /* MM i2c */ 1430 i2c_bus.valid = true; 1431 i2c_bus.hw_capable = true; 1432 i2c_bus.mm_i2c = true; 1433 i2c_bus.i2c_id = 0xa0; 1434 } else 1435 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); 1436 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1437 } 1438 } 1439 1440 if (!tmds->i2c_bus) { 1441 DRM_INFO("No valid Ext TMDS info found in BIOS\n"); 1442 return false; 1443 } 1444 1445 return true; 1446} 1447 1448bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) 1449{ 1450 struct radeon_device *rdev = dev->dev_private; 1451 struct radeon_i2c_bus_rec ddc_i2c; 1452 struct radeon_hpd hpd; 1453 1454 rdev->mode_info.connector_table = radeon_connector_table; 1455 if (rdev->mode_info.connector_table == CT_NONE) { 1456#ifdef CONFIG_PPC_PMAC 1457 if (of_machine_is_compatible("PowerBook3,3")) { 1458 /* powerbook with VGA */ 1459 rdev->mode_info.connector_table = CT_POWERBOOK_VGA; 1460 } else if (of_machine_is_compatible("PowerBook3,4") || 1461 of_machine_is_compatible("PowerBook3,5")) { 1462 /* powerbook with internal tmds */ 1463 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL; 1464 } else if (of_machine_is_compatible("PowerBook5,1") || 1465 of_machine_is_compatible("PowerBook5,2") || 1466 of_machine_is_compatible("PowerBook5,3") || 1467 of_machine_is_compatible("PowerBook5,4") || 1468 of_machine_is_compatible("PowerBook5,5")) { 1469 /* powerbook with external single link tmds (sil164) */ 1470 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1471 } else if (of_machine_is_compatible("PowerBook5,6")) { 1472 /* powerbook with external dual or single link tmds */ 1473 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1474 } else if (of_machine_is_compatible("PowerBook5,7") || 1475 of_machine_is_compatible("PowerBook5,8") || 1476 of_machine_is_compatible("PowerBook5,9")) { 1477 /* PowerBook6,2 ? */ 1478 /* powerbook with external dual link tmds (sil1178?) */ 1479 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1480 } else if (of_machine_is_compatible("PowerBook4,1") || 1481 of_machine_is_compatible("PowerBook4,2") || 1482 of_machine_is_compatible("PowerBook4,3") || 1483 of_machine_is_compatible("PowerBook6,3") || 1484 of_machine_is_compatible("PowerBook6,5") || 1485 of_machine_is_compatible("PowerBook6,7")) { 1486 /* ibook */ 1487 rdev->mode_info.connector_table = CT_IBOOK; 1488 } else if (of_machine_is_compatible("PowerMac4,4")) { 1489 /* emac */ 1490 rdev->mode_info.connector_table = CT_EMAC; 1491 } else if (of_machine_is_compatible("PowerMac10,1")) { 1492 /* mini with internal tmds */ 1493 rdev->mode_info.connector_table = CT_MINI_INTERNAL; 1494 } else if (of_machine_is_compatible("PowerMac10,2")) { 1495 /* mini with external tmds */ 1496 rdev->mode_info.connector_table = CT_MINI_EXTERNAL; 1497 } else if (of_machine_is_compatible("PowerMac12,1")) { 1498 /* PowerMac8,1 ? */ 1499 /* imac g5 isight */ 1500 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT; 1501 } else if ((rdev->pdev->device == 0x4a48) && 1502 (rdev->pdev->subsystem_vendor == 0x1002) && 1503 (rdev->pdev->subsystem_device == 0x4a48)) { 1504 /* Mac X800 */ 1505 rdev->mode_info.connector_table = CT_MAC_X800; 1506 } else 1507#endif /* CONFIG_PPC_PMAC */ 1508#ifdef CONFIG_PPC64 1509 if (ASIC_IS_RN50(rdev)) 1510 rdev->mode_info.connector_table = CT_RN50_POWER; 1511 else 1512#endif 1513 rdev->mode_info.connector_table = CT_GENERIC; 1514 } 1515 1516 switch (rdev->mode_info.connector_table) { 1517 case CT_GENERIC: 1518 DRM_INFO("Connector Table: %d (generic)\n", 1519 rdev->mode_info.connector_table); 1520 /* these are the most common settings */ 1521 if (rdev->flags & RADEON_SINGLE_CRTC) { 1522 /* VGA - primary dac */ 1523 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1524 hpd.hpd = RADEON_HPD_NONE; 1525 radeon_add_legacy_encoder(dev, 1526 radeon_get_encoder_enum(dev, 1527 ATOM_DEVICE_CRT1_SUPPORT, 1528 1), 1529 ATOM_DEVICE_CRT1_SUPPORT); 1530 radeon_add_legacy_connector(dev, 0, 1531 ATOM_DEVICE_CRT1_SUPPORT, 1532 DRM_MODE_CONNECTOR_VGA, 1533 &ddc_i2c, 1534 CONNECTOR_OBJECT_ID_VGA, 1535 &hpd); 1536 } else if (rdev->flags & RADEON_IS_MOBILITY) { 1537 /* LVDS */ 1538 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); 1539 hpd.hpd = RADEON_HPD_NONE; 1540 radeon_add_legacy_encoder(dev, 1541 radeon_get_encoder_enum(dev, 1542 ATOM_DEVICE_LCD1_SUPPORT, 1543 0), 1544 ATOM_DEVICE_LCD1_SUPPORT); 1545 radeon_add_legacy_connector(dev, 0, 1546 ATOM_DEVICE_LCD1_SUPPORT, 1547 DRM_MODE_CONNECTOR_LVDS, 1548 &ddc_i2c, 1549 CONNECTOR_OBJECT_ID_LVDS, 1550 &hpd); 1551 1552 /* VGA - primary dac */ 1553 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1554 hpd.hpd = RADEON_HPD_NONE; 1555 radeon_add_legacy_encoder(dev, 1556 radeon_get_encoder_enum(dev, 1557 ATOM_DEVICE_CRT1_SUPPORT, 1558 1), 1559 ATOM_DEVICE_CRT1_SUPPORT); 1560 radeon_add_legacy_connector(dev, 1, 1561 ATOM_DEVICE_CRT1_SUPPORT, 1562 DRM_MODE_CONNECTOR_VGA, 1563 &ddc_i2c, 1564 CONNECTOR_OBJECT_ID_VGA, 1565 &hpd); 1566 } else { 1567 /* DVI-I - tv dac, int tmds */ 1568 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1569 hpd.hpd = RADEON_HPD_1; 1570 radeon_add_legacy_encoder(dev, 1571 radeon_get_encoder_enum(dev, 1572 ATOM_DEVICE_DFP1_SUPPORT, 1573 0), 1574 ATOM_DEVICE_DFP1_SUPPORT); 1575 radeon_add_legacy_encoder(dev, 1576 radeon_get_encoder_enum(dev, 1577 ATOM_DEVICE_CRT2_SUPPORT, 1578 2), 1579 ATOM_DEVICE_CRT2_SUPPORT); 1580 radeon_add_legacy_connector(dev, 0, 1581 ATOM_DEVICE_DFP1_SUPPORT | 1582 ATOM_DEVICE_CRT2_SUPPORT, 1583 DRM_MODE_CONNECTOR_DVII, 1584 &ddc_i2c, 1585 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1586 &hpd); 1587 1588 /* VGA - primary dac */ 1589 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1590 hpd.hpd = RADEON_HPD_NONE; 1591 radeon_add_legacy_encoder(dev, 1592 radeon_get_encoder_enum(dev, 1593 ATOM_DEVICE_CRT1_SUPPORT, 1594 1), 1595 ATOM_DEVICE_CRT1_SUPPORT); 1596 radeon_add_legacy_connector(dev, 1, 1597 ATOM_DEVICE_CRT1_SUPPORT, 1598 DRM_MODE_CONNECTOR_VGA, 1599 &ddc_i2c, 1600 CONNECTOR_OBJECT_ID_VGA, 1601 &hpd); 1602 } 1603 1604 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 1605 /* TV - tv dac */ 1606 ddc_i2c.valid = false; 1607 hpd.hpd = RADEON_HPD_NONE; 1608 radeon_add_legacy_encoder(dev, 1609 radeon_get_encoder_enum(dev, 1610 ATOM_DEVICE_TV1_SUPPORT, 1611 2), 1612 ATOM_DEVICE_TV1_SUPPORT); 1613 radeon_add_legacy_connector(dev, 2, 1614 ATOM_DEVICE_TV1_SUPPORT, 1615 DRM_MODE_CONNECTOR_SVIDEO, 1616 &ddc_i2c, 1617 CONNECTOR_OBJECT_ID_SVIDEO, 1618 &hpd); 1619 } 1620 break; 1621 case CT_IBOOK: 1622 DRM_INFO("Connector Table: %d (ibook)\n", 1623 rdev->mode_info.connector_table); 1624 /* LVDS */ 1625 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1626 hpd.hpd = RADEON_HPD_NONE; 1627 radeon_add_legacy_encoder(dev, 1628 radeon_get_encoder_enum(dev, 1629 ATOM_DEVICE_LCD1_SUPPORT, 1630 0), 1631 ATOM_DEVICE_LCD1_SUPPORT); 1632 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1633 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1634 CONNECTOR_OBJECT_ID_LVDS, 1635 &hpd); 1636 /* VGA - TV DAC */ 1637 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1638 hpd.hpd = RADEON_HPD_NONE; 1639 radeon_add_legacy_encoder(dev, 1640 radeon_get_encoder_enum(dev, 1641 ATOM_DEVICE_CRT2_SUPPORT, 1642 2), 1643 ATOM_DEVICE_CRT2_SUPPORT); 1644 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1645 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1646 CONNECTOR_OBJECT_ID_VGA, 1647 &hpd); 1648 /* TV - TV DAC */ 1649 ddc_i2c.valid = false; 1650 hpd.hpd = RADEON_HPD_NONE; 1651 radeon_add_legacy_encoder(dev, 1652 radeon_get_encoder_enum(dev, 1653 ATOM_DEVICE_TV1_SUPPORT, 1654 2), 1655 ATOM_DEVICE_TV1_SUPPORT); 1656 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1657 DRM_MODE_CONNECTOR_SVIDEO, 1658 &ddc_i2c, 1659 CONNECTOR_OBJECT_ID_SVIDEO, 1660 &hpd); 1661 break; 1662 case CT_POWERBOOK_EXTERNAL: 1663 DRM_INFO("Connector Table: %d (powerbook external tmds)\n", 1664 rdev->mode_info.connector_table); 1665 /* LVDS */ 1666 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1667 hpd.hpd = RADEON_HPD_NONE; 1668 radeon_add_legacy_encoder(dev, 1669 radeon_get_encoder_enum(dev, 1670 ATOM_DEVICE_LCD1_SUPPORT, 1671 0), 1672 ATOM_DEVICE_LCD1_SUPPORT); 1673 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1674 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1675 CONNECTOR_OBJECT_ID_LVDS, 1676 &hpd); 1677 /* DVI-I - primary dac, ext tmds */ 1678 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1679 hpd.hpd = RADEON_HPD_2; /* ??? */ 1680 radeon_add_legacy_encoder(dev, 1681 radeon_get_encoder_enum(dev, 1682 ATOM_DEVICE_DFP2_SUPPORT, 1683 0), 1684 ATOM_DEVICE_DFP2_SUPPORT); 1685 radeon_add_legacy_encoder(dev, 1686 radeon_get_encoder_enum(dev, 1687 ATOM_DEVICE_CRT1_SUPPORT, 1688 1), 1689 ATOM_DEVICE_CRT1_SUPPORT); 1690 /* XXX some are SL */ 1691 radeon_add_legacy_connector(dev, 1, 1692 ATOM_DEVICE_DFP2_SUPPORT | 1693 ATOM_DEVICE_CRT1_SUPPORT, 1694 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1695 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, 1696 &hpd); 1697 /* TV - TV DAC */ 1698 ddc_i2c.valid = false; 1699 hpd.hpd = RADEON_HPD_NONE; 1700 radeon_add_legacy_encoder(dev, 1701 radeon_get_encoder_enum(dev, 1702 ATOM_DEVICE_TV1_SUPPORT, 1703 2), 1704 ATOM_DEVICE_TV1_SUPPORT); 1705 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1706 DRM_MODE_CONNECTOR_SVIDEO, 1707 &ddc_i2c, 1708 CONNECTOR_OBJECT_ID_SVIDEO, 1709 &hpd); 1710 break; 1711 case CT_POWERBOOK_INTERNAL: 1712 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n", 1713 rdev->mode_info.connector_table); 1714 /* LVDS */ 1715 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1716 hpd.hpd = RADEON_HPD_NONE; 1717 radeon_add_legacy_encoder(dev, 1718 radeon_get_encoder_enum(dev, 1719 ATOM_DEVICE_LCD1_SUPPORT, 1720 0), 1721 ATOM_DEVICE_LCD1_SUPPORT); 1722 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1723 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1724 CONNECTOR_OBJECT_ID_LVDS, 1725 &hpd); 1726 /* DVI-I - primary dac, int tmds */ 1727 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1728 hpd.hpd = RADEON_HPD_1; /* ??? */ 1729 radeon_add_legacy_encoder(dev, 1730 radeon_get_encoder_enum(dev, 1731 ATOM_DEVICE_DFP1_SUPPORT, 1732 0), 1733 ATOM_DEVICE_DFP1_SUPPORT); 1734 radeon_add_legacy_encoder(dev, 1735 radeon_get_encoder_enum(dev, 1736 ATOM_DEVICE_CRT1_SUPPORT, 1737 1), 1738 ATOM_DEVICE_CRT1_SUPPORT); 1739 radeon_add_legacy_connector(dev, 1, 1740 ATOM_DEVICE_DFP1_SUPPORT | 1741 ATOM_DEVICE_CRT1_SUPPORT, 1742 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1743 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1744 &hpd); 1745 /* TV - TV DAC */ 1746 ddc_i2c.valid = false; 1747 hpd.hpd = RADEON_HPD_NONE; 1748 radeon_add_legacy_encoder(dev, 1749 radeon_get_encoder_enum(dev, 1750 ATOM_DEVICE_TV1_SUPPORT, 1751 2), 1752 ATOM_DEVICE_TV1_SUPPORT); 1753 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1754 DRM_MODE_CONNECTOR_SVIDEO, 1755 &ddc_i2c, 1756 CONNECTOR_OBJECT_ID_SVIDEO, 1757 &hpd); 1758 break; 1759 case CT_POWERBOOK_VGA: 1760 DRM_INFO("Connector Table: %d (powerbook vga)\n", 1761 rdev->mode_info.connector_table); 1762 /* LVDS */ 1763 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1764 hpd.hpd = RADEON_HPD_NONE; 1765 radeon_add_legacy_encoder(dev, 1766 radeon_get_encoder_enum(dev, 1767 ATOM_DEVICE_LCD1_SUPPORT, 1768 0), 1769 ATOM_DEVICE_LCD1_SUPPORT); 1770 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1771 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1772 CONNECTOR_OBJECT_ID_LVDS, 1773 &hpd); 1774 /* VGA - primary dac */ 1775 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1776 hpd.hpd = RADEON_HPD_NONE; 1777 radeon_add_legacy_encoder(dev, 1778 radeon_get_encoder_enum(dev, 1779 ATOM_DEVICE_CRT1_SUPPORT, 1780 1), 1781 ATOM_DEVICE_CRT1_SUPPORT); 1782 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, 1783 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1784 CONNECTOR_OBJECT_ID_VGA, 1785 &hpd); 1786 /* TV - TV DAC */ 1787 ddc_i2c.valid = false; 1788 hpd.hpd = RADEON_HPD_NONE; 1789 radeon_add_legacy_encoder(dev, 1790 radeon_get_encoder_enum(dev, 1791 ATOM_DEVICE_TV1_SUPPORT, 1792 2), 1793 ATOM_DEVICE_TV1_SUPPORT); 1794 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1795 DRM_MODE_CONNECTOR_SVIDEO, 1796 &ddc_i2c, 1797 CONNECTOR_OBJECT_ID_SVIDEO, 1798 &hpd); 1799 break; 1800 case CT_MINI_EXTERNAL: 1801 DRM_INFO("Connector Table: %d (mini external tmds)\n", 1802 rdev->mode_info.connector_table); 1803 /* DVI-I - tv dac, ext tmds */ 1804 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1805 hpd.hpd = RADEON_HPD_2; /* ??? */ 1806 radeon_add_legacy_encoder(dev, 1807 radeon_get_encoder_enum(dev, 1808 ATOM_DEVICE_DFP2_SUPPORT, 1809 0), 1810 ATOM_DEVICE_DFP2_SUPPORT); 1811 radeon_add_legacy_encoder(dev, 1812 radeon_get_encoder_enum(dev, 1813 ATOM_DEVICE_CRT2_SUPPORT, 1814 2), 1815 ATOM_DEVICE_CRT2_SUPPORT); 1816 /* XXX are any DL? */ 1817 radeon_add_legacy_connector(dev, 0, 1818 ATOM_DEVICE_DFP2_SUPPORT | 1819 ATOM_DEVICE_CRT2_SUPPORT, 1820 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1821 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1822 &hpd); 1823 /* TV - TV DAC */ 1824 ddc_i2c.valid = false; 1825 hpd.hpd = RADEON_HPD_NONE; 1826 radeon_add_legacy_encoder(dev, 1827 radeon_get_encoder_enum(dev, 1828 ATOM_DEVICE_TV1_SUPPORT, 1829 2), 1830 ATOM_DEVICE_TV1_SUPPORT); 1831 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1832 DRM_MODE_CONNECTOR_SVIDEO, 1833 &ddc_i2c, 1834 CONNECTOR_OBJECT_ID_SVIDEO, 1835 &hpd); 1836 break; 1837 case CT_MINI_INTERNAL: 1838 DRM_INFO("Connector Table: %d (mini internal tmds)\n", 1839 rdev->mode_info.connector_table); 1840 /* DVI-I - tv dac, int tmds */ 1841 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1842 hpd.hpd = RADEON_HPD_1; /* ??? */ 1843 radeon_add_legacy_encoder(dev, 1844 radeon_get_encoder_enum(dev, 1845 ATOM_DEVICE_DFP1_SUPPORT, 1846 0), 1847 ATOM_DEVICE_DFP1_SUPPORT); 1848 radeon_add_legacy_encoder(dev, 1849 radeon_get_encoder_enum(dev, 1850 ATOM_DEVICE_CRT2_SUPPORT, 1851 2), 1852 ATOM_DEVICE_CRT2_SUPPORT); 1853 radeon_add_legacy_connector(dev, 0, 1854 ATOM_DEVICE_DFP1_SUPPORT | 1855 ATOM_DEVICE_CRT2_SUPPORT, 1856 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1857 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1858 &hpd); 1859 /* TV - TV DAC */ 1860 ddc_i2c.valid = false; 1861 hpd.hpd = RADEON_HPD_NONE; 1862 radeon_add_legacy_encoder(dev, 1863 radeon_get_encoder_enum(dev, 1864 ATOM_DEVICE_TV1_SUPPORT, 1865 2), 1866 ATOM_DEVICE_TV1_SUPPORT); 1867 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1868 DRM_MODE_CONNECTOR_SVIDEO, 1869 &ddc_i2c, 1870 CONNECTOR_OBJECT_ID_SVIDEO, 1871 &hpd); 1872 break; 1873 case CT_IMAC_G5_ISIGHT: 1874 DRM_INFO("Connector Table: %d (imac g5 isight)\n", 1875 rdev->mode_info.connector_table); 1876 /* DVI-D - int tmds */ 1877 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1878 hpd.hpd = RADEON_HPD_1; /* ??? */ 1879 radeon_add_legacy_encoder(dev, 1880 radeon_get_encoder_enum(dev, 1881 ATOM_DEVICE_DFP1_SUPPORT, 1882 0), 1883 ATOM_DEVICE_DFP1_SUPPORT); 1884 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT, 1885 DRM_MODE_CONNECTOR_DVID, &ddc_i2c, 1886 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 1887 &hpd); 1888 /* VGA - tv dac */ 1889 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1890 hpd.hpd = RADEON_HPD_NONE; 1891 radeon_add_legacy_encoder(dev, 1892 radeon_get_encoder_enum(dev, 1893 ATOM_DEVICE_CRT2_SUPPORT, 1894 2), 1895 ATOM_DEVICE_CRT2_SUPPORT); 1896 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1897 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1898 CONNECTOR_OBJECT_ID_VGA, 1899 &hpd); 1900 /* TV - TV DAC */ 1901 ddc_i2c.valid = false; 1902 hpd.hpd = RADEON_HPD_NONE; 1903 radeon_add_legacy_encoder(dev, 1904 radeon_get_encoder_enum(dev, 1905 ATOM_DEVICE_TV1_SUPPORT, 1906 2), 1907 ATOM_DEVICE_TV1_SUPPORT); 1908 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1909 DRM_MODE_CONNECTOR_SVIDEO, 1910 &ddc_i2c, 1911 CONNECTOR_OBJECT_ID_SVIDEO, 1912 &hpd); 1913 break; 1914 case CT_EMAC: 1915 DRM_INFO("Connector Table: %d (emac)\n", 1916 rdev->mode_info.connector_table); 1917 /* VGA - primary dac */ 1918 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1919 hpd.hpd = RADEON_HPD_NONE; 1920 radeon_add_legacy_encoder(dev, 1921 radeon_get_encoder_enum(dev, 1922 ATOM_DEVICE_CRT1_SUPPORT, 1923 1), 1924 ATOM_DEVICE_CRT1_SUPPORT); 1925 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, 1926 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1927 CONNECTOR_OBJECT_ID_VGA, 1928 &hpd); 1929 /* VGA - tv dac */ 1930 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1931 hpd.hpd = RADEON_HPD_NONE; 1932 radeon_add_legacy_encoder(dev, 1933 radeon_get_encoder_enum(dev, 1934 ATOM_DEVICE_CRT2_SUPPORT, 1935 2), 1936 ATOM_DEVICE_CRT2_SUPPORT); 1937 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1938 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1939 CONNECTOR_OBJECT_ID_VGA, 1940 &hpd); 1941 /* TV - TV DAC */ 1942 ddc_i2c.valid = false; 1943 hpd.hpd = RADEON_HPD_NONE; 1944 radeon_add_legacy_encoder(dev, 1945 radeon_get_encoder_enum(dev, 1946 ATOM_DEVICE_TV1_SUPPORT, 1947 2), 1948 ATOM_DEVICE_TV1_SUPPORT); 1949 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1950 DRM_MODE_CONNECTOR_SVIDEO, 1951 &ddc_i2c, 1952 CONNECTOR_OBJECT_ID_SVIDEO, 1953 &hpd); 1954 break; 1955 case CT_RN50_POWER: 1956 DRM_INFO("Connector Table: %d (rn50-power)\n", 1957 rdev->mode_info.connector_table); 1958 /* VGA - primary dac */ 1959 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1960 hpd.hpd = RADEON_HPD_NONE; 1961 radeon_add_legacy_encoder(dev, 1962 radeon_get_encoder_enum(dev, 1963 ATOM_DEVICE_CRT1_SUPPORT, 1964 1), 1965 ATOM_DEVICE_CRT1_SUPPORT); 1966 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, 1967 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1968 CONNECTOR_OBJECT_ID_VGA, 1969 &hpd); 1970 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1971 hpd.hpd = RADEON_HPD_NONE; 1972 radeon_add_legacy_encoder(dev, 1973 radeon_get_encoder_enum(dev, 1974 ATOM_DEVICE_CRT2_SUPPORT, 1975 2), 1976 ATOM_DEVICE_CRT2_SUPPORT); 1977 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1978 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1979 CONNECTOR_OBJECT_ID_VGA, 1980 &hpd); 1981 break; 1982 case CT_MAC_X800: 1983 DRM_INFO("Connector Table: %d (mac x800)\n", 1984 rdev->mode_info.connector_table); 1985 /* DVI - primary dac, internal tmds */ 1986 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1987 hpd.hpd = RADEON_HPD_1; /* ??? */ 1988 radeon_add_legacy_encoder(dev, 1989 radeon_get_encoder_enum(dev, 1990 ATOM_DEVICE_DFP1_SUPPORT, 1991 0), 1992 ATOM_DEVICE_DFP1_SUPPORT); 1993 radeon_add_legacy_encoder(dev, 1994 radeon_get_encoder_enum(dev, 1995 ATOM_DEVICE_CRT1_SUPPORT, 1996 1), 1997 ATOM_DEVICE_CRT1_SUPPORT); 1998 radeon_add_legacy_connector(dev, 0, 1999 ATOM_DEVICE_DFP1_SUPPORT | 2000 ATOM_DEVICE_CRT1_SUPPORT, 2001 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2002 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2003 &hpd); 2004 /* DVI - tv dac, dvo */ 2005 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 2006 hpd.hpd = RADEON_HPD_2; /* ??? */ 2007 radeon_add_legacy_encoder(dev, 2008 radeon_get_encoder_enum(dev, 2009 ATOM_DEVICE_DFP2_SUPPORT, 2010 0), 2011 ATOM_DEVICE_DFP2_SUPPORT); 2012 radeon_add_legacy_encoder(dev, 2013 radeon_get_encoder_enum(dev, 2014 ATOM_DEVICE_CRT2_SUPPORT, 2015 2), 2016 ATOM_DEVICE_CRT2_SUPPORT); 2017 radeon_add_legacy_connector(dev, 1, 2018 ATOM_DEVICE_DFP2_SUPPORT | 2019 ATOM_DEVICE_CRT2_SUPPORT, 2020 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2021 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, 2022 &hpd); 2023 break; 2024 default: 2025 DRM_INFO("Connector table: %d (invalid)\n", 2026 rdev->mode_info.connector_table); 2027 return false; 2028 } 2029 2030 radeon_link_encoder_connector(dev); 2031 2032 return true; 2033} 2034 2035static bool radeon_apply_legacy_quirks(struct drm_device *dev, 2036 int bios_index, 2037 enum radeon_combios_connector 2038 *legacy_connector, 2039 struct radeon_i2c_bus_rec *ddc_i2c, 2040 struct radeon_hpd *hpd) 2041{ 2042 2043 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, 2044 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ 2045 if (dev->pdev->device == 0x515e && 2046 dev->pdev->subsystem_vendor == 0x1014) { 2047 if (*legacy_connector == CONNECTOR_CRT_LEGACY && 2048 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) 2049 return false; 2050 } 2051 2052 /* X300 card with extra non-existent DVI port */ 2053 if (dev->pdev->device == 0x5B60 && 2054 dev->pdev->subsystem_vendor == 0x17af && 2055 dev->pdev->subsystem_device == 0x201e && bios_index == 2) { 2056 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY) 2057 return false; 2058 } 2059 2060 return true; 2061} 2062 2063static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev) 2064{ 2065 /* Acer 5102 has non-existent TV port */ 2066 if (dev->pdev->device == 0x5975 && 2067 dev->pdev->subsystem_vendor == 0x1025 && 2068 dev->pdev->subsystem_device == 0x009f) 2069 return false; 2070 2071 /* HP dc5750 has non-existent TV port */ 2072 if (dev->pdev->device == 0x5974 && 2073 dev->pdev->subsystem_vendor == 0x103c && 2074 dev->pdev->subsystem_device == 0x280a) 2075 return false; 2076 2077 /* MSI S270 has non-existent TV port */ 2078 if (dev->pdev->device == 0x5955 && 2079 dev->pdev->subsystem_vendor == 0x1462 && 2080 dev->pdev->subsystem_device == 0x0131) 2081 return false; 2082 2083 return true; 2084} 2085 2086static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d) 2087{ 2088 struct radeon_device *rdev = dev->dev_private; 2089 uint32_t ext_tmds_info; 2090 2091 if (rdev->flags & RADEON_IS_IGP) { 2092 if (is_dvi_d) 2093 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 2094 else 2095 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2096 } 2097 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 2098 if (ext_tmds_info) { 2099 uint8_t rev = RBIOS8(ext_tmds_info); 2100 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5); 2101 if (rev >= 3) { 2102 if (is_dvi_d) 2103 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 2104 else 2105 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 2106 } else { 2107 if (flags & 1) { 2108 if (is_dvi_d) 2109 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 2110 else 2111 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 2112 } 2113 } 2114 } 2115 if (is_dvi_d) 2116 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 2117 else 2118 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2119} 2120 2121bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) 2122{ 2123 struct radeon_device *rdev = dev->dev_private; 2124 uint32_t conn_info, entry, devices; 2125 uint16_t tmp, connector_object_id; 2126 enum radeon_combios_ddc ddc_type; 2127 enum radeon_combios_connector connector; 2128 int i = 0; 2129 struct radeon_i2c_bus_rec ddc_i2c; 2130 struct radeon_hpd hpd; 2131 2132 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE); 2133 if (conn_info) { 2134 for (i = 0; i < 4; i++) { 2135 entry = conn_info + 2 + i * 2; 2136 2137 if (!RBIOS16(entry)) 2138 break; 2139 2140 tmp = RBIOS16(entry); 2141 2142 connector = (tmp >> 12) & 0xf; 2143 2144 ddc_type = (tmp >> 8) & 0xf; 2145 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0); 2146 2147 switch (connector) { 2148 case CONNECTOR_PROPRIETARY_LEGACY: 2149 case CONNECTOR_DVI_I_LEGACY: 2150 case CONNECTOR_DVI_D_LEGACY: 2151 if ((tmp >> 4) & 0x1) 2152 hpd.hpd = RADEON_HPD_2; 2153 else 2154 hpd.hpd = RADEON_HPD_1; 2155 break; 2156 default: 2157 hpd.hpd = RADEON_HPD_NONE; 2158 break; 2159 } 2160 2161 if (!radeon_apply_legacy_quirks(dev, i, &connector, 2162 &ddc_i2c, &hpd)) 2163 continue; 2164 2165 switch (connector) { 2166 case CONNECTOR_PROPRIETARY_LEGACY: 2167 if ((tmp >> 4) & 0x1) 2168 devices = ATOM_DEVICE_DFP2_SUPPORT; 2169 else 2170 devices = ATOM_DEVICE_DFP1_SUPPORT; 2171 radeon_add_legacy_encoder(dev, 2172 radeon_get_encoder_enum 2173 (dev, devices, 0), 2174 devices); 2175 radeon_add_legacy_connector(dev, i, devices, 2176 legacy_connector_convert 2177 [connector], 2178 &ddc_i2c, 2179 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 2180 &hpd); 2181 break; 2182 case CONNECTOR_CRT_LEGACY: 2183 if (tmp & 0x1) { 2184 devices = ATOM_DEVICE_CRT2_SUPPORT; 2185 radeon_add_legacy_encoder(dev, 2186 radeon_get_encoder_enum 2187 (dev, 2188 ATOM_DEVICE_CRT2_SUPPORT, 2189 2), 2190 ATOM_DEVICE_CRT2_SUPPORT); 2191 } else { 2192 devices = ATOM_DEVICE_CRT1_SUPPORT; 2193 radeon_add_legacy_encoder(dev, 2194 radeon_get_encoder_enum 2195 (dev, 2196 ATOM_DEVICE_CRT1_SUPPORT, 2197 1), 2198 ATOM_DEVICE_CRT1_SUPPORT); 2199 } 2200 radeon_add_legacy_connector(dev, 2201 i, 2202 devices, 2203 legacy_connector_convert 2204 [connector], 2205 &ddc_i2c, 2206 CONNECTOR_OBJECT_ID_VGA, 2207 &hpd); 2208 break; 2209 case CONNECTOR_DVI_I_LEGACY: 2210 devices = 0; 2211 if (tmp & 0x1) { 2212 devices |= ATOM_DEVICE_CRT2_SUPPORT; 2213 radeon_add_legacy_encoder(dev, 2214 radeon_get_encoder_enum 2215 (dev, 2216 ATOM_DEVICE_CRT2_SUPPORT, 2217 2), 2218 ATOM_DEVICE_CRT2_SUPPORT); 2219 } else { 2220 devices |= ATOM_DEVICE_CRT1_SUPPORT; 2221 radeon_add_legacy_encoder(dev, 2222 radeon_get_encoder_enum 2223 (dev, 2224 ATOM_DEVICE_CRT1_SUPPORT, 2225 1), 2226 ATOM_DEVICE_CRT1_SUPPORT); 2227 } 2228 if ((tmp >> 4) & 0x1) { 2229 devices |= ATOM_DEVICE_DFP2_SUPPORT; 2230 radeon_add_legacy_encoder(dev, 2231 radeon_get_encoder_enum 2232 (dev, 2233 ATOM_DEVICE_DFP2_SUPPORT, 2234 0), 2235 ATOM_DEVICE_DFP2_SUPPORT); 2236 connector_object_id = combios_check_dl_dvi(dev, 0); 2237 } else { 2238 devices |= ATOM_DEVICE_DFP1_SUPPORT; 2239 radeon_add_legacy_encoder(dev, 2240 radeon_get_encoder_enum 2241 (dev, 2242 ATOM_DEVICE_DFP1_SUPPORT, 2243 0), 2244 ATOM_DEVICE_DFP1_SUPPORT); 2245 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2246 } 2247 radeon_add_legacy_connector(dev, 2248 i, 2249 devices, 2250 legacy_connector_convert 2251 [connector], 2252 &ddc_i2c, 2253 connector_object_id, 2254 &hpd); 2255 break; 2256 case CONNECTOR_DVI_D_LEGACY: 2257 if ((tmp >> 4) & 0x1) { 2258 devices = ATOM_DEVICE_DFP2_SUPPORT; 2259 connector_object_id = combios_check_dl_dvi(dev, 1); 2260 } else { 2261 devices = ATOM_DEVICE_DFP1_SUPPORT; 2262 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2263 } 2264 radeon_add_legacy_encoder(dev, 2265 radeon_get_encoder_enum 2266 (dev, devices, 0), 2267 devices); 2268 radeon_add_legacy_connector(dev, i, devices, 2269 legacy_connector_convert 2270 [connector], 2271 &ddc_i2c, 2272 connector_object_id, 2273 &hpd); 2274 break; 2275 case CONNECTOR_CTV_LEGACY: 2276 case CONNECTOR_STV_LEGACY: 2277 radeon_add_legacy_encoder(dev, 2278 radeon_get_encoder_enum 2279 (dev, 2280 ATOM_DEVICE_TV1_SUPPORT, 2281 2), 2282 ATOM_DEVICE_TV1_SUPPORT); 2283 radeon_add_legacy_connector(dev, i, 2284 ATOM_DEVICE_TV1_SUPPORT, 2285 legacy_connector_convert 2286 [connector], 2287 &ddc_i2c, 2288 CONNECTOR_OBJECT_ID_SVIDEO, 2289 &hpd); 2290 break; 2291 default: 2292 DRM_ERROR("Unknown connector type: %d\n", 2293 connector); 2294 continue; 2295 } 2296 2297 } 2298 } else { 2299 uint16_t tmds_info = 2300 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 2301 if (tmds_info) { 2302 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n"); 2303 2304 radeon_add_legacy_encoder(dev, 2305 radeon_get_encoder_enum(dev, 2306 ATOM_DEVICE_CRT1_SUPPORT, 2307 1), 2308 ATOM_DEVICE_CRT1_SUPPORT); 2309 radeon_add_legacy_encoder(dev, 2310 radeon_get_encoder_enum(dev, 2311 ATOM_DEVICE_DFP1_SUPPORT, 2312 0), 2313 ATOM_DEVICE_DFP1_SUPPORT); 2314 2315 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2316 hpd.hpd = RADEON_HPD_1; 2317 radeon_add_legacy_connector(dev, 2318 0, 2319 ATOM_DEVICE_CRT1_SUPPORT | 2320 ATOM_DEVICE_DFP1_SUPPORT, 2321 DRM_MODE_CONNECTOR_DVII, 2322 &ddc_i2c, 2323 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2324 &hpd); 2325 } else { 2326 uint16_t crt_info = 2327 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 2328 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n"); 2329 if (crt_info) { 2330 radeon_add_legacy_encoder(dev, 2331 radeon_get_encoder_enum(dev, 2332 ATOM_DEVICE_CRT1_SUPPORT, 2333 1), 2334 ATOM_DEVICE_CRT1_SUPPORT); 2335 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2336 hpd.hpd = RADEON_HPD_NONE; 2337 radeon_add_legacy_connector(dev, 2338 0, 2339 ATOM_DEVICE_CRT1_SUPPORT, 2340 DRM_MODE_CONNECTOR_VGA, 2341 &ddc_i2c, 2342 CONNECTOR_OBJECT_ID_VGA, 2343 &hpd); 2344 } else { 2345 DRM_DEBUG_KMS("No connector info found\n"); 2346 return false; 2347 } 2348 } 2349 } 2350 2351 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) { 2352 uint16_t lcd_info = 2353 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 2354 if (lcd_info) { 2355 uint16_t lcd_ddc_info = 2356 combios_get_table_offset(dev, 2357 COMBIOS_LCD_DDC_INFO_TABLE); 2358 2359 radeon_add_legacy_encoder(dev, 2360 radeon_get_encoder_enum(dev, 2361 ATOM_DEVICE_LCD1_SUPPORT, 2362 0), 2363 ATOM_DEVICE_LCD1_SUPPORT); 2364 2365 if (lcd_ddc_info) { 2366 ddc_type = RBIOS8(lcd_ddc_info + 2); 2367 switch (ddc_type) { 2368 case DDC_LCD: 2369 ddc_i2c = 2370 combios_setup_i2c_bus(rdev, 2371 DDC_LCD, 2372 RBIOS32(lcd_ddc_info + 3), 2373 RBIOS32(lcd_ddc_info + 7)); 2374 radeon_i2c_add(rdev, &ddc_i2c, "LCD"); 2375 break; 2376 case DDC_GPIO: 2377 ddc_i2c = 2378 combios_setup_i2c_bus(rdev, 2379 DDC_GPIO, 2380 RBIOS32(lcd_ddc_info + 3), 2381 RBIOS32(lcd_ddc_info + 7)); 2382 radeon_i2c_add(rdev, &ddc_i2c, "LCD"); 2383 break; 2384 default: 2385 ddc_i2c = 2386 combios_setup_i2c_bus(rdev, ddc_type, 0, 0); 2387 break; 2388 } 2389 DRM_DEBUG_KMS("LCD DDC Info Table found!\n"); 2390 } else 2391 ddc_i2c.valid = false; 2392 2393 hpd.hpd = RADEON_HPD_NONE; 2394 radeon_add_legacy_connector(dev, 2395 5, 2396 ATOM_DEVICE_LCD1_SUPPORT, 2397 DRM_MODE_CONNECTOR_LVDS, 2398 &ddc_i2c, 2399 CONNECTOR_OBJECT_ID_LVDS, 2400 &hpd); 2401 } 2402 } 2403 2404 /* check TV table */ 2405 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 2406 uint32_t tv_info = 2407 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 2408 if (tv_info) { 2409 if (RBIOS8(tv_info + 6) == 'T') { 2410 if (radeon_apply_legacy_tv_quirks(dev)) { 2411 hpd.hpd = RADEON_HPD_NONE; 2412 ddc_i2c.valid = false; 2413 radeon_add_legacy_encoder(dev, 2414 radeon_get_encoder_enum 2415 (dev, 2416 ATOM_DEVICE_TV1_SUPPORT, 2417 2), 2418 ATOM_DEVICE_TV1_SUPPORT); 2419 radeon_add_legacy_connector(dev, 6, 2420 ATOM_DEVICE_TV1_SUPPORT, 2421 DRM_MODE_CONNECTOR_SVIDEO, 2422 &ddc_i2c, 2423 CONNECTOR_OBJECT_ID_SVIDEO, 2424 &hpd); 2425 } 2426 } 2427 } 2428 } 2429 2430 radeon_link_encoder_connector(dev); 2431 2432 return true; 2433} 2434 2435void radeon_combios_get_power_modes(struct radeon_device *rdev) 2436{ 2437 struct drm_device *dev = rdev->ddev; 2438 u16 offset, misc, misc2 = 0; 2439 u8 rev, blocks, tmp; 2440 int state_index = 0; 2441 2442 rdev->pm.default_power_state_index = -1; 2443 2444 if (rdev->flags & RADEON_IS_MOBILITY) { 2445 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE); 2446 if (offset) { 2447 rev = RBIOS8(offset); 2448 blocks = RBIOS8(offset + 0x2); 2449 /* power mode 0 tends to be the only valid one */ 2450 rdev->pm.power_state[state_index].num_clock_modes = 1; 2451 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2); 2452 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6); 2453 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2454 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2455 goto default_mode; 2456 rdev->pm.power_state[state_index].type = 2457 POWER_STATE_TYPE_BATTERY; 2458 misc = RBIOS16(offset + 0x5 + 0x0); 2459 if (rev > 4) 2460 misc2 = RBIOS16(offset + 0x5 + 0xe); 2461 rdev->pm.power_state[state_index].misc = misc; 2462 rdev->pm.power_state[state_index].misc2 = misc2; 2463 if (misc & 0x4) { 2464 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO; 2465 if (misc & 0x8) 2466 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2467 true; 2468 else 2469 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2470 false; 2471 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true; 2472 if (rev < 6) { 2473 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = 2474 RBIOS16(offset + 0x5 + 0xb) * 4; 2475 tmp = RBIOS8(offset + 0x5 + 0xd); 2476 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); 2477 } else { 2478 u8 entries = RBIOS8(offset + 0x5 + 0xb); 2479 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc); 2480 if (entries && voltage_table_offset) { 2481 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = 2482 RBIOS16(voltage_table_offset) * 4; 2483 tmp = RBIOS8(voltage_table_offset + 0x2); 2484 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); 2485 } else 2486 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false; 2487 } 2488 switch ((misc2 & 0x700) >> 8) { 2489 case 0: 2490 default: 2491 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0; 2492 break; 2493 case 1: 2494 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33; 2495 break; 2496 case 2: 2497 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66; 2498 break; 2499 case 3: 2500 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99; 2501 break; 2502 case 4: 2503 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132; 2504 break; 2505 } 2506 } else 2507 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2508 if (rev > 6) 2509 rdev->pm.power_state[state_index].pcie_lanes = 2510 RBIOS8(offset + 0x5 + 0x10); 2511 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2512 state_index++; 2513 } else { 2514 /* XXX figure out some good default low power mode for mobility cards w/out power tables */ 2515 } 2516 } else { 2517 /* XXX figure out some good default low power mode for desktop cards */ 2518 } 2519 2520default_mode: 2521 /* add the default mode */ 2522 rdev->pm.power_state[state_index].type = 2523 POWER_STATE_TYPE_DEFAULT; 2524 rdev->pm.power_state[state_index].num_clock_modes = 1; 2525 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; 2526 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; 2527 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; 2528 if ((state_index > 0) && 2529 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO)) 2530 rdev->pm.power_state[state_index].clock_info[0].voltage = 2531 rdev->pm.power_state[0].clock_info[0].voltage; 2532 else 2533 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2534 rdev->pm.power_state[state_index].pcie_lanes = 16; 2535 rdev->pm.power_state[state_index].flags = 0; 2536 rdev->pm.default_power_state_index = state_index; 2537 rdev->pm.num_power_states = state_index + 1; 2538 2539 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2540 rdev->pm.current_clock_mode_index = 0; 2541} 2542 2543void radeon_external_tmds_setup(struct drm_encoder *encoder) 2544{ 2545 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2546 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2547 2548 if (!tmds) 2549 return; 2550 2551 switch (tmds->dvo_chip) { 2552 case DVO_SIL164: 2553 /* sil 164 */ 2554 radeon_i2c_put_byte(tmds->i2c_bus, 2555 tmds->slave_addr, 2556 0x08, 0x30); 2557 radeon_i2c_put_byte(tmds->i2c_bus, 2558 tmds->slave_addr, 2559 0x09, 0x00); 2560 radeon_i2c_put_byte(tmds->i2c_bus, 2561 tmds->slave_addr, 2562 0x0a, 0x90); 2563 radeon_i2c_put_byte(tmds->i2c_bus, 2564 tmds->slave_addr, 2565 0x0c, 0x89); 2566 radeon_i2c_put_byte(tmds->i2c_bus, 2567 tmds->slave_addr, 2568 0x08, 0x3b); 2569 break; 2570 case DVO_SIL1178: 2571 /* sil 1178 - untested */ 2572 /* 2573 * 0x0f, 0x44 2574 * 0x0f, 0x4c 2575 * 0x0e, 0x01 2576 * 0x0a, 0x80 2577 * 0x09, 0x30 2578 * 0x0c, 0xc9 2579 * 0x0d, 0x70 2580 * 0x08, 0x32 2581 * 0x08, 0x33 2582 */ 2583 break; 2584 default: 2585 break; 2586 } 2587 2588} 2589 2590bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder) 2591{ 2592 struct drm_device *dev = encoder->dev; 2593 struct radeon_device *rdev = dev->dev_private; 2594 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2595 uint16_t offset; 2596 uint8_t blocks, slave_addr, rev; 2597 uint32_t index, id; 2598 uint32_t reg, val, and_mask, or_mask; 2599 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2600 2601 if (!tmds) 2602 return false; 2603 2604 if (rdev->flags & RADEON_IS_IGP) { 2605 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE); 2606 rev = RBIOS8(offset); 2607 if (offset) { 2608 rev = RBIOS8(offset); 2609 if (rev > 1) { 2610 blocks = RBIOS8(offset + 3); 2611 index = offset + 4; 2612 while (blocks > 0) { 2613 id = RBIOS16(index); 2614 index += 2; 2615 switch (id >> 13) { 2616 case 0: 2617 reg = (id & 0x1fff) * 4; 2618 val = RBIOS32(index); 2619 index += 4; 2620 WREG32(reg, val); 2621 break; 2622 case 2: 2623 reg = (id & 0x1fff) * 4; 2624 and_mask = RBIOS32(index); 2625 index += 4; 2626 or_mask = RBIOS32(index); 2627 index += 4; 2628 val = RREG32(reg); 2629 val = (val & and_mask) | or_mask; 2630 WREG32(reg, val); 2631 break; 2632 case 3: 2633 val = RBIOS16(index); 2634 index += 2; 2635 udelay(val); 2636 break; 2637 case 4: 2638 val = RBIOS16(index); 2639 index += 2; 2640 udelay(val * 1000); 2641 break; 2642 case 6: 2643 slave_addr = id & 0xff; 2644 slave_addr >>= 1; /* 7 bit addressing */ 2645 index++; 2646 reg = RBIOS8(index); 2647 index++; 2648 val = RBIOS8(index); 2649 index++; 2650 radeon_i2c_put_byte(tmds->i2c_bus, 2651 slave_addr, 2652 reg, val); 2653 break; 2654 default: 2655 DRM_ERROR("Unknown id %d\n", id >> 13); 2656 break; 2657 } 2658 blocks--; 2659 } 2660 return true; 2661 } 2662 } 2663 } else { 2664 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 2665 if (offset) { 2666 index = offset + 10; 2667 id = RBIOS16(index); 2668 while (id != 0xffff) { 2669 index += 2; 2670 switch (id >> 13) { 2671 case 0: 2672 reg = (id & 0x1fff) * 4; 2673 val = RBIOS32(index); 2674 WREG32(reg, val); 2675 break; 2676 case 2: 2677 reg = (id & 0x1fff) * 4; 2678 and_mask = RBIOS32(index); 2679 index += 4; 2680 or_mask = RBIOS32(index); 2681 index += 4; 2682 val = RREG32(reg); 2683 val = (val & and_mask) | or_mask; 2684 WREG32(reg, val); 2685 break; 2686 case 4: 2687 val = RBIOS16(index); 2688 index += 2; 2689 udelay(val); 2690 break; 2691 case 5: 2692 reg = id & 0x1fff; 2693 and_mask = RBIOS32(index); 2694 index += 4; 2695 or_mask = RBIOS32(index); 2696 index += 4; 2697 val = RREG32_PLL(reg); 2698 val = (val & and_mask) | or_mask; 2699 WREG32_PLL(reg, val); 2700 break; 2701 case 6: 2702 reg = id & 0x1fff; 2703 val = RBIOS8(index); 2704 index += 1; 2705 radeon_i2c_put_byte(tmds->i2c_bus, 2706 tmds->slave_addr, 2707 reg, val); 2708 break; 2709 default: 2710 DRM_ERROR("Unknown id %d\n", id >> 13); 2711 break; 2712 } 2713 id = RBIOS16(index); 2714 } 2715 return true; 2716 } 2717 } 2718 return false; 2719} 2720 2721static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset) 2722{ 2723 struct radeon_device *rdev = dev->dev_private; 2724 2725 if (offset) { 2726 while (RBIOS16(offset)) { 2727 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13); 2728 uint32_t addr = (RBIOS16(offset) & 0x1fff); 2729 uint32_t val, and_mask, or_mask; 2730 uint32_t tmp; 2731 2732 offset += 2; 2733 switch (cmd) { 2734 case 0: 2735 val = RBIOS32(offset); 2736 offset += 4; 2737 WREG32(addr, val); 2738 break; 2739 case 1: 2740 val = RBIOS32(offset); 2741 offset += 4; 2742 WREG32(addr, val); 2743 break; 2744 case 2: 2745 and_mask = RBIOS32(offset); 2746 offset += 4; 2747 or_mask = RBIOS32(offset); 2748 offset += 4; 2749 tmp = RREG32(addr); 2750 tmp &= and_mask; 2751 tmp |= or_mask; 2752 WREG32(addr, tmp); 2753 break; 2754 case 3: 2755 and_mask = RBIOS32(offset); 2756 offset += 4; 2757 or_mask = RBIOS32(offset); 2758 offset += 4; 2759 tmp = RREG32(addr); 2760 tmp &= and_mask; 2761 tmp |= or_mask; 2762 WREG32(addr, tmp); 2763 break; 2764 case 4: 2765 val = RBIOS16(offset); 2766 offset += 2; 2767 udelay(val); 2768 break; 2769 case 5: 2770 val = RBIOS16(offset); 2771 offset += 2; 2772 switch (addr) { 2773 case 8: 2774 while (val--) { 2775 if (! 2776 (RREG32_PLL 2777 (RADEON_CLK_PWRMGT_CNTL) & 2778 RADEON_MC_BUSY)) 2779 break; 2780 } 2781 break; 2782 case 9: 2783 while (val--) { 2784 if ((RREG32(RADEON_MC_STATUS) & 2785 RADEON_MC_IDLE)) 2786 break; 2787 } 2788 break; 2789 default: 2790 break; 2791 } 2792 break; 2793 default: 2794 break; 2795 } 2796 } 2797 } 2798} 2799 2800static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset) 2801{ 2802 struct radeon_device *rdev = dev->dev_private; 2803 2804 if (offset) { 2805 while (RBIOS8(offset)) { 2806 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6); 2807 uint8_t addr = (RBIOS8(offset) & 0x3f); 2808 uint32_t val, shift, tmp; 2809 uint32_t and_mask, or_mask; 2810 2811 offset++; 2812 switch (cmd) { 2813 case 0: 2814 val = RBIOS32(offset); 2815 offset += 4; 2816 WREG32_PLL(addr, val); 2817 break; 2818 case 1: 2819 shift = RBIOS8(offset) * 8; 2820 offset++; 2821 and_mask = RBIOS8(offset) << shift; 2822 and_mask |= ~(0xff << shift); 2823 offset++; 2824 or_mask = RBIOS8(offset) << shift; 2825 offset++; 2826 tmp = RREG32_PLL(addr); 2827 tmp &= and_mask; 2828 tmp |= or_mask; 2829 WREG32_PLL(addr, tmp); 2830 break; 2831 case 2: 2832 case 3: 2833 tmp = 1000; 2834 switch (addr) { 2835 case 1: 2836 udelay(150); 2837 break; 2838 case 2: 2839 udelay(1000); 2840 break; 2841 case 3: 2842 while (tmp--) { 2843 if (! 2844 (RREG32_PLL 2845 (RADEON_CLK_PWRMGT_CNTL) & 2846 RADEON_MC_BUSY)) 2847 break; 2848 } 2849 break; 2850 case 4: 2851 while (tmp--) { 2852 if (RREG32_PLL 2853 (RADEON_CLK_PWRMGT_CNTL) & 2854 RADEON_DLL_READY) 2855 break; 2856 } 2857 break; 2858 case 5: 2859 tmp = 2860 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); 2861 if (tmp & RADEON_CG_NO1_DEBUG_0) { 2862#if 0 2863 uint32_t mclk_cntl = 2864 RREG32_PLL 2865 (RADEON_MCLK_CNTL); 2866 mclk_cntl &= 0xffff0000; 2867 /*mclk_cntl |= 0x00001111;*//* ??? */ 2868 WREG32_PLL(RADEON_MCLK_CNTL, 2869 mclk_cntl); 2870 udelay(10000); 2871#endif 2872 WREG32_PLL 2873 (RADEON_CLK_PWRMGT_CNTL, 2874 tmp & 2875 ~RADEON_CG_NO1_DEBUG_0); 2876 udelay(10000); 2877 } 2878 break; 2879 default: 2880 break; 2881 } 2882 break; 2883 default: 2884 break; 2885 } 2886 } 2887 } 2888} 2889 2890static void combios_parse_ram_reset_table(struct drm_device *dev, 2891 uint16_t offset) 2892{ 2893 struct radeon_device *rdev = dev->dev_private; 2894 uint32_t tmp; 2895 2896 if (offset) { 2897 uint8_t val = RBIOS8(offset); 2898 while (val != 0xff) { 2899 offset++; 2900 2901 if (val == 0x0f) { 2902 uint32_t channel_complete_mask; 2903 2904 if (ASIC_IS_R300(rdev)) 2905 channel_complete_mask = 2906 R300_MEM_PWRUP_COMPLETE; 2907 else 2908 channel_complete_mask = 2909 RADEON_MEM_PWRUP_COMPLETE; 2910 tmp = 20000; 2911 while (tmp--) { 2912 if ((RREG32(RADEON_MEM_STR_CNTL) & 2913 channel_complete_mask) == 2914 channel_complete_mask) 2915 break; 2916 } 2917 } else { 2918 uint32_t or_mask = RBIOS16(offset); 2919 offset += 2; 2920 2921 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 2922 tmp &= RADEON_SDRAM_MODE_MASK; 2923 tmp |= or_mask; 2924 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 2925 2926 or_mask = val << 24; 2927 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 2928 tmp &= RADEON_B3MEM_RESET_MASK; 2929 tmp |= or_mask; 2930 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 2931 } 2932 val = RBIOS8(offset); 2933 } 2934 } 2935} 2936 2937static uint32_t combios_detect_ram(struct drm_device *dev, int ram, 2938 int mem_addr_mapping) 2939{ 2940 struct radeon_device *rdev = dev->dev_private; 2941 uint32_t mem_cntl; 2942 uint32_t mem_size; 2943 uint32_t addr = 0; 2944 2945 mem_cntl = RREG32(RADEON_MEM_CNTL); 2946 if (mem_cntl & RV100_HALF_MODE) 2947 ram /= 2; 2948 mem_size = ram; 2949 mem_cntl &= ~(0xff << 8); 2950 mem_cntl |= (mem_addr_mapping & 0xff) << 8; 2951 WREG32(RADEON_MEM_CNTL, mem_cntl); 2952 RREG32(RADEON_MEM_CNTL); 2953 2954 /* sdram reset ? */ 2955 2956 /* something like this???? */ 2957 while (ram--) { 2958 addr = ram * 1024 * 1024; 2959 /* write to each page */ 2960 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER); 2961 WREG32(RADEON_MM_DATA, 0xdeadbeef); 2962 /* read back and verify */ 2963 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER); 2964 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef) 2965 return 0; 2966 } 2967 2968 return mem_size; 2969} 2970 2971static void combios_write_ram_size(struct drm_device *dev) 2972{ 2973 struct radeon_device *rdev = dev->dev_private; 2974 uint8_t rev; 2975 uint16_t offset; 2976 uint32_t mem_size = 0; 2977 uint32_t mem_cntl = 0; 2978 2979 /* should do something smarter here I guess... */ 2980 if (rdev->flags & RADEON_IS_IGP) 2981 return; 2982 2983 /* first check detected mem table */ 2984 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE); 2985 if (offset) { 2986 rev = RBIOS8(offset); 2987 if (rev < 3) { 2988 mem_cntl = RBIOS32(offset + 1); 2989 mem_size = RBIOS16(offset + 5); 2990 if ((rdev->family < CHIP_R200) && 2991 !ASIC_IS_RN50(rdev)) 2992 WREG32(RADEON_MEM_CNTL, mem_cntl); 2993 } 2994 } 2995 2996 if (!mem_size) { 2997 offset = 2998 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 2999 if (offset) { 3000 rev = RBIOS8(offset - 1); 3001 if (rev < 1) { 3002 if ((rdev->family < CHIP_R200) 3003 && !ASIC_IS_RN50(rdev)) { 3004 int ram = 0; 3005 int mem_addr_mapping = 0; 3006 3007 while (RBIOS8(offset)) { 3008 ram = RBIOS8(offset); 3009 mem_addr_mapping = 3010 RBIOS8(offset + 1); 3011 if (mem_addr_mapping != 0x25) 3012 ram *= 2; 3013 mem_size = 3014 combios_detect_ram(dev, ram, 3015 mem_addr_mapping); 3016 if (mem_size) 3017 break; 3018 offset += 2; 3019 } 3020 } else 3021 mem_size = RBIOS8(offset); 3022 } else { 3023 mem_size = RBIOS8(offset); 3024 mem_size *= 2; /* convert to MB */ 3025 } 3026 } 3027 } 3028 3029 mem_size *= (1024 * 1024); /* convert to bytes */ 3030 WREG32(RADEON_CONFIG_MEMSIZE, mem_size); 3031} 3032 3033void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable) 3034{ 3035 uint16_t dyn_clk_info = 3036 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); 3037 3038 if (dyn_clk_info) 3039 combios_parse_pll_table(dev, dyn_clk_info); 3040} 3041 3042void radeon_combios_asic_init(struct drm_device *dev) 3043{ 3044 struct radeon_device *rdev = dev->dev_private; 3045 uint16_t table; 3046 3047 /* port hardcoded mac stuff from radeonfb */ 3048 if (rdev->bios == NULL) 3049 return; 3050 3051 /* ASIC INIT 1 */ 3052 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE); 3053 if (table) 3054 combios_parse_mmio_table(dev, table); 3055 3056 /* PLL INIT */ 3057 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE); 3058 if (table) 3059 combios_parse_pll_table(dev, table); 3060 3061 /* ASIC INIT 2 */ 3062 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE); 3063 if (table) 3064 combios_parse_mmio_table(dev, table); 3065 3066 if (!(rdev->flags & RADEON_IS_IGP)) { 3067 /* ASIC INIT 4 */ 3068 table = 3069 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE); 3070 if (table) 3071 combios_parse_mmio_table(dev, table); 3072 3073 /* RAM RESET */ 3074 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE); 3075 if (table) 3076 combios_parse_ram_reset_table(dev, table); 3077 3078 /* ASIC INIT 3 */ 3079 table = 3080 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE); 3081 if (table) 3082 combios_parse_mmio_table(dev, table); 3083 3084 /* write CONFIG_MEMSIZE */ 3085 combios_write_ram_size(dev); 3086 } 3087 3088 /* quirk for rs4xx HP nx6125 laptop to make it resume 3089 * - it hangs on resume inside the dynclk 1 table. 3090 */ 3091 if (rdev->family == CHIP_RS480 && 3092 rdev->pdev->subsystem_vendor == 0x103c && 3093 rdev->pdev->subsystem_device == 0x308b) 3094 return; 3095 3096 /* quirk for rs4xx HP dv5000 laptop to make it resume 3097 * - it hangs on resume inside the dynclk 1 table. 3098 */ 3099 if (rdev->family == CHIP_RS480 && 3100 rdev->pdev->subsystem_vendor == 0x103c && 3101 rdev->pdev->subsystem_device == 0x30a4) 3102 return; 3103 3104 /* DYN CLK 1 */ 3105 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); 3106 if (table) 3107 combios_parse_pll_table(dev, table); 3108 3109} 3110 3111void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev) 3112{ 3113 struct radeon_device *rdev = dev->dev_private; 3114 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch; 3115 3116 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 3117 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3118 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH); 3119 3120 /* let the bios control the backlight */ 3121 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; 3122 3123 /* tell the bios not to handle mode switching */ 3124 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS | 3125 RADEON_ACC_MODE_CHANGE); 3126 3127 /* tell the bios a driver is loaded */ 3128 bios_7_scratch |= RADEON_DRV_LOADED; 3129 3130 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); 3131 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3132 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch); 3133} 3134 3135void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock) 3136{ 3137 struct drm_device *dev = encoder->dev; 3138 struct radeon_device *rdev = dev->dev_private; 3139 uint32_t bios_6_scratch; 3140 3141 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3142 3143 if (lock) 3144 bios_6_scratch |= RADEON_DRIVER_CRITICAL; 3145 else 3146 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL; 3147 3148 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3149} 3150 3151void 3152radeon_combios_connected_scratch_regs(struct drm_connector *connector, 3153 struct drm_encoder *encoder, 3154 bool connected) 3155{ 3156 struct drm_device *dev = connector->dev; 3157 struct radeon_device *rdev = dev->dev_private; 3158 struct radeon_connector *radeon_connector = 3159 to_radeon_connector(connector); 3160 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3161 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH); 3162 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 3163 3164 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 3165 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 3166 if (connected) { 3167 DRM_DEBUG_KMS("TV1 connected\n"); 3168 /* fix me */ 3169 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO; 3170 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */ 3171 bios_5_scratch |= RADEON_TV1_ON; 3172 bios_5_scratch |= RADEON_ACC_REQ_TV1; 3173 } else { 3174 DRM_DEBUG_KMS("TV1 disconnected\n"); 3175 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK; 3176 bios_5_scratch &= ~RADEON_TV1_ON; 3177 bios_5_scratch &= ~RADEON_ACC_REQ_TV1; 3178 } 3179 } 3180 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 3181 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 3182 if (connected) { 3183 DRM_DEBUG_KMS("LCD1 connected\n"); 3184 bios_4_scratch |= RADEON_LCD1_ATTACHED; 3185 bios_5_scratch |= RADEON_LCD1_ON; 3186 bios_5_scratch |= RADEON_ACC_REQ_LCD1; 3187 } else { 3188 DRM_DEBUG_KMS("LCD1 disconnected\n"); 3189 bios_4_scratch &= ~RADEON_LCD1_ATTACHED; 3190 bios_5_scratch &= ~RADEON_LCD1_ON; 3191 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1; 3192 } 3193 } 3194 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 3195 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 3196 if (connected) { 3197 DRM_DEBUG_KMS("CRT1 connected\n"); 3198 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR; 3199 bios_5_scratch |= RADEON_CRT1_ON; 3200 bios_5_scratch |= RADEON_ACC_REQ_CRT1; 3201 } else { 3202 DRM_DEBUG_KMS("CRT1 disconnected\n"); 3203 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK; 3204 bios_5_scratch &= ~RADEON_CRT1_ON; 3205 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1; 3206 } 3207 } 3208 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 3209 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 3210 if (connected) { 3211 DRM_DEBUG_KMS("CRT2 connected\n"); 3212 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR; 3213 bios_5_scratch |= RADEON_CRT2_ON; 3214 bios_5_scratch |= RADEON_ACC_REQ_CRT2; 3215 } else { 3216 DRM_DEBUG_KMS("CRT2 disconnected\n"); 3217 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK; 3218 bios_5_scratch &= ~RADEON_CRT2_ON; 3219 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2; 3220 } 3221 } 3222 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 3223 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 3224 if (connected) { 3225 DRM_DEBUG_KMS("DFP1 connected\n"); 3226 bios_4_scratch |= RADEON_DFP1_ATTACHED; 3227 bios_5_scratch |= RADEON_DFP1_ON; 3228 bios_5_scratch |= RADEON_ACC_REQ_DFP1; 3229 } else { 3230 DRM_DEBUG_KMS("DFP1 disconnected\n"); 3231 bios_4_scratch &= ~RADEON_DFP1_ATTACHED; 3232 bios_5_scratch &= ~RADEON_DFP1_ON; 3233 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1; 3234 } 3235 } 3236 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 3237 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 3238 if (connected) { 3239 DRM_DEBUG_KMS("DFP2 connected\n"); 3240 bios_4_scratch |= RADEON_DFP2_ATTACHED; 3241 bios_5_scratch |= RADEON_DFP2_ON; 3242 bios_5_scratch |= RADEON_ACC_REQ_DFP2; 3243 } else { 3244 DRM_DEBUG_KMS("DFP2 disconnected\n"); 3245 bios_4_scratch &= ~RADEON_DFP2_ATTACHED; 3246 bios_5_scratch &= ~RADEON_DFP2_ON; 3247 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2; 3248 } 3249 } 3250 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch); 3251 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 3252} 3253 3254void 3255radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) 3256{ 3257 struct drm_device *dev = encoder->dev; 3258 struct radeon_device *rdev = dev->dev_private; 3259 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3260 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 3261 3262 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 3263 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK; 3264 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT); 3265 } 3266 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 3267 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK; 3268 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT); 3269 } 3270 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 3271 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK; 3272 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT); 3273 } 3274 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 3275 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK; 3276 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT); 3277 } 3278 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 3279 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK; 3280 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT); 3281 } 3282 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 3283 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK; 3284 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT); 3285 } 3286 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 3287} 3288 3289void 3290radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) 3291{ 3292 struct drm_device *dev = encoder->dev; 3293 struct radeon_device *rdev = dev->dev_private; 3294 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3295 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3296 3297 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 3298 if (on) 3299 bios_6_scratch |= RADEON_TV_DPMS_ON; 3300 else 3301 bios_6_scratch &= ~RADEON_TV_DPMS_ON; 3302 } 3303 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3304 if (on) 3305 bios_6_scratch |= RADEON_CRT_DPMS_ON; 3306 else 3307 bios_6_scratch &= ~RADEON_CRT_DPMS_ON; 3308 } 3309 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3310 if (on) 3311 bios_6_scratch |= RADEON_LCD_DPMS_ON; 3312 else 3313 bios_6_scratch &= ~RADEON_LCD_DPMS_ON; 3314 } 3315 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 3316 if (on) 3317 bios_6_scratch |= RADEON_DFP_DPMS_ON; 3318 else 3319 bios_6_scratch &= ~RADEON_DFP_DPMS_ON; 3320 } 3321 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3322} 3323