radeon_combios.c revision bcc1c2a1d22974215e39dc87ce746ba9a39223e5
1/* 2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario 3 * Copyright 2007-8 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 */ 27#include "drmP.h" 28#include "radeon_drm.h" 29#include "radeon.h" 30#include "atom.h" 31 32#ifdef CONFIG_PPC_PMAC 33/* not sure which of these are needed */ 34#include <asm/machdep.h> 35#include <asm/pmac_feature.h> 36#include <asm/prom.h> 37#include <asm/pci-bridge.h> 38#endif /* CONFIG_PPC_PMAC */ 39 40/* from radeon_encoder.c */ 41extern uint32_t 42radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, 43 uint8_t dac); 44extern void radeon_link_encoder_connector(struct drm_device *dev); 45 46/* from radeon_connector.c */ 47extern void 48radeon_add_legacy_connector(struct drm_device *dev, 49 uint32_t connector_id, 50 uint32_t supported_device, 51 int connector_type, 52 struct radeon_i2c_bus_rec *i2c_bus, 53 uint16_t connector_object_id, 54 struct radeon_hpd *hpd); 55 56/* from radeon_legacy_encoder.c */ 57extern void 58radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, 59 uint32_t supported_device); 60 61/* old legacy ATI BIOS routines */ 62 63/* COMBIOS table offsets */ 64enum radeon_combios_table_offset { 65 /* absolute offset tables */ 66 COMBIOS_ASIC_INIT_1_TABLE, 67 COMBIOS_BIOS_SUPPORT_TABLE, 68 COMBIOS_DAC_PROGRAMMING_TABLE, 69 COMBIOS_MAX_COLOR_DEPTH_TABLE, 70 COMBIOS_CRTC_INFO_TABLE, 71 COMBIOS_PLL_INFO_TABLE, 72 COMBIOS_TV_INFO_TABLE, 73 COMBIOS_DFP_INFO_TABLE, 74 COMBIOS_HW_CONFIG_INFO_TABLE, 75 COMBIOS_MULTIMEDIA_INFO_TABLE, 76 COMBIOS_TV_STD_PATCH_TABLE, 77 COMBIOS_LCD_INFO_TABLE, 78 COMBIOS_MOBILE_INFO_TABLE, 79 COMBIOS_PLL_INIT_TABLE, 80 COMBIOS_MEM_CONFIG_TABLE, 81 COMBIOS_SAVE_MASK_TABLE, 82 COMBIOS_HARDCODED_EDID_TABLE, 83 COMBIOS_ASIC_INIT_2_TABLE, 84 COMBIOS_CONNECTOR_INFO_TABLE, 85 COMBIOS_DYN_CLK_1_TABLE, 86 COMBIOS_RESERVED_MEM_TABLE, 87 COMBIOS_EXT_TMDS_INFO_TABLE, 88 COMBIOS_MEM_CLK_INFO_TABLE, 89 COMBIOS_EXT_DAC_INFO_TABLE, 90 COMBIOS_MISC_INFO_TABLE, 91 COMBIOS_CRT_INFO_TABLE, 92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE, 93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE, 94 COMBIOS_FAN_SPEED_INFO_TABLE, 95 COMBIOS_OVERDRIVE_INFO_TABLE, 96 COMBIOS_OEM_INFO_TABLE, 97 COMBIOS_DYN_CLK_2_TABLE, 98 COMBIOS_POWER_CONNECTOR_INFO_TABLE, 99 COMBIOS_I2C_INFO_TABLE, 100 /* relative offset tables */ 101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */ 102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */ 103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */ 104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */ 105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */ 106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */ 107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */ 108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */ 109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */ 110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */ 111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */ 112}; 113 114enum radeon_combios_ddc { 115 DDC_NONE_DETECTED, 116 DDC_MONID, 117 DDC_DVI, 118 DDC_VGA, 119 DDC_CRT2, 120 DDC_LCD, 121 DDC_GPIO, 122}; 123 124enum radeon_combios_connector { 125 CONNECTOR_NONE_LEGACY, 126 CONNECTOR_PROPRIETARY_LEGACY, 127 CONNECTOR_CRT_LEGACY, 128 CONNECTOR_DVI_I_LEGACY, 129 CONNECTOR_DVI_D_LEGACY, 130 CONNECTOR_CTV_LEGACY, 131 CONNECTOR_STV_LEGACY, 132 CONNECTOR_UNSUPPORTED_LEGACY 133}; 134 135const int legacy_connector_convert[] = { 136 DRM_MODE_CONNECTOR_Unknown, 137 DRM_MODE_CONNECTOR_DVID, 138 DRM_MODE_CONNECTOR_VGA, 139 DRM_MODE_CONNECTOR_DVII, 140 DRM_MODE_CONNECTOR_DVID, 141 DRM_MODE_CONNECTOR_Composite, 142 DRM_MODE_CONNECTOR_SVIDEO, 143 DRM_MODE_CONNECTOR_Unknown, 144}; 145 146static uint16_t combios_get_table_offset(struct drm_device *dev, 147 enum radeon_combios_table_offset table) 148{ 149 struct radeon_device *rdev = dev->dev_private; 150 int rev; 151 uint16_t offset = 0, check_offset; 152 153 switch (table) { 154 /* absolute offset tables */ 155 case COMBIOS_ASIC_INIT_1_TABLE: 156 check_offset = RBIOS16(rdev->bios_header_start + 0xc); 157 if (check_offset) 158 offset = check_offset; 159 break; 160 case COMBIOS_BIOS_SUPPORT_TABLE: 161 check_offset = RBIOS16(rdev->bios_header_start + 0x14); 162 if (check_offset) 163 offset = check_offset; 164 break; 165 case COMBIOS_DAC_PROGRAMMING_TABLE: 166 check_offset = RBIOS16(rdev->bios_header_start + 0x2a); 167 if (check_offset) 168 offset = check_offset; 169 break; 170 case COMBIOS_MAX_COLOR_DEPTH_TABLE: 171 check_offset = RBIOS16(rdev->bios_header_start + 0x2c); 172 if (check_offset) 173 offset = check_offset; 174 break; 175 case COMBIOS_CRTC_INFO_TABLE: 176 check_offset = RBIOS16(rdev->bios_header_start + 0x2e); 177 if (check_offset) 178 offset = check_offset; 179 break; 180 case COMBIOS_PLL_INFO_TABLE: 181 check_offset = RBIOS16(rdev->bios_header_start + 0x30); 182 if (check_offset) 183 offset = check_offset; 184 break; 185 case COMBIOS_TV_INFO_TABLE: 186 check_offset = RBIOS16(rdev->bios_header_start + 0x32); 187 if (check_offset) 188 offset = check_offset; 189 break; 190 case COMBIOS_DFP_INFO_TABLE: 191 check_offset = RBIOS16(rdev->bios_header_start + 0x34); 192 if (check_offset) 193 offset = check_offset; 194 break; 195 case COMBIOS_HW_CONFIG_INFO_TABLE: 196 check_offset = RBIOS16(rdev->bios_header_start + 0x36); 197 if (check_offset) 198 offset = check_offset; 199 break; 200 case COMBIOS_MULTIMEDIA_INFO_TABLE: 201 check_offset = RBIOS16(rdev->bios_header_start + 0x38); 202 if (check_offset) 203 offset = check_offset; 204 break; 205 case COMBIOS_TV_STD_PATCH_TABLE: 206 check_offset = RBIOS16(rdev->bios_header_start + 0x3e); 207 if (check_offset) 208 offset = check_offset; 209 break; 210 case COMBIOS_LCD_INFO_TABLE: 211 check_offset = RBIOS16(rdev->bios_header_start + 0x40); 212 if (check_offset) 213 offset = check_offset; 214 break; 215 case COMBIOS_MOBILE_INFO_TABLE: 216 check_offset = RBIOS16(rdev->bios_header_start + 0x42); 217 if (check_offset) 218 offset = check_offset; 219 break; 220 case COMBIOS_PLL_INIT_TABLE: 221 check_offset = RBIOS16(rdev->bios_header_start + 0x46); 222 if (check_offset) 223 offset = check_offset; 224 break; 225 case COMBIOS_MEM_CONFIG_TABLE: 226 check_offset = RBIOS16(rdev->bios_header_start + 0x48); 227 if (check_offset) 228 offset = check_offset; 229 break; 230 case COMBIOS_SAVE_MASK_TABLE: 231 check_offset = RBIOS16(rdev->bios_header_start + 0x4a); 232 if (check_offset) 233 offset = check_offset; 234 break; 235 case COMBIOS_HARDCODED_EDID_TABLE: 236 check_offset = RBIOS16(rdev->bios_header_start + 0x4c); 237 if (check_offset) 238 offset = check_offset; 239 break; 240 case COMBIOS_ASIC_INIT_2_TABLE: 241 check_offset = RBIOS16(rdev->bios_header_start + 0x4e); 242 if (check_offset) 243 offset = check_offset; 244 break; 245 case COMBIOS_CONNECTOR_INFO_TABLE: 246 check_offset = RBIOS16(rdev->bios_header_start + 0x50); 247 if (check_offset) 248 offset = check_offset; 249 break; 250 case COMBIOS_DYN_CLK_1_TABLE: 251 check_offset = RBIOS16(rdev->bios_header_start + 0x52); 252 if (check_offset) 253 offset = check_offset; 254 break; 255 case COMBIOS_RESERVED_MEM_TABLE: 256 check_offset = RBIOS16(rdev->bios_header_start + 0x54); 257 if (check_offset) 258 offset = check_offset; 259 break; 260 case COMBIOS_EXT_TMDS_INFO_TABLE: 261 check_offset = RBIOS16(rdev->bios_header_start + 0x58); 262 if (check_offset) 263 offset = check_offset; 264 break; 265 case COMBIOS_MEM_CLK_INFO_TABLE: 266 check_offset = RBIOS16(rdev->bios_header_start + 0x5a); 267 if (check_offset) 268 offset = check_offset; 269 break; 270 case COMBIOS_EXT_DAC_INFO_TABLE: 271 check_offset = RBIOS16(rdev->bios_header_start + 0x5c); 272 if (check_offset) 273 offset = check_offset; 274 break; 275 case COMBIOS_MISC_INFO_TABLE: 276 check_offset = RBIOS16(rdev->bios_header_start + 0x5e); 277 if (check_offset) 278 offset = check_offset; 279 break; 280 case COMBIOS_CRT_INFO_TABLE: 281 check_offset = RBIOS16(rdev->bios_header_start + 0x60); 282 if (check_offset) 283 offset = check_offset; 284 break; 285 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE: 286 check_offset = RBIOS16(rdev->bios_header_start + 0x62); 287 if (check_offset) 288 offset = check_offset; 289 break; 290 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE: 291 check_offset = RBIOS16(rdev->bios_header_start + 0x64); 292 if (check_offset) 293 offset = check_offset; 294 break; 295 case COMBIOS_FAN_SPEED_INFO_TABLE: 296 check_offset = RBIOS16(rdev->bios_header_start + 0x66); 297 if (check_offset) 298 offset = check_offset; 299 break; 300 case COMBIOS_OVERDRIVE_INFO_TABLE: 301 check_offset = RBIOS16(rdev->bios_header_start + 0x68); 302 if (check_offset) 303 offset = check_offset; 304 break; 305 case COMBIOS_OEM_INFO_TABLE: 306 check_offset = RBIOS16(rdev->bios_header_start + 0x6a); 307 if (check_offset) 308 offset = check_offset; 309 break; 310 case COMBIOS_DYN_CLK_2_TABLE: 311 check_offset = RBIOS16(rdev->bios_header_start + 0x6c); 312 if (check_offset) 313 offset = check_offset; 314 break; 315 case COMBIOS_POWER_CONNECTOR_INFO_TABLE: 316 check_offset = RBIOS16(rdev->bios_header_start + 0x6e); 317 if (check_offset) 318 offset = check_offset; 319 break; 320 case COMBIOS_I2C_INFO_TABLE: 321 check_offset = RBIOS16(rdev->bios_header_start + 0x70); 322 if (check_offset) 323 offset = check_offset; 324 break; 325 /* relative offset tables */ 326 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */ 327 check_offset = 328 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 329 if (check_offset) { 330 rev = RBIOS8(check_offset); 331 if (rev > 0) { 332 check_offset = RBIOS16(check_offset + 0x3); 333 if (check_offset) 334 offset = check_offset; 335 } 336 } 337 break; 338 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */ 339 check_offset = 340 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 341 if (check_offset) { 342 rev = RBIOS8(check_offset); 343 if (rev > 0) { 344 check_offset = RBIOS16(check_offset + 0x5); 345 if (check_offset) 346 offset = check_offset; 347 } 348 } 349 break; 350 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */ 351 check_offset = 352 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 353 if (check_offset) { 354 rev = RBIOS8(check_offset); 355 if (rev > 0) { 356 check_offset = RBIOS16(check_offset + 0x7); 357 if (check_offset) 358 offset = check_offset; 359 } 360 } 361 break; 362 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */ 363 check_offset = 364 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 365 if (check_offset) { 366 rev = RBIOS8(check_offset); 367 if (rev == 2) { 368 check_offset = RBIOS16(check_offset + 0x9); 369 if (check_offset) 370 offset = check_offset; 371 } 372 } 373 break; 374 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */ 375 check_offset = 376 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 377 if (check_offset) { 378 while (RBIOS8(check_offset++)); 379 check_offset += 2; 380 if (check_offset) 381 offset = check_offset; 382 } 383 break; 384 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */ 385 check_offset = 386 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 387 if (check_offset) { 388 check_offset = RBIOS16(check_offset + 0x11); 389 if (check_offset) 390 offset = check_offset; 391 } 392 break; 393 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */ 394 check_offset = 395 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 396 if (check_offset) { 397 check_offset = RBIOS16(check_offset + 0x13); 398 if (check_offset) 399 offset = check_offset; 400 } 401 break; 402 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */ 403 check_offset = 404 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 405 if (check_offset) { 406 check_offset = RBIOS16(check_offset + 0x15); 407 if (check_offset) 408 offset = check_offset; 409 } 410 break; 411 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */ 412 check_offset = 413 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 414 if (check_offset) { 415 check_offset = RBIOS16(check_offset + 0x17); 416 if (check_offset) 417 offset = check_offset; 418 } 419 break; 420 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */ 421 check_offset = 422 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 423 if (check_offset) { 424 check_offset = RBIOS16(check_offset + 0x2); 425 if (check_offset) 426 offset = check_offset; 427 } 428 break; 429 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */ 430 check_offset = 431 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 432 if (check_offset) { 433 check_offset = RBIOS16(check_offset + 0x4); 434 if (check_offset) 435 offset = check_offset; 436 } 437 break; 438 default: 439 break; 440 } 441 442 return offset; 443 444} 445 446bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev) 447{ 448 int edid_info; 449 struct edid *edid; 450 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE); 451 if (!edid_info) 452 return false; 453 454 edid = kmalloc(EDID_LENGTH * (DRM_MAX_EDID_EXT_NUM + 1), 455 GFP_KERNEL); 456 if (edid == NULL) 457 return false; 458 459 memcpy((unsigned char *)edid, 460 (unsigned char *)(rdev->bios + edid_info), EDID_LENGTH); 461 462 if (!drm_edid_is_valid(edid)) { 463 kfree(edid); 464 return false; 465 } 466 467 rdev->mode_info.bios_hardcoded_edid = edid; 468 return true; 469} 470 471struct edid * 472radeon_combios_get_hardcoded_edid(struct radeon_device *rdev) 473{ 474 if (rdev->mode_info.bios_hardcoded_edid) 475 return rdev->mode_info.bios_hardcoded_edid; 476 return NULL; 477} 478 479static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev, 480 int ddc_line) 481{ 482 struct radeon_i2c_bus_rec i2c; 483 484 if (ddc_line == RADEON_GPIOPAD_MASK) { 485 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; 486 i2c.mask_data_reg = RADEON_GPIOPAD_MASK; 487 i2c.a_clk_reg = RADEON_GPIOPAD_A; 488 i2c.a_data_reg = RADEON_GPIOPAD_A; 489 i2c.en_clk_reg = RADEON_GPIOPAD_EN; 490 i2c.en_data_reg = RADEON_GPIOPAD_EN; 491 i2c.y_clk_reg = RADEON_GPIOPAD_Y; 492 i2c.y_data_reg = RADEON_GPIOPAD_Y; 493 } else if (ddc_line == RADEON_MDGPIO_MASK) { 494 i2c.mask_clk_reg = RADEON_MDGPIO_MASK; 495 i2c.mask_data_reg = RADEON_MDGPIO_MASK; 496 i2c.a_clk_reg = RADEON_MDGPIO_A; 497 i2c.a_data_reg = RADEON_MDGPIO_A; 498 i2c.en_clk_reg = RADEON_MDGPIO_EN; 499 i2c.en_data_reg = RADEON_MDGPIO_EN; 500 i2c.y_clk_reg = RADEON_MDGPIO_Y; 501 i2c.y_data_reg = RADEON_MDGPIO_Y; 502 } else { 503 i2c.mask_clk_mask = RADEON_GPIO_EN_1; 504 i2c.mask_data_mask = RADEON_GPIO_EN_0; 505 i2c.a_clk_mask = RADEON_GPIO_A_1; 506 i2c.a_data_mask = RADEON_GPIO_A_0; 507 i2c.en_clk_mask = RADEON_GPIO_EN_1; 508 i2c.en_data_mask = RADEON_GPIO_EN_0; 509 i2c.y_clk_mask = RADEON_GPIO_Y_1; 510 i2c.y_data_mask = RADEON_GPIO_Y_0; 511 512 i2c.mask_clk_reg = ddc_line; 513 i2c.mask_data_reg = ddc_line; 514 i2c.a_clk_reg = ddc_line; 515 i2c.a_data_reg = ddc_line; 516 i2c.en_clk_reg = ddc_line; 517 i2c.en_data_reg = ddc_line; 518 i2c.y_clk_reg = ddc_line; 519 i2c.y_data_reg = ddc_line; 520 } 521 522 switch (rdev->family) { 523 case CHIP_R100: 524 case CHIP_RV100: 525 case CHIP_RS100: 526 case CHIP_RV200: 527 case CHIP_RS200: 528 case CHIP_RS300: 529 switch (ddc_line) { 530 case RADEON_GPIO_DVI_DDC: 531 /* in theory this should be hw capable, 532 * but it doesn't seem to work 533 */ 534 i2c.hw_capable = false; 535 break; 536 default: 537 i2c.hw_capable = false; 538 break; 539 } 540 break; 541 case CHIP_R200: 542 switch (ddc_line) { 543 case RADEON_GPIO_DVI_DDC: 544 case RADEON_GPIO_MONID: 545 i2c.hw_capable = true; 546 break; 547 default: 548 i2c.hw_capable = false; 549 break; 550 } 551 break; 552 case CHIP_RV250: 553 case CHIP_RV280: 554 switch (ddc_line) { 555 case RADEON_GPIO_VGA_DDC: 556 case RADEON_GPIO_DVI_DDC: 557 case RADEON_GPIO_CRT2_DDC: 558 i2c.hw_capable = true; 559 break; 560 default: 561 i2c.hw_capable = false; 562 break; 563 } 564 break; 565 case CHIP_R300: 566 case CHIP_R350: 567 switch (ddc_line) { 568 case RADEON_GPIO_VGA_DDC: 569 case RADEON_GPIO_DVI_DDC: 570 i2c.hw_capable = true; 571 break; 572 default: 573 i2c.hw_capable = false; 574 break; 575 } 576 break; 577 case CHIP_RV350: 578 case CHIP_RV380: 579 case CHIP_RS400: 580 case CHIP_RS480: 581 switch (ddc_line) { 582 case RADEON_GPIO_VGA_DDC: 583 case RADEON_GPIO_DVI_DDC: 584 i2c.hw_capable = true; 585 break; 586 case RADEON_GPIO_MONID: 587 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work 588 * reliably on some pre-r4xx hardware; not sure why. 589 */ 590 i2c.hw_capable = false; 591 break; 592 default: 593 i2c.hw_capable = false; 594 break; 595 } 596 break; 597 default: 598 i2c.hw_capable = false; 599 break; 600 } 601 i2c.mm_i2c = false; 602 i2c.i2c_id = 0; 603 i2c.hpd_id = 0; 604 605 if (ddc_line) 606 i2c.valid = true; 607 else 608 i2c.valid = false; 609 610 return i2c; 611} 612 613bool radeon_combios_get_clock_info(struct drm_device *dev) 614{ 615 struct radeon_device *rdev = dev->dev_private; 616 uint16_t pll_info; 617 struct radeon_pll *p1pll = &rdev->clock.p1pll; 618 struct radeon_pll *p2pll = &rdev->clock.p2pll; 619 struct radeon_pll *spll = &rdev->clock.spll; 620 struct radeon_pll *mpll = &rdev->clock.mpll; 621 int8_t rev; 622 uint16_t sclk, mclk; 623 624 if (rdev->bios == NULL) 625 return false; 626 627 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE); 628 if (pll_info) { 629 rev = RBIOS8(pll_info); 630 631 /* pixel clocks */ 632 p1pll->reference_freq = RBIOS16(pll_info + 0xe); 633 p1pll->reference_div = RBIOS16(pll_info + 0x10); 634 p1pll->pll_out_min = RBIOS32(pll_info + 0x12); 635 p1pll->pll_out_max = RBIOS32(pll_info + 0x16); 636 637 if (rev > 9) { 638 p1pll->pll_in_min = RBIOS32(pll_info + 0x36); 639 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a); 640 } else { 641 p1pll->pll_in_min = 40; 642 p1pll->pll_in_max = 500; 643 } 644 *p2pll = *p1pll; 645 646 /* system clock */ 647 spll->reference_freq = RBIOS16(pll_info + 0x1a); 648 spll->reference_div = RBIOS16(pll_info + 0x1c); 649 spll->pll_out_min = RBIOS32(pll_info + 0x1e); 650 spll->pll_out_max = RBIOS32(pll_info + 0x22); 651 652 if (rev > 10) { 653 spll->pll_in_min = RBIOS32(pll_info + 0x48); 654 spll->pll_in_max = RBIOS32(pll_info + 0x4c); 655 } else { 656 /* ??? */ 657 spll->pll_in_min = 40; 658 spll->pll_in_max = 500; 659 } 660 661 /* memory clock */ 662 mpll->reference_freq = RBIOS16(pll_info + 0x26); 663 mpll->reference_div = RBIOS16(pll_info + 0x28); 664 mpll->pll_out_min = RBIOS32(pll_info + 0x2a); 665 mpll->pll_out_max = RBIOS32(pll_info + 0x2e); 666 667 if (rev > 10) { 668 mpll->pll_in_min = RBIOS32(pll_info + 0x5a); 669 mpll->pll_in_max = RBIOS32(pll_info + 0x5e); 670 } else { 671 /* ??? */ 672 mpll->pll_in_min = 40; 673 mpll->pll_in_max = 500; 674 } 675 676 /* default sclk/mclk */ 677 sclk = RBIOS16(pll_info + 0xa); 678 mclk = RBIOS16(pll_info + 0x8); 679 if (sclk == 0) 680 sclk = 200 * 100; 681 if (mclk == 0) 682 mclk = 200 * 100; 683 684 rdev->clock.default_sclk = sclk; 685 rdev->clock.default_mclk = mclk; 686 687 return true; 688 } 689 return false; 690} 691 692bool radeon_combios_sideport_present(struct radeon_device *rdev) 693{ 694 struct drm_device *dev = rdev->ddev; 695 u16 igp_info; 696 697 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE); 698 699 if (igp_info) { 700 if (RBIOS16(igp_info + 0x4)) 701 return true; 702 } 703 return false; 704} 705 706static const uint32_t default_primarydac_adj[CHIP_LAST] = { 707 0x00000808, /* r100 */ 708 0x00000808, /* rv100 */ 709 0x00000808, /* rs100 */ 710 0x00000808, /* rv200 */ 711 0x00000808, /* rs200 */ 712 0x00000808, /* r200 */ 713 0x00000808, /* rv250 */ 714 0x00000000, /* rs300 */ 715 0x00000808, /* rv280 */ 716 0x00000808, /* r300 */ 717 0x00000808, /* r350 */ 718 0x00000808, /* rv350 */ 719 0x00000808, /* rv380 */ 720 0x00000808, /* r420 */ 721 0x00000808, /* r423 */ 722 0x00000808, /* rv410 */ 723 0x00000000, /* rs400 */ 724 0x00000000, /* rs480 */ 725}; 726 727static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev, 728 struct radeon_encoder_primary_dac *p_dac) 729{ 730 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family]; 731 return; 732} 733 734struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct 735 radeon_encoder 736 *encoder) 737{ 738 struct drm_device *dev = encoder->base.dev; 739 struct radeon_device *rdev = dev->dev_private; 740 uint16_t dac_info; 741 uint8_t rev, bg, dac; 742 struct radeon_encoder_primary_dac *p_dac = NULL; 743 int found = 0; 744 745 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), 746 GFP_KERNEL); 747 748 if (!p_dac) 749 return NULL; 750 751 if (rdev->bios == NULL) 752 goto out; 753 754 /* check CRT table */ 755 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 756 if (dac_info) { 757 rev = RBIOS8(dac_info) & 0x3; 758 if (rev < 2) { 759 bg = RBIOS8(dac_info + 0x2) & 0xf; 760 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf; 761 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 762 } else { 763 bg = RBIOS8(dac_info + 0x2) & 0xf; 764 dac = RBIOS8(dac_info + 0x3) & 0xf; 765 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 766 } 767 found = 1; 768 } 769 770out: 771 if (!found) /* fallback to defaults */ 772 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac); 773 774 return p_dac; 775} 776 777enum radeon_tv_std 778radeon_combios_get_tv_info(struct radeon_device *rdev) 779{ 780 struct drm_device *dev = rdev->ddev; 781 uint16_t tv_info; 782 enum radeon_tv_std tv_std = TV_STD_NTSC; 783 784 if (rdev->bios == NULL) 785 return tv_std; 786 787 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 788 if (tv_info) { 789 if (RBIOS8(tv_info + 6) == 'T') { 790 switch (RBIOS8(tv_info + 7) & 0xf) { 791 case 1: 792 tv_std = TV_STD_NTSC; 793 DRM_INFO("Default TV standard: NTSC\n"); 794 break; 795 case 2: 796 tv_std = TV_STD_PAL; 797 DRM_INFO("Default TV standard: PAL\n"); 798 break; 799 case 3: 800 tv_std = TV_STD_PAL_M; 801 DRM_INFO("Default TV standard: PAL-M\n"); 802 break; 803 case 4: 804 tv_std = TV_STD_PAL_60; 805 DRM_INFO("Default TV standard: PAL-60\n"); 806 break; 807 case 5: 808 tv_std = TV_STD_NTSC_J; 809 DRM_INFO("Default TV standard: NTSC-J\n"); 810 break; 811 case 6: 812 tv_std = TV_STD_SCART_PAL; 813 DRM_INFO("Default TV standard: SCART-PAL\n"); 814 break; 815 default: 816 tv_std = TV_STD_NTSC; 817 DRM_INFO 818 ("Unknown TV standard; defaulting to NTSC\n"); 819 break; 820 } 821 822 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) { 823 case 0: 824 DRM_INFO("29.498928713 MHz TV ref clk\n"); 825 break; 826 case 1: 827 DRM_INFO("28.636360000 MHz TV ref clk\n"); 828 break; 829 case 2: 830 DRM_INFO("14.318180000 MHz TV ref clk\n"); 831 break; 832 case 3: 833 DRM_INFO("27.000000000 MHz TV ref clk\n"); 834 break; 835 default: 836 break; 837 } 838 } 839 } 840 return tv_std; 841} 842 843static const uint32_t default_tvdac_adj[CHIP_LAST] = { 844 0x00000000, /* r100 */ 845 0x00280000, /* rv100 */ 846 0x00000000, /* rs100 */ 847 0x00880000, /* rv200 */ 848 0x00000000, /* rs200 */ 849 0x00000000, /* r200 */ 850 0x00770000, /* rv250 */ 851 0x00290000, /* rs300 */ 852 0x00560000, /* rv280 */ 853 0x00780000, /* r300 */ 854 0x00770000, /* r350 */ 855 0x00780000, /* rv350 */ 856 0x00780000, /* rv380 */ 857 0x01080000, /* r420 */ 858 0x01080000, /* r423 */ 859 0x01080000, /* rv410 */ 860 0x00780000, /* rs400 */ 861 0x00780000, /* rs480 */ 862}; 863 864static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev, 865 struct radeon_encoder_tv_dac *tv_dac) 866{ 867 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family]; 868 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250)) 869 tv_dac->ps2_tvdac_adj = 0x00880000; 870 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 871 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 872 return; 873} 874 875struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct 876 radeon_encoder 877 *encoder) 878{ 879 struct drm_device *dev = encoder->base.dev; 880 struct radeon_device *rdev = dev->dev_private; 881 uint16_t dac_info; 882 uint8_t rev, bg, dac; 883 struct radeon_encoder_tv_dac *tv_dac = NULL; 884 int found = 0; 885 886 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); 887 if (!tv_dac) 888 return NULL; 889 890 if (rdev->bios == NULL) 891 goto out; 892 893 /* first check TV table */ 894 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 895 if (dac_info) { 896 rev = RBIOS8(dac_info + 0x3); 897 if (rev > 4) { 898 bg = RBIOS8(dac_info + 0xc) & 0xf; 899 dac = RBIOS8(dac_info + 0xd) & 0xf; 900 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 901 902 bg = RBIOS8(dac_info + 0xe) & 0xf; 903 dac = RBIOS8(dac_info + 0xf) & 0xf; 904 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 905 906 bg = RBIOS8(dac_info + 0x10) & 0xf; 907 dac = RBIOS8(dac_info + 0x11) & 0xf; 908 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 909 found = 1; 910 } else if (rev > 1) { 911 bg = RBIOS8(dac_info + 0xc) & 0xf; 912 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf; 913 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 914 915 bg = RBIOS8(dac_info + 0xd) & 0xf; 916 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf; 917 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 918 919 bg = RBIOS8(dac_info + 0xe) & 0xf; 920 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf; 921 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 922 found = 1; 923 } 924 tv_dac->tv_std = radeon_combios_get_tv_info(rdev); 925 } 926 if (!found) { 927 /* then check CRT table */ 928 dac_info = 929 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 930 if (dac_info) { 931 rev = RBIOS8(dac_info) & 0x3; 932 if (rev < 2) { 933 bg = RBIOS8(dac_info + 0x3) & 0xf; 934 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf; 935 tv_dac->ps2_tvdac_adj = 936 (bg << 16) | (dac << 20); 937 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 938 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 939 found = 1; 940 } else { 941 bg = RBIOS8(dac_info + 0x4) & 0xf; 942 dac = RBIOS8(dac_info + 0x5) & 0xf; 943 tv_dac->ps2_tvdac_adj = 944 (bg << 16) | (dac << 20); 945 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 946 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 947 found = 1; 948 } 949 } else { 950 DRM_INFO("No TV DAC info found in BIOS\n"); 951 } 952 } 953 954out: 955 if (!found) /* fallback to defaults */ 956 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac); 957 958 return tv_dac; 959} 960 961static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct 962 radeon_device 963 *rdev) 964{ 965 struct radeon_encoder_lvds *lvds = NULL; 966 uint32_t fp_vert_stretch, fp_horz_stretch; 967 uint32_t ppll_div_sel, ppll_val; 968 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); 969 970 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); 971 972 if (!lvds) 973 return NULL; 974 975 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH); 976 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH); 977 978 /* These should be fail-safe defaults, fingers crossed */ 979 lvds->panel_pwr_delay = 200; 980 lvds->panel_vcc_delay = 2000; 981 982 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 983 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf; 984 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf; 985 986 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) 987 lvds->native_mode.vdisplay = 988 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >> 989 RADEON_VERT_PANEL_SHIFT) + 1; 990 else 991 lvds->native_mode.vdisplay = 992 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1; 993 994 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE) 995 lvds->native_mode.hdisplay = 996 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >> 997 RADEON_HORZ_PANEL_SHIFT) + 1) * 8; 998 else 999 lvds->native_mode.hdisplay = 1000 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8; 1001 1002 if ((lvds->native_mode.hdisplay < 640) || 1003 (lvds->native_mode.vdisplay < 480)) { 1004 lvds->native_mode.hdisplay = 640; 1005 lvds->native_mode.vdisplay = 480; 1006 } 1007 1008 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; 1009 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel); 1010 if ((ppll_val & 0x000707ff) == 0x1bb) 1011 lvds->use_bios_dividers = false; 1012 else { 1013 lvds->panel_ref_divider = 1014 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; 1015 lvds->panel_post_divider = (ppll_val >> 16) & 0x7; 1016 lvds->panel_fb_divider = ppll_val & 0x7ff; 1017 1018 if ((lvds->panel_ref_divider != 0) && 1019 (lvds->panel_fb_divider > 3)) 1020 lvds->use_bios_dividers = true; 1021 } 1022 lvds->panel_vcc_delay = 200; 1023 1024 DRM_INFO("Panel info derived from registers\n"); 1025 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 1026 lvds->native_mode.vdisplay); 1027 1028 return lvds; 1029} 1030 1031struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder 1032 *encoder) 1033{ 1034 struct drm_device *dev = encoder->base.dev; 1035 struct radeon_device *rdev = dev->dev_private; 1036 uint16_t lcd_info; 1037 uint32_t panel_setup; 1038 char stmp[30]; 1039 int tmp, i; 1040 struct radeon_encoder_lvds *lvds = NULL; 1041 1042 if (rdev->bios == NULL) { 1043 lvds = radeon_legacy_get_lvds_info_from_regs(rdev); 1044 goto out; 1045 } 1046 1047 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 1048 1049 if (lcd_info) { 1050 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); 1051 1052 if (!lvds) 1053 return NULL; 1054 1055 for (i = 0; i < 24; i++) 1056 stmp[i] = RBIOS8(lcd_info + i + 1); 1057 stmp[24] = 0; 1058 1059 DRM_INFO("Panel ID String: %s\n", stmp); 1060 1061 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19); 1062 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b); 1063 1064 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 1065 lvds->native_mode.vdisplay); 1066 1067 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c); 1068 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000); 1069 1070 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24); 1071 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf; 1072 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf; 1073 1074 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e); 1075 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30); 1076 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31); 1077 if ((lvds->panel_ref_divider != 0) && 1078 (lvds->panel_fb_divider > 3)) 1079 lvds->use_bios_dividers = true; 1080 1081 panel_setup = RBIOS32(lcd_info + 0x39); 1082 lvds->lvds_gen_cntl = 0xff00; 1083 if (panel_setup & 0x1) 1084 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT; 1085 1086 if ((panel_setup >> 4) & 0x1) 1087 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE; 1088 1089 switch ((panel_setup >> 8) & 0x7) { 1090 case 0: 1091 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM; 1092 break; 1093 case 1: 1094 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY; 1095 break; 1096 case 2: 1097 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY; 1098 break; 1099 default: 1100 break; 1101 } 1102 1103 if ((panel_setup >> 16) & 0x1) 1104 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW; 1105 1106 if ((panel_setup >> 17) & 0x1) 1107 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW; 1108 1109 if ((panel_setup >> 18) & 0x1) 1110 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW; 1111 1112 if ((panel_setup >> 23) & 0x1) 1113 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL; 1114 1115 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000); 1116 1117 for (i = 0; i < 32; i++) { 1118 tmp = RBIOS16(lcd_info + 64 + i * 2); 1119 if (tmp == 0) 1120 break; 1121 1122 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) && 1123 (RBIOS16(tmp + 2) == 1124 lvds->native_mode.vdisplay)) { 1125 lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8; 1126 lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8; 1127 lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) + 1128 RBIOS16(tmp + 21)) * 8; 1129 1130 lvds->native_mode.vtotal = RBIOS16(tmp + 24); 1131 lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff; 1132 lvds->native_mode.vsync_end = 1133 ((RBIOS16(tmp + 28) & 0xf800) >> 11) + 1134 (RBIOS16(tmp + 28) & 0x7ff); 1135 1136 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10; 1137 lvds->native_mode.flags = 0; 1138 /* set crtc values */ 1139 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); 1140 1141 } 1142 } 1143 } else { 1144 DRM_INFO("No panel info found in BIOS\n"); 1145 lvds = radeon_legacy_get_lvds_info_from_regs(rdev); 1146 } 1147out: 1148 if (lvds) 1149 encoder->native_mode = lvds->native_mode; 1150 return lvds; 1151} 1152 1153static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = { 1154 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */ 1155 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */ 1156 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */ 1157 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */ 1158 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */ 1159 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */ 1160 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */ 1161 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */ 1162 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */ 1163 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */ 1164 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */ 1165 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */ 1166 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */ 1167 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */ 1168 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */ 1169 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */ 1170 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */ 1171 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */ 1172}; 1173 1174bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 1175 struct radeon_encoder_int_tmds *tmds) 1176{ 1177 struct drm_device *dev = encoder->base.dev; 1178 struct radeon_device *rdev = dev->dev_private; 1179 int i; 1180 1181 for (i = 0; i < 4; i++) { 1182 tmds->tmds_pll[i].value = 1183 default_tmds_pll[rdev->family][i].value; 1184 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq; 1185 } 1186 1187 return true; 1188} 1189 1190bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 1191 struct radeon_encoder_int_tmds *tmds) 1192{ 1193 struct drm_device *dev = encoder->base.dev; 1194 struct radeon_device *rdev = dev->dev_private; 1195 uint16_t tmds_info; 1196 int i, n; 1197 uint8_t ver; 1198 1199 if (rdev->bios == NULL) 1200 return false; 1201 1202 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 1203 1204 if (tmds_info) { 1205 ver = RBIOS8(tmds_info); 1206 DRM_INFO("DFP table revision: %d\n", ver); 1207 if (ver == 3) { 1208 n = RBIOS8(tmds_info + 5) + 1; 1209 if (n > 4) 1210 n = 4; 1211 for (i = 0; i < n; i++) { 1212 tmds->tmds_pll[i].value = 1213 RBIOS32(tmds_info + i * 10 + 0x08); 1214 tmds->tmds_pll[i].freq = 1215 RBIOS16(tmds_info + i * 10 + 0x10); 1216 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n", 1217 tmds->tmds_pll[i].freq, 1218 tmds->tmds_pll[i].value); 1219 } 1220 } else if (ver == 4) { 1221 int stride = 0; 1222 n = RBIOS8(tmds_info + 5) + 1; 1223 if (n > 4) 1224 n = 4; 1225 for (i = 0; i < n; i++) { 1226 tmds->tmds_pll[i].value = 1227 RBIOS32(tmds_info + stride + 0x08); 1228 tmds->tmds_pll[i].freq = 1229 RBIOS16(tmds_info + stride + 0x10); 1230 if (i == 0) 1231 stride += 10; 1232 else 1233 stride += 6; 1234 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n", 1235 tmds->tmds_pll[i].freq, 1236 tmds->tmds_pll[i].value); 1237 } 1238 } 1239 } else { 1240 DRM_INFO("No TMDS info found in BIOS\n"); 1241 return false; 1242 } 1243 return true; 1244} 1245 1246bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 1247 struct radeon_encoder_ext_tmds *tmds) 1248{ 1249 struct drm_device *dev = encoder->base.dev; 1250 struct radeon_device *rdev = dev->dev_private; 1251 struct radeon_i2c_bus_rec i2c_bus; 1252 1253 /* default for macs */ 1254 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1255 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1256 1257 /* XXX some macs have duallink chips */ 1258 switch (rdev->mode_info.connector_table) { 1259 case CT_POWERBOOK_EXTERNAL: 1260 case CT_MINI_EXTERNAL: 1261 default: 1262 tmds->dvo_chip = DVO_SIL164; 1263 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1264 break; 1265 } 1266 1267 return true; 1268} 1269 1270bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 1271 struct radeon_encoder_ext_tmds *tmds) 1272{ 1273 struct drm_device *dev = encoder->base.dev; 1274 struct radeon_device *rdev = dev->dev_private; 1275 uint16_t offset; 1276 uint8_t ver, id, blocks, clk, data; 1277 int i; 1278 enum radeon_combios_ddc gpio; 1279 struct radeon_i2c_bus_rec i2c_bus; 1280 1281 if (rdev->bios == NULL) 1282 return false; 1283 1284 tmds->i2c_bus = NULL; 1285 if (rdev->flags & RADEON_IS_IGP) { 1286 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE); 1287 if (offset) { 1288 ver = RBIOS8(offset); 1289 DRM_INFO("GPIO Table revision: %d\n", ver); 1290 blocks = RBIOS8(offset + 2); 1291 for (i = 0; i < blocks; i++) { 1292 id = RBIOS8(offset + 3 + (i * 5) + 0); 1293 if (id == 136) { 1294 clk = RBIOS8(offset + 3 + (i * 5) + 3); 1295 data = RBIOS8(offset + 3 + (i * 5) + 4); 1296 i2c_bus.valid = true; 1297 i2c_bus.mask_clk_mask = (1 << clk); 1298 i2c_bus.mask_data_mask = (1 << data); 1299 i2c_bus.a_clk_mask = (1 << clk); 1300 i2c_bus.a_data_mask = (1 << data); 1301 i2c_bus.en_clk_mask = (1 << clk); 1302 i2c_bus.en_data_mask = (1 << data); 1303 i2c_bus.y_clk_mask = (1 << clk); 1304 i2c_bus.y_data_mask = (1 << data); 1305 i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK; 1306 i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK; 1307 i2c_bus.a_clk_reg = RADEON_GPIOPAD_A; 1308 i2c_bus.a_data_reg = RADEON_GPIOPAD_A; 1309 i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN; 1310 i2c_bus.en_data_reg = RADEON_GPIOPAD_EN; 1311 i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y; 1312 i2c_bus.y_data_reg = RADEON_GPIOPAD_Y; 1313 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1314 tmds->dvo_chip = DVO_SIL164; 1315 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1316 break; 1317 } 1318 } 1319 } 1320 } else { 1321 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 1322 if (offset) { 1323 ver = RBIOS8(offset); 1324 DRM_INFO("External TMDS Table revision: %d\n", ver); 1325 tmds->slave_addr = RBIOS8(offset + 4 + 2); 1326 tmds->slave_addr >>= 1; /* 7 bit addressing */ 1327 gpio = RBIOS8(offset + 4 + 3); 1328 switch (gpio) { 1329 case DDC_MONID: 1330 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1331 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1332 break; 1333 case DDC_DVI: 1334 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1335 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1336 break; 1337 case DDC_VGA: 1338 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1339 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1340 break; 1341 case DDC_CRT2: 1342 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */ 1343 if (rdev->family >= CHIP_R300) 1344 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1345 else 1346 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1347 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1348 break; 1349 case DDC_LCD: /* MM i2c */ 1350 i2c_bus.valid = true; 1351 i2c_bus.hw_capable = true; 1352 i2c_bus.mm_i2c = true; 1353 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1354 break; 1355 default: 1356 DRM_ERROR("Unsupported gpio %d\n", gpio); 1357 break; 1358 } 1359 } 1360 } 1361 1362 if (!tmds->i2c_bus) { 1363 DRM_INFO("No valid Ext TMDS info found in BIOS\n"); 1364 return false; 1365 } 1366 1367 return true; 1368} 1369 1370bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) 1371{ 1372 struct radeon_device *rdev = dev->dev_private; 1373 struct radeon_i2c_bus_rec ddc_i2c; 1374 struct radeon_hpd hpd; 1375 1376 rdev->mode_info.connector_table = radeon_connector_table; 1377 if (rdev->mode_info.connector_table == CT_NONE) { 1378#ifdef CONFIG_PPC_PMAC 1379 if (machine_is_compatible("PowerBook3,3")) { 1380 /* powerbook with VGA */ 1381 rdev->mode_info.connector_table = CT_POWERBOOK_VGA; 1382 } else if (machine_is_compatible("PowerBook3,4") || 1383 machine_is_compatible("PowerBook3,5")) { 1384 /* powerbook with internal tmds */ 1385 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL; 1386 } else if (machine_is_compatible("PowerBook5,1") || 1387 machine_is_compatible("PowerBook5,2") || 1388 machine_is_compatible("PowerBook5,3") || 1389 machine_is_compatible("PowerBook5,4") || 1390 machine_is_compatible("PowerBook5,5")) { 1391 /* powerbook with external single link tmds (sil164) */ 1392 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1393 } else if (machine_is_compatible("PowerBook5,6")) { 1394 /* powerbook with external dual or single link tmds */ 1395 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1396 } else if (machine_is_compatible("PowerBook5,7") || 1397 machine_is_compatible("PowerBook5,8") || 1398 machine_is_compatible("PowerBook5,9")) { 1399 /* PowerBook6,2 ? */ 1400 /* powerbook with external dual link tmds (sil1178?) */ 1401 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1402 } else if (machine_is_compatible("PowerBook4,1") || 1403 machine_is_compatible("PowerBook4,2") || 1404 machine_is_compatible("PowerBook4,3") || 1405 machine_is_compatible("PowerBook6,3") || 1406 machine_is_compatible("PowerBook6,5") || 1407 machine_is_compatible("PowerBook6,7")) { 1408 /* ibook */ 1409 rdev->mode_info.connector_table = CT_IBOOK; 1410 } else if (machine_is_compatible("PowerMac4,4")) { 1411 /* emac */ 1412 rdev->mode_info.connector_table = CT_EMAC; 1413 } else if (machine_is_compatible("PowerMac10,1")) { 1414 /* mini with internal tmds */ 1415 rdev->mode_info.connector_table = CT_MINI_INTERNAL; 1416 } else if (machine_is_compatible("PowerMac10,2")) { 1417 /* mini with external tmds */ 1418 rdev->mode_info.connector_table = CT_MINI_EXTERNAL; 1419 } else if (machine_is_compatible("PowerMac12,1")) { 1420 /* PowerMac8,1 ? */ 1421 /* imac g5 isight */ 1422 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT; 1423 } else 1424#endif /* CONFIG_PPC_PMAC */ 1425 rdev->mode_info.connector_table = CT_GENERIC; 1426 } 1427 1428 switch (rdev->mode_info.connector_table) { 1429 case CT_GENERIC: 1430 DRM_INFO("Connector Table: %d (generic)\n", 1431 rdev->mode_info.connector_table); 1432 /* these are the most common settings */ 1433 if (rdev->flags & RADEON_SINGLE_CRTC) { 1434 /* VGA - primary dac */ 1435 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1436 hpd.hpd = RADEON_HPD_NONE; 1437 radeon_add_legacy_encoder(dev, 1438 radeon_get_encoder_id(dev, 1439 ATOM_DEVICE_CRT1_SUPPORT, 1440 1), 1441 ATOM_DEVICE_CRT1_SUPPORT); 1442 radeon_add_legacy_connector(dev, 0, 1443 ATOM_DEVICE_CRT1_SUPPORT, 1444 DRM_MODE_CONNECTOR_VGA, 1445 &ddc_i2c, 1446 CONNECTOR_OBJECT_ID_VGA, 1447 &hpd); 1448 } else if (rdev->flags & RADEON_IS_MOBILITY) { 1449 /* LVDS */ 1450 ddc_i2c = combios_setup_i2c_bus(rdev, 0); 1451 hpd.hpd = RADEON_HPD_NONE; 1452 radeon_add_legacy_encoder(dev, 1453 radeon_get_encoder_id(dev, 1454 ATOM_DEVICE_LCD1_SUPPORT, 1455 0), 1456 ATOM_DEVICE_LCD1_SUPPORT); 1457 radeon_add_legacy_connector(dev, 0, 1458 ATOM_DEVICE_LCD1_SUPPORT, 1459 DRM_MODE_CONNECTOR_LVDS, 1460 &ddc_i2c, 1461 CONNECTOR_OBJECT_ID_LVDS, 1462 &hpd); 1463 1464 /* VGA - primary dac */ 1465 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1466 hpd.hpd = RADEON_HPD_NONE; 1467 radeon_add_legacy_encoder(dev, 1468 radeon_get_encoder_id(dev, 1469 ATOM_DEVICE_CRT1_SUPPORT, 1470 1), 1471 ATOM_DEVICE_CRT1_SUPPORT); 1472 radeon_add_legacy_connector(dev, 1, 1473 ATOM_DEVICE_CRT1_SUPPORT, 1474 DRM_MODE_CONNECTOR_VGA, 1475 &ddc_i2c, 1476 CONNECTOR_OBJECT_ID_VGA, 1477 &hpd); 1478 } else { 1479 /* DVI-I - tv dac, int tmds */ 1480 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1481 hpd.hpd = RADEON_HPD_1; 1482 radeon_add_legacy_encoder(dev, 1483 radeon_get_encoder_id(dev, 1484 ATOM_DEVICE_DFP1_SUPPORT, 1485 0), 1486 ATOM_DEVICE_DFP1_SUPPORT); 1487 radeon_add_legacy_encoder(dev, 1488 radeon_get_encoder_id(dev, 1489 ATOM_DEVICE_CRT2_SUPPORT, 1490 2), 1491 ATOM_DEVICE_CRT2_SUPPORT); 1492 radeon_add_legacy_connector(dev, 0, 1493 ATOM_DEVICE_DFP1_SUPPORT | 1494 ATOM_DEVICE_CRT2_SUPPORT, 1495 DRM_MODE_CONNECTOR_DVII, 1496 &ddc_i2c, 1497 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1498 &hpd); 1499 1500 /* VGA - primary dac */ 1501 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1502 hpd.hpd = RADEON_HPD_NONE; 1503 radeon_add_legacy_encoder(dev, 1504 radeon_get_encoder_id(dev, 1505 ATOM_DEVICE_CRT1_SUPPORT, 1506 1), 1507 ATOM_DEVICE_CRT1_SUPPORT); 1508 radeon_add_legacy_connector(dev, 1, 1509 ATOM_DEVICE_CRT1_SUPPORT, 1510 DRM_MODE_CONNECTOR_VGA, 1511 &ddc_i2c, 1512 CONNECTOR_OBJECT_ID_VGA, 1513 &hpd); 1514 } 1515 1516 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 1517 /* TV - tv dac */ 1518 ddc_i2c.valid = false; 1519 hpd.hpd = RADEON_HPD_NONE; 1520 radeon_add_legacy_encoder(dev, 1521 radeon_get_encoder_id(dev, 1522 ATOM_DEVICE_TV1_SUPPORT, 1523 2), 1524 ATOM_DEVICE_TV1_SUPPORT); 1525 radeon_add_legacy_connector(dev, 2, 1526 ATOM_DEVICE_TV1_SUPPORT, 1527 DRM_MODE_CONNECTOR_SVIDEO, 1528 &ddc_i2c, 1529 CONNECTOR_OBJECT_ID_SVIDEO, 1530 &hpd); 1531 } 1532 break; 1533 case CT_IBOOK: 1534 DRM_INFO("Connector Table: %d (ibook)\n", 1535 rdev->mode_info.connector_table); 1536 /* LVDS */ 1537 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1538 hpd.hpd = RADEON_HPD_NONE; 1539 radeon_add_legacy_encoder(dev, 1540 radeon_get_encoder_id(dev, 1541 ATOM_DEVICE_LCD1_SUPPORT, 1542 0), 1543 ATOM_DEVICE_LCD1_SUPPORT); 1544 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1545 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1546 CONNECTOR_OBJECT_ID_LVDS, 1547 &hpd); 1548 /* VGA - TV DAC */ 1549 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1550 hpd.hpd = RADEON_HPD_NONE; 1551 radeon_add_legacy_encoder(dev, 1552 radeon_get_encoder_id(dev, 1553 ATOM_DEVICE_CRT2_SUPPORT, 1554 2), 1555 ATOM_DEVICE_CRT2_SUPPORT); 1556 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1557 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1558 CONNECTOR_OBJECT_ID_VGA, 1559 &hpd); 1560 /* TV - TV DAC */ 1561 ddc_i2c.valid = false; 1562 hpd.hpd = RADEON_HPD_NONE; 1563 radeon_add_legacy_encoder(dev, 1564 radeon_get_encoder_id(dev, 1565 ATOM_DEVICE_TV1_SUPPORT, 1566 2), 1567 ATOM_DEVICE_TV1_SUPPORT); 1568 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1569 DRM_MODE_CONNECTOR_SVIDEO, 1570 &ddc_i2c, 1571 CONNECTOR_OBJECT_ID_SVIDEO, 1572 &hpd); 1573 break; 1574 case CT_POWERBOOK_EXTERNAL: 1575 DRM_INFO("Connector Table: %d (powerbook external tmds)\n", 1576 rdev->mode_info.connector_table); 1577 /* LVDS */ 1578 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1579 hpd.hpd = RADEON_HPD_NONE; 1580 radeon_add_legacy_encoder(dev, 1581 radeon_get_encoder_id(dev, 1582 ATOM_DEVICE_LCD1_SUPPORT, 1583 0), 1584 ATOM_DEVICE_LCD1_SUPPORT); 1585 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1586 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1587 CONNECTOR_OBJECT_ID_LVDS, 1588 &hpd); 1589 /* DVI-I - primary dac, ext tmds */ 1590 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1591 hpd.hpd = RADEON_HPD_2; /* ??? */ 1592 radeon_add_legacy_encoder(dev, 1593 radeon_get_encoder_id(dev, 1594 ATOM_DEVICE_DFP2_SUPPORT, 1595 0), 1596 ATOM_DEVICE_DFP2_SUPPORT); 1597 radeon_add_legacy_encoder(dev, 1598 radeon_get_encoder_id(dev, 1599 ATOM_DEVICE_CRT1_SUPPORT, 1600 1), 1601 ATOM_DEVICE_CRT1_SUPPORT); 1602 /* XXX some are SL */ 1603 radeon_add_legacy_connector(dev, 1, 1604 ATOM_DEVICE_DFP2_SUPPORT | 1605 ATOM_DEVICE_CRT1_SUPPORT, 1606 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1607 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, 1608 &hpd); 1609 /* TV - TV DAC */ 1610 ddc_i2c.valid = false; 1611 hpd.hpd = RADEON_HPD_NONE; 1612 radeon_add_legacy_encoder(dev, 1613 radeon_get_encoder_id(dev, 1614 ATOM_DEVICE_TV1_SUPPORT, 1615 2), 1616 ATOM_DEVICE_TV1_SUPPORT); 1617 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1618 DRM_MODE_CONNECTOR_SVIDEO, 1619 &ddc_i2c, 1620 CONNECTOR_OBJECT_ID_SVIDEO, 1621 &hpd); 1622 break; 1623 case CT_POWERBOOK_INTERNAL: 1624 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n", 1625 rdev->mode_info.connector_table); 1626 /* LVDS */ 1627 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1628 hpd.hpd = RADEON_HPD_NONE; 1629 radeon_add_legacy_encoder(dev, 1630 radeon_get_encoder_id(dev, 1631 ATOM_DEVICE_LCD1_SUPPORT, 1632 0), 1633 ATOM_DEVICE_LCD1_SUPPORT); 1634 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1635 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1636 CONNECTOR_OBJECT_ID_LVDS, 1637 &hpd); 1638 /* DVI-I - primary dac, int tmds */ 1639 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1640 hpd.hpd = RADEON_HPD_1; /* ??? */ 1641 radeon_add_legacy_encoder(dev, 1642 radeon_get_encoder_id(dev, 1643 ATOM_DEVICE_DFP1_SUPPORT, 1644 0), 1645 ATOM_DEVICE_DFP1_SUPPORT); 1646 radeon_add_legacy_encoder(dev, 1647 radeon_get_encoder_id(dev, 1648 ATOM_DEVICE_CRT1_SUPPORT, 1649 1), 1650 ATOM_DEVICE_CRT1_SUPPORT); 1651 radeon_add_legacy_connector(dev, 1, 1652 ATOM_DEVICE_DFP1_SUPPORT | 1653 ATOM_DEVICE_CRT1_SUPPORT, 1654 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1655 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1656 &hpd); 1657 /* TV - TV DAC */ 1658 ddc_i2c.valid = false; 1659 hpd.hpd = RADEON_HPD_NONE; 1660 radeon_add_legacy_encoder(dev, 1661 radeon_get_encoder_id(dev, 1662 ATOM_DEVICE_TV1_SUPPORT, 1663 2), 1664 ATOM_DEVICE_TV1_SUPPORT); 1665 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1666 DRM_MODE_CONNECTOR_SVIDEO, 1667 &ddc_i2c, 1668 CONNECTOR_OBJECT_ID_SVIDEO, 1669 &hpd); 1670 break; 1671 case CT_POWERBOOK_VGA: 1672 DRM_INFO("Connector Table: %d (powerbook vga)\n", 1673 rdev->mode_info.connector_table); 1674 /* LVDS */ 1675 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1676 hpd.hpd = RADEON_HPD_NONE; 1677 radeon_add_legacy_encoder(dev, 1678 radeon_get_encoder_id(dev, 1679 ATOM_DEVICE_LCD1_SUPPORT, 1680 0), 1681 ATOM_DEVICE_LCD1_SUPPORT); 1682 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1683 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1684 CONNECTOR_OBJECT_ID_LVDS, 1685 &hpd); 1686 /* VGA - primary dac */ 1687 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1688 hpd.hpd = RADEON_HPD_NONE; 1689 radeon_add_legacy_encoder(dev, 1690 radeon_get_encoder_id(dev, 1691 ATOM_DEVICE_CRT1_SUPPORT, 1692 1), 1693 ATOM_DEVICE_CRT1_SUPPORT); 1694 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, 1695 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1696 CONNECTOR_OBJECT_ID_VGA, 1697 &hpd); 1698 /* TV - TV DAC */ 1699 ddc_i2c.valid = false; 1700 hpd.hpd = RADEON_HPD_NONE; 1701 radeon_add_legacy_encoder(dev, 1702 radeon_get_encoder_id(dev, 1703 ATOM_DEVICE_TV1_SUPPORT, 1704 2), 1705 ATOM_DEVICE_TV1_SUPPORT); 1706 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1707 DRM_MODE_CONNECTOR_SVIDEO, 1708 &ddc_i2c, 1709 CONNECTOR_OBJECT_ID_SVIDEO, 1710 &hpd); 1711 break; 1712 case CT_MINI_EXTERNAL: 1713 DRM_INFO("Connector Table: %d (mini external tmds)\n", 1714 rdev->mode_info.connector_table); 1715 /* DVI-I - tv dac, ext tmds */ 1716 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1717 hpd.hpd = RADEON_HPD_2; /* ??? */ 1718 radeon_add_legacy_encoder(dev, 1719 radeon_get_encoder_id(dev, 1720 ATOM_DEVICE_DFP2_SUPPORT, 1721 0), 1722 ATOM_DEVICE_DFP2_SUPPORT); 1723 radeon_add_legacy_encoder(dev, 1724 radeon_get_encoder_id(dev, 1725 ATOM_DEVICE_CRT2_SUPPORT, 1726 2), 1727 ATOM_DEVICE_CRT2_SUPPORT); 1728 /* XXX are any DL? */ 1729 radeon_add_legacy_connector(dev, 0, 1730 ATOM_DEVICE_DFP2_SUPPORT | 1731 ATOM_DEVICE_CRT2_SUPPORT, 1732 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1733 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1734 &hpd); 1735 /* TV - TV DAC */ 1736 ddc_i2c.valid = false; 1737 hpd.hpd = RADEON_HPD_NONE; 1738 radeon_add_legacy_encoder(dev, 1739 radeon_get_encoder_id(dev, 1740 ATOM_DEVICE_TV1_SUPPORT, 1741 2), 1742 ATOM_DEVICE_TV1_SUPPORT); 1743 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1744 DRM_MODE_CONNECTOR_SVIDEO, 1745 &ddc_i2c, 1746 CONNECTOR_OBJECT_ID_SVIDEO, 1747 &hpd); 1748 break; 1749 case CT_MINI_INTERNAL: 1750 DRM_INFO("Connector Table: %d (mini internal tmds)\n", 1751 rdev->mode_info.connector_table); 1752 /* DVI-I - tv dac, int tmds */ 1753 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1754 hpd.hpd = RADEON_HPD_1; /* ??? */ 1755 radeon_add_legacy_encoder(dev, 1756 radeon_get_encoder_id(dev, 1757 ATOM_DEVICE_DFP1_SUPPORT, 1758 0), 1759 ATOM_DEVICE_DFP1_SUPPORT); 1760 radeon_add_legacy_encoder(dev, 1761 radeon_get_encoder_id(dev, 1762 ATOM_DEVICE_CRT2_SUPPORT, 1763 2), 1764 ATOM_DEVICE_CRT2_SUPPORT); 1765 radeon_add_legacy_connector(dev, 0, 1766 ATOM_DEVICE_DFP1_SUPPORT | 1767 ATOM_DEVICE_CRT2_SUPPORT, 1768 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1769 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1770 &hpd); 1771 /* TV - TV DAC */ 1772 ddc_i2c.valid = false; 1773 hpd.hpd = RADEON_HPD_NONE; 1774 radeon_add_legacy_encoder(dev, 1775 radeon_get_encoder_id(dev, 1776 ATOM_DEVICE_TV1_SUPPORT, 1777 2), 1778 ATOM_DEVICE_TV1_SUPPORT); 1779 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1780 DRM_MODE_CONNECTOR_SVIDEO, 1781 &ddc_i2c, 1782 CONNECTOR_OBJECT_ID_SVIDEO, 1783 &hpd); 1784 break; 1785 case CT_IMAC_G5_ISIGHT: 1786 DRM_INFO("Connector Table: %d (imac g5 isight)\n", 1787 rdev->mode_info.connector_table); 1788 /* DVI-D - int tmds */ 1789 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1790 hpd.hpd = RADEON_HPD_1; /* ??? */ 1791 radeon_add_legacy_encoder(dev, 1792 radeon_get_encoder_id(dev, 1793 ATOM_DEVICE_DFP1_SUPPORT, 1794 0), 1795 ATOM_DEVICE_DFP1_SUPPORT); 1796 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT, 1797 DRM_MODE_CONNECTOR_DVID, &ddc_i2c, 1798 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 1799 &hpd); 1800 /* VGA - tv dac */ 1801 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1802 hpd.hpd = RADEON_HPD_NONE; 1803 radeon_add_legacy_encoder(dev, 1804 radeon_get_encoder_id(dev, 1805 ATOM_DEVICE_CRT2_SUPPORT, 1806 2), 1807 ATOM_DEVICE_CRT2_SUPPORT); 1808 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1809 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1810 CONNECTOR_OBJECT_ID_VGA, 1811 &hpd); 1812 /* TV - TV DAC */ 1813 ddc_i2c.valid = false; 1814 hpd.hpd = RADEON_HPD_NONE; 1815 radeon_add_legacy_encoder(dev, 1816 radeon_get_encoder_id(dev, 1817 ATOM_DEVICE_TV1_SUPPORT, 1818 2), 1819 ATOM_DEVICE_TV1_SUPPORT); 1820 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1821 DRM_MODE_CONNECTOR_SVIDEO, 1822 &ddc_i2c, 1823 CONNECTOR_OBJECT_ID_SVIDEO, 1824 &hpd); 1825 break; 1826 case CT_EMAC: 1827 DRM_INFO("Connector Table: %d (emac)\n", 1828 rdev->mode_info.connector_table); 1829 /* VGA - primary dac */ 1830 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1831 hpd.hpd = RADEON_HPD_NONE; 1832 radeon_add_legacy_encoder(dev, 1833 radeon_get_encoder_id(dev, 1834 ATOM_DEVICE_CRT1_SUPPORT, 1835 1), 1836 ATOM_DEVICE_CRT1_SUPPORT); 1837 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, 1838 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1839 CONNECTOR_OBJECT_ID_VGA, 1840 &hpd); 1841 /* VGA - tv dac */ 1842 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1843 hpd.hpd = RADEON_HPD_NONE; 1844 radeon_add_legacy_encoder(dev, 1845 radeon_get_encoder_id(dev, 1846 ATOM_DEVICE_CRT2_SUPPORT, 1847 2), 1848 ATOM_DEVICE_CRT2_SUPPORT); 1849 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1850 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1851 CONNECTOR_OBJECT_ID_VGA, 1852 &hpd); 1853 /* TV - TV DAC */ 1854 ddc_i2c.valid = false; 1855 hpd.hpd = RADEON_HPD_NONE; 1856 radeon_add_legacy_encoder(dev, 1857 radeon_get_encoder_id(dev, 1858 ATOM_DEVICE_TV1_SUPPORT, 1859 2), 1860 ATOM_DEVICE_TV1_SUPPORT); 1861 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1862 DRM_MODE_CONNECTOR_SVIDEO, 1863 &ddc_i2c, 1864 CONNECTOR_OBJECT_ID_SVIDEO, 1865 &hpd); 1866 break; 1867 default: 1868 DRM_INFO("Connector table: %d (invalid)\n", 1869 rdev->mode_info.connector_table); 1870 return false; 1871 } 1872 1873 radeon_link_encoder_connector(dev); 1874 1875 return true; 1876} 1877 1878static bool radeon_apply_legacy_quirks(struct drm_device *dev, 1879 int bios_index, 1880 enum radeon_combios_connector 1881 *legacy_connector, 1882 struct radeon_i2c_bus_rec *ddc_i2c, 1883 struct radeon_hpd *hpd) 1884{ 1885 struct radeon_device *rdev = dev->dev_private; 1886 1887 /* XPRESS DDC quirks */ 1888 if ((rdev->family == CHIP_RS400 || 1889 rdev->family == CHIP_RS480) && 1890 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) 1891 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1892 else if ((rdev->family == CHIP_RS400 || 1893 rdev->family == CHIP_RS480) && 1894 ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) { 1895 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK); 1896 ddc_i2c->mask_clk_mask = (0x20 << 8); 1897 ddc_i2c->mask_data_mask = 0x80; 1898 ddc_i2c->a_clk_mask = (0x20 << 8); 1899 ddc_i2c->a_data_mask = 0x80; 1900 ddc_i2c->en_clk_mask = (0x20 << 8); 1901 ddc_i2c->en_data_mask = 0x80; 1902 ddc_i2c->y_clk_mask = (0x20 << 8); 1903 ddc_i2c->y_data_mask = 0x80; 1904 } 1905 1906 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */ 1907 if ((rdev->family >= CHIP_R300) && 1908 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) 1909 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1910 1911 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, 1912 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ 1913 if (dev->pdev->device == 0x515e && 1914 dev->pdev->subsystem_vendor == 0x1014) { 1915 if (*legacy_connector == CONNECTOR_CRT_LEGACY && 1916 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) 1917 return false; 1918 } 1919 1920 /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */ 1921 if (dev->pdev->device == 0x5159 && 1922 dev->pdev->subsystem_vendor == 0x1002 && 1923 dev->pdev->subsystem_device == 0x013a) { 1924 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY) 1925 *legacy_connector = CONNECTOR_CRT_LEGACY; 1926 1927 } 1928 1929 /* X300 card with extra non-existent DVI port */ 1930 if (dev->pdev->device == 0x5B60 && 1931 dev->pdev->subsystem_vendor == 0x17af && 1932 dev->pdev->subsystem_device == 0x201e && bios_index == 2) { 1933 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY) 1934 return false; 1935 } 1936 1937 return true; 1938} 1939 1940static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev) 1941{ 1942 /* Acer 5102 has non-existent TV port */ 1943 if (dev->pdev->device == 0x5975 && 1944 dev->pdev->subsystem_vendor == 0x1025 && 1945 dev->pdev->subsystem_device == 0x009f) 1946 return false; 1947 1948 /* HP dc5750 has non-existent TV port */ 1949 if (dev->pdev->device == 0x5974 && 1950 dev->pdev->subsystem_vendor == 0x103c && 1951 dev->pdev->subsystem_device == 0x280a) 1952 return false; 1953 1954 /* MSI S270 has non-existent TV port */ 1955 if (dev->pdev->device == 0x5955 && 1956 dev->pdev->subsystem_vendor == 0x1462 && 1957 dev->pdev->subsystem_device == 0x0131) 1958 return false; 1959 1960 return true; 1961} 1962 1963static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d) 1964{ 1965 struct radeon_device *rdev = dev->dev_private; 1966 uint32_t ext_tmds_info; 1967 1968 if (rdev->flags & RADEON_IS_IGP) { 1969 if (is_dvi_d) 1970 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 1971 else 1972 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 1973 } 1974 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 1975 if (ext_tmds_info) { 1976 uint8_t rev = RBIOS8(ext_tmds_info); 1977 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5); 1978 if (rev >= 3) { 1979 if (is_dvi_d) 1980 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 1981 else 1982 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 1983 } else { 1984 if (flags & 1) { 1985 if (is_dvi_d) 1986 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 1987 else 1988 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 1989 } 1990 } 1991 } 1992 if (is_dvi_d) 1993 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 1994 else 1995 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 1996} 1997 1998bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) 1999{ 2000 struct radeon_device *rdev = dev->dev_private; 2001 uint32_t conn_info, entry, devices; 2002 uint16_t tmp, connector_object_id; 2003 enum radeon_combios_ddc ddc_type; 2004 enum radeon_combios_connector connector; 2005 int i = 0; 2006 struct radeon_i2c_bus_rec ddc_i2c; 2007 struct radeon_hpd hpd; 2008 2009 if (rdev->bios == NULL) 2010 return false; 2011 2012 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE); 2013 if (conn_info) { 2014 for (i = 0; i < 4; i++) { 2015 entry = conn_info + 2 + i * 2; 2016 2017 if (!RBIOS16(entry)) 2018 break; 2019 2020 tmp = RBIOS16(entry); 2021 2022 connector = (tmp >> 12) & 0xf; 2023 2024 ddc_type = (tmp >> 8) & 0xf; 2025 switch (ddc_type) { 2026 case DDC_MONID: 2027 ddc_i2c = 2028 combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 2029 break; 2030 case DDC_DVI: 2031 ddc_i2c = 2032 combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 2033 break; 2034 case DDC_VGA: 2035 ddc_i2c = 2036 combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 2037 break; 2038 case DDC_CRT2: 2039 ddc_i2c = 2040 combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 2041 break; 2042 default: 2043 break; 2044 } 2045 2046 switch (connector) { 2047 case CONNECTOR_PROPRIETARY_LEGACY: 2048 case CONNECTOR_DVI_I_LEGACY: 2049 case CONNECTOR_DVI_D_LEGACY: 2050 if ((tmp >> 4) & 0x1) 2051 hpd.hpd = RADEON_HPD_2; 2052 else 2053 hpd.hpd = RADEON_HPD_1; 2054 break; 2055 default: 2056 hpd.hpd = RADEON_HPD_NONE; 2057 break; 2058 } 2059 2060 if (!radeon_apply_legacy_quirks(dev, i, &connector, 2061 &ddc_i2c, &hpd)) 2062 continue; 2063 2064 switch (connector) { 2065 case CONNECTOR_PROPRIETARY_LEGACY: 2066 if ((tmp >> 4) & 0x1) 2067 devices = ATOM_DEVICE_DFP2_SUPPORT; 2068 else 2069 devices = ATOM_DEVICE_DFP1_SUPPORT; 2070 radeon_add_legacy_encoder(dev, 2071 radeon_get_encoder_id 2072 (dev, devices, 0), 2073 devices); 2074 radeon_add_legacy_connector(dev, i, devices, 2075 legacy_connector_convert 2076 [connector], 2077 &ddc_i2c, 2078 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 2079 &hpd); 2080 break; 2081 case CONNECTOR_CRT_LEGACY: 2082 if (tmp & 0x1) { 2083 devices = ATOM_DEVICE_CRT2_SUPPORT; 2084 radeon_add_legacy_encoder(dev, 2085 radeon_get_encoder_id 2086 (dev, 2087 ATOM_DEVICE_CRT2_SUPPORT, 2088 2), 2089 ATOM_DEVICE_CRT2_SUPPORT); 2090 } else { 2091 devices = ATOM_DEVICE_CRT1_SUPPORT; 2092 radeon_add_legacy_encoder(dev, 2093 radeon_get_encoder_id 2094 (dev, 2095 ATOM_DEVICE_CRT1_SUPPORT, 2096 1), 2097 ATOM_DEVICE_CRT1_SUPPORT); 2098 } 2099 radeon_add_legacy_connector(dev, 2100 i, 2101 devices, 2102 legacy_connector_convert 2103 [connector], 2104 &ddc_i2c, 2105 CONNECTOR_OBJECT_ID_VGA, 2106 &hpd); 2107 break; 2108 case CONNECTOR_DVI_I_LEGACY: 2109 devices = 0; 2110 if (tmp & 0x1) { 2111 devices |= ATOM_DEVICE_CRT2_SUPPORT; 2112 radeon_add_legacy_encoder(dev, 2113 radeon_get_encoder_id 2114 (dev, 2115 ATOM_DEVICE_CRT2_SUPPORT, 2116 2), 2117 ATOM_DEVICE_CRT2_SUPPORT); 2118 } else { 2119 devices |= ATOM_DEVICE_CRT1_SUPPORT; 2120 radeon_add_legacy_encoder(dev, 2121 radeon_get_encoder_id 2122 (dev, 2123 ATOM_DEVICE_CRT1_SUPPORT, 2124 1), 2125 ATOM_DEVICE_CRT1_SUPPORT); 2126 } 2127 if ((tmp >> 4) & 0x1) { 2128 devices |= ATOM_DEVICE_DFP2_SUPPORT; 2129 radeon_add_legacy_encoder(dev, 2130 radeon_get_encoder_id 2131 (dev, 2132 ATOM_DEVICE_DFP2_SUPPORT, 2133 0), 2134 ATOM_DEVICE_DFP2_SUPPORT); 2135 connector_object_id = combios_check_dl_dvi(dev, 0); 2136 } else { 2137 devices |= ATOM_DEVICE_DFP1_SUPPORT; 2138 radeon_add_legacy_encoder(dev, 2139 radeon_get_encoder_id 2140 (dev, 2141 ATOM_DEVICE_DFP1_SUPPORT, 2142 0), 2143 ATOM_DEVICE_DFP1_SUPPORT); 2144 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2145 } 2146 radeon_add_legacy_connector(dev, 2147 i, 2148 devices, 2149 legacy_connector_convert 2150 [connector], 2151 &ddc_i2c, 2152 connector_object_id, 2153 &hpd); 2154 break; 2155 case CONNECTOR_DVI_D_LEGACY: 2156 if ((tmp >> 4) & 0x1) { 2157 devices = ATOM_DEVICE_DFP2_SUPPORT; 2158 connector_object_id = combios_check_dl_dvi(dev, 1); 2159 } else { 2160 devices = ATOM_DEVICE_DFP1_SUPPORT; 2161 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2162 } 2163 radeon_add_legacy_encoder(dev, 2164 radeon_get_encoder_id 2165 (dev, devices, 0), 2166 devices); 2167 radeon_add_legacy_connector(dev, i, devices, 2168 legacy_connector_convert 2169 [connector], 2170 &ddc_i2c, 2171 connector_object_id, 2172 &hpd); 2173 break; 2174 case CONNECTOR_CTV_LEGACY: 2175 case CONNECTOR_STV_LEGACY: 2176 radeon_add_legacy_encoder(dev, 2177 radeon_get_encoder_id 2178 (dev, 2179 ATOM_DEVICE_TV1_SUPPORT, 2180 2), 2181 ATOM_DEVICE_TV1_SUPPORT); 2182 radeon_add_legacy_connector(dev, i, 2183 ATOM_DEVICE_TV1_SUPPORT, 2184 legacy_connector_convert 2185 [connector], 2186 &ddc_i2c, 2187 CONNECTOR_OBJECT_ID_SVIDEO, 2188 &hpd); 2189 break; 2190 default: 2191 DRM_ERROR("Unknown connector type: %d\n", 2192 connector); 2193 continue; 2194 } 2195 2196 } 2197 } else { 2198 uint16_t tmds_info = 2199 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 2200 if (tmds_info) { 2201 DRM_DEBUG("Found DFP table, assuming DVI connector\n"); 2202 2203 radeon_add_legacy_encoder(dev, 2204 radeon_get_encoder_id(dev, 2205 ATOM_DEVICE_CRT1_SUPPORT, 2206 1), 2207 ATOM_DEVICE_CRT1_SUPPORT); 2208 radeon_add_legacy_encoder(dev, 2209 radeon_get_encoder_id(dev, 2210 ATOM_DEVICE_DFP1_SUPPORT, 2211 0), 2212 ATOM_DEVICE_DFP1_SUPPORT); 2213 2214 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 2215 hpd.hpd = RADEON_HPD_NONE; 2216 radeon_add_legacy_connector(dev, 2217 0, 2218 ATOM_DEVICE_CRT1_SUPPORT | 2219 ATOM_DEVICE_DFP1_SUPPORT, 2220 DRM_MODE_CONNECTOR_DVII, 2221 &ddc_i2c, 2222 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2223 &hpd); 2224 } else { 2225 uint16_t crt_info = 2226 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 2227 DRM_DEBUG("Found CRT table, assuming VGA connector\n"); 2228 if (crt_info) { 2229 radeon_add_legacy_encoder(dev, 2230 radeon_get_encoder_id(dev, 2231 ATOM_DEVICE_CRT1_SUPPORT, 2232 1), 2233 ATOM_DEVICE_CRT1_SUPPORT); 2234 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 2235 hpd.hpd = RADEON_HPD_NONE; 2236 radeon_add_legacy_connector(dev, 2237 0, 2238 ATOM_DEVICE_CRT1_SUPPORT, 2239 DRM_MODE_CONNECTOR_VGA, 2240 &ddc_i2c, 2241 CONNECTOR_OBJECT_ID_VGA, 2242 &hpd); 2243 } else { 2244 DRM_DEBUG("No connector info found\n"); 2245 return false; 2246 } 2247 } 2248 } 2249 2250 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) { 2251 uint16_t lcd_info = 2252 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 2253 if (lcd_info) { 2254 uint16_t lcd_ddc_info = 2255 combios_get_table_offset(dev, 2256 COMBIOS_LCD_DDC_INFO_TABLE); 2257 2258 radeon_add_legacy_encoder(dev, 2259 radeon_get_encoder_id(dev, 2260 ATOM_DEVICE_LCD1_SUPPORT, 2261 0), 2262 ATOM_DEVICE_LCD1_SUPPORT); 2263 2264 if (lcd_ddc_info) { 2265 ddc_type = RBIOS8(lcd_ddc_info + 2); 2266 switch (ddc_type) { 2267 case DDC_MONID: 2268 ddc_i2c = 2269 combios_setup_i2c_bus 2270 (rdev, RADEON_GPIO_MONID); 2271 break; 2272 case DDC_DVI: 2273 ddc_i2c = 2274 combios_setup_i2c_bus 2275 (rdev, RADEON_GPIO_DVI_DDC); 2276 break; 2277 case DDC_VGA: 2278 ddc_i2c = 2279 combios_setup_i2c_bus 2280 (rdev, RADEON_GPIO_VGA_DDC); 2281 break; 2282 case DDC_CRT2: 2283 ddc_i2c = 2284 combios_setup_i2c_bus 2285 (rdev, RADEON_GPIO_CRT2_DDC); 2286 break; 2287 case DDC_LCD: 2288 ddc_i2c = 2289 combios_setup_i2c_bus 2290 (rdev, RADEON_GPIOPAD_MASK); 2291 ddc_i2c.mask_clk_mask = 2292 RBIOS32(lcd_ddc_info + 3); 2293 ddc_i2c.mask_data_mask = 2294 RBIOS32(lcd_ddc_info + 7); 2295 ddc_i2c.a_clk_mask = 2296 RBIOS32(lcd_ddc_info + 3); 2297 ddc_i2c.a_data_mask = 2298 RBIOS32(lcd_ddc_info + 7); 2299 ddc_i2c.en_clk_mask = 2300 RBIOS32(lcd_ddc_info + 3); 2301 ddc_i2c.en_data_mask = 2302 RBIOS32(lcd_ddc_info + 7); 2303 ddc_i2c.y_clk_mask = 2304 RBIOS32(lcd_ddc_info + 3); 2305 ddc_i2c.y_data_mask = 2306 RBIOS32(lcd_ddc_info + 7); 2307 break; 2308 case DDC_GPIO: 2309 ddc_i2c = 2310 combios_setup_i2c_bus 2311 (rdev, RADEON_MDGPIO_MASK); 2312 ddc_i2c.mask_clk_mask = 2313 RBIOS32(lcd_ddc_info + 3); 2314 ddc_i2c.mask_data_mask = 2315 RBIOS32(lcd_ddc_info + 7); 2316 ddc_i2c.a_clk_mask = 2317 RBIOS32(lcd_ddc_info + 3); 2318 ddc_i2c.a_data_mask = 2319 RBIOS32(lcd_ddc_info + 7); 2320 ddc_i2c.en_clk_mask = 2321 RBIOS32(lcd_ddc_info + 3); 2322 ddc_i2c.en_data_mask = 2323 RBIOS32(lcd_ddc_info + 7); 2324 ddc_i2c.y_clk_mask = 2325 RBIOS32(lcd_ddc_info + 3); 2326 ddc_i2c.y_data_mask = 2327 RBIOS32(lcd_ddc_info + 7); 2328 break; 2329 default: 2330 ddc_i2c.valid = false; 2331 break; 2332 } 2333 DRM_DEBUG("LCD DDC Info Table found!\n"); 2334 } else 2335 ddc_i2c.valid = false; 2336 2337 hpd.hpd = RADEON_HPD_NONE; 2338 radeon_add_legacy_connector(dev, 2339 5, 2340 ATOM_DEVICE_LCD1_SUPPORT, 2341 DRM_MODE_CONNECTOR_LVDS, 2342 &ddc_i2c, 2343 CONNECTOR_OBJECT_ID_LVDS, 2344 &hpd); 2345 } 2346 } 2347 2348 /* check TV table */ 2349 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 2350 uint32_t tv_info = 2351 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 2352 if (tv_info) { 2353 if (RBIOS8(tv_info + 6) == 'T') { 2354 if (radeon_apply_legacy_tv_quirks(dev)) { 2355 hpd.hpd = RADEON_HPD_NONE; 2356 radeon_add_legacy_encoder(dev, 2357 radeon_get_encoder_id 2358 (dev, 2359 ATOM_DEVICE_TV1_SUPPORT, 2360 2), 2361 ATOM_DEVICE_TV1_SUPPORT); 2362 radeon_add_legacy_connector(dev, 6, 2363 ATOM_DEVICE_TV1_SUPPORT, 2364 DRM_MODE_CONNECTOR_SVIDEO, 2365 &ddc_i2c, 2366 CONNECTOR_OBJECT_ID_SVIDEO, 2367 &hpd); 2368 } 2369 } 2370 } 2371 } 2372 2373 radeon_link_encoder_connector(dev); 2374 2375 return true; 2376} 2377 2378void radeon_combios_get_power_modes(struct radeon_device *rdev) 2379{ 2380 struct drm_device *dev = rdev->ddev; 2381 u16 offset, misc, misc2 = 0; 2382 u8 rev, blocks, tmp; 2383 int state_index = 0; 2384 2385 rdev->pm.default_power_state = NULL; 2386 rdev->pm.current_power_state = NULL; 2387 2388 /* XXX mac/sparc cards */ 2389 if (rdev->bios == NULL) 2390 goto default_mode; 2391 2392 if (rdev->flags & RADEON_IS_MOBILITY) { 2393 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE); 2394 if (offset) { 2395 rev = RBIOS8(offset); 2396 blocks = RBIOS8(offset + 0x2); 2397 /* power mode 0 tends to be the only valid one */ 2398 rdev->pm.power_state[state_index].num_clock_modes = 1; 2399 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2); 2400 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6); 2401 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2402 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2403 goto default_mode; 2404 /* skip overclock modes for now */ 2405 if ((rdev->pm.power_state[state_index].clock_info[0].mclk > 2406 rdev->clock.default_mclk) || 2407 (rdev->pm.power_state[state_index].clock_info[0].sclk > 2408 rdev->clock.default_sclk)) 2409 goto default_mode; 2410 rdev->pm.power_state[state_index].type = 2411 POWER_STATE_TYPE_BATTERY; 2412 misc = RBIOS16(offset + 0x5 + 0x0); 2413 if (rev > 4) 2414 misc2 = RBIOS16(offset + 0x5 + 0xe); 2415 if (misc & 0x4) { 2416 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO; 2417 if (misc & 0x8) 2418 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2419 true; 2420 else 2421 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2422 false; 2423 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true; 2424 if (rev < 6) { 2425 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = 2426 RBIOS16(offset + 0x5 + 0xb) * 4; 2427 tmp = RBIOS8(offset + 0x5 + 0xd); 2428 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); 2429 } else { 2430 u8 entries = RBIOS8(offset + 0x5 + 0xb); 2431 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc); 2432 if (entries && voltage_table_offset) { 2433 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = 2434 RBIOS16(voltage_table_offset) * 4; 2435 tmp = RBIOS8(voltage_table_offset + 0x2); 2436 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); 2437 } else 2438 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false; 2439 } 2440 switch ((misc2 & 0x700) >> 8) { 2441 case 0: 2442 default: 2443 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0; 2444 break; 2445 case 1: 2446 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33; 2447 break; 2448 case 2: 2449 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66; 2450 break; 2451 case 3: 2452 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99; 2453 break; 2454 case 4: 2455 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132; 2456 break; 2457 } 2458 } else 2459 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2460 if (rev > 6) 2461 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 2462 RBIOS8(offset + 0x5 + 0x10); 2463 state_index++; 2464 } else { 2465 /* XXX figure out some good default low power mode for mobility cards w/out power tables */ 2466 } 2467 } else { 2468 /* XXX figure out some good default low power mode for desktop cards */ 2469 } 2470 2471default_mode: 2472 /* add the default mode */ 2473 rdev->pm.power_state[state_index].type = 2474 POWER_STATE_TYPE_DEFAULT; 2475 rdev->pm.power_state[state_index].num_clock_modes = 1; 2476 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; 2477 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; 2478 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; 2479 rdev->pm.power_state[state_index].current_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; 2480 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2481 if (rdev->asic->get_pcie_lanes) 2482 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev); 2483 else 2484 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16; 2485 rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; 2486 rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; 2487 rdev->pm.num_power_states = state_index + 1; 2488} 2489 2490void radeon_external_tmds_setup(struct drm_encoder *encoder) 2491{ 2492 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2493 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2494 2495 if (!tmds) 2496 return; 2497 2498 switch (tmds->dvo_chip) { 2499 case DVO_SIL164: 2500 /* sil 164 */ 2501 radeon_i2c_put_byte(tmds->i2c_bus, 2502 tmds->slave_addr, 2503 0x08, 0x30); 2504 radeon_i2c_put_byte(tmds->i2c_bus, 2505 tmds->slave_addr, 2506 0x09, 0x00); 2507 radeon_i2c_put_byte(tmds->i2c_bus, 2508 tmds->slave_addr, 2509 0x0a, 0x90); 2510 radeon_i2c_put_byte(tmds->i2c_bus, 2511 tmds->slave_addr, 2512 0x0c, 0x89); 2513 radeon_i2c_put_byte(tmds->i2c_bus, 2514 tmds->slave_addr, 2515 0x08, 0x3b); 2516 break; 2517 case DVO_SIL1178: 2518 /* sil 1178 - untested */ 2519 /* 2520 * 0x0f, 0x44 2521 * 0x0f, 0x4c 2522 * 0x0e, 0x01 2523 * 0x0a, 0x80 2524 * 0x09, 0x30 2525 * 0x0c, 0xc9 2526 * 0x0d, 0x70 2527 * 0x08, 0x32 2528 * 0x08, 0x33 2529 */ 2530 break; 2531 default: 2532 break; 2533 } 2534 2535} 2536 2537bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder) 2538{ 2539 struct drm_device *dev = encoder->dev; 2540 struct radeon_device *rdev = dev->dev_private; 2541 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2542 uint16_t offset; 2543 uint8_t blocks, slave_addr, rev; 2544 uint32_t index, id; 2545 uint32_t reg, val, and_mask, or_mask; 2546 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2547 2548 if (rdev->bios == NULL) 2549 return false; 2550 2551 if (!tmds) 2552 return false; 2553 2554 if (rdev->flags & RADEON_IS_IGP) { 2555 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE); 2556 rev = RBIOS8(offset); 2557 if (offset) { 2558 rev = RBIOS8(offset); 2559 if (rev > 1) { 2560 blocks = RBIOS8(offset + 3); 2561 index = offset + 4; 2562 while (blocks > 0) { 2563 id = RBIOS16(index); 2564 index += 2; 2565 switch (id >> 13) { 2566 case 0: 2567 reg = (id & 0x1fff) * 4; 2568 val = RBIOS32(index); 2569 index += 4; 2570 WREG32(reg, val); 2571 break; 2572 case 2: 2573 reg = (id & 0x1fff) * 4; 2574 and_mask = RBIOS32(index); 2575 index += 4; 2576 or_mask = RBIOS32(index); 2577 index += 4; 2578 val = RREG32(reg); 2579 val = (val & and_mask) | or_mask; 2580 WREG32(reg, val); 2581 break; 2582 case 3: 2583 val = RBIOS16(index); 2584 index += 2; 2585 udelay(val); 2586 break; 2587 case 4: 2588 val = RBIOS16(index); 2589 index += 2; 2590 udelay(val * 1000); 2591 break; 2592 case 6: 2593 slave_addr = id & 0xff; 2594 slave_addr >>= 1; /* 7 bit addressing */ 2595 index++; 2596 reg = RBIOS8(index); 2597 index++; 2598 val = RBIOS8(index); 2599 index++; 2600 radeon_i2c_put_byte(tmds->i2c_bus, 2601 slave_addr, 2602 reg, val); 2603 break; 2604 default: 2605 DRM_ERROR("Unknown id %d\n", id >> 13); 2606 break; 2607 } 2608 blocks--; 2609 } 2610 return true; 2611 } 2612 } 2613 } else { 2614 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 2615 if (offset) { 2616 index = offset + 10; 2617 id = RBIOS16(index); 2618 while (id != 0xffff) { 2619 index += 2; 2620 switch (id >> 13) { 2621 case 0: 2622 reg = (id & 0x1fff) * 4; 2623 val = RBIOS32(index); 2624 WREG32(reg, val); 2625 break; 2626 case 2: 2627 reg = (id & 0x1fff) * 4; 2628 and_mask = RBIOS32(index); 2629 index += 4; 2630 or_mask = RBIOS32(index); 2631 index += 4; 2632 val = RREG32(reg); 2633 val = (val & and_mask) | or_mask; 2634 WREG32(reg, val); 2635 break; 2636 case 4: 2637 val = RBIOS16(index); 2638 index += 2; 2639 udelay(val); 2640 break; 2641 case 5: 2642 reg = id & 0x1fff; 2643 and_mask = RBIOS32(index); 2644 index += 4; 2645 or_mask = RBIOS32(index); 2646 index += 4; 2647 val = RREG32_PLL(reg); 2648 val = (val & and_mask) | or_mask; 2649 WREG32_PLL(reg, val); 2650 break; 2651 case 6: 2652 reg = id & 0x1fff; 2653 val = RBIOS8(index); 2654 index += 1; 2655 radeon_i2c_put_byte(tmds->i2c_bus, 2656 tmds->slave_addr, 2657 reg, val); 2658 break; 2659 default: 2660 DRM_ERROR("Unknown id %d\n", id >> 13); 2661 break; 2662 } 2663 id = RBIOS16(index); 2664 } 2665 return true; 2666 } 2667 } 2668 return false; 2669} 2670 2671static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset) 2672{ 2673 struct radeon_device *rdev = dev->dev_private; 2674 2675 if (offset) { 2676 while (RBIOS16(offset)) { 2677 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13); 2678 uint32_t addr = (RBIOS16(offset) & 0x1fff); 2679 uint32_t val, and_mask, or_mask; 2680 uint32_t tmp; 2681 2682 offset += 2; 2683 switch (cmd) { 2684 case 0: 2685 val = RBIOS32(offset); 2686 offset += 4; 2687 WREG32(addr, val); 2688 break; 2689 case 1: 2690 val = RBIOS32(offset); 2691 offset += 4; 2692 WREG32(addr, val); 2693 break; 2694 case 2: 2695 and_mask = RBIOS32(offset); 2696 offset += 4; 2697 or_mask = RBIOS32(offset); 2698 offset += 4; 2699 tmp = RREG32(addr); 2700 tmp &= and_mask; 2701 tmp |= or_mask; 2702 WREG32(addr, tmp); 2703 break; 2704 case 3: 2705 and_mask = RBIOS32(offset); 2706 offset += 4; 2707 or_mask = RBIOS32(offset); 2708 offset += 4; 2709 tmp = RREG32(addr); 2710 tmp &= and_mask; 2711 tmp |= or_mask; 2712 WREG32(addr, tmp); 2713 break; 2714 case 4: 2715 val = RBIOS16(offset); 2716 offset += 2; 2717 udelay(val); 2718 break; 2719 case 5: 2720 val = RBIOS16(offset); 2721 offset += 2; 2722 switch (addr) { 2723 case 8: 2724 while (val--) { 2725 if (! 2726 (RREG32_PLL 2727 (RADEON_CLK_PWRMGT_CNTL) & 2728 RADEON_MC_BUSY)) 2729 break; 2730 } 2731 break; 2732 case 9: 2733 while (val--) { 2734 if ((RREG32(RADEON_MC_STATUS) & 2735 RADEON_MC_IDLE)) 2736 break; 2737 } 2738 break; 2739 default: 2740 break; 2741 } 2742 break; 2743 default: 2744 break; 2745 } 2746 } 2747 } 2748} 2749 2750static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset) 2751{ 2752 struct radeon_device *rdev = dev->dev_private; 2753 2754 if (offset) { 2755 while (RBIOS8(offset)) { 2756 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6); 2757 uint8_t addr = (RBIOS8(offset) & 0x3f); 2758 uint32_t val, shift, tmp; 2759 uint32_t and_mask, or_mask; 2760 2761 offset++; 2762 switch (cmd) { 2763 case 0: 2764 val = RBIOS32(offset); 2765 offset += 4; 2766 WREG32_PLL(addr, val); 2767 break; 2768 case 1: 2769 shift = RBIOS8(offset) * 8; 2770 offset++; 2771 and_mask = RBIOS8(offset) << shift; 2772 and_mask |= ~(0xff << shift); 2773 offset++; 2774 or_mask = RBIOS8(offset) << shift; 2775 offset++; 2776 tmp = RREG32_PLL(addr); 2777 tmp &= and_mask; 2778 tmp |= or_mask; 2779 WREG32_PLL(addr, tmp); 2780 break; 2781 case 2: 2782 case 3: 2783 tmp = 1000; 2784 switch (addr) { 2785 case 1: 2786 udelay(150); 2787 break; 2788 case 2: 2789 udelay(1000); 2790 break; 2791 case 3: 2792 while (tmp--) { 2793 if (! 2794 (RREG32_PLL 2795 (RADEON_CLK_PWRMGT_CNTL) & 2796 RADEON_MC_BUSY)) 2797 break; 2798 } 2799 break; 2800 case 4: 2801 while (tmp--) { 2802 if (RREG32_PLL 2803 (RADEON_CLK_PWRMGT_CNTL) & 2804 RADEON_DLL_READY) 2805 break; 2806 } 2807 break; 2808 case 5: 2809 tmp = 2810 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); 2811 if (tmp & RADEON_CG_NO1_DEBUG_0) { 2812#if 0 2813 uint32_t mclk_cntl = 2814 RREG32_PLL 2815 (RADEON_MCLK_CNTL); 2816 mclk_cntl &= 0xffff0000; 2817 /*mclk_cntl |= 0x00001111;*//* ??? */ 2818 WREG32_PLL(RADEON_MCLK_CNTL, 2819 mclk_cntl); 2820 udelay(10000); 2821#endif 2822 WREG32_PLL 2823 (RADEON_CLK_PWRMGT_CNTL, 2824 tmp & 2825 ~RADEON_CG_NO1_DEBUG_0); 2826 udelay(10000); 2827 } 2828 break; 2829 default: 2830 break; 2831 } 2832 break; 2833 default: 2834 break; 2835 } 2836 } 2837 } 2838} 2839 2840static void combios_parse_ram_reset_table(struct drm_device *dev, 2841 uint16_t offset) 2842{ 2843 struct radeon_device *rdev = dev->dev_private; 2844 uint32_t tmp; 2845 2846 if (offset) { 2847 uint8_t val = RBIOS8(offset); 2848 while (val != 0xff) { 2849 offset++; 2850 2851 if (val == 0x0f) { 2852 uint32_t channel_complete_mask; 2853 2854 if (ASIC_IS_R300(rdev)) 2855 channel_complete_mask = 2856 R300_MEM_PWRUP_COMPLETE; 2857 else 2858 channel_complete_mask = 2859 RADEON_MEM_PWRUP_COMPLETE; 2860 tmp = 20000; 2861 while (tmp--) { 2862 if ((RREG32(RADEON_MEM_STR_CNTL) & 2863 channel_complete_mask) == 2864 channel_complete_mask) 2865 break; 2866 } 2867 } else { 2868 uint32_t or_mask = RBIOS16(offset); 2869 offset += 2; 2870 2871 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 2872 tmp &= RADEON_SDRAM_MODE_MASK; 2873 tmp |= or_mask; 2874 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 2875 2876 or_mask = val << 24; 2877 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 2878 tmp &= RADEON_B3MEM_RESET_MASK; 2879 tmp |= or_mask; 2880 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 2881 } 2882 val = RBIOS8(offset); 2883 } 2884 } 2885} 2886 2887static uint32_t combios_detect_ram(struct drm_device *dev, int ram, 2888 int mem_addr_mapping) 2889{ 2890 struct radeon_device *rdev = dev->dev_private; 2891 uint32_t mem_cntl; 2892 uint32_t mem_size; 2893 uint32_t addr = 0; 2894 2895 mem_cntl = RREG32(RADEON_MEM_CNTL); 2896 if (mem_cntl & RV100_HALF_MODE) 2897 ram /= 2; 2898 mem_size = ram; 2899 mem_cntl &= ~(0xff << 8); 2900 mem_cntl |= (mem_addr_mapping & 0xff) << 8; 2901 WREG32(RADEON_MEM_CNTL, mem_cntl); 2902 RREG32(RADEON_MEM_CNTL); 2903 2904 /* sdram reset ? */ 2905 2906 /* something like this???? */ 2907 while (ram--) { 2908 addr = ram * 1024 * 1024; 2909 /* write to each page */ 2910 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER); 2911 WREG32(RADEON_MM_DATA, 0xdeadbeef); 2912 /* read back and verify */ 2913 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER); 2914 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef) 2915 return 0; 2916 } 2917 2918 return mem_size; 2919} 2920 2921static void combios_write_ram_size(struct drm_device *dev) 2922{ 2923 struct radeon_device *rdev = dev->dev_private; 2924 uint8_t rev; 2925 uint16_t offset; 2926 uint32_t mem_size = 0; 2927 uint32_t mem_cntl = 0; 2928 2929 /* should do something smarter here I guess... */ 2930 if (rdev->flags & RADEON_IS_IGP) 2931 return; 2932 2933 /* first check detected mem table */ 2934 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE); 2935 if (offset) { 2936 rev = RBIOS8(offset); 2937 if (rev < 3) { 2938 mem_cntl = RBIOS32(offset + 1); 2939 mem_size = RBIOS16(offset + 5); 2940 if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) && 2941 ((dev->pdev->device != 0x515e) 2942 && (dev->pdev->device != 0x5969))) 2943 WREG32(RADEON_MEM_CNTL, mem_cntl); 2944 } 2945 } 2946 2947 if (!mem_size) { 2948 offset = 2949 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 2950 if (offset) { 2951 rev = RBIOS8(offset - 1); 2952 if (rev < 1) { 2953 if (((rdev->flags & RADEON_FAMILY_MASK) < 2954 CHIP_R200) 2955 && ((dev->pdev->device != 0x515e) 2956 && (dev->pdev->device != 0x5969))) { 2957 int ram = 0; 2958 int mem_addr_mapping = 0; 2959 2960 while (RBIOS8(offset)) { 2961 ram = RBIOS8(offset); 2962 mem_addr_mapping = 2963 RBIOS8(offset + 1); 2964 if (mem_addr_mapping != 0x25) 2965 ram *= 2; 2966 mem_size = 2967 combios_detect_ram(dev, ram, 2968 mem_addr_mapping); 2969 if (mem_size) 2970 break; 2971 offset += 2; 2972 } 2973 } else 2974 mem_size = RBIOS8(offset); 2975 } else { 2976 mem_size = RBIOS8(offset); 2977 mem_size *= 2; /* convert to MB */ 2978 } 2979 } 2980 } 2981 2982 mem_size *= (1024 * 1024); /* convert to bytes */ 2983 WREG32(RADEON_CONFIG_MEMSIZE, mem_size); 2984} 2985 2986void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable) 2987{ 2988 uint16_t dyn_clk_info = 2989 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); 2990 2991 if (dyn_clk_info) 2992 combios_parse_pll_table(dev, dyn_clk_info); 2993} 2994 2995void radeon_combios_asic_init(struct drm_device *dev) 2996{ 2997 struct radeon_device *rdev = dev->dev_private; 2998 uint16_t table; 2999 3000 /* port hardcoded mac stuff from radeonfb */ 3001 if (rdev->bios == NULL) 3002 return; 3003 3004 /* ASIC INIT 1 */ 3005 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE); 3006 if (table) 3007 combios_parse_mmio_table(dev, table); 3008 3009 /* PLL INIT */ 3010 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE); 3011 if (table) 3012 combios_parse_pll_table(dev, table); 3013 3014 /* ASIC INIT 2 */ 3015 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE); 3016 if (table) 3017 combios_parse_mmio_table(dev, table); 3018 3019 if (!(rdev->flags & RADEON_IS_IGP)) { 3020 /* ASIC INIT 4 */ 3021 table = 3022 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE); 3023 if (table) 3024 combios_parse_mmio_table(dev, table); 3025 3026 /* RAM RESET */ 3027 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE); 3028 if (table) 3029 combios_parse_ram_reset_table(dev, table); 3030 3031 /* ASIC INIT 3 */ 3032 table = 3033 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE); 3034 if (table) 3035 combios_parse_mmio_table(dev, table); 3036 3037 /* write CONFIG_MEMSIZE */ 3038 combios_write_ram_size(dev); 3039 } 3040 3041 /* DYN CLK 1 */ 3042 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); 3043 if (table) 3044 combios_parse_pll_table(dev, table); 3045 3046} 3047 3048void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev) 3049{ 3050 struct radeon_device *rdev = dev->dev_private; 3051 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch; 3052 3053 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 3054 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3055 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH); 3056 3057 /* let the bios control the backlight */ 3058 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; 3059 3060 /* tell the bios not to handle mode switching */ 3061 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS | 3062 RADEON_ACC_MODE_CHANGE); 3063 3064 /* tell the bios a driver is loaded */ 3065 bios_7_scratch |= RADEON_DRV_LOADED; 3066 3067 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); 3068 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3069 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch); 3070} 3071 3072void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock) 3073{ 3074 struct drm_device *dev = encoder->dev; 3075 struct radeon_device *rdev = dev->dev_private; 3076 uint32_t bios_6_scratch; 3077 3078 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3079 3080 if (lock) 3081 bios_6_scratch |= RADEON_DRIVER_CRITICAL; 3082 else 3083 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL; 3084 3085 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3086} 3087 3088void 3089radeon_combios_connected_scratch_regs(struct drm_connector *connector, 3090 struct drm_encoder *encoder, 3091 bool connected) 3092{ 3093 struct drm_device *dev = connector->dev; 3094 struct radeon_device *rdev = dev->dev_private; 3095 struct radeon_connector *radeon_connector = 3096 to_radeon_connector(connector); 3097 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3098 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH); 3099 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 3100 3101 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 3102 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 3103 if (connected) { 3104 DRM_DEBUG("TV1 connected\n"); 3105 /* fix me */ 3106 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO; 3107 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */ 3108 bios_5_scratch |= RADEON_TV1_ON; 3109 bios_5_scratch |= RADEON_ACC_REQ_TV1; 3110 } else { 3111 DRM_DEBUG("TV1 disconnected\n"); 3112 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK; 3113 bios_5_scratch &= ~RADEON_TV1_ON; 3114 bios_5_scratch &= ~RADEON_ACC_REQ_TV1; 3115 } 3116 } 3117 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 3118 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 3119 if (connected) { 3120 DRM_DEBUG("LCD1 connected\n"); 3121 bios_4_scratch |= RADEON_LCD1_ATTACHED; 3122 bios_5_scratch |= RADEON_LCD1_ON; 3123 bios_5_scratch |= RADEON_ACC_REQ_LCD1; 3124 } else { 3125 DRM_DEBUG("LCD1 disconnected\n"); 3126 bios_4_scratch &= ~RADEON_LCD1_ATTACHED; 3127 bios_5_scratch &= ~RADEON_LCD1_ON; 3128 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1; 3129 } 3130 } 3131 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 3132 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 3133 if (connected) { 3134 DRM_DEBUG("CRT1 connected\n"); 3135 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR; 3136 bios_5_scratch |= RADEON_CRT1_ON; 3137 bios_5_scratch |= RADEON_ACC_REQ_CRT1; 3138 } else { 3139 DRM_DEBUG("CRT1 disconnected\n"); 3140 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK; 3141 bios_5_scratch &= ~RADEON_CRT1_ON; 3142 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1; 3143 } 3144 } 3145 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 3146 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 3147 if (connected) { 3148 DRM_DEBUG("CRT2 connected\n"); 3149 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR; 3150 bios_5_scratch |= RADEON_CRT2_ON; 3151 bios_5_scratch |= RADEON_ACC_REQ_CRT2; 3152 } else { 3153 DRM_DEBUG("CRT2 disconnected\n"); 3154 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK; 3155 bios_5_scratch &= ~RADEON_CRT2_ON; 3156 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2; 3157 } 3158 } 3159 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 3160 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 3161 if (connected) { 3162 DRM_DEBUG("DFP1 connected\n"); 3163 bios_4_scratch |= RADEON_DFP1_ATTACHED; 3164 bios_5_scratch |= RADEON_DFP1_ON; 3165 bios_5_scratch |= RADEON_ACC_REQ_DFP1; 3166 } else { 3167 DRM_DEBUG("DFP1 disconnected\n"); 3168 bios_4_scratch &= ~RADEON_DFP1_ATTACHED; 3169 bios_5_scratch &= ~RADEON_DFP1_ON; 3170 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1; 3171 } 3172 } 3173 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 3174 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 3175 if (connected) { 3176 DRM_DEBUG("DFP2 connected\n"); 3177 bios_4_scratch |= RADEON_DFP2_ATTACHED; 3178 bios_5_scratch |= RADEON_DFP2_ON; 3179 bios_5_scratch |= RADEON_ACC_REQ_DFP2; 3180 } else { 3181 DRM_DEBUG("DFP2 disconnected\n"); 3182 bios_4_scratch &= ~RADEON_DFP2_ATTACHED; 3183 bios_5_scratch &= ~RADEON_DFP2_ON; 3184 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2; 3185 } 3186 } 3187 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch); 3188 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 3189} 3190 3191void 3192radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) 3193{ 3194 struct drm_device *dev = encoder->dev; 3195 struct radeon_device *rdev = dev->dev_private; 3196 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3197 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 3198 3199 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 3200 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK; 3201 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT); 3202 } 3203 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 3204 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK; 3205 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT); 3206 } 3207 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 3208 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK; 3209 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT); 3210 } 3211 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 3212 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK; 3213 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT); 3214 } 3215 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 3216 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK; 3217 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT); 3218 } 3219 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 3220 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK; 3221 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT); 3222 } 3223 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 3224} 3225 3226void 3227radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) 3228{ 3229 struct drm_device *dev = encoder->dev; 3230 struct radeon_device *rdev = dev->dev_private; 3231 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3232 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3233 3234 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 3235 if (on) 3236 bios_6_scratch |= RADEON_TV_DPMS_ON; 3237 else 3238 bios_6_scratch &= ~RADEON_TV_DPMS_ON; 3239 } 3240 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3241 if (on) 3242 bios_6_scratch |= RADEON_CRT_DPMS_ON; 3243 else 3244 bios_6_scratch &= ~RADEON_CRT_DPMS_ON; 3245 } 3246 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3247 if (on) 3248 bios_6_scratch |= RADEON_LCD_DPMS_ON; 3249 else 3250 bios_6_scratch &= ~RADEON_LCD_DPMS_ON; 3251 } 3252 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 3253 if (on) 3254 bios_6_scratch |= RADEON_DFP_DPMS_ON; 3255 else 3256 bios_6_scratch &= ~RADEON_DFP_DPMS_ON; 3257 } 3258 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3259} 3260