radeon_combios.c revision eed45b30cd1423f8dc10b4312700773cac13c1c8
1/* 2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario 3 * Copyright 2007-8 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 */ 27#include "drmP.h" 28#include "radeon_drm.h" 29#include "radeon.h" 30#include "atom.h" 31 32#ifdef CONFIG_PPC_PMAC 33/* not sure which of these are needed */ 34#include <asm/machdep.h> 35#include <asm/pmac_feature.h> 36#include <asm/prom.h> 37#include <asm/pci-bridge.h> 38#endif /* CONFIG_PPC_PMAC */ 39 40/* from radeon_encoder.c */ 41extern uint32_t 42radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, 43 uint8_t dac); 44extern void radeon_link_encoder_connector(struct drm_device *dev); 45 46/* from radeon_connector.c */ 47extern void 48radeon_add_legacy_connector(struct drm_device *dev, 49 uint32_t connector_id, 50 uint32_t supported_device, 51 int connector_type, 52 struct radeon_i2c_bus_rec *i2c_bus, 53 uint16_t connector_object_id, 54 struct radeon_hpd *hpd); 55 56/* from radeon_legacy_encoder.c */ 57extern void 58radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, 59 uint32_t supported_device); 60 61/* old legacy ATI BIOS routines */ 62 63/* COMBIOS table offsets */ 64enum radeon_combios_table_offset { 65 /* absolute offset tables */ 66 COMBIOS_ASIC_INIT_1_TABLE, 67 COMBIOS_BIOS_SUPPORT_TABLE, 68 COMBIOS_DAC_PROGRAMMING_TABLE, 69 COMBIOS_MAX_COLOR_DEPTH_TABLE, 70 COMBIOS_CRTC_INFO_TABLE, 71 COMBIOS_PLL_INFO_TABLE, 72 COMBIOS_TV_INFO_TABLE, 73 COMBIOS_DFP_INFO_TABLE, 74 COMBIOS_HW_CONFIG_INFO_TABLE, 75 COMBIOS_MULTIMEDIA_INFO_TABLE, 76 COMBIOS_TV_STD_PATCH_TABLE, 77 COMBIOS_LCD_INFO_TABLE, 78 COMBIOS_MOBILE_INFO_TABLE, 79 COMBIOS_PLL_INIT_TABLE, 80 COMBIOS_MEM_CONFIG_TABLE, 81 COMBIOS_SAVE_MASK_TABLE, 82 COMBIOS_HARDCODED_EDID_TABLE, 83 COMBIOS_ASIC_INIT_2_TABLE, 84 COMBIOS_CONNECTOR_INFO_TABLE, 85 COMBIOS_DYN_CLK_1_TABLE, 86 COMBIOS_RESERVED_MEM_TABLE, 87 COMBIOS_EXT_TMDS_INFO_TABLE, 88 COMBIOS_MEM_CLK_INFO_TABLE, 89 COMBIOS_EXT_DAC_INFO_TABLE, 90 COMBIOS_MISC_INFO_TABLE, 91 COMBIOS_CRT_INFO_TABLE, 92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE, 93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE, 94 COMBIOS_FAN_SPEED_INFO_TABLE, 95 COMBIOS_OVERDRIVE_INFO_TABLE, 96 COMBIOS_OEM_INFO_TABLE, 97 COMBIOS_DYN_CLK_2_TABLE, 98 COMBIOS_POWER_CONNECTOR_INFO_TABLE, 99 COMBIOS_I2C_INFO_TABLE, 100 /* relative offset tables */ 101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */ 102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */ 103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */ 104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */ 105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */ 106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */ 107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */ 108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */ 109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */ 110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */ 111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */ 112}; 113 114enum radeon_combios_ddc { 115 DDC_NONE_DETECTED, 116 DDC_MONID, 117 DDC_DVI, 118 DDC_VGA, 119 DDC_CRT2, 120 DDC_LCD, 121 DDC_GPIO, 122}; 123 124enum radeon_combios_connector { 125 CONNECTOR_NONE_LEGACY, 126 CONNECTOR_PROPRIETARY_LEGACY, 127 CONNECTOR_CRT_LEGACY, 128 CONNECTOR_DVI_I_LEGACY, 129 CONNECTOR_DVI_D_LEGACY, 130 CONNECTOR_CTV_LEGACY, 131 CONNECTOR_STV_LEGACY, 132 CONNECTOR_UNSUPPORTED_LEGACY 133}; 134 135const int legacy_connector_convert[] = { 136 DRM_MODE_CONNECTOR_Unknown, 137 DRM_MODE_CONNECTOR_DVID, 138 DRM_MODE_CONNECTOR_VGA, 139 DRM_MODE_CONNECTOR_DVII, 140 DRM_MODE_CONNECTOR_DVID, 141 DRM_MODE_CONNECTOR_Composite, 142 DRM_MODE_CONNECTOR_SVIDEO, 143 DRM_MODE_CONNECTOR_Unknown, 144}; 145 146static uint16_t combios_get_table_offset(struct drm_device *dev, 147 enum radeon_combios_table_offset table) 148{ 149 struct radeon_device *rdev = dev->dev_private; 150 int rev; 151 uint16_t offset = 0, check_offset; 152 153 switch (table) { 154 /* absolute offset tables */ 155 case COMBIOS_ASIC_INIT_1_TABLE: 156 check_offset = RBIOS16(rdev->bios_header_start + 0xc); 157 if (check_offset) 158 offset = check_offset; 159 break; 160 case COMBIOS_BIOS_SUPPORT_TABLE: 161 check_offset = RBIOS16(rdev->bios_header_start + 0x14); 162 if (check_offset) 163 offset = check_offset; 164 break; 165 case COMBIOS_DAC_PROGRAMMING_TABLE: 166 check_offset = RBIOS16(rdev->bios_header_start + 0x2a); 167 if (check_offset) 168 offset = check_offset; 169 break; 170 case COMBIOS_MAX_COLOR_DEPTH_TABLE: 171 check_offset = RBIOS16(rdev->bios_header_start + 0x2c); 172 if (check_offset) 173 offset = check_offset; 174 break; 175 case COMBIOS_CRTC_INFO_TABLE: 176 check_offset = RBIOS16(rdev->bios_header_start + 0x2e); 177 if (check_offset) 178 offset = check_offset; 179 break; 180 case COMBIOS_PLL_INFO_TABLE: 181 check_offset = RBIOS16(rdev->bios_header_start + 0x30); 182 if (check_offset) 183 offset = check_offset; 184 break; 185 case COMBIOS_TV_INFO_TABLE: 186 check_offset = RBIOS16(rdev->bios_header_start + 0x32); 187 if (check_offset) 188 offset = check_offset; 189 break; 190 case COMBIOS_DFP_INFO_TABLE: 191 check_offset = RBIOS16(rdev->bios_header_start + 0x34); 192 if (check_offset) 193 offset = check_offset; 194 break; 195 case COMBIOS_HW_CONFIG_INFO_TABLE: 196 check_offset = RBIOS16(rdev->bios_header_start + 0x36); 197 if (check_offset) 198 offset = check_offset; 199 break; 200 case COMBIOS_MULTIMEDIA_INFO_TABLE: 201 check_offset = RBIOS16(rdev->bios_header_start + 0x38); 202 if (check_offset) 203 offset = check_offset; 204 break; 205 case COMBIOS_TV_STD_PATCH_TABLE: 206 check_offset = RBIOS16(rdev->bios_header_start + 0x3e); 207 if (check_offset) 208 offset = check_offset; 209 break; 210 case COMBIOS_LCD_INFO_TABLE: 211 check_offset = RBIOS16(rdev->bios_header_start + 0x40); 212 if (check_offset) 213 offset = check_offset; 214 break; 215 case COMBIOS_MOBILE_INFO_TABLE: 216 check_offset = RBIOS16(rdev->bios_header_start + 0x42); 217 if (check_offset) 218 offset = check_offset; 219 break; 220 case COMBIOS_PLL_INIT_TABLE: 221 check_offset = RBIOS16(rdev->bios_header_start + 0x46); 222 if (check_offset) 223 offset = check_offset; 224 break; 225 case COMBIOS_MEM_CONFIG_TABLE: 226 check_offset = RBIOS16(rdev->bios_header_start + 0x48); 227 if (check_offset) 228 offset = check_offset; 229 break; 230 case COMBIOS_SAVE_MASK_TABLE: 231 check_offset = RBIOS16(rdev->bios_header_start + 0x4a); 232 if (check_offset) 233 offset = check_offset; 234 break; 235 case COMBIOS_HARDCODED_EDID_TABLE: 236 check_offset = RBIOS16(rdev->bios_header_start + 0x4c); 237 if (check_offset) 238 offset = check_offset; 239 break; 240 case COMBIOS_ASIC_INIT_2_TABLE: 241 check_offset = RBIOS16(rdev->bios_header_start + 0x4e); 242 if (check_offset) 243 offset = check_offset; 244 break; 245 case COMBIOS_CONNECTOR_INFO_TABLE: 246 check_offset = RBIOS16(rdev->bios_header_start + 0x50); 247 if (check_offset) 248 offset = check_offset; 249 break; 250 case COMBIOS_DYN_CLK_1_TABLE: 251 check_offset = RBIOS16(rdev->bios_header_start + 0x52); 252 if (check_offset) 253 offset = check_offset; 254 break; 255 case COMBIOS_RESERVED_MEM_TABLE: 256 check_offset = RBIOS16(rdev->bios_header_start + 0x54); 257 if (check_offset) 258 offset = check_offset; 259 break; 260 case COMBIOS_EXT_TMDS_INFO_TABLE: 261 check_offset = RBIOS16(rdev->bios_header_start + 0x58); 262 if (check_offset) 263 offset = check_offset; 264 break; 265 case COMBIOS_MEM_CLK_INFO_TABLE: 266 check_offset = RBIOS16(rdev->bios_header_start + 0x5a); 267 if (check_offset) 268 offset = check_offset; 269 break; 270 case COMBIOS_EXT_DAC_INFO_TABLE: 271 check_offset = RBIOS16(rdev->bios_header_start + 0x5c); 272 if (check_offset) 273 offset = check_offset; 274 break; 275 case COMBIOS_MISC_INFO_TABLE: 276 check_offset = RBIOS16(rdev->bios_header_start + 0x5e); 277 if (check_offset) 278 offset = check_offset; 279 break; 280 case COMBIOS_CRT_INFO_TABLE: 281 check_offset = RBIOS16(rdev->bios_header_start + 0x60); 282 if (check_offset) 283 offset = check_offset; 284 break; 285 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE: 286 check_offset = RBIOS16(rdev->bios_header_start + 0x62); 287 if (check_offset) 288 offset = check_offset; 289 break; 290 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE: 291 check_offset = RBIOS16(rdev->bios_header_start + 0x64); 292 if (check_offset) 293 offset = check_offset; 294 break; 295 case COMBIOS_FAN_SPEED_INFO_TABLE: 296 check_offset = RBIOS16(rdev->bios_header_start + 0x66); 297 if (check_offset) 298 offset = check_offset; 299 break; 300 case COMBIOS_OVERDRIVE_INFO_TABLE: 301 check_offset = RBIOS16(rdev->bios_header_start + 0x68); 302 if (check_offset) 303 offset = check_offset; 304 break; 305 case COMBIOS_OEM_INFO_TABLE: 306 check_offset = RBIOS16(rdev->bios_header_start + 0x6a); 307 if (check_offset) 308 offset = check_offset; 309 break; 310 case COMBIOS_DYN_CLK_2_TABLE: 311 check_offset = RBIOS16(rdev->bios_header_start + 0x6c); 312 if (check_offset) 313 offset = check_offset; 314 break; 315 case COMBIOS_POWER_CONNECTOR_INFO_TABLE: 316 check_offset = RBIOS16(rdev->bios_header_start + 0x6e); 317 if (check_offset) 318 offset = check_offset; 319 break; 320 case COMBIOS_I2C_INFO_TABLE: 321 check_offset = RBIOS16(rdev->bios_header_start + 0x70); 322 if (check_offset) 323 offset = check_offset; 324 break; 325 /* relative offset tables */ 326 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */ 327 check_offset = 328 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 329 if (check_offset) { 330 rev = RBIOS8(check_offset); 331 if (rev > 0) { 332 check_offset = RBIOS16(check_offset + 0x3); 333 if (check_offset) 334 offset = check_offset; 335 } 336 } 337 break; 338 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */ 339 check_offset = 340 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 341 if (check_offset) { 342 rev = RBIOS8(check_offset); 343 if (rev > 0) { 344 check_offset = RBIOS16(check_offset + 0x5); 345 if (check_offset) 346 offset = check_offset; 347 } 348 } 349 break; 350 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */ 351 check_offset = 352 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 353 if (check_offset) { 354 rev = RBIOS8(check_offset); 355 if (rev > 0) { 356 check_offset = RBIOS16(check_offset + 0x7); 357 if (check_offset) 358 offset = check_offset; 359 } 360 } 361 break; 362 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */ 363 check_offset = 364 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 365 if (check_offset) { 366 rev = RBIOS8(check_offset); 367 if (rev == 2) { 368 check_offset = RBIOS16(check_offset + 0x9); 369 if (check_offset) 370 offset = check_offset; 371 } 372 } 373 break; 374 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */ 375 check_offset = 376 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 377 if (check_offset) { 378 while (RBIOS8(check_offset++)); 379 check_offset += 2; 380 if (check_offset) 381 offset = check_offset; 382 } 383 break; 384 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */ 385 check_offset = 386 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 387 if (check_offset) { 388 check_offset = RBIOS16(check_offset + 0x11); 389 if (check_offset) 390 offset = check_offset; 391 } 392 break; 393 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */ 394 check_offset = 395 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 396 if (check_offset) { 397 check_offset = RBIOS16(check_offset + 0x13); 398 if (check_offset) 399 offset = check_offset; 400 } 401 break; 402 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */ 403 check_offset = 404 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 405 if (check_offset) { 406 check_offset = RBIOS16(check_offset + 0x15); 407 if (check_offset) 408 offset = check_offset; 409 } 410 break; 411 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */ 412 check_offset = 413 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 414 if (check_offset) { 415 check_offset = RBIOS16(check_offset + 0x17); 416 if (check_offset) 417 offset = check_offset; 418 } 419 break; 420 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */ 421 check_offset = 422 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 423 if (check_offset) { 424 check_offset = RBIOS16(check_offset + 0x2); 425 if (check_offset) 426 offset = check_offset; 427 } 428 break; 429 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */ 430 check_offset = 431 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 432 if (check_offset) { 433 check_offset = RBIOS16(check_offset + 0x4); 434 if (check_offset) 435 offset = check_offset; 436 } 437 break; 438 default: 439 break; 440 } 441 442 return offset; 443 444} 445 446static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev, 447 int ddc_line) 448{ 449 struct radeon_i2c_bus_rec i2c; 450 451 if (ddc_line == RADEON_GPIOPAD_MASK) { 452 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; 453 i2c.mask_data_reg = RADEON_GPIOPAD_MASK; 454 i2c.a_clk_reg = RADEON_GPIOPAD_A; 455 i2c.a_data_reg = RADEON_GPIOPAD_A; 456 i2c.en_clk_reg = RADEON_GPIOPAD_EN; 457 i2c.en_data_reg = RADEON_GPIOPAD_EN; 458 i2c.y_clk_reg = RADEON_GPIOPAD_Y; 459 i2c.y_data_reg = RADEON_GPIOPAD_Y; 460 } else if (ddc_line == RADEON_MDGPIO_MASK) { 461 i2c.mask_clk_reg = RADEON_MDGPIO_MASK; 462 i2c.mask_data_reg = RADEON_MDGPIO_MASK; 463 i2c.a_clk_reg = RADEON_MDGPIO_A; 464 i2c.a_data_reg = RADEON_MDGPIO_A; 465 i2c.en_clk_reg = RADEON_MDGPIO_EN; 466 i2c.en_data_reg = RADEON_MDGPIO_EN; 467 i2c.y_clk_reg = RADEON_MDGPIO_Y; 468 i2c.y_data_reg = RADEON_MDGPIO_Y; 469 } else { 470 i2c.mask_clk_mask = RADEON_GPIO_EN_1; 471 i2c.mask_data_mask = RADEON_GPIO_EN_0; 472 i2c.a_clk_mask = RADEON_GPIO_A_1; 473 i2c.a_data_mask = RADEON_GPIO_A_0; 474 i2c.en_clk_mask = RADEON_GPIO_EN_1; 475 i2c.en_data_mask = RADEON_GPIO_EN_0; 476 i2c.y_clk_mask = RADEON_GPIO_Y_1; 477 i2c.y_data_mask = RADEON_GPIO_Y_0; 478 479 i2c.mask_clk_reg = ddc_line; 480 i2c.mask_data_reg = ddc_line; 481 i2c.a_clk_reg = ddc_line; 482 i2c.a_data_reg = ddc_line; 483 i2c.en_clk_reg = ddc_line; 484 i2c.en_data_reg = ddc_line; 485 i2c.y_clk_reg = ddc_line; 486 i2c.y_data_reg = ddc_line; 487 } 488 489 if (rdev->family < CHIP_R200) 490 i2c.hw_capable = false; 491 else { 492 switch (ddc_line) { 493 case RADEON_GPIO_VGA_DDC: 494 case RADEON_GPIO_DVI_DDC: 495 i2c.hw_capable = true; 496 break; 497 case RADEON_GPIO_MONID: 498 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work 499 * reliably on some pre-r4xx hardware; not sure why. 500 */ 501 i2c.hw_capable = false; 502 break; 503 default: 504 i2c.hw_capable = false; 505 break; 506 } 507 } 508 i2c.mm_i2c = false; 509 i2c.i2c_id = 0; 510 511 if (ddc_line) 512 i2c.valid = true; 513 else 514 i2c.valid = false; 515 516 return i2c; 517} 518 519bool radeon_combios_get_clock_info(struct drm_device *dev) 520{ 521 struct radeon_device *rdev = dev->dev_private; 522 uint16_t pll_info; 523 struct radeon_pll *p1pll = &rdev->clock.p1pll; 524 struct radeon_pll *p2pll = &rdev->clock.p2pll; 525 struct radeon_pll *spll = &rdev->clock.spll; 526 struct radeon_pll *mpll = &rdev->clock.mpll; 527 int8_t rev; 528 uint16_t sclk, mclk; 529 530 if (rdev->bios == NULL) 531 return false; 532 533 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE); 534 if (pll_info) { 535 rev = RBIOS8(pll_info); 536 537 /* pixel clocks */ 538 p1pll->reference_freq = RBIOS16(pll_info + 0xe); 539 p1pll->reference_div = RBIOS16(pll_info + 0x10); 540 p1pll->pll_out_min = RBIOS32(pll_info + 0x12); 541 p1pll->pll_out_max = RBIOS32(pll_info + 0x16); 542 543 if (rev > 9) { 544 p1pll->pll_in_min = RBIOS32(pll_info + 0x36); 545 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a); 546 } else { 547 p1pll->pll_in_min = 40; 548 p1pll->pll_in_max = 500; 549 } 550 *p2pll = *p1pll; 551 552 /* system clock */ 553 spll->reference_freq = RBIOS16(pll_info + 0x1a); 554 spll->reference_div = RBIOS16(pll_info + 0x1c); 555 spll->pll_out_min = RBIOS32(pll_info + 0x1e); 556 spll->pll_out_max = RBIOS32(pll_info + 0x22); 557 558 if (rev > 10) { 559 spll->pll_in_min = RBIOS32(pll_info + 0x48); 560 spll->pll_in_max = RBIOS32(pll_info + 0x4c); 561 } else { 562 /* ??? */ 563 spll->pll_in_min = 40; 564 spll->pll_in_max = 500; 565 } 566 567 /* memory clock */ 568 mpll->reference_freq = RBIOS16(pll_info + 0x26); 569 mpll->reference_div = RBIOS16(pll_info + 0x28); 570 mpll->pll_out_min = RBIOS32(pll_info + 0x2a); 571 mpll->pll_out_max = RBIOS32(pll_info + 0x2e); 572 573 if (rev > 10) { 574 mpll->pll_in_min = RBIOS32(pll_info + 0x5a); 575 mpll->pll_in_max = RBIOS32(pll_info + 0x5e); 576 } else { 577 /* ??? */ 578 mpll->pll_in_min = 40; 579 mpll->pll_in_max = 500; 580 } 581 582 /* default sclk/mclk */ 583 sclk = RBIOS16(pll_info + 0xa); 584 mclk = RBIOS16(pll_info + 0x8); 585 if (sclk == 0) 586 sclk = 200 * 100; 587 if (mclk == 0) 588 mclk = 200 * 100; 589 590 rdev->clock.default_sclk = sclk; 591 rdev->clock.default_mclk = mclk; 592 593 return true; 594 } 595 return false; 596} 597 598struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct 599 radeon_encoder 600 *encoder) 601{ 602 struct drm_device *dev = encoder->base.dev; 603 struct radeon_device *rdev = dev->dev_private; 604 uint16_t dac_info; 605 uint8_t rev, bg, dac; 606 struct radeon_encoder_primary_dac *p_dac = NULL; 607 608 if (rdev->bios == NULL) 609 return NULL; 610 611 /* check CRT table */ 612 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 613 if (dac_info) { 614 p_dac = 615 kzalloc(sizeof(struct radeon_encoder_primary_dac), 616 GFP_KERNEL); 617 618 if (!p_dac) 619 return NULL; 620 621 rev = RBIOS8(dac_info) & 0x3; 622 if (rev < 2) { 623 bg = RBIOS8(dac_info + 0x2) & 0xf; 624 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf; 625 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 626 } else { 627 bg = RBIOS8(dac_info + 0x2) & 0xf; 628 dac = RBIOS8(dac_info + 0x3) & 0xf; 629 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 630 } 631 632 } 633 634 return p_dac; 635} 636 637static enum radeon_tv_std 638radeon_combios_get_tv_info(struct radeon_encoder *encoder) 639{ 640 struct drm_device *dev = encoder->base.dev; 641 struct radeon_device *rdev = dev->dev_private; 642 uint16_t tv_info; 643 enum radeon_tv_std tv_std = TV_STD_NTSC; 644 645 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 646 if (tv_info) { 647 if (RBIOS8(tv_info + 6) == 'T') { 648 switch (RBIOS8(tv_info + 7) & 0xf) { 649 case 1: 650 tv_std = TV_STD_NTSC; 651 DRM_INFO("Default TV standard: NTSC\n"); 652 break; 653 case 2: 654 tv_std = TV_STD_PAL; 655 DRM_INFO("Default TV standard: PAL\n"); 656 break; 657 case 3: 658 tv_std = TV_STD_PAL_M; 659 DRM_INFO("Default TV standard: PAL-M\n"); 660 break; 661 case 4: 662 tv_std = TV_STD_PAL_60; 663 DRM_INFO("Default TV standard: PAL-60\n"); 664 break; 665 case 5: 666 tv_std = TV_STD_NTSC_J; 667 DRM_INFO("Default TV standard: NTSC-J\n"); 668 break; 669 case 6: 670 tv_std = TV_STD_SCART_PAL; 671 DRM_INFO("Default TV standard: SCART-PAL\n"); 672 break; 673 default: 674 tv_std = TV_STD_NTSC; 675 DRM_INFO 676 ("Unknown TV standard; defaulting to NTSC\n"); 677 break; 678 } 679 680 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) { 681 case 0: 682 DRM_INFO("29.498928713 MHz TV ref clk\n"); 683 break; 684 case 1: 685 DRM_INFO("28.636360000 MHz TV ref clk\n"); 686 break; 687 case 2: 688 DRM_INFO("14.318180000 MHz TV ref clk\n"); 689 break; 690 case 3: 691 DRM_INFO("27.000000000 MHz TV ref clk\n"); 692 break; 693 default: 694 break; 695 } 696 } 697 } 698 return tv_std; 699} 700 701static const uint32_t default_tvdac_adj[CHIP_LAST] = { 702 0x00000000, /* r100 */ 703 0x00280000, /* rv100 */ 704 0x00000000, /* rs100 */ 705 0x00880000, /* rv200 */ 706 0x00000000, /* rs200 */ 707 0x00000000, /* r200 */ 708 0x00770000, /* rv250 */ 709 0x00290000, /* rs300 */ 710 0x00560000, /* rv280 */ 711 0x00780000, /* r300 */ 712 0x00770000, /* r350 */ 713 0x00780000, /* rv350 */ 714 0x00780000, /* rv380 */ 715 0x01080000, /* r420 */ 716 0x01080000, /* r423 */ 717 0x01080000, /* rv410 */ 718 0x00780000, /* rs400 */ 719 0x00780000, /* rs480 */ 720}; 721 722static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev, 723 struct radeon_encoder_tv_dac *tv_dac) 724{ 725 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family]; 726 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250)) 727 tv_dac->ps2_tvdac_adj = 0x00880000; 728 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 729 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 730 return; 731} 732 733struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct 734 radeon_encoder 735 *encoder) 736{ 737 struct drm_device *dev = encoder->base.dev; 738 struct radeon_device *rdev = dev->dev_private; 739 uint16_t dac_info; 740 uint8_t rev, bg, dac; 741 struct radeon_encoder_tv_dac *tv_dac = NULL; 742 int found = 0; 743 744 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); 745 if (!tv_dac) 746 return NULL; 747 748 if (rdev->bios == NULL) 749 goto out; 750 751 /* first check TV table */ 752 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 753 if (dac_info) { 754 rev = RBIOS8(dac_info + 0x3); 755 if (rev > 4) { 756 bg = RBIOS8(dac_info + 0xc) & 0xf; 757 dac = RBIOS8(dac_info + 0xd) & 0xf; 758 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 759 760 bg = RBIOS8(dac_info + 0xe) & 0xf; 761 dac = RBIOS8(dac_info + 0xf) & 0xf; 762 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 763 764 bg = RBIOS8(dac_info + 0x10) & 0xf; 765 dac = RBIOS8(dac_info + 0x11) & 0xf; 766 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 767 found = 1; 768 } else if (rev > 1) { 769 bg = RBIOS8(dac_info + 0xc) & 0xf; 770 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf; 771 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 772 773 bg = RBIOS8(dac_info + 0xd) & 0xf; 774 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf; 775 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 776 777 bg = RBIOS8(dac_info + 0xe) & 0xf; 778 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf; 779 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 780 found = 1; 781 } 782 tv_dac->tv_std = radeon_combios_get_tv_info(encoder); 783 } 784 if (!found) { 785 /* then check CRT table */ 786 dac_info = 787 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 788 if (dac_info) { 789 rev = RBIOS8(dac_info) & 0x3; 790 if (rev < 2) { 791 bg = RBIOS8(dac_info + 0x3) & 0xf; 792 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf; 793 tv_dac->ps2_tvdac_adj = 794 (bg << 16) | (dac << 20); 795 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 796 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 797 found = 1; 798 } else { 799 bg = RBIOS8(dac_info + 0x4) & 0xf; 800 dac = RBIOS8(dac_info + 0x5) & 0xf; 801 tv_dac->ps2_tvdac_adj = 802 (bg << 16) | (dac << 20); 803 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 804 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 805 found = 1; 806 } 807 } else { 808 DRM_INFO("No TV DAC info found in BIOS\n"); 809 } 810 } 811 812out: 813 if (!found) /* fallback to defaults */ 814 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac); 815 816 return tv_dac; 817} 818 819static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct 820 radeon_device 821 *rdev) 822{ 823 struct radeon_encoder_lvds *lvds = NULL; 824 uint32_t fp_vert_stretch, fp_horz_stretch; 825 uint32_t ppll_div_sel, ppll_val; 826 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); 827 828 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); 829 830 if (!lvds) 831 return NULL; 832 833 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH); 834 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH); 835 836 /* These should be fail-safe defaults, fingers crossed */ 837 lvds->panel_pwr_delay = 200; 838 lvds->panel_vcc_delay = 2000; 839 840 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 841 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf; 842 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf; 843 844 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) 845 lvds->native_mode.vdisplay = 846 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >> 847 RADEON_VERT_PANEL_SHIFT) + 1; 848 else 849 lvds->native_mode.vdisplay = 850 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1; 851 852 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE) 853 lvds->native_mode.hdisplay = 854 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >> 855 RADEON_HORZ_PANEL_SHIFT) + 1) * 8; 856 else 857 lvds->native_mode.hdisplay = 858 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8; 859 860 if ((lvds->native_mode.hdisplay < 640) || 861 (lvds->native_mode.vdisplay < 480)) { 862 lvds->native_mode.hdisplay = 640; 863 lvds->native_mode.vdisplay = 480; 864 } 865 866 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; 867 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel); 868 if ((ppll_val & 0x000707ff) == 0x1bb) 869 lvds->use_bios_dividers = false; 870 else { 871 lvds->panel_ref_divider = 872 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; 873 lvds->panel_post_divider = (ppll_val >> 16) & 0x7; 874 lvds->panel_fb_divider = ppll_val & 0x7ff; 875 876 if ((lvds->panel_ref_divider != 0) && 877 (lvds->panel_fb_divider > 3)) 878 lvds->use_bios_dividers = true; 879 } 880 lvds->panel_vcc_delay = 200; 881 882 DRM_INFO("Panel info derived from registers\n"); 883 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 884 lvds->native_mode.vdisplay); 885 886 return lvds; 887} 888 889struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder 890 *encoder) 891{ 892 struct drm_device *dev = encoder->base.dev; 893 struct radeon_device *rdev = dev->dev_private; 894 uint16_t lcd_info; 895 uint32_t panel_setup; 896 char stmp[30]; 897 int tmp, i; 898 struct radeon_encoder_lvds *lvds = NULL; 899 900 if (rdev->bios == NULL) { 901 lvds = radeon_legacy_get_lvds_info_from_regs(rdev); 902 goto out; 903 } 904 905 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 906 907 if (lcd_info) { 908 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); 909 910 if (!lvds) 911 return NULL; 912 913 for (i = 0; i < 24; i++) 914 stmp[i] = RBIOS8(lcd_info + i + 1); 915 stmp[24] = 0; 916 917 DRM_INFO("Panel ID String: %s\n", stmp); 918 919 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19); 920 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b); 921 922 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 923 lvds->native_mode.vdisplay); 924 925 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c); 926 if (lvds->panel_vcc_delay > 2000 || lvds->panel_vcc_delay < 0) 927 lvds->panel_vcc_delay = 2000; 928 929 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24); 930 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf; 931 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf; 932 933 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e); 934 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30); 935 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31); 936 if ((lvds->panel_ref_divider != 0) && 937 (lvds->panel_fb_divider > 3)) 938 lvds->use_bios_dividers = true; 939 940 panel_setup = RBIOS32(lcd_info + 0x39); 941 lvds->lvds_gen_cntl = 0xff00; 942 if (panel_setup & 0x1) 943 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT; 944 945 if ((panel_setup >> 4) & 0x1) 946 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE; 947 948 switch ((panel_setup >> 8) & 0x7) { 949 case 0: 950 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM; 951 break; 952 case 1: 953 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY; 954 break; 955 case 2: 956 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY; 957 break; 958 default: 959 break; 960 } 961 962 if ((panel_setup >> 16) & 0x1) 963 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW; 964 965 if ((panel_setup >> 17) & 0x1) 966 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW; 967 968 if ((panel_setup >> 18) & 0x1) 969 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW; 970 971 if ((panel_setup >> 23) & 0x1) 972 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL; 973 974 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000); 975 976 for (i = 0; i < 32; i++) { 977 tmp = RBIOS16(lcd_info + 64 + i * 2); 978 if (tmp == 0) 979 break; 980 981 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) && 982 (RBIOS16(tmp + 2) == 983 lvds->native_mode.vdisplay)) { 984 lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8; 985 lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8; 986 lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) + 987 RBIOS16(tmp + 21)) * 8; 988 989 lvds->native_mode.vtotal = RBIOS16(tmp + 24); 990 lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff; 991 lvds->native_mode.vsync_end = 992 ((RBIOS16(tmp + 28) & 0xf800) >> 11) + 993 (RBIOS16(tmp + 28) & 0x7ff); 994 995 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10; 996 lvds->native_mode.flags = 0; 997 /* set crtc values */ 998 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); 999 1000 } 1001 } 1002 } else { 1003 DRM_INFO("No panel info found in BIOS\n"); 1004 lvds = radeon_legacy_get_lvds_info_from_regs(rdev); 1005 } 1006out: 1007 if (lvds) 1008 encoder->native_mode = lvds->native_mode; 1009 return lvds; 1010} 1011 1012static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = { 1013 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */ 1014 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */ 1015 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */ 1016 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */ 1017 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */ 1018 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */ 1019 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */ 1020 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */ 1021 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */ 1022 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */ 1023 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */ 1024 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */ 1025 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */ 1026 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */ 1027 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */ 1028 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */ 1029 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */ 1030 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */ 1031}; 1032 1033bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 1034 struct radeon_encoder_int_tmds *tmds) 1035{ 1036 struct drm_device *dev = encoder->base.dev; 1037 struct radeon_device *rdev = dev->dev_private; 1038 int i; 1039 1040 for (i = 0; i < 4; i++) { 1041 tmds->tmds_pll[i].value = 1042 default_tmds_pll[rdev->family][i].value; 1043 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq; 1044 } 1045 1046 return true; 1047} 1048 1049bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 1050 struct radeon_encoder_int_tmds *tmds) 1051{ 1052 struct drm_device *dev = encoder->base.dev; 1053 struct radeon_device *rdev = dev->dev_private; 1054 uint16_t tmds_info; 1055 int i, n; 1056 uint8_t ver; 1057 1058 if (rdev->bios == NULL) 1059 return false; 1060 1061 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 1062 1063 if (tmds_info) { 1064 ver = RBIOS8(tmds_info); 1065 DRM_INFO("DFP table revision: %d\n", ver); 1066 if (ver == 3) { 1067 n = RBIOS8(tmds_info + 5) + 1; 1068 if (n > 4) 1069 n = 4; 1070 for (i = 0; i < n; i++) { 1071 tmds->tmds_pll[i].value = 1072 RBIOS32(tmds_info + i * 10 + 0x08); 1073 tmds->tmds_pll[i].freq = 1074 RBIOS16(tmds_info + i * 10 + 0x10); 1075 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n", 1076 tmds->tmds_pll[i].freq, 1077 tmds->tmds_pll[i].value); 1078 } 1079 } else if (ver == 4) { 1080 int stride = 0; 1081 n = RBIOS8(tmds_info + 5) + 1; 1082 if (n > 4) 1083 n = 4; 1084 for (i = 0; i < n; i++) { 1085 tmds->tmds_pll[i].value = 1086 RBIOS32(tmds_info + stride + 0x08); 1087 tmds->tmds_pll[i].freq = 1088 RBIOS16(tmds_info + stride + 0x10); 1089 if (i == 0) 1090 stride += 10; 1091 else 1092 stride += 6; 1093 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n", 1094 tmds->tmds_pll[i].freq, 1095 tmds->tmds_pll[i].value); 1096 } 1097 } 1098 } else { 1099 DRM_INFO("No TMDS info found in BIOS\n"); 1100 return false; 1101 } 1102 return true; 1103} 1104 1105bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 1106 struct radeon_encoder_ext_tmds *tmds) 1107{ 1108 struct drm_device *dev = encoder->base.dev; 1109 struct radeon_device *rdev = dev->dev_private; 1110 struct radeon_i2c_bus_rec i2c_bus; 1111 1112 /* default for macs */ 1113 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1114 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1115 1116 /* XXX some macs have duallink chips */ 1117 switch (rdev->mode_info.connector_table) { 1118 case CT_POWERBOOK_EXTERNAL: 1119 case CT_MINI_EXTERNAL: 1120 default: 1121 tmds->dvo_chip = DVO_SIL164; 1122 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1123 break; 1124 } 1125 1126 return true; 1127} 1128 1129bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 1130 struct radeon_encoder_ext_tmds *tmds) 1131{ 1132 struct drm_device *dev = encoder->base.dev; 1133 struct radeon_device *rdev = dev->dev_private; 1134 uint16_t offset; 1135 uint8_t ver, id, blocks, clk, data; 1136 int i; 1137 enum radeon_combios_ddc gpio; 1138 struct radeon_i2c_bus_rec i2c_bus; 1139 1140 if (rdev->bios == NULL) 1141 return false; 1142 1143 tmds->i2c_bus = NULL; 1144 if (rdev->flags & RADEON_IS_IGP) { 1145 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE); 1146 if (offset) { 1147 ver = RBIOS8(offset); 1148 DRM_INFO("GPIO Table revision: %d\n", ver); 1149 blocks = RBIOS8(offset + 2); 1150 for (i = 0; i < blocks; i++) { 1151 id = RBIOS8(offset + 3 + (i * 5) + 0); 1152 if (id == 136) { 1153 clk = RBIOS8(offset + 3 + (i * 5) + 3); 1154 data = RBIOS8(offset + 3 + (i * 5) + 4); 1155 i2c_bus.valid = true; 1156 i2c_bus.mask_clk_mask = (1 << clk); 1157 i2c_bus.mask_data_mask = (1 << data); 1158 i2c_bus.a_clk_mask = (1 << clk); 1159 i2c_bus.a_data_mask = (1 << data); 1160 i2c_bus.en_clk_mask = (1 << clk); 1161 i2c_bus.en_data_mask = (1 << data); 1162 i2c_bus.y_clk_mask = (1 << clk); 1163 i2c_bus.y_data_mask = (1 << data); 1164 i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK; 1165 i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK; 1166 i2c_bus.a_clk_reg = RADEON_GPIOPAD_A; 1167 i2c_bus.a_data_reg = RADEON_GPIOPAD_A; 1168 i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN; 1169 i2c_bus.en_data_reg = RADEON_GPIOPAD_EN; 1170 i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y; 1171 i2c_bus.y_data_reg = RADEON_GPIOPAD_Y; 1172 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1173 tmds->dvo_chip = DVO_SIL164; 1174 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1175 break; 1176 } 1177 } 1178 } 1179 } else { 1180 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 1181 if (offset) { 1182 ver = RBIOS8(offset); 1183 DRM_INFO("External TMDS Table revision: %d\n", ver); 1184 tmds->slave_addr = RBIOS8(offset + 4 + 2); 1185 tmds->slave_addr >>= 1; /* 7 bit addressing */ 1186 gpio = RBIOS8(offset + 4 + 3); 1187 switch (gpio) { 1188 case DDC_MONID: 1189 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1190 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1191 break; 1192 case DDC_DVI: 1193 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1194 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1195 break; 1196 case DDC_VGA: 1197 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1198 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1199 break; 1200 case DDC_CRT2: 1201 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */ 1202 if (rdev->family >= CHIP_R300) 1203 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1204 else 1205 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1206 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1207 break; 1208 case DDC_LCD: /* MM i2c */ 1209 DRM_ERROR("MM i2c requires hw i2c engine\n"); 1210 break; 1211 default: 1212 DRM_ERROR("Unsupported gpio %d\n", gpio); 1213 break; 1214 } 1215 } 1216 } 1217 1218 if (!tmds->i2c_bus) { 1219 DRM_INFO("No valid Ext TMDS info found in BIOS\n"); 1220 return false; 1221 } 1222 1223 return true; 1224} 1225 1226bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) 1227{ 1228 struct radeon_device *rdev = dev->dev_private; 1229 struct radeon_i2c_bus_rec ddc_i2c; 1230 struct radeon_hpd hpd; 1231 1232 rdev->mode_info.connector_table = radeon_connector_table; 1233 if (rdev->mode_info.connector_table == CT_NONE) { 1234#ifdef CONFIG_PPC_PMAC 1235 if (machine_is_compatible("PowerBook3,3")) { 1236 /* powerbook with VGA */ 1237 rdev->mode_info.connector_table = CT_POWERBOOK_VGA; 1238 } else if (machine_is_compatible("PowerBook3,4") || 1239 machine_is_compatible("PowerBook3,5")) { 1240 /* powerbook with internal tmds */ 1241 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL; 1242 } else if (machine_is_compatible("PowerBook5,1") || 1243 machine_is_compatible("PowerBook5,2") || 1244 machine_is_compatible("PowerBook5,3") || 1245 machine_is_compatible("PowerBook5,4") || 1246 machine_is_compatible("PowerBook5,5")) { 1247 /* powerbook with external single link tmds (sil164) */ 1248 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1249 } else if (machine_is_compatible("PowerBook5,6")) { 1250 /* powerbook with external dual or single link tmds */ 1251 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1252 } else if (machine_is_compatible("PowerBook5,7") || 1253 machine_is_compatible("PowerBook5,8") || 1254 machine_is_compatible("PowerBook5,9")) { 1255 /* PowerBook6,2 ? */ 1256 /* powerbook with external dual link tmds (sil1178?) */ 1257 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1258 } else if (machine_is_compatible("PowerBook4,1") || 1259 machine_is_compatible("PowerBook4,2") || 1260 machine_is_compatible("PowerBook4,3") || 1261 machine_is_compatible("PowerBook6,3") || 1262 machine_is_compatible("PowerBook6,5") || 1263 machine_is_compatible("PowerBook6,7")) { 1264 /* ibook */ 1265 rdev->mode_info.connector_table = CT_IBOOK; 1266 } else if (machine_is_compatible("PowerMac4,4")) { 1267 /* emac */ 1268 rdev->mode_info.connector_table = CT_EMAC; 1269 } else if (machine_is_compatible("PowerMac10,1")) { 1270 /* mini with internal tmds */ 1271 rdev->mode_info.connector_table = CT_MINI_INTERNAL; 1272 } else if (machine_is_compatible("PowerMac10,2")) { 1273 /* mini with external tmds */ 1274 rdev->mode_info.connector_table = CT_MINI_EXTERNAL; 1275 } else if (machine_is_compatible("PowerMac12,1")) { 1276 /* PowerMac8,1 ? */ 1277 /* imac g5 isight */ 1278 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT; 1279 } else 1280#endif /* CONFIG_PPC_PMAC */ 1281 rdev->mode_info.connector_table = CT_GENERIC; 1282 } 1283 1284 switch (rdev->mode_info.connector_table) { 1285 case CT_GENERIC: 1286 DRM_INFO("Connector Table: %d (generic)\n", 1287 rdev->mode_info.connector_table); 1288 /* these are the most common settings */ 1289 if (rdev->flags & RADEON_SINGLE_CRTC) { 1290 /* VGA - primary dac */ 1291 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1292 hpd.hpd = RADEON_HPD_NONE; 1293 radeon_add_legacy_encoder(dev, 1294 radeon_get_encoder_id(dev, 1295 ATOM_DEVICE_CRT1_SUPPORT, 1296 1), 1297 ATOM_DEVICE_CRT1_SUPPORT); 1298 radeon_add_legacy_connector(dev, 0, 1299 ATOM_DEVICE_CRT1_SUPPORT, 1300 DRM_MODE_CONNECTOR_VGA, 1301 &ddc_i2c, 1302 CONNECTOR_OBJECT_ID_VGA, 1303 &hpd); 1304 } else if (rdev->flags & RADEON_IS_MOBILITY) { 1305 /* LVDS */ 1306 ddc_i2c = combios_setup_i2c_bus(rdev, 0); 1307 hpd.hpd = RADEON_HPD_NONE; 1308 radeon_add_legacy_encoder(dev, 1309 radeon_get_encoder_id(dev, 1310 ATOM_DEVICE_LCD1_SUPPORT, 1311 0), 1312 ATOM_DEVICE_LCD1_SUPPORT); 1313 radeon_add_legacy_connector(dev, 0, 1314 ATOM_DEVICE_LCD1_SUPPORT, 1315 DRM_MODE_CONNECTOR_LVDS, 1316 &ddc_i2c, 1317 CONNECTOR_OBJECT_ID_LVDS, 1318 &hpd); 1319 1320 /* VGA - primary dac */ 1321 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1322 hpd.hpd = RADEON_HPD_NONE; 1323 radeon_add_legacy_encoder(dev, 1324 radeon_get_encoder_id(dev, 1325 ATOM_DEVICE_CRT1_SUPPORT, 1326 1), 1327 ATOM_DEVICE_CRT1_SUPPORT); 1328 radeon_add_legacy_connector(dev, 1, 1329 ATOM_DEVICE_CRT1_SUPPORT, 1330 DRM_MODE_CONNECTOR_VGA, 1331 &ddc_i2c, 1332 CONNECTOR_OBJECT_ID_VGA, 1333 &hpd); 1334 } else { 1335 /* DVI-I - tv dac, int tmds */ 1336 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1337 hpd.hpd = RADEON_HPD_1; 1338 radeon_add_legacy_encoder(dev, 1339 radeon_get_encoder_id(dev, 1340 ATOM_DEVICE_DFP1_SUPPORT, 1341 0), 1342 ATOM_DEVICE_DFP1_SUPPORT); 1343 radeon_add_legacy_encoder(dev, 1344 radeon_get_encoder_id(dev, 1345 ATOM_DEVICE_CRT2_SUPPORT, 1346 2), 1347 ATOM_DEVICE_CRT2_SUPPORT); 1348 radeon_add_legacy_connector(dev, 0, 1349 ATOM_DEVICE_DFP1_SUPPORT | 1350 ATOM_DEVICE_CRT2_SUPPORT, 1351 DRM_MODE_CONNECTOR_DVII, 1352 &ddc_i2c, 1353 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1354 &hpd); 1355 1356 /* VGA - primary dac */ 1357 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1358 hpd.hpd = RADEON_HPD_NONE; 1359 radeon_add_legacy_encoder(dev, 1360 radeon_get_encoder_id(dev, 1361 ATOM_DEVICE_CRT1_SUPPORT, 1362 1), 1363 ATOM_DEVICE_CRT1_SUPPORT); 1364 radeon_add_legacy_connector(dev, 1, 1365 ATOM_DEVICE_CRT1_SUPPORT, 1366 DRM_MODE_CONNECTOR_VGA, 1367 &ddc_i2c, 1368 CONNECTOR_OBJECT_ID_VGA, 1369 &hpd); 1370 } 1371 1372 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 1373 /* TV - tv dac */ 1374 ddc_i2c.valid = false; 1375 hpd.hpd = RADEON_HPD_NONE; 1376 radeon_add_legacy_encoder(dev, 1377 radeon_get_encoder_id(dev, 1378 ATOM_DEVICE_TV1_SUPPORT, 1379 2), 1380 ATOM_DEVICE_TV1_SUPPORT); 1381 radeon_add_legacy_connector(dev, 2, 1382 ATOM_DEVICE_TV1_SUPPORT, 1383 DRM_MODE_CONNECTOR_SVIDEO, 1384 &ddc_i2c, 1385 CONNECTOR_OBJECT_ID_SVIDEO, 1386 &hpd); 1387 } 1388 break; 1389 case CT_IBOOK: 1390 DRM_INFO("Connector Table: %d (ibook)\n", 1391 rdev->mode_info.connector_table); 1392 /* LVDS */ 1393 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1394 hpd.hpd = RADEON_HPD_NONE; 1395 radeon_add_legacy_encoder(dev, 1396 radeon_get_encoder_id(dev, 1397 ATOM_DEVICE_LCD1_SUPPORT, 1398 0), 1399 ATOM_DEVICE_LCD1_SUPPORT); 1400 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1401 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1402 CONNECTOR_OBJECT_ID_LVDS, 1403 &hpd); 1404 /* VGA - TV DAC */ 1405 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1406 hpd.hpd = RADEON_HPD_NONE; 1407 radeon_add_legacy_encoder(dev, 1408 radeon_get_encoder_id(dev, 1409 ATOM_DEVICE_CRT2_SUPPORT, 1410 2), 1411 ATOM_DEVICE_CRT2_SUPPORT); 1412 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1413 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1414 CONNECTOR_OBJECT_ID_VGA, 1415 &hpd); 1416 /* TV - TV DAC */ 1417 ddc_i2c.valid = false; 1418 hpd.hpd = RADEON_HPD_NONE; 1419 radeon_add_legacy_encoder(dev, 1420 radeon_get_encoder_id(dev, 1421 ATOM_DEVICE_TV1_SUPPORT, 1422 2), 1423 ATOM_DEVICE_TV1_SUPPORT); 1424 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1425 DRM_MODE_CONNECTOR_SVIDEO, 1426 &ddc_i2c, 1427 CONNECTOR_OBJECT_ID_SVIDEO, 1428 &hpd); 1429 break; 1430 case CT_POWERBOOK_EXTERNAL: 1431 DRM_INFO("Connector Table: %d (powerbook external tmds)\n", 1432 rdev->mode_info.connector_table); 1433 /* LVDS */ 1434 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1435 hpd.hpd = RADEON_HPD_NONE; 1436 radeon_add_legacy_encoder(dev, 1437 radeon_get_encoder_id(dev, 1438 ATOM_DEVICE_LCD1_SUPPORT, 1439 0), 1440 ATOM_DEVICE_LCD1_SUPPORT); 1441 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1442 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1443 CONNECTOR_OBJECT_ID_LVDS, 1444 &hpd); 1445 /* DVI-I - primary dac, ext tmds */ 1446 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1447 hpd.hpd = RADEON_HPD_2; /* ??? */ 1448 radeon_add_legacy_encoder(dev, 1449 radeon_get_encoder_id(dev, 1450 ATOM_DEVICE_DFP2_SUPPORT, 1451 0), 1452 ATOM_DEVICE_DFP2_SUPPORT); 1453 radeon_add_legacy_encoder(dev, 1454 radeon_get_encoder_id(dev, 1455 ATOM_DEVICE_CRT1_SUPPORT, 1456 1), 1457 ATOM_DEVICE_CRT1_SUPPORT); 1458 /* XXX some are SL */ 1459 radeon_add_legacy_connector(dev, 1, 1460 ATOM_DEVICE_DFP2_SUPPORT | 1461 ATOM_DEVICE_CRT1_SUPPORT, 1462 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1463 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, 1464 &hpd); 1465 /* TV - TV DAC */ 1466 ddc_i2c.valid = false; 1467 hpd.hpd = RADEON_HPD_NONE; 1468 radeon_add_legacy_encoder(dev, 1469 radeon_get_encoder_id(dev, 1470 ATOM_DEVICE_TV1_SUPPORT, 1471 2), 1472 ATOM_DEVICE_TV1_SUPPORT); 1473 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1474 DRM_MODE_CONNECTOR_SVIDEO, 1475 &ddc_i2c, 1476 CONNECTOR_OBJECT_ID_SVIDEO, 1477 &hpd); 1478 break; 1479 case CT_POWERBOOK_INTERNAL: 1480 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n", 1481 rdev->mode_info.connector_table); 1482 /* LVDS */ 1483 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1484 hpd.hpd = RADEON_HPD_NONE; 1485 radeon_add_legacy_encoder(dev, 1486 radeon_get_encoder_id(dev, 1487 ATOM_DEVICE_LCD1_SUPPORT, 1488 0), 1489 ATOM_DEVICE_LCD1_SUPPORT); 1490 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1491 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1492 CONNECTOR_OBJECT_ID_LVDS, 1493 &hpd); 1494 /* DVI-I - primary dac, int tmds */ 1495 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1496 hpd.hpd = RADEON_HPD_1; /* ??? */ 1497 radeon_add_legacy_encoder(dev, 1498 radeon_get_encoder_id(dev, 1499 ATOM_DEVICE_DFP1_SUPPORT, 1500 0), 1501 ATOM_DEVICE_DFP1_SUPPORT); 1502 radeon_add_legacy_encoder(dev, 1503 radeon_get_encoder_id(dev, 1504 ATOM_DEVICE_CRT1_SUPPORT, 1505 1), 1506 ATOM_DEVICE_CRT1_SUPPORT); 1507 radeon_add_legacy_connector(dev, 1, 1508 ATOM_DEVICE_DFP1_SUPPORT | 1509 ATOM_DEVICE_CRT1_SUPPORT, 1510 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1511 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1512 &hpd); 1513 /* TV - TV DAC */ 1514 ddc_i2c.valid = false; 1515 hpd.hpd = RADEON_HPD_NONE; 1516 radeon_add_legacy_encoder(dev, 1517 radeon_get_encoder_id(dev, 1518 ATOM_DEVICE_TV1_SUPPORT, 1519 2), 1520 ATOM_DEVICE_TV1_SUPPORT); 1521 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1522 DRM_MODE_CONNECTOR_SVIDEO, 1523 &ddc_i2c, 1524 CONNECTOR_OBJECT_ID_SVIDEO, 1525 &hpd); 1526 break; 1527 case CT_POWERBOOK_VGA: 1528 DRM_INFO("Connector Table: %d (powerbook vga)\n", 1529 rdev->mode_info.connector_table); 1530 /* LVDS */ 1531 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1532 hpd.hpd = RADEON_HPD_NONE; 1533 radeon_add_legacy_encoder(dev, 1534 radeon_get_encoder_id(dev, 1535 ATOM_DEVICE_LCD1_SUPPORT, 1536 0), 1537 ATOM_DEVICE_LCD1_SUPPORT); 1538 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1539 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1540 CONNECTOR_OBJECT_ID_LVDS, 1541 &hpd); 1542 /* VGA - primary dac */ 1543 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1544 hpd.hpd = RADEON_HPD_NONE; 1545 radeon_add_legacy_encoder(dev, 1546 radeon_get_encoder_id(dev, 1547 ATOM_DEVICE_CRT1_SUPPORT, 1548 1), 1549 ATOM_DEVICE_CRT1_SUPPORT); 1550 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, 1551 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1552 CONNECTOR_OBJECT_ID_VGA, 1553 &hpd); 1554 /* TV - TV DAC */ 1555 ddc_i2c.valid = false; 1556 hpd.hpd = RADEON_HPD_NONE; 1557 radeon_add_legacy_encoder(dev, 1558 radeon_get_encoder_id(dev, 1559 ATOM_DEVICE_TV1_SUPPORT, 1560 2), 1561 ATOM_DEVICE_TV1_SUPPORT); 1562 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1563 DRM_MODE_CONNECTOR_SVIDEO, 1564 &ddc_i2c, 1565 CONNECTOR_OBJECT_ID_SVIDEO, 1566 &hpd); 1567 break; 1568 case CT_MINI_EXTERNAL: 1569 DRM_INFO("Connector Table: %d (mini external tmds)\n", 1570 rdev->mode_info.connector_table); 1571 /* DVI-I - tv dac, ext tmds */ 1572 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1573 hpd.hpd = RADEON_HPD_2; /* ??? */ 1574 radeon_add_legacy_encoder(dev, 1575 radeon_get_encoder_id(dev, 1576 ATOM_DEVICE_DFP2_SUPPORT, 1577 0), 1578 ATOM_DEVICE_DFP2_SUPPORT); 1579 radeon_add_legacy_encoder(dev, 1580 radeon_get_encoder_id(dev, 1581 ATOM_DEVICE_CRT2_SUPPORT, 1582 2), 1583 ATOM_DEVICE_CRT2_SUPPORT); 1584 /* XXX are any DL? */ 1585 radeon_add_legacy_connector(dev, 0, 1586 ATOM_DEVICE_DFP2_SUPPORT | 1587 ATOM_DEVICE_CRT2_SUPPORT, 1588 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1589 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1590 &hpd); 1591 /* TV - TV DAC */ 1592 ddc_i2c.valid = false; 1593 hpd.hpd = RADEON_HPD_NONE; 1594 radeon_add_legacy_encoder(dev, 1595 radeon_get_encoder_id(dev, 1596 ATOM_DEVICE_TV1_SUPPORT, 1597 2), 1598 ATOM_DEVICE_TV1_SUPPORT); 1599 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1600 DRM_MODE_CONNECTOR_SVIDEO, 1601 &ddc_i2c, 1602 CONNECTOR_OBJECT_ID_SVIDEO, 1603 &hpd); 1604 break; 1605 case CT_MINI_INTERNAL: 1606 DRM_INFO("Connector Table: %d (mini internal tmds)\n", 1607 rdev->mode_info.connector_table); 1608 /* DVI-I - tv dac, int tmds */ 1609 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1610 hpd.hpd = RADEON_HPD_1; /* ??? */ 1611 radeon_add_legacy_encoder(dev, 1612 radeon_get_encoder_id(dev, 1613 ATOM_DEVICE_DFP1_SUPPORT, 1614 0), 1615 ATOM_DEVICE_DFP1_SUPPORT); 1616 radeon_add_legacy_encoder(dev, 1617 radeon_get_encoder_id(dev, 1618 ATOM_DEVICE_CRT2_SUPPORT, 1619 2), 1620 ATOM_DEVICE_CRT2_SUPPORT); 1621 radeon_add_legacy_connector(dev, 0, 1622 ATOM_DEVICE_DFP1_SUPPORT | 1623 ATOM_DEVICE_CRT2_SUPPORT, 1624 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1625 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1626 &hpd); 1627 /* TV - TV DAC */ 1628 ddc_i2c.valid = false; 1629 hpd.hpd = RADEON_HPD_NONE; 1630 radeon_add_legacy_encoder(dev, 1631 radeon_get_encoder_id(dev, 1632 ATOM_DEVICE_TV1_SUPPORT, 1633 2), 1634 ATOM_DEVICE_TV1_SUPPORT); 1635 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1636 DRM_MODE_CONNECTOR_SVIDEO, 1637 &ddc_i2c, 1638 CONNECTOR_OBJECT_ID_SVIDEO, 1639 &hpd); 1640 break; 1641 case CT_IMAC_G5_ISIGHT: 1642 DRM_INFO("Connector Table: %d (imac g5 isight)\n", 1643 rdev->mode_info.connector_table); 1644 /* DVI-D - int tmds */ 1645 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1646 hpd.hpd = RADEON_HPD_1; /* ??? */ 1647 radeon_add_legacy_encoder(dev, 1648 radeon_get_encoder_id(dev, 1649 ATOM_DEVICE_DFP1_SUPPORT, 1650 0), 1651 ATOM_DEVICE_DFP1_SUPPORT); 1652 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT, 1653 DRM_MODE_CONNECTOR_DVID, &ddc_i2c, 1654 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 1655 &hpd); 1656 /* VGA - tv dac */ 1657 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1658 hpd.hpd = RADEON_HPD_NONE; 1659 radeon_add_legacy_encoder(dev, 1660 radeon_get_encoder_id(dev, 1661 ATOM_DEVICE_CRT2_SUPPORT, 1662 2), 1663 ATOM_DEVICE_CRT2_SUPPORT); 1664 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1665 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1666 CONNECTOR_OBJECT_ID_VGA, 1667 &hpd); 1668 /* TV - TV DAC */ 1669 ddc_i2c.valid = false; 1670 hpd.hpd = RADEON_HPD_NONE; 1671 radeon_add_legacy_encoder(dev, 1672 radeon_get_encoder_id(dev, 1673 ATOM_DEVICE_TV1_SUPPORT, 1674 2), 1675 ATOM_DEVICE_TV1_SUPPORT); 1676 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1677 DRM_MODE_CONNECTOR_SVIDEO, 1678 &ddc_i2c, 1679 CONNECTOR_OBJECT_ID_SVIDEO, 1680 &hpd); 1681 break; 1682 case CT_EMAC: 1683 DRM_INFO("Connector Table: %d (emac)\n", 1684 rdev->mode_info.connector_table); 1685 /* VGA - primary dac */ 1686 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1687 hpd.hpd = RADEON_HPD_NONE; 1688 radeon_add_legacy_encoder(dev, 1689 radeon_get_encoder_id(dev, 1690 ATOM_DEVICE_CRT1_SUPPORT, 1691 1), 1692 ATOM_DEVICE_CRT1_SUPPORT); 1693 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, 1694 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1695 CONNECTOR_OBJECT_ID_VGA, 1696 &hpd); 1697 /* VGA - tv dac */ 1698 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1699 hpd.hpd = RADEON_HPD_NONE; 1700 radeon_add_legacy_encoder(dev, 1701 radeon_get_encoder_id(dev, 1702 ATOM_DEVICE_CRT2_SUPPORT, 1703 2), 1704 ATOM_DEVICE_CRT2_SUPPORT); 1705 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1706 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1707 CONNECTOR_OBJECT_ID_VGA, 1708 &hpd); 1709 /* TV - TV DAC */ 1710 ddc_i2c.valid = false; 1711 hpd.hpd = RADEON_HPD_NONE; 1712 radeon_add_legacy_encoder(dev, 1713 radeon_get_encoder_id(dev, 1714 ATOM_DEVICE_TV1_SUPPORT, 1715 2), 1716 ATOM_DEVICE_TV1_SUPPORT); 1717 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1718 DRM_MODE_CONNECTOR_SVIDEO, 1719 &ddc_i2c, 1720 CONNECTOR_OBJECT_ID_SVIDEO, 1721 &hpd); 1722 break; 1723 default: 1724 DRM_INFO("Connector table: %d (invalid)\n", 1725 rdev->mode_info.connector_table); 1726 return false; 1727 } 1728 1729 radeon_link_encoder_connector(dev); 1730 1731 return true; 1732} 1733 1734static bool radeon_apply_legacy_quirks(struct drm_device *dev, 1735 int bios_index, 1736 enum radeon_combios_connector 1737 *legacy_connector, 1738 struct radeon_i2c_bus_rec *ddc_i2c, 1739 struct radeon_hpd *hpd) 1740{ 1741 struct radeon_device *rdev = dev->dev_private; 1742 1743 /* XPRESS DDC quirks */ 1744 if ((rdev->family == CHIP_RS400 || 1745 rdev->family == CHIP_RS480) && 1746 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) 1747 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1748 else if ((rdev->family == CHIP_RS400 || 1749 rdev->family == CHIP_RS480) && 1750 ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) { 1751 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK); 1752 ddc_i2c->mask_clk_mask = (0x20 << 8); 1753 ddc_i2c->mask_data_mask = 0x80; 1754 ddc_i2c->a_clk_mask = (0x20 << 8); 1755 ddc_i2c->a_data_mask = 0x80; 1756 ddc_i2c->en_clk_mask = (0x20 << 8); 1757 ddc_i2c->en_data_mask = 0x80; 1758 ddc_i2c->y_clk_mask = (0x20 << 8); 1759 ddc_i2c->y_data_mask = 0x80; 1760 } 1761 1762 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */ 1763 if ((rdev->family >= CHIP_R300) && 1764 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) 1765 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1766 1767 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, 1768 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ 1769 if (dev->pdev->device == 0x515e && 1770 dev->pdev->subsystem_vendor == 0x1014) { 1771 if (*legacy_connector == CONNECTOR_CRT_LEGACY && 1772 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) 1773 return false; 1774 } 1775 1776 /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */ 1777 if (dev->pdev->device == 0x5159 && 1778 dev->pdev->subsystem_vendor == 0x1002 && 1779 dev->pdev->subsystem_device == 0x013a) { 1780 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY) 1781 *legacy_connector = CONNECTOR_CRT_LEGACY; 1782 1783 } 1784 1785 /* X300 card with extra non-existent DVI port */ 1786 if (dev->pdev->device == 0x5B60 && 1787 dev->pdev->subsystem_vendor == 0x17af && 1788 dev->pdev->subsystem_device == 0x201e && bios_index == 2) { 1789 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY) 1790 return false; 1791 } 1792 1793 return true; 1794} 1795 1796static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev) 1797{ 1798 /* Acer 5102 has non-existent TV port */ 1799 if (dev->pdev->device == 0x5975 && 1800 dev->pdev->subsystem_vendor == 0x1025 && 1801 dev->pdev->subsystem_device == 0x009f) 1802 return false; 1803 1804 /* HP dc5750 has non-existent TV port */ 1805 if (dev->pdev->device == 0x5974 && 1806 dev->pdev->subsystem_vendor == 0x103c && 1807 dev->pdev->subsystem_device == 0x280a) 1808 return false; 1809 1810 /* MSI S270 has non-existent TV port */ 1811 if (dev->pdev->device == 0x5955 && 1812 dev->pdev->subsystem_vendor == 0x1462 && 1813 dev->pdev->subsystem_device == 0x0131) 1814 return false; 1815 1816 return true; 1817} 1818 1819static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d) 1820{ 1821 struct radeon_device *rdev = dev->dev_private; 1822 uint32_t ext_tmds_info; 1823 1824 if (rdev->flags & RADEON_IS_IGP) { 1825 if (is_dvi_d) 1826 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 1827 else 1828 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 1829 } 1830 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 1831 if (ext_tmds_info) { 1832 uint8_t rev = RBIOS8(ext_tmds_info); 1833 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5); 1834 if (rev >= 3) { 1835 if (is_dvi_d) 1836 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 1837 else 1838 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 1839 } else { 1840 if (flags & 1) { 1841 if (is_dvi_d) 1842 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 1843 else 1844 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 1845 } 1846 } 1847 } 1848 if (is_dvi_d) 1849 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 1850 else 1851 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 1852} 1853 1854bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) 1855{ 1856 struct radeon_device *rdev = dev->dev_private; 1857 uint32_t conn_info, entry, devices; 1858 uint16_t tmp, connector_object_id; 1859 enum radeon_combios_ddc ddc_type; 1860 enum radeon_combios_connector connector; 1861 int i = 0; 1862 struct radeon_i2c_bus_rec ddc_i2c; 1863 struct radeon_hpd hpd; 1864 1865 if (rdev->bios == NULL) 1866 return false; 1867 1868 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE); 1869 if (conn_info) { 1870 for (i = 0; i < 4; i++) { 1871 entry = conn_info + 2 + i * 2; 1872 1873 if (!RBIOS16(entry)) 1874 break; 1875 1876 tmp = RBIOS16(entry); 1877 1878 connector = (tmp >> 12) & 0xf; 1879 1880 ddc_type = (tmp >> 8) & 0xf; 1881 switch (ddc_type) { 1882 case DDC_MONID: 1883 ddc_i2c = 1884 combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1885 break; 1886 case DDC_DVI: 1887 ddc_i2c = 1888 combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1889 break; 1890 case DDC_VGA: 1891 ddc_i2c = 1892 combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1893 break; 1894 case DDC_CRT2: 1895 ddc_i2c = 1896 combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1897 break; 1898 default: 1899 break; 1900 } 1901 1902 switch (connector) { 1903 case CONNECTOR_PROPRIETARY_LEGACY: 1904 case CONNECTOR_DVI_I_LEGACY: 1905 case CONNECTOR_DVI_D_LEGACY: 1906 if ((tmp >> 4) & 0x1) 1907 hpd.hpd = RADEON_HPD_2; 1908 else 1909 hpd.hpd = RADEON_HPD_1; 1910 break; 1911 default: 1912 hpd.hpd = RADEON_HPD_NONE; 1913 break; 1914 } 1915 1916 if (!radeon_apply_legacy_quirks(dev, i, &connector, 1917 &ddc_i2c, &hpd)) 1918 continue; 1919 1920 switch (connector) { 1921 case CONNECTOR_PROPRIETARY_LEGACY: 1922 if ((tmp >> 4) & 0x1) 1923 devices = ATOM_DEVICE_DFP2_SUPPORT; 1924 else 1925 devices = ATOM_DEVICE_DFP1_SUPPORT; 1926 radeon_add_legacy_encoder(dev, 1927 radeon_get_encoder_id 1928 (dev, devices, 0), 1929 devices); 1930 radeon_add_legacy_connector(dev, i, devices, 1931 legacy_connector_convert 1932 [connector], 1933 &ddc_i2c, 1934 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 1935 &hpd); 1936 break; 1937 case CONNECTOR_CRT_LEGACY: 1938 if (tmp & 0x1) { 1939 devices = ATOM_DEVICE_CRT2_SUPPORT; 1940 radeon_add_legacy_encoder(dev, 1941 radeon_get_encoder_id 1942 (dev, 1943 ATOM_DEVICE_CRT2_SUPPORT, 1944 2), 1945 ATOM_DEVICE_CRT2_SUPPORT); 1946 } else { 1947 devices = ATOM_DEVICE_CRT1_SUPPORT; 1948 radeon_add_legacy_encoder(dev, 1949 radeon_get_encoder_id 1950 (dev, 1951 ATOM_DEVICE_CRT1_SUPPORT, 1952 1), 1953 ATOM_DEVICE_CRT1_SUPPORT); 1954 } 1955 radeon_add_legacy_connector(dev, 1956 i, 1957 devices, 1958 legacy_connector_convert 1959 [connector], 1960 &ddc_i2c, 1961 CONNECTOR_OBJECT_ID_VGA, 1962 &hpd); 1963 break; 1964 case CONNECTOR_DVI_I_LEGACY: 1965 devices = 0; 1966 if (tmp & 0x1) { 1967 devices |= ATOM_DEVICE_CRT2_SUPPORT; 1968 radeon_add_legacy_encoder(dev, 1969 radeon_get_encoder_id 1970 (dev, 1971 ATOM_DEVICE_CRT2_SUPPORT, 1972 2), 1973 ATOM_DEVICE_CRT2_SUPPORT); 1974 } else { 1975 devices |= ATOM_DEVICE_CRT1_SUPPORT; 1976 radeon_add_legacy_encoder(dev, 1977 radeon_get_encoder_id 1978 (dev, 1979 ATOM_DEVICE_CRT1_SUPPORT, 1980 1), 1981 ATOM_DEVICE_CRT1_SUPPORT); 1982 } 1983 if ((tmp >> 4) & 0x1) { 1984 devices |= ATOM_DEVICE_DFP2_SUPPORT; 1985 radeon_add_legacy_encoder(dev, 1986 radeon_get_encoder_id 1987 (dev, 1988 ATOM_DEVICE_DFP2_SUPPORT, 1989 0), 1990 ATOM_DEVICE_DFP2_SUPPORT); 1991 connector_object_id = combios_check_dl_dvi(dev, 0); 1992 } else { 1993 devices |= ATOM_DEVICE_DFP1_SUPPORT; 1994 radeon_add_legacy_encoder(dev, 1995 radeon_get_encoder_id 1996 (dev, 1997 ATOM_DEVICE_DFP1_SUPPORT, 1998 0), 1999 ATOM_DEVICE_DFP1_SUPPORT); 2000 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2001 } 2002 radeon_add_legacy_connector(dev, 2003 i, 2004 devices, 2005 legacy_connector_convert 2006 [connector], 2007 &ddc_i2c, 2008 connector_object_id, 2009 &hpd); 2010 break; 2011 case CONNECTOR_DVI_D_LEGACY: 2012 if ((tmp >> 4) & 0x1) { 2013 devices = ATOM_DEVICE_DFP2_SUPPORT; 2014 connector_object_id = combios_check_dl_dvi(dev, 1); 2015 } else { 2016 devices = ATOM_DEVICE_DFP1_SUPPORT; 2017 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2018 } 2019 radeon_add_legacy_encoder(dev, 2020 radeon_get_encoder_id 2021 (dev, devices, 0), 2022 devices); 2023 radeon_add_legacy_connector(dev, i, devices, 2024 legacy_connector_convert 2025 [connector], 2026 &ddc_i2c, 2027 connector_object_id, 2028 &hpd); 2029 break; 2030 case CONNECTOR_CTV_LEGACY: 2031 case CONNECTOR_STV_LEGACY: 2032 radeon_add_legacy_encoder(dev, 2033 radeon_get_encoder_id 2034 (dev, 2035 ATOM_DEVICE_TV1_SUPPORT, 2036 2), 2037 ATOM_DEVICE_TV1_SUPPORT); 2038 radeon_add_legacy_connector(dev, i, 2039 ATOM_DEVICE_TV1_SUPPORT, 2040 legacy_connector_convert 2041 [connector], 2042 &ddc_i2c, 2043 CONNECTOR_OBJECT_ID_SVIDEO, 2044 &hpd); 2045 break; 2046 default: 2047 DRM_ERROR("Unknown connector type: %d\n", 2048 connector); 2049 continue; 2050 } 2051 2052 } 2053 } else { 2054 uint16_t tmds_info = 2055 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 2056 if (tmds_info) { 2057 DRM_DEBUG("Found DFP table, assuming DVI connector\n"); 2058 2059 radeon_add_legacy_encoder(dev, 2060 radeon_get_encoder_id(dev, 2061 ATOM_DEVICE_CRT1_SUPPORT, 2062 1), 2063 ATOM_DEVICE_CRT1_SUPPORT); 2064 radeon_add_legacy_encoder(dev, 2065 radeon_get_encoder_id(dev, 2066 ATOM_DEVICE_DFP1_SUPPORT, 2067 0), 2068 ATOM_DEVICE_DFP1_SUPPORT); 2069 2070 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 2071 hpd.hpd = RADEON_HPD_NONE; 2072 radeon_add_legacy_connector(dev, 2073 0, 2074 ATOM_DEVICE_CRT1_SUPPORT | 2075 ATOM_DEVICE_DFP1_SUPPORT, 2076 DRM_MODE_CONNECTOR_DVII, 2077 &ddc_i2c, 2078 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2079 &hpd); 2080 } else { 2081 uint16_t crt_info = 2082 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 2083 DRM_DEBUG("Found CRT table, assuming VGA connector\n"); 2084 if (crt_info) { 2085 radeon_add_legacy_encoder(dev, 2086 radeon_get_encoder_id(dev, 2087 ATOM_DEVICE_CRT1_SUPPORT, 2088 1), 2089 ATOM_DEVICE_CRT1_SUPPORT); 2090 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 2091 hpd.hpd = RADEON_HPD_NONE; 2092 radeon_add_legacy_connector(dev, 2093 0, 2094 ATOM_DEVICE_CRT1_SUPPORT, 2095 DRM_MODE_CONNECTOR_VGA, 2096 &ddc_i2c, 2097 CONNECTOR_OBJECT_ID_VGA, 2098 &hpd); 2099 } else { 2100 DRM_DEBUG("No connector info found\n"); 2101 return false; 2102 } 2103 } 2104 } 2105 2106 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) { 2107 uint16_t lcd_info = 2108 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 2109 if (lcd_info) { 2110 uint16_t lcd_ddc_info = 2111 combios_get_table_offset(dev, 2112 COMBIOS_LCD_DDC_INFO_TABLE); 2113 2114 radeon_add_legacy_encoder(dev, 2115 radeon_get_encoder_id(dev, 2116 ATOM_DEVICE_LCD1_SUPPORT, 2117 0), 2118 ATOM_DEVICE_LCD1_SUPPORT); 2119 2120 if (lcd_ddc_info) { 2121 ddc_type = RBIOS8(lcd_ddc_info + 2); 2122 switch (ddc_type) { 2123 case DDC_MONID: 2124 ddc_i2c = 2125 combios_setup_i2c_bus 2126 (rdev, RADEON_GPIO_MONID); 2127 break; 2128 case DDC_DVI: 2129 ddc_i2c = 2130 combios_setup_i2c_bus 2131 (rdev, RADEON_GPIO_DVI_DDC); 2132 break; 2133 case DDC_VGA: 2134 ddc_i2c = 2135 combios_setup_i2c_bus 2136 (rdev, RADEON_GPIO_VGA_DDC); 2137 break; 2138 case DDC_CRT2: 2139 ddc_i2c = 2140 combios_setup_i2c_bus 2141 (rdev, RADEON_GPIO_CRT2_DDC); 2142 break; 2143 case DDC_LCD: 2144 ddc_i2c = 2145 combios_setup_i2c_bus 2146 (rdev, RADEON_GPIOPAD_MASK); 2147 ddc_i2c.mask_clk_mask = 2148 RBIOS32(lcd_ddc_info + 3); 2149 ddc_i2c.mask_data_mask = 2150 RBIOS32(lcd_ddc_info + 7); 2151 ddc_i2c.a_clk_mask = 2152 RBIOS32(lcd_ddc_info + 3); 2153 ddc_i2c.a_data_mask = 2154 RBIOS32(lcd_ddc_info + 7); 2155 ddc_i2c.en_clk_mask = 2156 RBIOS32(lcd_ddc_info + 3); 2157 ddc_i2c.en_data_mask = 2158 RBIOS32(lcd_ddc_info + 7); 2159 ddc_i2c.y_clk_mask = 2160 RBIOS32(lcd_ddc_info + 3); 2161 ddc_i2c.y_data_mask = 2162 RBIOS32(lcd_ddc_info + 7); 2163 break; 2164 case DDC_GPIO: 2165 ddc_i2c = 2166 combios_setup_i2c_bus 2167 (rdev, RADEON_MDGPIO_MASK); 2168 ddc_i2c.mask_clk_mask = 2169 RBIOS32(lcd_ddc_info + 3); 2170 ddc_i2c.mask_data_mask = 2171 RBIOS32(lcd_ddc_info + 7); 2172 ddc_i2c.a_clk_mask = 2173 RBIOS32(lcd_ddc_info + 3); 2174 ddc_i2c.a_data_mask = 2175 RBIOS32(lcd_ddc_info + 7); 2176 ddc_i2c.en_clk_mask = 2177 RBIOS32(lcd_ddc_info + 3); 2178 ddc_i2c.en_data_mask = 2179 RBIOS32(lcd_ddc_info + 7); 2180 ddc_i2c.y_clk_mask = 2181 RBIOS32(lcd_ddc_info + 3); 2182 ddc_i2c.y_data_mask = 2183 RBIOS32(lcd_ddc_info + 7); 2184 break; 2185 default: 2186 ddc_i2c.valid = false; 2187 break; 2188 } 2189 DRM_DEBUG("LCD DDC Info Table found!\n"); 2190 } else 2191 ddc_i2c.valid = false; 2192 2193 hpd.hpd = RADEON_HPD_NONE; 2194 radeon_add_legacy_connector(dev, 2195 5, 2196 ATOM_DEVICE_LCD1_SUPPORT, 2197 DRM_MODE_CONNECTOR_LVDS, 2198 &ddc_i2c, 2199 CONNECTOR_OBJECT_ID_LVDS, 2200 &hpd); 2201 } 2202 } 2203 2204 /* check TV table */ 2205 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 2206 uint32_t tv_info = 2207 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 2208 if (tv_info) { 2209 if (RBIOS8(tv_info + 6) == 'T') { 2210 if (radeon_apply_legacy_tv_quirks(dev)) { 2211 hpd.hpd = RADEON_HPD_NONE; 2212 radeon_add_legacy_encoder(dev, 2213 radeon_get_encoder_id 2214 (dev, 2215 ATOM_DEVICE_TV1_SUPPORT, 2216 2), 2217 ATOM_DEVICE_TV1_SUPPORT); 2218 radeon_add_legacy_connector(dev, 6, 2219 ATOM_DEVICE_TV1_SUPPORT, 2220 DRM_MODE_CONNECTOR_SVIDEO, 2221 &ddc_i2c, 2222 CONNECTOR_OBJECT_ID_SVIDEO, 2223 &hpd); 2224 } 2225 } 2226 } 2227 } 2228 2229 radeon_link_encoder_connector(dev); 2230 2231 return true; 2232} 2233 2234void radeon_external_tmds_setup(struct drm_encoder *encoder) 2235{ 2236 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2237 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2238 2239 if (!tmds) 2240 return; 2241 2242 switch (tmds->dvo_chip) { 2243 case DVO_SIL164: 2244 /* sil 164 */ 2245 radeon_i2c_do_lock(tmds->i2c_bus, 1); 2246 radeon_i2c_sw_put_byte(tmds->i2c_bus, 2247 tmds->slave_addr, 2248 0x08, 0x30); 2249 radeon_i2c_sw_put_byte(tmds->i2c_bus, 2250 tmds->slave_addr, 2251 0x09, 0x00); 2252 radeon_i2c_sw_put_byte(tmds->i2c_bus, 2253 tmds->slave_addr, 2254 0x0a, 0x90); 2255 radeon_i2c_sw_put_byte(tmds->i2c_bus, 2256 tmds->slave_addr, 2257 0x0c, 0x89); 2258 radeon_i2c_sw_put_byte(tmds->i2c_bus, 2259 tmds->slave_addr, 2260 0x08, 0x3b); 2261 radeon_i2c_do_lock(tmds->i2c_bus, 0); 2262 break; 2263 case DVO_SIL1178: 2264 /* sil 1178 - untested */ 2265 /* 2266 * 0x0f, 0x44 2267 * 0x0f, 0x4c 2268 * 0x0e, 0x01 2269 * 0x0a, 0x80 2270 * 0x09, 0x30 2271 * 0x0c, 0xc9 2272 * 0x0d, 0x70 2273 * 0x08, 0x32 2274 * 0x08, 0x33 2275 */ 2276 break; 2277 default: 2278 break; 2279 } 2280 2281} 2282 2283bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder) 2284{ 2285 struct drm_device *dev = encoder->dev; 2286 struct radeon_device *rdev = dev->dev_private; 2287 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2288 uint16_t offset; 2289 uint8_t blocks, slave_addr, rev; 2290 uint32_t index, id; 2291 uint32_t reg, val, and_mask, or_mask; 2292 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2293 2294 if (rdev->bios == NULL) 2295 return false; 2296 2297 if (!tmds) 2298 return false; 2299 2300 if (rdev->flags & RADEON_IS_IGP) { 2301 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE); 2302 rev = RBIOS8(offset); 2303 if (offset) { 2304 rev = RBIOS8(offset); 2305 if (rev > 1) { 2306 blocks = RBIOS8(offset + 3); 2307 index = offset + 4; 2308 while (blocks > 0) { 2309 id = RBIOS16(index); 2310 index += 2; 2311 switch (id >> 13) { 2312 case 0: 2313 reg = (id & 0x1fff) * 4; 2314 val = RBIOS32(index); 2315 index += 4; 2316 WREG32(reg, val); 2317 break; 2318 case 2: 2319 reg = (id & 0x1fff) * 4; 2320 and_mask = RBIOS32(index); 2321 index += 4; 2322 or_mask = RBIOS32(index); 2323 index += 4; 2324 val = RREG32(reg); 2325 val = (val & and_mask) | or_mask; 2326 WREG32(reg, val); 2327 break; 2328 case 3: 2329 val = RBIOS16(index); 2330 index += 2; 2331 udelay(val); 2332 break; 2333 case 4: 2334 val = RBIOS16(index); 2335 index += 2; 2336 udelay(val * 1000); 2337 break; 2338 case 6: 2339 slave_addr = id & 0xff; 2340 slave_addr >>= 1; /* 7 bit addressing */ 2341 index++; 2342 reg = RBIOS8(index); 2343 index++; 2344 val = RBIOS8(index); 2345 index++; 2346 radeon_i2c_do_lock(tmds->i2c_bus, 1); 2347 radeon_i2c_sw_put_byte(tmds->i2c_bus, 2348 slave_addr, 2349 reg, val); 2350 radeon_i2c_do_lock(tmds->i2c_bus, 0); 2351 break; 2352 default: 2353 DRM_ERROR("Unknown id %d\n", id >> 13); 2354 break; 2355 } 2356 blocks--; 2357 } 2358 return true; 2359 } 2360 } 2361 } else { 2362 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 2363 if (offset) { 2364 index = offset + 10; 2365 id = RBIOS16(index); 2366 while (id != 0xffff) { 2367 index += 2; 2368 switch (id >> 13) { 2369 case 0: 2370 reg = (id & 0x1fff) * 4; 2371 val = RBIOS32(index); 2372 WREG32(reg, val); 2373 break; 2374 case 2: 2375 reg = (id & 0x1fff) * 4; 2376 and_mask = RBIOS32(index); 2377 index += 4; 2378 or_mask = RBIOS32(index); 2379 index += 4; 2380 val = RREG32(reg); 2381 val = (val & and_mask) | or_mask; 2382 WREG32(reg, val); 2383 break; 2384 case 4: 2385 val = RBIOS16(index); 2386 index += 2; 2387 udelay(val); 2388 break; 2389 case 5: 2390 reg = id & 0x1fff; 2391 and_mask = RBIOS32(index); 2392 index += 4; 2393 or_mask = RBIOS32(index); 2394 index += 4; 2395 val = RREG32_PLL(reg); 2396 val = (val & and_mask) | or_mask; 2397 WREG32_PLL(reg, val); 2398 break; 2399 case 6: 2400 reg = id & 0x1fff; 2401 val = RBIOS8(index); 2402 index += 1; 2403 radeon_i2c_do_lock(tmds->i2c_bus, 1); 2404 radeon_i2c_sw_put_byte(tmds->i2c_bus, 2405 tmds->slave_addr, 2406 reg, val); 2407 radeon_i2c_do_lock(tmds->i2c_bus, 0); 2408 break; 2409 default: 2410 DRM_ERROR("Unknown id %d\n", id >> 13); 2411 break; 2412 } 2413 id = RBIOS16(index); 2414 } 2415 return true; 2416 } 2417 } 2418 return false; 2419} 2420 2421static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset) 2422{ 2423 struct radeon_device *rdev = dev->dev_private; 2424 2425 if (offset) { 2426 while (RBIOS16(offset)) { 2427 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13); 2428 uint32_t addr = (RBIOS16(offset) & 0x1fff); 2429 uint32_t val, and_mask, or_mask; 2430 uint32_t tmp; 2431 2432 offset += 2; 2433 switch (cmd) { 2434 case 0: 2435 val = RBIOS32(offset); 2436 offset += 4; 2437 WREG32(addr, val); 2438 break; 2439 case 1: 2440 val = RBIOS32(offset); 2441 offset += 4; 2442 WREG32(addr, val); 2443 break; 2444 case 2: 2445 and_mask = RBIOS32(offset); 2446 offset += 4; 2447 or_mask = RBIOS32(offset); 2448 offset += 4; 2449 tmp = RREG32(addr); 2450 tmp &= and_mask; 2451 tmp |= or_mask; 2452 WREG32(addr, tmp); 2453 break; 2454 case 3: 2455 and_mask = RBIOS32(offset); 2456 offset += 4; 2457 or_mask = RBIOS32(offset); 2458 offset += 4; 2459 tmp = RREG32(addr); 2460 tmp &= and_mask; 2461 tmp |= or_mask; 2462 WREG32(addr, tmp); 2463 break; 2464 case 4: 2465 val = RBIOS16(offset); 2466 offset += 2; 2467 udelay(val); 2468 break; 2469 case 5: 2470 val = RBIOS16(offset); 2471 offset += 2; 2472 switch (addr) { 2473 case 8: 2474 while (val--) { 2475 if (! 2476 (RREG32_PLL 2477 (RADEON_CLK_PWRMGT_CNTL) & 2478 RADEON_MC_BUSY)) 2479 break; 2480 } 2481 break; 2482 case 9: 2483 while (val--) { 2484 if ((RREG32(RADEON_MC_STATUS) & 2485 RADEON_MC_IDLE)) 2486 break; 2487 } 2488 break; 2489 default: 2490 break; 2491 } 2492 break; 2493 default: 2494 break; 2495 } 2496 } 2497 } 2498} 2499 2500static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset) 2501{ 2502 struct radeon_device *rdev = dev->dev_private; 2503 2504 if (offset) { 2505 while (RBIOS8(offset)) { 2506 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6); 2507 uint8_t addr = (RBIOS8(offset) & 0x3f); 2508 uint32_t val, shift, tmp; 2509 uint32_t and_mask, or_mask; 2510 2511 offset++; 2512 switch (cmd) { 2513 case 0: 2514 val = RBIOS32(offset); 2515 offset += 4; 2516 WREG32_PLL(addr, val); 2517 break; 2518 case 1: 2519 shift = RBIOS8(offset) * 8; 2520 offset++; 2521 and_mask = RBIOS8(offset) << shift; 2522 and_mask |= ~(0xff << shift); 2523 offset++; 2524 or_mask = RBIOS8(offset) << shift; 2525 offset++; 2526 tmp = RREG32_PLL(addr); 2527 tmp &= and_mask; 2528 tmp |= or_mask; 2529 WREG32_PLL(addr, tmp); 2530 break; 2531 case 2: 2532 case 3: 2533 tmp = 1000; 2534 switch (addr) { 2535 case 1: 2536 udelay(150); 2537 break; 2538 case 2: 2539 udelay(1000); 2540 break; 2541 case 3: 2542 while (tmp--) { 2543 if (! 2544 (RREG32_PLL 2545 (RADEON_CLK_PWRMGT_CNTL) & 2546 RADEON_MC_BUSY)) 2547 break; 2548 } 2549 break; 2550 case 4: 2551 while (tmp--) { 2552 if (RREG32_PLL 2553 (RADEON_CLK_PWRMGT_CNTL) & 2554 RADEON_DLL_READY) 2555 break; 2556 } 2557 break; 2558 case 5: 2559 tmp = 2560 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); 2561 if (tmp & RADEON_CG_NO1_DEBUG_0) { 2562#if 0 2563 uint32_t mclk_cntl = 2564 RREG32_PLL 2565 (RADEON_MCLK_CNTL); 2566 mclk_cntl &= 0xffff0000; 2567 /*mclk_cntl |= 0x00001111;*//* ??? */ 2568 WREG32_PLL(RADEON_MCLK_CNTL, 2569 mclk_cntl); 2570 udelay(10000); 2571#endif 2572 WREG32_PLL 2573 (RADEON_CLK_PWRMGT_CNTL, 2574 tmp & 2575 ~RADEON_CG_NO1_DEBUG_0); 2576 udelay(10000); 2577 } 2578 break; 2579 default: 2580 break; 2581 } 2582 break; 2583 default: 2584 break; 2585 } 2586 } 2587 } 2588} 2589 2590static void combios_parse_ram_reset_table(struct drm_device *dev, 2591 uint16_t offset) 2592{ 2593 struct radeon_device *rdev = dev->dev_private; 2594 uint32_t tmp; 2595 2596 if (offset) { 2597 uint8_t val = RBIOS8(offset); 2598 while (val != 0xff) { 2599 offset++; 2600 2601 if (val == 0x0f) { 2602 uint32_t channel_complete_mask; 2603 2604 if (ASIC_IS_R300(rdev)) 2605 channel_complete_mask = 2606 R300_MEM_PWRUP_COMPLETE; 2607 else 2608 channel_complete_mask = 2609 RADEON_MEM_PWRUP_COMPLETE; 2610 tmp = 20000; 2611 while (tmp--) { 2612 if ((RREG32(RADEON_MEM_STR_CNTL) & 2613 channel_complete_mask) == 2614 channel_complete_mask) 2615 break; 2616 } 2617 } else { 2618 uint32_t or_mask = RBIOS16(offset); 2619 offset += 2; 2620 2621 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 2622 tmp &= RADEON_SDRAM_MODE_MASK; 2623 tmp |= or_mask; 2624 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 2625 2626 or_mask = val << 24; 2627 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 2628 tmp &= RADEON_B3MEM_RESET_MASK; 2629 tmp |= or_mask; 2630 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 2631 } 2632 val = RBIOS8(offset); 2633 } 2634 } 2635} 2636 2637static uint32_t combios_detect_ram(struct drm_device *dev, int ram, 2638 int mem_addr_mapping) 2639{ 2640 struct radeon_device *rdev = dev->dev_private; 2641 uint32_t mem_cntl; 2642 uint32_t mem_size; 2643 uint32_t addr = 0; 2644 2645 mem_cntl = RREG32(RADEON_MEM_CNTL); 2646 if (mem_cntl & RV100_HALF_MODE) 2647 ram /= 2; 2648 mem_size = ram; 2649 mem_cntl &= ~(0xff << 8); 2650 mem_cntl |= (mem_addr_mapping & 0xff) << 8; 2651 WREG32(RADEON_MEM_CNTL, mem_cntl); 2652 RREG32(RADEON_MEM_CNTL); 2653 2654 /* sdram reset ? */ 2655 2656 /* something like this???? */ 2657 while (ram--) { 2658 addr = ram * 1024 * 1024; 2659 /* write to each page */ 2660 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER); 2661 WREG32(RADEON_MM_DATA, 0xdeadbeef); 2662 /* read back and verify */ 2663 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER); 2664 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef) 2665 return 0; 2666 } 2667 2668 return mem_size; 2669} 2670 2671static void combios_write_ram_size(struct drm_device *dev) 2672{ 2673 struct radeon_device *rdev = dev->dev_private; 2674 uint8_t rev; 2675 uint16_t offset; 2676 uint32_t mem_size = 0; 2677 uint32_t mem_cntl = 0; 2678 2679 /* should do something smarter here I guess... */ 2680 if (rdev->flags & RADEON_IS_IGP) 2681 return; 2682 2683 /* first check detected mem table */ 2684 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE); 2685 if (offset) { 2686 rev = RBIOS8(offset); 2687 if (rev < 3) { 2688 mem_cntl = RBIOS32(offset + 1); 2689 mem_size = RBIOS16(offset + 5); 2690 if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) && 2691 ((dev->pdev->device != 0x515e) 2692 && (dev->pdev->device != 0x5969))) 2693 WREG32(RADEON_MEM_CNTL, mem_cntl); 2694 } 2695 } 2696 2697 if (!mem_size) { 2698 offset = 2699 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 2700 if (offset) { 2701 rev = RBIOS8(offset - 1); 2702 if (rev < 1) { 2703 if (((rdev->flags & RADEON_FAMILY_MASK) < 2704 CHIP_R200) 2705 && ((dev->pdev->device != 0x515e) 2706 && (dev->pdev->device != 0x5969))) { 2707 int ram = 0; 2708 int mem_addr_mapping = 0; 2709 2710 while (RBIOS8(offset)) { 2711 ram = RBIOS8(offset); 2712 mem_addr_mapping = 2713 RBIOS8(offset + 1); 2714 if (mem_addr_mapping != 0x25) 2715 ram *= 2; 2716 mem_size = 2717 combios_detect_ram(dev, ram, 2718 mem_addr_mapping); 2719 if (mem_size) 2720 break; 2721 offset += 2; 2722 } 2723 } else 2724 mem_size = RBIOS8(offset); 2725 } else { 2726 mem_size = RBIOS8(offset); 2727 mem_size *= 2; /* convert to MB */ 2728 } 2729 } 2730 } 2731 2732 mem_size *= (1024 * 1024); /* convert to bytes */ 2733 WREG32(RADEON_CONFIG_MEMSIZE, mem_size); 2734} 2735 2736void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable) 2737{ 2738 uint16_t dyn_clk_info = 2739 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); 2740 2741 if (dyn_clk_info) 2742 combios_parse_pll_table(dev, dyn_clk_info); 2743} 2744 2745void radeon_combios_asic_init(struct drm_device *dev) 2746{ 2747 struct radeon_device *rdev = dev->dev_private; 2748 uint16_t table; 2749 2750 /* port hardcoded mac stuff from radeonfb */ 2751 if (rdev->bios == NULL) 2752 return; 2753 2754 /* ASIC INIT 1 */ 2755 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE); 2756 if (table) 2757 combios_parse_mmio_table(dev, table); 2758 2759 /* PLL INIT */ 2760 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE); 2761 if (table) 2762 combios_parse_pll_table(dev, table); 2763 2764 /* ASIC INIT 2 */ 2765 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE); 2766 if (table) 2767 combios_parse_mmio_table(dev, table); 2768 2769 if (!(rdev->flags & RADEON_IS_IGP)) { 2770 /* ASIC INIT 4 */ 2771 table = 2772 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE); 2773 if (table) 2774 combios_parse_mmio_table(dev, table); 2775 2776 /* RAM RESET */ 2777 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE); 2778 if (table) 2779 combios_parse_ram_reset_table(dev, table); 2780 2781 /* ASIC INIT 3 */ 2782 table = 2783 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE); 2784 if (table) 2785 combios_parse_mmio_table(dev, table); 2786 2787 /* write CONFIG_MEMSIZE */ 2788 combios_write_ram_size(dev); 2789 } 2790 2791 /* DYN CLK 1 */ 2792 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); 2793 if (table) 2794 combios_parse_pll_table(dev, table); 2795 2796} 2797 2798void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev) 2799{ 2800 struct radeon_device *rdev = dev->dev_private; 2801 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch; 2802 2803 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 2804 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 2805 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH); 2806 2807 /* let the bios control the backlight */ 2808 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; 2809 2810 /* tell the bios not to handle mode switching */ 2811 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS | 2812 RADEON_ACC_MODE_CHANGE); 2813 2814 /* tell the bios a driver is loaded */ 2815 bios_7_scratch |= RADEON_DRV_LOADED; 2816 2817 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); 2818 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 2819 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch); 2820} 2821 2822void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock) 2823{ 2824 struct drm_device *dev = encoder->dev; 2825 struct radeon_device *rdev = dev->dev_private; 2826 uint32_t bios_6_scratch; 2827 2828 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 2829 2830 if (lock) 2831 bios_6_scratch |= RADEON_DRIVER_CRITICAL; 2832 else 2833 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL; 2834 2835 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 2836} 2837 2838void 2839radeon_combios_connected_scratch_regs(struct drm_connector *connector, 2840 struct drm_encoder *encoder, 2841 bool connected) 2842{ 2843 struct drm_device *dev = connector->dev; 2844 struct radeon_device *rdev = dev->dev_private; 2845 struct radeon_connector *radeon_connector = 2846 to_radeon_connector(connector); 2847 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2848 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH); 2849 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 2850 2851 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 2852 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 2853 if (connected) { 2854 DRM_DEBUG("TV1 connected\n"); 2855 /* fix me */ 2856 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO; 2857 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */ 2858 bios_5_scratch |= RADEON_TV1_ON; 2859 bios_5_scratch |= RADEON_ACC_REQ_TV1; 2860 } else { 2861 DRM_DEBUG("TV1 disconnected\n"); 2862 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK; 2863 bios_5_scratch &= ~RADEON_TV1_ON; 2864 bios_5_scratch &= ~RADEON_ACC_REQ_TV1; 2865 } 2866 } 2867 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 2868 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 2869 if (connected) { 2870 DRM_DEBUG("LCD1 connected\n"); 2871 bios_4_scratch |= RADEON_LCD1_ATTACHED; 2872 bios_5_scratch |= RADEON_LCD1_ON; 2873 bios_5_scratch |= RADEON_ACC_REQ_LCD1; 2874 } else { 2875 DRM_DEBUG("LCD1 disconnected\n"); 2876 bios_4_scratch &= ~RADEON_LCD1_ATTACHED; 2877 bios_5_scratch &= ~RADEON_LCD1_ON; 2878 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1; 2879 } 2880 } 2881 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 2882 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 2883 if (connected) { 2884 DRM_DEBUG("CRT1 connected\n"); 2885 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR; 2886 bios_5_scratch |= RADEON_CRT1_ON; 2887 bios_5_scratch |= RADEON_ACC_REQ_CRT1; 2888 } else { 2889 DRM_DEBUG("CRT1 disconnected\n"); 2890 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK; 2891 bios_5_scratch &= ~RADEON_CRT1_ON; 2892 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1; 2893 } 2894 } 2895 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 2896 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 2897 if (connected) { 2898 DRM_DEBUG("CRT2 connected\n"); 2899 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR; 2900 bios_5_scratch |= RADEON_CRT2_ON; 2901 bios_5_scratch |= RADEON_ACC_REQ_CRT2; 2902 } else { 2903 DRM_DEBUG("CRT2 disconnected\n"); 2904 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK; 2905 bios_5_scratch &= ~RADEON_CRT2_ON; 2906 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2; 2907 } 2908 } 2909 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 2910 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 2911 if (connected) { 2912 DRM_DEBUG("DFP1 connected\n"); 2913 bios_4_scratch |= RADEON_DFP1_ATTACHED; 2914 bios_5_scratch |= RADEON_DFP1_ON; 2915 bios_5_scratch |= RADEON_ACC_REQ_DFP1; 2916 } else { 2917 DRM_DEBUG("DFP1 disconnected\n"); 2918 bios_4_scratch &= ~RADEON_DFP1_ATTACHED; 2919 bios_5_scratch &= ~RADEON_DFP1_ON; 2920 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1; 2921 } 2922 } 2923 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 2924 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 2925 if (connected) { 2926 DRM_DEBUG("DFP2 connected\n"); 2927 bios_4_scratch |= RADEON_DFP2_ATTACHED; 2928 bios_5_scratch |= RADEON_DFP2_ON; 2929 bios_5_scratch |= RADEON_ACC_REQ_DFP2; 2930 } else { 2931 DRM_DEBUG("DFP2 disconnected\n"); 2932 bios_4_scratch &= ~RADEON_DFP2_ATTACHED; 2933 bios_5_scratch &= ~RADEON_DFP2_ON; 2934 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2; 2935 } 2936 } 2937 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch); 2938 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 2939} 2940 2941void 2942radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) 2943{ 2944 struct drm_device *dev = encoder->dev; 2945 struct radeon_device *rdev = dev->dev_private; 2946 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2947 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 2948 2949 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 2950 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK; 2951 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT); 2952 } 2953 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2954 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK; 2955 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT); 2956 } 2957 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2958 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK; 2959 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT); 2960 } 2961 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 2962 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK; 2963 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT); 2964 } 2965 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 2966 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK; 2967 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT); 2968 } 2969 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 2970 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK; 2971 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT); 2972 } 2973 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 2974} 2975 2976void 2977radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) 2978{ 2979 struct drm_device *dev = encoder->dev; 2980 struct radeon_device *rdev = dev->dev_private; 2981 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2982 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 2983 2984 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 2985 if (on) 2986 bios_6_scratch |= RADEON_TV_DPMS_ON; 2987 else 2988 bios_6_scratch &= ~RADEON_TV_DPMS_ON; 2989 } 2990 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 2991 if (on) 2992 bios_6_scratch |= RADEON_CRT_DPMS_ON; 2993 else 2994 bios_6_scratch &= ~RADEON_CRT_DPMS_ON; 2995 } 2996 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2997 if (on) 2998 bios_6_scratch |= RADEON_LCD_DPMS_ON; 2999 else 3000 bios_6_scratch &= ~RADEON_LCD_DPMS_ON; 3001 } 3002 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 3003 if (on) 3004 bios_6_scratch |= RADEON_DFP_DPMS_ON; 3005 else 3006 bios_6_scratch &= ~RADEON_DFP_DPMS_ON; 3007 } 3008 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3009} 3010