1a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher/* 2a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher * Copyright 2013 Advanced Micro Devices, Inc. 3a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher * 4a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher * copy of this software and associated documentation files (the "Software"), 6a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher * to deal in the Software without restriction, including without limitation 7a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher * Software is furnished to do so, subject to the following conditions: 10a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher * 11a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher * The above copyright notice and this permission notice shall be included in 12a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher * all copies or substantial portions of the Software. 13a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher * 14a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher * 22a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher */ 23a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#ifndef PP_SISLANDS_SMC_H 24a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define PP_SISLANDS_SMC_H 25a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 26a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#include "ppsmc.h" 27a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 28a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#pragma pack(push, 1) 29a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 30a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16 31a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 32a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucherstruct PP_SIslands_Dpm2PerfLevel 33a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher{ 34a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t MaxPS; 35a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t TgtAct; 36a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t MaxPS_StepInc; 37a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t MaxPS_StepDec; 38a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t PSSamplingTime; 39a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t NearTDPDec; 40a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t AboveSafeInc; 41a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t BelowSafeInc; 42a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t PSDeltaLimit; 43a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t PSDeltaWin; 44a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint16_t PwrEfficiencyRatio; 45a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t Reserved[4]; 46a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher}; 47a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 48a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deuchertypedef struct PP_SIslands_Dpm2PerfLevel PP_SIslands_Dpm2PerfLevel; 49a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 50a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucherstruct PP_SIslands_DPM2Status 51a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher{ 52a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t dpm2Flags; 53a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t CurrPSkip; 54a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t CurrPSkipPowerShift; 55a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t CurrPSkipTDP; 56a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t CurrPSkipOCP; 57a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t MaxSPLLIndex; 58a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t MinSPLLIndex; 59a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t CurrSPLLIndex; 60a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t InfSweepMode; 61a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t InfSweepDir; 62a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t TDPexceeded; 63a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t reserved; 64a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t SwitchDownThreshold; 65a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t SwitchDownCounter; 66a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t SysScalingFactor; 67a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher}; 68a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 69a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deuchertypedef struct PP_SIslands_DPM2Status PP_SIslands_DPM2Status; 70a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 71a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucherstruct PP_SIslands_DPM2Parameters 72a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher{ 73a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t TDPLimit; 74a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t NearTDPLimit; 75a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t SafePowerLimit; 76a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t PowerBoostLimit; 77a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t MinLimitDelta; 78a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher}; 79a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deuchertypedef struct PP_SIslands_DPM2Parameters PP_SIslands_DPM2Parameters; 80a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 81a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucherstruct PP_SIslands_PAPMStatus 82a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher{ 83a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t EstimatedDGPU_T; 84a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t EstimatedDGPU_P; 85a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t EstimatedAPU_T; 86a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t EstimatedAPU_P; 87a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t dGPU_T_Limit_Exceeded; 88a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t reserved[3]; 89a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher}; 90a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deuchertypedef struct PP_SIslands_PAPMStatus PP_SIslands_PAPMStatus; 91a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 92a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucherstruct PP_SIslands_PAPMParameters 93a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher{ 94a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t NearTDPLimitTherm; 95a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t NearTDPLimitPAPM; 96a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t PlatformPowerLimit; 97a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t dGPU_T_Limit; 98a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t dGPU_T_Warning; 99a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t dGPU_T_Hysteresis; 100a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher}; 101a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deuchertypedef struct PP_SIslands_PAPMParameters PP_SIslands_PAPMParameters; 102a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 103a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucherstruct SISLANDS_SMC_SCLK_VALUE 104a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher{ 105a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t vCG_SPLL_FUNC_CNTL; 106a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t vCG_SPLL_FUNC_CNTL_2; 107a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t vCG_SPLL_FUNC_CNTL_3; 108a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t vCG_SPLL_FUNC_CNTL_4; 109a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t vCG_SPLL_SPREAD_SPECTRUM; 110a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; 111a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t sclk_value; 112a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher}; 113a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 114a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deuchertypedef struct SISLANDS_SMC_SCLK_VALUE SISLANDS_SMC_SCLK_VALUE; 115a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 116a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucherstruct SISLANDS_SMC_MCLK_VALUE 117a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher{ 118a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t vMPLL_FUNC_CNTL; 119a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t vMPLL_FUNC_CNTL_1; 120a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t vMPLL_FUNC_CNTL_2; 121a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t vMPLL_AD_FUNC_CNTL; 122a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t vMPLL_DQ_FUNC_CNTL; 123a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t vMCLK_PWRMGT_CNTL; 124a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t vDLL_CNTL; 125a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t vMPLL_SS; 126a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t vMPLL_SS2; 127a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t mclk_value; 128a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher}; 129a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 130a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deuchertypedef struct SISLANDS_SMC_MCLK_VALUE SISLANDS_SMC_MCLK_VALUE; 131a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 132a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucherstruct SISLANDS_SMC_VOLTAGE_VALUE 133a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher{ 134a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint16_t value; 135a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t index; 136a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t phase_settings; 137a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher}; 138a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 139a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deuchertypedef struct SISLANDS_SMC_VOLTAGE_VALUE SISLANDS_SMC_VOLTAGE_VALUE; 140a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 141a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucherstruct SISLANDS_SMC_HW_PERFORMANCE_LEVEL 142a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher{ 143a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t ACIndex; 144a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t displayWatermark; 145a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t gen2PCIE; 146a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t UVDWatermark; 147a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t VCEWatermark; 148a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t strobeMode; 149a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t mcFlags; 150a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t padding; 151a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t aT; 152a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t bSP; 153a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher SISLANDS_SMC_SCLK_VALUE sclk; 154a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher SISLANDS_SMC_MCLK_VALUE mclk; 155a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher SISLANDS_SMC_VOLTAGE_VALUE vddc; 156a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher SISLANDS_SMC_VOLTAGE_VALUE mvdd; 157a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher SISLANDS_SMC_VOLTAGE_VALUE vddci; 158a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher SISLANDS_SMC_VOLTAGE_VALUE std_vddc; 159a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t hysteresisUp; 160a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t hysteresisDown; 161a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t stateFlags; 162a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t arbRefreshState; 163a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t SQPowerThrottle; 164a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t SQPowerThrottle_2; 165a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t MaxPoweredUpCU; 166a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher SISLANDS_SMC_VOLTAGE_VALUE high_temp_vddc; 167a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher SISLANDS_SMC_VOLTAGE_VALUE low_temp_vddc; 168a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t reserved[2]; 169a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher PP_SIslands_Dpm2PerfLevel dpm2; 170a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher}; 171a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 172a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SISLANDS_SMC_STROBE_RATIO 0x0F 173a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SISLANDS_SMC_STROBE_ENABLE 0x10 174a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 175a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SISLANDS_SMC_MC_EDC_RD_FLAG 0x01 176a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SISLANDS_SMC_MC_EDC_WR_FLAG 0x02 177a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SISLANDS_SMC_MC_RTT_ENABLE 0x04 178a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SISLANDS_SMC_MC_STUTTER_EN 0x08 179a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SISLANDS_SMC_MC_PG_EN 0x10 180a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 181a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deuchertypedef struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL SISLANDS_SMC_HW_PERFORMANCE_LEVEL; 182a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 183a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucherstruct SISLANDS_SMC_SWSTATE 184a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher{ 185a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t flags; 186a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t levelCount; 187a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t padding2; 188a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t padding3; 189a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher SISLANDS_SMC_HW_PERFORMANCE_LEVEL levels[1]; 190a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher}; 191a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 192a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deuchertypedef struct SISLANDS_SMC_SWSTATE SISLANDS_SMC_SWSTATE; 193a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 194a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SISLANDS_SMC_VOLTAGEMASK_VDDC 0 195a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SISLANDS_SMC_VOLTAGEMASK_MVDD 1 196a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SISLANDS_SMC_VOLTAGEMASK_VDDCI 2 197a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SISLANDS_SMC_VOLTAGEMASK_MAX 4 198a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 199a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucherstruct SISLANDS_SMC_VOLTAGEMASKTABLE 200a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher{ 201a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t lowMask[SISLANDS_SMC_VOLTAGEMASK_MAX]; 202a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher}; 203a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 204a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deuchertypedef struct SISLANDS_SMC_VOLTAGEMASKTABLE SISLANDS_SMC_VOLTAGEMASKTABLE; 205a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 206a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SISLANDS_MAX_NO_VREG_STEPS 32 207a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 208a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucherstruct SISLANDS_SMC_STATETABLE 209a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher{ 210a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t thermalProtectType; 211a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t systemFlags; 212a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t maxVDDCIndexInPPTable; 213a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t extraFlags; 214a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t lowSMIO[SISLANDS_MAX_NO_VREG_STEPS]; 215a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher SISLANDS_SMC_VOLTAGEMASKTABLE voltageMaskTable; 216a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher SISLANDS_SMC_VOLTAGEMASKTABLE phaseMaskTable; 217a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher PP_SIslands_DPM2Parameters dpm2Params; 218a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher SISLANDS_SMC_SWSTATE initialState; 219a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher SISLANDS_SMC_SWSTATE ACPIState; 220a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher SISLANDS_SMC_SWSTATE ULVState; 221a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher SISLANDS_SMC_SWSTATE driverState; 222a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher SISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1]; 223a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher}; 224a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 225a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deuchertypedef struct SISLANDS_SMC_STATETABLE SISLANDS_SMC_STATETABLE; 226a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 227a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SI_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0 228a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SI_SMC_SOFT_REGISTER_delay_vreg 0xC 229a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SI_SMC_SOFT_REGISTER_delay_acpi 0x28 230a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SI_SMC_SOFT_REGISTER_seq_index 0x5C 231a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SI_SMC_SOFT_REGISTER_mvdd_chg_time 0x60 232a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SI_SMC_SOFT_REGISTER_mclk_switch_lim 0x70 233a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SI_SMC_SOFT_REGISTER_watermark_threshold 0x78 234a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SI_SMC_SOFT_REGISTER_phase_shedding_delay 0x88 235a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SI_SMC_SOFT_REGISTER_ulv_volt_change_delay 0x8C 236a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SI_SMC_SOFT_REGISTER_mc_block_delay 0x98 237a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SI_SMC_SOFT_REGISTER_ticks_per_us 0xA8 238a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SI_SMC_SOFT_REGISTER_crtc_index 0xC4 239a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min 0xC8 240a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max 0xCC 241a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width 0xF4 242a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen 0xFC 243a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SI_SMC_SOFT_REGISTER_vr_hot_gpio 0x100 244636e2582658742b94e7620becce58f939996c961Alex Deucher#define SI_SMC_SOFT_REGISTER_svi_rework_plat_type 0x118 245636e2582658742b94e7620becce58f939996c961Alex Deucher#define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd 0x11c 246636e2582658742b94e7620becce58f939996c961Alex Deucher#define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc 0x120 247a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 248a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16 249a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES 32 250a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 251a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SMC_SISLANDS_SCALE_I 7 252a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SMC_SISLANDS_SCALE_R 12 253a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 254a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucherstruct PP_SIslands_CacConfig 255a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher{ 256a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint16_t cac_lkge_lut[SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES]; 257a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t lkge_lut_V0; 258a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t lkge_lut_Vstep; 259a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t WinTime; 260a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t R_LL; 261a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t calculation_repeats; 262a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t l2numWin_TDP; 263a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t dc_cac; 264a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t lts_truncate_n; 265a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t SHIFT_N; 266a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t log2_PG_LKG_SCALE; 267a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t cac_temp; 268a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t lkge_lut_T0; 269a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t lkge_lut_Tstep; 270a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher}; 271a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 272a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deuchertypedef struct PP_SIslands_CacConfig PP_SIslands_CacConfig; 273a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 274a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE 16 275a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20 276a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 277a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucherstruct SMC_SIslands_MCRegisterAddress 278a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher{ 279a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint16_t s0; 280a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint16_t s1; 281a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher}; 282a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 283a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deuchertypedef struct SMC_SIslands_MCRegisterAddress SMC_SIslands_MCRegisterAddress; 284a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 285a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucherstruct SMC_SIslands_MCRegisterSet 286a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher{ 287a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t value[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; 288a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher}; 289a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 290a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deuchertypedef struct SMC_SIslands_MCRegisterSet SMC_SIslands_MCRegisterSet; 291a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 292a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucherstruct SMC_SIslands_MCRegisters 293a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher{ 294a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t last; 295a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t reserved[3]; 296a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher SMC_SIslands_MCRegisterAddress address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; 297a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher SMC_SIslands_MCRegisterSet data[SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT]; 298a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher}; 299a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 300a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deuchertypedef struct SMC_SIslands_MCRegisters SMC_SIslands_MCRegisters; 301a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 302a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucherstruct SMC_SIslands_MCArbDramTimingRegisterSet 303a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher{ 304a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t mc_arb_dram_timing; 305a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t mc_arb_dram_timing2; 306a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t mc_arb_rfsh_rate; 307a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t mc_arb_burst_time; 308a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t padding[2]; 309a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher}; 310a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 311a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deuchertypedef struct SMC_SIslands_MCArbDramTimingRegisterSet SMC_SIslands_MCArbDramTimingRegisterSet; 312a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 313a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucherstruct SMC_SIslands_MCArbDramTimingRegisters 314a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher{ 315a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t arb_current; 316a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t reserved[3]; 317a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher SMC_SIslands_MCArbDramTimingRegisterSet data[16]; 318a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher}; 319a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 320a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deuchertypedef struct SMC_SIslands_MCArbDramTimingRegisters SMC_SIslands_MCArbDramTimingRegisters; 321a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 322a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucherstruct SMC_SISLANDS_SPLL_DIV_TABLE 323a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher{ 324a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t freq[256]; 325a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t ss[256]; 326a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher}; 327a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 328a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK 0x01ffffff 329a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT 0 330a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK 0xfe000000 331a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT 25 332a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK 0x000fffff 333a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT 0 334a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK 0xfff00000 335a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT 20 336a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 337a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deuchertypedef struct SMC_SISLANDS_SPLL_DIV_TABLE SMC_SISLANDS_SPLL_DIV_TABLE; 338a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 339a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SMC_SISLANDS_DTE_MAX_FILTER_STAGES 5 340a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 341a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE 16 342a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 343a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucherstruct Smc_SIslands_DTE_Configuration 344a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher{ 345a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES]; 346a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t R[SMC_SISLANDS_DTE_MAX_FILTER_STAGES]; 347a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t K; 348a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t T0; 349a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t MaxT; 350a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t WindowSize; 351a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t Tdep_count; 352a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t temp_select; 353a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t DTE_mode; 354a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint8_t T_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; 355a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t Tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; 356a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t Tdep_R[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; 357a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher uint32_t Tthreshold; 358a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher}; 359a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 360a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deuchertypedef struct Smc_SIslands_DTE_Configuration Smc_SIslands_DTE_Configuration; 361a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 362a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SMC_SISLANDS_DTE_STATUS_FLAG_DTE_ON 1 363a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 364a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SISLANDS_SMC_FIRMWARE_HEADER_LOCATION 0x10000 365a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 366a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SISLANDS_SMC_FIRMWARE_HEADER_version 0x0 367a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SISLANDS_SMC_FIRMWARE_HEADER_flags 0x4 368a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SISLANDS_SMC_FIRMWARE_HEADER_softRegisters 0xC 369a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SISLANDS_SMC_FIRMWARE_HEADER_stateTable 0x10 370a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SISLANDS_SMC_FIRMWARE_HEADER_fanTable 0x14 371a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable 0x18 372a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable 0x24 373a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable 0x30 374a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SISLANDS_SMC_FIRMWARE_HEADER_spllTable 0x38 375a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration 0x40 376a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#define SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters 0x48 377a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 378a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#pragma pack(pop) 379a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 380a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucherint si_copy_bytes_to_smc(struct radeon_device *rdev, 381a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher u32 smc_start_address, 382a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher const u8 *src, u32 byte_count, u32 limit); 383a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deuchervoid si_start_smc(struct radeon_device *rdev); 384a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deuchervoid si_reset_smc(struct radeon_device *rdev); 385a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucherint si_program_jump_on_start(struct radeon_device *rdev); 386a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deuchervoid si_stop_smc_clock(struct radeon_device *rdev); 387a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deuchervoid si_start_smc_clock(struct radeon_device *rdev); 388a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucherbool si_is_smc_running(struct radeon_device *rdev); 389a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex DeucherPPSMC_Result si_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg); 390a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex DeucherPPSMC_Result si_wait_for_smc_inactive(struct radeon_device *rdev); 391a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucherint si_load_smc_ucode(struct radeon_device *rdev, u32 limit); 392a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucherint si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address, 393a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher u32 *value, u32 limit); 394a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucherint si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address, 395a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher u32 value, u32 limit); 396a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 397a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher#endif 398a9e61410921bcc1aa8f594ffa6301d5baba90f3bAlex Deucher 399