116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark/* 216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * Copyright (C) 2012 Texas Instruments 316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * Author: Rob Clark <robdclark@gmail.com> 416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * 516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * This program is free software; you can redistribute it and/or modify it 616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * under the terms of the GNU General Public License version 2 as published by 716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * the Free Software Foundation. 816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * 916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * This program is distributed in the hope that it will be useful, but WITHOUT 1016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * more details. 1316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * 1416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * You should have received a copy of the GNU General Public License along with 1516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * this program. If not, see <http://www.gnu.org/licenses/>. 1616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark */ 1716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 18a464d618c715b7a850f7459754d9d155f5e60538Rob Clark#include "drm_flip_work.h" 1916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 2016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#include "tilcdc_drv.h" 2116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#include "tilcdc_regs.h" 2216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 2316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstruct tilcdc_crtc { 2416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_crtc base; 2516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 2616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark const struct tilcdc_panel_info *info; 2716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark uint32_t dirty; 2816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark dma_addr_t start, end; 2916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_pending_vblank_event *event; 3016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark int dpms; 3116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark wait_queue_head_t frame_done_wq; 3216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark bool frame_done; 3316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 3416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* fb currently set to scanout 0/1: */ 3516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_framebuffer *scanout[2]; 3616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 3716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* for deferred fb unref's: */ 38a464d618c715b7a850f7459754d9d155f5e60538Rob Clark struct drm_flip_work unref_work; 3916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark}; 4016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base) 4116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 42a464d618c715b7a850f7459754d9d155f5e60538Rob Clarkstatic void unref_worker(struct drm_flip_work *work, void *val) 4316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 44f7b4575601dafb3cf3c568465ec6980de6d09b94Darren Etheridge struct tilcdc_crtc *tilcdc_crtc = 45a464d618c715b7a850f7459754d9d155f5e60538Rob Clark container_of(work, struct tilcdc_crtc, unref_work); 4616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_device *dev = tilcdc_crtc->base.dev; 4716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 4816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark mutex_lock(&dev->mode_config.mutex); 49a464d618c715b7a850f7459754d9d155f5e60538Rob Clark drm_framebuffer_unreference(val); 5016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark mutex_unlock(&dev->mode_config.mutex); 5116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 5216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 5316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic void set_scanout(struct drm_crtc *crtc, int n) 5416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 5516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark static const uint32_t base_reg[] = { 56f7b4575601dafb3cf3c568465ec6980de6d09b94Darren Etheridge LCDC_DMA_FB_BASE_ADDR_0_REG, 57f7b4575601dafb3cf3c568465ec6980de6d09b94Darren Etheridge LCDC_DMA_FB_BASE_ADDR_1_REG, 5816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark }; 5916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark static const uint32_t ceil_reg[] = { 60f7b4575601dafb3cf3c568465ec6980de6d09b94Darren Etheridge LCDC_DMA_FB_CEILING_ADDR_0_REG, 61f7b4575601dafb3cf3c568465ec6980de6d09b94Darren Etheridge LCDC_DMA_FB_CEILING_ADDR_1_REG, 6216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark }; 6316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark static const uint32_t stat[] = { 6416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark LCDC_END_OF_FRAME0, LCDC_END_OF_FRAME1, 6516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark }; 6616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 6716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_device *dev = crtc->dev; 68a464d618c715b7a850f7459754d9d155f5e60538Rob Clark struct tilcdc_drm_private *priv = dev->dev_private; 6916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 7016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark pm_runtime_get_sync(dev->dev); 7116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_write(dev, base_reg[n], tilcdc_crtc->start); 7216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_write(dev, ceil_reg[n], tilcdc_crtc->end); 7316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (tilcdc_crtc->scanout[n]) { 74a464d618c715b7a850f7459754d9d155f5e60538Rob Clark drm_flip_work_queue(&tilcdc_crtc->unref_work, tilcdc_crtc->scanout[n]); 75a464d618c715b7a850f7459754d9d155f5e60538Rob Clark drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq); 7616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 77f4510a2752b75ad5847b7935b68c233cab497f97Matt Roper tilcdc_crtc->scanout[n] = crtc->primary->fb; 7816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark drm_framebuffer_reference(tilcdc_crtc->scanout[n]); 7916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->dirty &= ~stat[n]; 8016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark pm_runtime_put_sync(dev->dev); 8116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 8216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 8316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic void update_scanout(struct drm_crtc *crtc) 8416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 8516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 8616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_device *dev = crtc->dev; 87f4510a2752b75ad5847b7935b68c233cab497f97Matt Roper struct drm_framebuffer *fb = crtc->primary->fb; 8816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_gem_cma_object *gem; 8916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark unsigned int depth, bpp; 9016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 9116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp); 9216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark gem = drm_fb_cma_get_gem_obj(fb, 0); 9316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 9416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->start = gem->paddr + fb->offsets[0] + 9516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark (crtc->y * fb->pitches[0]) + (crtc->x * bpp/8); 9616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 9716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->end = tilcdc_crtc->start + 9816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark (crtc->mode.vdisplay * fb->pitches[0]); 9916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 10016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (tilcdc_crtc->dpms == DRM_MODE_DPMS_ON) { 10116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* already enabled, so just mark the frames that need 10216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * updating and they will be updated on vblank: 10316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark */ 10416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->dirty |= LCDC_END_OF_FRAME0 | LCDC_END_OF_FRAME1; 10516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark drm_vblank_get(dev, 0); 10616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } else { 10716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* not enabled yet, so update registers immediately: */ 10816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark set_scanout(crtc, 0); 10916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark set_scanout(crtc, 1); 11016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 11116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 11216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 11316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic void start(struct drm_crtc *crtc) 11416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 11516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_device *dev = crtc->dev; 11616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_drm_private *priv = dev->dev_private; 11716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 11816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (priv->rev == 2) { 11916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET); 12016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark msleep(1); 12116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET); 12216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark msleep(1); 12316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 12416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 12516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_set(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE); 12616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_PALETTE_LOAD_MODE(DATA_ONLY)); 12716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); 12816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 12916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 13016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic void stop(struct drm_crtc *crtc) 13116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 13216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_device *dev = crtc->dev; 13316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 13416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); 13516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 13616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 13716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic void tilcdc_crtc_destroy(struct drm_crtc *crtc) 13816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 13916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 14016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 14116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark WARN_ON(tilcdc_crtc->dpms == DRM_MODE_DPMS_ON); 14216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 14316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark drm_crtc_cleanup(crtc); 144a464d618c715b7a850f7459754d9d155f5e60538Rob Clark drm_flip_work_cleanup(&tilcdc_crtc->unref_work); 145a464d618c715b7a850f7459754d9d155f5e60538Rob Clark 14616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark kfree(tilcdc_crtc); 14716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 14816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 14916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic int tilcdc_crtc_page_flip(struct drm_crtc *crtc, 15016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_framebuffer *fb, 151ed8d19756e80ec63003a93aa4d70406e6ba61522Keith Packard struct drm_pending_vblank_event *event, 152ed8d19756e80ec63003a93aa4d70406e6ba61522Keith Packard uint32_t page_flip_flags) 15316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 15416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 15516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_device *dev = crtc->dev; 15616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 15716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (tilcdc_crtc->event) { 15816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark dev_err(dev->dev, "already pending page flip!\n"); 15916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return -EBUSY; 16016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 16116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 162f4510a2752b75ad5847b7935b68c233cab497f97Matt Roper crtc->primary->fb = fb; 16316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->event = event; 16416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark update_scanout(crtc); 16516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 16616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return 0; 16716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 16816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 16916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode) 17016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 17116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 17216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_device *dev = crtc->dev; 17316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_drm_private *priv = dev->dev_private; 17416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 17516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* we really only care about on or off: */ 17616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (mode != DRM_MODE_DPMS_ON) 17716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark mode = DRM_MODE_DPMS_OFF; 17816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 17916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (tilcdc_crtc->dpms == mode) 18016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return; 18116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 18216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->dpms = mode; 18316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 18416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark pm_runtime_get_sync(dev->dev); 18516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 18616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (mode == DRM_MODE_DPMS_ON) { 18716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark pm_runtime_forbid(dev->dev); 18816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark start(crtc); 18916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } else { 19016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->frame_done = false; 19116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark stop(crtc); 19216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 193f7b4575601dafb3cf3c568465ec6980de6d09b94Darren Etheridge /* 194f7b4575601dafb3cf3c568465ec6980de6d09b94Darren Etheridge * if necessary wait for framedone irq which will still come 19516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * before putting things to sleep.. 19616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark */ 19716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (priv->rev == 2) { 19816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark int ret = wait_event_timeout( 19916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->frame_done_wq, 20016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->frame_done, 20116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark msecs_to_jiffies(50)); 20216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (ret == 0) 20316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark dev_err(dev->dev, "timeout waiting for framedone\n"); 20416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 20516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark pm_runtime_allow(dev->dev); 20616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 20716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 20816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark pm_runtime_put_sync(dev->dev); 20916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 21016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 21116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc, 21216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark const struct drm_display_mode *mode, 21316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_display_mode *adjusted_mode) 21416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 21516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return true; 21616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 21716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 21816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic void tilcdc_crtc_prepare(struct drm_crtc *crtc) 21916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 22016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 22116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 22216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 22316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic void tilcdc_crtc_commit(struct drm_crtc *crtc) 22416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 22516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 22616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 22716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 22816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic int tilcdc_crtc_mode_set(struct drm_crtc *crtc, 22916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_display_mode *mode, 23016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_display_mode *adjusted_mode, 23116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark int x, int y, 23216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_framebuffer *old_fb) 23316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 23416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 23516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_device *dev = crtc->dev; 23616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_drm_private *priv = dev->dev_private; 23716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark const struct tilcdc_panel_info *info = tilcdc_crtc->info; 23816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw; 23916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark int ret; 24016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 24116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark ret = tilcdc_crtc_mode_valid(crtc, mode); 24216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (WARN_ON(ret)) 24316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return ret; 24416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 24516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (WARN_ON(!info)) 24616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return -EINVAL; 24716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 24816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark pm_runtime_get_sync(dev->dev); 24916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 25016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* Configure the Burst Size and fifo threshold of DMA: */ 25116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770; 25216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark switch (info->dma_burst_sz) { 25316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark case 1: 25416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1); 25516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark break; 25616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark case 2: 25716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2); 25816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark break; 25916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark case 4: 26016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4); 26116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark break; 26216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark case 8: 26316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8); 26416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark break; 26516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark case 16: 26616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16); 26716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark break; 26816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark default: 26916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return -EINVAL; 27016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 27116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= (info->fifo_th << 8); 27216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg); 27316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 27416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* Configure timings: */ 27516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark hbp = mode->htotal - mode->hsync_end; 27616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark hfp = mode->hsync_start - mode->hdisplay; 27716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark hsw = mode->hsync_end - mode->hsync_start; 27816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark vbp = mode->vtotal - mode->vsync_end; 27916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark vfp = mode->vsync_start - mode->vdisplay; 28016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark vsw = mode->vsync_end - mode->vsync_start; 28116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 28216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u", 28316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw); 28416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 28516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* Configure the AC Bias Period and Number of Transitions per Interrupt: */ 28616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00; 28716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) | 28816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt); 289db2b4bd09b43fc27ecd097e193f1135f5e40d347Darren Etheridge 290db2b4bd09b43fc27ecd097e193f1135f5e40d347Darren Etheridge /* 291db2b4bd09b43fc27ecd097e193f1135f5e40d347Darren Etheridge * subtract one from hfp, hbp, hsw because the hardware uses 292db2b4bd09b43fc27ecd097e193f1135f5e40d347Darren Etheridge * a value of 0 as 1 293db2b4bd09b43fc27ecd097e193f1135f5e40d347Darren Etheridge */ 29416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (priv->rev == 2) { 295c19b3e238d7573cbe0bb60f4578b7d1de4a13746Pantelis Antoniou /* clear bits we're going to set */ 296c19b3e238d7573cbe0bb60f4578b7d1de4a13746Pantelis Antoniou reg &= ~0x78000033; 297db2b4bd09b43fc27ecd097e193f1135f5e40d347Darren Etheridge reg |= ((hfp-1) & 0x300) >> 8; 298db2b4bd09b43fc27ecd097e193f1135f5e40d347Darren Etheridge reg |= ((hbp-1) & 0x300) >> 4; 299db2b4bd09b43fc27ecd097e193f1135f5e40d347Darren Etheridge reg |= ((hsw-1) & 0x3c0) << 21; 30016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 30116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg); 30216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 30316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg = (((mode->hdisplay >> 4) - 1) << 4) | 304db2b4bd09b43fc27ecd097e193f1135f5e40d347Darren Etheridge (((hbp-1) & 0xff) << 24) | 305db2b4bd09b43fc27ecd097e193f1135f5e40d347Darren Etheridge (((hfp-1) & 0xff) << 16) | 306db2b4bd09b43fc27ecd097e193f1135f5e40d347Darren Etheridge (((hsw-1) & 0x3f) << 10); 30716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (priv->rev == 2) 30816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3; 30916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg); 31016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 31116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg = ((mode->vdisplay - 1) & 0x3ff) | 31216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark ((vbp & 0xff) << 24) | 31316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark ((vfp & 0xff) << 16) | 314db2b4bd09b43fc27ecd097e193f1135f5e40d347Darren Etheridge (((vsw-1) & 0x3f) << 10); 31516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg); 31616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 3176bf02c66b97379609a05bc715b96f874f2cefb33Darren Etheridge /* 3186bf02c66b97379609a05bc715b96f874f2cefb33Darren Etheridge * be sure to set Bit 10 for the V2 LCDC controller, 3196bf02c66b97379609a05bc715b96f874f2cefb33Darren Etheridge * otherwise limited to 1024 pixels width, stopping 3206bf02c66b97379609a05bc715b96f874f2cefb33Darren Etheridge * 1920x1080 being suppoted. 3216bf02c66b97379609a05bc715b96f874f2cefb33Darren Etheridge */ 3226bf02c66b97379609a05bc715b96f874f2cefb33Darren Etheridge if (priv->rev == 2) { 3236bf02c66b97379609a05bc715b96f874f2cefb33Darren Etheridge if ((mode->vdisplay - 1) & 0x400) { 3246bf02c66b97379609a05bc715b96f874f2cefb33Darren Etheridge tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, 3256bf02c66b97379609a05bc715b96f874f2cefb33Darren Etheridge LCDC_LPP_B10); 3266bf02c66b97379609a05bc715b96f874f2cefb33Darren Etheridge } else { 3276bf02c66b97379609a05bc715b96f874f2cefb33Darren Etheridge tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, 3286bf02c66b97379609a05bc715b96f874f2cefb33Darren Etheridge LCDC_LPP_B10); 3296bf02c66b97379609a05bc715b96f874f2cefb33Darren Etheridge } 3306bf02c66b97379609a05bc715b96f874f2cefb33Darren Etheridge } 3316bf02c66b97379609a05bc715b96f874f2cefb33Darren Etheridge 33216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* Configure display type: */ 33316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) & 33416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE | 33516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK | 0x000ff000); 33616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= LCDC_TFT_MODE; /* no monochrome/passive support */ 33716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (info->tft_alt_mode) 33816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= LCDC_TFT_ALT_ENABLE; 33916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (priv->rev == 2) { 34016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark unsigned int depth, bpp; 34116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 342f4510a2752b75ad5847b7935b68c233cab497f97Matt Roper drm_fb_get_bpp_depth(crtc->primary->fb->pixel_format, &depth, &bpp); 34316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark switch (bpp) { 34416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark case 16: 34516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark break; 34616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark case 32: 34716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= LCDC_V2_TFT_24BPP_UNPACK; 34816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* fallthrough */ 34916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark case 24: 35016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= LCDC_V2_TFT_24BPP_MODE; 35116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark break; 35216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark default: 35316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark dev_err(dev->dev, "invalid pixel format\n"); 35416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return -EINVAL; 35516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 35616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 35716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= info->fdd < 12; 35816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg); 35916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 36016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (info->invert_pxl_clk) 36116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK); 36216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark else 36316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK); 36416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 36516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (info->sync_ctrl) 36616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); 36716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark else 36816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); 36916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 37016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (info->sync_edge) 37116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE); 37216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark else 37316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE); 37416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 375a9767188678725aac99d7990025dd5b822728ba8Darren Etheridge /* 376a9767188678725aac99d7990025dd5b822728ba8Darren Etheridge * use value from adjusted_mode here as this might have been 377a9767188678725aac99d7990025dd5b822728ba8Darren Etheridge * changed as part of the fixup for slave encoders to solve the 378a9767188678725aac99d7990025dd5b822728ba8Darren Etheridge * issue where tilcdc timings are not VESA compliant 379a9767188678725aac99d7990025dd5b822728ba8Darren Etheridge */ 380a9767188678725aac99d7990025dd5b822728ba8Darren Etheridge if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 38116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC); 38216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark else 38316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC); 38416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 38516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (mode->flags & DRM_MODE_FLAG_NVSYNC) 38616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC); 38716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark else 38816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC); 38916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 39016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (info->raster_order) 39116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER); 39216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark else 39316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER); 39416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 39516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 39616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark update_scanout(crtc); 39716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc_update_clk(crtc); 39816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 39916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark pm_runtime_put_sync(dev->dev); 40016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 40116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return 0; 40216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 40316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 40416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic int tilcdc_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 40516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_framebuffer *old_fb) 40616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 40716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark update_scanout(crtc); 40816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return 0; 40916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 41016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 41116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic const struct drm_crtc_funcs tilcdc_crtc_funcs = { 41216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark .destroy = tilcdc_crtc_destroy, 41316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark .set_config = drm_crtc_helper_set_config, 41416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark .page_flip = tilcdc_crtc_page_flip, 41516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark}; 41616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 41716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = { 41816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark .dpms = tilcdc_crtc_dpms, 41916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark .mode_fixup = tilcdc_crtc_mode_fixup, 42016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark .prepare = tilcdc_crtc_prepare, 42116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark .commit = tilcdc_crtc_commit, 42216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark .mode_set = tilcdc_crtc_mode_set, 42316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark .mode_set_base = tilcdc_crtc_mode_set_base, 42416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark}; 42516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 42616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkint tilcdc_crtc_max_width(struct drm_crtc *crtc) 42716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 42816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_device *dev = crtc->dev; 42916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_drm_private *priv = dev->dev_private; 43016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark int max_width = 0; 43116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 43216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (priv->rev == 1) 43316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark max_width = 1024; 43416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark else if (priv->rev == 2) 43516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark max_width = 2048; 43616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 43716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return max_width; 43816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 43916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 44016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkint tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode) 44116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 44216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_drm_private *priv = crtc->dev->dev_private; 44316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark unsigned int bandwidth; 444e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge uint32_t hbp, hfp, hsw, vbp, vfp, vsw; 44516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 446e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge /* 447e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge * check to see if the width is within the range that 448e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge * the LCD Controller physically supports 449e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge */ 45016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (mode->hdisplay > tilcdc_crtc_max_width(crtc)) 45116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return MODE_VIRTUAL_X; 45216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 45316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* width must be multiple of 16 */ 45416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (mode->hdisplay & 0xf) 45516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return MODE_VIRTUAL_X; 45616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 45716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (mode->vdisplay > 2048) 45816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return MODE_VIRTUAL_Y; 45916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 460e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge DBG("Processing mode %dx%d@%d with pixel clock %d", 461e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge mode->hdisplay, mode->vdisplay, 462e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge drm_mode_vrefresh(mode), mode->clock); 463e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge 464e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge hbp = mode->htotal - mode->hsync_end; 465e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge hfp = mode->hsync_start - mode->hdisplay; 466e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge hsw = mode->hsync_end - mode->hsync_start; 467e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge vbp = mode->vtotal - mode->vsync_end; 468e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge vfp = mode->vsync_start - mode->vdisplay; 469e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge vsw = mode->vsync_end - mode->vsync_start; 470e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge 471e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge if ((hbp-1) & ~0x3ff) { 472e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge DBG("Pruning mode: Horizontal Back Porch out of range"); 473e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge return MODE_HBLANK_WIDE; 474e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge } 475e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge 476e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge if ((hfp-1) & ~0x3ff) { 477e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge DBG("Pruning mode: Horizontal Front Porch out of range"); 478e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge return MODE_HBLANK_WIDE; 479e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge } 480e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge 481e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge if ((hsw-1) & ~0x3ff) { 482e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge DBG("Pruning mode: Horizontal Sync Width out of range"); 483e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge return MODE_HSYNC_WIDE; 484e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge } 485e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge 486e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge if (vbp & ~0xff) { 487e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge DBG("Pruning mode: Vertical Back Porch out of range"); 488e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge return MODE_VBLANK_WIDE; 489e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge } 490e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge 491e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge if (vfp & ~0xff) { 492e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge DBG("Pruning mode: Vertical Front Porch out of range"); 493e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge return MODE_VBLANK_WIDE; 494e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge } 495e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge 496e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge if ((vsw-1) & ~0x3f) { 497e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge DBG("Pruning mode: Vertical Sync Width out of range"); 498e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge return MODE_VSYNC_WIDE; 499e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge } 500e1c5d0a819e495a79cf76a8c63c5a30c327a89a5Darren Etheridge 5014e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge /* 5024e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge * some devices have a maximum allowed pixel clock 5034e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge * configured from the DT 5044e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge */ 5054e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge if (mode->clock > priv->max_pixelclock) { 506f7b4575601dafb3cf3c568465ec6980de6d09b94Darren Etheridge DBG("Pruning mode: pixel clock too high"); 5074e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge return MODE_CLOCK_HIGH; 5084e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge } 5094e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge 5104e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge /* 5114e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge * some devices further limit the max horizontal resolution 5124e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge * configured from the DT 5134e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge */ 5144e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge if (mode->hdisplay > priv->max_width) 5154e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge return MODE_BAD_WIDTH; 5164e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge 51716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* filter out modes that would require too much memory bandwidth: */ 5184e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge bandwidth = mode->hdisplay * mode->vdisplay * 5194e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge drm_mode_vrefresh(mode); 5204e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge if (bandwidth > priv->max_bandwidth) { 521f7b4575601dafb3cf3c568465ec6980de6d09b94Darren Etheridge DBG("Pruning mode: exceeds defined bandwidth limit"); 52216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return MODE_BAD; 5234e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge } 52416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 52516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return MODE_OK; 52616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 52716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 52816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkvoid tilcdc_crtc_set_panel_info(struct drm_crtc *crtc, 52916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark const struct tilcdc_panel_info *info) 53016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 53116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 53216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->info = info; 53316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 53416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 53516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkvoid tilcdc_crtc_update_clk(struct drm_crtc *crtc) 53616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 53716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 53816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_device *dev = crtc->dev; 53916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_drm_private *priv = dev->dev_private; 54016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark int dpms = tilcdc_crtc->dpms; 54116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark unsigned int lcd_clk, div; 54216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark int ret; 54316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 54416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark pm_runtime_get_sync(dev->dev); 54516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 54616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (dpms == DRM_MODE_DPMS_ON) 54716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 54816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 54916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* in raster mode, minimum divisor is 2: */ 55016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark ret = clk_set_rate(priv->disp_clk, crtc->mode.clock * 1000 * 2); 55116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (ret) { 55216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark dev_err(dev->dev, "failed to set display clock rate to: %d\n", 55316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark crtc->mode.clock); 55416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark goto out; 55516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 55616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 55716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark lcd_clk = clk_get_rate(priv->clk); 55816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark div = lcd_clk / (crtc->mode.clock * 1000); 55916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 56016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark DBG("lcd_clk=%u, mode clock=%d, div=%u", lcd_clk, crtc->mode.clock, div); 56116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark DBG("fck=%lu, dpll_disp_ck=%lu", clk_get_rate(priv->clk), clk_get_rate(priv->disp_clk)); 56216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 56316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* Configure the LCD clock divisor. */ 56416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(div) | 56516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark LCDC_RASTER_MODE); 56616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 56716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (priv->rev == 2) 56816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_set(dev, LCDC_CLK_ENABLE_REG, 56916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN | 57016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark LCDC_V2_CORE_CLK_EN); 57116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 57216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (dpms == DRM_MODE_DPMS_ON) 57316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 57416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 57516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkout: 57616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark pm_runtime_put_sync(dev->dev); 57716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 57816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 57916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkirqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc) 58016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 58116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 58216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_device *dev = crtc->dev; 58316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_drm_private *priv = dev->dev_private; 58416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark uint32_t stat = tilcdc_read_irqstatus(dev); 58516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 58616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if ((stat & LCDC_SYNC_LOST) && (stat & LCDC_FIFO_UNDERFLOW)) { 58716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark stop(crtc); 58816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark dev_err(dev->dev, "error: %08x\n", stat); 58916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_clear_irqstatus(dev, stat); 59016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark start(crtc); 59116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } else if (stat & LCDC_PL_LOAD_DONE) { 59216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_clear_irqstatus(dev, stat); 59316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } else { 59416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_pending_vblank_event *event; 59516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark unsigned long flags; 59616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark uint32_t dirty = tilcdc_crtc->dirty & stat; 59716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 59816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_clear_irqstatus(dev, stat); 59916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 60016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (dirty & LCDC_END_OF_FRAME0) 60116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark set_scanout(crtc, 0); 60216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 60316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (dirty & LCDC_END_OF_FRAME1) 60416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark set_scanout(crtc, 1); 60516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 60616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark drm_handle_vblank(dev, 0); 60716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 60816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark spin_lock_irqsave(&dev->event_lock, flags); 60916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark event = tilcdc_crtc->event; 61016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->event = NULL; 61116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (event) 61216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark drm_send_vblank_event(dev, 0, event); 61316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark spin_unlock_irqrestore(&dev->event_lock, flags); 61416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 61516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (dirty && !tilcdc_crtc->dirty) 61616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark drm_vblank_put(dev, 0); 61716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 61816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 61916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (priv->rev == 2) { 62016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (stat & LCDC_FRAME_DONE) { 62116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->frame_done = true; 62216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark wake_up(&tilcdc_crtc->frame_done_wq); 62316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 62416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0); 62516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 62616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 62716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return IRQ_HANDLED; 62816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 62916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 63016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkvoid tilcdc_crtc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file) 63116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 63216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 63316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_pending_vblank_event *event; 63416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_device *dev = crtc->dev; 63516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark unsigned long flags; 63616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 63716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* Destroy the pending vertical blanking event associated with the 63816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * pending page flip, if any, and disable vertical blanking interrupts. 63916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark */ 64016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark spin_lock_irqsave(&dev->event_lock, flags); 64116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark event = tilcdc_crtc->event; 64216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (event && event->base.file_priv == file) { 64316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->event = NULL; 64416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark event->base.destroy(&event->base); 64516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark drm_vblank_put(dev, 0); 64616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 64716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark spin_unlock_irqrestore(&dev->event_lock, flags); 64816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 64916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 65016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstruct drm_crtc *tilcdc_crtc_create(struct drm_device *dev) 65116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 65216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_crtc *tilcdc_crtc; 65316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_crtc *crtc; 65416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark int ret; 65516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 65616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc = kzalloc(sizeof(*tilcdc_crtc), GFP_KERNEL); 65716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (!tilcdc_crtc) { 65816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark dev_err(dev->dev, "allocation failed\n"); 65916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return NULL; 66016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 66116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 66216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark crtc = &tilcdc_crtc->base; 66316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 66416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->dpms = DRM_MODE_DPMS_OFF; 66516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark init_waitqueue_head(&tilcdc_crtc->frame_done_wq); 66616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 667a464d618c715b7a850f7459754d9d155f5e60538Rob Clark ret = drm_flip_work_init(&tilcdc_crtc->unref_work, 16, 668a464d618c715b7a850f7459754d9d155f5e60538Rob Clark "unref", unref_worker); 66916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (ret) { 67016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark dev_err(dev->dev, "could not allocate unref FIFO\n"); 67116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark goto fail; 67216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 67316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 67416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark ret = drm_crtc_init(dev, crtc, &tilcdc_crtc_funcs); 67516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (ret < 0) 67616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark goto fail; 67716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 67816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs); 67916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 68016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return crtc; 68116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 68216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkfail: 68316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc_destroy(crtc); 68416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return NULL; 68516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 686