tilcdc_crtc.c revision 16ea975eac671fa40a78594a116a44fef8e3f4a9
116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark/* 216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * Copyright (C) 2012 Texas Instruments 316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * Author: Rob Clark <robdclark@gmail.com> 416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * 516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * This program is free software; you can redistribute it and/or modify it 616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * under the terms of the GNU General Public License version 2 as published by 716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * the Free Software Foundation. 816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * 916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * This program is distributed in the hope that it will be useful, but WITHOUT 1016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * more details. 1316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * 1416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * You should have received a copy of the GNU General Public License along with 1516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * this program. If not, see <http://www.gnu.org/licenses/>. 1616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark */ 1716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 1816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#include <linux/kfifo.h> 1916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 2016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#include "tilcdc_drv.h" 2116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#include "tilcdc_regs.h" 2216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 2316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstruct tilcdc_crtc { 2416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_crtc base; 2516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 2616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark const struct tilcdc_panel_info *info; 2716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark uint32_t dirty; 2816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark dma_addr_t start, end; 2916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_pending_vblank_event *event; 3016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark int dpms; 3116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark wait_queue_head_t frame_done_wq; 3216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark bool frame_done; 3316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 3416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* fb currently set to scanout 0/1: */ 3516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_framebuffer *scanout[2]; 3616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 3716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* for deferred fb unref's: */ 3816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark DECLARE_KFIFO_PTR(unref_fifo, struct drm_framebuffer *); 3916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct work_struct work; 4016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark}; 4116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base) 4216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 4316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic void unref_worker(struct work_struct *work) 4416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 4516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_crtc *tilcdc_crtc = container_of(work, struct tilcdc_crtc, work); 4616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_device *dev = tilcdc_crtc->base.dev; 4716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_framebuffer *fb; 4816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 4916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark mutex_lock(&dev->mode_config.mutex); 5016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark while (kfifo_get(&tilcdc_crtc->unref_fifo, &fb)) 5116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark drm_framebuffer_unreference(fb); 5216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark mutex_unlock(&dev->mode_config.mutex); 5316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 5416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 5516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic void set_scanout(struct drm_crtc *crtc, int n) 5616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 5716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark static const uint32_t base_reg[] = { 5816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark LCDC_DMA_FB_BASE_ADDR_0_REG, LCDC_DMA_FB_BASE_ADDR_1_REG, 5916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark }; 6016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark static const uint32_t ceil_reg[] = { 6116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark LCDC_DMA_FB_CEILING_ADDR_0_REG, LCDC_DMA_FB_CEILING_ADDR_1_REG, 6216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark }; 6316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark static const uint32_t stat[] = { 6416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark LCDC_END_OF_FRAME0, LCDC_END_OF_FRAME1, 6516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark }; 6616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 6716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_device *dev = crtc->dev; 6816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 6916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark pm_runtime_get_sync(dev->dev); 7016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_write(dev, base_reg[n], tilcdc_crtc->start); 7116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_write(dev, ceil_reg[n], tilcdc_crtc->end); 7216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (tilcdc_crtc->scanout[n]) { 7316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (kfifo_put(&tilcdc_crtc->unref_fifo, 7416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark (const struct drm_framebuffer **)&tilcdc_crtc->scanout[n])) { 7516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_drm_private *priv = dev->dev_private; 7616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark queue_work(priv->wq, &tilcdc_crtc->work); 7716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } else { 7816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark dev_err(dev->dev, "unref fifo full!\n"); 7916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark drm_framebuffer_unreference(tilcdc_crtc->scanout[n]); 8016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 8116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 8216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->scanout[n] = crtc->fb; 8316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark drm_framebuffer_reference(tilcdc_crtc->scanout[n]); 8416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->dirty &= ~stat[n]; 8516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark pm_runtime_put_sync(dev->dev); 8616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 8716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 8816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic void update_scanout(struct drm_crtc *crtc) 8916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 9016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 9116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_device *dev = crtc->dev; 9216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_framebuffer *fb = crtc->fb; 9316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_gem_cma_object *gem; 9416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark unsigned int depth, bpp; 9516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 9616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp); 9716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark gem = drm_fb_cma_get_gem_obj(fb, 0); 9816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 9916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->start = gem->paddr + fb->offsets[0] + 10016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark (crtc->y * fb->pitches[0]) + (crtc->x * bpp/8); 10116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 10216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->end = tilcdc_crtc->start + 10316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark (crtc->mode.vdisplay * fb->pitches[0]); 10416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 10516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (tilcdc_crtc->dpms == DRM_MODE_DPMS_ON) { 10616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* already enabled, so just mark the frames that need 10716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * updating and they will be updated on vblank: 10816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark */ 10916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->dirty |= LCDC_END_OF_FRAME0 | LCDC_END_OF_FRAME1; 11016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark drm_vblank_get(dev, 0); 11116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } else { 11216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* not enabled yet, so update registers immediately: */ 11316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark set_scanout(crtc, 0); 11416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark set_scanout(crtc, 1); 11516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 11616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 11716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 11816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic void start(struct drm_crtc *crtc) 11916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 12016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_device *dev = crtc->dev; 12116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_drm_private *priv = dev->dev_private; 12216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 12316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (priv->rev == 2) { 12416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET); 12516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark msleep(1); 12616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET); 12716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark msleep(1); 12816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 12916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 13016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_set(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE); 13116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_PALETTE_LOAD_MODE(DATA_ONLY)); 13216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); 13316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 13416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 13516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic void stop(struct drm_crtc *crtc) 13616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 13716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_device *dev = crtc->dev; 13816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 13916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); 14016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 14116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 14216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic void tilcdc_crtc_destroy(struct drm_crtc *crtc) 14316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 14416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 14516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 14616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark WARN_ON(tilcdc_crtc->dpms == DRM_MODE_DPMS_ON); 14716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 14816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark drm_crtc_cleanup(crtc); 14916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark WARN_ON(!kfifo_is_empty(&tilcdc_crtc->unref_fifo)); 15016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark kfifo_free(&tilcdc_crtc->unref_fifo); 15116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark kfree(tilcdc_crtc); 15216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 15316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 15416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic int tilcdc_crtc_page_flip(struct drm_crtc *crtc, 15516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_framebuffer *fb, 15616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_pending_vblank_event *event) 15716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 15816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 15916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_device *dev = crtc->dev; 16016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 16116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (tilcdc_crtc->event) { 16216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark dev_err(dev->dev, "already pending page flip!\n"); 16316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return -EBUSY; 16416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 16516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 16616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark crtc->fb = fb; 16716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->event = event; 16816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark update_scanout(crtc); 16916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 17016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return 0; 17116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 17216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 17316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode) 17416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 17516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 17616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_device *dev = crtc->dev; 17716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_drm_private *priv = dev->dev_private; 17816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 17916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* we really only care about on or off: */ 18016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (mode != DRM_MODE_DPMS_ON) 18116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark mode = DRM_MODE_DPMS_OFF; 18216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 18316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (tilcdc_crtc->dpms == mode) 18416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return; 18516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 18616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->dpms = mode; 18716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 18816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark pm_runtime_get_sync(dev->dev); 18916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 19016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (mode == DRM_MODE_DPMS_ON) { 19116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark pm_runtime_forbid(dev->dev); 19216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark start(crtc); 19316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } else { 19416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->frame_done = false; 19516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark stop(crtc); 19616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 19716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* if necessary wait for framedone irq which will still come 19816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * before putting things to sleep.. 19916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark */ 20016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (priv->rev == 2) { 20116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark int ret = wait_event_timeout( 20216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->frame_done_wq, 20316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->frame_done, 20416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark msecs_to_jiffies(50)); 20516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (ret == 0) 20616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark dev_err(dev->dev, "timeout waiting for framedone\n"); 20716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 20816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark pm_runtime_allow(dev->dev); 20916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 21016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 21116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark pm_runtime_put_sync(dev->dev); 21216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 21316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 21416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc, 21516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark const struct drm_display_mode *mode, 21616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_display_mode *adjusted_mode) 21716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 21816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return true; 21916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 22016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 22116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic void tilcdc_crtc_prepare(struct drm_crtc *crtc) 22216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 22316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 22416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 22516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 22616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic void tilcdc_crtc_commit(struct drm_crtc *crtc) 22716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 22816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 22916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 23016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 23116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic int tilcdc_crtc_mode_set(struct drm_crtc *crtc, 23216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_display_mode *mode, 23316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_display_mode *adjusted_mode, 23416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark int x, int y, 23516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_framebuffer *old_fb) 23616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 23716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 23816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_device *dev = crtc->dev; 23916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_drm_private *priv = dev->dev_private; 24016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark const struct tilcdc_panel_info *info = tilcdc_crtc->info; 24116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw; 24216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark int ret; 24316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 24416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark ret = tilcdc_crtc_mode_valid(crtc, mode); 24516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (WARN_ON(ret)) 24616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return ret; 24716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 24816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (WARN_ON(!info)) 24916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return -EINVAL; 25016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 25116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark pm_runtime_get_sync(dev->dev); 25216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 25316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* Configure the Burst Size and fifo threshold of DMA: */ 25416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770; 25516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark switch (info->dma_burst_sz) { 25616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark case 1: 25716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1); 25816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark break; 25916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark case 2: 26016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2); 26116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark break; 26216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark case 4: 26316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4); 26416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark break; 26516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark case 8: 26616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8); 26716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark break; 26816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark case 16: 26916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16); 27016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark break; 27116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark default: 27216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return -EINVAL; 27316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 27416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= (info->fifo_th << 8); 27516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg); 27616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 27716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* Configure timings: */ 27816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark hbp = mode->htotal - mode->hsync_end; 27916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark hfp = mode->hsync_start - mode->hdisplay; 28016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark hsw = mode->hsync_end - mode->hsync_start; 28116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark vbp = mode->vtotal - mode->vsync_end; 28216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark vfp = mode->vsync_start - mode->vdisplay; 28316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark vsw = mode->vsync_end - mode->vsync_start; 28416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 28516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u", 28616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw); 28716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 28816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* Configure the AC Bias Period and Number of Transitions per Interrupt: */ 28916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00; 29016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) | 29116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt); 29216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (priv->rev == 2) { 29316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= (hfp & 0x300) >> 8; 29416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= (hbp & 0x300) >> 4; 29516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= (hsw & 0x3c0) << 21; 29616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 29716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg); 29816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 29916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg = (((mode->hdisplay >> 4) - 1) << 4) | 30016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark ((hbp & 0xff) << 24) | 30116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark ((hfp & 0xff) << 16) | 30216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark ((hsw & 0x3f) << 10); 30316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (priv->rev == 2) 30416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3; 30516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg); 30616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 30716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg = ((mode->vdisplay - 1) & 0x3ff) | 30816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark ((vbp & 0xff) << 24) | 30916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark ((vfp & 0xff) << 16) | 31016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark ((vsw & 0x3f) << 10); 31116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg); 31216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 31316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* Configure display type: */ 31416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) & 31516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE | 31616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK | 0x000ff000); 31716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= LCDC_TFT_MODE; /* no monochrome/passive support */ 31816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (info->tft_alt_mode) 31916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= LCDC_TFT_ALT_ENABLE; 32016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (priv->rev == 2) { 32116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark unsigned int depth, bpp; 32216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 32316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark drm_fb_get_bpp_depth(crtc->fb->pixel_format, &depth, &bpp); 32416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark switch (bpp) { 32516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark case 16: 32616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark break; 32716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark case 32: 32816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= LCDC_V2_TFT_24BPP_UNPACK; 32916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* fallthrough */ 33016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark case 24: 33116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= LCDC_V2_TFT_24BPP_MODE; 33216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark break; 33316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark default: 33416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark dev_err(dev->dev, "invalid pixel format\n"); 33516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return -EINVAL; 33616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 33716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 33816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark reg |= info->fdd < 12; 33916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg); 34016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 34116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (info->invert_pxl_clk) 34216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK); 34316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark else 34416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK); 34516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 34616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (info->sync_ctrl) 34716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); 34816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark else 34916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); 35016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 35116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (info->sync_edge) 35216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE); 35316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark else 35416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE); 35516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 35616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (mode->flags & DRM_MODE_FLAG_NHSYNC) 35716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC); 35816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark else 35916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC); 36016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 36116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (mode->flags & DRM_MODE_FLAG_NVSYNC) 36216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC); 36316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark else 36416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC); 36516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 36616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (info->raster_order) 36716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER); 36816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark else 36916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER); 37016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 37116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 37216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark update_scanout(crtc); 37316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc_update_clk(crtc); 37416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 37516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark pm_runtime_put_sync(dev->dev); 37616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 37716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return 0; 37816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 37916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 38016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic int tilcdc_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 38116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_framebuffer *old_fb) 38216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 38316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark update_scanout(crtc); 38416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return 0; 38516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 38616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 38716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic void tilcdc_crtc_load_lut(struct drm_crtc *crtc) 38816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 38916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 39016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 39116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic const struct drm_crtc_funcs tilcdc_crtc_funcs = { 39216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark .destroy = tilcdc_crtc_destroy, 39316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark .set_config = drm_crtc_helper_set_config, 39416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark .page_flip = tilcdc_crtc_page_flip, 39516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark}; 39616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 39716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstatic const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = { 39816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark .dpms = tilcdc_crtc_dpms, 39916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark .mode_fixup = tilcdc_crtc_mode_fixup, 40016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark .prepare = tilcdc_crtc_prepare, 40116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark .commit = tilcdc_crtc_commit, 40216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark .mode_set = tilcdc_crtc_mode_set, 40316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark .mode_set_base = tilcdc_crtc_mode_set_base, 40416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark .load_lut = tilcdc_crtc_load_lut, 40516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark}; 40616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 40716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkint tilcdc_crtc_max_width(struct drm_crtc *crtc) 40816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 40916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_device *dev = crtc->dev; 41016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_drm_private *priv = dev->dev_private; 41116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark int max_width = 0; 41216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 41316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (priv->rev == 1) 41416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark max_width = 1024; 41516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark else if (priv->rev == 2) 41616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark max_width = 2048; 41716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 41816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return max_width; 41916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 42016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 42116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkint tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode) 42216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 42316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_drm_private *priv = crtc->dev->dev_private; 42416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark unsigned int bandwidth; 42516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 42616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (mode->hdisplay > tilcdc_crtc_max_width(crtc)) 42716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return MODE_VIRTUAL_X; 42816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 42916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* width must be multiple of 16 */ 43016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (mode->hdisplay & 0xf) 43116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return MODE_VIRTUAL_X; 43216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 43316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (mode->vdisplay > 2048) 43416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return MODE_VIRTUAL_Y; 43516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 43616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* filter out modes that would require too much memory bandwidth: */ 43716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark bandwidth = mode->hdisplay * mode->vdisplay * drm_mode_vrefresh(mode); 43816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (bandwidth > priv->max_bandwidth) 43916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return MODE_BAD; 44016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 44116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return MODE_OK; 44216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 44316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 44416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkvoid tilcdc_crtc_set_panel_info(struct drm_crtc *crtc, 44516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark const struct tilcdc_panel_info *info) 44616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 44716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 44816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->info = info; 44916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 45016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 45116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkvoid tilcdc_crtc_update_clk(struct drm_crtc *crtc) 45216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 45316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 45416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_device *dev = crtc->dev; 45516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_drm_private *priv = dev->dev_private; 45616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark int dpms = tilcdc_crtc->dpms; 45716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark unsigned int lcd_clk, div; 45816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark int ret; 45916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 46016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark pm_runtime_get_sync(dev->dev); 46116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 46216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (dpms == DRM_MODE_DPMS_ON) 46316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 46416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 46516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* in raster mode, minimum divisor is 2: */ 46616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark ret = clk_set_rate(priv->disp_clk, crtc->mode.clock * 1000 * 2); 46716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (ret) { 46816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark dev_err(dev->dev, "failed to set display clock rate to: %d\n", 46916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark crtc->mode.clock); 47016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark goto out; 47116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 47216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 47316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark lcd_clk = clk_get_rate(priv->clk); 47416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark div = lcd_clk / (crtc->mode.clock * 1000); 47516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 47616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark DBG("lcd_clk=%u, mode clock=%d, div=%u", lcd_clk, crtc->mode.clock, div); 47716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark DBG("fck=%lu, dpll_disp_ck=%lu", clk_get_rate(priv->clk), clk_get_rate(priv->disp_clk)); 47816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 47916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* Configure the LCD clock divisor. */ 48016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(div) | 48116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark LCDC_RASTER_MODE); 48216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 48316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (priv->rev == 2) 48416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_set(dev, LCDC_CLK_ENABLE_REG, 48516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN | 48616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark LCDC_V2_CORE_CLK_EN); 48716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 48816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (dpms == DRM_MODE_DPMS_ON) 48916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 49016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 49116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkout: 49216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark pm_runtime_put_sync(dev->dev); 49316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 49416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 49516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkirqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc) 49616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 49716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 49816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_device *dev = crtc->dev; 49916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_drm_private *priv = dev->dev_private; 50016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark uint32_t stat = tilcdc_read_irqstatus(dev); 50116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 50216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if ((stat & LCDC_SYNC_LOST) && (stat & LCDC_FIFO_UNDERFLOW)) { 50316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark stop(crtc); 50416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark dev_err(dev->dev, "error: %08x\n", stat); 50516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_clear_irqstatus(dev, stat); 50616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark start(crtc); 50716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } else if (stat & LCDC_PL_LOAD_DONE) { 50816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_clear_irqstatus(dev, stat); 50916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } else { 51016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_pending_vblank_event *event; 51116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark unsigned long flags; 51216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark uint32_t dirty = tilcdc_crtc->dirty & stat; 51316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 51416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_clear_irqstatus(dev, stat); 51516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 51616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (dirty & LCDC_END_OF_FRAME0) 51716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark set_scanout(crtc, 0); 51816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 51916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (dirty & LCDC_END_OF_FRAME1) 52016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark set_scanout(crtc, 1); 52116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 52216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark drm_handle_vblank(dev, 0); 52316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 52416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark spin_lock_irqsave(&dev->event_lock, flags); 52516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark event = tilcdc_crtc->event; 52616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->event = NULL; 52716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (event) 52816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark drm_send_vblank_event(dev, 0, event); 52916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark spin_unlock_irqrestore(&dev->event_lock, flags); 53016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 53116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (dirty && !tilcdc_crtc->dirty) 53216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark drm_vblank_put(dev, 0); 53316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 53416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 53516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (priv->rev == 2) { 53616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (stat & LCDC_FRAME_DONE) { 53716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->frame_done = true; 53816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark wake_up(&tilcdc_crtc->frame_done_wq); 53916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 54016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0); 54116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 54216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 54316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return IRQ_HANDLED; 54416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 54516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 54616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkvoid tilcdc_crtc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file) 54716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 54816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 54916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_pending_vblank_event *event; 55016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_device *dev = crtc->dev; 55116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark unsigned long flags; 55216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 55316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* Destroy the pending vertical blanking event associated with the 55416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * pending page flip, if any, and disable vertical blanking interrupts. 55516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark */ 55616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark spin_lock_irqsave(&dev->event_lock, flags); 55716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark event = tilcdc_crtc->event; 55816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (event && event->base.file_priv == file) { 55916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->event = NULL; 56016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark event->base.destroy(&event->base); 56116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark drm_vblank_put(dev, 0); 56216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 56316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark spin_unlock_irqrestore(&dev->event_lock, flags); 56416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 56516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 56616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstruct drm_crtc *tilcdc_crtc_create(struct drm_device *dev) 56716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark{ 56816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct tilcdc_crtc *tilcdc_crtc; 56916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_crtc *crtc; 57016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark int ret; 57116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 57216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc = kzalloc(sizeof(*tilcdc_crtc), GFP_KERNEL); 57316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (!tilcdc_crtc) { 57416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark dev_err(dev->dev, "allocation failed\n"); 57516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return NULL; 57616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 57716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 57816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark crtc = &tilcdc_crtc->base; 57916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 58016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc->dpms = DRM_MODE_DPMS_OFF; 58116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark init_waitqueue_head(&tilcdc_crtc->frame_done_wq); 58216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 58316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark ret = kfifo_alloc(&tilcdc_crtc->unref_fifo, 16, GFP_KERNEL); 58416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (ret) { 58516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark dev_err(dev->dev, "could not allocate unref FIFO\n"); 58616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark goto fail; 58716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark } 58816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 58916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark INIT_WORK(&tilcdc_crtc->work, unref_worker); 59016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 59116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark ret = drm_crtc_init(dev, crtc, &tilcdc_crtc_funcs); 59216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark if (ret < 0) 59316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark goto fail; 59416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 59516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs); 59616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 59716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return crtc; 59816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 59916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkfail: 60016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark tilcdc_crtc_destroy(crtc); 60116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark return NULL; 60216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark} 603