tilcdc_crtc.c revision 6bf02c66b97379609a05bc715b96f874f2cefb33
1/* 2 * Copyright (C) 2012 Texas Instruments 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18#include <linux/kfifo.h> 19 20#include "tilcdc_drv.h" 21#include "tilcdc_regs.h" 22 23struct tilcdc_crtc { 24 struct drm_crtc base; 25 26 const struct tilcdc_panel_info *info; 27 uint32_t dirty; 28 dma_addr_t start, end; 29 struct drm_pending_vblank_event *event; 30 int dpms; 31 wait_queue_head_t frame_done_wq; 32 bool frame_done; 33 34 /* fb currently set to scanout 0/1: */ 35 struct drm_framebuffer *scanout[2]; 36 37 /* for deferred fb unref's: */ 38 DECLARE_KFIFO_PTR(unref_fifo, struct drm_framebuffer *); 39 struct work_struct work; 40}; 41#define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base) 42 43static void unref_worker(struct work_struct *work) 44{ 45 struct tilcdc_crtc *tilcdc_crtc = container_of(work, struct tilcdc_crtc, work); 46 struct drm_device *dev = tilcdc_crtc->base.dev; 47 struct drm_framebuffer *fb; 48 49 mutex_lock(&dev->mode_config.mutex); 50 while (kfifo_get(&tilcdc_crtc->unref_fifo, &fb)) 51 drm_framebuffer_unreference(fb); 52 mutex_unlock(&dev->mode_config.mutex); 53} 54 55static void set_scanout(struct drm_crtc *crtc, int n) 56{ 57 static const uint32_t base_reg[] = { 58 LCDC_DMA_FB_BASE_ADDR_0_REG, LCDC_DMA_FB_BASE_ADDR_1_REG, 59 }; 60 static const uint32_t ceil_reg[] = { 61 LCDC_DMA_FB_CEILING_ADDR_0_REG, LCDC_DMA_FB_CEILING_ADDR_1_REG, 62 }; 63 static const uint32_t stat[] = { 64 LCDC_END_OF_FRAME0, LCDC_END_OF_FRAME1, 65 }; 66 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 67 struct drm_device *dev = crtc->dev; 68 69 pm_runtime_get_sync(dev->dev); 70 tilcdc_write(dev, base_reg[n], tilcdc_crtc->start); 71 tilcdc_write(dev, ceil_reg[n], tilcdc_crtc->end); 72 if (tilcdc_crtc->scanout[n]) { 73 if (kfifo_put(&tilcdc_crtc->unref_fifo, 74 (const struct drm_framebuffer **)&tilcdc_crtc->scanout[n])) { 75 struct tilcdc_drm_private *priv = dev->dev_private; 76 queue_work(priv->wq, &tilcdc_crtc->work); 77 } else { 78 dev_err(dev->dev, "unref fifo full!\n"); 79 drm_framebuffer_unreference(tilcdc_crtc->scanout[n]); 80 } 81 } 82 tilcdc_crtc->scanout[n] = crtc->fb; 83 drm_framebuffer_reference(tilcdc_crtc->scanout[n]); 84 tilcdc_crtc->dirty &= ~stat[n]; 85 pm_runtime_put_sync(dev->dev); 86} 87 88static void update_scanout(struct drm_crtc *crtc) 89{ 90 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 91 struct drm_device *dev = crtc->dev; 92 struct drm_framebuffer *fb = crtc->fb; 93 struct drm_gem_cma_object *gem; 94 unsigned int depth, bpp; 95 96 drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp); 97 gem = drm_fb_cma_get_gem_obj(fb, 0); 98 99 tilcdc_crtc->start = gem->paddr + fb->offsets[0] + 100 (crtc->y * fb->pitches[0]) + (crtc->x * bpp/8); 101 102 tilcdc_crtc->end = tilcdc_crtc->start + 103 (crtc->mode.vdisplay * fb->pitches[0]); 104 105 if (tilcdc_crtc->dpms == DRM_MODE_DPMS_ON) { 106 /* already enabled, so just mark the frames that need 107 * updating and they will be updated on vblank: 108 */ 109 tilcdc_crtc->dirty |= LCDC_END_OF_FRAME0 | LCDC_END_OF_FRAME1; 110 drm_vblank_get(dev, 0); 111 } else { 112 /* not enabled yet, so update registers immediately: */ 113 set_scanout(crtc, 0); 114 set_scanout(crtc, 1); 115 } 116} 117 118static void start(struct drm_crtc *crtc) 119{ 120 struct drm_device *dev = crtc->dev; 121 struct tilcdc_drm_private *priv = dev->dev_private; 122 123 if (priv->rev == 2) { 124 tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET); 125 msleep(1); 126 tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET); 127 msleep(1); 128 } 129 130 tilcdc_set(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE); 131 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_PALETTE_LOAD_MODE(DATA_ONLY)); 132 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); 133} 134 135static void stop(struct drm_crtc *crtc) 136{ 137 struct drm_device *dev = crtc->dev; 138 139 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); 140} 141 142static void tilcdc_crtc_destroy(struct drm_crtc *crtc) 143{ 144 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 145 146 WARN_ON(tilcdc_crtc->dpms == DRM_MODE_DPMS_ON); 147 148 drm_crtc_cleanup(crtc); 149 WARN_ON(!kfifo_is_empty(&tilcdc_crtc->unref_fifo)); 150 kfifo_free(&tilcdc_crtc->unref_fifo); 151 kfree(tilcdc_crtc); 152} 153 154static int tilcdc_crtc_page_flip(struct drm_crtc *crtc, 155 struct drm_framebuffer *fb, 156 struct drm_pending_vblank_event *event) 157{ 158 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 159 struct drm_device *dev = crtc->dev; 160 161 if (tilcdc_crtc->event) { 162 dev_err(dev->dev, "already pending page flip!\n"); 163 return -EBUSY; 164 } 165 166 crtc->fb = fb; 167 tilcdc_crtc->event = event; 168 update_scanout(crtc); 169 170 return 0; 171} 172 173static void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode) 174{ 175 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 176 struct drm_device *dev = crtc->dev; 177 struct tilcdc_drm_private *priv = dev->dev_private; 178 179 /* we really only care about on or off: */ 180 if (mode != DRM_MODE_DPMS_ON) 181 mode = DRM_MODE_DPMS_OFF; 182 183 if (tilcdc_crtc->dpms == mode) 184 return; 185 186 tilcdc_crtc->dpms = mode; 187 188 pm_runtime_get_sync(dev->dev); 189 190 if (mode == DRM_MODE_DPMS_ON) { 191 pm_runtime_forbid(dev->dev); 192 start(crtc); 193 } else { 194 tilcdc_crtc->frame_done = false; 195 stop(crtc); 196 197 /* if necessary wait for framedone irq which will still come 198 * before putting things to sleep.. 199 */ 200 if (priv->rev == 2) { 201 int ret = wait_event_timeout( 202 tilcdc_crtc->frame_done_wq, 203 tilcdc_crtc->frame_done, 204 msecs_to_jiffies(50)); 205 if (ret == 0) 206 dev_err(dev->dev, "timeout waiting for framedone\n"); 207 } 208 pm_runtime_allow(dev->dev); 209 } 210 211 pm_runtime_put_sync(dev->dev); 212} 213 214static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc, 215 const struct drm_display_mode *mode, 216 struct drm_display_mode *adjusted_mode) 217{ 218 return true; 219} 220 221static void tilcdc_crtc_prepare(struct drm_crtc *crtc) 222{ 223 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 224} 225 226static void tilcdc_crtc_commit(struct drm_crtc *crtc) 227{ 228 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 229} 230 231static int tilcdc_crtc_mode_set(struct drm_crtc *crtc, 232 struct drm_display_mode *mode, 233 struct drm_display_mode *adjusted_mode, 234 int x, int y, 235 struct drm_framebuffer *old_fb) 236{ 237 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 238 struct drm_device *dev = crtc->dev; 239 struct tilcdc_drm_private *priv = dev->dev_private; 240 const struct tilcdc_panel_info *info = tilcdc_crtc->info; 241 uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw; 242 int ret; 243 244 ret = tilcdc_crtc_mode_valid(crtc, mode); 245 if (WARN_ON(ret)) 246 return ret; 247 248 if (WARN_ON(!info)) 249 return -EINVAL; 250 251 pm_runtime_get_sync(dev->dev); 252 253 /* Configure the Burst Size and fifo threshold of DMA: */ 254 reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770; 255 switch (info->dma_burst_sz) { 256 case 1: 257 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1); 258 break; 259 case 2: 260 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2); 261 break; 262 case 4: 263 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4); 264 break; 265 case 8: 266 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8); 267 break; 268 case 16: 269 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16); 270 break; 271 default: 272 return -EINVAL; 273 } 274 reg |= (info->fifo_th << 8); 275 tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg); 276 277 /* Configure timings: */ 278 hbp = mode->htotal - mode->hsync_end; 279 hfp = mode->hsync_start - mode->hdisplay; 280 hsw = mode->hsync_end - mode->hsync_start; 281 vbp = mode->vtotal - mode->vsync_end; 282 vfp = mode->vsync_start - mode->vdisplay; 283 vsw = mode->vsync_end - mode->vsync_start; 284 285 DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u", 286 mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw); 287 288 /* Configure the AC Bias Period and Number of Transitions per Interrupt: */ 289 reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00; 290 reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) | 291 LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt); 292 if (priv->rev == 2) { 293 reg |= (hfp & 0x300) >> 8; 294 reg |= (hbp & 0x300) >> 4; 295 reg |= (hsw & 0x3c0) << 21; 296 } 297 tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg); 298 299 reg = (((mode->hdisplay >> 4) - 1) << 4) | 300 ((hbp & 0xff) << 24) | 301 ((hfp & 0xff) << 16) | 302 ((hsw & 0x3f) << 10); 303 if (priv->rev == 2) 304 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3; 305 tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg); 306 307 reg = ((mode->vdisplay - 1) & 0x3ff) | 308 ((vbp & 0xff) << 24) | 309 ((vfp & 0xff) << 16) | 310 ((vsw & 0x3f) << 10); 311 tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg); 312 313 /* 314 * be sure to set Bit 10 for the V2 LCDC controller, 315 * otherwise limited to 1024 pixels width, stopping 316 * 1920x1080 being suppoted. 317 */ 318 if (priv->rev == 2) { 319 if ((mode->vdisplay - 1) & 0x400) { 320 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, 321 LCDC_LPP_B10); 322 } else { 323 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, 324 LCDC_LPP_B10); 325 } 326 } 327 328 /* Configure display type: */ 329 reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) & 330 ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE | 331 LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK | 0x000ff000); 332 reg |= LCDC_TFT_MODE; /* no monochrome/passive support */ 333 if (info->tft_alt_mode) 334 reg |= LCDC_TFT_ALT_ENABLE; 335 if (priv->rev == 2) { 336 unsigned int depth, bpp; 337 338 drm_fb_get_bpp_depth(crtc->fb->pixel_format, &depth, &bpp); 339 switch (bpp) { 340 case 16: 341 break; 342 case 32: 343 reg |= LCDC_V2_TFT_24BPP_UNPACK; 344 /* fallthrough */ 345 case 24: 346 reg |= LCDC_V2_TFT_24BPP_MODE; 347 break; 348 default: 349 dev_err(dev->dev, "invalid pixel format\n"); 350 return -EINVAL; 351 } 352 } 353 reg |= info->fdd < 12; 354 tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg); 355 356 if (info->invert_pxl_clk) 357 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK); 358 else 359 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK); 360 361 if (info->sync_ctrl) 362 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); 363 else 364 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); 365 366 if (info->sync_edge) 367 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE); 368 else 369 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE); 370 371 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 372 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC); 373 else 374 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC); 375 376 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 377 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC); 378 else 379 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC); 380 381 if (info->raster_order) 382 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER); 383 else 384 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER); 385 386 387 update_scanout(crtc); 388 tilcdc_crtc_update_clk(crtc); 389 390 pm_runtime_put_sync(dev->dev); 391 392 return 0; 393} 394 395static int tilcdc_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 396 struct drm_framebuffer *old_fb) 397{ 398 update_scanout(crtc); 399 return 0; 400} 401 402static const struct drm_crtc_funcs tilcdc_crtc_funcs = { 403 .destroy = tilcdc_crtc_destroy, 404 .set_config = drm_crtc_helper_set_config, 405 .page_flip = tilcdc_crtc_page_flip, 406}; 407 408static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = { 409 .dpms = tilcdc_crtc_dpms, 410 .mode_fixup = tilcdc_crtc_mode_fixup, 411 .prepare = tilcdc_crtc_prepare, 412 .commit = tilcdc_crtc_commit, 413 .mode_set = tilcdc_crtc_mode_set, 414 .mode_set_base = tilcdc_crtc_mode_set_base, 415}; 416 417int tilcdc_crtc_max_width(struct drm_crtc *crtc) 418{ 419 struct drm_device *dev = crtc->dev; 420 struct tilcdc_drm_private *priv = dev->dev_private; 421 int max_width = 0; 422 423 if (priv->rev == 1) 424 max_width = 1024; 425 else if (priv->rev == 2) 426 max_width = 2048; 427 428 return max_width; 429} 430 431int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode) 432{ 433 struct tilcdc_drm_private *priv = crtc->dev->dev_private; 434 unsigned int bandwidth; 435 436 if (mode->hdisplay > tilcdc_crtc_max_width(crtc)) 437 return MODE_VIRTUAL_X; 438 439 /* width must be multiple of 16 */ 440 if (mode->hdisplay & 0xf) 441 return MODE_VIRTUAL_X; 442 443 if (mode->vdisplay > 2048) 444 return MODE_VIRTUAL_Y; 445 446 /* filter out modes that would require too much memory bandwidth: */ 447 bandwidth = mode->hdisplay * mode->vdisplay * drm_mode_vrefresh(mode); 448 if (bandwidth > priv->max_bandwidth) 449 return MODE_BAD; 450 451 return MODE_OK; 452} 453 454void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc, 455 const struct tilcdc_panel_info *info) 456{ 457 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 458 tilcdc_crtc->info = info; 459} 460 461void tilcdc_crtc_update_clk(struct drm_crtc *crtc) 462{ 463 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 464 struct drm_device *dev = crtc->dev; 465 struct tilcdc_drm_private *priv = dev->dev_private; 466 int dpms = tilcdc_crtc->dpms; 467 unsigned int lcd_clk, div; 468 int ret; 469 470 pm_runtime_get_sync(dev->dev); 471 472 if (dpms == DRM_MODE_DPMS_ON) 473 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 474 475 /* in raster mode, minimum divisor is 2: */ 476 ret = clk_set_rate(priv->disp_clk, crtc->mode.clock * 1000 * 2); 477 if (ret) { 478 dev_err(dev->dev, "failed to set display clock rate to: %d\n", 479 crtc->mode.clock); 480 goto out; 481 } 482 483 lcd_clk = clk_get_rate(priv->clk); 484 div = lcd_clk / (crtc->mode.clock * 1000); 485 486 DBG("lcd_clk=%u, mode clock=%d, div=%u", lcd_clk, crtc->mode.clock, div); 487 DBG("fck=%lu, dpll_disp_ck=%lu", clk_get_rate(priv->clk), clk_get_rate(priv->disp_clk)); 488 489 /* Configure the LCD clock divisor. */ 490 tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(div) | 491 LCDC_RASTER_MODE); 492 493 if (priv->rev == 2) 494 tilcdc_set(dev, LCDC_CLK_ENABLE_REG, 495 LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN | 496 LCDC_V2_CORE_CLK_EN); 497 498 if (dpms == DRM_MODE_DPMS_ON) 499 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 500 501out: 502 pm_runtime_put_sync(dev->dev); 503} 504 505irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc) 506{ 507 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 508 struct drm_device *dev = crtc->dev; 509 struct tilcdc_drm_private *priv = dev->dev_private; 510 uint32_t stat = tilcdc_read_irqstatus(dev); 511 512 if ((stat & LCDC_SYNC_LOST) && (stat & LCDC_FIFO_UNDERFLOW)) { 513 stop(crtc); 514 dev_err(dev->dev, "error: %08x\n", stat); 515 tilcdc_clear_irqstatus(dev, stat); 516 start(crtc); 517 } else if (stat & LCDC_PL_LOAD_DONE) { 518 tilcdc_clear_irqstatus(dev, stat); 519 } else { 520 struct drm_pending_vblank_event *event; 521 unsigned long flags; 522 uint32_t dirty = tilcdc_crtc->dirty & stat; 523 524 tilcdc_clear_irqstatus(dev, stat); 525 526 if (dirty & LCDC_END_OF_FRAME0) 527 set_scanout(crtc, 0); 528 529 if (dirty & LCDC_END_OF_FRAME1) 530 set_scanout(crtc, 1); 531 532 drm_handle_vblank(dev, 0); 533 534 spin_lock_irqsave(&dev->event_lock, flags); 535 event = tilcdc_crtc->event; 536 tilcdc_crtc->event = NULL; 537 if (event) 538 drm_send_vblank_event(dev, 0, event); 539 spin_unlock_irqrestore(&dev->event_lock, flags); 540 541 if (dirty && !tilcdc_crtc->dirty) 542 drm_vblank_put(dev, 0); 543 } 544 545 if (priv->rev == 2) { 546 if (stat & LCDC_FRAME_DONE) { 547 tilcdc_crtc->frame_done = true; 548 wake_up(&tilcdc_crtc->frame_done_wq); 549 } 550 tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0); 551 } 552 553 return IRQ_HANDLED; 554} 555 556void tilcdc_crtc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file) 557{ 558 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 559 struct drm_pending_vblank_event *event; 560 struct drm_device *dev = crtc->dev; 561 unsigned long flags; 562 563 /* Destroy the pending vertical blanking event associated with the 564 * pending page flip, if any, and disable vertical blanking interrupts. 565 */ 566 spin_lock_irqsave(&dev->event_lock, flags); 567 event = tilcdc_crtc->event; 568 if (event && event->base.file_priv == file) { 569 tilcdc_crtc->event = NULL; 570 event->base.destroy(&event->base); 571 drm_vblank_put(dev, 0); 572 } 573 spin_unlock_irqrestore(&dev->event_lock, flags); 574} 575 576struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev) 577{ 578 struct tilcdc_crtc *tilcdc_crtc; 579 struct drm_crtc *crtc; 580 int ret; 581 582 tilcdc_crtc = kzalloc(sizeof(*tilcdc_crtc), GFP_KERNEL); 583 if (!tilcdc_crtc) { 584 dev_err(dev->dev, "allocation failed\n"); 585 return NULL; 586 } 587 588 crtc = &tilcdc_crtc->base; 589 590 tilcdc_crtc->dpms = DRM_MODE_DPMS_OFF; 591 init_waitqueue_head(&tilcdc_crtc->frame_done_wq); 592 593 ret = kfifo_alloc(&tilcdc_crtc->unref_fifo, 16, GFP_KERNEL); 594 if (ret) { 595 dev_err(dev->dev, "could not allocate unref FIFO\n"); 596 goto fail; 597 } 598 599 INIT_WORK(&tilcdc_crtc->work, unref_worker); 600 601 ret = drm_crtc_init(dev, crtc, &tilcdc_crtc_funcs); 602 if (ret < 0) 603 goto fail; 604 605 drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs); 606 607 return crtc; 608 609fail: 610 tilcdc_crtc_destroy(crtc); 611 return NULL; 612} 613