tilcdc_crtc.c revision a464d618c715b7a850f7459754d9d155f5e60538
1/* 2 * Copyright (C) 2012 Texas Instruments 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18#include "drm_flip_work.h" 19 20#include "tilcdc_drv.h" 21#include "tilcdc_regs.h" 22 23struct tilcdc_crtc { 24 struct drm_crtc base; 25 26 const struct tilcdc_panel_info *info; 27 uint32_t dirty; 28 dma_addr_t start, end; 29 struct drm_pending_vblank_event *event; 30 int dpms; 31 wait_queue_head_t frame_done_wq; 32 bool frame_done; 33 34 /* fb currently set to scanout 0/1: */ 35 struct drm_framebuffer *scanout[2]; 36 37 /* for deferred fb unref's: */ 38 struct drm_flip_work unref_work; 39}; 40#define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base) 41 42static void unref_worker(struct drm_flip_work *work, void *val) 43{ 44 struct tilcdc_crtc *tilcdc_crtc = 45 container_of(work, struct tilcdc_crtc, unref_work); 46 struct drm_device *dev = tilcdc_crtc->base.dev; 47 48 mutex_lock(&dev->mode_config.mutex); 49 drm_framebuffer_unreference(val); 50 mutex_unlock(&dev->mode_config.mutex); 51} 52 53static void set_scanout(struct drm_crtc *crtc, int n) 54{ 55 static const uint32_t base_reg[] = { 56 LCDC_DMA_FB_BASE_ADDR_0_REG, 57 LCDC_DMA_FB_BASE_ADDR_1_REG, 58 }; 59 static const uint32_t ceil_reg[] = { 60 LCDC_DMA_FB_CEILING_ADDR_0_REG, 61 LCDC_DMA_FB_CEILING_ADDR_1_REG, 62 }; 63 static const uint32_t stat[] = { 64 LCDC_END_OF_FRAME0, LCDC_END_OF_FRAME1, 65 }; 66 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 67 struct drm_device *dev = crtc->dev; 68 struct tilcdc_drm_private *priv = dev->dev_private; 69 70 pm_runtime_get_sync(dev->dev); 71 tilcdc_write(dev, base_reg[n], tilcdc_crtc->start); 72 tilcdc_write(dev, ceil_reg[n], tilcdc_crtc->end); 73 if (tilcdc_crtc->scanout[n]) { 74 drm_flip_work_queue(&tilcdc_crtc->unref_work, tilcdc_crtc->scanout[n]); 75 drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq); 76 } 77 tilcdc_crtc->scanout[n] = crtc->fb; 78 drm_framebuffer_reference(tilcdc_crtc->scanout[n]); 79 tilcdc_crtc->dirty &= ~stat[n]; 80 pm_runtime_put_sync(dev->dev); 81} 82 83static void update_scanout(struct drm_crtc *crtc) 84{ 85 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 86 struct drm_device *dev = crtc->dev; 87 struct drm_framebuffer *fb = crtc->fb; 88 struct drm_gem_cma_object *gem; 89 unsigned int depth, bpp; 90 91 drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp); 92 gem = drm_fb_cma_get_gem_obj(fb, 0); 93 94 tilcdc_crtc->start = gem->paddr + fb->offsets[0] + 95 (crtc->y * fb->pitches[0]) + (crtc->x * bpp/8); 96 97 tilcdc_crtc->end = tilcdc_crtc->start + 98 (crtc->mode.vdisplay * fb->pitches[0]); 99 100 if (tilcdc_crtc->dpms == DRM_MODE_DPMS_ON) { 101 /* already enabled, so just mark the frames that need 102 * updating and they will be updated on vblank: 103 */ 104 tilcdc_crtc->dirty |= LCDC_END_OF_FRAME0 | LCDC_END_OF_FRAME1; 105 drm_vblank_get(dev, 0); 106 } else { 107 /* not enabled yet, so update registers immediately: */ 108 set_scanout(crtc, 0); 109 set_scanout(crtc, 1); 110 } 111} 112 113static void start(struct drm_crtc *crtc) 114{ 115 struct drm_device *dev = crtc->dev; 116 struct tilcdc_drm_private *priv = dev->dev_private; 117 118 if (priv->rev == 2) { 119 tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET); 120 msleep(1); 121 tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET); 122 msleep(1); 123 } 124 125 tilcdc_set(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE); 126 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_PALETTE_LOAD_MODE(DATA_ONLY)); 127 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); 128} 129 130static void stop(struct drm_crtc *crtc) 131{ 132 struct drm_device *dev = crtc->dev; 133 134 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); 135} 136 137static void tilcdc_crtc_destroy(struct drm_crtc *crtc) 138{ 139 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 140 141 WARN_ON(tilcdc_crtc->dpms == DRM_MODE_DPMS_ON); 142 143 drm_crtc_cleanup(crtc); 144 drm_flip_work_cleanup(&tilcdc_crtc->unref_work); 145 146 kfree(tilcdc_crtc); 147} 148 149static int tilcdc_crtc_page_flip(struct drm_crtc *crtc, 150 struct drm_framebuffer *fb, 151 struct drm_pending_vblank_event *event) 152{ 153 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 154 struct drm_device *dev = crtc->dev; 155 156 if (tilcdc_crtc->event) { 157 dev_err(dev->dev, "already pending page flip!\n"); 158 return -EBUSY; 159 } 160 161 crtc->fb = fb; 162 tilcdc_crtc->event = event; 163 update_scanout(crtc); 164 165 return 0; 166} 167 168static void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode) 169{ 170 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 171 struct drm_device *dev = crtc->dev; 172 struct tilcdc_drm_private *priv = dev->dev_private; 173 174 /* we really only care about on or off: */ 175 if (mode != DRM_MODE_DPMS_ON) 176 mode = DRM_MODE_DPMS_OFF; 177 178 if (tilcdc_crtc->dpms == mode) 179 return; 180 181 tilcdc_crtc->dpms = mode; 182 183 pm_runtime_get_sync(dev->dev); 184 185 if (mode == DRM_MODE_DPMS_ON) { 186 pm_runtime_forbid(dev->dev); 187 start(crtc); 188 } else { 189 tilcdc_crtc->frame_done = false; 190 stop(crtc); 191 192 /* 193 * if necessary wait for framedone irq which will still come 194 * before putting things to sleep.. 195 */ 196 if (priv->rev == 2) { 197 int ret = wait_event_timeout( 198 tilcdc_crtc->frame_done_wq, 199 tilcdc_crtc->frame_done, 200 msecs_to_jiffies(50)); 201 if (ret == 0) 202 dev_err(dev->dev, "timeout waiting for framedone\n"); 203 } 204 pm_runtime_allow(dev->dev); 205 } 206 207 pm_runtime_put_sync(dev->dev); 208} 209 210static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc, 211 const struct drm_display_mode *mode, 212 struct drm_display_mode *adjusted_mode) 213{ 214 return true; 215} 216 217static void tilcdc_crtc_prepare(struct drm_crtc *crtc) 218{ 219 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 220} 221 222static void tilcdc_crtc_commit(struct drm_crtc *crtc) 223{ 224 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 225} 226 227static int tilcdc_crtc_mode_set(struct drm_crtc *crtc, 228 struct drm_display_mode *mode, 229 struct drm_display_mode *adjusted_mode, 230 int x, int y, 231 struct drm_framebuffer *old_fb) 232{ 233 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 234 struct drm_device *dev = crtc->dev; 235 struct tilcdc_drm_private *priv = dev->dev_private; 236 const struct tilcdc_panel_info *info = tilcdc_crtc->info; 237 uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw; 238 int ret; 239 240 ret = tilcdc_crtc_mode_valid(crtc, mode); 241 if (WARN_ON(ret)) 242 return ret; 243 244 if (WARN_ON(!info)) 245 return -EINVAL; 246 247 pm_runtime_get_sync(dev->dev); 248 249 /* Configure the Burst Size and fifo threshold of DMA: */ 250 reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770; 251 switch (info->dma_burst_sz) { 252 case 1: 253 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1); 254 break; 255 case 2: 256 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2); 257 break; 258 case 4: 259 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4); 260 break; 261 case 8: 262 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8); 263 break; 264 case 16: 265 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16); 266 break; 267 default: 268 return -EINVAL; 269 } 270 reg |= (info->fifo_th << 8); 271 tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg); 272 273 /* Configure timings: */ 274 hbp = mode->htotal - mode->hsync_end; 275 hfp = mode->hsync_start - mode->hdisplay; 276 hsw = mode->hsync_end - mode->hsync_start; 277 vbp = mode->vtotal - mode->vsync_end; 278 vfp = mode->vsync_start - mode->vdisplay; 279 vsw = mode->vsync_end - mode->vsync_start; 280 281 DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u", 282 mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw); 283 284 /* Configure the AC Bias Period and Number of Transitions per Interrupt: */ 285 reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00; 286 reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) | 287 LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt); 288 289 /* 290 * subtract one from hfp, hbp, hsw because the hardware uses 291 * a value of 0 as 1 292 */ 293 if (priv->rev == 2) { 294 /* clear bits we're going to set */ 295 reg &= ~0x78000033; 296 reg |= ((hfp-1) & 0x300) >> 8; 297 reg |= ((hbp-1) & 0x300) >> 4; 298 reg |= ((hsw-1) & 0x3c0) << 21; 299 } 300 tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg); 301 302 reg = (((mode->hdisplay >> 4) - 1) << 4) | 303 (((hbp-1) & 0xff) << 24) | 304 (((hfp-1) & 0xff) << 16) | 305 (((hsw-1) & 0x3f) << 10); 306 if (priv->rev == 2) 307 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3; 308 tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg); 309 310 reg = ((mode->vdisplay - 1) & 0x3ff) | 311 ((vbp & 0xff) << 24) | 312 ((vfp & 0xff) << 16) | 313 (((vsw-1) & 0x3f) << 10); 314 tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg); 315 316 /* 317 * be sure to set Bit 10 for the V2 LCDC controller, 318 * otherwise limited to 1024 pixels width, stopping 319 * 1920x1080 being suppoted. 320 */ 321 if (priv->rev == 2) { 322 if ((mode->vdisplay - 1) & 0x400) { 323 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, 324 LCDC_LPP_B10); 325 } else { 326 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, 327 LCDC_LPP_B10); 328 } 329 } 330 331 /* Configure display type: */ 332 reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) & 333 ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE | 334 LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK | 0x000ff000); 335 reg |= LCDC_TFT_MODE; /* no monochrome/passive support */ 336 if (info->tft_alt_mode) 337 reg |= LCDC_TFT_ALT_ENABLE; 338 if (priv->rev == 2) { 339 unsigned int depth, bpp; 340 341 drm_fb_get_bpp_depth(crtc->fb->pixel_format, &depth, &bpp); 342 switch (bpp) { 343 case 16: 344 break; 345 case 32: 346 reg |= LCDC_V2_TFT_24BPP_UNPACK; 347 /* fallthrough */ 348 case 24: 349 reg |= LCDC_V2_TFT_24BPP_MODE; 350 break; 351 default: 352 dev_err(dev->dev, "invalid pixel format\n"); 353 return -EINVAL; 354 } 355 } 356 reg |= info->fdd < 12; 357 tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg); 358 359 if (info->invert_pxl_clk) 360 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK); 361 else 362 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK); 363 364 if (info->sync_ctrl) 365 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); 366 else 367 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); 368 369 if (info->sync_edge) 370 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE); 371 else 372 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE); 373 374 /* 375 * use value from adjusted_mode here as this might have been 376 * changed as part of the fixup for slave encoders to solve the 377 * issue where tilcdc timings are not VESA compliant 378 */ 379 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 380 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC); 381 else 382 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC); 383 384 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 385 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC); 386 else 387 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC); 388 389 if (info->raster_order) 390 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER); 391 else 392 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER); 393 394 395 update_scanout(crtc); 396 tilcdc_crtc_update_clk(crtc); 397 398 pm_runtime_put_sync(dev->dev); 399 400 return 0; 401} 402 403static int tilcdc_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 404 struct drm_framebuffer *old_fb) 405{ 406 update_scanout(crtc); 407 return 0; 408} 409 410static const struct drm_crtc_funcs tilcdc_crtc_funcs = { 411 .destroy = tilcdc_crtc_destroy, 412 .set_config = drm_crtc_helper_set_config, 413 .page_flip = tilcdc_crtc_page_flip, 414}; 415 416static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = { 417 .dpms = tilcdc_crtc_dpms, 418 .mode_fixup = tilcdc_crtc_mode_fixup, 419 .prepare = tilcdc_crtc_prepare, 420 .commit = tilcdc_crtc_commit, 421 .mode_set = tilcdc_crtc_mode_set, 422 .mode_set_base = tilcdc_crtc_mode_set_base, 423}; 424 425int tilcdc_crtc_max_width(struct drm_crtc *crtc) 426{ 427 struct drm_device *dev = crtc->dev; 428 struct tilcdc_drm_private *priv = dev->dev_private; 429 int max_width = 0; 430 431 if (priv->rev == 1) 432 max_width = 1024; 433 else if (priv->rev == 2) 434 max_width = 2048; 435 436 return max_width; 437} 438 439int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode) 440{ 441 struct tilcdc_drm_private *priv = crtc->dev->dev_private; 442 unsigned int bandwidth; 443 uint32_t hbp, hfp, hsw, vbp, vfp, vsw; 444 445 /* 446 * check to see if the width is within the range that 447 * the LCD Controller physically supports 448 */ 449 if (mode->hdisplay > tilcdc_crtc_max_width(crtc)) 450 return MODE_VIRTUAL_X; 451 452 /* width must be multiple of 16 */ 453 if (mode->hdisplay & 0xf) 454 return MODE_VIRTUAL_X; 455 456 if (mode->vdisplay > 2048) 457 return MODE_VIRTUAL_Y; 458 459 DBG("Processing mode %dx%d@%d with pixel clock %d", 460 mode->hdisplay, mode->vdisplay, 461 drm_mode_vrefresh(mode), mode->clock); 462 463 hbp = mode->htotal - mode->hsync_end; 464 hfp = mode->hsync_start - mode->hdisplay; 465 hsw = mode->hsync_end - mode->hsync_start; 466 vbp = mode->vtotal - mode->vsync_end; 467 vfp = mode->vsync_start - mode->vdisplay; 468 vsw = mode->vsync_end - mode->vsync_start; 469 470 if ((hbp-1) & ~0x3ff) { 471 DBG("Pruning mode: Horizontal Back Porch out of range"); 472 return MODE_HBLANK_WIDE; 473 } 474 475 if ((hfp-1) & ~0x3ff) { 476 DBG("Pruning mode: Horizontal Front Porch out of range"); 477 return MODE_HBLANK_WIDE; 478 } 479 480 if ((hsw-1) & ~0x3ff) { 481 DBG("Pruning mode: Horizontal Sync Width out of range"); 482 return MODE_HSYNC_WIDE; 483 } 484 485 if (vbp & ~0xff) { 486 DBG("Pruning mode: Vertical Back Porch out of range"); 487 return MODE_VBLANK_WIDE; 488 } 489 490 if (vfp & ~0xff) { 491 DBG("Pruning mode: Vertical Front Porch out of range"); 492 return MODE_VBLANK_WIDE; 493 } 494 495 if ((vsw-1) & ~0x3f) { 496 DBG("Pruning mode: Vertical Sync Width out of range"); 497 return MODE_VSYNC_WIDE; 498 } 499 500 /* 501 * some devices have a maximum allowed pixel clock 502 * configured from the DT 503 */ 504 if (mode->clock > priv->max_pixelclock) { 505 DBG("Pruning mode: pixel clock too high"); 506 return MODE_CLOCK_HIGH; 507 } 508 509 /* 510 * some devices further limit the max horizontal resolution 511 * configured from the DT 512 */ 513 if (mode->hdisplay > priv->max_width) 514 return MODE_BAD_WIDTH; 515 516 /* filter out modes that would require too much memory bandwidth: */ 517 bandwidth = mode->hdisplay * mode->vdisplay * 518 drm_mode_vrefresh(mode); 519 if (bandwidth > priv->max_bandwidth) { 520 DBG("Pruning mode: exceeds defined bandwidth limit"); 521 return MODE_BAD; 522 } 523 524 return MODE_OK; 525} 526 527void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc, 528 const struct tilcdc_panel_info *info) 529{ 530 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 531 tilcdc_crtc->info = info; 532} 533 534void tilcdc_crtc_update_clk(struct drm_crtc *crtc) 535{ 536 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 537 struct drm_device *dev = crtc->dev; 538 struct tilcdc_drm_private *priv = dev->dev_private; 539 int dpms = tilcdc_crtc->dpms; 540 unsigned int lcd_clk, div; 541 int ret; 542 543 pm_runtime_get_sync(dev->dev); 544 545 if (dpms == DRM_MODE_DPMS_ON) 546 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 547 548 /* in raster mode, minimum divisor is 2: */ 549 ret = clk_set_rate(priv->disp_clk, crtc->mode.clock * 1000 * 2); 550 if (ret) { 551 dev_err(dev->dev, "failed to set display clock rate to: %d\n", 552 crtc->mode.clock); 553 goto out; 554 } 555 556 lcd_clk = clk_get_rate(priv->clk); 557 div = lcd_clk / (crtc->mode.clock * 1000); 558 559 DBG("lcd_clk=%u, mode clock=%d, div=%u", lcd_clk, crtc->mode.clock, div); 560 DBG("fck=%lu, dpll_disp_ck=%lu", clk_get_rate(priv->clk), clk_get_rate(priv->disp_clk)); 561 562 /* Configure the LCD clock divisor. */ 563 tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(div) | 564 LCDC_RASTER_MODE); 565 566 if (priv->rev == 2) 567 tilcdc_set(dev, LCDC_CLK_ENABLE_REG, 568 LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN | 569 LCDC_V2_CORE_CLK_EN); 570 571 if (dpms == DRM_MODE_DPMS_ON) 572 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 573 574out: 575 pm_runtime_put_sync(dev->dev); 576} 577 578irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc) 579{ 580 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 581 struct drm_device *dev = crtc->dev; 582 struct tilcdc_drm_private *priv = dev->dev_private; 583 uint32_t stat = tilcdc_read_irqstatus(dev); 584 585 if ((stat & LCDC_SYNC_LOST) && (stat & LCDC_FIFO_UNDERFLOW)) { 586 stop(crtc); 587 dev_err(dev->dev, "error: %08x\n", stat); 588 tilcdc_clear_irqstatus(dev, stat); 589 start(crtc); 590 } else if (stat & LCDC_PL_LOAD_DONE) { 591 tilcdc_clear_irqstatus(dev, stat); 592 } else { 593 struct drm_pending_vblank_event *event; 594 unsigned long flags; 595 uint32_t dirty = tilcdc_crtc->dirty & stat; 596 597 tilcdc_clear_irqstatus(dev, stat); 598 599 if (dirty & LCDC_END_OF_FRAME0) 600 set_scanout(crtc, 0); 601 602 if (dirty & LCDC_END_OF_FRAME1) 603 set_scanout(crtc, 1); 604 605 drm_handle_vblank(dev, 0); 606 607 spin_lock_irqsave(&dev->event_lock, flags); 608 event = tilcdc_crtc->event; 609 tilcdc_crtc->event = NULL; 610 if (event) 611 drm_send_vblank_event(dev, 0, event); 612 spin_unlock_irqrestore(&dev->event_lock, flags); 613 614 if (dirty && !tilcdc_crtc->dirty) 615 drm_vblank_put(dev, 0); 616 } 617 618 if (priv->rev == 2) { 619 if (stat & LCDC_FRAME_DONE) { 620 tilcdc_crtc->frame_done = true; 621 wake_up(&tilcdc_crtc->frame_done_wq); 622 } 623 tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0); 624 } 625 626 return IRQ_HANDLED; 627} 628 629void tilcdc_crtc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file) 630{ 631 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 632 struct drm_pending_vblank_event *event; 633 struct drm_device *dev = crtc->dev; 634 unsigned long flags; 635 636 /* Destroy the pending vertical blanking event associated with the 637 * pending page flip, if any, and disable vertical blanking interrupts. 638 */ 639 spin_lock_irqsave(&dev->event_lock, flags); 640 event = tilcdc_crtc->event; 641 if (event && event->base.file_priv == file) { 642 tilcdc_crtc->event = NULL; 643 event->base.destroy(&event->base); 644 drm_vblank_put(dev, 0); 645 } 646 spin_unlock_irqrestore(&dev->event_lock, flags); 647} 648 649struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev) 650{ 651 struct tilcdc_crtc *tilcdc_crtc; 652 struct drm_crtc *crtc; 653 int ret; 654 655 tilcdc_crtc = kzalloc(sizeof(*tilcdc_crtc), GFP_KERNEL); 656 if (!tilcdc_crtc) { 657 dev_err(dev->dev, "allocation failed\n"); 658 return NULL; 659 } 660 661 crtc = &tilcdc_crtc->base; 662 663 tilcdc_crtc->dpms = DRM_MODE_DPMS_OFF; 664 init_waitqueue_head(&tilcdc_crtc->frame_done_wq); 665 666 ret = drm_flip_work_init(&tilcdc_crtc->unref_work, 16, 667 "unref", unref_worker); 668 if (ret) { 669 dev_err(dev->dev, "could not allocate unref FIFO\n"); 670 goto fail; 671 } 672 673 ret = drm_crtc_init(dev, crtc, &tilcdc_crtc_funcs); 674 if (ret < 0) 675 goto fail; 676 677 drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs); 678 679 return crtc; 680 681fail: 682 tilcdc_crtc_destroy(crtc); 683 return NULL; 684} 685