116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark/* 216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * Copyright (C) 2012 Texas Instruments 316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * Author: Rob Clark <robdclark@gmail.com> 416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * 516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * This program is free software; you can redistribute it and/or modify it 616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * under the terms of the GNU General Public License version 2 as published by 716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * the Free Software Foundation. 816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * 916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * This program is distributed in the hope that it will be useful, but WITHOUT 1016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * more details. 1316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * 1416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * You should have received a copy of the GNU General Public License along with 1516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * this program. If not, see <http://www.gnu.org/licenses/>. 1616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark */ 1716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 1816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#ifndef __TILCDC_DRV_H__ 1916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#define __TILCDC_DRV_H__ 2016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 2116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#include <linux/clk.h> 2216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#include <linux/cpufreq.h> 2316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#include <linux/module.h> 2416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#include <linux/platform_device.h> 2516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#include <linux/pm.h> 2616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#include <linux/pm_runtime.h> 2716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#include <linux/slab.h> 2816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#include <linux/of.h> 2916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#include <linux/of_device.h> 3016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#include <linux/list.h> 3116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 3216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#include <drm/drmP.h> 3316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#include <drm/drm_crtc_helper.h> 3416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#include <drm/drm_gem_cma_helper.h> 3516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#include <drm/drm_fb_cma_helper.h> 3616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 374e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge/* Defaulting to pixel clock defined on AM335x */ 384e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge#define TILCDC_DEFAULT_MAX_PIXELCLOCK 126000 394e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge/* Defaulting to max width as defined on AM335x */ 404e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge#define TILCDC_DEFAULT_MAX_WIDTH 2048 414e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge/* 424e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge * This may need some tweaking, but want to allow at least 1280x1024@60 434e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge * with optimized DDR & EMIF settings tweaked 1920x1080@24 appears to 444e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge * be supportable 454e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge */ 464e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge#define TILCDC_DEFAULT_MAX_BANDWIDTH (1280*1024*60) 474e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge 484e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge 4916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstruct tilcdc_drm_private { 5016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark void __iomem *mmio; 5116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 5216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct clk *disp_clk; /* display dpll */ 5316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct clk *clk; /* functional clock */ 5416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark int rev; /* IP revision */ 5516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 5616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* don't attempt resolutions w/ higher W * H * Hz: */ 5716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark uint32_t max_bandwidth; 584e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge /* 594e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge * Pixel Clock will be restricted to some value as 604e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge * defined in the device datasheet measured in KHz 614e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge */ 624e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge uint32_t max_pixelclock; 634e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge /* 644e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge * Max allowable width is limited on a per device basis 654e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge * measured in pixels 664e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge */ 674e5643468715260209e42b715e8cd9643456d2bdDarren Etheridge uint32_t max_width; 6816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 6916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* register contents saved across suspend/resume: */ 7016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark u32 saved_register[12]; 7116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 7216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#ifdef CONFIG_CPU_FREQ 7316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct notifier_block freq_transition; 7416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark unsigned int lcd_fck_rate; 7516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#endif 7616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 7716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct workqueue_struct *wq; 7816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 7916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_fbdev_cma *fbdev; 8016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 8116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_crtc *crtc; 8216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 8316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark unsigned int num_encoders; 8416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_encoder *encoders[8]; 8516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 8616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark unsigned int num_connectors; 8716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct drm_connector *connectors[8]; 8816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark}; 8916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 9016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark/* Sub-module for display. Since we don't know at compile time what panels 9116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * or display adapter(s) might be present (for ex, off chip dvi/tfp410, 9216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * hdmi encoder, various lcd panels), the connector/encoder(s) are split into 9316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * separate drivers. If they are probed and found to be present, they 9416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * register themselves with tilcdc_register_module(). 9516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark */ 9616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstruct tilcdc_module; 9716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 9816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstruct tilcdc_module_ops { 9916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* create appropriate encoders/connectors: */ 10016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark int (*modeset_init)(struct tilcdc_module *mod, struct drm_device *dev); 10116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#ifdef CONFIG_DEBUG_FS 10216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* create debugfs nodes (can be NULL): */ 10316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark int (*debugfs_init)(struct tilcdc_module *mod, struct drm_minor *minor); 10416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* cleanup debugfs nodes (can be NULL): */ 10516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark void (*debugfs_cleanup)(struct tilcdc_module *mod, struct drm_minor *minor); 10616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#endif 10716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark}; 10816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 10916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstruct tilcdc_module { 11016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark const char *name; 11116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark struct list_head list; 11216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark const struct tilcdc_module_ops *funcs; 113dc28aa072f502433b6adc5c9ae8f56955c07580aBenoit Parrot unsigned int preferred_bpp; 11416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark}; 11516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 11616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkvoid tilcdc_module_init(struct tilcdc_module *mod, const char *name, 11716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark const struct tilcdc_module_ops *funcs); 11816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkvoid tilcdc_module_cleanup(struct tilcdc_module *mod); 11939de6194131c155901f96686a063212656d80c2eDarren Etheridgevoid tilcdc_slave_probedefer(bool defered); 12016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 12116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark/* Panel config that needs to be set in the crtc, but is not coming from 12216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * the mode timings. The display module is expected to call 12316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark * tilcdc_crtc_set_panel_info() to set this during modeset. 12416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark */ 12516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstruct tilcdc_panel_info { 12616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 12716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* AC Bias Pin Frequency */ 12816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark uint32_t ac_bias; 12916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 13016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* AC Bias Pin Transitions per Interrupt */ 13116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark uint32_t ac_bias_intrpt; 13216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 13316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* DMA burst size */ 13416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark uint32_t dma_burst_sz; 13516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 13616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* Bits per pixel */ 13716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark uint32_t bpp; 13816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 13916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* FIFO DMA Request Delay */ 14016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark uint32_t fdd; 14116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 14216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* TFT Alternative Signal Mapping (Only for active) */ 14316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark bool tft_alt_mode; 14416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 14516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* Invert pixel clock */ 14616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark bool invert_pxl_clk; 14716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 14816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */ 14916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark uint32_t sync_edge; 15016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 15116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* Horizontal and Vertical Sync: Control: 0=ignore */ 15216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark uint32_t sync_ctrl; 15316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 15416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */ 15516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark uint32_t raster_order; 15616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 15716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark /* DMA FIFO threshold */ 15816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark uint32_t fifo_th; 15916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark}; 16016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 16116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 16216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 16316ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkstruct drm_crtc *tilcdc_crtc_create(struct drm_device *dev); 16416ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkvoid tilcdc_crtc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file); 16516ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkirqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc); 16616ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkvoid tilcdc_crtc_update_clk(struct drm_crtc *crtc); 16716ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkvoid tilcdc_crtc_set_panel_info(struct drm_crtc *crtc, 16816ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark const struct tilcdc_panel_info *info); 16916ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkint tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode); 17016ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clarkint tilcdc_crtc_max_width(struct drm_crtc *crtc); 17116ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark 17216ea975eac671fa40a78594a116a44fef8e3f4a9Rob Clark#endif /* __TILCDC_DRV_H__ */ 173