i2c-au1550.c revision 84785f120f4d64c5fa8cf4bab1cf07c2507d434f 
1/*
2 * i2c-au1550.c: SMBus (i2c) adapter for Alchemy PSC interface
3 * Copyright (C) 2004 Embedded Edge, LLC <dan@embeddededge.com>
4 *
5 * 2.6 port by Matt Porter <mporter@kernel.crashing.org>
6 *
7 * The documentation describes this as an SMBus controller, but it doesn't
8 * understand any of the SMBus protocol in hardware.  It's really an I2C
9 * controller that could emulate most of the SMBus in software.
10 *
11 * This is just a skeleton adapter to use with the Au1550 PSC
12 * algorithm.  It was developed for the Pb1550, but will work with
13 * any Au1550 board that has a similar PSC configuration.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version 2
18 * of the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
28 */
29
30#include <linux/delay.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/platform_device.h>
34#include <linux/init.h>
35#include <linux/errno.h>
36#include <linux/i2c.h>
37#include <linux/slab.h>
38
39#include <asm/mach-au1x00/au1xxx.h>
40#include <asm/mach-au1x00/au1xxx_psc.h>
41
42#define PSC_SEL		0x00
43#define PSC_CTRL	0x04
44#define PSC_SMBCFG	0x08
45#define PSC_SMBMSK	0x0C
46#define PSC_SMBPCR	0x10
47#define PSC_SMBSTAT	0x14
48#define PSC_SMBEVNT	0x18
49#define PSC_SMBTXRX	0x1C
50#define PSC_SMBTMR	0x20
51
52struct i2c_au1550_data {
53	void __iomem *psc_base;
54	int	xfer_timeout;
55	struct i2c_adapter adap;
56	struct resource *ioarea;
57};
58
59static inline void WR(struct i2c_au1550_data *a, int r, unsigned long v)
60{
61	__raw_writel(v, a->psc_base + r);
62	wmb();
63}
64
65static inline unsigned long RD(struct i2c_au1550_data *a, int r)
66{
67	return __raw_readl(a->psc_base + r);
68}
69
70static int wait_xfer_done(struct i2c_au1550_data *adap)
71{
72	int i;
73
74	/* Wait for Tx Buffer Empty */
75	for (i = 0; i < adap->xfer_timeout; i++) {
76		if (RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_TE)
77			return 0;
78
79		udelay(1);
80	}
81
82	return -ETIMEDOUT;
83}
84
85static int wait_ack(struct i2c_au1550_data *adap)
86{
87	unsigned long stat;
88
89	if (wait_xfer_done(adap))
90		return -ETIMEDOUT;
91
92	stat = RD(adap, PSC_SMBEVNT);
93	if ((stat & (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | PSC_SMBEVNT_AL)) != 0)
94		return -ETIMEDOUT;
95
96	return 0;
97}
98
99static int wait_master_done(struct i2c_au1550_data *adap)
100{
101	int i;
102
103	/* Wait for Master Done. */
104	for (i = 0; i < 2 * adap->xfer_timeout; i++) {
105		if ((RD(adap, PSC_SMBEVNT) & PSC_SMBEVNT_MD) != 0)
106			return 0;
107		udelay(1);
108	}
109
110	return -ETIMEDOUT;
111}
112
113static int
114do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd, int q)
115{
116	unsigned long stat;
117
118	/* Reset the FIFOs, clear events. */
119	stat = RD(adap, PSC_SMBSTAT);
120	WR(adap, PSC_SMBEVNT, PSC_SMBEVNT_ALLCLR);
121
122	if (!(stat & PSC_SMBSTAT_TE) || !(stat & PSC_SMBSTAT_RE)) {
123		WR(adap, PSC_SMBPCR, PSC_SMBPCR_DC);
124		while ((RD(adap, PSC_SMBPCR) & PSC_SMBPCR_DC) != 0)
125			cpu_relax();
126		udelay(50);
127	}
128
129	/* Write out the i2c chip address and specify operation */
130	addr <<= 1;
131	if (rd)
132		addr |= 1;
133
134	/* zero-byte xfers stop immediately */
135	if (q)
136		addr |= PSC_SMBTXRX_STP;
137
138	/* Put byte into fifo, start up master. */
139	WR(adap, PSC_SMBTXRX, addr);
140	WR(adap, PSC_SMBPCR, PSC_SMBPCR_MS);
141	if (wait_ack(adap))
142		return -EIO;
143	return (q) ? wait_master_done(adap) : 0;
144}
145
146static int wait_for_rx_byte(struct i2c_au1550_data *adap, unsigned char *out)
147{
148	int j;
149
150	if (wait_xfer_done(adap))
151		return -EIO;
152
153	j =  adap->xfer_timeout * 100;
154	do {
155		j--;
156		if (j <= 0)
157			return -EIO;
158
159		if ((RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_RE) == 0)
160			j = 0;
161		else
162			udelay(1);
163	} while (j > 0);
164
165	*out = RD(adap, PSC_SMBTXRX);
166
167	return 0;
168}
169
170static int i2c_read(struct i2c_au1550_data *adap, unsigned char *buf,
171		    unsigned int len)
172{
173	int i;
174
175	if (len == 0)
176		return 0;
177
178	/* A read is performed by stuffing the transmit fifo with
179	 * zero bytes for timing, waiting for bytes to appear in the
180	 * receive fifo, then reading the bytes.
181	 */
182	i = 0;
183	while (i < (len - 1)) {
184		WR(adap, PSC_SMBTXRX, 0);
185		if (wait_for_rx_byte(adap, &buf[i]))
186			return -EIO;
187
188		i++;
189	}
190
191	/* The last byte has to indicate transfer done. */
192	WR(adap, PSC_SMBTXRX, PSC_SMBTXRX_STP);
193	if (wait_master_done(adap))
194		return -EIO;
195
196	buf[i] = (unsigned char)(RD(adap, PSC_SMBTXRX) & 0xff);
197	return 0;
198}
199
200static int i2c_write(struct i2c_au1550_data *adap, unsigned char *buf,
201		     unsigned int len)
202{
203	int i;
204	unsigned long data;
205
206	if (len == 0)
207		return 0;
208
209	i = 0;
210	while (i < (len-1)) {
211		data = buf[i];
212		WR(adap, PSC_SMBTXRX, data);
213		if (wait_ack(adap))
214			return -EIO;
215		i++;
216	}
217
218	/* The last byte has to indicate transfer done. */
219	data = buf[i];
220	data |= PSC_SMBTXRX_STP;
221	WR(adap, PSC_SMBTXRX, data);
222	if (wait_master_done(adap))
223		return -EIO;
224	return 0;
225}
226
227static int
228au1550_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num)
229{
230	struct i2c_au1550_data *adap = i2c_adap->algo_data;
231	struct i2c_msg *p;
232	int i, err = 0;
233
234	WR(adap, PSC_CTRL, PSC_CTRL_ENABLE);
235
236	for (i = 0; !err && i < num; i++) {
237		p = &msgs[i];
238		err = do_address(adap, p->addr, p->flags & I2C_M_RD,
239				 (p->len == 0));
240		if (err || !p->len)
241			continue;
242		if (p->flags & I2C_M_RD)
243			err = i2c_read(adap, p->buf, p->len);
244		else
245			err = i2c_write(adap, p->buf, p->len);
246	}
247
248	/* Return the number of messages processed, or the error code.
249	*/
250	if (err == 0)
251		err = num;
252
253	WR(adap, PSC_CTRL, PSC_CTRL_SUSPEND);
254
255	return err;
256}
257
258static u32 au1550_func(struct i2c_adapter *adap)
259{
260	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
261}
262
263static const struct i2c_algorithm au1550_algo = {
264	.master_xfer	= au1550_xfer,
265	.functionality	= au1550_func,
266};
267
268static void i2c_au1550_setup(struct i2c_au1550_data *priv)
269{
270	unsigned long cfg;
271
272	WR(priv, PSC_CTRL, PSC_CTRL_DISABLE);
273	WR(priv, PSC_SEL, PSC_SEL_PS_SMBUSMODE);
274	WR(priv, PSC_SMBCFG, 0);
275	WR(priv, PSC_CTRL, PSC_CTRL_ENABLE);
276	while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0)
277		cpu_relax();
278
279	cfg = PSC_SMBCFG_RT_FIFO8 | PSC_SMBCFG_TT_FIFO8 | PSC_SMBCFG_DD_DISABLE;
280	WR(priv, PSC_SMBCFG, cfg);
281
282	/* Divide by 8 to get a 6.25 MHz clock.  The later protocol
283	 * timings are based on this clock.
284	 */
285	cfg |= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV8);
286	WR(priv, PSC_SMBCFG, cfg);
287	WR(priv, PSC_SMBMSK, PSC_SMBMSK_ALLMASK);
288
289	/* Set the protocol timer values.  See Table 71 in the
290	 * Au1550 Data Book for standard timing values.
291	 */
292	WR(priv, PSC_SMBTMR, PSC_SMBTMR_SET_TH(0) | PSC_SMBTMR_SET_PS(15) | \
293		PSC_SMBTMR_SET_PU(15) | PSC_SMBTMR_SET_SH(15) | \
294		PSC_SMBTMR_SET_SU(15) | PSC_SMBTMR_SET_CL(15) | \
295		PSC_SMBTMR_SET_CH(15));
296
297	cfg |= PSC_SMBCFG_DE_ENABLE;
298	WR(priv, PSC_SMBCFG, cfg);
299	while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0)
300		cpu_relax();
301
302	WR(priv, PSC_CTRL, PSC_CTRL_SUSPEND);
303}
304
305static void i2c_au1550_disable(struct i2c_au1550_data *priv)
306{
307	WR(priv, PSC_SMBCFG, 0);
308	WR(priv, PSC_CTRL, PSC_CTRL_DISABLE);
309}
310
311/*
312 * registering functions to load algorithms at runtime
313 * Prior to calling us, the 50MHz clock frequency and routing
314 * must have been set up for the PSC indicated by the adapter.
315 */
316static int __devinit
317i2c_au1550_probe(struct platform_device *pdev)
318{
319	struct i2c_au1550_data *priv;
320	struct resource *r;
321	int ret;
322
323	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
324	if (!r) {
325		ret = -ENODEV;
326		goto out;
327	}
328
329	priv = kzalloc(sizeof(struct i2c_au1550_data), GFP_KERNEL);
330	if (!priv) {
331		ret = -ENOMEM;
332		goto out;
333	}
334
335	priv->ioarea = request_mem_region(r->start, resource_size(r),
336					  pdev->name);
337	if (!priv->ioarea) {
338		ret = -EBUSY;
339		goto out_mem;
340	}
341
342	priv->psc_base = ioremap(r->start, resource_size(r));
343	if (!priv->psc_base) {
344		ret = -EIO;
345		goto out_map;
346	}
347	priv->xfer_timeout = 200;
348
349	priv->adap.nr = pdev->id;
350	priv->adap.algo = &au1550_algo;
351	priv->adap.algo_data = priv;
352	priv->adap.dev.parent = &pdev->dev;
353	strlcpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name));
354
355	/* Now, set up the PSC for SMBus PIO mode. */
356	i2c_au1550_setup(priv);
357
358	ret = i2c_add_numbered_adapter(&priv->adap);
359	if (ret == 0) {
360		platform_set_drvdata(pdev, priv);
361		return 0;
362	}
363
364	i2c_au1550_disable(priv);
365	iounmap(priv->psc_base);
366out_map:
367	release_resource(priv->ioarea);
368	kfree(priv->ioarea);
369out_mem:
370	kfree(priv);
371out:
372	return ret;
373}
374
375static int __devexit i2c_au1550_remove(struct platform_device *pdev)
376{
377	struct i2c_au1550_data *priv = platform_get_drvdata(pdev);
378
379	platform_set_drvdata(pdev, NULL);
380	i2c_del_adapter(&priv->adap);
381	i2c_au1550_disable(priv);
382	iounmap(priv->psc_base);
383	release_resource(priv->ioarea);
384	kfree(priv->ioarea);
385	kfree(priv);
386	return 0;
387}
388
389#ifdef CONFIG_PM
390static int
391i2c_au1550_suspend(struct platform_device *pdev, pm_message_t state)
392{
393	struct i2c_au1550_data *priv = platform_get_drvdata(pdev);
394
395	i2c_au1550_disable(priv);
396
397	return 0;
398}
399
400static int
401i2c_au1550_resume(struct platform_device *pdev)
402{
403	struct i2c_au1550_data *priv = platform_get_drvdata(pdev);
404
405	i2c_au1550_setup(priv);
406
407	return 0;
408}
409#else
410#define i2c_au1550_suspend	NULL
411#define i2c_au1550_resume	NULL
412#endif
413
414static struct platform_driver au1xpsc_smbus_driver = {
415	.driver = {
416		.name	= "au1xpsc_smbus",
417		.owner	= THIS_MODULE,
418	},
419	.probe		= i2c_au1550_probe,
420	.remove		= __devexit_p(i2c_au1550_remove),
421	.suspend	= i2c_au1550_suspend,
422	.resume		= i2c_au1550_resume,
423};
424
425static int __init i2c_au1550_init(void)
426{
427	return platform_driver_register(&au1xpsc_smbus_driver);
428}
429
430static void __exit i2c_au1550_exit(void)
431{
432	platform_driver_unregister(&au1xpsc_smbus_driver);
433}
434
435MODULE_AUTHOR("Dan Malek, Embedded Edge, LLC.");
436MODULE_DESCRIPTION("SMBus adapter Alchemy pb1550");
437MODULE_LICENSE("GPL");
438MODULE_ALIAS("platform:au1xpsc_smbus");
439
440module_init (i2c_au1550_init);
441module_exit (i2c_au1550_exit);
442