i2c-au1550.c revision ca1f8da9ac5ce6e63d8f6933f83fabc1f3f961f4 
1/*
2 * i2c-au1550.c: SMBus (i2c) adapter for Alchemy PSC interface
3 * Copyright (C) 2004 Embedded Edge, LLC <dan@embeddededge.com>
4 *
5 * 2.6 port by Matt Porter <mporter@kernel.crashing.org>
6 *
7 * The documentation describes this as an SMBus controller, but it doesn't
8 * understand any of the SMBus protocol in hardware.  It's really an I2C
9 * controller that could emulate most of the SMBus in software.
10 *
11 * This is just a skeleton adapter to use with the Au1550 PSC
12 * algorithm.  It was developed for the Pb1550, but will work with
13 * any Au1550 board that has a similar PSC configuration.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version 2
18 * of the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23 * GNU General Public License for more details.
24 */
25
26#include <linux/delay.h>
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/platform_device.h>
30#include <linux/errno.h>
31#include <linux/i2c.h>
32#include <linux/slab.h>
33
34#include <asm/mach-au1x00/au1000.h>
35#include <asm/mach-au1x00/au1xxx_psc.h>
36
37#define PSC_SEL		0x00
38#define PSC_CTRL	0x04
39#define PSC_SMBCFG	0x08
40#define PSC_SMBMSK	0x0C
41#define PSC_SMBPCR	0x10
42#define PSC_SMBSTAT	0x14
43#define PSC_SMBEVNT	0x18
44#define PSC_SMBTXRX	0x1C
45#define PSC_SMBTMR	0x20
46
47struct i2c_au1550_data {
48	void __iomem *psc_base;
49	int	xfer_timeout;
50	struct i2c_adapter adap;
51	struct resource *ioarea;
52};
53
54static inline void WR(struct i2c_au1550_data *a, int r, unsigned long v)
55{
56	__raw_writel(v, a->psc_base + r);
57	wmb();
58}
59
60static inline unsigned long RD(struct i2c_au1550_data *a, int r)
61{
62	return __raw_readl(a->psc_base + r);
63}
64
65static int wait_xfer_done(struct i2c_au1550_data *adap)
66{
67	int i;
68
69	/* Wait for Tx Buffer Empty */
70	for (i = 0; i < adap->xfer_timeout; i++) {
71		if (RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_TE)
72			return 0;
73
74		udelay(1);
75	}
76
77	return -ETIMEDOUT;
78}
79
80static int wait_ack(struct i2c_au1550_data *adap)
81{
82	unsigned long stat;
83
84	if (wait_xfer_done(adap))
85		return -ETIMEDOUT;
86
87	stat = RD(adap, PSC_SMBEVNT);
88	if ((stat & (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | PSC_SMBEVNT_AL)) != 0)
89		return -ETIMEDOUT;
90
91	return 0;
92}
93
94static int wait_master_done(struct i2c_au1550_data *adap)
95{
96	int i;
97
98	/* Wait for Master Done. */
99	for (i = 0; i < 2 * adap->xfer_timeout; i++) {
100		if ((RD(adap, PSC_SMBEVNT) & PSC_SMBEVNT_MD) != 0)
101			return 0;
102		udelay(1);
103	}
104
105	return -ETIMEDOUT;
106}
107
108static int
109do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd, int q)
110{
111	unsigned long stat;
112
113	/* Reset the FIFOs, clear events. */
114	stat = RD(adap, PSC_SMBSTAT);
115	WR(adap, PSC_SMBEVNT, PSC_SMBEVNT_ALLCLR);
116
117	if (!(stat & PSC_SMBSTAT_TE) || !(stat & PSC_SMBSTAT_RE)) {
118		WR(adap, PSC_SMBPCR, PSC_SMBPCR_DC);
119		while ((RD(adap, PSC_SMBPCR) & PSC_SMBPCR_DC) != 0)
120			cpu_relax();
121		udelay(50);
122	}
123
124	/* Write out the i2c chip address and specify operation */
125	addr <<= 1;
126	if (rd)
127		addr |= 1;
128
129	/* zero-byte xfers stop immediately */
130	if (q)
131		addr |= PSC_SMBTXRX_STP;
132
133	/* Put byte into fifo, start up master. */
134	WR(adap, PSC_SMBTXRX, addr);
135	WR(adap, PSC_SMBPCR, PSC_SMBPCR_MS);
136	if (wait_ack(adap))
137		return -EIO;
138	return (q) ? wait_master_done(adap) : 0;
139}
140
141static int wait_for_rx_byte(struct i2c_au1550_data *adap, unsigned char *out)
142{
143	int j;
144
145	if (wait_xfer_done(adap))
146		return -EIO;
147
148	j =  adap->xfer_timeout * 100;
149	do {
150		j--;
151		if (j <= 0)
152			return -EIO;
153
154		if ((RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_RE) == 0)
155			j = 0;
156		else
157			udelay(1);
158	} while (j > 0);
159
160	*out = RD(adap, PSC_SMBTXRX);
161
162	return 0;
163}
164
165static int i2c_read(struct i2c_au1550_data *adap, unsigned char *buf,
166		    unsigned int len)
167{
168	int i;
169
170	if (len == 0)
171		return 0;
172
173	/* A read is performed by stuffing the transmit fifo with
174	 * zero bytes for timing, waiting for bytes to appear in the
175	 * receive fifo, then reading the bytes.
176	 */
177	i = 0;
178	while (i < (len - 1)) {
179		WR(adap, PSC_SMBTXRX, 0);
180		if (wait_for_rx_byte(adap, &buf[i]))
181			return -EIO;
182
183		i++;
184	}
185
186	/* The last byte has to indicate transfer done. */
187	WR(adap, PSC_SMBTXRX, PSC_SMBTXRX_STP);
188	if (wait_master_done(adap))
189		return -EIO;
190
191	buf[i] = (unsigned char)(RD(adap, PSC_SMBTXRX) & 0xff);
192	return 0;
193}
194
195static int i2c_write(struct i2c_au1550_data *adap, unsigned char *buf,
196		     unsigned int len)
197{
198	int i;
199	unsigned long data;
200
201	if (len == 0)
202		return 0;
203
204	i = 0;
205	while (i < (len-1)) {
206		data = buf[i];
207		WR(adap, PSC_SMBTXRX, data);
208		if (wait_ack(adap))
209			return -EIO;
210		i++;
211	}
212
213	/* The last byte has to indicate transfer done. */
214	data = buf[i];
215	data |= PSC_SMBTXRX_STP;
216	WR(adap, PSC_SMBTXRX, data);
217	if (wait_master_done(adap))
218		return -EIO;
219	return 0;
220}
221
222static int
223au1550_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num)
224{
225	struct i2c_au1550_data *adap = i2c_adap->algo_data;
226	struct i2c_msg *p;
227	int i, err = 0;
228
229	WR(adap, PSC_CTRL, PSC_CTRL_ENABLE);
230
231	for (i = 0; !err && i < num; i++) {
232		p = &msgs[i];
233		err = do_address(adap, p->addr, p->flags & I2C_M_RD,
234				 (p->len == 0));
235		if (err || !p->len)
236			continue;
237		if (p->flags & I2C_M_RD)
238			err = i2c_read(adap, p->buf, p->len);
239		else
240			err = i2c_write(adap, p->buf, p->len);
241	}
242
243	/* Return the number of messages processed, or the error code.
244	*/
245	if (err == 0)
246		err = num;
247
248	WR(adap, PSC_CTRL, PSC_CTRL_SUSPEND);
249
250	return err;
251}
252
253static u32 au1550_func(struct i2c_adapter *adap)
254{
255	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
256}
257
258static const struct i2c_algorithm au1550_algo = {
259	.master_xfer	= au1550_xfer,
260	.functionality	= au1550_func,
261};
262
263static void i2c_au1550_setup(struct i2c_au1550_data *priv)
264{
265	unsigned long cfg;
266
267	WR(priv, PSC_CTRL, PSC_CTRL_DISABLE);
268	WR(priv, PSC_SEL, PSC_SEL_PS_SMBUSMODE);
269	WR(priv, PSC_SMBCFG, 0);
270	WR(priv, PSC_CTRL, PSC_CTRL_ENABLE);
271	while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0)
272		cpu_relax();
273
274	cfg = PSC_SMBCFG_RT_FIFO8 | PSC_SMBCFG_TT_FIFO8 | PSC_SMBCFG_DD_DISABLE;
275	WR(priv, PSC_SMBCFG, cfg);
276
277	/* Divide by 8 to get a 6.25 MHz clock.  The later protocol
278	 * timings are based on this clock.
279	 */
280	cfg |= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV8);
281	WR(priv, PSC_SMBCFG, cfg);
282	WR(priv, PSC_SMBMSK, PSC_SMBMSK_ALLMASK);
283
284	/* Set the protocol timer values.  See Table 71 in the
285	 * Au1550 Data Book for standard timing values.
286	 */
287	WR(priv, PSC_SMBTMR, PSC_SMBTMR_SET_TH(0) | PSC_SMBTMR_SET_PS(15) | \
288		PSC_SMBTMR_SET_PU(15) | PSC_SMBTMR_SET_SH(15) | \
289		PSC_SMBTMR_SET_SU(15) | PSC_SMBTMR_SET_CL(15) | \
290		PSC_SMBTMR_SET_CH(15));
291
292	cfg |= PSC_SMBCFG_DE_ENABLE;
293	WR(priv, PSC_SMBCFG, cfg);
294	while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0)
295		cpu_relax();
296
297	WR(priv, PSC_CTRL, PSC_CTRL_SUSPEND);
298}
299
300static void i2c_au1550_disable(struct i2c_au1550_data *priv)
301{
302	WR(priv, PSC_SMBCFG, 0);
303	WR(priv, PSC_CTRL, PSC_CTRL_DISABLE);
304}
305
306/*
307 * registering functions to load algorithms at runtime
308 * Prior to calling us, the 50MHz clock frequency and routing
309 * must have been set up for the PSC indicated by the adapter.
310 */
311static int
312i2c_au1550_probe(struct platform_device *pdev)
313{
314	struct i2c_au1550_data *priv;
315	struct resource *r;
316	int ret;
317
318	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
319	if (!r) {
320		ret = -ENODEV;
321		goto out;
322	}
323
324	priv = kzalloc(sizeof(struct i2c_au1550_data), GFP_KERNEL);
325	if (!priv) {
326		ret = -ENOMEM;
327		goto out;
328	}
329
330	priv->ioarea = request_mem_region(r->start, resource_size(r),
331					  pdev->name);
332	if (!priv->ioarea) {
333		ret = -EBUSY;
334		goto out_mem;
335	}
336
337	priv->psc_base = ioremap(r->start, resource_size(r));
338	if (!priv->psc_base) {
339		ret = -EIO;
340		goto out_map;
341	}
342	priv->xfer_timeout = 200;
343
344	priv->adap.nr = pdev->id;
345	priv->adap.algo = &au1550_algo;
346	priv->adap.algo_data = priv;
347	priv->adap.dev.parent = &pdev->dev;
348	strlcpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name));
349
350	/* Now, set up the PSC for SMBus PIO mode. */
351	i2c_au1550_setup(priv);
352
353	ret = i2c_add_numbered_adapter(&priv->adap);
354	if (ret == 0) {
355		platform_set_drvdata(pdev, priv);
356		return 0;
357	}
358
359	i2c_au1550_disable(priv);
360	iounmap(priv->psc_base);
361out_map:
362	release_resource(priv->ioarea);
363	kfree(priv->ioarea);
364out_mem:
365	kfree(priv);
366out:
367	return ret;
368}
369
370static int i2c_au1550_remove(struct platform_device *pdev)
371{
372	struct i2c_au1550_data *priv = platform_get_drvdata(pdev);
373
374	i2c_del_adapter(&priv->adap);
375	i2c_au1550_disable(priv);
376	iounmap(priv->psc_base);
377	release_resource(priv->ioarea);
378	kfree(priv->ioarea);
379	kfree(priv);
380	return 0;
381}
382
383#ifdef CONFIG_PM
384static int i2c_au1550_suspend(struct device *dev)
385{
386	struct i2c_au1550_data *priv = dev_get_drvdata(dev);
387
388	i2c_au1550_disable(priv);
389
390	return 0;
391}
392
393static int i2c_au1550_resume(struct device *dev)
394{
395	struct i2c_au1550_data *priv = dev_get_drvdata(dev);
396
397	i2c_au1550_setup(priv);
398
399	return 0;
400}
401
402static const struct dev_pm_ops i2c_au1550_pmops = {
403	.suspend	= i2c_au1550_suspend,
404	.resume		= i2c_au1550_resume,
405};
406
407#define AU1XPSC_SMBUS_PMOPS (&i2c_au1550_pmops)
408
409#else
410#define AU1XPSC_SMBUS_PMOPS NULL
411#endif
412
413static struct platform_driver au1xpsc_smbus_driver = {
414	.driver = {
415		.name	= "au1xpsc_smbus",
416		.owner	= THIS_MODULE,
417		.pm	= AU1XPSC_SMBUS_PMOPS,
418	},
419	.probe		= i2c_au1550_probe,
420	.remove		= i2c_au1550_remove,
421};
422
423module_platform_driver(au1xpsc_smbus_driver);
424
425MODULE_AUTHOR("Dan Malek, Embedded Edge, LLC.");
426MODULE_DESCRIPTION("SMBus adapter Alchemy pb1550");
427MODULE_LICENSE("GPL");
428MODULE_ALIAS("platform:au1xpsc_smbus");
429