aec62xx.c revision 898ec223fea2a2df88035e58dbf50f493577e225
1/* 2 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> 3 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com> 4 * 5 */ 6 7#include <linux/module.h> 8#include <linux/types.h> 9#include <linux/pci.h> 10#include <linux/ide.h> 11#include <linux/init.h> 12 13#include <asm/io.h> 14 15#define DRV_NAME "aec62xx" 16 17struct chipset_bus_clock_list_entry { 18 u8 xfer_speed; 19 u8 chipset_settings; 20 u8 ultra_settings; 21}; 22 23static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = { 24 { XFER_UDMA_6, 0x31, 0x07 }, 25 { XFER_UDMA_5, 0x31, 0x06 }, 26 { XFER_UDMA_4, 0x31, 0x05 }, 27 { XFER_UDMA_3, 0x31, 0x04 }, 28 { XFER_UDMA_2, 0x31, 0x03 }, 29 { XFER_UDMA_1, 0x31, 0x02 }, 30 { XFER_UDMA_0, 0x31, 0x01 }, 31 32 { XFER_MW_DMA_2, 0x31, 0x00 }, 33 { XFER_MW_DMA_1, 0x31, 0x00 }, 34 { XFER_MW_DMA_0, 0x0a, 0x00 }, 35 { XFER_PIO_4, 0x31, 0x00 }, 36 { XFER_PIO_3, 0x33, 0x00 }, 37 { XFER_PIO_2, 0x08, 0x00 }, 38 { XFER_PIO_1, 0x0a, 0x00 }, 39 { XFER_PIO_0, 0x00, 0x00 }, 40 { 0, 0x00, 0x00 } 41}; 42 43static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = { 44 { XFER_UDMA_6, 0x41, 0x06 }, 45 { XFER_UDMA_5, 0x41, 0x05 }, 46 { XFER_UDMA_4, 0x41, 0x04 }, 47 { XFER_UDMA_3, 0x41, 0x03 }, 48 { XFER_UDMA_2, 0x41, 0x02 }, 49 { XFER_UDMA_1, 0x41, 0x01 }, 50 { XFER_UDMA_0, 0x41, 0x01 }, 51 52 { XFER_MW_DMA_2, 0x41, 0x00 }, 53 { XFER_MW_DMA_1, 0x42, 0x00 }, 54 { XFER_MW_DMA_0, 0x7a, 0x00 }, 55 { XFER_PIO_4, 0x41, 0x00 }, 56 { XFER_PIO_3, 0x43, 0x00 }, 57 { XFER_PIO_2, 0x78, 0x00 }, 58 { XFER_PIO_1, 0x7a, 0x00 }, 59 { XFER_PIO_0, 0x70, 0x00 }, 60 { 0, 0x00, 0x00 } 61}; 62 63/* 64 * TO DO: active tuning and correction of cards without a bios. 65 */ 66static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table) 67{ 68 for ( ; chipset_table->xfer_speed ; chipset_table++) 69 if (chipset_table->xfer_speed == speed) { 70 return chipset_table->chipset_settings; 71 } 72 return chipset_table->chipset_settings; 73} 74 75static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table) 76{ 77 for ( ; chipset_table->xfer_speed ; chipset_table++) 78 if (chipset_table->xfer_speed == speed) { 79 return chipset_table->ultra_settings; 80 } 81 return chipset_table->ultra_settings; 82} 83 84static void aec6210_set_mode(ide_drive_t *drive, const u8 speed) 85{ 86 ide_hwif_t *hwif = drive->hwif; 87 struct pci_dev *dev = to_pci_dev(hwif->dev); 88 struct ide_host *host = pci_get_drvdata(dev); 89 struct chipset_bus_clock_list_entry *bus_clock = host->host_priv; 90 u16 d_conf = 0; 91 u8 ultra = 0, ultra_conf = 0; 92 u8 tmp0 = 0, tmp1 = 0, tmp2 = 0; 93 unsigned long flags; 94 95 local_irq_save(flags); 96 /* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */ 97 pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf); 98 tmp0 = pci_bus_clock_list(speed, bus_clock); 99 d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf); 100 pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf); 101 102 tmp1 = 0x00; 103 tmp2 = 0x00; 104 pci_read_config_byte(dev, 0x54, &ultra); 105 tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn)))); 106 ultra_conf = pci_bus_clock_list_ultra(speed, bus_clock); 107 tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn)))); 108 pci_write_config_byte(dev, 0x54, tmp2); 109 local_irq_restore(flags); 110} 111 112static void aec6260_set_mode(ide_drive_t *drive, const u8 speed) 113{ 114 ide_hwif_t *hwif = drive->hwif; 115 struct pci_dev *dev = to_pci_dev(hwif->dev); 116 struct ide_host *host = pci_get_drvdata(dev); 117 struct chipset_bus_clock_list_entry *bus_clock = host->host_priv; 118 u8 unit = drive->dn & 1; 119 u8 tmp1 = 0, tmp2 = 0; 120 u8 ultra = 0, drive_conf = 0, ultra_conf = 0; 121 unsigned long flags; 122 123 local_irq_save(flags); 124 /* high 4-bits: Active, low 4-bits: Recovery */ 125 pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf); 126 drive_conf = pci_bus_clock_list(speed, bus_clock); 127 pci_write_config_byte(dev, 0x40|drive->dn, drive_conf); 128 129 pci_read_config_byte(dev, (0x44|hwif->channel), &ultra); 130 tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit)))); 131 ultra_conf = pci_bus_clock_list_ultra(speed, bus_clock); 132 tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit)))); 133 pci_write_config_byte(dev, (0x44|hwif->channel), tmp2); 134 local_irq_restore(flags); 135} 136 137static void aec_set_pio_mode(ide_drive_t *drive, const u8 pio) 138{ 139 drive->hwif->port_ops->set_dma_mode(drive, pio + XFER_PIO_0); 140} 141 142static unsigned int init_chipset_aec62xx(struct pci_dev *dev) 143{ 144 /* These are necessary to get AEC6280 Macintosh cards to work */ 145 if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) || 146 (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) { 147 u8 reg49h = 0, reg4ah = 0; 148 /* Clear reset and test bits. */ 149 pci_read_config_byte(dev, 0x49, ®49h); 150 pci_write_config_byte(dev, 0x49, reg49h & ~0x30); 151 /* Enable chip interrupt output. */ 152 pci_read_config_byte(dev, 0x4a, ®4ah); 153 pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01); 154 /* Enable burst mode. */ 155 pci_read_config_byte(dev, 0x4a, ®4ah); 156 pci_write_config_byte(dev, 0x4a, reg4ah | 0x80); 157 } 158 159 return dev->irq; 160} 161 162static u8 atp86x_cable_detect(ide_hwif_t *hwif) 163{ 164 struct pci_dev *dev = to_pci_dev(hwif->dev); 165 u8 ata66 = 0, mask = hwif->channel ? 0x02 : 0x01; 166 167 pci_read_config_byte(dev, 0x49, &ata66); 168 169 return (ata66 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80; 170} 171 172static const struct ide_port_ops atp850_port_ops = { 173 .set_pio_mode = aec_set_pio_mode, 174 .set_dma_mode = aec6210_set_mode, 175}; 176 177static const struct ide_port_ops atp86x_port_ops = { 178 .set_pio_mode = aec_set_pio_mode, 179 .set_dma_mode = aec6260_set_mode, 180 .cable_detect = atp86x_cable_detect, 181}; 182 183static const struct ide_port_info aec62xx_chipsets[] __devinitdata = { 184 { /* 0: AEC6210 */ 185 .name = DRV_NAME, 186 .init_chipset = init_chipset_aec62xx, 187 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, 188 .port_ops = &atp850_port_ops, 189 .host_flags = IDE_HFLAG_SERIALIZE | 190 IDE_HFLAG_NO_ATAPI_DMA | 191 IDE_HFLAG_NO_DSC | 192 IDE_HFLAG_OFF_BOARD, 193 .pio_mask = ATA_PIO4, 194 .mwdma_mask = ATA_MWDMA2, 195 .udma_mask = ATA_UDMA2, 196 }, 197 { /* 1: AEC6260 */ 198 .name = DRV_NAME, 199 .init_chipset = init_chipset_aec62xx, 200 .port_ops = &atp86x_port_ops, 201 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_NO_AUTODMA | 202 IDE_HFLAG_OFF_BOARD, 203 .pio_mask = ATA_PIO4, 204 .mwdma_mask = ATA_MWDMA2, 205 .udma_mask = ATA_UDMA4, 206 }, 207 { /* 2: AEC6260R */ 208 .name = DRV_NAME, 209 .init_chipset = init_chipset_aec62xx, 210 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, 211 .port_ops = &atp86x_port_ops, 212 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | 213 IDE_HFLAG_NON_BOOTABLE, 214 .pio_mask = ATA_PIO4, 215 .mwdma_mask = ATA_MWDMA2, 216 .udma_mask = ATA_UDMA4, 217 }, 218 { /* 3: AEC6280 */ 219 .name = DRV_NAME, 220 .init_chipset = init_chipset_aec62xx, 221 .port_ops = &atp86x_port_ops, 222 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | 223 IDE_HFLAG_OFF_BOARD, 224 .pio_mask = ATA_PIO4, 225 .mwdma_mask = ATA_MWDMA2, 226 .udma_mask = ATA_UDMA5, 227 }, 228 { /* 4: AEC6280R */ 229 .name = DRV_NAME, 230 .init_chipset = init_chipset_aec62xx, 231 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, 232 .port_ops = &atp86x_port_ops, 233 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | 234 IDE_HFLAG_OFF_BOARD, 235 .pio_mask = ATA_PIO4, 236 .mwdma_mask = ATA_MWDMA2, 237 .udma_mask = ATA_UDMA5, 238 } 239}; 240 241/** 242 * aec62xx_init_one - called when a AEC is found 243 * @dev: the aec62xx device 244 * @id: the matching pci id 245 * 246 * Called when the PCI registration layer (or the IDE initialization) 247 * finds a device matching our IDE device tables. 248 * 249 * NOTE: since we're going to modify the 'name' field for AEC-6[26]80[R] 250 * chips, pass a local copy of 'struct ide_port_info' down the call chain. 251 */ 252 253static int __devinit aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id) 254{ 255 const struct chipset_bus_clock_list_entry *bus_clock; 256 struct ide_port_info d; 257 u8 idx = id->driver_data; 258 int bus_speed = ide_pci_clk ? ide_pci_clk : 33; 259 int err; 260 261 if (bus_speed <= 33) 262 bus_clock = aec6xxx_33_base; 263 else 264 bus_clock = aec6xxx_34_base; 265 266 err = pci_enable_device(dev); 267 if (err) 268 return err; 269 270 d = aec62xx_chipsets[idx]; 271 272 if (idx == 3 || idx == 4) { 273 unsigned long dma_base = pci_resource_start(dev, 4); 274 275 if (inb(dma_base + 2) & 0x10) { 276 printk(KERN_INFO DRV_NAME " %s: AEC6880%s card detected" 277 "\n", pci_name(dev), (idx == 4) ? "R" : ""); 278 d.udma_mask = ATA_UDMA6; 279 } 280 } 281 282 err = ide_pci_init_one(dev, &d, (void *)bus_clock); 283 if (err) 284 pci_disable_device(dev); 285 286 return err; 287} 288 289static void __devexit aec62xx_remove(struct pci_dev *dev) 290{ 291 ide_pci_remove(dev); 292 pci_disable_device(dev); 293} 294 295static const struct pci_device_id aec62xx_pci_tbl[] = { 296 { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF), 0 }, 297 { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860), 1 }, 298 { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R), 2 }, 299 { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865), 3 }, 300 { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R), 4 }, 301 { 0, }, 302}; 303MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl); 304 305static struct pci_driver aec62xx_pci_driver = { 306 .name = "AEC62xx_IDE", 307 .id_table = aec62xx_pci_tbl, 308 .probe = aec62xx_init_one, 309 .remove = __devexit_p(aec62xx_remove), 310 .suspend = ide_pci_suspend, 311 .resume = ide_pci_resume, 312}; 313 314static int __init aec62xx_ide_init(void) 315{ 316 return ide_pci_register_driver(&aec62xx_pci_driver); 317} 318 319static void __exit aec62xx_ide_exit(void) 320{ 321 pci_unregister_driver(&aec62xx_pci_driver); 322} 323 324module_init(aec62xx_ide_init); 325module_exit(aec62xx_ide_exit); 326 327MODULE_AUTHOR("Andre Hedrick"); 328MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE"); 329MODULE_LICENSE("GPL"); 330