au1xxx-ide.c revision b1681c56f5b6bf551bed2617a395855055836571
1/* 2 * BRIEF MODULE DESCRIPTION 3 * AMD Alchemy Au1xxx IDE interface routines over the Static Bus 4 * 5 * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions 6 * 7 * This program is free software; you can redistribute it and/or modify it under 8 * the terms of the GNU General Public License as published by the Free Software 9 * Foundation; either version 2 of the License, or (at your option) any later 10 * version. 11 * 12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 13 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND 14 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR 15 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 16 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 17 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 18 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 19 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 20 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 21 * POSSIBILITY OF SUCH DAMAGE. 22 * 23 * You should have received a copy of the GNU General Public License along with 24 * this program; if not, write to the Free Software Foundation, Inc., 25 * 675 Mass Ave, Cambridge, MA 02139, USA. 26 * 27 * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE 28 * Interface and Linux Device Driver" Application Note. 29 */ 30#include <linux/types.h> 31#include <linux/module.h> 32#include <linux/kernel.h> 33#include <linux/delay.h> 34#include <linux/platform_device.h> 35#include <linux/init.h> 36#include <linux/ide.h> 37#include <linux/scatterlist.h> 38 39#include <asm/mach-au1x00/au1xxx.h> 40#include <asm/mach-au1x00/au1xxx_dbdma.h> 41#include <asm/mach-au1x00/au1xxx_ide.h> 42 43#define DRV_NAME "au1200-ide" 44#define DRV_AUTHOR "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>" 45 46/* enable the burstmode in the dbdma */ 47#define IDE_AU1XXX_BURSTMODE 1 48 49static _auide_hwif auide_hwif; 50 51#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA) 52 53static inline void auide_insw(unsigned long port, void *addr, u32 count) 54{ 55 _auide_hwif *ahwif = &auide_hwif; 56 chan_tab_t *ctp; 57 au1x_ddma_desc_t *dp; 58 59 if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1, 60 DDMA_FLAGS_NOIE)) { 61 printk(KERN_ERR "%s failed %d\n", __func__, __LINE__); 62 return; 63 } 64 ctp = *((chan_tab_t **)ahwif->rx_chan); 65 dp = ctp->cur_ptr; 66 while (dp->dscr_cmd0 & DSCR_CMD0_V) 67 ; 68 ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp); 69} 70 71static inline void auide_outsw(unsigned long port, void *addr, u32 count) 72{ 73 _auide_hwif *ahwif = &auide_hwif; 74 chan_tab_t *ctp; 75 au1x_ddma_desc_t *dp; 76 77 if(!put_source_flags(ahwif->tx_chan, (void*)addr, 78 count << 1, DDMA_FLAGS_NOIE)) { 79 printk(KERN_ERR "%s failed %d\n", __func__, __LINE__); 80 return; 81 } 82 ctp = *((chan_tab_t **)ahwif->tx_chan); 83 dp = ctp->cur_ptr; 84 while (dp->dscr_cmd0 & DSCR_CMD0_V) 85 ; 86 ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp); 87} 88 89static void au1xxx_input_data(ide_drive_t *drive, struct ide_cmd *cmd, 90 void *buf, unsigned int len) 91{ 92 auide_insw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2); 93} 94 95static void au1xxx_output_data(ide_drive_t *drive, struct ide_cmd *cmd, 96 void *buf, unsigned int len) 97{ 98 auide_outsw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2); 99} 100#endif 101 102static void au1xxx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) 103{ 104 int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2); 105 106 switch (drive->pio_mode - XFER_PIO_0) { 107 case 0: 108 mem_sttime = SBC_IDE_TIMING(PIO0); 109 110 /* set configuration for RCS2# */ 111 mem_stcfg |= TS_MASK; 112 mem_stcfg &= ~TCSOE_MASK; 113 mem_stcfg &= ~TOECS_MASK; 114 mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS; 115 break; 116 117 case 1: 118 mem_sttime = SBC_IDE_TIMING(PIO1); 119 120 /* set configuration for RCS2# */ 121 mem_stcfg |= TS_MASK; 122 mem_stcfg &= ~TCSOE_MASK; 123 mem_stcfg &= ~TOECS_MASK; 124 mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS; 125 break; 126 127 case 2: 128 mem_sttime = SBC_IDE_TIMING(PIO2); 129 130 /* set configuration for RCS2# */ 131 mem_stcfg &= ~TS_MASK; 132 mem_stcfg &= ~TCSOE_MASK; 133 mem_stcfg &= ~TOECS_MASK; 134 mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS; 135 break; 136 137 case 3: 138 mem_sttime = SBC_IDE_TIMING(PIO3); 139 140 /* set configuration for RCS2# */ 141 mem_stcfg &= ~TS_MASK; 142 mem_stcfg &= ~TCSOE_MASK; 143 mem_stcfg &= ~TOECS_MASK; 144 mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS; 145 146 break; 147 148 case 4: 149 mem_sttime = SBC_IDE_TIMING(PIO4); 150 151 /* set configuration for RCS2# */ 152 mem_stcfg &= ~TS_MASK; 153 mem_stcfg &= ~TCSOE_MASK; 154 mem_stcfg &= ~TOECS_MASK; 155 mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS; 156 break; 157 } 158 159 au_writel(mem_sttime,MEM_STTIME2); 160 au_writel(mem_stcfg,MEM_STCFG2); 161} 162 163static void auide_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) 164{ 165 int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2); 166 167 switch (drive->dma_mode) { 168#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA 169 case XFER_MW_DMA_2: 170 mem_sttime = SBC_IDE_TIMING(MDMA2); 171 172 /* set configuration for RCS2# */ 173 mem_stcfg &= ~TS_MASK; 174 mem_stcfg &= ~TCSOE_MASK; 175 mem_stcfg &= ~TOECS_MASK; 176 mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS; 177 178 break; 179 case XFER_MW_DMA_1: 180 mem_sttime = SBC_IDE_TIMING(MDMA1); 181 182 /* set configuration for RCS2# */ 183 mem_stcfg &= ~TS_MASK; 184 mem_stcfg &= ~TCSOE_MASK; 185 mem_stcfg &= ~TOECS_MASK; 186 mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS; 187 188 break; 189 case XFER_MW_DMA_0: 190 mem_sttime = SBC_IDE_TIMING(MDMA0); 191 192 /* set configuration for RCS2# */ 193 mem_stcfg |= TS_MASK; 194 mem_stcfg &= ~TCSOE_MASK; 195 mem_stcfg &= ~TOECS_MASK; 196 mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS; 197 198 break; 199#endif 200 } 201 202 au_writel(mem_sttime,MEM_STTIME2); 203 au_writel(mem_stcfg,MEM_STCFG2); 204} 205 206/* 207 * Multi-Word DMA + DbDMA functions 208 */ 209 210#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA 211static int auide_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd) 212{ 213 ide_hwif_t *hwif = drive->hwif; 214 _auide_hwif *ahwif = &auide_hwif; 215 struct scatterlist *sg; 216 int i = cmd->sg_nents, count = 0; 217 int iswrite = !!(cmd->tf_flags & IDE_TFLAG_WRITE); 218 219 /* Save for interrupt context */ 220 ahwif->drive = drive; 221 222 /* fill the descriptors */ 223 sg = hwif->sg_table; 224 while (i && sg_dma_len(sg)) { 225 u32 cur_addr; 226 u32 cur_len; 227 228 cur_addr = sg_dma_address(sg); 229 cur_len = sg_dma_len(sg); 230 231 while (cur_len) { 232 u32 flags = DDMA_FLAGS_NOIE; 233 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00; 234 235 if (++count >= PRD_ENTRIES) { 236 printk(KERN_WARNING "%s: DMA table too small\n", 237 drive->name); 238 return 0; 239 } 240 241 /* Lets enable intr for the last descriptor only */ 242 if (1==i) 243 flags = DDMA_FLAGS_IE; 244 else 245 flags = DDMA_FLAGS_NOIE; 246 247 if (iswrite) { 248 if(!put_source_flags(ahwif->tx_chan, 249 (void*) sg_virt(sg), 250 tc, flags)) { 251 printk(KERN_ERR "%s failed %d\n", 252 __func__, __LINE__); 253 } 254 } else 255 { 256 if(!put_dest_flags(ahwif->rx_chan, 257 (void*) sg_virt(sg), 258 tc, flags)) { 259 printk(KERN_ERR "%s failed %d\n", 260 __func__, __LINE__); 261 } 262 } 263 264 cur_addr += tc; 265 cur_len -= tc; 266 } 267 sg = sg_next(sg); 268 i--; 269 } 270 271 if (count) 272 return 1; 273 274 return 0; /* revert to PIO for this request */ 275} 276 277static int auide_dma_end(ide_drive_t *drive) 278{ 279 return 0; 280} 281 282static void auide_dma_start(ide_drive_t *drive ) 283{ 284} 285 286 287static int auide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd) 288{ 289 if (auide_build_dmatable(drive, cmd) == 0) 290 return 1; 291 292 return 0; 293} 294 295static int auide_dma_test_irq(ide_drive_t *drive) 296{ 297 /* If dbdma didn't execute the STOP command yet, the 298 * active bit is still set 299 */ 300 drive->waiting_for_dma++; 301 if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) { 302 printk(KERN_WARNING "%s: timeout waiting for ddma to complete\n", 303 drive->name); 304 return 1; 305 } 306 udelay(10); 307 return 0; 308} 309 310static void auide_dma_host_set(ide_drive_t *drive, int on) 311{ 312} 313 314static void auide_ddma_tx_callback(int irq, void *param) 315{ 316} 317 318static void auide_ddma_rx_callback(int irq, void *param) 319{ 320} 321#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */ 322 323static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags) 324{ 325 dev->dev_id = dev_id; 326 dev->dev_physaddr = (u32)IDE_PHYS_ADDR; 327 dev->dev_intlevel = 0; 328 dev->dev_intpolarity = 0; 329 dev->dev_tsize = tsize; 330 dev->dev_devwidth = devwidth; 331 dev->dev_flags = flags; 332} 333 334#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA 335static const struct ide_dma_ops au1xxx_dma_ops = { 336 .dma_host_set = auide_dma_host_set, 337 .dma_setup = auide_dma_setup, 338 .dma_start = auide_dma_start, 339 .dma_end = auide_dma_end, 340 .dma_test_irq = auide_dma_test_irq, 341 .dma_lost_irq = ide_dma_lost_irq, 342}; 343 344static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d) 345{ 346 _auide_hwif *auide = &auide_hwif; 347 dbdev_tab_t source_dev_tab, target_dev_tab; 348 u32 dev_id, tsize, devwidth, flags; 349 350 dev_id = IDE_DDMA_REQ; 351 352 tsize = 8; /* 1 */ 353 devwidth = 32; /* 16 */ 354 355#ifdef IDE_AU1XXX_BURSTMODE 356 flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE; 357#else 358 flags = DEV_FLAGS_SYNC; 359#endif 360 361 /* setup dev_tab for tx channel */ 362 auide_init_dbdma_dev( &source_dev_tab, 363 dev_id, 364 tsize, devwidth, DEV_FLAGS_OUT | flags); 365 auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); 366 367 auide_init_dbdma_dev( &source_dev_tab, 368 dev_id, 369 tsize, devwidth, DEV_FLAGS_IN | flags); 370 auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); 371 372 /* We also need to add a target device for the DMA */ 373 auide_init_dbdma_dev( &target_dev_tab, 374 (u32)DSCR_CMD0_ALWAYS, 375 tsize, devwidth, DEV_FLAGS_ANYUSE); 376 auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab); 377 378 /* Get a channel for TX */ 379 auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id, 380 auide->tx_dev_id, 381 auide_ddma_tx_callback, 382 (void*)auide); 383 384 /* Get a channel for RX */ 385 auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id, 386 auide->target_dev_id, 387 auide_ddma_rx_callback, 388 (void*)auide); 389 390 auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan, 391 NUM_DESCRIPTORS); 392 auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan, 393 NUM_DESCRIPTORS); 394 395 /* FIXME: check return value */ 396 (void)ide_allocate_dma_engine(hwif); 397 398 au1xxx_dbdma_start( auide->tx_chan ); 399 au1xxx_dbdma_start( auide->rx_chan ); 400 401 return 0; 402} 403#else 404static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d) 405{ 406 _auide_hwif *auide = &auide_hwif; 407 dbdev_tab_t source_dev_tab; 408 int flags; 409 410#ifdef IDE_AU1XXX_BURSTMODE 411 flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE; 412#else 413 flags = DEV_FLAGS_SYNC; 414#endif 415 416 /* setup dev_tab for tx channel */ 417 auide_init_dbdma_dev( &source_dev_tab, 418 (u32)DSCR_CMD0_ALWAYS, 419 8, 32, DEV_FLAGS_OUT | flags); 420 auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); 421 422 auide_init_dbdma_dev( &source_dev_tab, 423 (u32)DSCR_CMD0_ALWAYS, 424 8, 32, DEV_FLAGS_IN | flags); 425 auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); 426 427 /* Get a channel for TX */ 428 auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS, 429 auide->tx_dev_id, 430 NULL, 431 (void*)auide); 432 433 /* Get a channel for RX */ 434 auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id, 435 DSCR_CMD0_ALWAYS, 436 NULL, 437 (void*)auide); 438 439 auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan, 440 NUM_DESCRIPTORS); 441 auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan, 442 NUM_DESCRIPTORS); 443 444 au1xxx_dbdma_start( auide->tx_chan ); 445 au1xxx_dbdma_start( auide->rx_chan ); 446 447 return 0; 448} 449#endif 450 451static void auide_setup_ports(struct ide_hw *hw, _auide_hwif *ahwif) 452{ 453 int i; 454 unsigned long *ata_regs = hw->io_ports_array; 455 456 /* FIXME? */ 457 for (i = 0; i < 8; i++) 458 *ata_regs++ = ahwif->regbase + (i << IDE_REG_SHIFT); 459 460 /* set the Alternative Status register */ 461 *ata_regs = ahwif->regbase + (14 << IDE_REG_SHIFT); 462} 463 464#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA 465static const struct ide_tp_ops au1xxx_tp_ops = { 466 .exec_command = ide_exec_command, 467 .read_status = ide_read_status, 468 .read_altstatus = ide_read_altstatus, 469 .write_devctl = ide_write_devctl, 470 471 .dev_select = ide_dev_select, 472 .tf_load = ide_tf_load, 473 .tf_read = ide_tf_read, 474 475 .input_data = au1xxx_input_data, 476 .output_data = au1xxx_output_data, 477}; 478#endif 479 480static const struct ide_port_ops au1xxx_port_ops = { 481 .set_pio_mode = au1xxx_set_pio_mode, 482 .set_dma_mode = auide_set_dma_mode, 483}; 484 485static const struct ide_port_info au1xxx_port_info = { 486 .init_dma = auide_ddma_init, 487#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA 488 .tp_ops = &au1xxx_tp_ops, 489#endif 490 .port_ops = &au1xxx_port_ops, 491#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA 492 .dma_ops = &au1xxx_dma_ops, 493#endif 494 .host_flags = IDE_HFLAG_POST_SET_MODE | 495 IDE_HFLAG_NO_IO_32BIT | 496 IDE_HFLAG_UNMASK_IRQS, 497 .pio_mask = ATA_PIO4, 498#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA 499 .mwdma_mask = ATA_MWDMA2, 500#endif 501 .chipset = ide_au1xxx, 502}; 503 504static int au_ide_probe(struct platform_device *dev) 505{ 506 _auide_hwif *ahwif = &auide_hwif; 507 struct resource *res; 508 struct ide_host *host; 509 int ret = 0; 510 struct ide_hw hw, *hws[] = { &hw }; 511 512#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA) 513 char *mode = "MWDMA2"; 514#elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA) 515 char *mode = "PIO+DDMA(offload)"; 516#endif 517 518 memset(&auide_hwif, 0, sizeof(_auide_hwif)); 519 ahwif->irq = platform_get_irq(dev, 0); 520 521 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 522 523 if (res == NULL) { 524 pr_debug("%s %d: no base address\n", DRV_NAME, dev->id); 525 ret = -ENODEV; 526 goto out; 527 } 528 if (ahwif->irq < 0) { 529 pr_debug("%s %d: no IRQ\n", DRV_NAME, dev->id); 530 ret = -ENODEV; 531 goto out; 532 } 533 534 if (!request_mem_region(res->start, resource_size(res), dev->name)) { 535 pr_debug("%s: request_mem_region failed\n", DRV_NAME); 536 ret = -EBUSY; 537 goto out; 538 } 539 540 ahwif->regbase = (u32)ioremap(res->start, resource_size(res)); 541 if (ahwif->regbase == 0) { 542 ret = -ENOMEM; 543 goto out; 544 } 545 546 memset(&hw, 0, sizeof(hw)); 547 auide_setup_ports(&hw, ahwif); 548 hw.irq = ahwif->irq; 549 hw.dev = &dev->dev; 550 551 ret = ide_host_add(&au1xxx_port_info, hws, 1, &host); 552 if (ret) 553 goto out; 554 555 auide_hwif.hwif = host->ports[0]; 556 557 platform_set_drvdata(dev, host); 558 559 printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode ); 560 561 out: 562 return ret; 563} 564 565static int au_ide_remove(struct platform_device *dev) 566{ 567 struct resource *res; 568 struct ide_host *host = platform_get_drvdata(dev); 569 _auide_hwif *ahwif = &auide_hwif; 570 571 ide_host_remove(host); 572 573 iounmap((void *)ahwif->regbase); 574 575 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 576 release_mem_region(res->start, resource_size(res)); 577 578 return 0; 579} 580 581static struct platform_driver au1200_ide_driver = { 582 .driver = { 583 .name = "au1200-ide", 584 .owner = THIS_MODULE, 585 }, 586 .probe = au_ide_probe, 587 .remove = au_ide_remove, 588}; 589 590static int __init au_ide_init(void) 591{ 592 return platform_driver_register(&au1200_ide_driver); 593} 594 595static void __exit au_ide_exit(void) 596{ 597 platform_driver_unregister(&au1200_ide_driver); 598} 599 600MODULE_LICENSE("GPL"); 601MODULE_DESCRIPTION("AU1200 IDE driver"); 602 603module_init(au_ide_init); 604module_exit(au_ide_exit); 605