cmd64x.c revision 628df2f33d99dace08838779d8a02bf1deaff100
1/* 2 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines. 3 * Due to massive hardware bugs, UltraDMA is only supported 4 * on the 646U2 and not on the 646U. 5 * 6 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) 7 * Copyright (C) 1998 David S. Miller (davem@redhat.com) 8 * 9 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> 10 * Copyright (C) 2007,2009 MontaVista Software, Inc. <source@mvista.com> 11 */ 12 13#include <linux/module.h> 14#include <linux/types.h> 15#include <linux/pci.h> 16#include <linux/ide.h> 17#include <linux/init.h> 18 19#include <asm/io.h> 20 21#define DRV_NAME "cmd64x" 22 23#define CMD_DEBUG 0 24 25#if CMD_DEBUG 26#define cmdprintk(x...) printk(x) 27#else 28#define cmdprintk(x...) 29#endif 30 31/* 32 * CMD64x specific registers definition. 33 */ 34#define CFR 0x50 35#define CFR_INTR_CH0 0x04 36 37#define CMDTIM 0x52 38#define ARTTIM0 0x53 39#define DRWTIM0 0x54 40#define ARTTIM1 0x55 41#define DRWTIM1 0x56 42#define ARTTIM23 0x57 43#define ARTTIM23_DIS_RA2 0x04 44#define ARTTIM23_DIS_RA3 0x08 45#define ARTTIM23_INTR_CH1 0x10 46#define DRWTIM2 0x58 47#define BRST 0x59 48#define DRWTIM3 0x5b 49 50#define BMIDECR0 0x70 51#define MRDMODE 0x71 52#define MRDMODE_INTR_CH0 0x04 53#define MRDMODE_INTR_CH1 0x08 54#define UDIDETCR0 0x73 55#define DTPR0 0x74 56#define BMIDECR1 0x78 57#define BMIDECSR 0x79 58#define UDIDETCR1 0x7B 59#define DTPR1 0x7C 60 61static u8 quantize_timing(int timing, int quant) 62{ 63 return (timing + quant - 1) / quant; 64} 65 66/* 67 * This routine calculates active/recovery counts and then writes them into 68 * the chipset registers. 69 */ 70static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time) 71{ 72 struct pci_dev *dev = to_pci_dev(drive->hwif->dev); 73 int clock_time = 1000 / (ide_pci_clk ? ide_pci_clk : 33); 74 u8 cycle_count, active_count, recovery_count, drwtim; 75 static const u8 recovery_values[] = 76 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0}; 77 static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3}; 78 79 cmdprintk("program_cycle_times parameters: total=%d, active=%d\n", 80 cycle_time, active_time); 81 82 cycle_count = quantize_timing( cycle_time, clock_time); 83 active_count = quantize_timing(active_time, clock_time); 84 recovery_count = cycle_count - active_count; 85 86 /* 87 * In case we've got too long recovery phase, try to lengthen 88 * the active phase 89 */ 90 if (recovery_count > 16) { 91 active_count += recovery_count - 16; 92 recovery_count = 16; 93 } 94 if (active_count > 16) /* shouldn't actually happen... */ 95 active_count = 16; 96 97 cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n", 98 cycle_count, active_count, recovery_count); 99 100 /* 101 * Convert values to internal chipset representation 102 */ 103 recovery_count = recovery_values[recovery_count]; 104 active_count &= 0x0f; 105 106 /* Program the active/recovery counts into the DRWTIM register */ 107 drwtim = (active_count << 4) | recovery_count; 108 (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim); 109 cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]); 110} 111 112/* 113 * This routine writes into the chipset registers 114 * PIO setup/active/recovery timings. 115 */ 116static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio) 117{ 118 ide_hwif_t *hwif = drive->hwif; 119 struct pci_dev *dev = to_pci_dev(hwif->dev); 120 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio); 121 unsigned int cycle_time; 122 u8 setup_count, arttim = 0; 123 124 static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0}; 125 static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23}; 126 127 cycle_time = ide_pio_cycle_time(drive, pio); 128 129 program_cycle_times(drive, cycle_time, t->active); 130 131 setup_count = quantize_timing(t->setup, 132 1000 / (ide_pci_clk ? ide_pci_clk : 33)); 133 134 /* 135 * The primary channel has individual address setup timing registers 136 * for each drive and the hardware selects the slowest timing itself. 137 * The secondary channel has one common register and we have to select 138 * the slowest address setup timing ourselves. 139 */ 140 if (hwif->channel) { 141 ide_drive_t *pair = ide_get_pair_dev(drive); 142 143 drive->drive_data = setup_count; 144 145 if (pair) 146 setup_count = max_t(u8, setup_count, pair->drive_data); 147 } 148 149 if (setup_count > 5) /* shouldn't actually happen... */ 150 setup_count = 5; 151 cmdprintk("Final address setup count: %d\n", setup_count); 152 153 /* 154 * Program the address setup clocks into the ARTTIM registers. 155 * Avoid clearing the secondary channel's interrupt bit. 156 */ 157 (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim); 158 if (hwif->channel) 159 arttim &= ~ARTTIM23_INTR_CH1; 160 arttim &= ~0xc0; 161 arttim |= setup_values[setup_count]; 162 (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim); 163 cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]); 164} 165 166/* 167 * Attempts to set drive's PIO mode. 168 * Special cases are 8: prefetch off, 9: prefetch on (both never worked) 169 */ 170 171static void cmd64x_set_pio_mode(ide_drive_t *drive, const u8 pio) 172{ 173 /* 174 * Filter out the prefetch control values 175 * to prevent PIO5 from being programmed 176 */ 177 if (pio == 8 || pio == 9) 178 return; 179 180 cmd64x_tune_pio(drive, pio); 181} 182 183static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed) 184{ 185 ide_hwif_t *hwif = drive->hwif; 186 struct pci_dev *dev = to_pci_dev(hwif->dev); 187 u8 unit = drive->dn & 0x01; 188 u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0; 189 190 if (speed >= XFER_SW_DMA_0) { 191 (void) pci_read_config_byte(dev, pciU, ®U); 192 regU &= ~(unit ? 0xCA : 0x35); 193 } 194 195 switch(speed) { 196 case XFER_UDMA_5: 197 regU |= unit ? 0x0A : 0x05; 198 break; 199 case XFER_UDMA_4: 200 regU |= unit ? 0x4A : 0x15; 201 break; 202 case XFER_UDMA_3: 203 regU |= unit ? 0x8A : 0x25; 204 break; 205 case XFER_UDMA_2: 206 regU |= unit ? 0x42 : 0x11; 207 break; 208 case XFER_UDMA_1: 209 regU |= unit ? 0x82 : 0x21; 210 break; 211 case XFER_UDMA_0: 212 regU |= unit ? 0xC2 : 0x31; 213 break; 214 case XFER_MW_DMA_2: 215 program_cycle_times(drive, 120, 70); 216 break; 217 case XFER_MW_DMA_1: 218 program_cycle_times(drive, 150, 80); 219 break; 220 case XFER_MW_DMA_0: 221 program_cycle_times(drive, 480, 215); 222 break; 223 } 224 225 if (speed >= XFER_SW_DMA_0) 226 (void) pci_write_config_byte(dev, pciU, regU); 227} 228 229static void cmd648_clear_irq(ide_drive_t *drive) 230{ 231 ide_hwif_t *hwif = drive->hwif; 232 struct pci_dev *dev = to_pci_dev(hwif->dev); 233 unsigned long base = pci_resource_start(dev, 4); 234 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 : 235 MRDMODE_INTR_CH0; 236 u8 mrdmode = inb(base + 1); 237 238 /* clear the interrupt bit */ 239 outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask, 240 base + 1); 241} 242 243static void cmd64x_clear_irq(ide_drive_t *drive) 244{ 245 ide_hwif_t *hwif = drive->hwif; 246 struct pci_dev *dev = to_pci_dev(hwif->dev); 247 int irq_reg = hwif->channel ? ARTTIM23 : CFR; 248 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 : 249 CFR_INTR_CH0; 250 u8 irq_stat = 0; 251 252 (void) pci_read_config_byte(dev, irq_reg, &irq_stat); 253 /* clear the interrupt bit */ 254 (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask); 255} 256 257static int cmd648_test_irq(ide_hwif_t *hwif) 258{ 259 struct pci_dev *dev = to_pci_dev(hwif->dev); 260 unsigned long base = pci_resource_start(dev, 4); 261 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 : 262 MRDMODE_INTR_CH0; 263 u8 mrdmode = inb(base + 1); 264 265 pr_debug("%s: mrdmode: 0x%02x irq_mask: 0x%02x\n", 266 hwif->name, mrdmode, irq_mask); 267 268 return (mrdmode & irq_mask) ? 1 : 0; 269} 270 271static int cmd64x_test_irq(ide_hwif_t *hwif) 272{ 273 struct pci_dev *dev = to_pci_dev(hwif->dev); 274 int irq_reg = hwif->channel ? ARTTIM23 : CFR; 275 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 : 276 CFR_INTR_CH0; 277 u8 irq_stat = 0; 278 279 (void) pci_read_config_byte(dev, irq_reg, &irq_stat); 280 281 pr_debug("%s: irq_stat: 0x%02x irq_mask: 0x%02x\n", 282 hwif->name, irq_stat, irq_mask); 283 284 return (irq_stat & irq_mask) ? 1 : 0; 285} 286 287/* 288 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old 289 * event order for DMA transfers. 290 */ 291 292static int cmd646_1_dma_end(ide_drive_t *drive) 293{ 294 ide_hwif_t *hwif = drive->hwif; 295 u8 dma_stat = 0, dma_cmd = 0; 296 297 /* get DMA status */ 298 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); 299 /* read DMA command state */ 300 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); 301 /* stop DMA */ 302 outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD); 303 /* clear the INTR & ERROR bits */ 304 outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS); 305 /* verify good DMA status */ 306 return (dma_stat & 7) != 4; 307} 308 309static int init_chipset_cmd64x(struct pci_dev *dev) 310{ 311 u8 mrdmode = 0; 312 313 /* Set a good latency timer and cache line size value. */ 314 (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); 315 /* FIXME: pci_set_master() to ensure a good latency timer value */ 316 317 /* 318 * Enable interrupts, select MEMORY READ LINE for reads. 319 * 320 * NOTE: although not mentioned in the PCI0646U specs, 321 * bits 0-1 are write only and won't be read back as 322 * set or not -- PCI0646U2 specs clarify this point. 323 */ 324 (void) pci_read_config_byte (dev, MRDMODE, &mrdmode); 325 mrdmode &= ~0x30; 326 (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02)); 327 328 return 0; 329} 330 331static u8 cmd64x_cable_detect(ide_hwif_t *hwif) 332{ 333 struct pci_dev *dev = to_pci_dev(hwif->dev); 334 u8 bmidecsr = 0, mask = hwif->channel ? 0x02 : 0x01; 335 336 switch (dev->device) { 337 case PCI_DEVICE_ID_CMD_648: 338 case PCI_DEVICE_ID_CMD_649: 339 pci_read_config_byte(dev, BMIDECSR, &bmidecsr); 340 return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; 341 default: 342 return ATA_CBL_PATA40; 343 } 344} 345 346static const struct ide_port_ops cmd64x_port_ops = { 347 .set_pio_mode = cmd64x_set_pio_mode, 348 .set_dma_mode = cmd64x_set_dma_mode, 349 .clear_irq = cmd64x_clear_irq, 350 .test_irq = cmd64x_test_irq, 351 .cable_detect = cmd64x_cable_detect, 352}; 353 354static const struct ide_port_ops cmd648_port_ops = { 355 .set_pio_mode = cmd64x_set_pio_mode, 356 .set_dma_mode = cmd64x_set_dma_mode, 357 .clear_irq = cmd648_clear_irq, 358 .test_irq = cmd648_test_irq, 359 .cable_detect = cmd64x_cable_detect, 360}; 361 362static const struct ide_dma_ops cmd646_rev1_dma_ops = { 363 .dma_host_set = ide_dma_host_set, 364 .dma_setup = ide_dma_setup, 365 .dma_start = ide_dma_start, 366 .dma_end = cmd646_1_dma_end, 367 .dma_test_irq = ide_dma_test_irq, 368 .dma_lost_irq = ide_dma_lost_irq, 369 .dma_timer_expiry = ide_dma_sff_timer_expiry, 370 .dma_sff_read_status = ide_dma_sff_read_status, 371}; 372 373static const struct ide_port_info cmd64x_chipsets[] __devinitdata = { 374 { /* 0: CMD643 */ 375 .name = DRV_NAME, 376 .init_chipset = init_chipset_cmd64x, 377 .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}}, 378 .port_ops = &cmd64x_port_ops, 379 .host_flags = IDE_HFLAG_CLEAR_SIMPLEX | 380 IDE_HFLAG_ABUSE_PREFETCH, 381 .pio_mask = ATA_PIO5, 382 .mwdma_mask = ATA_MWDMA2, 383 .udma_mask = 0x00, /* no udma */ 384 }, 385 { /* 1: CMD646 */ 386 .name = DRV_NAME, 387 .init_chipset = init_chipset_cmd64x, 388 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, 389 .port_ops = &cmd648_port_ops, 390 .host_flags = IDE_HFLAG_SERIALIZE | 391 IDE_HFLAG_ABUSE_PREFETCH, 392 .pio_mask = ATA_PIO5, 393 .mwdma_mask = ATA_MWDMA2, 394 .udma_mask = ATA_UDMA2, 395 }, 396 { /* 2: CMD648 */ 397 .name = DRV_NAME, 398 .init_chipset = init_chipset_cmd64x, 399 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, 400 .port_ops = &cmd648_port_ops, 401 .host_flags = IDE_HFLAG_ABUSE_PREFETCH, 402 .pio_mask = ATA_PIO5, 403 .mwdma_mask = ATA_MWDMA2, 404 .udma_mask = ATA_UDMA4, 405 }, 406 { /* 3: CMD649 */ 407 .name = DRV_NAME, 408 .init_chipset = init_chipset_cmd64x, 409 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, 410 .port_ops = &cmd648_port_ops, 411 .host_flags = IDE_HFLAG_ABUSE_PREFETCH, 412 .pio_mask = ATA_PIO5, 413 .mwdma_mask = ATA_MWDMA2, 414 .udma_mask = ATA_UDMA5, 415 } 416}; 417 418static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id) 419{ 420 struct ide_port_info d; 421 u8 idx = id->driver_data; 422 423 d = cmd64x_chipsets[idx]; 424 425 if (idx == 1) { 426 /* 427 * UltraDMA only supported on PCI646U and PCI646U2, which 428 * correspond to revisions 0x03, 0x05 and 0x07 respectively. 429 * Actually, although the CMD tech support people won't 430 * tell me the details, the 0x03 revision cannot support 431 * UDMA correctly without hardware modifications, and even 432 * then it only works with Quantum disks due to some 433 * hold time assumptions in the 646U part which are fixed 434 * in the 646U2. 435 * 436 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets. 437 */ 438 if (dev->revision < 5) { 439 d.udma_mask = 0x00; 440 /* 441 * The original PCI0646 didn't have the primary 442 * channel enable bit, it appeared starting with 443 * PCI0646U (i.e. revision ID 3). 444 */ 445 if (dev->revision < 3) { 446 d.enablebits[0].reg = 0; 447 d.port_ops = &cmd64x_port_ops; 448 if (dev->revision == 1) 449 d.dma_ops = &cmd646_rev1_dma_ops; 450 } 451 } 452 } 453 454 return ide_pci_init_one(dev, &d, NULL); 455} 456 457static const struct pci_device_id cmd64x_pci_tbl[] = { 458 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 }, 459 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 }, 460 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 }, 461 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 }, 462 { 0, }, 463}; 464MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl); 465 466static struct pci_driver cmd64x_pci_driver = { 467 .name = "CMD64x_IDE", 468 .id_table = cmd64x_pci_tbl, 469 .probe = cmd64x_init_one, 470 .remove = ide_pci_remove, 471 .suspend = ide_pci_suspend, 472 .resume = ide_pci_resume, 473}; 474 475static int __init cmd64x_ide_init(void) 476{ 477 return ide_pci_register_driver(&cmd64x_pci_driver); 478} 479 480static void __exit cmd64x_ide_exit(void) 481{ 482 pci_unregister_driver(&cmd64x_pci_driver); 483} 484 485module_init(cmd64x_ide_init); 486module_exit(cmd64x_ide_exit); 487 488MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick"); 489MODULE_DESCRIPTION("PCI driver module for CMD64x IDE"); 490MODULE_LICENSE("GPL"); 491